ctrl_reg          294 arch/arm/kernel/hw_breakpoint.c 	u32 ctrl_reg;
ctrl_reg          303 arch/arm/kernel/hw_breakpoint.c 	ctrl_reg = encode_ctrl_reg(ctrl);
ctrl_reg          306 arch/arm/kernel/hw_breakpoint.c 	write_wb_reg(ARM_BASE_WCR, ctrl_reg);
ctrl_reg          307 arch/arm/kernel/hw_breakpoint.c 	if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
ctrl_reg          687 arch/arm/kernel/hw_breakpoint.c 	u32 val, ctrl_reg, alignment_mask;
ctrl_reg          724 arch/arm/kernel/hw_breakpoint.c 			ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
ctrl_reg          725 arch/arm/kernel/hw_breakpoint.c 			decode_ctrl_reg(ctrl_reg, &ctrl);
ctrl_reg          792 arch/arm/kernel/hw_breakpoint.c 	u32 ctrl_reg, val, addr;
ctrl_reg          819 arch/arm/kernel/hw_breakpoint.c 		ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
ctrl_reg          820 arch/arm/kernel/hw_breakpoint.c 		decode_ctrl_reg(ctrl_reg, &ctrl);
ctrl_reg          228 arch/arm64/kernel/hw_breakpoint.c 	int i, max_slots, ctrl_reg, val_reg, reg_enable;
ctrl_reg          234 arch/arm64/kernel/hw_breakpoint.c 		ctrl_reg = AARCH64_DBG_REG_BCR;
ctrl_reg          241 arch/arm64/kernel/hw_breakpoint.c 		ctrl_reg = AARCH64_DBG_REG_WCR;
ctrl_reg          267 arch/arm64/kernel/hw_breakpoint.c 		write_wb_reg(ctrl_reg, i,
ctrl_reg          272 arch/arm64/kernel/hw_breakpoint.c 		write_wb_reg(ctrl_reg, i, 0);
ctrl_reg          624 arch/arm64/kernel/hw_breakpoint.c 	u32 ctrl_reg;
ctrl_reg          648 arch/arm64/kernel/hw_breakpoint.c 		ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);
ctrl_reg          649 arch/arm64/kernel/hw_breakpoint.c 		decode_ctrl_reg(ctrl_reg, &ctrl);
ctrl_reg          738 arch/arm64/kernel/hw_breakpoint.c 	u32 ctrl_reg;
ctrl_reg          769 arch/arm64/kernel/hw_breakpoint.c 		ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);
ctrl_reg          770 arch/arm64/kernel/hw_breakpoint.c 		decode_ctrl_reg(ctrl_reg, &ctrl);
ctrl_reg          178 arch/powerpc/platforms/52xx/mpc52xx_pic.c 	u32 ctrl_reg, type;
ctrl_reg          194 arch/powerpc/platforms/52xx/mpc52xx_pic.c 	ctrl_reg = in_be32(&intr->ctrl);
ctrl_reg          195 arch/powerpc/platforms/52xx/mpc52xx_pic.c 	ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
ctrl_reg          196 arch/powerpc/platforms/52xx/mpc52xx_pic.c 	ctrl_reg |= (type << (22 - (l2irq * 2)));
ctrl_reg          197 arch/powerpc/platforms/52xx/mpc52xx_pic.c 	out_be32(&intr->ctrl, ctrl_reg);
ctrl_reg           12 arch/x86/kvm/pmu.h #define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)
ctrl_reg         2440 drivers/atm/iphase.c         static u32 ctrl_reg; 
ctrl_reg         2443 drivers/atm/iphase.c 	      ctrl_reg = readl(ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
ctrl_reg         2446 drivers/atm/iphase.c                  ctrl_reg &= (~CTRL_LED);
ctrl_reg         2447 drivers/atm/iphase.c                  writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
ctrl_reg         2452 drivers/atm/iphase.c 		 ctrl_reg |= CTRL_LED;
ctrl_reg         2453 drivers/atm/iphase.c                  writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
ctrl_reg         2509 drivers/atm/iphase.c 	u32 ctrl_reg;  
ctrl_reg         2536 drivers/atm/iphase.c 	ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);  
ctrl_reg         2537 drivers/atm/iphase.c 	ctrl_reg = (ctrl_reg & (CTRL_LED | CTRL_FE_RST))  
ctrl_reg         2552 drivers/atm/iphase.c        writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);   
ctrl_reg         2567 drivers/atm/iphase.c 	ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);  
ctrl_reg         2568 drivers/atm/iphase.c        	writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);   
ctrl_reg           79 drivers/bluetooth/bluecard_cs.c 	unsigned char ctrl_reg;
ctrl_reg          265 drivers/bluetooth/bluecard_cs.c 			info->ctrl_reg |= REG_CONTROL_RTS;
ctrl_reg          266 drivers/bluetooth/bluecard_cs.c 			outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          308 drivers/bluetooth/bluecard_cs.c 			info->ctrl_reg &= ~0x03;
ctrl_reg          309 drivers/bluetooth/bluecard_cs.c 			info->ctrl_reg |= baud_reg;
ctrl_reg          310 drivers/bluetooth/bluecard_cs.c 			outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          313 drivers/bluetooth/bluecard_cs.c 			info->ctrl_reg &= ~REG_CONTROL_RTS;
ctrl_reg          314 drivers/bluetooth/bluecard_cs.c 			outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          513 drivers/bluetooth/bluecard_cs.c 	info->ctrl_reg &= ~REG_CONTROL_INTERRUPT;
ctrl_reg          514 drivers/bluetooth/bluecard_cs.c 	outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          547 drivers/bluetooth/bluecard_cs.c 	info->ctrl_reg |= REG_CONTROL_INTERRUPT;
ctrl_reg          548 drivers/bluetooth/bluecard_cs.c 	outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          728 drivers/bluetooth/bluecard_cs.c 	info->ctrl_reg = REG_CONTROL_BT_RESET | REG_CONTROL_CARD_RESET;
ctrl_reg          729 drivers/bluetooth/bluecard_cs.c 	outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          741 drivers/bluetooth/bluecard_cs.c 	info->ctrl_reg = REG_CONTROL_BT_ON | REG_CONTROL_BT_RES_PU;
ctrl_reg          742 drivers/bluetooth/bluecard_cs.c 	outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          746 drivers/bluetooth/bluecard_cs.c 	info->ctrl_reg |= REG_CONTROL_INTERRUPT;
ctrl_reg          747 drivers/bluetooth/bluecard_cs.c 	outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          751 drivers/bluetooth/bluecard_cs.c 		info->ctrl_reg |= REG_CONTROL_RTS;
ctrl_reg          752 drivers/bluetooth/bluecard_cs.c 		outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          755 drivers/bluetooth/bluecard_cs.c 		info->ctrl_reg |= 0x03;
ctrl_reg          756 drivers/bluetooth/bluecard_cs.c 		outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          759 drivers/bluetooth/bluecard_cs.c 		info->ctrl_reg &= ~REG_CONTROL_RTS;
ctrl_reg          760 drivers/bluetooth/bluecard_cs.c 		outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          808 drivers/bluetooth/bluecard_cs.c 	info->ctrl_reg = REG_CONTROL_BT_RESET | REG_CONTROL_CARD_RESET;
ctrl_reg          809 drivers/bluetooth/bluecard_cs.c 	outb(info->ctrl_reg, iobase + REG_CONTROL);
ctrl_reg          136 drivers/clk/hisilicon/clk-hix5hd2.c 	u32		ctrl_reg;
ctrl_reg          148 drivers/clk/hisilicon/clk-hix5hd2.c 	void __iomem	*ctrl_reg;
ctrl_reg          174 drivers/clk/hisilicon/clk-hix5hd2.c 	val = readl_relaxed(clk->ctrl_reg);
ctrl_reg          176 drivers/clk/hisilicon/clk-hix5hd2.c 	writel_relaxed(val, clk->ctrl_reg);
ctrl_reg          178 drivers/clk/hisilicon/clk-hix5hd2.c 	writel_relaxed(val, clk->ctrl_reg);
ctrl_reg          203 drivers/clk/hisilicon/clk-hix5hd2.c 	val = readl_relaxed(clk->ctrl_reg);
ctrl_reg          205 drivers/clk/hisilicon/clk-hix5hd2.c 	writel_relaxed(val, clk->ctrl_reg);
ctrl_reg          218 drivers/clk/hisilicon/clk-hix5hd2.c 	val = readl_relaxed(clk->ctrl_reg);
ctrl_reg          221 drivers/clk/hisilicon/clk-hix5hd2.c 	writel_relaxed(val, clk->ctrl_reg);
ctrl_reg          236 drivers/clk/hisilicon/clk-hix5hd2.c 	val = readl_relaxed(clk->ctrl_reg);
ctrl_reg          239 drivers/clk/hisilicon/clk-hix5hd2.c 	writel_relaxed(val, clk->ctrl_reg);
ctrl_reg          279 drivers/clk/hisilicon/clk-hix5hd2.c 		p_clk->ctrl_reg = base + clks[i].ctrl_reg;
ctrl_reg           91 drivers/clk/microchip/clk-core.c 	void __iomem *ctrl_reg;
ctrl_reg          101 drivers/clk/microchip/clk-core.c 	return readl(pb->ctrl_reg) & PB_DIV_ENABLE;
ctrl_reg          108 drivers/clk/microchip/clk-core.c 	writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg));
ctrl_reg          116 drivers/clk/microchip/clk-core.c 	writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg));
ctrl_reg          147 drivers/clk/microchip/clk-core.c 	return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1;
ctrl_reg          174 drivers/clk/microchip/clk-core.c 	err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
ctrl_reg          185 drivers/clk/microchip/clk-core.c 	v = readl(pb->ctrl_reg);
ctrl_reg          191 drivers/clk/microchip/clk-core.c 	writel(v, pb->ctrl_reg);
ctrl_reg          196 drivers/clk/microchip/clk-core.c 	err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
ctrl_reg          226 drivers/clk/microchip/clk-core.c 	pbclk->ctrl_reg = desc->ctrl_reg + core->iobase;
ctrl_reg          240 drivers/clk/microchip/clk-core.c 	void __iomem *ctrl_reg;
ctrl_reg          251 drivers/clk/microchip/clk-core.c 	return readl(refo->ctrl_reg) & REFO_ON;
ctrl_reg          258 drivers/clk/microchip/clk-core.c 	writel(REFO_ON | REFO_OE, PIC32_SET(refo->ctrl_reg));
ctrl_reg          266 drivers/clk/microchip/clk-core.c 	writel(REFO_ON | REFO_OE, PIC32_CLR(refo->ctrl_reg));
ctrl_reg          280 drivers/clk/microchip/clk-core.c 	v = (readl(refo->ctrl_reg) >> REFO_SEL_SHIFT) & REFO_SEL_MASK;
ctrl_reg          363 drivers/clk/microchip/clk-core.c 	v = readl(refo->ctrl_reg);
ctrl_reg          367 drivers/clk/microchip/clk-core.c 	v = readl(refo->ctrl_reg + REFO_TRIM_REG);
ctrl_reg          450 drivers/clk/microchip/clk-core.c 	err = readl_poll_timeout(refo->ctrl_reg, v, !(v & REFO_ACTIVE),
ctrl_reg          462 drivers/clk/microchip/clk-core.c 	v = readl(refo->ctrl_reg);
ctrl_reg          466 drivers/clk/microchip/clk-core.c 	writel(v, refo->ctrl_reg);
ctrl_reg          490 drivers/clk/microchip/clk-core.c 	err = readl_poll_timeout(refo->ctrl_reg, v,
ctrl_reg          499 drivers/clk/microchip/clk-core.c 	v = readl(refo->ctrl_reg);
ctrl_reg          513 drivers/clk/microchip/clk-core.c 	writel(v, refo->ctrl_reg);
ctrl_reg          516 drivers/clk/microchip/clk-core.c 	v = readl(refo->ctrl_reg + REFO_TRIM_REG);
ctrl_reg          519 drivers/clk/microchip/clk-core.c 	writel(v, refo->ctrl_reg + REFO_TRIM_REG);
ctrl_reg          522 drivers/clk/microchip/clk-core.c 	writel(REFO_ON | REFO_DIVSW_EN, PIC32_SET(refo->ctrl_reg));
ctrl_reg          525 drivers/clk/microchip/clk-core.c 	err = readl_poll_timeout_atomic(refo->ctrl_reg, v, !(v & REFO_DIVSW_EN),
ctrl_reg          528 drivers/clk/microchip/clk-core.c 	writel(REFO_ON, PIC32_CLR(refo->ctrl_reg));
ctrl_reg          568 drivers/clk/microchip/clk-core.c 	refo->ctrl_reg = data->ctrl_reg + core->iobase;
ctrl_reg          580 drivers/clk/microchip/clk-core.c 	void __iomem *ctrl_reg;
ctrl_reg          650 drivers/clk/microchip/clk-core.c 	v = readl(pll->ctrl_reg);
ctrl_reg          700 drivers/clk/microchip/clk-core.c 	v = readl(pll->ctrl_reg);
ctrl_reg          708 drivers/clk/microchip/clk-core.c 	writel(v, pll->ctrl_reg);
ctrl_reg          742 drivers/clk/microchip/clk-core.c 	spll->ctrl_reg = data->ctrl_reg + core->iobase;
ctrl_reg          747 drivers/clk/microchip/clk-core.c 	spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK;
ctrl_reg           21 drivers/clk/microchip/clk-core.h 	const u32 ctrl_reg;
ctrl_reg           38 drivers/clk/microchip/clk-core.h 	const u32 ctrl_reg;
ctrl_reg           45 drivers/clk/microchip/clk-core.h 	const u32 ctrl_reg;
ctrl_reg           29 drivers/clk/microchip/clk-pic32mzda.c 		.ctrl_reg = (__reg),				\
ctrl_reg           43 drivers/clk/microchip/clk-pic32mzda.c 		.ctrl_reg = (__reg),					\
ctrl_reg           97 drivers/clk/microchip/clk-pic32mzda.c 	.ctrl_reg = 0x020,
ctrl_reg          110 drivers/clocksource/timer-cadence-ttc.c 	u32 ctrl_reg;
ctrl_reg          113 drivers/clocksource/timer-cadence-ttc.c 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
ctrl_reg          114 drivers/clocksource/timer-cadence-ttc.c 	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
ctrl_reg          115 drivers/clocksource/timer-cadence-ttc.c 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
ctrl_reg          123 drivers/clocksource/timer-cadence-ttc.c 	ctrl_reg |= CNT_CNTRL_RESET;
ctrl_reg          124 drivers/clocksource/timer-cadence-ttc.c 	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
ctrl_reg          125 drivers/clocksource/timer-cadence-ttc.c 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
ctrl_reg          194 drivers/clocksource/timer-cadence-ttc.c 	u32 ctrl_reg;
ctrl_reg          196 drivers/clocksource/timer-cadence-ttc.c 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
ctrl_reg          197 drivers/clocksource/timer-cadence-ttc.c 	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
ctrl_reg          198 drivers/clocksource/timer-cadence-ttc.c 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
ctrl_reg          216 drivers/clocksource/timer-cadence-ttc.c 	u32 ctrl_reg;
ctrl_reg          218 drivers/clocksource/timer-cadence-ttc.c 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
ctrl_reg          219 drivers/clocksource/timer-cadence-ttc.c 	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
ctrl_reg          220 drivers/clocksource/timer-cadence-ttc.c 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
ctrl_reg          133 drivers/clocksource/timer-rockchip.c 	u32 ctrl_reg = TIMER_CONTROL_REG3288;
ctrl_reg          142 drivers/clocksource/timer-rockchip.c 		ctrl_reg = TIMER_CONTROL_REG3399;
ctrl_reg          144 drivers/clocksource/timer-rockchip.c 	timer->ctrl = timer->base + ctrl_reg;
ctrl_reg         1205 drivers/dma/xilinx/xilinx_dma.c 	u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
ctrl_reg         1224 drivers/dma/xilinx/xilinx_dma.c 		ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;
ctrl_reg         1225 drivers/dma/xilinx/xilinx_dma.c 		ctrl_reg |= chan->desc_pendingcount <<
ctrl_reg         1227 drivers/dma/xilinx/xilinx_dma.c 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
ctrl_reg          337 drivers/fpga/socfpga.c 	u32 ctrl_reg;
ctrl_reg          346 drivers/fpga/socfpga.c 	ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);
ctrl_reg          347 drivers/fpga/socfpga.c 	ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK;
ctrl_reg          348 drivers/fpga/socfpga.c 	ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK;
ctrl_reg          349 drivers/fpga/socfpga.c 	ctrl_reg |= cfgmgr_modes[mode].ctrl;
ctrl_reg          352 drivers/fpga/socfpga.c 	ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE;
ctrl_reg          353 drivers/fpga/socfpga.c 	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
ctrl_reg          361 drivers/fpga/socfpga.c 	u32 ctrl_reg, status;
ctrl_reg          378 drivers/fpga/socfpga.c 	ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);
ctrl_reg          379 drivers/fpga/socfpga.c 	ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL;
ctrl_reg          380 drivers/fpga/socfpga.c 	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
ctrl_reg          386 drivers/fpga/socfpga.c 	ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCFGPULL;
ctrl_reg          387 drivers/fpga/socfpga.c 	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
ctrl_reg          221 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 	u32 ctrl_reg;
ctrl_reg          226 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 		ctrl_reg = sender->mipi_hs_gen_ctrl_reg;
ctrl_reg          230 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 		ctrl_reg = sender->mipi_lp_gen_ctrl_reg;
ctrl_reg          238 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 	REG_WRITE(ctrl_reg, val);
ctrl_reg          247 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 	u32 ctrl_reg;
ctrl_reg          256 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 		ctrl_reg = sender->mipi_hs_gen_ctrl_reg;
ctrl_reg          261 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 		ctrl_reg = sender->mipi_lp_gen_ctrl_reg;
ctrl_reg          302 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 	REG_WRITE(ctrl_reg, val);
ctrl_reg          132 drivers/gpu/drm/i915/display/vlv_dsi.c 	i915_reg_t data_reg, ctrl_reg;
ctrl_reg          145 drivers/gpu/drm/i915/display/vlv_dsi.c 		ctrl_reg = MIPI_LP_GEN_CTRL(port);
ctrl_reg          150 drivers/gpu/drm/i915/display/vlv_dsi.c 		ctrl_reg = MIPI_HS_GEN_CTRL(port);
ctrl_reg          173 drivers/gpu/drm/i915/display/vlv_dsi.c 	I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
ctrl_reg          981 drivers/gpu/drm/i915/display/vlv_dsi.c 		i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
ctrl_reg          983 drivers/gpu/drm/i915/display/vlv_dsi.c 		bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
ctrl_reg          198 drivers/gpu/drm/i915/gt/intel_engine_types.h 	u32 __iomem *ctrl_reg;
ctrl_reg          700 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (execlists->ctrl_reg) {
ctrl_reg          793 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (execlists->ctrl_reg)
ctrl_reg          794 drivers/gpu/drm/i915/gt/intel_lrc.c 		writel(EL_CTRL_LOAD, execlists->ctrl_reg);
ctrl_reg         3132 drivers/gpu/drm/i915/gt/intel_lrc.c 		execlists->ctrl_reg = uncore->regs +
ctrl_reg         1197 drivers/gpu/drm/i915/gvt/cmd_parser.c 	i915_reg_t ctrl_reg;
ctrl_reg         1243 drivers/gpu/drm/i915/gvt/cmd_parser.c 		info->ctrl_reg = DSPCNTR(info->pipe);
ctrl_reg         1247 drivers/gpu/drm/i915/gvt/cmd_parser.c 		info->ctrl_reg = SPRCTL(info->pipe);
ctrl_reg         1309 drivers/gpu/drm/i915/gvt/cmd_parser.c 	info->ctrl_reg = DSPCNTR(info->pipe);
ctrl_reg         1327 drivers/gpu/drm/i915/gvt/cmd_parser.c 		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
ctrl_reg         1332 drivers/gpu/drm/i915/gvt/cmd_parser.c 		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
ctrl_reg         1356 drivers/gpu/drm/i915/gvt/cmd_parser.c 		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
ctrl_reg         1361 drivers/gpu/drm/i915/gvt/cmd_parser.c 		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
ctrl_reg          300 drivers/gpu/drm/mediatek/mtk_hdmi.c 	u32 ctrl_reg = GRL_CTRL;
ctrl_reg          326 drivers/gpu/drm/mediatek/mtk_hdmi.c 		ctrl_reg = GRL_CTRL;
ctrl_reg          330 drivers/gpu/drm/mediatek/mtk_hdmi.c 		ctrl_reg = GRL_CTRL;
ctrl_reg          334 drivers/gpu/drm/mediatek/mtk_hdmi.c 		ctrl_reg = GRL_CTRL;
ctrl_reg          338 drivers/gpu/drm/mediatek/mtk_hdmi.c 		ctrl_reg = GRL_ACP_ISRC_CTRL;
ctrl_reg          344 drivers/gpu/drm/mediatek/mtk_hdmi.c 	mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
ctrl_reg          353 drivers/gpu/drm/mediatek/mtk_hdmi.c 	mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
ctrl_reg          207 drivers/hwmon/aspeed-pwm-tacho.c 	u32 ctrl_reg;
ctrl_reg          218 drivers/hwmon/aspeed-pwm-tacho.c 		.ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
ctrl_reg          227 drivers/hwmon/aspeed-pwm-tacho.c 		.ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
ctrl_reg          236 drivers/hwmon/aspeed-pwm-tacho.c 		.ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
ctrl_reg          245 drivers/hwmon/aspeed-pwm-tacho.c 	u32 ctrl_reg;
ctrl_reg          258 drivers/hwmon/aspeed-pwm-tacho.c 		.ctrl_reg = ASPEED_PTCR_CTRL,
ctrl_reg          269 drivers/hwmon/aspeed-pwm-tacho.c 		.ctrl_reg = ASPEED_PTCR_CTRL,
ctrl_reg          280 drivers/hwmon/aspeed-pwm-tacho.c 		.ctrl_reg = ASPEED_PTCR_CTRL,
ctrl_reg          291 drivers/hwmon/aspeed-pwm-tacho.c 		.ctrl_reg = ASPEED_PTCR_CTRL,
ctrl_reg          302 drivers/hwmon/aspeed-pwm-tacho.c 		.ctrl_reg = ASPEED_PTCR_CTRL_EXT,
ctrl_reg          313 drivers/hwmon/aspeed-pwm-tacho.c 		.ctrl_reg = ASPEED_PTCR_CTRL_EXT,
ctrl_reg          324 drivers/hwmon/aspeed-pwm-tacho.c 		.ctrl_reg = ASPEED_PTCR_CTRL_EXT,
ctrl_reg          335 drivers/hwmon/aspeed-pwm-tacho.c 		.ctrl_reg = ASPEED_PTCR_CTRL_EXT,
ctrl_reg          402 drivers/hwmon/aspeed-pwm-tacho.c 	regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
ctrl_reg          414 drivers/hwmon/aspeed-pwm-tacho.c 	regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
ctrl_reg          435 drivers/hwmon/aspeed-pwm-tacho.c 	regmap_update_bits(regmap, type_params[type].ctrl_reg,
ctrl_reg          447 drivers/hwmon/aspeed-pwm-tacho.c 	regmap_update_bits(regmap, type_params[type].ctrl_reg,
ctrl_reg          361 drivers/i2c/busses/i2c-cadence.c 	unsigned int ctrl_reg;
ctrl_reg          368 drivers/i2c/busses/i2c-cadence.c 	ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
ctrl_reg          369 drivers/i2c/busses/i2c-cadence.c 	ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
ctrl_reg          381 drivers/i2c/busses/i2c-cadence.c 		ctrl_reg |= CDNS_I2C_CR_HOLD;
ctrl_reg          383 drivers/i2c/busses/i2c-cadence.c 		ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD;
ctrl_reg          385 drivers/i2c/busses/i2c-cadence.c 	cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
ctrl_reg          424 drivers/i2c/busses/i2c-cadence.c 	unsigned int ctrl_reg;
ctrl_reg          432 drivers/i2c/busses/i2c-cadence.c 	ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
ctrl_reg          433 drivers/i2c/busses/i2c-cadence.c 	ctrl_reg &= ~CDNS_I2C_CR_RW;
ctrl_reg          434 drivers/i2c/busses/i2c-cadence.c 	ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
ctrl_reg          441 drivers/i2c/busses/i2c-cadence.c 		ctrl_reg |= CDNS_I2C_CR_HOLD;
ctrl_reg          443 drivers/i2c/busses/i2c-cadence.c 		ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD;
ctrl_reg          445 drivers/i2c/busses/i2c-cadence.c 	cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
ctrl_reg          740 drivers/i2c/busses/i2c-cadence.c 	unsigned int ctrl_reg;
ctrl_reg          748 drivers/i2c/busses/i2c-cadence.c 	ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
ctrl_reg          749 drivers/i2c/busses/i2c-cadence.c 	ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
ctrl_reg          750 drivers/i2c/busses/i2c-cadence.c 	ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
ctrl_reg          752 drivers/i2c/busses/i2c-cadence.c 	cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
ctrl_reg          607 drivers/i2c/busses/i2c-mv64xxx.c 	unsigned long ctrl_reg;
ctrl_reg          613 drivers/i2c/busses/i2c-mv64xxx.c 	ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
ctrl_reg          617 drivers/i2c/busses/i2c-mv64xxx.c 		ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
ctrl_reg          623 drivers/i2c/busses/i2c-mv64xxx.c 		ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
ctrl_reg          631 drivers/i2c/busses/i2c-mv64xxx.c 		ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
ctrl_reg          642 drivers/i2c/busses/i2c-mv64xxx.c 		ctrl_reg |=
ctrl_reg          653 drivers/i2c/busses/i2c-mv64xxx.c 	writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
ctrl_reg          399 drivers/iio/accel/sca3000.c 				 u8 ctrl_reg)
ctrl_reg          412 drivers/iio/accel/sca3000.c 	ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg);
ctrl_reg          105 drivers/input/keyboard/pmic8xxx-keypad.c 	u8 ctrl_reg;
ctrl_reg          454 drivers/input/keyboard/pmic8xxx-keypad.c 	kp->ctrl_reg |= KEYP_CTRL_KEYP_EN;
ctrl_reg          456 drivers/input/keyboard/pmic8xxx-keypad.c 	rc = regmap_write(kp->regmap, KEYP_CTRL, kp->ctrl_reg);
ctrl_reg          467 drivers/input/keyboard/pmic8xxx-keypad.c 	kp->ctrl_reg &= ~KEYP_CTRL_KEYP_EN;
ctrl_reg          469 drivers/input/keyboard/pmic8xxx-keypad.c 	rc = regmap_write(kp->regmap, KEYP_CTRL, kp->ctrl_reg);
ctrl_reg          611 drivers/input/keyboard/pmic8xxx-keypad.c 	kp->ctrl_reg = ctrl_val;
ctrl_reg          275 drivers/input/rmi4/rmi_f30.c 	u8 *ctrl_reg = f30->ctrl_regs;
ctrl_reg          300 drivers/input/rmi4/rmi_f30.c 				      f30->register_count, &ctrl_reg);
ctrl_reg          303 drivers/input/rmi4/rmi_f30.c 			      sizeof(u8), &ctrl_reg);
ctrl_reg          307 drivers/input/rmi4/rmi_f30.c 				      f30->register_count, &ctrl_reg);
ctrl_reg          310 drivers/input/rmi4/rmi_f30.c 				      f30->register_count, &ctrl_reg);
ctrl_reg          315 drivers/input/rmi4/rmi_f30.c 				      f30->register_count, &ctrl_reg);
ctrl_reg          319 drivers/input/rmi4/rmi_f30.c 				      &ctrl_reg);
ctrl_reg          325 drivers/input/rmi4/rmi_f30.c 				      f30->gpioled_count, &ctrl_reg);
ctrl_reg          331 drivers/input/rmi4/rmi_f30.c 				      f30->gpioled_count, &ctrl_reg);
ctrl_reg          336 drivers/input/rmi4/rmi_f30.c 				      f30->register_count, &ctrl_reg);
ctrl_reg          339 drivers/input/rmi4/rmi_f30.c 				      sizeof(u8), &ctrl_reg);
ctrl_reg          344 drivers/input/rmi4/rmi_f30.c 				      sizeof(u8), &ctrl_reg);
ctrl_reg          346 drivers/input/rmi4/rmi_f30.c 	f30->ctrl_regs_size = ctrl_reg -
ctrl_reg          790 drivers/iommu/mtk_iommu.c 	reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
ctrl_reg          815 drivers/iommu/mtk_iommu.c 	writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
ctrl_reg           23 drivers/iommu/mtk_iommu.h 	u32				ctrl_reg;
ctrl_reg          668 drivers/iommu/mtk_iommu_v1.c 	reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
ctrl_reg          683 drivers/iommu/mtk_iommu_v1.c 	writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
ctrl_reg          399 drivers/media/platform/davinci/vpif.h 	u32 ctrl_reg;
ctrl_reg          401 drivers/media/platform/davinci/vpif.h 		ctrl_reg = VPIF_CH0_CTRL;
ctrl_reg          403 drivers/media/platform/davinci/vpif.h 		ctrl_reg = VPIF_CH1_CTRL;
ctrl_reg          406 drivers/media/platform/davinci/vpif.h 		vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
ctrl_reg          408 drivers/media/platform/davinci/vpif.h 		vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
ctrl_reg          413 drivers/media/platform/davinci/vpif.h 	u32 ctrl_reg;
ctrl_reg          415 drivers/media/platform/davinci/vpif.h 		ctrl_reg = VPIF_CH0_CTRL;
ctrl_reg          417 drivers/media/platform/davinci/vpif.h 		ctrl_reg = VPIF_CH1_CTRL;
ctrl_reg          420 drivers/media/platform/davinci/vpif.h 		vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
ctrl_reg          422 drivers/media/platform/davinci/vpif.h 		vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
ctrl_reg           53 drivers/misc/ibmasm/lowlevel.h 	void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
ctrl_reg           54 drivers/misc/ibmasm/lowlevel.h 	writel( readl(ctrl_reg) & ~mask, ctrl_reg);
ctrl_reg           59 drivers/misc/ibmasm/lowlevel.h 	void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
ctrl_reg           60 drivers/misc/ibmasm/lowlevel.h 	writel( readl(ctrl_reg) | mask, ctrl_reg);
ctrl_reg          602 drivers/mmc/host/mvsdio.c 	u32 ctrl_reg = 0;
ctrl_reg          624 drivers/mmc/host/mvsdio.c 	ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
ctrl_reg          625 drivers/mmc/host/mvsdio.c 	ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
ctrl_reg          628 drivers/mmc/host/mvsdio.c 	ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
ctrl_reg          629 drivers/mmc/host/mvsdio.c 	ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
ctrl_reg          632 drivers/mmc/host/mvsdio.c 		ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
ctrl_reg          635 drivers/mmc/host/mvsdio.c 		ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
ctrl_reg          647 drivers/mmc/host/mvsdio.c 		ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
ctrl_reg          650 drivers/mmc/host/mvsdio.c 	host->ctrl = ctrl_reg;
ctrl_reg          651 drivers/mmc/host/mvsdio.c 	mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
ctrl_reg          652 drivers/mmc/host/mvsdio.c 	dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
ctrl_reg          653 drivers/mmc/host/mvsdio.c 		(ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
ctrl_reg          655 drivers/mmc/host/mvsdio.c 		(ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
ctrl_reg          657 drivers/mmc/host/mvsdio.c 		(ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
ctrl_reg         1258 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c 		unsigned int ctrl_reg = CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A;
ctrl_reg         1259 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c 		void __iomem *ctrl = adap->regs + PF_REG(mbox, ctrl_reg);
ctrl_reg         1138 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 	u32 ctrl_reg;
ctrl_reg         1143 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 	ctrl_reg = er32(CTRL);
ctrl_reg         1144 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 	ctrl_reg |= (E1000_CTRL_ILOS |		/* Invert Loss-Of-Signal */
ctrl_reg         1150 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 	ew32(CTRL, ctrl_reg);
ctrl_reg         1205 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 	u32 ctrl_reg = 0;
ctrl_reg         1220 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 	ctrl_reg = er32(CTRL);
ctrl_reg         1226 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 	ctrl_reg = er32(CTRL);
ctrl_reg         1227 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 	ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
ctrl_reg         1228 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 	ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
ctrl_reg         1235 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 		ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
ctrl_reg         1242 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 			ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
ctrl_reg         1245 drivers/net/ethernet/intel/e1000/e1000_ethtool.c 	ew32(CTRL, ctrl_reg);
ctrl_reg         1314 drivers/net/ethernet/intel/e1000e/ethtool.c 	u32 ctrl_reg = 0;
ctrl_reg         1325 drivers/net/ethernet/intel/e1000e/ethtool.c 		ctrl_reg = er32(CTRL);
ctrl_reg         1326 drivers/net/ethernet/intel/e1000e/ethtool.c 		ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
ctrl_reg         1327 drivers/net/ethernet/intel/e1000e/ethtool.c 		ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
ctrl_reg         1332 drivers/net/ethernet/intel/e1000e/ethtool.c 		ew32(CTRL, ctrl_reg);
ctrl_reg         1404 drivers/net/ethernet/intel/e1000e/ethtool.c 	ctrl_reg = er32(CTRL);
ctrl_reg         1405 drivers/net/ethernet/intel/e1000e/ethtool.c 	ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
ctrl_reg         1406 drivers/net/ethernet/intel/e1000e/ethtool.c 	ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
ctrl_reg         1412 drivers/net/ethernet/intel/e1000e/ethtool.c 		ctrl_reg |= E1000_CTRL_SLU;	/* Set Link Up */
ctrl_reg         1416 drivers/net/ethernet/intel/e1000e/ethtool.c 		ctrl_reg |= E1000_CTRL_ILOS;	/* Invert Loss of Signal */
ctrl_reg         1422 drivers/net/ethernet/intel/e1000e/ethtool.c 			ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
ctrl_reg         1425 drivers/net/ethernet/intel/e1000e/ethtool.c 	ew32(CTRL, ctrl_reg);
ctrl_reg         2267 drivers/net/ethernet/intel/e1000e/ich8lan.c 	u32 ctrl_reg = 0;
ctrl_reg         2289 drivers/net/ethernet/intel/e1000e/ich8lan.c 	ctrl_reg = er32(CTRL);
ctrl_reg         2291 drivers/net/ethernet/intel/e1000e/ich8lan.c 	reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
ctrl_reg         2298 drivers/net/ethernet/intel/e1000e/ich8lan.c 	ew32(CTRL, ctrl_reg);
ctrl_reg         1656 drivers/net/ethernet/intel/igb/e1000_82575.c 	u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
ctrl_reg         1679 drivers/net/ethernet/intel/igb/e1000_82575.c 	ctrl_reg = rd32(E1000_CTRL);
ctrl_reg         1680 drivers/net/ethernet/intel/igb/e1000_82575.c 	ctrl_reg |= E1000_CTRL_SLU;
ctrl_reg         1684 drivers/net/ethernet/intel/igb/e1000_82575.c 		ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
ctrl_reg         1725 drivers/net/ethernet/intel/igb/e1000_82575.c 		ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
ctrl_reg         1733 drivers/net/ethernet/intel/igb/e1000_82575.c 	wr32(E1000_CTRL, ctrl_reg);
ctrl_reg         1607 drivers/net/ethernet/intel/igb/igb_ethtool.c 	u32 ctrl_reg = 0;
ctrl_reg         1636 drivers/net/ethernet/intel/igb/igb_ethtool.c 	ctrl_reg = rd32(E1000_CTRL);
ctrl_reg         1637 drivers/net/ethernet/intel/igb/igb_ethtool.c 	ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
ctrl_reg         1638 drivers/net/ethernet/intel/igb/igb_ethtool.c 	ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
ctrl_reg         1645 drivers/net/ethernet/intel/igb/igb_ethtool.c 		ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
ctrl_reg         1647 drivers/net/ethernet/intel/igb/igb_ethtool.c 	wr32(E1000_CTRL, ctrl_reg);
ctrl_reg           49 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	u32 ctrl_reg;
ctrl_reg           51 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	ctrl_reg =  IXGB_CTRL0_RST |
ctrl_reg           62 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
ctrl_reg           64 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
ctrl_reg           69 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	ctrl_reg = IXGB_READ_REG(hw, CTRL0);
ctrl_reg           72 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
ctrl_reg           76 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 		ctrl_reg =  /* Enable interrupt from XFP and SerDes */
ctrl_reg           82 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 		IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
ctrl_reg           89 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	return ctrl_reg;
ctrl_reg          100 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	u32 ctrl_reg;
ctrl_reg          138 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	ctrl_reg = ixgb_mac_reset(hw);
ctrl_reg          147 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	return ctrl_reg & IXGB_CTRL0_RST;
ctrl_reg          277 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	u32 ctrl_reg;
ctrl_reg          289 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	ctrl_reg = ixgb_mac_reset(hw);
ctrl_reg          615 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	u32 ctrl_reg;
ctrl_reg          622 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	ctrl_reg = IXGB_READ_REG(hw, CTRL0);
ctrl_reg          625 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
ctrl_reg          639 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 		ctrl_reg |= (IXGB_CTRL0_CMDC);
ctrl_reg          645 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 		ctrl_reg |= (IXGB_CTRL0_RPE);
ctrl_reg          651 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 		ctrl_reg |= (IXGB_CTRL0_TPE);
ctrl_reg          658 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 		ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
ctrl_reg          669 drivers/net/ethernet/intel/ixgb/ixgb_hw.c 	IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
ctrl_reg          123 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c 	u32 ctrl_reg;		/* GMAC glue-logic control register */
ctrl_reg          164 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c 	u32 reg = dwmac->ctrl_reg;
ctrl_reg          200 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c 	u32 reg = dwmac->ctrl_reg;
ctrl_reg          231 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c 	u32 reg = dwmac->ctrl_reg;
ctrl_reg          266 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c 	err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg);
ctrl_reg          757 drivers/net/ethernet/sun/niu.c 	unsigned long ctrl_reg, test_cfg_reg, i;
ctrl_reg          763 drivers/net/ethernet/sun/niu.c 		ctrl_reg = ENET_SERDES_0_CTRL_CFG;
ctrl_reg          767 drivers/net/ethernet/sun/niu.c 		ctrl_reg = ENET_SERDES_1_CTRL_CFG;
ctrl_reg          799 drivers/net/ethernet/sun/niu.c 	nw64(ctrl_reg, ctrl_val);
ctrl_reg          910 drivers/net/ethernet/sun/niu.c 	unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
ctrl_reg          921 drivers/net/ethernet/sun/niu.c 		ctrl_reg = ENET_SERDES_0_CTRL_CFG;
ctrl_reg          927 drivers/net/ethernet/sun/niu.c 		ctrl_reg = ENET_SERDES_1_CTRL_CFG;
ctrl_reg          965 drivers/net/ethernet/sun/niu.c 	nw64(ctrl_reg, ctrl_val);
ctrl_reg         2353 drivers/net/ethernet/sun/niu.c 	unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
ctrl_reg         2358 drivers/net/ethernet/sun/niu.c 		ctrl_reg = ENET_SERDES_0_CTRL_CFG;
ctrl_reg         2363 drivers/net/ethernet/sun/niu.c 		ctrl_reg = ENET_SERDES_1_CTRL_CFG;
ctrl_reg         2398 drivers/net/ethernet/sun/niu.c 	nw64(ctrl_reg, ctrl_val);
ctrl_reg          740 drivers/net/ethernet/xilinx/xilinx_emaclite.c 	u32 ctrl_reg;
ctrl_reg          750 drivers/net/ethernet/xilinx/xilinx_emaclite.c 	ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
ctrl_reg          754 drivers/net/ethernet/xilinx/xilinx_emaclite.c 	xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
ctrl_reg          785 drivers/net/ethernet/xilinx/xilinx_emaclite.c 	u32 ctrl_reg;
ctrl_reg          799 drivers/net/ethernet/xilinx/xilinx_emaclite.c 	ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
ctrl_reg          804 drivers/net/ethernet/xilinx/xilinx_emaclite.c 	xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
ctrl_reg          102 drivers/net/wireless/realtek/rtw88/sec.c 	u16 ctrl_reg;
ctrl_reg          108 drivers/net/wireless/realtek/rtw88/sec.c 	ctrl_reg = rtw_read16(rtwdev, REG_CR);
ctrl_reg          109 drivers/net/wireless/realtek/rtw88/sec.c 	ctrl_reg |= RTW_SEC_ENGINE_EN;
ctrl_reg          110 drivers/net/wireless/realtek/rtw88/sec.c 	rtw_write16(rtwdev, REG_CR, ctrl_reg);
ctrl_reg          178 drivers/net/wireless/st/cw1200/bh.c 					  u16 *ctrl_reg)
ctrl_reg          183 drivers/net/wireless/st/cw1200/bh.c 			ST90TDS_CONTROL_REG_ID, ctrl_reg);
ctrl_reg          186 drivers/net/wireless/st/cw1200/bh.c 				ST90TDS_CONTROL_REG_ID, ctrl_reg);
ctrl_reg          196 drivers/net/wireless/st/cw1200/bh.c 	u16 ctrl_reg;
ctrl_reg          213 drivers/net/wireless/st/cw1200/bh.c 	ret = cw1200_bh_read_ctrl_reg(priv, &ctrl_reg);
ctrl_reg          220 drivers/net/wireless/st/cw1200/bh.c 	if (ctrl_reg & ST90TDS_CONT_RDY_BIT) {
ctrl_reg          238 drivers/net/wireless/st/cw1200/bh.c 			       uint16_t *ctrl_reg,
ctrl_reg          252 drivers/net/wireless/st/cw1200/bh.c 	read_len = (*ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) * 2;
ctrl_reg          259 drivers/net/wireless/st/cw1200/bh.c 			 read_len, *ctrl_reg);
ctrl_reg          293 drivers/net/wireless/st/cw1200/bh.c 	*ctrl_reg = __le16_to_cpu(
ctrl_reg          424 drivers/net/wireless/st/cw1200/bh.c 	u16 ctrl_reg = 0;
ctrl_reg          548 drivers/net/wireless/st/cw1200/bh.c 		if (cw1200_bh_read_ctrl_reg(priv, &ctrl_reg))
ctrl_reg          552 drivers/net/wireless/st/cw1200/bh.c 		if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) {
ctrl_reg          553 drivers/net/wireless/st/cw1200/bh.c 			ret = cw1200_bh_rx_helper(priv, &ctrl_reg, &tx);
ctrl_reg          557 drivers/net/wireless/st/cw1200/bh.c 			if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) {
ctrl_reg          558 drivers/net/wireless/st/cw1200/bh.c 				ret = cw1200_bh_rx_helper(priv, &ctrl_reg, &tx);
ctrl_reg          586 drivers/net/wireless/st/cw1200/bh.c 			if (cw1200_bh_read_ctrl_reg(priv, &ctrl_reg))
ctrl_reg          593 drivers/net/wireless/st/cw1200/bh.c 		if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK)
ctrl_reg          140 drivers/pci/hotplug/cpqphp.h 	SLOT_RST =		offsetof(struct ctrl_reg, slot_RST),
ctrl_reg          141 drivers/pci/hotplug/cpqphp.h 	SLOT_ENABLE =		offsetof(struct ctrl_reg, slot_enable),
ctrl_reg          142 drivers/pci/hotplug/cpqphp.h 	MISC =			offsetof(struct ctrl_reg, misc),
ctrl_reg          143 drivers/pci/hotplug/cpqphp.h 	LED_CONTROL =		offsetof(struct ctrl_reg, led_control),
ctrl_reg          144 drivers/pci/hotplug/cpqphp.h 	INT_INPUT_CLEAR =	offsetof(struct ctrl_reg, int_input_clear),
ctrl_reg          145 drivers/pci/hotplug/cpqphp.h 	INT_MASK =		offsetof(struct ctrl_reg, int_mask),
ctrl_reg          146 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED0 =	offsetof(struct ctrl_reg, reserved0),
ctrl_reg          147 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED1 =	offsetof(struct ctrl_reg, reserved1),
ctrl_reg          148 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED2 =	offsetof(struct ctrl_reg, reserved1),
ctrl_reg          149 drivers/pci/hotplug/cpqphp.h 	GEN_OUTPUT_AB =		offsetof(struct ctrl_reg, gen_output_AB),
ctrl_reg          150 drivers/pci/hotplug/cpqphp.h 	NON_INT_INPUT =		offsetof(struct ctrl_reg, non_int_input),
ctrl_reg          151 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED3 =	offsetof(struct ctrl_reg, reserved3),
ctrl_reg          152 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED4 =	offsetof(struct ctrl_reg, reserved4),
ctrl_reg          153 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED5 =	offsetof(struct ctrl_reg, reserved5),
ctrl_reg          154 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED6 =	offsetof(struct ctrl_reg, reserved6),
ctrl_reg          155 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED7 =	offsetof(struct ctrl_reg, reserved7),
ctrl_reg          156 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED8 =	offsetof(struct ctrl_reg, reserved8),
ctrl_reg          157 drivers/pci/hotplug/cpqphp.h 	SLOT_MASK =		offsetof(struct ctrl_reg, slot_mask),
ctrl_reg          158 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED9 =	offsetof(struct ctrl_reg, reserved9),
ctrl_reg          159 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED10 =	offsetof(struct ctrl_reg, reserved10),
ctrl_reg          160 drivers/pci/hotplug/cpqphp.h 	CTRL_RESERVED11 =	offsetof(struct ctrl_reg, reserved11),
ctrl_reg          161 drivers/pci/hotplug/cpqphp.h 	SLOT_SERR =		offsetof(struct ctrl_reg, slot_SERR),
ctrl_reg          162 drivers/pci/hotplug/cpqphp.h 	SLOT_POWER =		offsetof(struct ctrl_reg, slot_power),
ctrl_reg          163 drivers/pci/hotplug/cpqphp.h 	NEXT_CURR_FREQ =	offsetof(struct ctrl_reg, next_curr_freq),
ctrl_reg          164 drivers/pci/hotplug/cpqphp.h 	RESET_FREQ_MODE =	offsetof(struct ctrl_reg, reset_freq_mode),
ctrl_reg          195 drivers/pci/hotplug/shpchp.h 	BASE_OFFSET	 = offsetof(struct ctrl_reg, base_offset),
ctrl_reg          196 drivers/pci/hotplug/shpchp.h 	SLOT_AVAIL1	 = offsetof(struct ctrl_reg, slot_avail1),
ctrl_reg          197 drivers/pci/hotplug/shpchp.h 	SLOT_AVAIL2	 = offsetof(struct ctrl_reg, slot_avail2),
ctrl_reg          198 drivers/pci/hotplug/shpchp.h 	SLOT_CONFIG	 = offsetof(struct ctrl_reg, slot_config),
ctrl_reg          199 drivers/pci/hotplug/shpchp.h 	SEC_BUS_CONFIG	 = offsetof(struct ctrl_reg, sec_bus_config),
ctrl_reg          200 drivers/pci/hotplug/shpchp.h 	MSI_CTRL	 = offsetof(struct ctrl_reg, msi_ctrl),
ctrl_reg          201 drivers/pci/hotplug/shpchp.h 	PROG_INTERFACE	 = offsetof(struct ctrl_reg, prog_interface),
ctrl_reg          202 drivers/pci/hotplug/shpchp.h 	CMD		 = offsetof(struct ctrl_reg, cmd),
ctrl_reg          203 drivers/pci/hotplug/shpchp.h 	CMD_STATUS	 = offsetof(struct ctrl_reg, cmd_status),
ctrl_reg          204 drivers/pci/hotplug/shpchp.h 	INTR_LOC	 = offsetof(struct ctrl_reg, intr_loc),
ctrl_reg          205 drivers/pci/hotplug/shpchp.h 	SERR_LOC	 = offsetof(struct ctrl_reg, serr_loc),
ctrl_reg          206 drivers/pci/hotplug/shpchp.h 	SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
ctrl_reg          207 drivers/pci/hotplug/shpchp.h 	SLOT1		 = offsetof(struct ctrl_reg, slot1),
ctrl_reg           65 drivers/phy/marvell/phy-berlin-sata.c static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,
ctrl_reg           71 drivers/phy/marvell/phy-berlin-sata.c 	writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
ctrl_reg           74 drivers/phy/marvell/phy-berlin-sata.c 	regval = readl(ctrl_reg + PORT_VSR_DATA);
ctrl_reg           77 drivers/phy/marvell/phy-berlin-sata.c 	writel(regval, ctrl_reg + PORT_VSR_DATA);
ctrl_reg           84 drivers/phy/marvell/phy-berlin-sata.c 	void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80);
ctrl_reg          104 drivers/phy/marvell/phy-berlin-sata.c 	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
ctrl_reg          109 drivers/phy/marvell/phy-berlin-sata.c 	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
ctrl_reg          113 drivers/phy/marvell/phy-berlin-sata.c 	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
ctrl_reg          117 drivers/phy/marvell/phy-berlin-sata.c 	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
ctrl_reg          121 drivers/phy/marvell/phy-berlin-sata.c 	regval = readl(ctrl_reg + PORT_SCR_CTL);
ctrl_reg          124 drivers/phy/marvell/phy-berlin-sata.c 	writel(regval, ctrl_reg + PORT_SCR_CTL);
ctrl_reg          373 drivers/pinctrl/cirrus/pinctrl-lochnagar.c 	.ctrl_reg = LOCHNAGAR1_##CTRL, \
ctrl_reg          385 drivers/pinctrl/cirrus/pinctrl-lochnagar.c 	.ctrl_reg = LOCHNAGAR2_##ID##_CTRL, \
ctrl_reg          399 drivers/pinctrl/cirrus/pinctrl-lochnagar.c 	u16 ctrl_reg;
ctrl_reg          878 drivers/pinctrl/cirrus/pinctrl-lochnagar.c 	ret = regmap_update_bits(regmap, aif->ctrl_reg,
ctrl_reg         1003 drivers/pinctrl/cirrus/pinctrl-lochnagar.c 	ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val);
ctrl_reg         5639 drivers/pinctrl/sirf/pinctrl-atlas7.c 	void __iomem *ctrl_reg;
ctrl_reg         5645 drivers/pinctrl/sirf/pinctrl-atlas7.c 	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
ctrl_reg         5649 drivers/pinctrl/sirf/pinctrl-atlas7.c 	val = readl(ctrl_reg);
ctrl_reg         5651 drivers/pinctrl/sirf/pinctrl-atlas7.c 	writel(val, ctrl_reg);
ctrl_reg         5659 drivers/pinctrl/sirf/pinctrl-atlas7.c 	void __iomem *ctrl_reg;
ctrl_reg         5664 drivers/pinctrl/sirf/pinctrl-atlas7.c 	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
ctrl_reg         5666 drivers/pinctrl/sirf/pinctrl-atlas7.c 	val = readl(ctrl_reg);
ctrl_reg         5669 drivers/pinctrl/sirf/pinctrl-atlas7.c 	writel(val, ctrl_reg);
ctrl_reg         5690 drivers/pinctrl/sirf/pinctrl-atlas7.c 	void __iomem *ctrl_reg;
ctrl_reg         5696 drivers/pinctrl/sirf/pinctrl-atlas7.c 	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
ctrl_reg         5700 drivers/pinctrl/sirf/pinctrl-atlas7.c 	val = readl(ctrl_reg);
ctrl_reg         5703 drivers/pinctrl/sirf/pinctrl-atlas7.c 	writel(val, ctrl_reg);
ctrl_reg         5714 drivers/pinctrl/sirf/pinctrl-atlas7.c 	void __iomem *ctrl_reg;
ctrl_reg         5720 drivers/pinctrl/sirf/pinctrl-atlas7.c 	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
ctrl_reg         5724 drivers/pinctrl/sirf/pinctrl-atlas7.c 	val = readl(ctrl_reg);
ctrl_reg         5763 drivers/pinctrl/sirf/pinctrl-atlas7.c 	writel(val, ctrl_reg);
ctrl_reg         5834 drivers/pinctrl/sirf/pinctrl-atlas7.c 	void __iomem *ctrl_reg;
ctrl_reg         5839 drivers/pinctrl/sirf/pinctrl-atlas7.c 	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
ctrl_reg         5841 drivers/pinctrl/sirf/pinctrl-atlas7.c 	val = readl(ctrl_reg);
ctrl_reg         5843 drivers/pinctrl/sirf/pinctrl-atlas7.c 	writel(val, ctrl_reg);
ctrl_reg         5909 drivers/pinctrl/sirf/pinctrl-atlas7.c 	void __iomem *ctrl_reg;
ctrl_reg         5914 drivers/pinctrl/sirf/pinctrl-atlas7.c 	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
ctrl_reg         5916 drivers/pinctrl/sirf/pinctrl-atlas7.c 	out_ctrl = readl(ctrl_reg);
ctrl_reg         5924 drivers/pinctrl/sirf/pinctrl-atlas7.c 	writel(out_ctrl, ctrl_reg);
ctrl_reg         5967 drivers/pinctrl/sirf/pinctrl-atlas7.c 	void __iomem *ctrl_reg;
ctrl_reg         5973 drivers/pinctrl/sirf/pinctrl-atlas7.c 	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
ctrl_reg         5977 drivers/pinctrl/sirf/pinctrl-atlas7.c 	ctrl = readl(ctrl_reg);
ctrl_reg         5982 drivers/pinctrl/sirf/pinctrl-atlas7.c 	writel(ctrl, ctrl_reg);
ctrl_reg         6104 drivers/pinctrl/sirf/pinctrl-atlas7.c 	void __iomem *ctrl_reg;
ctrl_reg         6110 drivers/pinctrl/sirf/pinctrl-atlas7.c 			ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
ctrl_reg         6111 drivers/pinctrl/sirf/pinctrl-atlas7.c 			bank->sleep_data[pin] = readl(ctrl_reg);
ctrl_reg         6122 drivers/pinctrl/sirf/pinctrl-atlas7.c 	void __iomem *ctrl_reg;
ctrl_reg         6128 drivers/pinctrl/sirf/pinctrl-atlas7.c 			ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
ctrl_reg         6129 drivers/pinctrl/sirf/pinctrl-atlas7.c 			writel(bank->sleep_data[pin], ctrl_reg);
ctrl_reg          217 drivers/power/supply/ltc2941-battery-gauge.c 	u8 ctrl_reg;
ctrl_reg          229 drivers/power/supply/ltc2941-battery-gauge.c 		LTC294X_REG_CONTROL, &ctrl_reg, 1);
ctrl_reg          233 drivers/power/supply/ltc2941-battery-gauge.c 	ctrl_reg |= LTC294X_REG_CONTROL_SHUTDOWN_MASK;
ctrl_reg          235 drivers/power/supply/ltc2941-battery-gauge.c 		LTC294X_REG_CONTROL, &ctrl_reg, 1);
ctrl_reg          247 drivers/power/supply/ltc2941-battery-gauge.c 	ctrl_reg &= ~LTC294X_REG_CONTROL_SHUTDOWN_MASK;
ctrl_reg          249 drivers/power/supply/ltc2941-battery-gauge.c 		LTC294X_REG_CONTROL, &ctrl_reg, 1);
ctrl_reg         1627 drivers/regulator/qcom_spmi-regulator.c 	u8 ctrl_reg[8], reg, mask;
ctrl_reg         1631 drivers/regulator/qcom_spmi-regulator.c 	ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
ctrl_reg         1641 drivers/regulator/qcom_spmi-regulator.c 		ctrl_reg[SPMI_COMMON_IDX_ENABLE] &=
ctrl_reg         1643 drivers/regulator/qcom_spmi-regulator.c 		ctrl_reg[SPMI_COMMON_IDX_ENABLE] |=
ctrl_reg         1652 drivers/regulator/qcom_spmi-regulator.c 		ctrl_reg[SPMI_COMMON_IDX_MODE] &=
ctrl_reg         1654 drivers/regulator/qcom_spmi-regulator.c 		ctrl_reg[SPMI_COMMON_IDX_MODE] |=
ctrl_reg         1660 drivers/regulator/qcom_spmi-regulator.c 		ctrl_reg[SPMI_COMMON_IDX_MODE] &=
ctrl_reg         1662 drivers/regulator/qcom_spmi-regulator.c 		ctrl_reg[SPMI_COMMON_IDX_MODE] |=
ctrl_reg         1671 drivers/regulator/qcom_spmi-regulator.c 		ctrl_reg[SPMI_COMMON_IDX_MODE] &=
ctrl_reg         1673 drivers/regulator/qcom_spmi-regulator.c 		ctrl_reg[SPMI_COMMON_IDX_MODE] |=
ctrl_reg         1678 drivers/regulator/qcom_spmi-regulator.c 	ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
ctrl_reg           40 drivers/regulator/vctrl-regulator.c 	struct regulator *ctrl_reg;
ctrl_reg           85 drivers/regulator/vctrl-regulator.c 	int ctrl_uV = regulator_get_voltage_rdev(vctrl->ctrl_reg->rdev);
ctrl_reg           95 drivers/regulator/vctrl-regulator.c 	struct regulator *ctrl_reg = vctrl->ctrl_reg;
ctrl_reg           96 drivers/regulator/vctrl-regulator.c 	int orig_ctrl_uV = regulator_get_voltage_rdev(ctrl_reg->rdev);
ctrl_reg          102 drivers/regulator/vctrl-regulator.c 		return regulator_set_voltage_rdev(ctrl_reg->rdev,
ctrl_reg          120 drivers/regulator/vctrl-regulator.c 		ret = regulator_set_voltage_rdev(ctrl_reg->rdev,
ctrl_reg          137 drivers/regulator/vctrl-regulator.c 	regulator_set_voltage_rdev(ctrl_reg->rdev, orig_ctrl_uV, orig_ctrl_uV,
ctrl_reg          154 drivers/regulator/vctrl-regulator.c 	struct regulator *ctrl_reg = vctrl->ctrl_reg;
ctrl_reg          163 drivers/regulator/vctrl-regulator.c 		ret = regulator_set_voltage_rdev(ctrl_reg->rdev,
ctrl_reg          182 drivers/regulator/vctrl-regulator.c 		ret = regulator_set_voltage_rdev(ctrl_reg->rdev,
ctrl_reg          205 drivers/regulator/vctrl-regulator.c 		if (!regulator_set_voltage_rdev(ctrl_reg->rdev,
ctrl_reg          237 drivers/regulator/vctrl-regulator.c 	vctrl->ctrl_reg = devm_regulator_get(&pdev->dev, "ctrl");
ctrl_reg          238 drivers/regulator/vctrl-regulator.c 	if (IS_ERR(vctrl->ctrl_reg))
ctrl_reg          239 drivers/regulator/vctrl-regulator.c 		return PTR_ERR(vctrl->ctrl_reg);
ctrl_reg          322 drivers/regulator/vctrl-regulator.c 	struct regulator *ctrl_reg = vctrl->ctrl_reg;
ctrl_reg          328 drivers/regulator/vctrl-regulator.c 	n_voltages = regulator_count_voltages(ctrl_reg);
ctrl_reg          334 drivers/regulator/vctrl-regulator.c 		ctrl_uV = regulator_list_voltage(ctrl_reg, i);
ctrl_reg          354 drivers/regulator/vctrl-regulator.c 		ctrl_uV = regulator_list_voltage(ctrl_reg, i);
ctrl_reg          398 drivers/regulator/vctrl-regulator.c 	int ret = regulator_enable(vctrl->ctrl_reg);
ctrl_reg          409 drivers/regulator/vctrl-regulator.c 	int ret = regulator_disable(vctrl->ctrl_reg);
ctrl_reg          471 drivers/regulator/vctrl-regulator.c 	if ((regulator_get_linear_step(vctrl->ctrl_reg) == 1) ||
ctrl_reg          472 drivers/regulator/vctrl-regulator.c 	    (regulator_count_voltages(vctrl->ctrl_reg) == -EINVAL)) {
ctrl_reg          493 drivers/regulator/vctrl-regulator.c 		ctrl_uV = regulator_get_voltage_rdev(vctrl->ctrl_reg->rdev);
ctrl_reg           85 drivers/regulator/wm831x-ldo.c 	int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;
ctrl_reg           96 drivers/regulator/wm831x-ldo.c 	ret = wm831x_reg_read(wm831x, ctrl_reg);
ctrl_reg          111 drivers/regulator/wm831x-ldo.c 	int ctrl_reg = ldo->base + WM831X_LDO_CONTROL;
ctrl_reg          125 drivers/regulator/wm831x-ldo.c 		ret = wm831x_set_bits(wm831x, ctrl_reg,
ctrl_reg          138 drivers/regulator/wm831x-ldo.c 		ret = wm831x_set_bits(wm831x, ctrl_reg,
ctrl_reg           54 drivers/rtc/rtc-bd70528.c 	unsigned int ctrl_reg;
ctrl_reg           56 drivers/rtc/rtc-bd70528.c 	ret = regmap_read(bd70528->regmap, BD70528_REG_WAKE_EN, &ctrl_reg);
ctrl_reg           61 drivers/rtc/rtc-bd70528.c 		if (ctrl_reg & BD70528_MASK_WAKE_EN)
ctrl_reg           71 drivers/rtc/rtc-bd70528.c 		ctrl_reg |= BD70528_MASK_WAKE_EN;
ctrl_reg           73 drivers/rtc/rtc-bd70528.c 		ctrl_reg &= ~BD70528_MASK_WAKE_EN;
ctrl_reg           76 drivers/rtc/rtc-bd70528.c 			    ctrl_reg);
ctrl_reg           83 drivers/rtc/rtc-bd70528.c 	unsigned int ctrl_reg;
ctrl_reg           98 drivers/rtc/rtc-bd70528.c 			  &ctrl_reg);
ctrl_reg          103 drivers/rtc/rtc-bd70528.c 		if (ctrl_reg & BD70528_MASK_ELAPSED_TIMER_EN)
ctrl_reg          113 drivers/rtc/rtc-bd70528.c 		ctrl_reg |= BD70528_MASK_ELAPSED_TIMER_EN;
ctrl_reg          115 drivers/rtc/rtc-bd70528.c 		ctrl_reg &= ~BD70528_MASK_ELAPSED_TIMER_EN;
ctrl_reg          118 drivers/rtc/rtc-bd70528.c 			    ctrl_reg);
ctrl_reg          810 drivers/rtc/rtc-ds1307.c 	unsigned int ctrl_reg;
ctrl_reg          813 drivers/rtc/rtc-ds1307.c 	regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
ctrl_reg          815 drivers/rtc/rtc-ds1307.c 	val = ctrl_reg & M41TXX_M_CALIBRATION;
ctrl_reg          818 drivers/rtc/rtc-ds1307.c 	if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
ctrl_reg          829 drivers/rtc/rtc-ds1307.c 	unsigned int ctrl_reg;
ctrl_reg          835 drivers/rtc/rtc-ds1307.c 		ctrl_reg = DIV_ROUND_CLOSEST(offset,
ctrl_reg          837 drivers/rtc/rtc-ds1307.c 		ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
ctrl_reg          839 drivers/rtc/rtc-ds1307.c 		ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
ctrl_reg          845 drivers/rtc/rtc-ds1307.c 				  ctrl_reg);
ctrl_reg         1148 drivers/rtc/rtc-ds1307.c 	unsigned int ctrl_reg;
ctrl_reg         1150 drivers/rtc/rtc-ds1307.c 	regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
ctrl_reg         1152 drivers/rtc/rtc-ds1307.c 	return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
ctrl_reg           80 drivers/rtc/rtc-pm8xxx.c 	unsigned int ctrl_reg, rtc_ctrl_reg;
ctrl_reg           98 drivers/rtc/rtc-pm8xxx.c 	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
ctrl_reg          102 drivers/rtc/rtc-pm8xxx.c 	if (ctrl_reg & regs->alarm_en) {
ctrl_reg          104 drivers/rtc/rtc-pm8xxx.c 		ctrl_reg &= ~regs->alarm_en;
ctrl_reg          105 drivers/rtc/rtc-pm8xxx.c 		rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
ctrl_reg          160 drivers/rtc/rtc-pm8xxx.c 		ctrl_reg |= regs->alarm_en;
ctrl_reg          161 drivers/rtc/rtc-pm8xxx.c 		rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
ctrl_reg          222 drivers/rtc/rtc-pm8xxx.c 	unsigned int ctrl_reg;
ctrl_reg          243 drivers/rtc/rtc-pm8xxx.c 	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
ctrl_reg          248 drivers/rtc/rtc-pm8xxx.c 		ctrl_reg |= regs->alarm_en;
ctrl_reg          250 drivers/rtc/rtc-pm8xxx.c 		ctrl_reg &= ~regs->alarm_en;
ctrl_reg          252 drivers/rtc/rtc-pm8xxx.c 	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
ctrl_reg          303 drivers/rtc/rtc-pm8xxx.c 	unsigned int ctrl_reg;
ctrl_reg          307 drivers/rtc/rtc-pm8xxx.c 	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
ctrl_reg          312 drivers/rtc/rtc-pm8xxx.c 		ctrl_reg |= regs->alarm_en;
ctrl_reg          314 drivers/rtc/rtc-pm8xxx.c 		ctrl_reg &= ~regs->alarm_en;
ctrl_reg          316 drivers/rtc/rtc-pm8xxx.c 	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
ctrl_reg          339 drivers/rtc/rtc-pm8xxx.c 	unsigned int ctrl_reg;
ctrl_reg          348 drivers/rtc/rtc-pm8xxx.c 	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
ctrl_reg          354 drivers/rtc/rtc-pm8xxx.c 	ctrl_reg &= ~regs->alarm_en;
ctrl_reg          356 drivers/rtc/rtc-pm8xxx.c 	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
ctrl_reg          367 drivers/rtc/rtc-pm8xxx.c 	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
ctrl_reg          374 drivers/rtc/rtc-pm8xxx.c 	ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
ctrl_reg          375 drivers/rtc/rtc-pm8xxx.c 	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
ctrl_reg          387 drivers/rtc/rtc-pm8xxx.c 	unsigned int ctrl_reg;
ctrl_reg          391 drivers/rtc/rtc-pm8xxx.c 	rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
ctrl_reg          395 drivers/rtc/rtc-pm8xxx.c 	if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
ctrl_reg          396 drivers/rtc/rtc-pm8xxx.c 		ctrl_reg |= PM8xxx_RTC_ENABLE;
ctrl_reg          397 drivers/rtc/rtc-pm8xxx.c 		rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
ctrl_reg           46 drivers/rtc/rtc-rk808.c 	unsigned int ctrl_reg;
ctrl_reg          105 drivers/rtc/rtc-rk808.c 	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
ctrl_reg          119 drivers/rtc/rtc-rk808.c 	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
ctrl_reg          166 drivers/rtc/rtc-rk808.c 	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
ctrl_reg          181 drivers/rtc/rtc-rk808.c 	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
ctrl_reg          372 drivers/rtc/rtc-rk808.c 	.ctrl_reg = RK808_RTC_CTRL_REG,
ctrl_reg          380 drivers/rtc/rtc-rk808.c 	.ctrl_reg = RK817_RTC_CTRL_REG,
ctrl_reg          410 drivers/rtc/rtc-rk808.c 	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
ctrl_reg         7015 drivers/scsi/advansys.c 	uchar ctrl_reg;
ctrl_reg         7039 drivers/scsi/advansys.c 	ctrl_reg = AscGetChipControl(iop_base);
ctrl_reg         7040 drivers/scsi/advansys.c 	saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
ctrl_reg         7069 drivers/scsi/advansys.c 		if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
ctrl_reg          445 drivers/scsi/zorro_esp.c 	writeb(*ctrl_data, &dregs->ctrl_reg);
ctrl_reg          538 drivers/scsi/zorro_esp.c 	writeb(*ctrl_data, &dregs->ctrl_reg);
ctrl_reg          143 drivers/soc/mediatek/mtk-scpsys.c 	struct scp_ctrl_reg ctrl_reg;
ctrl_reg          165 drivers/soc/mediatek/mtk-scpsys.c 	u32 status = readl(scp->base + scp->ctrl_reg.pwr_sta_offs) &
ctrl_reg          167 drivers/soc/mediatek/mtk-scpsys.c 	u32 status2 = readl(scp->base + scp->ctrl_reg.pwr_sta2nd_offs) &
ctrl_reg          359 drivers/soc/mediatek/mtk-scpsys.c 	scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
ctrl_reg          360 drivers/soc/mediatek/mtk-scpsys.c 	scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
ctrl_reg          346 drivers/spi/spi-armada-3700.c 	unsigned int ctrl_reg;
ctrl_reg          357 drivers/spi/spi-armada-3700.c 	ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
ctrl_reg          358 drivers/spi/spi-armada-3700.c 	if (a3700_spi->wait_mask & ctrl_reg)
ctrl_reg          383 drivers/spi/spi-armada-3700.c 	ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
ctrl_reg          384 drivers/spi/spi-armada-3700.c 	if (a3700_spi->wait_mask & ctrl_reg)
ctrl_reg          151 drivers/spi/spi-cadence.c 	u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
ctrl_reg          154 drivers/spi/spi-cadence.c 		ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
ctrl_reg          164 drivers/spi/spi-cadence.c 	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
ctrl_reg          176 drivers/spi/spi-cadence.c 	u32 ctrl_reg;
ctrl_reg          178 drivers/spi/spi-cadence.c 	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
ctrl_reg          182 drivers/spi/spi-cadence.c 		ctrl_reg |= CDNS_SPI_CR_SSCTRL;
ctrl_reg          185 drivers/spi/spi-cadence.c 		ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
ctrl_reg          187 drivers/spi/spi-cadence.c 			ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
ctrl_reg          191 drivers/spi/spi-cadence.c 			ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
ctrl_reg          195 drivers/spi/spi-cadence.c 	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
ctrl_reg          207 drivers/spi/spi-cadence.c 	u32 ctrl_reg, new_ctrl_reg;
ctrl_reg          210 drivers/spi/spi-cadence.c 	ctrl_reg = new_ctrl_reg;
ctrl_reg          219 drivers/spi/spi-cadence.c 	if (new_ctrl_reg != ctrl_reg) {
ctrl_reg          250 drivers/spi/spi-cadence.c 	u32 ctrl_reg, baud_rate_val;
ctrl_reg          255 drivers/spi/spi-cadence.c 	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
ctrl_reg          265 drivers/spi/spi-cadence.c 		ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
ctrl_reg          266 drivers/spi/spi-cadence.c 		ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
ctrl_reg          270 drivers/spi/spi-cadence.c 	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
ctrl_reg           44 drivers/spi/spi-jcore.c static int jcore_spi_wait(void __iomem *ctrl_reg)
ctrl_reg           49 drivers/spi/spi-jcore.c 		if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY))
ctrl_reg           59 drivers/spi/spi-jcore.c 	void __iomem *ctrl_reg = hw->base + CTRL_REG;
ctrl_reg           61 drivers/spi/spi-jcore.c 	if (jcore_spi_wait(ctrl_reg))
ctrl_reg           65 drivers/spi/spi-jcore.c 	writel(hw->cs_reg | hw->speed_reg, ctrl_reg);
ctrl_reg          101 drivers/spi/spi-jcore.c 	void __iomem *ctrl_reg = hw->base + CTRL_REG;
ctrl_reg          119 drivers/spi/spi-jcore.c 		if (jcore_spi_wait(ctrl_reg))
ctrl_reg          123 drivers/spi/spi-jcore.c 		writel(xmit, ctrl_reg);
ctrl_reg          125 drivers/spi/spi-jcore.c 		if (jcore_spi_wait(ctrl_reg))
ctrl_reg           49 drivers/spi/spi-ti-qspi.c 	unsigned int		ctrl_reg;
ctrl_reg          486 drivers/spi/spi-ti-qspi.c 		regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
ctrl_reg          500 drivers/spi/spi-ti-qspi.c 		regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
ctrl_reg          746 drivers/spi/spi-ti-qspi.c 						 1, &qspi->ctrl_reg);
ctrl_reg          436 drivers/staging/comedi/drivers/das16.c 	unsigned int		ctrl_reg;
ctrl_reg          481 drivers/staging/comedi/drivers/das16.c 	if (!(devpriv->ctrl_reg & DAS16_CTRL_DMAE)) {
ctrl_reg          747 drivers/staging/comedi/drivers/das16.c 	devpriv->ctrl_reg &= ~(DAS16_CTRL_INTE | DAS16_CTRL_PACING_MASK);
ctrl_reg          748 drivers/staging/comedi/drivers/das16.c 	devpriv->ctrl_reg |= DAS16_CTRL_DMAE;
ctrl_reg          750 drivers/staging/comedi/drivers/das16.c 		devpriv->ctrl_reg |= DAS16_CTRL_EXT_PACER;
ctrl_reg          752 drivers/staging/comedi/drivers/das16.c 		devpriv->ctrl_reg |= DAS16_CTRL_INT_PACER;
ctrl_reg          753 drivers/staging/comedi/drivers/das16.c 	outb(devpriv->ctrl_reg, dev->iobase + DAS16_CTRL_REG);
ctrl_reg          771 drivers/staging/comedi/drivers/das16.c 	devpriv->ctrl_reg &= ~(DAS16_CTRL_INTE | DAS16_CTRL_DMAE |
ctrl_reg          773 drivers/staging/comedi/drivers/das16.c 	outb(devpriv->ctrl_reg, dev->iobase + DAS16_CTRL_REG);
ctrl_reg         1157 drivers/staging/comedi/drivers/das16.c 	devpriv->ctrl_reg = DAS16_CTRL_IRQ(dev->irq);
ctrl_reg         1158 drivers/staging/comedi/drivers/das16.c 	outb(devpriv->ctrl_reg, dev->iobase + DAS16_CTRL_REG);
ctrl_reg          490 drivers/tty/serial/xilinx_uartps.c 	u32 ctrl_reg;
ctrl_reg          520 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
ctrl_reg          521 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
ctrl_reg          522 drivers/tty/serial/xilinx_uartps.c 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
ctrl_reg          547 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
ctrl_reg          548 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
ctrl_reg          549 drivers/tty/serial/xilinx_uartps.c 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
ctrl_reg          561 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
ctrl_reg          562 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
ctrl_reg          563 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
ctrl_reg          564 drivers/tty/serial/xilinx_uartps.c 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
ctrl_reg          690 drivers/tty/serial/xilinx_uartps.c 	unsigned int ctrl_reg, mode_reg, val;
ctrl_reg          707 drivers/tty/serial/xilinx_uartps.c 	ctrl_reg = readl(port->membase + CDNS_UART_CR);
ctrl_reg          708 drivers/tty/serial/xilinx_uartps.c 	ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
ctrl_reg          709 drivers/tty/serial/xilinx_uartps.c 	writel(ctrl_reg, port->membase + CDNS_UART_CR);
ctrl_reg          728 drivers/tty/serial/xilinx_uartps.c 	ctrl_reg = readl(port->membase + CDNS_UART_CR);
ctrl_reg          729 drivers/tty/serial/xilinx_uartps.c 	ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
ctrl_reg          730 drivers/tty/serial/xilinx_uartps.c 	writel(ctrl_reg, port->membase + CDNS_UART_CR);
ctrl_reg          740 drivers/tty/serial/xilinx_uartps.c 	ctrl_reg = readl(port->membase + CDNS_UART_CR);
ctrl_reg          741 drivers/tty/serial/xilinx_uartps.c 	ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
ctrl_reg          742 drivers/tty/serial/xilinx_uartps.c 	ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
ctrl_reg          743 drivers/tty/serial/xilinx_uartps.c 	writel(ctrl_reg, port->membase + CDNS_UART_CR);
ctrl_reg         1323 drivers/tty/serial/xilinx_uartps.c 	u32 ctrl_reg;
ctrl_reg         1335 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
ctrl_reg         1336 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
ctrl_reg         1337 drivers/tty/serial/xilinx_uartps.c 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
ctrl_reg         1345 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg = readl(port->membase + CDNS_UART_CR);
ctrl_reg         1346 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
ctrl_reg         1347 drivers/tty/serial/xilinx_uartps.c 		ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
ctrl_reg         1348 drivers/tty/serial/xilinx_uartps.c 		writel(ctrl_reg, port->membase + CDNS_UART_CR);
ctrl_reg           48 drivers/usb/c67x00/c67x00-sched.c 	u8 ctrl_reg;		/* Byte 6 */
ctrl_reg          125 drivers/usb/c67x00/c67x00-sched.c 				  !(td->ctrl_reg & SEQ_SEL)))
ctrl_reg          148 drivers/usb/c67x00/c67x00-sched.c 	dev_dbg(dev, "ctrl_reg:       0x%02x\n", td->ctrl_reg);
ctrl_reg          620 drivers/usb/c67x00/c67x00-sched.c 	td->ctrl_reg = cmd;
ctrl_reg         1031 drivers/usb/c67x00/c67x00-sched.c 				      !(td->ctrl_reg & SEQ_SEL));
ctrl_reg          715 drivers/video/fbdev/sm501fb.c 	void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL;
ctrl_reg          718 drivers/video/fbdev/sm501fb.c 	control = smc501_readl(ctrl_reg);
ctrl_reg          724 drivers/video/fbdev/sm501fb.c 		smc501_writel(control, ctrl_reg);
ctrl_reg          729 drivers/video/fbdev/sm501fb.c 		smc501_writel(control, ctrl_reg);
ctrl_reg          741 drivers/video/fbdev/sm501fb.c 			smc501_writel(control, ctrl_reg);
ctrl_reg          752 drivers/video/fbdev/sm501fb.c 			smc501_writel(control, ctrl_reg);
ctrl_reg          764 drivers/video/fbdev/sm501fb.c 			smc501_writel(control, ctrl_reg);
ctrl_reg          775 drivers/video/fbdev/sm501fb.c 			smc501_writel(control, ctrl_reg);
ctrl_reg          781 drivers/video/fbdev/sm501fb.c 		smc501_writel(control, ctrl_reg);
ctrl_reg          786 drivers/video/fbdev/sm501fb.c 		smc501_writel(control, ctrl_reg);
ctrl_reg          187 drivers/watchdog/machzwd.c 	unsigned int ctrl_reg = 0;
ctrl_reg          195 drivers/watchdog/machzwd.c 	ctrl_reg = zf_get_control();
ctrl_reg          196 drivers/watchdog/machzwd.c 	ctrl_reg |= (ENABLE_WD1|ENABLE_WD2);	/* disable wd1 and wd2 */
ctrl_reg          197 drivers/watchdog/machzwd.c 	ctrl_reg &= ~(ENABLE_WD1|ENABLE_WD2);
ctrl_reg          198 drivers/watchdog/machzwd.c 	zf_set_control(ctrl_reg);
ctrl_reg          210 drivers/watchdog/machzwd.c 	unsigned int ctrl_reg = 0;
ctrl_reg          226 drivers/watchdog/machzwd.c 	ctrl_reg = zf_get_control();
ctrl_reg          227 drivers/watchdog/machzwd.c 	ctrl_reg |= (ENABLE_WD1|zf_action);
ctrl_reg          228 drivers/watchdog/machzwd.c 	zf_set_control(ctrl_reg);
ctrl_reg          237 drivers/watchdog/machzwd.c 	unsigned int ctrl_reg = 0;
ctrl_reg          250 drivers/watchdog/machzwd.c 		ctrl_reg = zf_get_control();
ctrl_reg          251 drivers/watchdog/machzwd.c 		ctrl_reg |= RESET_WD1;
ctrl_reg          252 drivers/watchdog/machzwd.c 		zf_set_control(ctrl_reg);
ctrl_reg          255 drivers/watchdog/machzwd.c 		ctrl_reg &= ~(RESET_WD1);
ctrl_reg          256 drivers/watchdog/machzwd.c 		zf_set_control(ctrl_reg);