crtc_state 2581 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c static bool modeset_required(struct drm_crtc_state *crtc_state, crtc_state 2585 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (!drm_atomic_crtc_needs_modeset(crtc_state)) crtc_state 2588 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (!crtc_state->enable) crtc_state 2591 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c return crtc_state->active; crtc_state 2594 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c static bool modereset_required(struct drm_crtc_state *crtc_state) crtc_state 2596 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (!drm_atomic_crtc_needs_modeset(crtc_state)) crtc_state 2599 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c return !crtc_state->enable || !crtc_state->active; crtc_state 3070 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct drm_crtc_state *crtc_state) crtc_state 3072 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); crtc_state 4421 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct drm_crtc_state *crtc_state, crtc_state 5421 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; crtc_state 5443 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (crtc_state && crtc_state->stream) { crtc_state 5445 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dc_stream_set_cursor_position(crtc_state->stream, crtc_state 5466 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (crtc_state->stream) { crtc_state 5468 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (!dc_stream_set_cursor_attributes(crtc_state->stream, crtc_state 5472 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (!dc_stream_set_cursor_position(crtc_state->stream, crtc_state 6096 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, crtc_state 6099 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); crtc_state 6445 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct drm_crtc_state *crtc_state; crtc_state 6465 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); crtc_state 6467 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ret = PTR_ERR_OR_ZERO(crtc_state); crtc_state 6472 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c crtc_state->mode_changed = true; crtc_state 141 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c struct dm_crtc_state *crtc_state; crtc_state 179 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c crtc_state = to_dm_crtc_state(crtc->state); crtc_state 196 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c dm_is_crc_source_dprx(crtc_state->crc_src))) { crtc_state 226 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { crtc_state 235 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src); crtc_state 259 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c crtc_state->crc_src = source; crtc_state 262 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c crtc_state->crc_skip_count = 0; crtc_state 282 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c struct dm_crtc_state *crtc_state; crtc_state 289 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c crtc_state = to_dm_crtc_state(crtc->state); crtc_state 290 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c stream_state = crtc_state->stream; crtc_state 293 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c if (!amdgpu_dm_is_valid_crc_source(crtc_state->crc_src)) crtc_state 302 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c if (crtc_state->crc_skip_count < 2) { crtc_state 303 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c crtc_state->crc_skip_count += 1; crtc_state 307 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c if (dm_is_crc_source_crtc(crtc_state->crc_src)) { crtc_state 2020 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c enum crtc_state state) crtc_state 275 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h enum crtc_state state); crtc_state 226 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c enum crtc_state state) crtc_state 793 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c enum crtc_state state) crtc_state 753 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c enum crtc_state state) crtc_state 607 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h enum crtc_state state); crtc_state 180 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h enum crtc_state state); crtc_state 236 drivers/gpu/drm/arm/hdlcd_crtc.c struct drm_crtc_state *crtc_state; crtc_state 245 drivers/gpu/drm/arm/hdlcd_crtc.c for_each_new_crtc_in_state(state->state, crtc, crtc_state, i) { crtc_state 247 drivers/gpu/drm/arm/hdlcd_crtc.c if (!state->fb && crtc_state->active) crtc_state 249 drivers/gpu/drm/arm/hdlcd_crtc.c return drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 126 drivers/gpu/drm/arm/malidp_mw.c struct drm_crtc_state *crtc_state, crtc_state 138 drivers/gpu/drm/arm/malidp_mw.c if ((fb->width != crtc_state->mode.hdisplay) || crtc_state 139 drivers/gpu/drm/arm/malidp_mw.c (fb->height != crtc_state->mode.vdisplay)) { crtc_state 273 drivers/gpu/drm/arm/malidp_planes.c struct drm_crtc_state *crtc_state = crtc_state 279 drivers/gpu/drm/arm/malidp_planes.c if (!crtc_state) crtc_state 282 drivers/gpu/drm/arm/malidp_planes.c mc = to_malidp_crtc_state(crtc_state); crtc_state 284 drivers/gpu/drm/arm/malidp_planes.c ret = drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 113 drivers/gpu/drm/armada/armada_plane.c struct drm_crtc_state *crtc_state; crtc_state 123 drivers/gpu/drm/armada/armada_plane.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); crtc_state 125 drivers/gpu/drm/armada/armada_plane.c crtc_state = crtc->state; crtc_state 127 drivers/gpu/drm/armada/armada_plane.c ret = drm_atomic_helper_check_plane_state(state, crtc_state, 0, crtc_state 132 drivers/gpu/drm/armada/armada_plane.c interlace = crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE; crtc_state 142 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c struct drm_crtc_state *crtc_state, crtc_state 603 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c struct drm_crtc_state *crtc_state; crtc_state 611 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c crtc_state = drm_atomic_get_existing_crtc_state(s->state, s->crtc); crtc_state 612 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c mode = &crtc_state->adjusted_mode; crtc_state 614 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c ret = drm_atomic_helper_check_plane_state(s, crtc_state, crtc_state 47 drivers/gpu/drm/bochs/bochs_kms.c struct drm_crtc_state *crtc_state, crtc_state 52 drivers/gpu/drm/bochs/bochs_kms.c bochs_hw_setmode(bochs, &crtc_state->mode); crtc_state 1156 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c struct drm_crtc_state *crtc_state; crtc_state 1167 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); crtc_state 1168 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (!crtc_state) crtc_state 1171 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (crtc_state->self_refresh_active && !dp->psr_supported) crtc_state 403 drivers/gpu/drm/cirrus/cirrus.c struct drm_crtc_state *crtc_state) crtc_state 413 drivers/gpu/drm/cirrus/cirrus.c struct drm_crtc_state *crtc_state, crtc_state 418 drivers/gpu/drm/cirrus/cirrus.c cirrus_mode_set(cirrus, &crtc_state->mode, plane_state->fb); crtc_state 294 drivers/gpu/drm/drm_atomic.c struct drm_crtc_state *crtc_state; crtc_state 298 drivers/gpu/drm/drm_atomic.c crtc_state = drm_atomic_get_existing_crtc_state(state, crtc); crtc_state 299 drivers/gpu/drm/drm_atomic.c if (crtc_state) crtc_state 300 drivers/gpu/drm/drm_atomic.c return crtc_state; crtc_state 306 drivers/gpu/drm/drm_atomic.c crtc_state = crtc->funcs->atomic_duplicate_state(crtc); crtc_state 307 drivers/gpu/drm/drm_atomic.c if (!crtc_state) crtc_state 310 drivers/gpu/drm/drm_atomic.c state->crtcs[index].state = crtc_state; crtc_state 312 drivers/gpu/drm/drm_atomic.c state->crtcs[index].new_state = crtc_state; crtc_state 314 drivers/gpu/drm/drm_atomic.c crtc_state->state = state; crtc_state 317 drivers/gpu/drm/drm_atomic.c crtc->base.id, crtc->name, crtc_state, state); crtc_state 319 drivers/gpu/drm/drm_atomic.c return crtc_state; crtc_state 405 drivers/gpu/drm/drm_atomic.c struct drm_crtc_state *crtc_state; crtc_state 423 drivers/gpu/drm/drm_atomic.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc_state 426 drivers/gpu/drm/drm_atomic.c if (writeback_job->fb && !crtc_state->active) { crtc_state 498 drivers/gpu/drm/drm_atomic.c struct drm_crtc_state *crtc_state; crtc_state 500 drivers/gpu/drm/drm_atomic.c crtc_state = drm_atomic_get_crtc_state(state, crtc_state 502 drivers/gpu/drm/drm_atomic.c if (IS_ERR(crtc_state)) crtc_state 503 drivers/gpu/drm/drm_atomic.c return ERR_CAST(crtc_state); crtc_state 989 drivers/gpu/drm/drm_atomic.c struct drm_crtc_state *crtc_state; crtc_state 991 drivers/gpu/drm/drm_atomic.c crtc_state = drm_atomic_get_crtc_state(state, crtc_state 993 drivers/gpu/drm/drm_atomic.c if (IS_ERR(crtc_state)) crtc_state 994 drivers/gpu/drm/drm_atomic.c return ERR_CAST(crtc_state); crtc_state 1043 drivers/gpu/drm/drm_atomic.c struct drm_crtc_state *crtc_state; crtc_state 1046 drivers/gpu/drm/drm_atomic.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 1047 drivers/gpu/drm/drm_atomic.c if (IS_ERR(crtc_state)) crtc_state 1048 drivers/gpu/drm/drm_atomic.c return PTR_ERR(crtc_state); crtc_state 1063 drivers/gpu/drm/drm_atomic.c if (!(crtc_state->connector_mask & drm_connector_mask(connector))) crtc_state 1354 drivers/gpu/drm/drm_atomic.c struct drm_crtc_state *crtc_state; crtc_state 1360 drivers/gpu/drm/drm_atomic.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 1361 drivers/gpu/drm/drm_atomic.c if (IS_ERR(crtc_state)) crtc_state 1362 drivers/gpu/drm/drm_atomic.c return PTR_ERR(crtc_state); crtc_state 1372 drivers/gpu/drm/drm_atomic.c ret = drm_atomic_set_mode_for_crtc(crtc_state, NULL); crtc_state 1376 drivers/gpu/drm/drm_atomic.c crtc_state->active = false; crtc_state 1390 drivers/gpu/drm/drm_atomic.c ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode); crtc_state 1394 drivers/gpu/drm/drm_atomic.c crtc_state->active = true; crtc_state 1432 drivers/gpu/drm/drm_atomic.c struct drm_crtc_state *crtc_state; crtc_state 1442 drivers/gpu/drm/drm_atomic.c for_each_new_crtc_in_state(state, crtc, crtc_state, i) crtc_state 1443 drivers/gpu/drm/drm_atomic.c drm_atomic_crtc_print_state(&p, crtc_state); crtc_state 78 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 81 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, crtc_state 84 drivers/gpu/drm/drm_atomic_helper.c if (WARN_ON(!crtc_state)) crtc_state 87 drivers/gpu/drm/drm_atomic_helper.c crtc_state->planes_changed = true; crtc_state 91 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); crtc_state 93 drivers/gpu/drm/drm_atomic_helper.c if (WARN_ON(!crtc_state)) crtc_state 96 drivers/gpu/drm/drm_atomic_helper.c crtc_state->planes_changed = true; crtc_state 169 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 199 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); crtc_state 205 drivers/gpu/drm/drm_atomic_helper.c if (!crtc_state->connector_mask) { crtc_state 206 drivers/gpu/drm/drm_atomic_helper.c ret = drm_atomic_set_mode_prop_for_crtc(crtc_state, crtc_state 211 drivers/gpu/drm/drm_atomic_helper.c crtc_state->active = false; crtc_state 225 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 240 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, crtc); crtc_state 242 drivers/gpu/drm/drm_atomic_helper.c crtc_state->encoder_mask &= crtc_state 251 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, crtc); crtc_state 253 drivers/gpu/drm/drm_atomic_helper.c crtc_state->encoder_mask |= crtc_state 265 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 284 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, encoder_crtc); crtc_state 285 drivers/gpu/drm/drm_atomic_helper.c crtc_state->connectors_changed = true; crtc_state 299 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 307 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, old_connector_state->crtc); crtc_state 308 drivers/gpu/drm/drm_atomic_helper.c crtc_state->connectors_changed = true; crtc_state 312 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, new_connector_state->crtc); crtc_state 313 drivers/gpu/drm/drm_atomic_helper.c crtc_state->connectors_changed = true; crtc_state 327 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, crtc_state 348 drivers/gpu/drm/drm_atomic_helper.c crtc_state->active) { crtc_state 398 drivers/gpu/drm/drm_atomic_helper.c crtc_state->connectors_changed = true; crtc_state 540 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 547 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, crtc); crtc_state 548 drivers/gpu/drm/drm_atomic_helper.c if (!crtc_state) crtc_state 550 drivers/gpu/drm/drm_atomic_helper.c if (!crtc_state->mode_changed && !crtc_state->connectors_changed) crtc_state 553 drivers/gpu/drm/drm_atomic_helper.c mode = &crtc_state->mode; crtc_state 768 drivers/gpu/drm/drm_atomic_helper.c const struct drm_crtc_state *crtc_state, crtc_state 781 drivers/gpu/drm/drm_atomic_helper.c WARN_ON(plane_state->crtc && plane_state->crtc != crtc_state->crtc); crtc_state 797 drivers/gpu/drm/drm_atomic_helper.c if (!crtc_state->enable && !can_update_disabled) { crtc_state 814 drivers/gpu/drm/drm_atomic_helper.c if (crtc_state->enable) crtc_state 815 drivers/gpu/drm/drm_atomic_helper.c drm_mode_get_hv_timing(&crtc_state->mode, &clip.x2, &clip.y2); crtc_state 1658 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 1665 drivers/gpu/drm/drm_atomic_helper.c for_each_new_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 1666 drivers/gpu/drm/drm_atomic_helper.c if (drm_atomic_crtc_needs_modeset(crtc_state)) crtc_state 2484 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 2486 drivers/gpu/drm/drm_atomic_helper.c crtc_state = old_plane_state->crtc->state; crtc_state 2488 drivers/gpu/drm/drm_atomic_helper.c if (drm_atomic_crtc_needs_modeset(crtc_state) && crtc_state 2992 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 3003 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 3004 drivers/gpu/drm/drm_atomic_helper.c if (IS_ERR(crtc_state)) { crtc_state 3005 drivers/gpu/drm/drm_atomic_helper.c ret = PTR_ERR(crtc_state); crtc_state 3009 drivers/gpu/drm/drm_atomic_helper.c crtc_state->active = false; crtc_state 3011 drivers/gpu/drm/drm_atomic_helper.c ret = drm_atomic_set_mode_prop_for_crtc(crtc_state, NULL); crtc_state 3114 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 3116 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 3117 drivers/gpu/drm/drm_atomic_helper.c if (IS_ERR(crtc_state)) { crtc_state 3118 drivers/gpu/drm/drm_atomic_helper.c err = PTR_ERR(crtc_state); crtc_state 3303 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 3306 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 3307 drivers/gpu/drm/drm_atomic_helper.c if (IS_ERR(crtc_state)) crtc_state 3308 drivers/gpu/drm/drm_atomic_helper.c return PTR_ERR(crtc_state); crtc_state 3310 drivers/gpu/drm/drm_atomic_helper.c crtc_state->event = event; crtc_state 3311 drivers/gpu/drm/drm_atomic_helper.c crtc_state->async_flip = flags & DRM_MODE_PAGE_FLIP_ASYNC; crtc_state 3324 drivers/gpu/drm/drm_atomic_helper.c if (!crtc_state->active) { crtc_state 3402 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 3415 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, crtc); crtc_state 3416 drivers/gpu/drm/drm_atomic_helper.c if (WARN_ON(!crtc_state)) { crtc_state 3420 drivers/gpu/drm/drm_atomic_helper.c crtc_state->target_vblank = target; crtc_state 3450 drivers/gpu/drm/drm_atomic_helper.c struct drm_crtc_state *crtc_state; crtc_state 3478 drivers/gpu/drm/drm_atomic_helper.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 3479 drivers/gpu/drm/drm_atomic_helper.c if (IS_ERR(crtc_state)) { crtc_state 3480 drivers/gpu/drm/drm_atomic_helper.c ret = PTR_ERR(crtc_state); crtc_state 3485 drivers/gpu/drm/drm_atomic_helper.c replaced = drm_property_replace_blob(&crtc_state->degamma_lut, NULL); crtc_state 3486 drivers/gpu/drm/drm_atomic_helper.c replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL); crtc_state 3487 drivers/gpu/drm/drm_atomic_helper.c replaced |= drm_property_replace_blob(&crtc_state->gamma_lut, blob); crtc_state 3488 drivers/gpu/drm/drm_atomic_helper.c crtc_state->color_mgmt_changed |= replaced; crtc_state 74 drivers/gpu/drm/drm_atomic_state_helper.c struct drm_crtc_state *crtc_state) crtc_state 76 drivers/gpu/drm/drm_atomic_state_helper.c if (crtc_state) crtc_state 77 drivers/gpu/drm/drm_atomic_state_helper.c crtc_state->crtc = crtc; crtc_state 79 drivers/gpu/drm/drm_atomic_state_helper.c crtc->state = crtc_state; crtc_state 92 drivers/gpu/drm/drm_atomic_state_helper.c struct drm_crtc_state *crtc_state = crtc_state 98 drivers/gpu/drm/drm_atomic_state_helper.c __drm_atomic_helper_crtc_reset(crtc, crtc_state); crtc_state 181 drivers/gpu/drm/drm_atomic_uapi.c struct drm_crtc_state *crtc_state; crtc_state 186 drivers/gpu/drm/drm_atomic_uapi.c crtc_state = drm_atomic_get_crtc_state(plane_state->state, crtc_state 188 drivers/gpu/drm/drm_atomic_uapi.c if (WARN_ON(IS_ERR(crtc_state))) crtc_state 189 drivers/gpu/drm/drm_atomic_uapi.c return PTR_ERR(crtc_state); crtc_state 191 drivers/gpu/drm/drm_atomic_uapi.c crtc_state->plane_mask &= ~drm_plane_mask(plane); crtc_state 197 drivers/gpu/drm/drm_atomic_uapi.c crtc_state = drm_atomic_get_crtc_state(plane_state->state, crtc_state 199 drivers/gpu/drm/drm_atomic_uapi.c if (IS_ERR(crtc_state)) crtc_state 200 drivers/gpu/drm/drm_atomic_uapi.c return PTR_ERR(crtc_state); crtc_state 201 drivers/gpu/drm/drm_atomic_uapi.c crtc_state->plane_mask |= drm_plane_mask(plane); crtc_state 300 drivers/gpu/drm/drm_atomic_uapi.c struct drm_crtc_state *crtc_state; crtc_state 306 drivers/gpu/drm/drm_atomic_uapi.c crtc_state = drm_atomic_get_new_crtc_state(conn_state->state, crtc_state 309 drivers/gpu/drm/drm_atomic_uapi.c crtc_state->connector_mask &= crtc_state 317 drivers/gpu/drm/drm_atomic_uapi.c crtc_state = drm_atomic_get_crtc_state(conn_state->state, crtc); crtc_state 318 drivers/gpu/drm/drm_atomic_uapi.c if (IS_ERR(crtc_state)) crtc_state 319 drivers/gpu/drm/drm_atomic_uapi.c return PTR_ERR(crtc_state); crtc_state 321 drivers/gpu/drm/drm_atomic_uapi.c crtc_state->connector_mask |= crtc_state 919 drivers/gpu/drm/drm_atomic_uapi.c struct drm_crtc_state *crtc_state; crtc_state 939 drivers/gpu/drm/drm_atomic_uapi.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 940 drivers/gpu/drm/drm_atomic_uapi.c if (IS_ERR(crtc_state)) { crtc_state 941 drivers/gpu/drm/drm_atomic_uapi.c ret = PTR_ERR(crtc_state); crtc_state 954 drivers/gpu/drm/drm_atomic_uapi.c crtc_state->active = active; crtc_state 992 drivers/gpu/drm/drm_atomic_uapi.c struct drm_crtc_state *crtc_state; crtc_state 994 drivers/gpu/drm/drm_atomic_uapi.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 995 drivers/gpu/drm/drm_atomic_uapi.c if (IS_ERR(crtc_state)) { crtc_state 996 drivers/gpu/drm/drm_atomic_uapi.c ret = PTR_ERR(crtc_state); crtc_state 1001 drivers/gpu/drm/drm_atomic_uapi.c crtc_state, prop, prop_value); crtc_state 1111 drivers/gpu/drm/drm_atomic_uapi.c struct drm_crtc_state *crtc_state; crtc_state 1119 drivers/gpu/drm/drm_atomic_uapi.c for_each_new_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 1122 drivers/gpu/drm/drm_atomic_uapi.c fence_ptr = get_out_fence_for_crtc(crtc_state->state, crtc); crtc_state 1131 drivers/gpu/drm/drm_atomic_uapi.c crtc_state->event = e; crtc_state 1135 drivers/gpu/drm/drm_atomic_uapi.c struct drm_pending_vblank_event *e = crtc_state->event; crtc_state 1144 drivers/gpu/drm/drm_atomic_uapi.c crtc_state->event = NULL; crtc_state 1173 drivers/gpu/drm/drm_atomic_uapi.c crtc_state->event->base.fence = fence; crtc_state 1233 drivers/gpu/drm/drm_atomic_uapi.c struct drm_crtc_state *crtc_state; crtc_state 1245 drivers/gpu/drm/drm_atomic_uapi.c for_each_new_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 1246 drivers/gpu/drm/drm_atomic_uapi.c struct drm_pending_vblank_event *event = crtc_state->event; crtc_state 1254 drivers/gpu/drm/drm_atomic_uapi.c crtc_state->event = NULL; crtc_state 423 drivers/gpu/drm/drm_blend.c struct drm_crtc_state *crtc_state) crtc_state 425 drivers/gpu/drm/drm_blend.c struct drm_atomic_state *state = crtc_state->state; crtc_state 444 drivers/gpu/drm/drm_blend.c drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) { crtc_state 466 drivers/gpu/drm/drm_blend.c crtc_state->zpos_changed = true; crtc_state 959 drivers/gpu/drm/drm_client_modeset.c struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); crtc_state 961 drivers/gpu/drm/drm_client_modeset.c crtc_state->active = false; crtc_state 123 drivers/gpu/drm/drm_damage_helper.c struct drm_crtc_state *crtc_state; crtc_state 126 drivers/gpu/drm/drm_damage_helper.c crtc_state = drm_atomic_get_new_crtc_state(state, crtc_state 129 drivers/gpu/drm/drm_damage_helper.c if (WARN_ON(!crtc_state)) crtc_state 132 drivers/gpu/drm/drm_damage_helper.c if (drm_atomic_crtc_needs_modeset(crtc_state)) { crtc_state 1037 drivers/gpu/drm/drm_fb_helper.c struct drm_crtc_state *crtc_state; crtc_state 1066 drivers/gpu/drm/drm_fb_helper.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 1067 drivers/gpu/drm/drm_fb_helper.c if (IS_ERR(crtc_state)) { crtc_state 1068 drivers/gpu/drm/drm_fb_helper.c ret = PTR_ERR(crtc_state); crtc_state 1072 drivers/gpu/drm/drm_fb_helper.c replaced = drm_property_replace_blob(&crtc_state->degamma_lut, crtc_state 1074 drivers/gpu/drm/drm_fb_helper.c replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL); crtc_state 1075 drivers/gpu/drm/drm_fb_helper.c replaced |= drm_property_replace_blob(&crtc_state->gamma_lut, crtc_state 1077 drivers/gpu/drm/drm_fb_helper.c crtc_state->color_mgmt_changed |= replaced; crtc_state 873 drivers/gpu/drm/drm_framebuffer.c struct drm_crtc_state *crtc_state; crtc_state 875 drivers/gpu/drm/drm_framebuffer.c crtc_state = drm_atomic_get_existing_crtc_state(state, plane_state->crtc); crtc_state 881 drivers/gpu/drm/drm_framebuffer.c crtc_state->active = false; crtc_state 882 drivers/gpu/drm/drm_framebuffer.c ret = drm_atomic_set_mode_for_crtc(crtc_state, NULL); crtc_state 332 drivers/gpu/drm/drm_mipi_dbi.c struct drm_crtc_state *crtc_state, crtc_state 128 drivers/gpu/drm/drm_plane_helper.c struct drm_crtc_state crtc_state = { crtc_state 135 drivers/gpu/drm/drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 78 drivers/gpu/drm/drm_self_refresh_helper.c struct drm_crtc_state *crtc_state; crtc_state 92 drivers/gpu/drm/drm_self_refresh_helper.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 93 drivers/gpu/drm/drm_self_refresh_helper.c if (IS_ERR(crtc_state)) { crtc_state 94 drivers/gpu/drm/drm_self_refresh_helper.c ret = PTR_ERR(crtc_state); crtc_state 98 drivers/gpu/drm/drm_self_refresh_helper.c if (!crtc_state->enable) crtc_state 110 drivers/gpu/drm/drm_self_refresh_helper.c crtc_state->active = false; crtc_state 111 drivers/gpu/drm/drm_self_refresh_helper.c crtc_state->self_refresh_active = true; crtc_state 190 drivers/gpu/drm/drm_self_refresh_helper.c struct drm_crtc_state *crtc_state; crtc_state 194 drivers/gpu/drm/drm_self_refresh_helper.c for_each_old_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 195 drivers/gpu/drm/drm_self_refresh_helper.c if (crtc_state->self_refresh_active) { crtc_state 203 drivers/gpu/drm/drm_self_refresh_helper.c for_each_new_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 208 drivers/gpu/drm/drm_self_refresh_helper.c if (crtc_state->self_refresh_active) crtc_state 131 drivers/gpu/drm/drm_simple_kms_helper.c struct drm_crtc_state *crtc_state; crtc_state 135 drivers/gpu/drm/drm_simple_kms_helper.c crtc_state = drm_atomic_get_new_crtc_state(plane_state->state, crtc_state 138 drivers/gpu/drm/drm_simple_kms_helper.c ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, crtc_state 151 drivers/gpu/drm/drm_simple_kms_helper.c return pipe->funcs->check(pipe, plane_state, crtc_state); crtc_state 59 drivers/gpu/drm/exynos/exynos_drm_plane.c struct drm_crtc_state *crtc_state = crtc_state 61 drivers/gpu/drm/exynos/exynos_drm_plane.c struct drm_display_mode *mode = &crtc_state->adjusted_mode; crtc_state 499 drivers/gpu/drm/gma500/gma_display.c kfree(gma_crtc->crtc_state); crtc_state 529 drivers/gpu/drm/gma500/gma_display.c struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; crtc_state 534 drivers/gpu/drm/gma500/gma_display.c if (!crtc_state) { crtc_state 539 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDSPCNTR = REG_READ(map->cntr); crtc_state 540 drivers/gpu/drm/gma500/gma_display.c crtc_state->savePIPECONF = REG_READ(map->conf); crtc_state 541 drivers/gpu/drm/gma500/gma_display.c crtc_state->savePIPESRC = REG_READ(map->src); crtc_state 542 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveFP0 = REG_READ(map->fp0); crtc_state 543 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveFP1 = REG_READ(map->fp1); crtc_state 544 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDPLL = REG_READ(map->dpll); crtc_state 545 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveHTOTAL = REG_READ(map->htotal); crtc_state 546 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveHBLANK = REG_READ(map->hblank); crtc_state 547 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveHSYNC = REG_READ(map->hsync); crtc_state 548 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveVTOTAL = REG_READ(map->vtotal); crtc_state 549 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveVBLANK = REG_READ(map->vblank); crtc_state 550 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveVSYNC = REG_READ(map->vsync); crtc_state 551 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDSPSTRIDE = REG_READ(map->stride); crtc_state 554 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDSPSIZE = REG_READ(map->size); crtc_state 555 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDSPPOS = REG_READ(map->pos); crtc_state 557 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDSPBASE = REG_READ(map->base); crtc_state 561 drivers/gpu/drm/gma500/gma_display.c crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2)); crtc_state 572 drivers/gpu/drm/gma500/gma_display.c struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; crtc_state 577 drivers/gpu/drm/gma500/gma_display.c if (!crtc_state) { crtc_state 582 drivers/gpu/drm/gma500/gma_display.c if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { crtc_state 584 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); crtc_state 589 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->fp0, crtc_state->saveFP0); crtc_state 592 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->fp1, crtc_state->saveFP1); crtc_state 595 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->dpll, crtc_state->saveDPLL); crtc_state 599 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->htotal, crtc_state->saveHTOTAL); crtc_state 600 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->hblank, crtc_state->saveHBLANK); crtc_state 601 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->hsync, crtc_state->saveHSYNC); crtc_state 602 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); crtc_state 603 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->vblank, crtc_state->saveVBLANK); crtc_state 604 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->vsync, crtc_state->saveVSYNC); crtc_state 605 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); crtc_state 607 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->size, crtc_state->saveDSPSIZE); crtc_state 608 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->pos, crtc_state->saveDSPPOS); crtc_state 610 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->src, crtc_state->savePIPESRC); crtc_state 611 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->base, crtc_state->saveDSPBASE); crtc_state 612 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->conf, crtc_state->savePIPECONF); crtc_state 616 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); crtc_state 617 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->base, crtc_state->saveDSPBASE); crtc_state 623 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]); crtc_state 492 drivers/gpu/drm/gma500/psb_intel_display.c gma_crtc->crtc_state = crtc_state 494 drivers/gpu/drm/gma500/psb_intel_display.c if (!gma_crtc->crtc_state) { crtc_state 182 drivers/gpu/drm/gma500/psb_intel_drv.h struct psb_intel_crtc_state *crtc_state; crtc_state 62 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c struct drm_crtc_state *crtc_state; crtc_state 69 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c crtc_state = drm_atomic_get_crtc_state(state->state, crtc); crtc_state 70 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c if (IS_ERR(crtc_state)) crtc_state 71 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c return PTR_ERR(crtc_state); crtc_state 84 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c crtc_state->adjusted_mode.hdisplay || crtc_state 86 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c crtc_state->adjusted_mode.vdisplay) { crtc_state 683 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c struct drm_crtc_state *crtc_state, crtc_state 765 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c struct drm_crtc_state *crtc_state; crtc_state 783 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c crtc_state = drm_atomic_get_crtc_state(state->state, crtc); crtc_state 784 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c if (IS_ERR(crtc_state)) crtc_state 785 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c return PTR_ERR(crtc_state); crtc_state 798 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay || crtc_state 799 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay) crtc_state 592 drivers/gpu/drm/i915/display/icl_dsi.c const struct intel_crtc_state *crtc_state) crtc_state 596 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_shared_dpll *pll = crtc_state->shared_dpll; crtc_state 1293 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_crtc_state *crtc_state) crtc_state 129 drivers/gpu/drm/i915/display/intel_atomic.c struct drm_crtc_state *crtc_state; crtc_state 136 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); crtc_state 150 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->mode_changed = true; crtc_state 189 drivers/gpu/drm/i915/display/intel_atomic.c struct intel_crtc_state *crtc_state; crtc_state 191 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL); crtc_state 192 drivers/gpu/drm/i915/display/intel_atomic.c if (!crtc_state) crtc_state 195 drivers/gpu/drm/i915/display/intel_atomic.c __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base); crtc_state 197 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->update_pipe = false; crtc_state 198 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->disable_lp_wm = false; crtc_state 199 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->disable_cxsr = false; crtc_state 200 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->update_wm_pre = false; crtc_state 201 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->update_wm_post = false; crtc_state 202 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->fb_changed = false; crtc_state 203 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->fifo_changed = false; crtc_state 204 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->preload_luts = false; crtc_state 205 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->wm.need_postvbl_update = false; crtc_state 206 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->fb_bits = 0; crtc_state 207 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->update_planes = 0; crtc_state 209 drivers/gpu/drm/i915/display/intel_atomic.c return &crtc_state->base; crtc_state 313 drivers/gpu/drm/i915/display/intel_atomic.c struct intel_crtc_state *crtc_state) crtc_state 319 drivers/gpu/drm/i915/display/intel_atomic.c &crtc_state->scaler_state; crtc_state 320 drivers/gpu/drm/i915/display/intel_atomic.c struct drm_atomic_state *drm_state = crtc_state->base.state; crtc_state 388 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->base.planes_changed = true; crtc_state 435 drivers/gpu/drm/i915/display/intel_atomic.c struct drm_crtc_state *crtc_state; crtc_state 436 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); crtc_state 437 drivers/gpu/drm/i915/display/intel_atomic.c if (IS_ERR(crtc_state)) crtc_state 438 drivers/gpu/drm/i915/display/intel_atomic.c return ERR_CAST(crtc_state); crtc_state 440 drivers/gpu/drm/i915/display/intel_atomic.c return to_intel_crtc_state(crtc_state); crtc_state 47 drivers/gpu/drm/i915/display/intel_atomic.h struct intel_crtc_state *crtc_state); crtc_state 118 drivers/gpu/drm/i915/display/intel_atomic_plane.c unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state, crtc_state 138 drivers/gpu/drm/i915/display/intel_atomic_plane.c return cpp * crtc_state->pixel_rate; crtc_state 232 drivers/gpu/drm/i915/display/intel_atomic_plane.c struct intel_crtc_state *crtc_state = crtc_state 248 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], crtc_state 251 drivers/gpu/drm/i915/display/intel_atomic_plane.c skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id], crtc_state 257 drivers/gpu/drm/i915/display/intel_atomic_plane.c entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; crtc_state 258 drivers/gpu/drm/i915/display/intel_atomic_plane.c entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id]; crtc_state 270 drivers/gpu/drm/i915/display/intel_atomic_plane.c const struct intel_crtc_state *crtc_state, crtc_state 273 drivers/gpu/drm/i915/display/intel_atomic_plane.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 276 drivers/gpu/drm/i915/display/intel_atomic_plane.c plane->update_plane(plane, crtc_state, plane_state); crtc_state 280 drivers/gpu/drm/i915/display/intel_atomic_plane.c const struct intel_crtc_state *crtc_state, crtc_state 283 drivers/gpu/drm/i915/display/intel_atomic_plane.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 286 drivers/gpu/drm/i915/display/intel_atomic_plane.c plane->update_slave(plane, crtc_state, plane_state); crtc_state 290 drivers/gpu/drm/i915/display/intel_atomic_plane.c const struct intel_crtc_state *crtc_state) crtc_state 292 drivers/gpu/drm/i915/display/intel_atomic_plane.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 295 drivers/gpu/drm/i915/display/intel_atomic_plane.c plane->disable_plane(plane, crtc_state); crtc_state 21 drivers/gpu/drm/i915/display/intel_atomic_plane.h unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state, crtc_state 24 drivers/gpu/drm/i915/display/intel_atomic_plane.h const struct intel_crtc_state *crtc_state, crtc_state 27 drivers/gpu/drm/i915/display/intel_atomic_plane.h const struct intel_crtc_state *crtc_state, crtc_state 30 drivers/gpu/drm/i915/display/intel_atomic_plane.h const struct intel_crtc_state *crtc_state); crtc_state 41 drivers/gpu/drm/i915/display/intel_atomic_plane.h struct intel_crtc_state *crtc_state, crtc_state 45 drivers/gpu/drm/i915/display/intel_atomic_plane.h struct intel_crtc_state *crtc_state, crtc_state 123 drivers/gpu/drm/i915/display/intel_audio.c audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) crtc_state 129 drivers/gpu/drm/i915/display/intel_audio.c crtc_state->port_clock == dp_aud_n_m[i].clock) crtc_state 233 drivers/gpu/drm/i915/display/intel_audio.c static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) crtc_state 236 drivers/gpu/drm/i915/display/intel_audio.c &crtc_state->base.adjusted_mode; crtc_state 257 drivers/gpu/drm/i915/display/intel_audio.c static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, crtc_state 263 drivers/gpu/drm/i915/display/intel_audio.c if (crtc_state->pipe_bpp == 36) { crtc_state 266 drivers/gpu/drm/i915/display/intel_audio.c } else if (crtc_state->pipe_bpp == 30) { crtc_state 276 drivers/gpu/drm/i915/display/intel_audio.c crtc_state->port_clock == hdmi_ncts_table[i].clock) { crtc_state 332 drivers/gpu/drm/i915/display/intel_audio.c const struct intel_crtc_state *crtc_state, crtc_state 373 drivers/gpu/drm/i915/display/intel_audio.c const struct intel_crtc_state *crtc_state) crtc_state 377 drivers/gpu/drm/i915/display/intel_audio.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 384 drivers/gpu/drm/i915/display/intel_audio.c nm = audio_config_dp_get_n_m(crtc_state, rate); crtc_state 420 drivers/gpu/drm/i915/display/intel_audio.c const struct intel_crtc_state *crtc_state) crtc_state 424 drivers/gpu/drm/i915/display/intel_audio.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 435 drivers/gpu/drm/i915/display/intel_audio.c tmp |= audio_config_hdmi_pixel_clock(crtc_state); crtc_state 437 drivers/gpu/drm/i915/display/intel_audio.c n = audio_config_hdmi_get_n(crtc_state, rate); crtc_state 462 drivers/gpu/drm/i915/display/intel_audio.c const struct intel_crtc_state *crtc_state) crtc_state 464 drivers/gpu/drm/i915/display/intel_audio.c if (intel_crtc_has_dp_encoder(crtc_state)) crtc_state 465 drivers/gpu/drm/i915/display/intel_audio.c hsw_dp_audio_config_update(encoder, crtc_state); crtc_state 467 drivers/gpu/drm/i915/display/intel_audio.c hsw_hdmi_audio_config_update(encoder, crtc_state); crtc_state 503 drivers/gpu/drm/i915/display/intel_audio.c const struct intel_crtc_state *crtc_state, crtc_state 508 drivers/gpu/drm/i915/display/intel_audio.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 547 drivers/gpu/drm/i915/display/intel_audio.c hsw_audio_config_update(encoder, crtc_state); crtc_state 599 drivers/gpu/drm/i915/display/intel_audio.c const struct intel_crtc_state *crtc_state, crtc_state 603 drivers/gpu/drm/i915/display/intel_audio.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 670 drivers/gpu/drm/i915/display/intel_audio.c if (intel_crtc_has_dp_encoder(crtc_state)) crtc_state 673 drivers/gpu/drm/i915/display/intel_audio.c tmp |= audio_config_hdmi_pixel_clock(crtc_state); crtc_state 687 drivers/gpu/drm/i915/display/intel_audio.c const struct intel_crtc_state *crtc_state, crtc_state 692 drivers/gpu/drm/i915/display/intel_audio.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 695 drivers/gpu/drm/i915/display/intel_audio.c &crtc_state->base.adjusted_mode; crtc_state 714 drivers/gpu/drm/i915/display/intel_audio.c crtc_state, crtc_state 727 drivers/gpu/drm/i915/display/intel_audio.c if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) crtc_state 734 drivers/gpu/drm/i915/display/intel_audio.c crtc_state->port_clock, crtc_state 735 drivers/gpu/drm/i915/display/intel_audio.c intel_crtc_has_dp_encoder(crtc_state)); crtc_state 16 drivers/gpu/drm/i915/display/intel_audio.h const struct intel_crtc_state *crtc_state, crtc_state 256 drivers/gpu/drm/i915/display/intel_bw.c static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state) crtc_state 262 drivers/gpu/drm/i915/display/intel_bw.c return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR)); crtc_state 265 drivers/gpu/drm/i915/display/intel_bw.c static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state) crtc_state 267 drivers/gpu/drm/i915/display/intel_bw.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 279 drivers/gpu/drm/i915/display/intel_bw.c data_rate += crtc_state->data_rate[plane_id]; crtc_state 286 drivers/gpu/drm/i915/display/intel_bw.c const struct intel_crtc_state *crtc_state) crtc_state 288 drivers/gpu/drm/i915/display/intel_bw.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 291 drivers/gpu/drm/i915/display/intel_bw.c intel_bw_crtc_data_rate(crtc_state); crtc_state 293 drivers/gpu/drm/i915/display/intel_bw.c intel_bw_crtc_num_active_planes(crtc_state); crtc_state 30 drivers/gpu/drm/i915/display/intel_bw.h const struct intel_crtc_state *crtc_state); crtc_state 2217 drivers/gpu/drm/i915/display/intel_cdclk.c int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) crtc_state 2220 drivers/gpu/drm/i915/display/intel_cdclk.c to_i915(crtc_state->base.crtc->dev); crtc_state 2223 drivers/gpu/drm/i915/display/intel_cdclk.c if (!crtc_state->base.enable) crtc_state 2226 drivers/gpu/drm/i915/display/intel_cdclk.c min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); crtc_state 2229 drivers/gpu/drm/i915/display/intel_cdclk.c if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) crtc_state 2237 drivers/gpu/drm/i915/display/intel_cdclk.c if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state 2238 drivers/gpu/drm/i915/display/intel_cdclk.c crtc_state->has_audio && crtc_state 2239 drivers/gpu/drm/i915/display/intel_cdclk.c crtc_state->port_clock >= 540000 && crtc_state 2240 drivers/gpu/drm/i915/display/intel_cdclk.c crtc_state->lane_count == 4) { crtc_state 2254 drivers/gpu/drm/i915/display/intel_cdclk.c if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) crtc_state 2265 drivers/gpu/drm/i915/display/intel_cdclk.c intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) crtc_state 2266 drivers/gpu/drm/i915/display/intel_cdclk.c min_cdclk = max(crtc_state->port_clock, min_cdclk); crtc_state 2272 drivers/gpu/drm/i915/display/intel_cdclk.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && crtc_state 2281 drivers/gpu/drm/i915/display/intel_cdclk.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && crtc_state 2298 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_crtc_state *crtc_state; crtc_state 2305 drivers/gpu/drm/i915/display/intel_cdclk.c for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 2306 drivers/gpu/drm/i915/display/intel_cdclk.c min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); crtc_state 2333 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_crtc_state *crtc_state; crtc_state 2341 drivers/gpu/drm/i915/display/intel_cdclk.c for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 2342 drivers/gpu/drm/i915/display/intel_cdclk.c if (crtc_state->base.enable) crtc_state 2344 drivers/gpu/drm/i915/display/intel_cdclk.c crtc_state->min_voltage_level; crtc_state 2420 drivers/gpu/drm/i915/display/intel_cdclk.c struct intel_crtc_state *crtc_state; crtc_state 2427 drivers/gpu/drm/i915/display/intel_cdclk.c for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 2428 drivers/gpu/drm/i915/display/intel_cdclk.c if (!crtc_state->base.enable) crtc_state 2431 drivers/gpu/drm/i915/display/intel_cdclk.c if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) crtc_state 2438 drivers/gpu/drm/i915/display/intel_cdclk.c switch (crtc_state->port_clock / 2) { crtc_state 18 drivers/gpu/drm/i915/display/intel_cdclk.h int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); crtc_state 102 drivers/gpu/drm/i915/display/intel_color.c static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state) crtc_state 104 drivers/gpu/drm/i915/display/intel_color.c return !crtc_state->base.degamma_lut && crtc_state 105 drivers/gpu/drm/i915/display/intel_color.c !crtc_state->base.ctm && crtc_state 106 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.gamma_lut && crtc_state 107 drivers/gpu/drm/i915/display/intel_color.c lut_is_legacy(crtc_state->base.gamma_lut); crtc_state 190 drivers/gpu/drm/i915/display/intel_color.c static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) crtc_state 192 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 198 drivers/gpu/drm/i915/display/intel_color.c return crtc_state->limited_color_range && crtc_state 203 drivers/gpu/drm/i915/display/intel_color.c static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state, crtc_state 206 drivers/gpu/drm/i915/display/intel_color.c const struct drm_color_ctm *ctm = crtc_state->base.ctm->data; crtc_state 211 drivers/gpu/drm/i915/display/intel_color.c if (ilk_csc_limited_range(crtc_state)) crtc_state 255 drivers/gpu/drm/i915/display/intel_color.c static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) crtc_state 257 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 259 drivers/gpu/drm/i915/display/intel_color.c bool limited_color_range = ilk_csc_limited_range(crtc_state); crtc_state 261 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.ctm) { crtc_state 264 drivers/gpu/drm/i915/display/intel_color.c ilk_csc_convert_ctm(crtc_state, coeff); crtc_state 269 drivers/gpu/drm/i915/display/intel_color.c } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { crtc_state 277 drivers/gpu/drm/i915/display/intel_color.c } else if (crtc_state->csc_enable) { crtc_state 291 drivers/gpu/drm/i915/display/intel_color.c I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode); crtc_state 294 drivers/gpu/drm/i915/display/intel_color.c static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) crtc_state 296 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 299 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.ctm) { crtc_state 302 drivers/gpu/drm/i915/display/intel_color.c ilk_csc_convert_ctm(crtc_state, coeff); crtc_state 307 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { crtc_state 311 drivers/gpu/drm/i915/display/intel_color.c } else if (crtc_state->limited_color_range) { crtc_state 317 drivers/gpu/drm/i915/display/intel_color.c I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode); crtc_state 323 drivers/gpu/drm/i915/display/intel_color.c static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state) crtc_state 325 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 329 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.ctm) { crtc_state 330 drivers/gpu/drm/i915/display/intel_color.c const struct drm_color_ctm *ctm = crtc_state->base.ctm->data; crtc_state 361 drivers/gpu/drm/i915/display/intel_color.c I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode); crtc_state 388 drivers/gpu/drm/i915/display/intel_color.c static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state, crtc_state 391 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 397 drivers/gpu/drm/i915/display/intel_color.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) crtc_state 420 drivers/gpu/drm/i915/display/intel_color.c static void i9xx_load_luts(const struct intel_crtc_state *crtc_state) crtc_state 422 drivers/gpu/drm/i915/display/intel_color.c i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut); crtc_state 425 drivers/gpu/drm/i915/display/intel_color.c static void i9xx_color_commit(const struct intel_crtc_state *crtc_state) crtc_state 427 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 434 drivers/gpu/drm/i915/display/intel_color.c val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); crtc_state 438 drivers/gpu/drm/i915/display/intel_color.c static void ilk_color_commit(const struct intel_crtc_state *crtc_state) crtc_state 440 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 447 drivers/gpu/drm/i915/display/intel_color.c val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); crtc_state 450 drivers/gpu/drm/i915/display/intel_color.c ilk_load_csc_matrix(crtc_state); crtc_state 453 drivers/gpu/drm/i915/display/intel_color.c static void hsw_color_commit(const struct intel_crtc_state *crtc_state) crtc_state 455 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 458 drivers/gpu/drm/i915/display/intel_color.c I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode); crtc_state 460 drivers/gpu/drm/i915/display/intel_color.c ilk_load_csc_matrix(crtc_state); crtc_state 463 drivers/gpu/drm/i915/display/intel_color.c static void skl_color_commit(const struct intel_crtc_state *crtc_state) crtc_state 465 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 475 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->gamma_enable) crtc_state 477 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->csc_enable) crtc_state 481 drivers/gpu/drm/i915/display/intel_color.c I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode); crtc_state 484 drivers/gpu/drm/i915/display/intel_color.c icl_load_csc_matrix(crtc_state); crtc_state 486 drivers/gpu/drm/i915/display/intel_color.c ilk_load_csc_matrix(crtc_state); crtc_state 509 drivers/gpu/drm/i915/display/intel_color.c static void i965_load_luts(const struct intel_crtc_state *crtc_state) crtc_state 511 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 512 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; crtc_state 514 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) crtc_state 515 drivers/gpu/drm/i915/display/intel_color.c i9xx_load_luts(crtc_state); crtc_state 532 drivers/gpu/drm/i915/display/intel_color.c static void ilk_load_luts(const struct intel_crtc_state *crtc_state) crtc_state 534 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 535 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; crtc_state 537 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) crtc_state 538 drivers/gpu/drm/i915/display/intel_color.c i9xx_load_luts(crtc_state); crtc_state 633 drivers/gpu/drm/i915/display/intel_color.c static void ivb_load_luts(const struct intel_crtc_state *crtc_state) crtc_state 635 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 636 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; crtc_state 637 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut; crtc_state 639 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) { crtc_state 640 drivers/gpu/drm/i915/display/intel_color.c i9xx_load_luts(crtc_state); crtc_state 641 drivers/gpu/drm/i915/display/intel_color.c } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { crtc_state 656 drivers/gpu/drm/i915/display/intel_color.c static void bdw_load_luts(const struct intel_crtc_state *crtc_state) crtc_state 658 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 659 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; crtc_state 660 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut; crtc_state 662 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) { crtc_state 663 drivers/gpu/drm/i915/display/intel_color.c i9xx_load_luts(crtc_state); crtc_state 664 drivers/gpu/drm/i915/display/intel_color.c } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { crtc_state 679 drivers/gpu/drm/i915/display/intel_color.c static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) crtc_state 681 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 685 drivers/gpu/drm/i915/display/intel_color.c const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data; crtc_state 718 drivers/gpu/drm/i915/display/intel_color.c static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state) crtc_state 720 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 745 drivers/gpu/drm/i915/display/intel_color.c static void glk_load_luts(const struct intel_crtc_state *crtc_state) crtc_state 747 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; crtc_state 748 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 758 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.degamma_lut) crtc_state 759 drivers/gpu/drm/i915/display/intel_color.c glk_load_degamma_lut(crtc_state); crtc_state 761 drivers/gpu/drm/i915/display/intel_color.c glk_load_degamma_lut_linear(crtc_state); crtc_state 763 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) { crtc_state 764 drivers/gpu/drm/i915/display/intel_color.c i9xx_load_luts(crtc_state); crtc_state 786 drivers/gpu/drm/i915/display/intel_color.c icl_load_gcmax(const struct intel_crtc_state *crtc_state, crtc_state 789 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 800 drivers/gpu/drm/i915/display/intel_color.c icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) crtc_state 802 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 804 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *blob = crtc_state->base.gamma_lut; crtc_state 829 drivers/gpu/drm/i915/display/intel_color.c icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) crtc_state 831 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 833 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *blob = crtc_state->base.gamma_lut; crtc_state 877 drivers/gpu/drm/i915/display/intel_color.c icl_load_gcmax(crtc_state, entry); crtc_state 881 drivers/gpu/drm/i915/display/intel_color.c static void icl_load_luts(const struct intel_crtc_state *crtc_state) crtc_state 883 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; crtc_state 884 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 886 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.degamma_lut) crtc_state 887 drivers/gpu/drm/i915/display/intel_color.c glk_load_degamma_lut(crtc_state); crtc_state 889 drivers/gpu/drm/i915/display/intel_color.c switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { crtc_state 891 drivers/gpu/drm/i915/display/intel_color.c i9xx_load_luts(crtc_state); crtc_state 895 drivers/gpu/drm/i915/display/intel_color.c icl_program_gamma_superfine_segment(crtc_state); crtc_state 896 drivers/gpu/drm/i915/display/intel_color.c icl_program_gamma_multi_segment(crtc_state); crtc_state 959 drivers/gpu/drm/i915/display/intel_color.c static void chv_load_luts(const struct intel_crtc_state *crtc_state) crtc_state 961 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 962 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; crtc_state 963 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut; crtc_state 965 drivers/gpu/drm/i915/display/intel_color.c cherryview_load_csc_matrix(crtc_state); crtc_state 967 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state_is_legacy_gamma(crtc_state)) { crtc_state 968 drivers/gpu/drm/i915/display/intel_color.c i9xx_load_luts(crtc_state); crtc_state 979 drivers/gpu/drm/i915/display/intel_color.c void intel_color_load_luts(const struct intel_crtc_state *crtc_state) crtc_state 981 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 983 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.load_luts(crtc_state); crtc_state 986 drivers/gpu/drm/i915/display/intel_color.c void intel_color_commit(const struct intel_crtc_state *crtc_state) crtc_state 988 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 990 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.color_commit(crtc_state); crtc_state 1042 drivers/gpu/drm/i915/display/intel_color.c int intel_color_check(struct intel_crtc_state *crtc_state) crtc_state 1044 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 1046 drivers/gpu/drm/i915/display/intel_color.c return dev_priv->display.color_check(crtc_state); crtc_state 1049 drivers/gpu/drm/i915/display/intel_color.c void intel_color_get_config(struct intel_crtc_state *crtc_state) crtc_state 1051 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 1054 drivers/gpu/drm/i915/display/intel_color.c dev_priv->display.read_luts(crtc_state); crtc_state 1058 drivers/gpu/drm/i915/display/intel_color.c const struct intel_crtc_state *crtc_state) crtc_state 1067 drivers/gpu/drm/i915/display/intel_color.c return crtc_state->active_planes & BIT(plane->id) || crtc_state 1124 drivers/gpu/drm/i915/display/intel_color.c static int check_luts(const struct intel_crtc_state *crtc_state) crtc_state 1126 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 1127 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; crtc_state 1128 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut; crtc_state 1133 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state_is_legacy_gamma(crtc_state)) crtc_state 1137 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->c8_planes) { crtc_state 1158 drivers/gpu/drm/i915/display/intel_color.c static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state) crtc_state 1160 drivers/gpu/drm/i915/display/intel_color.c if (!crtc_state->gamma_enable || crtc_state 1161 drivers/gpu/drm/i915/display/intel_color.c crtc_state_is_legacy_gamma(crtc_state)) crtc_state 1167 drivers/gpu/drm/i915/display/intel_color.c static int i9xx_color_check(struct intel_crtc_state *crtc_state) crtc_state 1171 drivers/gpu/drm/i915/display/intel_color.c ret = check_luts(crtc_state); crtc_state 1175 drivers/gpu/drm/i915/display/intel_color.c crtc_state->gamma_enable = crtc_state 1176 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.gamma_lut && crtc_state 1177 drivers/gpu/drm/i915/display/intel_color.c !crtc_state->c8_planes; crtc_state 1179 drivers/gpu/drm/i915/display/intel_color.c crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); crtc_state 1181 drivers/gpu/drm/i915/display/intel_color.c ret = intel_color_add_affected_planes(crtc_state); crtc_state 1185 drivers/gpu/drm/i915/display/intel_color.c crtc_state->preload_luts = intel_can_preload_luts(crtc_state); crtc_state 1190 drivers/gpu/drm/i915/display/intel_color.c static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) crtc_state 1194 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state_is_legacy_gamma(crtc_state)) crtc_state 1197 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.degamma_lut) crtc_state 1199 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.ctm) crtc_state 1201 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.gamma_lut) crtc_state 1215 drivers/gpu/drm/i915/display/intel_color.c static int chv_color_check(struct intel_crtc_state *crtc_state) crtc_state 1219 drivers/gpu/drm/i915/display/intel_color.c ret = check_luts(crtc_state); crtc_state 1227 drivers/gpu/drm/i915/display/intel_color.c crtc_state->gamma_enable = crtc_state 1228 drivers/gpu/drm/i915/display/intel_color.c crtc_state_is_legacy_gamma(crtc_state) && crtc_state 1229 drivers/gpu/drm/i915/display/intel_color.c !crtc_state->c8_planes; crtc_state 1231 drivers/gpu/drm/i915/display/intel_color.c crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; crtc_state 1233 drivers/gpu/drm/i915/display/intel_color.c crtc_state->cgm_mode = chv_cgm_mode(crtc_state); crtc_state 1235 drivers/gpu/drm/i915/display/intel_color.c ret = intel_color_add_affected_planes(crtc_state); crtc_state 1239 drivers/gpu/drm/i915/display/intel_color.c crtc_state->preload_luts = chv_can_preload_luts(crtc_state); crtc_state 1244 drivers/gpu/drm/i915/display/intel_color.c static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state) crtc_state 1246 drivers/gpu/drm/i915/display/intel_color.c if (!crtc_state->gamma_enable || crtc_state 1247 drivers/gpu/drm/i915/display/intel_color.c crtc_state_is_legacy_gamma(crtc_state)) crtc_state 1253 drivers/gpu/drm/i915/display/intel_color.c static int ilk_color_check(struct intel_crtc_state *crtc_state) crtc_state 1257 drivers/gpu/drm/i915/display/intel_color.c ret = check_luts(crtc_state); crtc_state 1261 drivers/gpu/drm/i915/display/intel_color.c crtc_state->gamma_enable = crtc_state 1262 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.gamma_lut && crtc_state 1263 drivers/gpu/drm/i915/display/intel_color.c !crtc_state->c8_planes; crtc_state 1270 drivers/gpu/drm/i915/display/intel_color.c crtc_state->csc_enable = false; crtc_state 1272 drivers/gpu/drm/i915/display/intel_color.c crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); crtc_state 1274 drivers/gpu/drm/i915/display/intel_color.c crtc_state->csc_mode = 0; crtc_state 1276 drivers/gpu/drm/i915/display/intel_color.c ret = intel_color_add_affected_planes(crtc_state); crtc_state 1280 drivers/gpu/drm/i915/display/intel_color.c crtc_state->preload_luts = intel_can_preload_luts(crtc_state); crtc_state 1285 drivers/gpu/drm/i915/display/intel_color.c static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state) crtc_state 1287 drivers/gpu/drm/i915/display/intel_color.c if (!crtc_state->gamma_enable || crtc_state 1288 drivers/gpu/drm/i915/display/intel_color.c crtc_state_is_legacy_gamma(crtc_state)) crtc_state 1290 drivers/gpu/drm/i915/display/intel_color.c else if (crtc_state->base.gamma_lut && crtc_state 1291 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.degamma_lut) crtc_state 1297 drivers/gpu/drm/i915/display/intel_color.c static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state) crtc_state 1299 drivers/gpu/drm/i915/display/intel_color.c bool limited_color_range = ilk_csc_limited_range(crtc_state); crtc_state 1305 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.degamma_lut || crtc_state 1306 drivers/gpu/drm/i915/display/intel_color.c crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || crtc_state 1313 drivers/gpu/drm/i915/display/intel_color.c static int ivb_color_check(struct intel_crtc_state *crtc_state) crtc_state 1315 drivers/gpu/drm/i915/display/intel_color.c bool limited_color_range = ilk_csc_limited_range(crtc_state); crtc_state 1318 drivers/gpu/drm/i915/display/intel_color.c ret = check_luts(crtc_state); crtc_state 1322 drivers/gpu/drm/i915/display/intel_color.c crtc_state->gamma_enable = crtc_state 1323 drivers/gpu/drm/i915/display/intel_color.c (crtc_state->base.gamma_lut || crtc_state 1324 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.degamma_lut) && crtc_state 1325 drivers/gpu/drm/i915/display/intel_color.c !crtc_state->c8_planes; crtc_state 1327 drivers/gpu/drm/i915/display/intel_color.c crtc_state->csc_enable = crtc_state 1328 drivers/gpu/drm/i915/display/intel_color.c crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || crtc_state 1329 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.ctm || limited_color_range; crtc_state 1331 drivers/gpu/drm/i915/display/intel_color.c crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); crtc_state 1333 drivers/gpu/drm/i915/display/intel_color.c crtc_state->csc_mode = ivb_csc_mode(crtc_state); crtc_state 1335 drivers/gpu/drm/i915/display/intel_color.c ret = intel_color_add_affected_planes(crtc_state); crtc_state 1339 drivers/gpu/drm/i915/display/intel_color.c crtc_state->preload_luts = intel_can_preload_luts(crtc_state); crtc_state 1344 drivers/gpu/drm/i915/display/intel_color.c static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state) crtc_state 1346 drivers/gpu/drm/i915/display/intel_color.c if (!crtc_state->gamma_enable || crtc_state 1347 drivers/gpu/drm/i915/display/intel_color.c crtc_state_is_legacy_gamma(crtc_state)) crtc_state 1353 drivers/gpu/drm/i915/display/intel_color.c static int glk_color_check(struct intel_crtc_state *crtc_state) crtc_state 1357 drivers/gpu/drm/i915/display/intel_color.c ret = check_luts(crtc_state); crtc_state 1361 drivers/gpu/drm/i915/display/intel_color.c crtc_state->gamma_enable = crtc_state 1362 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.gamma_lut && crtc_state 1363 drivers/gpu/drm/i915/display/intel_color.c !crtc_state->c8_planes; crtc_state 1366 drivers/gpu/drm/i915/display/intel_color.c crtc_state->csc_enable = crtc_state 1367 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.degamma_lut || crtc_state 1368 drivers/gpu/drm/i915/display/intel_color.c crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || crtc_state 1369 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.ctm || crtc_state->limited_color_range; crtc_state 1371 drivers/gpu/drm/i915/display/intel_color.c crtc_state->gamma_mode = glk_gamma_mode(crtc_state); crtc_state 1373 drivers/gpu/drm/i915/display/intel_color.c crtc_state->csc_mode = 0; crtc_state 1375 drivers/gpu/drm/i915/display/intel_color.c ret = intel_color_add_affected_planes(crtc_state); crtc_state 1379 drivers/gpu/drm/i915/display/intel_color.c crtc_state->preload_luts = glk_can_preload_luts(crtc_state); crtc_state 1384 drivers/gpu/drm/i915/display/intel_color.c static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) crtc_state 1388 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.degamma_lut) crtc_state 1391 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.gamma_lut && crtc_state 1392 drivers/gpu/drm/i915/display/intel_color.c !crtc_state->c8_planes) crtc_state 1395 drivers/gpu/drm/i915/display/intel_color.c if (!crtc_state->base.gamma_lut || crtc_state 1396 drivers/gpu/drm/i915/display/intel_color.c crtc_state_is_legacy_gamma(crtc_state)) crtc_state 1404 drivers/gpu/drm/i915/display/intel_color.c static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state) crtc_state 1408 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.ctm) crtc_state 1411 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || crtc_state 1412 drivers/gpu/drm/i915/display/intel_color.c crtc_state->limited_color_range) crtc_state 1418 drivers/gpu/drm/i915/display/intel_color.c static int icl_color_check(struct intel_crtc_state *crtc_state) crtc_state 1422 drivers/gpu/drm/i915/display/intel_color.c ret = check_luts(crtc_state); crtc_state 1426 drivers/gpu/drm/i915/display/intel_color.c crtc_state->gamma_mode = icl_gamma_mode(crtc_state); crtc_state 1428 drivers/gpu/drm/i915/display/intel_color.c crtc_state->csc_mode = icl_csc_mode(crtc_state); crtc_state 1430 drivers/gpu/drm/i915/display/intel_color.c crtc_state->preload_luts = intel_can_preload_luts(crtc_state); crtc_state 13 drivers/gpu/drm/i915/display/intel_color.h int intel_color_check(struct intel_crtc_state *crtc_state); crtc_state 14 drivers/gpu/drm/i915/display/intel_color.h void intel_color_commit(const struct intel_crtc_state *crtc_state); crtc_state 15 drivers/gpu/drm/i915/display/intel_color.h void intel_color_load_luts(const struct intel_crtc_state *crtc_state); crtc_state 16 drivers/gpu/drm/i915/display/intel_color.h void intel_color_get_config(struct intel_crtc_state *crtc_state); crtc_state 159 drivers/gpu/drm/i915/display/intel_crt.c const struct intel_crtc_state *crtc_state, crtc_state 164 drivers/gpu/drm/i915/display/intel_crt.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 165 drivers/gpu/drm/i915/display/intel_crt.c const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; crtc_state 259 drivers/gpu/drm/i915/display/intel_crt.c const struct intel_crtc_state *crtc_state, crtc_state 264 drivers/gpu/drm/i915/display/intel_crt.c WARN_ON(!crtc_state->has_pch_encoder); crtc_state 270 drivers/gpu/drm/i915/display/intel_crt.c const struct intel_crtc_state *crtc_state, crtc_state 274 drivers/gpu/drm/i915/display/intel_crt.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 277 drivers/gpu/drm/i915/display/intel_crt.c WARN_ON(!crtc_state->has_pch_encoder); crtc_state 281 drivers/gpu/drm/i915/display/intel_crt.c dev_priv->display.fdi_link_train(crtc, crtc_state); crtc_state 283 drivers/gpu/drm/i915/display/intel_crt.c intel_ddi_enable_pipe_clock(crtc_state); crtc_state 287 drivers/gpu/drm/i915/display/intel_crt.c const struct intel_crtc_state *crtc_state, crtc_state 291 drivers/gpu/drm/i915/display/intel_crt.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 294 drivers/gpu/drm/i915/display/intel_crt.c WARN_ON(!crtc_state->has_pch_encoder); crtc_state 296 drivers/gpu/drm/i915/display/intel_crt.c intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); crtc_state 305 drivers/gpu/drm/i915/display/intel_crt.c const struct intel_crtc_state *crtc_state, crtc_state 308 drivers/gpu/drm/i915/display/intel_crt.c intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); crtc_state 920 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state) crtc_state 928 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) crtc_state 931 drivers/gpu/drm/i915/display/intel_ddi.c else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) crtc_state 1020 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state) crtc_state 1022 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_shared_dpll *pll = crtc_state->shared_dpll; crtc_state 1023 drivers/gpu/drm/i915/display/intel_ddi.c int clock = crtc_state->port_clock; crtc_state 1066 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state) crtc_state 1075 drivers/gpu/drm/i915/display/intel_ddi.c intel_prepare_dp_ddi_buffers(encoder, crtc_state); crtc_state 1092 drivers/gpu/drm/i915/display/intel_ddi.c FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); crtc_state 1102 drivers/gpu/drm/i915/display/intel_ddi.c ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); crtc_state 1122 drivers/gpu/drm/i915/display/intel_ddi.c ((crtc_state->fdi_lanes - 1) << 1) | crtc_state 1695 drivers/gpu/drm/i915/display/intel_ddi.c void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state) crtc_state 1697 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1699 drivers/gpu/drm/i915/display/intel_ddi.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 1702 drivers/gpu/drm/i915/display/intel_ddi.c if (!intel_crtc_has_dp_encoder(crtc_state)) crtc_state 1709 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->limited_color_range) crtc_state 1712 drivers/gpu/drm/i915/display/intel_ddi.c switch (crtc_state->pipe_bpp) { crtc_state 1726 drivers/gpu/drm/i915/display/intel_ddi.c MISSING_CASE(crtc_state->pipe_bpp); crtc_state 1735 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) crtc_state 1743 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) crtc_state 1748 drivers/gpu/drm/i915/display/intel_ddi.c void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, crtc_state 1751 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1753 drivers/gpu/drm/i915/display/intel_ddi.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 1764 drivers/gpu/drm/i915/display/intel_ddi.c void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) crtc_state 1766 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1770 drivers/gpu/drm/i915/display/intel_ddi.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 1781 drivers/gpu/drm/i915/display/intel_ddi.c switch (crtc_state->pipe_bpp) { crtc_state 1798 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) crtc_state 1800 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) crtc_state 1810 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->pch_pfit.force_thru) crtc_state 1827 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { crtc_state 1828 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->has_hdmi_sink) crtc_state 1833 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->hdmi_scrambling) crtc_state 1835 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->hdmi_high_tmds_clock_ratio) crtc_state 1837 drivers/gpu/drm/i915/display/intel_ddi.c } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { crtc_state 1839 drivers/gpu/drm/i915/display/intel_ddi.c temp |= (crtc_state->fdi_lanes - 1) << 1; crtc_state 1840 drivers/gpu/drm/i915/display/intel_ddi.c } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { crtc_state 1842 drivers/gpu/drm/i915/display/intel_ddi.c temp |= DDI_PORT_WIDTH(crtc_state->lane_count); crtc_state 1845 drivers/gpu/drm/i915/display/intel_ddi.c temp |= DDI_PORT_WIDTH(crtc_state->lane_count); crtc_state 1851 drivers/gpu/drm/i915/display/intel_ddi.c void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) crtc_state 1853 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1855 drivers/gpu/drm/i915/display/intel_ddi.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 1869 drivers/gpu/drm/i915/display/intel_ddi.c intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { crtc_state 2112 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *crtc_state) crtc_state 2123 drivers/gpu/drm/i915/display/intel_ddi.c if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) crtc_state 2137 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_crtc_has_dp_encoder(crtc_state) || crtc_state 2145 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->dsc_params.compression_enable) crtc_state 2147 drivers/gpu/drm/i915/display/intel_ddi.c intel_dsc_power_domain(crtc_state)); crtc_state 2150 drivers/gpu/drm/i915/display/intel_ddi.c void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) crtc_state 2152 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 2156 drivers/gpu/drm/i915/display/intel_ddi.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 2168 drivers/gpu/drm/i915/display/intel_ddi.c void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) crtc_state 2170 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 2171 drivers/gpu/drm/i915/display/intel_ddi.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 2790 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state) crtc_state 2793 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_shared_dpll *pll = crtc_state->shared_dpll; crtc_state 2919 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state) crtc_state 2925 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_shared_dpll *pll = crtc_state->shared_dpll; crtc_state 2935 drivers/gpu/drm/i915/display/intel_ddi.c icl_pll_to_ddi_clk_sel(encoder, crtc_state)); crtc_state 3123 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state) crtc_state 3125 drivers/gpu/drm/i915/display/intel_ddi.c if (!crtc_state->fec_enable) crtc_state 3133 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state) crtc_state 3139 drivers/gpu/drm/i915/display/intel_ddi.c if (!crtc_state->fec_enable) crtc_state 3152 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state) crtc_state 3158 drivers/gpu/drm/i915/display/intel_ddi.c if (!crtc_state->fec_enable) crtc_state 3168 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state, crtc_state 3176 drivers/gpu/drm/i915/display/intel_ddi.c bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); crtc_state 3181 drivers/gpu/drm/i915/display/intel_ddi.c intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state 3182 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->lane_count, is_mst); crtc_state 3186 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_clk_select(encoder, crtc_state); crtc_state 3197 drivers/gpu/drm/i915/display/intel_ddi.c icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, crtc_state 3204 drivers/gpu/drm/i915/display/intel_ddi.c intel_prepare_dp_ddi_buffers(encoder, crtc_state); crtc_state 3211 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->lane_count, crtc_state 3218 drivers/gpu/drm/i915/display/intel_ddi.c intel_dp_sink_set_decompression_state(intel_dp, crtc_state, crtc_state 3220 drivers/gpu/drm/i915/display/intel_ddi.c intel_dp_sink_set_fec_ready(intel_dp, crtc_state); crtc_state 3225 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_enable_fec(encoder, crtc_state); crtc_state 3230 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_enable_pipe_clock(crtc_state); crtc_state 3232 drivers/gpu/drm/i915/display/intel_ddi.c intel_dsc_enable(encoder, crtc_state); crtc_state 3236 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state, crtc_state 3247 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_clk_select(encoder, crtc_state); crtc_state 3255 drivers/gpu/drm/i915/display/intel_ddi.c icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, crtc_state 3269 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_enable_pipe_clock(crtc_state); crtc_state 3272 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->has_infoframe, crtc_state 3273 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state, conn_state); crtc_state 3277 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state, crtc_state 3280 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 3297 drivers/gpu/drm/i915/display/intel_ddi.c WARN_ON(crtc_state->has_pch_encoder); crtc_state 3300 drivers/gpu/drm/i915/display/intel_ddi.c icl_map_plls_to_ports(encoder, crtc_state); crtc_state 3304 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { crtc_state 3305 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state); crtc_state 3310 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state); crtc_state 3316 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->has_infoframe, crtc_state 3317 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state, conn_state); crtc_state 3323 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state) crtc_state 3343 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_disable_fec_state(encoder, crtc_state); crtc_state 3470 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state, crtc_state 3480 drivers/gpu/drm/i915/display/intel_ddi.c intel_edp_backlight_on(crtc_state, conn_state); crtc_state 3481 drivers/gpu/drm/i915/display/intel_ddi.c intel_psr_enable(intel_dp, crtc_state); crtc_state 3482 drivers/gpu/drm/i915/display/intel_ddi.c intel_dp_ycbcr_420_enable(intel_dp, crtc_state); crtc_state 3483 drivers/gpu/drm/i915/display/intel_ddi.c intel_edp_drrs_enable(intel_dp, crtc_state); crtc_state 3485 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->has_audio) crtc_state 3486 drivers/gpu/drm/i915/display/intel_ddi.c intel_audio_codec_enable(encoder, crtc_state, conn_state); crtc_state 3510 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state, crtc_state 3519 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->hdmi_high_tmds_clock_ratio, crtc_state 3520 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->hdmi_scrambling)) crtc_state 3566 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->has_audio) crtc_state 3567 drivers/gpu/drm/i915/display/intel_ddi.c intel_audio_codec_enable(encoder, crtc_state, conn_state); crtc_state 3571 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state, crtc_state 3574 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) crtc_state 3575 drivers/gpu/drm/i915/display/intel_ddi.c intel_enable_ddi_hdmi(encoder, crtc_state, conn_state); crtc_state 3577 drivers/gpu/drm/i915/display/intel_ddi.c intel_enable_ddi_dp(encoder, crtc_state, conn_state); crtc_state 3635 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state, crtc_state 3640 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_set_pipe_settings(crtc_state); crtc_state 3642 drivers/gpu/drm/i915/display/intel_ddi.c intel_psr_update(intel_dp, crtc_state); crtc_state 3643 drivers/gpu/drm/i915/display/intel_ddi.c intel_edp_drrs_enable(intel_dp, crtc_state); crtc_state 3645 drivers/gpu/drm/i915/display/intel_ddi.c intel_panel_update_backlight(encoder, crtc_state, conn_state); crtc_state 3649 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state, crtc_state 3660 drivers/gpu/drm/i915/display/intel_ddi.c if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) crtc_state 3661 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state); crtc_state 3694 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *crtc_state = crtc_state 3696 drivers/gpu/drm/i915/display/intel_ddi.c int required_lanes = crtc_state ? crtc_state->lane_count : 1; crtc_state 3701 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state && crtc_state->base.active) crtc_state 3715 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state, crtc_state 3724 drivers/gpu/drm/i915/display/intel_ddi.c intel_tc_port_get_link(dig_port, crtc_state->lane_count); crtc_state 3726 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) crtc_state 3735 drivers/gpu/drm/i915/display/intel_ddi.c intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); crtc_state 3738 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->lane_lat_optim_mask); crtc_state 3743 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_crtc_state *crtc_state, crtc_state 3751 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) crtc_state 3819 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *crtc_state) crtc_state 3821 drivers/gpu/drm/i915/display/intel_ddi.c if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) crtc_state 3822 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->min_voltage_level = 1; crtc_state 3823 drivers/gpu/drm/i915/display/intel_ddi.c else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) crtc_state 3824 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->min_voltage_level = 2; crtc_state 3958 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *crtc_state, crtc_state 4049 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_crtc_state *crtc_state; crtc_state 4058 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 4059 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_ERR(crtc_state)) { crtc_state 4060 drivers/gpu/drm/i915/display/intel_ddi.c ret = PTR_ERR(crtc_state); crtc_state 4064 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->connectors_changed = true; crtc_state 4082 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *crtc_state; crtc_state 4105 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 4107 drivers/gpu/drm/i915/display/intel_ddi.c WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); crtc_state 4109 drivers/gpu/drm/i915/display/intel_ddi.c if (!crtc_state->base.active) crtc_state 4112 drivers/gpu/drm/i915/display/intel_ddi.c if (!crtc_state->hdmi_high_tmds_clock_ratio && crtc_state 4113 drivers/gpu/drm/i915/display/intel_ddi.c !crtc_state->hdmi_scrambling) crtc_state 4127 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->hdmi_high_tmds_clock_ratio && crtc_state 4129 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->hdmi_scrambling) crtc_state 26 drivers/gpu/drm/i915/display/intel_ddi.h const struct intel_crtc_state *crtc_state); crtc_state 29 drivers/gpu/drm/i915/display/intel_ddi.h void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state); crtc_state 30 drivers/gpu/drm/i915/display/intel_ddi.h void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state); crtc_state 31 drivers/gpu/drm/i915/display/intel_ddi.h void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state); crtc_state 32 drivers/gpu/drm/i915/display/intel_ddi.h void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state); crtc_state 33 drivers/gpu/drm/i915/display/intel_ddi.h void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state); crtc_state 37 drivers/gpu/drm/i915/display/intel_ddi.h void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, crtc_state 40 drivers/gpu/drm/i915/display/intel_ddi.h struct intel_crtc_state *crtc_state); crtc_state 125 drivers/gpu/drm/i915/display/intel_display.c static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state); crtc_state 126 drivers/gpu/drm/i915/display/intel_display.c static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); crtc_state 127 drivers/gpu/drm/i915/display/intel_display.c static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, crtc_state 130 drivers/gpu/drm/i915/display/intel_display.c static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); crtc_state 131 drivers/gpu/drm/i915/display/intel_display.c static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state); crtc_state 132 drivers/gpu/drm/i915/display/intel_display.c static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state); crtc_state 133 drivers/gpu/drm/i915/display/intel_display.c static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); crtc_state 141 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state); crtc_state 142 drivers/gpu/drm/i915/display/intel_display.c static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state); crtc_state 144 drivers/gpu/drm/i915/display/intel_display.c static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state); crtc_state 632 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state, crtc_state 635 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 637 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { crtc_state 667 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 671 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc_state->base.crtc->dev; crtc_state 677 drivers/gpu/drm/i915/display/intel_display.c clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); crtc_state 725 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 729 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc_state->base.crtc->dev; crtc_state 735 drivers/gpu/drm/i915/display/intel_display.c clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); crtc_state 781 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 785 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc_state->base.crtc->dev; crtc_state 794 drivers/gpu/drm/i915/display/intel_display.c clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); crtc_state 875 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 879 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 935 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 939 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 991 drivers/gpu/drm/i915/display/intel_display.c bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, crtc_state 997 drivers/gpu/drm/i915/display/intel_display.c return chv_find_best_dpll(limit, crtc_state, crtc_state 998 drivers/gpu/drm/i915/display/intel_display.c crtc_state->port_clock, refclk, crtc_state 1484 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 1488 drivers/gpu/drm/i915/display/intel_display.c u32 dpll = crtc_state->dpll_hw_state.dpll; crtc_state 1511 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll_md); crtc_state 1529 drivers/gpu/drm/i915/display/intel_display.c static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) crtc_state 1531 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1620 drivers/gpu/drm/i915/display/intel_display.c static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) crtc_state 1622 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1629 drivers/gpu/drm/i915/display/intel_display.c assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); crtc_state 1655 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) crtc_state 1664 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) crtc_state 1764 drivers/gpu/drm/i915/display/intel_display.c static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state) crtc_state 1766 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 1773 drivers/gpu/drm/i915/display/intel_display.c (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT))) crtc_state 1784 drivers/gpu/drm/i915/display/intel_display.c static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) crtc_state 1786 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1789 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_max_vblank_count(crtc_state)); crtc_state 3111 drivers/gpu/drm/i915/display/intel_display.c intel_set_plane_visible(struct intel_crtc_state *crtc_state, crtc_state 3120 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.plane_mask |= drm_plane_mask(&plane->base); crtc_state 3122 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base); crtc_state 3125 drivers/gpu/drm/i915/display/intel_display.c static void fixup_active_planes(struct intel_crtc_state *crtc_state) crtc_state 3127 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 3135 drivers/gpu/drm/i915/display/intel_display.c crtc_state->active_planes = 0; crtc_state 3138 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.plane_mask) crtc_state 3139 drivers/gpu/drm/i915/display/intel_display.c crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); crtc_state 3145 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = crtc_state 3154 drivers/gpu/drm/i915/display/intel_display.c intel_set_plane_visible(crtc_state, plane_state, false); crtc_state 3155 drivers/gpu/drm/i915/display/intel_display.c fixup_active_planes(crtc_state); crtc_state 3156 drivers/gpu/drm/i915/display/intel_display.c crtc_state->data_rate[plane->id] = 0; crtc_state 3161 drivers/gpu/drm/i915/display/intel_display.c intel_disable_plane(plane, crtc_state); crtc_state 3595 drivers/gpu/drm/i915/display/intel_display.c static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) crtc_state 3597 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 3601 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->gamma_enable) crtc_state 3604 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->csc_enable) crtc_state 3613 drivers/gpu/drm/i915/display/intel_display.c static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, crtc_state 3740 drivers/gpu/drm/i915/display/intel_display.c i9xx_plane_check(struct intel_crtc_state *crtc_state, crtc_state 3751 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->base, crtc_state 3770 drivers/gpu/drm/i915/display/intel_display.c plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); crtc_state 3776 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state, crtc_state 3792 drivers/gpu/drm/i915/display/intel_display.c dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); crtc_state 3847 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 3864 drivers/gpu/drm/i915/display/intel_display.c dspcntr = i9xx_plane_ctl_crtc(crtc_state); crtc_state 3925 drivers/gpu/drm/i915/display/intel_display.c static void skl_detach_scalers(const struct intel_crtc_state *crtc_state) crtc_state 3927 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 3929 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->scaler_state; crtc_state 4120 drivers/gpu/drm/i915/display/intel_display.c u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) crtc_state 4122 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 4128 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->gamma_enable) crtc_state 4131 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->csc_enable) crtc_state 4137 drivers/gpu/drm/i915/display/intel_display.c u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, crtc_state 4176 drivers/gpu/drm/i915/display/intel_display.c u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) crtc_state 4178 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 4184 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->gamma_enable) crtc_state 4187 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->csc_enable) crtc_state 4193 drivers/gpu/drm/i915/display/intel_display.c u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, crtc_state 4225 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc_state *crtc_state; crtc_state 4240 drivers/gpu/drm/i915/display/intel_display.c for_each_new_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 4246 drivers/gpu/drm/i915/display/intel_display.c crtc_state->mode_changed = true; crtc_state 4479 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 4504 drivers/gpu/drm/i915/display/intel_display.c temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); crtc_state 4580 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 4603 drivers/gpu/drm/i915/display/intel_display.c temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); crtc_state 4713 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 4755 drivers/gpu/drm/i915/display/intel_display.c temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); crtc_state 4831 drivers/gpu/drm/i915/display/intel_display.c static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state) crtc_state 4833 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 4843 drivers/gpu/drm/i915/display/intel_display.c temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); crtc_state 4992 drivers/gpu/drm/i915/display/intel_display.c static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) crtc_state 4994 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 4996 drivers/gpu/drm/i915/display/intel_display.c int clock = crtc_state->base.adjusted_mode.crtc_clock; crtc_state 5107 drivers/gpu/drm/i915/display/intel_display.c static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state, crtc_state 5110 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5112 drivers/gpu/drm/i915/display/intel_display.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 5151 drivers/gpu/drm/i915/display/intel_display.c static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state) crtc_state 5153 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5160 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->fdi_lanes > 2) crtc_state 5181 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 5183 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5213 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 5215 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5224 drivers/gpu/drm/i915/display/intel_display.c ivybridge_update_fdi_bc_bifurcation(crtc_state); crtc_state 5232 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.fdi_link_train(crtc, crtc_state); crtc_state 5242 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->shared_dpll == crtc_state 5257 drivers/gpu/drm/i915/display/intel_display.c intel_enable_shared_dpll(crtc_state); crtc_state 5261 drivers/gpu/drm/i915/display/intel_display.c ironlake_pch_transcoder_set_timings(crtc_state, pipe); crtc_state 5267 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_has_dp_encoder(crtc_state)) { crtc_state 5269 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->base.adjusted_mode; crtc_state 5286 drivers/gpu/drm/i915/display/intel_display.c port = intel_get_crtc_new_encoder(state, crtc_state)->port; crtc_state 5293 drivers/gpu/drm/i915/display/intel_display.c ironlake_enable_pch_transcoder(crtc_state); crtc_state 5297 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 5299 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5301 drivers/gpu/drm/i915/display/intel_display.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 5305 drivers/gpu/drm/i915/display/intel_display.c lpt_program_iclkip(crtc_state); crtc_state 5308 drivers/gpu/drm/i915/display/intel_display.c ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A); crtc_state 5408 drivers/gpu/drm/i915/display/intel_display.c skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, crtc_state 5414 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->scaler_state; crtc_state 5416 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc(crtc_state->base.crtc); crtc_state 5419 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->base.adjusted_mode; crtc_state 5435 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && crtc_state 5529 drivers/gpu/drm/i915/display/intel_display.c static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, crtc_state 5545 drivers/gpu/drm/i915/display/intel_display.c ret = skl_update_scaler(crtc_state, force_detach, crtc_state 5611 drivers/gpu/drm/i915/display/intel_display.c static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state) crtc_state 5613 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5617 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->scaler_state; crtc_state 5619 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->pch_pfit.enabled) { crtc_state 5624 drivers/gpu/drm/i915/display/intel_display.c if (WARN_ON(crtc_state->scaler_state.scaler_id < 0)) crtc_state 5627 drivers/gpu/drm/i915/display/intel_display.c pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF; crtc_state 5628 drivers/gpu/drm/i915/display/intel_display.c pfit_h = crtc_state->pch_pfit.size & 0xFFFF; crtc_state 5630 drivers/gpu/drm/i915/display/intel_display.c hscale = (crtc_state->pipe_src_w << 16) / pfit_w; crtc_state 5631 drivers/gpu/drm/i915/display/intel_display.c vscale = (crtc_state->pipe_src_h << 16) / pfit_h; crtc_state 5643 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos); crtc_state 5644 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size); crtc_state 5648 drivers/gpu/drm/i915/display/intel_display.c static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state) crtc_state 5650 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5654 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->pch_pfit.enabled) { crtc_state 5664 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos); crtc_state 5665 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size); crtc_state 5669 drivers/gpu/drm/i915/display/intel_display.c void hsw_enable_ips(const struct intel_crtc_state *crtc_state) crtc_state 5671 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5675 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->ips_enabled) crtc_state 5683 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); crtc_state 5705 drivers/gpu/drm/i915/display/intel_display.c void hsw_disable_ips(const struct intel_crtc_state *crtc_state) crtc_state 5707 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5711 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->ips_enabled) crtc_state 5877 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 5879 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->nv12_planes) crtc_state 5890 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 5893 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv)) crtc_state 6156 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 6171 drivers/gpu/drm/i915/display/intel_display.c encoder->pre_pll_enable(encoder, crtc_state, conn_state); crtc_state 6176 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 6191 drivers/gpu/drm/i915/display/intel_display.c encoder->pre_enable(encoder, crtc_state, conn_state); crtc_state 6196 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 6211 drivers/gpu/drm/i915/display/intel_display.c encoder->enable(encoder, crtc_state, conn_state); crtc_state 6278 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 6293 drivers/gpu/drm/i915/display/intel_display.c encoder->update_pipe(encoder, crtc_state, conn_state); crtc_state 6297 drivers/gpu/drm/i915/display/intel_display.c static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) crtc_state 6299 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 6302 drivers/gpu/drm/i915/display/intel_display.c plane->disable_plane(plane, crtc_state); crtc_state 6658 drivers/gpu/drm/i915/display/intel_display.c static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) crtc_state 6660 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 6663 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->gmch_pfit.control) crtc_state 6673 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios); crtc_state 6674 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control); crtc_state 6788 drivers/gpu/drm/i915/display/intel_display.c static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) crtc_state 6790 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 6795 drivers/gpu/drm/i915/display/intel_display.c enum transcoder transcoder = crtc_state->cpu_transcoder; crtc_state 6797 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.active) crtc_state 6802 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->pch_pfit.enabled || crtc_state 6803 drivers/gpu/drm/i915/display/intel_display.c crtc_state->pch_pfit.force_thru) crtc_state 6807 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.encoder_mask) { crtc_state 6813 drivers/gpu/drm/i915/display/intel_display.c if (HAS_DDI(dev_priv) && crtc_state->has_audio) crtc_state 6816 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->shared_dpll) crtc_state 6823 drivers/gpu/drm/i915/display/intel_display.c modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state) crtc_state 6825 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 6832 drivers/gpu/drm/i915/display/intel_display.c get_crtc_power_domains(crtc_state); crtc_state 6908 drivers/gpu/drm/i915/display/intel_display.c static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state) crtc_state 6910 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 6913 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0); crtc_state 6914 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1); crtc_state 7044 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 7068 drivers/gpu/drm/i915/display/intel_display.c crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); crtc_state 7071 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(IS_ERR(crtc_state) || ret); crtc_state 7073 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.crtc_disable(crtc_state, to_intel_atomic_state(state)); crtc_state 7136 drivers/gpu/drm/i915/display/intel_display.c static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, crtc_state 7148 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(!crtc_state, crtc_state 7151 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state) crtc_state 7154 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(!crtc_state->base.active, crtc_state 7166 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(crtc_state && crtc_state->base.active, crtc_state 7168 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(!crtc_state && conn_state->best_encoder, crtc_state 7173 drivers/gpu/drm/i915/display/intel_display.c static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) crtc_state 7175 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.enable && crtc_state->has_pch_encoder) crtc_state 7176 drivers/gpu/drm/i915/display/intel_display.c return crtc_state->fdi_lanes; crtc_state 7302 drivers/gpu/drm/i915/display/intel_display.c bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) crtc_state 7304 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 7314 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->pipe_bpp > 24) crtc_state 7325 drivers/gpu/drm/i915/display/intel_display.c crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100) crtc_state 7331 drivers/gpu/drm/i915/display/intel_display.c static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state) crtc_state 7334 drivers/gpu/drm/i915/display/intel_display.c to_i915(crtc_state->base.crtc->dev); crtc_state 7336 drivers/gpu/drm/i915/display/intel_display.c to_intel_atomic_state(crtc_state->base.state); crtc_state 7338 drivers/gpu/drm/i915/display/intel_display.c if (!hsw_crtc_state_ips_capable(crtc_state)) crtc_state 7347 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->crc_enabled) crtc_state 7351 drivers/gpu/drm/i915/display/intel_display.c if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))) crtc_state 7356 drivers/gpu/drm/i915/display/intel_display.c crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100) crtc_state 7406 drivers/gpu/drm/i915/display/intel_display.c static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) crtc_state 7408 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 7412 drivers/gpu/drm/i915/display/intel_display.c crtc_state->pixel_rate = crtc_state 7413 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.adjusted_mode.crtc_clock; crtc_state 7415 drivers/gpu/drm/i915/display/intel_display.c crtc_state->pixel_rate = crtc_state 7416 drivers/gpu/drm/i915/display/intel_display.c ilk_pipe_pixel_rate(crtc_state); crtc_state 7564 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 7571 drivers/gpu/drm/i915/display/intel_display.c fp = pnv_dpll_compute_fp(&crtc_state->dpll); crtc_state 7575 drivers/gpu/drm/i915/display/intel_display.c fp = i9xx_dpll_compute_fp(&crtc_state->dpll); crtc_state 7580 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.fp0 = fp; crtc_state 7582 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && crtc_state 7584 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.fp1 = fp2; crtc_state 7586 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.fp1 = fp; crtc_state 7619 drivers/gpu/drm/i915/display/intel_display.c static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, crtc_state 7622 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 7645 drivers/gpu/drm/i915/display/intel_display.c static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, crtc_state 7649 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 7652 drivers/gpu/drm/i915/display/intel_display.c enum transcoder transcoder = crtc_state->cpu_transcoder; crtc_state 7663 drivers/gpu/drm/i915/display/intel_display.c if (m2_n2 && crtc_state->has_drrs && crtc_state 7679 drivers/gpu/drm/i915/display/intel_display.c void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n) crtc_state 7684 drivers/gpu/drm/i915/display/intel_display.c dp_m_n = &crtc_state->dp_m_n; crtc_state 7685 drivers/gpu/drm/i915/display/intel_display.c dp_m2_n2 = &crtc_state->dp_m2_n2; crtc_state 7692 drivers/gpu/drm/i915/display/intel_display.c dp_m_n = &crtc_state->dp_m2_n2; crtc_state 7698 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->has_pch_encoder) crtc_state 7699 drivers/gpu/drm/i915/display/intel_display.c intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n); crtc_state 7701 drivers/gpu/drm/i915/display/intel_display.c intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2); crtc_state 7998 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 8003 drivers/gpu/drm/i915/display/intel_display.c struct dpll *clock = &crtc_state->dpll; crtc_state 8005 drivers/gpu/drm/i915/display/intel_display.c i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); crtc_state 8009 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) crtc_state 8016 drivers/gpu/drm/i915/display/intel_display.c dpll |= (crtc_state->pixel_multiplier - 1) crtc_state 8020 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || crtc_state 8021 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) crtc_state 8024 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_dp_encoder(crtc_state)) crtc_state 8052 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->sdvo_tv_clock) crtc_state 8054 drivers/gpu/drm/i915/display/intel_display.c else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && crtc_state 8061 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll = dpll; crtc_state 8064 drivers/gpu/drm/i915/display/intel_display.c u32 dpll_md = (crtc_state->pixel_multiplier - 1) crtc_state 8066 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll_md = dpll_md; crtc_state 8071 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 8077 drivers/gpu/drm/i915/display/intel_display.c struct dpll *clock = &crtc_state->dpll; crtc_state 8079 drivers/gpu/drm/i915/display/intel_display.c i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); crtc_state 8083 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { crtc_state 8107 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) crtc_state 8110 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && crtc_state 8117 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll = dpll; crtc_state 8120 drivers/gpu/drm/i915/display/intel_display.c static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state) crtc_state 8122 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 8125 drivers/gpu/drm/i915/display/intel_display.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 8126 drivers/gpu/drm/i915/display/intel_display.c const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; crtc_state 8140 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) crtc_state 8182 drivers/gpu/drm/i915/display/intel_display.c static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) crtc_state 8184 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 8192 drivers/gpu/drm/i915/display/intel_display.c ((crtc_state->pipe_src_w - 1) << 16) | crtc_state 8193 drivers/gpu/drm/i915/display/intel_display.c (crtc_state->pipe_src_h - 1)); crtc_state 8279 drivers/gpu/drm/i915/display/intel_display.c static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) crtc_state 8281 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 8291 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->double_wide) crtc_state 8298 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->dither && crtc_state->pipe_bpp != 30) crtc_state 8302 drivers/gpu/drm/i915/display/intel_display.c switch (crtc_state->pipe_bpp) { crtc_state 8318 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { crtc_state 8320 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) crtc_state 8329 drivers/gpu/drm/i915/display/intel_display.c crtc_state->limited_color_range) crtc_state 8332 drivers/gpu/drm/i915/display/intel_display.c pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); crtc_state 8339 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state) crtc_state 8346 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 8347 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); crtc_state 8349 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { crtc_state 8356 drivers/gpu/drm/i915/display/intel_display.c } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { crtc_state 8362 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->clock_set && crtc_state 8363 drivers/gpu/drm/i915/display/intel_display.c !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, crtc_state 8364 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { crtc_state 8369 drivers/gpu/drm/i915/display/intel_display.c i8xx_compute_dpll(crtc, crtc_state, NULL); crtc_state 8375 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state) crtc_state 8381 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 8382 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); crtc_state 8384 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { crtc_state 8394 drivers/gpu/drm/i915/display/intel_display.c } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || crtc_state 8395 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { crtc_state 8397 drivers/gpu/drm/i915/display/intel_display.c } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { crtc_state 8404 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->clock_set && crtc_state 8405 drivers/gpu/drm/i915/display/intel_display.c !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, crtc_state 8406 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { crtc_state 8411 drivers/gpu/drm/i915/display/intel_display.c i9xx_compute_dpll(crtc, crtc_state, NULL); crtc_state 8417 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state) crtc_state 8424 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 8425 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); crtc_state 8427 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { crtc_state 8438 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->clock_set && crtc_state 8439 drivers/gpu/drm/i915/display/intel_display.c !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, crtc_state 8440 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { crtc_state 8445 drivers/gpu/drm/i915/display/intel_display.c i9xx_compute_dpll(crtc, crtc_state, NULL); crtc_state 8451 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state) crtc_state 8458 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 8459 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); crtc_state 8461 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { crtc_state 8472 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->clock_set && crtc_state 8473 drivers/gpu/drm/i915/display/intel_display.c !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, crtc_state 8474 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { crtc_state 8479 drivers/gpu/drm/i915/display/intel_display.c i9xx_compute_dpll(crtc, crtc_state, NULL); crtc_state 8485 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state) crtc_state 8490 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 8491 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); crtc_state 8493 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->clock_set && crtc_state 8494 drivers/gpu/drm/i915/display/intel_display.c !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, crtc_state 8495 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { crtc_state 8500 drivers/gpu/drm/i915/display/intel_display.c chv_compute_dpll(crtc, crtc_state); crtc_state 8506 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state) crtc_state 8511 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 8512 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); crtc_state 8514 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->clock_set && crtc_state 8515 drivers/gpu/drm/i915/display/intel_display.c !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, crtc_state 8516 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { crtc_state 8521 drivers/gpu/drm/i915/display/intel_display.c vlv_compute_dpll(crtc, crtc_state); crtc_state 8748 drivers/gpu/drm/i915/display/intel_display.c static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) crtc_state 8750 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 8759 drivers/gpu/drm/i915/display/intel_display.c crtc_state->gamma_enable = true; crtc_state 8763 drivers/gpu/drm/i915/display/intel_display.c crtc_state->csc_enable = true; crtc_state 9387 drivers/gpu/drm/i915/display/intel_display.c static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state) crtc_state 9389 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 9396 drivers/gpu/drm/i915/display/intel_display.c switch (crtc_state->pipe_bpp) { crtc_state 9414 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->dither) crtc_state 9417 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) crtc_state 9422 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->limited_color_range) crtc_state 9425 drivers/gpu/drm/i915/display/intel_display.c val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); crtc_state 9431 drivers/gpu/drm/i915/display/intel_display.c static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state) crtc_state 9433 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 9435 drivers/gpu/drm/i915/display/intel_display.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 9438 drivers/gpu/drm/i915/display/intel_display.c if (IS_HASWELL(dev_priv) && crtc_state->dither) crtc_state 9441 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) crtc_state 9450 drivers/gpu/drm/i915/display/intel_display.c static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) crtc_state 9452 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 9456 drivers/gpu/drm/i915/display/intel_display.c switch (crtc_state->pipe_bpp) { crtc_state 9470 drivers/gpu/drm/i915/display/intel_display.c MISSING_CASE(crtc_state->pipe_bpp); crtc_state 9474 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->dither) crtc_state 9477 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || crtc_state 9478 drivers/gpu/drm/i915/display/intel_display.c crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) crtc_state 9481 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) crtc_state 9486 drivers/gpu/drm/i915/display/intel_display.c (crtc_state->active_planes & ~(icl_hdr_plane_mask() | crtc_state 9532 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 9541 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { crtc_state 9547 drivers/gpu/drm/i915/display/intel_display.c } else if (crtc_state->sdvo_tv_clock) { crtc_state 9551 drivers/gpu/drm/i915/display/intel_display.c fp = i9xx_dpll_compute_fp(&crtc_state->dpll); crtc_state 9553 drivers/gpu/drm/i915/display/intel_display.c if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) crtc_state 9567 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) crtc_state 9572 drivers/gpu/drm/i915/display/intel_display.c dpll |= (crtc_state->pixel_multiplier - 1) crtc_state 9575 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || crtc_state 9576 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) crtc_state 9579 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_dp_encoder(crtc_state)) crtc_state 9597 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) crtc_state 9601 drivers/gpu/drm/i915/display/intel_display.c dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; crtc_state 9603 drivers/gpu/drm/i915/display/intel_display.c dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; crtc_state 9605 drivers/gpu/drm/i915/display/intel_display.c switch (crtc_state->dpll.p2) { crtc_state 9620 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && crtc_state 9628 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.dpll = dpll; crtc_state 9629 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.fp0 = fp; crtc_state 9630 drivers/gpu/drm/i915/display/intel_display.c crtc_state->dpll_hw_state.fp1 = fp2; crtc_state 9634 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state) crtc_state 9638 drivers/gpu/drm/i915/display/intel_display.c to_intel_atomic_state(crtc_state->base.state); crtc_state 9642 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 9643 drivers/gpu/drm/i915/display/intel_display.c sizeof(crtc_state->dpll_hw_state)); crtc_state 9646 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->has_pch_encoder) crtc_state 9649 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { crtc_state 9671 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->clock_set && crtc_state 9672 drivers/gpu/drm/i915/display/intel_display.c !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, crtc_state 9673 drivers/gpu/drm/i915/display/intel_display.c refclk, NULL, &crtc_state->dpll)) { crtc_state 9678 drivers/gpu/drm/i915/display/intel_display.c ironlake_compute_dpll(crtc, crtc_state, NULL); crtc_state 10050 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state) crtc_state 10054 drivers/gpu/drm/i915/display/intel_display.c to_intel_atomic_state(crtc_state->base.state); crtc_state 10056 drivers/gpu/drm/i915/display/intel_display.c if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) || crtc_state 10059 drivers/gpu/drm/i915/display/intel_display.c intel_get_crtc_new_encoder(state, crtc_state); crtc_state 10590 drivers/gpu/drm/i915/display/intel_display.c static int intel_check_cursor(struct intel_crtc_state *crtc_state, crtc_state 10602 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->base, crtc_state 10631 drivers/gpu/drm/i915/display/intel_display.c static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) crtc_state 10635 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->gamma_enable) crtc_state 10641 drivers/gpu/drm/i915/display/intel_display.c static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, crtc_state 10660 drivers/gpu/drm/i915/display/intel_display.c static int i845_check_cursor(struct intel_crtc_state *crtc_state, crtc_state 10666 drivers/gpu/drm/i915/display/intel_display.c ret = intel_check_cursor(crtc_state, plane_state); crtc_state 10697 drivers/gpu/drm/i915/display/intel_display.c plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); crtc_state 10703 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state, crtc_state 10715 drivers/gpu/drm/i915/display/intel_display.c i845_cursor_ctl_crtc(crtc_state); crtc_state 10748 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 10750 drivers/gpu/drm/i915/display/intel_display.c i845_update_cursor(plane, crtc_state, NULL); crtc_state 10783 drivers/gpu/drm/i915/display/intel_display.c static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) crtc_state 10785 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 10792 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->gamma_enable) crtc_state 10795 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->csc_enable) crtc_state 10804 drivers/gpu/drm/i915/display/intel_display.c static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, crtc_state 10873 drivers/gpu/drm/i915/display/intel_display.c static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, crtc_state 10882 drivers/gpu/drm/i915/display/intel_display.c ret = intel_check_cursor(crtc_state, plane_state); crtc_state 10923 drivers/gpu/drm/i915/display/intel_display.c plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); crtc_state 10929 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state, crtc_state 10939 drivers/gpu/drm/i915/display/intel_display.c i9xx_cursor_ctl_crtc(crtc_state); crtc_state 10971 drivers/gpu/drm/i915/display/intel_display.c skl_write_cursor_wm(plane, crtc_state); crtc_state 10994 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *crtc_state) crtc_state 10996 drivers/gpu/drm/i915/display/intel_display.c i9xx_update_cursor(plane, crtc_state, NULL); crtc_state 11102 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 11186 drivers/gpu/drm/i915/display/intel_display.c crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); crtc_state 11187 drivers/gpu/drm/i915/display/intel_display.c if (IS_ERR(crtc_state)) { crtc_state 11188 drivers/gpu/drm/i915/display/intel_display.c ret = PTR_ERR(crtc_state); crtc_state 11192 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.active = crtc_state->base.enable = true; crtc_state 11197 drivers/gpu/drm/i915/display/intel_display.c ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); crtc_state 11415 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 11429 drivers/gpu/drm/i915/display/intel_display.c crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); crtc_state 11430 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state) { crtc_state 11435 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.crtc = &crtc->base; crtc_state 11437 drivers/gpu/drm/i915/display/intel_display.c if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) { crtc_state 11438 drivers/gpu/drm/i915/display/intel_display.c kfree(crtc_state); crtc_state 11443 drivers/gpu/drm/i915/display/intel_display.c encoder->get_config(encoder, crtc_state); crtc_state 11445 drivers/gpu/drm/i915/display/intel_display.c intel_mode_from_pipe_config(mode, crtc_state); crtc_state 11447 drivers/gpu/drm/i915/display/intel_display.c kfree(crtc_state); crtc_state 11502 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state, crtc_state 11506 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 11509 drivers/gpu/drm/i915/display/intel_display.c bool mode_changed = needs_modeset(crtc_state); crtc_state 11511 drivers/gpu/drm/i915/display/intel_display.c bool is_crtc_enabled = crtc_state->base.active; crtc_state 11517 drivers/gpu/drm/i915/display/intel_display.c ret = skl_update_scaler_plane(crtc_state, plane_state); crtc_state 11540 drivers/gpu/drm/i915/display/intel_display.c crtc_state->active_planes &= ~BIT(plane->id); crtc_state 11541 drivers/gpu/drm/i915/display/intel_display.c crtc_state->data_rate[plane->id] = 0; crtc_state 11548 drivers/gpu/drm/i915/display/intel_display.c crtc_state->fb_changed = true; crtc_state 11565 drivers/gpu/drm/i915/display/intel_display.c crtc_state->update_wm_pre = true; crtc_state 11569 drivers/gpu/drm/i915/display/intel_display.c crtc_state->disable_cxsr = true; crtc_state 11572 drivers/gpu/drm/i915/display/intel_display.c crtc_state->update_wm_post = true; crtc_state 11576 drivers/gpu/drm/i915/display/intel_display.c crtc_state->disable_cxsr = true; crtc_state 11580 drivers/gpu/drm/i915/display/intel_display.c crtc_state->update_wm_pre = true; crtc_state 11581 drivers/gpu/drm/i915/display/intel_display.c crtc_state->update_wm_post = true; crtc_state 11586 drivers/gpu/drm/i915/display/intel_display.c crtc_state->fb_bits |= plane->frontbuffer_bit; crtc_state 11626 drivers/gpu/drm/i915/display/intel_display.c crtc_state->disable_lp_wm = true; crtc_state 11684 drivers/gpu/drm/i915/display/intel_display.c static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) crtc_state 11686 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 11688 drivers/gpu/drm/i915/display/intel_display.c struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state); crtc_state 11706 drivers/gpu/drm/i915/display/intel_display.c crtc_state->active_planes &= ~BIT(plane->id); crtc_state 11707 drivers/gpu/drm/i915/display/intel_display.c crtc_state->update_planes |= BIT(plane->id); crtc_state 11713 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->nv12_planes) crtc_state 11720 drivers/gpu/drm/i915/display/intel_display.c !(crtc_state->nv12_planes & BIT(plane->id))) crtc_state 11727 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->active_planes & BIT(linked->id)) crtc_state 11739 drivers/gpu/drm/i915/display/intel_display.c hweight8(crtc_state->nv12_planes)); crtc_state 11748 drivers/gpu/drm/i915/display/intel_display.c crtc_state->active_planes |= BIT(linked->id); crtc_state 11749 drivers/gpu/drm/i915/display/intel_display.c crtc_state->update_planes |= BIT(linked->id); crtc_state 11768 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc_state *crtc_state) crtc_state 11773 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc_state(crtc_state); crtc_state 11778 drivers/gpu/drm/i915/display/intel_display.c mode_changed && !crtc_state->active) crtc_state 11781 drivers/gpu/drm/i915/display/intel_display.c if (mode_changed && crtc_state->enable && crtc_state 11795 drivers/gpu/drm/i915/display/intel_display.c crtc_state->color_mgmt_changed = true; crtc_state 11798 drivers/gpu/drm/i915/display/intel_display.c crtc_state->color_mgmt_changed) { crtc_state 12239 drivers/gpu/drm/i915/display/intel_display.c clear_intel_crtc_state(struct intel_crtc_state *crtc_state) crtc_state 12242 drivers/gpu/drm/i915/display/intel_display.c to_i915(crtc_state->base.crtc->dev); crtc_state 12254 drivers/gpu/drm/i915/display/intel_display.c saved_state->scaler_state = crtc_state->scaler_state; crtc_state 12255 drivers/gpu/drm/i915/display/intel_display.c saved_state->shared_dpll = crtc_state->shared_dpll; crtc_state 12256 drivers/gpu/drm/i915/display/intel_display.c saved_state->dpll_hw_state = crtc_state->dpll_hw_state; crtc_state 12257 drivers/gpu/drm/i915/display/intel_display.c memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, crtc_state 12259 drivers/gpu/drm/i915/display/intel_display.c saved_state->crc_enabled = crtc_state->crc_enabled; crtc_state 12262 drivers/gpu/drm/i915/display/intel_display.c saved_state->wm = crtc_state->wm; crtc_state 12266 drivers/gpu/drm/i915/display/intel_display.c memcpy(&crtc_state->base + 1, &saved_state->base + 1, crtc_state 12267 drivers/gpu/drm/i915/display/intel_display.c sizeof(*crtc_state) - sizeof(crtc_state->base)); crtc_state 13024 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = NULL; crtc_state 13030 drivers/gpu/drm/i915/display/intel_display.c crtc_state = intel_atomic_get_new_crtc_state(state, crtc); crtc_state 13032 drivers/gpu/drm/i915/display/intel_display.c intel_connector_verify_state(crtc_state, new_conn_state); crtc_state 13279 drivers/gpu/drm/i915/display/intel_display.c static void update_scanline_offset(const struct intel_crtc_state *crtc_state) crtc_state 13281 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 13312 drivers/gpu/drm/i915/display/intel_display.c const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; crtc_state 13321 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { crtc_state 13353 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 13361 drivers/gpu/drm/i915/display/intel_display.c for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 13362 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.active || crtc_state 13363 drivers/gpu/drm/i915/display/intel_display.c !needs_modeset(crtc_state)) crtc_state 13367 drivers/gpu/drm/i915/display/intel_display.c other_crtc_state = crtc_state; crtc_state 13370 drivers/gpu/drm/i915/display/intel_display.c first_crtc_state = crtc_state; crtc_state 13381 drivers/gpu/drm/i915/display/intel_display.c crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); crtc_state 13382 drivers/gpu/drm/i915/display/intel_display.c if (IS_ERR(crtc_state)) crtc_state 13383 drivers/gpu/drm/i915/display/intel_display.c return PTR_ERR(crtc_state); crtc_state 13385 drivers/gpu/drm/i915/display/intel_display.c crtc_state->hsw_workaround_pipe = INVALID_PIPE; crtc_state 13387 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.active || crtc_state 13388 drivers/gpu/drm/i915/display/intel_display.c needs_modeset(crtc_state)) crtc_state 13413 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 13415 drivers/gpu/drm/i915/display/intel_display.c crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); crtc_state 13416 drivers/gpu/drm/i915/display/intel_display.c if (IS_ERR(crtc_state)) crtc_state 13417 drivers/gpu/drm/i915/display/intel_display.c return PTR_ERR(crtc_state); crtc_state 13433 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 13436 drivers/gpu/drm/i915/display/intel_display.c crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); crtc_state 13437 drivers/gpu/drm/i915/display/intel_display.c if (IS_ERR(crtc_state)) crtc_state 13438 drivers/gpu/drm/i915/display/intel_display.c return PTR_ERR(crtc_state); crtc_state 13440 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.active || needs_modeset(crtc_state)) crtc_state 13443 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.mode_changed = true; crtc_state 13520 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 13524 drivers/gpu/drm/i915/display/intel_display.c crtc_state = intel_atomic_get_new_crtc_state(state, crtc); crtc_state 13525 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state && needs_modeset(crtc_state)) crtc_state 14377 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = crtc_state 14392 drivers/gpu/drm/i915/display/intel_display.c if (needs_modeset(crtc_state)) { crtc_state 14498 drivers/gpu/drm/i915/display/intel_display.c skl_max_scale(const struct intel_crtc_state *crtc_state, crtc_state 14501 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 14506 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.enable) crtc_state 14509 drivers/gpu/drm/i915/display/intel_display.c crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; crtc_state 14510 drivers/gpu/drm/i915/display/intel_display.c max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; crtc_state 14567 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state) crtc_state 14574 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->has_pch_encoder) { crtc_state 14697 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = crtc_state 14706 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.active || needs_modeset(crtc_state) || crtc_state 14707 drivers/gpu/drm/i915/display/intel_display.c crtc_state->update_pipe) crtc_state 14754 drivers/gpu/drm/i915/display/intel_display.c ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state, crtc_state 14786 drivers/gpu/drm/i915/display/intel_display.c crtc_state->active_planes = new_crtc_state->active_planes; crtc_state 14789 drivers/gpu/drm/i915/display/intel_display.c intel_update_plane(intel_plane, crtc_state, crtc_state 14792 drivers/gpu/drm/i915/display/intel_display.c intel_disable_plane(intel_plane, crtc_state); crtc_state 15014 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state) crtc_state 15017 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->scaler_state; crtc_state 15106 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = NULL; crtc_state 15115 drivers/gpu/drm/i915/display/intel_display.c crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); crtc_state 15116 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state) { crtc_state 15120 drivers/gpu/drm/i915/display/intel_display.c __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->base); crtc_state 15121 drivers/gpu/drm/i915/display/intel_display.c intel_crtc->config = crtc_state; crtc_state 15176 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_init_scalers(intel_crtc, crtc_state); crtc_state 15203 drivers/gpu/drm/i915/display/intel_display.c kfree(crtc_state); crtc_state 15987 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 16042 drivers/gpu/drm/i915/display/intel_display.c for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { crtc_state 16043 drivers/gpu/drm/i915/display/intel_display.c crtc_state->wm.need_postvbl_update = true; crtc_state 16044 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.optimize_watermarks(intel_state, crtc_state); crtc_state 16046 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; crtc_state 16077 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc_state *crtc_state; crtc_state 16090 drivers/gpu/drm/i915/display/intel_display.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 16091 drivers/gpu/drm/i915/display/intel_display.c if (IS_ERR(crtc_state)) { crtc_state 16092 drivers/gpu/drm/i915/display/intel_display.c ret = PTR_ERR(crtc_state); crtc_state 16096 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->active) { crtc_state 16107 drivers/gpu/drm/i915/display/intel_display.c crtc_state->color_mgmt_changed = true; crtc_state 16439 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 16440 drivers/gpu/drm/i915/display/intel_display.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 16450 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active) { crtc_state 16475 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active && !intel_crtc_has_encoders(crtc)) crtc_state 16478 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active || HAS_GMCH(dev_priv)) { crtc_state 16507 drivers/gpu/drm/i915/display/intel_display.c static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) crtc_state 16509 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 16522 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.active && crtc_state 16523 drivers/gpu/drm/i915/display/intel_display.c crtc_state->shared_dpll && crtc_state 16524 drivers/gpu/drm/i915/display/intel_display.c crtc_state->port_clock == 0; crtc_state 16532 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = crtc ? crtc_state 16538 drivers/gpu/drm/i915/display/intel_display.c bool has_active_crtc = crtc_state && crtc_state 16539 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.active; crtc_state 16541 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state && has_bogus_dpll_config(crtc_state)) { crtc_state 16556 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state) { crtc_state 16568 drivers/gpu/drm/i915/display/intel_display.c encoder->disable(encoder, crtc_state, crtc_state 16571 drivers/gpu/drm/i915/display/intel_display.c encoder->post_disable(encoder, crtc_state, crtc_state 16636 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 16643 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 16645 drivers/gpu/drm/i915/display/intel_display.c intel_set_plane_visible(crtc_state, plane_state, visible); crtc_state 16653 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = crtc_state 16656 drivers/gpu/drm/i915/display/intel_display.c fixup_active_planes(crtc_state); crtc_state 16673 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = crtc_state 16676 drivers/gpu/drm/i915/display/intel_display.c __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); crtc_state 16677 drivers/gpu/drm/i915/display/intel_display.c memset(crtc_state, 0, sizeof(*crtc_state)); crtc_state 16678 drivers/gpu/drm/i915/display/intel_display.c __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base); crtc_state 16680 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.active = crtc_state->base.enable = crtc_state 16681 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.get_pipe_config(crtc, crtc_state); crtc_state 16683 drivers/gpu/drm/i915/display/intel_display.c crtc->base.enabled = crtc_state->base.enable; crtc_state 16684 drivers/gpu/drm/i915/display/intel_display.c crtc->active = crtc_state->base.active; crtc_state 16686 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active) crtc_state 16691 drivers/gpu/drm/i915/display/intel_display.c enableddisabled(crtc_state->base.active)); crtc_state 16710 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = crtc_state 16713 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active && crtc_state 16714 drivers/gpu/drm/i915/display/intel_display.c crtc_state->shared_dpll == pll) crtc_state 16727 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 16730 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 16733 drivers/gpu/drm/i915/display/intel_display.c encoder->get_config(encoder, crtc_state); crtc_state 16778 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = crtc_state 16784 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active) { crtc_state 16785 drivers/gpu/drm/i915/display/intel_display.c intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); crtc_state 16786 drivers/gpu/drm/i915/display/intel_display.c crtc->base.mode.hdisplay = crtc_state->pipe_src_w; crtc_state 16787 drivers/gpu/drm/i915/display/intel_display.c crtc->base.mode.vdisplay = crtc_state->pipe_src_h; crtc_state 16788 drivers/gpu/drm/i915/display/intel_display.c intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); crtc_state 16800 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; crtc_state 16802 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_compute_pixel_rate(crtc_state); crtc_state 16805 drivers/gpu/drm/i915/display/intel_display.c min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); crtc_state 16811 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->base.adjusted_mode); crtc_state 16812 drivers/gpu/drm/i915/display/intel_display.c update_scanline_offset(crtc_state); crtc_state 16817 drivers/gpu/drm/i915/display/intel_display.c crtc_state->min_voltage_level; crtc_state 16828 drivers/gpu/drm/i915/display/intel_display.c crtc_state->data_rate[plane->id] = crtc_state 16829 drivers/gpu/drm/i915/display/intel_display.c 4 * crtc_state->pixel_rate; crtc_state 16832 drivers/gpu/drm/i915/display/intel_display.c intel_bw_crtc_update(bw_state, crtc_state); crtc_state 16834 drivers/gpu/drm/i915/display/intel_display.c intel_pipe_config_sanity_check(dev_priv, crtc_state); crtc_state 16844 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 16856 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(encoder->base.crtc->state); crtc_state 16857 drivers/gpu/drm/i915/display/intel_display.c encoder->get_power_domains(encoder, crtc_state); crtc_state 16948 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state; crtc_state 16981 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 16985 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active) crtc_state 16986 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_vblank_on(crtc_state); crtc_state 16995 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 16997 drivers/gpu/drm/i915/display/intel_display.c intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]"); crtc_state 17030 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 17031 drivers/gpu/drm/i915/display/intel_display.c put_domains = modeset_get_crtc_power_domains(crtc_state); crtc_state 500 drivers/gpu/drm/i915/display/intel_display.h void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, crtc_state 503 drivers/gpu/drm/i915/display/intel_display.h const struct intel_crtc_state *crtc_state); crtc_state 505 drivers/gpu/drm/i915/display/intel_display.h bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, crtc_state 510 drivers/gpu/drm/i915/display/intel_display.h bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); crtc_state 511 drivers/gpu/drm/i915/display/intel_display.h void hsw_enable_ips(const struct intel_crtc_state *crtc_state); crtc_state 512 drivers/gpu/drm/i915/display/intel_display.h void hsw_disable_ips(const struct intel_crtc_state *crtc_state); crtc_state 519 drivers/gpu/drm/i915/display/intel_display.h struct intel_crtc_state *crtc_state); crtc_state 522 drivers/gpu/drm/i915/display/intel_display.h int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); crtc_state 523 drivers/gpu/drm/i915/display/intel_display.h int skl_max_scale(const struct intel_crtc_state *crtc_state, crtc_state 525 drivers/gpu/drm/i915/display/intel_display.h u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, crtc_state 527 drivers/gpu/drm/i915/display/intel_display.h u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state); crtc_state 528 drivers/gpu/drm/i915/display/intel_display.h u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, crtc_state 530 drivers/gpu/drm/i915/display/intel_display.h u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); crtc_state 183 drivers/gpu/drm/i915/display/intel_display_types.h struct intel_crtc_state *crtc_state); crtc_state 224 drivers/gpu/drm/i915/display/intel_display_types.h void (*enable)(const struct intel_crtc_state *crtc_state, crtc_state 1055 drivers/gpu/drm/i915/display/intel_display_types.h const struct intel_crtc_state *crtc_state, crtc_state 1058 drivers/gpu/drm/i915/display/intel_display_types.h const struct intel_crtc_state *crtc_state, crtc_state 1061 drivers/gpu/drm/i915/display/intel_display_types.h const struct intel_crtc_state *crtc_state); crtc_state 1063 drivers/gpu/drm/i915/display/intel_display_types.h int (*check_plane)(struct intel_crtc_state *crtc_state, crtc_state 1275 drivers/gpu/drm/i915/display/intel_display_types.h const struct intel_crtc_state *crtc_state, crtc_state 1279 drivers/gpu/drm/i915/display/intel_display_types.h const struct intel_crtc_state *crtc_state, crtc_state 1284 drivers/gpu/drm/i915/display/intel_display_types.h const struct intel_crtc_state *crtc_state, crtc_state 1494 drivers/gpu/drm/i915/display/intel_display_types.h intel_crtc_has_type(const struct intel_crtc_state *crtc_state, crtc_state 1497 drivers/gpu/drm/i915/display/intel_display_types.h return crtc_state->output_types & (1 << type); crtc_state 1500 drivers/gpu/drm/i915/display/intel_display_types.h intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) crtc_state 1502 drivers/gpu/drm/i915/display/intel_display_types.h return crtc_state->output_types & crtc_state 164 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *crtc_state); crtc_state 1929 drivers/gpu/drm/i915/display/intel_dp.c static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp) crtc_state 1936 drivers/gpu/drm/i915/display/intel_dp.c if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) crtc_state 2093 drivers/gpu/drm/i915/display/intel_dp.c int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state) crtc_state 2095 drivers/gpu/drm/i915/display/intel_dp.c if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) crtc_state 2190 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc_state *crtc_state) crtc_state 2194 drivers/gpu/drm/i915/display/intel_dp.c &crtc_state->base.adjusted_mode; crtc_state 2195 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 2203 drivers/gpu/drm/i915/display/intel_dp.c crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; crtc_state 2206 drivers/gpu/drm/i915/display/intel_dp.c ret = skl_update_scaler_crtc(crtc_state); crtc_state 2212 drivers/gpu/drm/i915/display/intel_dp.c intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN); crtc_state 2217 drivers/gpu/drm/i915/display/intel_dp.c bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, crtc_state 2223 drivers/gpu/drm/i915/display/intel_dp.c &crtc_state->base.adjusted_mode; crtc_state 2231 drivers/gpu/drm/i915/display/intel_dp.c return crtc_state->pipe_bpp != 18 && crtc_state 2844 drivers/gpu/drm/i915/display/intel_dp.c void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, crtc_state 2854 drivers/gpu/drm/i915/display/intel_dp.c intel_panel_enable_backlight(crtc_state, conn_state); crtc_state 3021 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *crtc_state, crtc_state 3026 drivers/gpu/drm/i915/display/intel_dp.c if (!crtc_state->dsc_params.compression_enable) crtc_state 3543 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *crtc_state) crtc_state 3547 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 4423 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *crtc_state) crtc_state 4460 drivers/gpu/drm/i915/display/intel_dp.c switch (crtc_state->pipe_bpp) { crtc_state 4474 drivers/gpu/drm/i915/display/intel_dp.c MISSING_CASE(crtc_state->pipe_bpp); crtc_state 4499 drivers/gpu/drm/i915/display/intel_dp.c crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp)); crtc_state 4503 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *crtc_state) crtc_state 4505 drivers/gpu/drm/i915/display/intel_dp.c if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) crtc_state 4508 drivers/gpu/drm/i915/display/intel_dp.c intel_pixel_encoding_setup_vsc(intel_dp, crtc_state); crtc_state 4800 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc_state *crtc_state; crtc_state 4824 drivers/gpu/drm/i915/display/intel_dp.c crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 4826 drivers/gpu/drm/i915/display/intel_dp.c WARN_ON(!intel_crtc_has_dp_encoder(crtc_state)); crtc_state 4828 drivers/gpu/drm/i915/display/intel_dp.c if (!crtc_state->base.active) crtc_state 4840 drivers/gpu/drm/i915/display/intel_dp.c if (crtc_state->has_pch_encoder) crtc_state 4851 drivers/gpu/drm/i915/display/intel_dp.c if (crtc_state->has_pch_encoder) crtc_state 6649 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *crtc_state, crtc_state 6653 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 6686 drivers/gpu/drm/i915/display/intel_dp.c if (!crtc_state->base.active) { crtc_state 6694 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_set_m_n(crtc_state, M1_N1); crtc_state 6697 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_set_m_n(crtc_state, M2_N2); crtc_state 6704 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); crtc_state 6735 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *crtc_state) crtc_state 6739 drivers/gpu/drm/i915/display/intel_dp.c if (!crtc_state->has_drrs) { crtc_state 35 drivers/gpu/drm/i915/display/intel_dp.h bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, crtc_state 37 drivers/gpu/drm/i915/display/intel_dp.h int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state); crtc_state 54 drivers/gpu/drm/i915/display/intel_dp.h const struct intel_crtc_state *crtc_state, crtc_state 66 drivers/gpu/drm/i915/display/intel_dp.h void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, crtc_state 81 drivers/gpu/drm/i915/display/intel_dp.h const struct intel_crtc_state *crtc_state); crtc_state 83 drivers/gpu/drm/i915/display/intel_dp.h const struct intel_crtc_state *crtc_state); crtc_state 177 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 41 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_crtc_state *crtc_state, crtc_state 45 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_atomic_state *state = crtc_state->base.state; crtc_state 51 drivers/gpu/drm/i915/display/intel_dp_mst.c &crtc_state->base.adjusted_mode; crtc_state 57 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->lane_count = limits->max_lane_count; crtc_state 58 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->port_clock = limits->max_clock; crtc_state 61 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->pipe_bpp = bpp; crtc_state 63 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, crtc_state 64 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->pipe_bpp); crtc_state 67 drivers/gpu/drm/i915/display/intel_dp_mst.c port, crtc_state->pbn); crtc_state 79 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_link_compute_m_n(crtc_state->pipe_bpp, crtc_state 80 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->lane_count, crtc_state 82 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->port_clock, crtc_state 83 drivers/gpu/drm/i915/display/intel_dp_mst.c &crtc_state->dp_m_n, crtc_state 84 drivers/gpu/drm/i915/display/intel_dp_mst.c constant_n, crtc_state->fec_enable); crtc_state 85 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->dp_m_n.tu = slots; crtc_state 171 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_crtc_state *crtc_state; crtc_state 186 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); crtc_state 188 drivers/gpu/drm/i915/display/intel_dp_mst.c if (!crtc_state || crtc_state 189 drivers/gpu/drm/i915/display/intel_dp_mst.c !drm_atomic_crtc_needs_modeset(crtc_state) || crtc_state 190 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->enable) crtc_state 737 drivers/gpu/drm/i915/display/intel_dpio_phy.c const struct intel_crtc_state *crtc_state, crtc_state 742 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 753 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { crtc_state 770 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { crtc_state 782 drivers/gpu/drm/i915/display/intel_dpio_phy.c const struct intel_crtc_state *crtc_state) crtc_state 786 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 790 drivers/gpu/drm/i915/display/intel_dpio_phy.c intel_dp_unused_lane_mask(crtc_state->lane_count); crtc_state 806 drivers/gpu/drm/i915/display/intel_dpio_phy.c chv_data_lane_soft_reset(encoder, crtc_state, true); crtc_state 836 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { crtc_state 862 drivers/gpu/drm/i915/display/intel_dpio_phy.c const struct intel_crtc_state *crtc_state) crtc_state 867 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 880 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { crtc_state 887 drivers/gpu/drm/i915/display/intel_dpio_phy.c for (i = 0; i < crtc_state->lane_count; i++) { crtc_state 889 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count == 1) crtc_state 898 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->port_clock > 270000) crtc_state 900 drivers/gpu/drm/i915/display/intel_dpio_phy.c else if (crtc_state->port_clock > 135000) crtc_state 902 drivers/gpu/drm/i915/display/intel_dpio_phy.c else if (crtc_state->port_clock > 67500) crtc_state 904 drivers/gpu/drm/i915/display/intel_dpio_phy.c else if (crtc_state->port_clock > 33750) crtc_state 913 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { crtc_state 926 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { crtc_state 936 drivers/gpu/drm/i915/display/intel_dpio_phy.c chv_data_lane_soft_reset(encoder, crtc_state, false); crtc_state 1015 drivers/gpu/drm/i915/display/intel_dpio_phy.c const struct intel_crtc_state *crtc_state) crtc_state 1019 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1044 drivers/gpu/drm/i915/display/intel_dpio_phy.c const struct intel_crtc_state *crtc_state) crtc_state 1049 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 38 drivers/gpu/drm/i915/display/intel_dpio_phy.h const struct intel_crtc_state *crtc_state, crtc_state 41 drivers/gpu/drm/i915/display/intel_dpio_phy.h const struct intel_crtc_state *crtc_state); crtc_state 43 drivers/gpu/drm/i915/display/intel_dpio_phy.h const struct intel_crtc_state *crtc_state); crtc_state 52 drivers/gpu/drm/i915/display/intel_dpio_phy.h const struct intel_crtc_state *crtc_state); crtc_state 54 drivers/gpu/drm/i915/display/intel_dpio_phy.h const struct intel_crtc_state *crtc_state); crtc_state 137 drivers/gpu/drm/i915/display/intel_dpll_mgr.c void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state) crtc_state 139 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 141 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll = crtc_state->shared_dpll; crtc_state 164 drivers/gpu/drm/i915/display/intel_dpll_mgr.c void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) crtc_state 166 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 168 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll = crtc_state->shared_dpll; crtc_state 209 drivers/gpu/drm/i915/display/intel_dpll_mgr.c void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) crtc_state 211 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 213 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll = crtc_state->shared_dpll; crtc_state 450 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc_state *crtc_state = crtc_state 466 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, crtc_state 476 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); crtc_state 478 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = pll; crtc_state 816 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc_state *crtc_state = crtc_state 822 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); crtc_state 828 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.wrpll = val; crtc_state 831 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, crtc_state 841 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state) crtc_state 843 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 846 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int clock = crtc_state->port_clock; crtc_state 875 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc_state *crtc_state = crtc_state 879 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 880 drivers/gpu/drm/i915/display/intel_dpll_mgr.c sizeof(crtc_state->dpll_hw_state)); crtc_state 882 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { crtc_state 884 drivers/gpu/drm/i915/display/intel_dpll_mgr.c } else if (intel_crtc_has_dp_encoder(crtc_state)) { crtc_state 885 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = hsw_ddi_dp_get_dpll(crtc_state); crtc_state 886 drivers/gpu/drm/i915/display/intel_dpll_mgr.c } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { crtc_state 887 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (WARN_ON(crtc_state->port_clock / 2 != 135000)) crtc_state 890 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.spll = crtc_state 894 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, crtc_state 904 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); crtc_state 906 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = pll; crtc_state 1361 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) crtc_state 1374 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, crtc_state 1388 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 1389 drivers/gpu/drm/i915/display/intel_dpll_mgr.c sizeof(crtc_state->dpll_hw_state)); crtc_state 1391 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.ctrl1 = ctrl1; crtc_state 1392 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; crtc_state 1393 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; crtc_state 1398 drivers/gpu/drm/i915/display/intel_dpll_mgr.c skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) crtc_state 1407 drivers/gpu/drm/i915/display/intel_dpll_mgr.c switch (crtc_state->port_clock / 2) { crtc_state 1429 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 1430 drivers/gpu/drm/i915/display/intel_dpll_mgr.c sizeof(crtc_state->dpll_hw_state)); crtc_state 1432 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.ctrl1 = ctrl1; crtc_state 1441 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc_state *crtc_state = crtc_state 1446 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { crtc_state 1447 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bret = skl_ddi_hdmi_pll_dividers(crtc_state); crtc_state 1452 drivers/gpu/drm/i915/display/intel_dpll_mgr.c } else if (intel_crtc_has_dp_encoder(crtc_state)) { crtc_state 1453 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bret = skl_ddi_dp_set_dpll_hw_state(crtc_state); crtc_state 1462 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) crtc_state 1464 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, crtc_state 1469 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, crtc_state 1476 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); crtc_state 1478 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = pll; crtc_state 1749 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, crtc_state 1752 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1760 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!bxt_find_best_dpll(crtc_state, &best_clock)) { crtc_state 1762 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->port_clock, crtc_state 1780 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state, crtc_state 1783 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int clock = crtc_state->port_clock; crtc_state 1797 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, crtc_state 1800 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state; crtc_state 1801 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int clock = crtc_state->port_clock; crtc_state 1867 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) crtc_state 1871 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bxt_ddi_dp_pll_dividers(crtc_state, &clk_div); crtc_state 1873 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div); crtc_state 1877 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state) crtc_state 1881 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div); crtc_state 1883 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div); crtc_state 1890 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc_state *crtc_state = crtc_state 1896 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && crtc_state 1897 drivers/gpu/drm/i915/display/intel_dpll_mgr.c !bxt_ddi_hdmi_set_dpll_hw_state(crtc_state)) crtc_state 1900 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state 1901 drivers/gpu/drm/i915/display/intel_dpll_mgr.c !bxt_ddi_dp_set_dpll_hw_state(crtc_state)) crtc_state 1912 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); crtc_state 1914 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = pll; crtc_state 2272 drivers/gpu/drm/i915/display/intel_dpll_mgr.c cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state, crtc_state 2275 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 2276 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 afe_clock = crtc_state->port_clock * 5; crtc_state 2318 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) crtc_state 2325 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!cnl_ddi_calculate_wrpll(crtc_state, &wrpll_params)) crtc_state 2337 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 2338 drivers/gpu/drm/i915/display/intel_dpll_mgr.c sizeof(crtc_state->dpll_hw_state)); crtc_state 2340 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.cfgcr0 = cfgcr0; crtc_state 2341 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; crtc_state 2346 drivers/gpu/drm/i915/display/intel_dpll_mgr.c cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) crtc_state 2352 drivers/gpu/drm/i915/display/intel_dpll_mgr.c switch (crtc_state->port_clock / 2) { crtc_state 2382 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(&crtc_state->dpll_hw_state, 0, crtc_state 2383 drivers/gpu/drm/i915/display/intel_dpll_mgr.c sizeof(crtc_state->dpll_hw_state)); crtc_state 2385 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.cfgcr0 = cfgcr0; crtc_state 2394 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc_state *crtc_state = crtc_state 2399 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { crtc_state 2400 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bret = cnl_ddi_hdmi_pll_dividers(crtc_state); crtc_state 2405 drivers/gpu/drm/i915/display/intel_dpll_mgr.c } else if (intel_crtc_has_dp_encoder(crtc_state)) { crtc_state 2406 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state); crtc_state 2413 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->output_types); crtc_state 2418 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->dpll_hw_state, crtc_state 2427 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); crtc_state 2429 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = pll; crtc_state 2538 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, crtc_state 2541 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 2546 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int clock = crtc_state->port_clock; crtc_state 2560 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, crtc_state 2563 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 2570 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, crtc_state 2574 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 2581 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ret = icl_calc_tbt_pll(crtc_state, &pll_params); crtc_state 2582 drivers/gpu/drm/i915/display/intel_dpll_mgr.c else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || crtc_state 2583 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) crtc_state 2584 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ret = cnl_ddi_calculate_wrpll(crtc_state, &pll_params); crtc_state 2586 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ret = icl_calc_dp_combo_pll(crtc_state, &pll_params); crtc_state 2697 drivers/gpu/drm/i915/display/intel_dpll_mgr.c static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, crtc_state 2700 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 2702 drivers/gpu/drm/i915/display/intel_dpll_mgr.c int clock = crtc_state->port_clock; crtc_state 2710 drivers/gpu/drm/i915/display/intel_dpll_mgr.c bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); crtc_state 2870 drivers/gpu/drm/i915/display/intel_dpll_mgr.c void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, crtc_state 2874 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->icl_port_dplls[port_dpll_id]; crtc_state 2876 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = port_dpll->pll; crtc_state 2877 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state = port_dpll->hw_state; crtc_state 2884 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc_state *crtc_state = crtc_state 2898 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_set_active_port_dpll(crtc_state, port_dpll_id); crtc_state 2905 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc_state *crtc_state = crtc_state 2908 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; crtc_state 2913 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { crtc_state 2946 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc_state *crtc_state = crtc_state 2951 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; crtc_state 2952 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { crtc_state 2969 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; crtc_state 2970 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) { crtc_state 2993 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; crtc_state 365 drivers/gpu/drm/i915/display/intel_dpll_mgr.h void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, crtc_state 370 drivers/gpu/drm/i915/display/intel_dpll_mgr.h void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state); crtc_state 371 drivers/gpu/drm/i915/display/intel_dpll_mgr.h void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); crtc_state 372 drivers/gpu/drm/i915/display/intel_dpll_mgr.h void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); crtc_state 113 drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c static void dcs_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 658 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_crtc_state *crtc_state, crtc_state 669 drivers/gpu/drm/i915/display/intel_fbc.c cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags; crtc_state 671 drivers/gpu/drm/i915/display/intel_fbc.c cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate; crtc_state 857 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_crtc_state *crtc_state, crtc_state 877 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_update_state_cache(crtc, crtc_state, plane_state); crtc_state 1048 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_crtc_state *crtc_state; crtc_state 1057 drivers/gpu/drm/i915/display/intel_fbc.c crtc_state = intel_atomic_get_new_crtc_state(state, crtc); crtc_state 1059 drivers/gpu/drm/i915/display/intel_fbc.c crtc_state->enable_fbc = true; crtc_state 1083 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_crtc_state *crtc_state, crtc_state 1097 drivers/gpu/drm/i915/display/intel_fbc.c WARN_ON(!crtc_state->enable_fbc); crtc_state 1103 drivers/gpu/drm/i915/display/intel_fbc.c if (!crtc_state->enable_fbc) crtc_state 1109 drivers/gpu/drm/i915/display/intel_fbc.c intel_fbc_update_state_cache(crtc, crtc_state, plane_state); crtc_state 23 drivers/gpu/drm/i915/display/intel_fbc.h struct intel_crtc_state *crtc_state, crtc_state 29 drivers/gpu/drm/i915/display/intel_fbc.h struct intel_crtc_state *crtc_state, crtc_state 1951 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_crtc_state *crtc_state; crtc_state 1976 drivers/gpu/drm/i915/display/intel_hdcp.c crtc_state = drm_atomic_get_new_crtc_state(new_state->state, crtc_state 1978 drivers/gpu/drm/i915/display/intel_hdcp.c crtc_state->mode_changed = true; crtc_state 205 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 240 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 276 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 282 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 313 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 318 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 353 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 359 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 393 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 398 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 429 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 435 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 466 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 471 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 505 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 511 drivers/gpu/drm/i915/display/intel_hdmi.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 538 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 543 drivers/gpu/drm/i915/display/intel_hdmi.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 594 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state) crtc_state 601 drivers/gpu/drm/i915/display/intel_hdmi.c val = dig_port->infoframes_enabled(encoder, crtc_state); crtc_state 637 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 645 drivers/gpu/drm/i915/display/intel_hdmi.c if ((crtc_state->infoframes.enable & crtc_state 662 drivers/gpu/drm/i915/display/intel_hdmi.c intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); crtc_state 666 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 674 drivers/gpu/drm/i915/display/intel_hdmi.c if ((crtc_state->infoframes.enable & crtc_state 678 drivers/gpu/drm/i915/display/intel_hdmi.c intel_dig_port->read_infoframe(encoder, crtc_state, crtc_state 698 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc_state *crtc_state, crtc_state 701 drivers/gpu/drm/i915/display/intel_hdmi.c struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; crtc_state 703 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->base.adjusted_mode; crtc_state 707 drivers/gpu/drm/i915/display/intel_hdmi.c if (!crtc_state->has_infoframe) crtc_state 710 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.enable |= crtc_state 718 drivers/gpu/drm/i915/display/intel_hdmi.c if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) crtc_state 720 drivers/gpu/drm/i915/display/intel_hdmi.c else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) crtc_state 729 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->limited_color_range ? crtc_state 746 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc_state *crtc_state, crtc_state 749 drivers/gpu/drm/i915/display/intel_hdmi.c struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; crtc_state 752 drivers/gpu/drm/i915/display/intel_hdmi.c if (!crtc_state->has_infoframe) crtc_state 755 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.enable |= crtc_state 773 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc_state *crtc_state, crtc_state 777 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.hdmi.vendor.hdmi; crtc_state 782 drivers/gpu/drm/i915/display/intel_hdmi.c if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) crtc_state 785 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.enable |= crtc_state 790 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->base.adjusted_mode); crtc_state 803 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc_state *crtc_state, crtc_state 806 drivers/gpu/drm/i915/display/intel_hdmi.c struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; crtc_state 813 drivers/gpu/drm/i915/display/intel_hdmi.c if (!crtc_state->has_infoframe) crtc_state 819 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.enable |= crtc_state 837 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 892 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 894 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.avi); crtc_state 895 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 897 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.spd); crtc_state 898 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 900 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.hdmi); crtc_state 947 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 951 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 954 drivers/gpu/drm/i915/display/intel_hdmi.c if ((crtc_state->infoframes.enable & crtc_state 959 drivers/gpu/drm/i915/display/intel_hdmi.c reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); crtc_state 967 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, crtc_state->infoframes.gcp); crtc_state 973 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc_state *crtc_state) crtc_state 976 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 979 drivers/gpu/drm/i915/display/intel_hdmi.c if ((crtc_state->infoframes.enable & crtc_state 984 drivers/gpu/drm/i915/display/intel_hdmi.c reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); crtc_state 992 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.gcp = I915_READ(reg); crtc_state 996 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc_state *crtc_state, crtc_state 1001 drivers/gpu/drm/i915/display/intel_hdmi.c if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) crtc_state 1004 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.enable |= crtc_state 1008 drivers/gpu/drm/i915/display/intel_hdmi.c if (crtc_state->pipe_bpp > 24) crtc_state 1009 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; crtc_state 1012 drivers/gpu/drm/i915/display/intel_hdmi.c if (gcp_default_phase_possible(crtc_state->pipe_bpp, crtc_state 1013 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->base.adjusted_mode)) crtc_state 1014 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; crtc_state 1019 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 1023 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1059 drivers/gpu/drm/i915/display/intel_hdmi.c if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) crtc_state 1065 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1067 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.avi); crtc_state 1068 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1070 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.spd); crtc_state 1071 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1073 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.hdmi); crtc_state 1078 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 1082 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1108 drivers/gpu/drm/i915/display/intel_hdmi.c if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) crtc_state 1114 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1116 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.avi); crtc_state 1117 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1119 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.spd); crtc_state 1120 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1122 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.hdmi); crtc_state 1127 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 1131 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1166 drivers/gpu/drm/i915/display/intel_hdmi.c if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) crtc_state 1172 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1174 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.avi); crtc_state 1175 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1177 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.spd); crtc_state 1178 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1180 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.hdmi); crtc_state 1185 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state, crtc_state 1189 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); crtc_state 1193 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->cpu_transcoder); crtc_state 1206 drivers/gpu/drm/i915/display/intel_hdmi.c if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) crtc_state 1212 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1214 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.avi); crtc_state 1215 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1217 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.spd); crtc_state 1218 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1220 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.hdmi); crtc_state 1221 drivers/gpu/drm/i915/display/intel_hdmi.c intel_write_infoframe(encoder, crtc_state, crtc_state 1223 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->infoframes.drm); crtc_state 1719 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *crtc_state) crtc_state 1723 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1725 drivers/gpu/drm/i915/display/intel_hdmi.c const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; crtc_state 1731 drivers/gpu/drm/i915/display/intel_hdmi.c if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) crtc_state 1738 drivers/gpu/drm/i915/display/intel_hdmi.c if (crtc_state->pipe_bpp > 24) crtc_state 1743 drivers/gpu/drm/i915/display/intel_hdmi.c if (crtc_state->has_hdmi_sink) crtc_state 2191 drivers/gpu/drm/i915/display/intel_hdmi.c static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, crtc_state 2195 drivers/gpu/drm/i915/display/intel_hdmi.c to_i915(crtc_state->base.crtc->dev); crtc_state 2196 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_atomic_state *state = crtc_state->base.state; crtc_state 2200 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->base.adjusted_mode; crtc_state 2209 drivers/gpu/drm/i915/display/intel_hdmi.c if (crtc_state->pipe_bpp < bpc * 3) crtc_state 2212 drivers/gpu/drm/i915/display/intel_hdmi.c if (!crtc_state->has_hdmi_sink) crtc_state 2219 drivers/gpu/drm/i915/display/intel_hdmi.c if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) crtc_state 2225 drivers/gpu/drm/i915/display/intel_hdmi.c if (connector_state->crtc != crtc_state->base.crtc) crtc_state 2228 drivers/gpu/drm/i915/display/intel_hdmi.c if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { crtc_state 2253 drivers/gpu/drm/i915/display/intel_hdmi.c if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && crtc_state 42 drivers/gpu/drm/i915/display/intel_hdmi.h const struct intel_crtc_state *crtc_state); crtc_state 45 drivers/gpu/drm/i915/display/intel_hdmi.h struct intel_crtc_state *crtc_state); crtc_state 47 drivers/gpu/drm/i915/display/intel_hdmi.h const struct intel_crtc_state *crtc_state, crtc_state 188 drivers/gpu/drm/i915/display/intel_lspcon.c struct intel_crtc_state *crtc_state) crtc_state 192 drivers/gpu/drm/i915/display/intel_lspcon.c &crtc_state->base.adjusted_mode; crtc_state 196 drivers/gpu/drm/i915/display/intel_lspcon.c crtc_state->port_clock /= 2; crtc_state 197 drivers/gpu/drm/i915/display/intel_lspcon.c crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; crtc_state 198 drivers/gpu/drm/i915/display/intel_lspcon.c crtc_state->lspcon_downsampling = true; crtc_state 432 drivers/gpu/drm/i915/display/intel_lspcon.c const struct intel_crtc_state *crtc_state, crtc_state 460 drivers/gpu/drm/i915/display/intel_lspcon.c const struct intel_crtc_state *crtc_state, crtc_state 469 drivers/gpu/drm/i915/display/intel_lspcon.c const struct intel_crtc_state *crtc_state, crtc_state 478 drivers/gpu/drm/i915/display/intel_lspcon.c &crtc_state->base.adjusted_mode; crtc_state 495 drivers/gpu/drm/i915/display/intel_lspcon.c if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { crtc_state 496 drivers/gpu/drm/i915/display/intel_lspcon.c if (crtc_state->lspcon_downsampling) crtc_state 507 drivers/gpu/drm/i915/display/intel_lspcon.c crtc_state->limited_color_range ? crtc_state 517 drivers/gpu/drm/i915/display/intel_lspcon.c dig_port->write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, crtc_state 22 drivers/gpu/drm/i915/display/intel_lspcon.h const struct intel_crtc_state *crtc_state, crtc_state 26 drivers/gpu/drm/i915/display/intel_lspcon.h const struct intel_crtc_state *crtc_state, crtc_state 31 drivers/gpu/drm/i915/display/intel_lspcon.h const struct intel_crtc_state *crtc_state, crtc_state 36 drivers/gpu/drm/i915/display/intel_lspcon.h struct intel_crtc_state *crtc_state); crtc_state 874 drivers/gpu/drm/i915/display/intel_panel.c static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 924 drivers/gpu/drm/i915/display/intel_panel.c static void pch_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 930 drivers/gpu/drm/i915/display/intel_panel.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 970 drivers/gpu/drm/i915/display/intel_panel.c static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 1009 drivers/gpu/drm/i915/display/intel_panel.c static void i965_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 1044 drivers/gpu/drm/i915/display/intel_panel.c static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 1050 drivers/gpu/drm/i915/display/intel_panel.c enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; crtc_state 1074 drivers/gpu/drm/i915/display/intel_panel.c static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 1080 drivers/gpu/drm/i915/display/intel_panel.c enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; crtc_state 1122 drivers/gpu/drm/i915/display/intel_panel.c static void cnp_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 1153 drivers/gpu/drm/i915/display/intel_panel.c static void pwm_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 1163 drivers/gpu/drm/i915/display/intel_panel.c static void __intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 1180 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.enable(crtc_state, conn_state); crtc_state 1186 drivers/gpu/drm/i915/display/intel_panel.c void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 1192 drivers/gpu/drm/i915/display/intel_panel.c enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; crtc_state 1201 drivers/gpu/drm/i915/display/intel_panel.c __intel_panel_enable_backlight(crtc_state, conn_state); crtc_state 1880 drivers/gpu/drm/i915/display/intel_panel.c const struct intel_crtc_state *crtc_state, crtc_state 1892 drivers/gpu/drm/i915/display/intel_panel.c __intel_panel_enable_backlight(crtc_state, conn_state); crtc_state 38 drivers/gpu/drm/i915/display/intel_panel.h void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state, crtc_state 41 drivers/gpu/drm/i915/display/intel_panel.h const struct intel_crtc_state *crtc_state, crtc_state 76 drivers/gpu/drm/i915/display/intel_psr.c const struct intel_crtc_state *crtc_state) crtc_state 79 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(crtc_state->dsc_params.compression_enable && crtc_state 80 drivers/gpu/drm/i915/display/intel_psr.c crtc_state->has_psr2); crtc_state 87 drivers/gpu/drm/i915/display/intel_psr.c return crtc_state->has_psr2; crtc_state 342 drivers/gpu/drm/i915/display/intel_psr.c const struct intel_crtc_state *crtc_state) crtc_state 370 drivers/gpu/drm/i915/display/intel_psr.c crtc_state, crtc_state 537 drivers/gpu/drm/i915/display/intel_psr.c struct intel_crtc_state *crtc_state) crtc_state 540 drivers/gpu/drm/i915/display/intel_psr.c int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay; crtc_state 541 drivers/gpu/drm/i915/display/intel_psr.c int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; crtc_state 552 drivers/gpu/drm/i915/display/intel_psr.c if (crtc_state->dsc_params.compression_enable) { crtc_state 584 drivers/gpu/drm/i915/display/intel_psr.c if (crtc_state->crc_enabled) { crtc_state 593 drivers/gpu/drm/i915/display/intel_psr.c struct intel_crtc_state *crtc_state) crtc_state 598 drivers/gpu/drm/i915/display/intel_psr.c &crtc_state->base.adjusted_mode; crtc_state 643 drivers/gpu/drm/i915/display/intel_psr.c crtc_state->has_psr = true; crtc_state 644 drivers/gpu/drm/i915/display/intel_psr.c crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); crtc_state 686 drivers/gpu/drm/i915/display/intel_psr.c const struct intel_crtc_state *crtc_state) crtc_state 689 drivers/gpu/drm/i915/display/intel_psr.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 727 drivers/gpu/drm/i915/display/intel_psr.c const struct intel_crtc_state *crtc_state) crtc_state 733 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); crtc_state 735 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; crtc_state 739 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_setup_vsc(intel_dp, crtc_state); crtc_state 741 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_enable_source(intel_dp, crtc_state); crtc_state 755 drivers/gpu/drm/i915/display/intel_psr.c const struct intel_crtc_state *crtc_state) crtc_state 759 drivers/gpu/drm/i915/display/intel_psr.c if (!crtc_state->has_psr) crtc_state 774 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_enable_locked(dev_priv, crtc_state); crtc_state 895 drivers/gpu/drm/i915/display/intel_psr.c const struct intel_crtc_state *crtc_state) crtc_state 906 drivers/gpu/drm/i915/display/intel_psr.c enable = crtc_state->has_psr && psr_global_enabled(psr->debug); crtc_state 907 drivers/gpu/drm/i915/display/intel_psr.c psr2_enable = intel_psr2_enabled(dev_priv, crtc_state); crtc_state 911 drivers/gpu/drm/i915/display/intel_psr.c if (crtc_state->crc_enabled && psr->enabled) crtc_state 930 drivers/gpu/drm/i915/display/intel_psr.c intel_psr_enable_locked(dev_priv, crtc_state); crtc_state 1017 drivers/gpu/drm/i915/display/intel_psr.c struct drm_crtc_state *crtc_state; crtc_state 1020 drivers/gpu/drm/i915/display/intel_psr.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 1021 drivers/gpu/drm/i915/display/intel_psr.c if (IS_ERR(crtc_state)) { crtc_state 1022 drivers/gpu/drm/i915/display/intel_psr.c err = PTR_ERR(crtc_state); crtc_state 1026 drivers/gpu/drm/i915/display/intel_psr.c intel_crtc_state = to_intel_crtc_state(crtc_state); crtc_state 1028 drivers/gpu/drm/i915/display/intel_psr.c if (crtc_state->active && intel_crtc_state->has_psr) { crtc_state 1030 drivers/gpu/drm/i915/display/intel_psr.c crtc_state->mode_changed = true; crtc_state 18 drivers/gpu/drm/i915/display/intel_psr.h const struct intel_crtc_state *crtc_state); crtc_state 22 drivers/gpu/drm/i915/display/intel_psr.h const struct intel_crtc_state *crtc_state); crtc_state 32 drivers/gpu/drm/i915/display/intel_psr.h struct intel_crtc_state *crtc_state); crtc_state 1085 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_crtc_state *crtc_state, crtc_state 1088 drivers/gpu/drm/i915/display/intel_sdvo.c struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; crtc_state 1090 drivers/gpu/drm/i915/display/intel_sdvo.c &crtc_state->base.adjusted_mode; crtc_state 1093 drivers/gpu/drm/i915/display/intel_sdvo.c if (!crtc_state->has_hdmi_sink) crtc_state 1096 drivers/gpu/drm/i915/display/intel_sdvo.c crtc_state->infoframes.enable |= crtc_state 1108 drivers/gpu/drm/i915/display/intel_sdvo.c crtc_state->limited_color_range ? crtc_state 1120 drivers/gpu/drm/i915/display/intel_sdvo.c const struct intel_crtc_state *crtc_state) crtc_state 1123 drivers/gpu/drm/i915/display/intel_sdvo.c const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; crtc_state 1126 drivers/gpu/drm/i915/display/intel_sdvo.c if ((crtc_state->infoframes.enable & crtc_state 1143 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_crtc_state *crtc_state) crtc_state 1146 drivers/gpu/drm/i915/display/intel_sdvo.c union hdmi_infoframe *frame = &crtc_state->infoframes.avi; crtc_state 1150 drivers/gpu/drm/i915/display/intel_sdvo.c if (!crtc_state->has_hdmi_sink) crtc_state 1162 drivers/gpu/drm/i915/display/intel_sdvo.c crtc_state->infoframes.enable |= crtc_state 1428 drivers/gpu/drm/i915/display/intel_sdvo.c const struct intel_crtc_state *crtc_state, crtc_state 1432 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1433 drivers/gpu/drm/i915/display/intel_sdvo.c const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; crtc_state 1438 drivers/gpu/drm/i915/display/intel_sdvo.c const struct drm_display_mode *mode = &crtc_state->base.mode; crtc_state 1480 drivers/gpu/drm/i915/display/intel_sdvo.c if (crtc_state->has_hdmi_sink) { crtc_state 1484 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); crtc_state 1500 drivers/gpu/drm/i915/display/intel_sdvo.c switch (crtc_state->pixel_multiplier) { crtc_state 1516 drivers/gpu/drm/i915/display/intel_sdvo.c if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) crtc_state 1540 drivers/gpu/drm/i915/display/intel_sdvo.c sdvox |= (crtc_state->pixel_multiplier - 1) crtc_state 1700 drivers/gpu/drm/i915/display/intel_sdvo.c const struct intel_crtc_state *crtc_state, crtc_state 1704 drivers/gpu/drm/i915/display/intel_sdvo.c &crtc_state->base.adjusted_mode; crtc_state 2334 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_crtc_state *crtc_state = crtc_state 2337 drivers/gpu/drm/i915/display/intel_sdvo.c crtc_state->connectors_changed = true; crtc_state 2444 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_crtc_state *crtc_state = crtc_state 2448 drivers/gpu/drm/i915/display/intel_sdvo.c crtc_state->connectors_changed = true; crtc_state 360 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state, crtc_state 367 drivers/gpu/drm/i915/display/intel_sprite.c &crtc_state->scaler_state.scalers[scaler_id]; crtc_state 422 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state, crtc_state 540 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state, crtc_state 564 drivers/gpu/drm/i915/display/intel_sprite.c plane_ctl |= skl_plane_ctl_crtc(crtc_state); crtc_state 568 drivers/gpu/drm/i915/display/intel_sprite.c glk_plane_color_ctl_crtc(crtc_state); crtc_state 619 drivers/gpu/drm/i915/display/intel_sprite.c icl_program_input_csc(plane, crtc_state, plane_state); crtc_state 621 drivers/gpu/drm/i915/display/intel_sprite.c skl_write_plane_wm(plane, crtc_state); crtc_state 644 drivers/gpu/drm/i915/display/intel_sprite.c skl_program_scaler(plane, crtc_state, plane_state); crtc_state 651 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state, crtc_state 661 drivers/gpu/drm/i915/display/intel_sprite.c skl_program_plane(plane, crtc_state, plane_state, crtc_state 667 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state, crtc_state 670 drivers/gpu/drm/i915/display/intel_sprite.c skl_program_plane(plane, crtc_state, plane_state, 0, true, crtc_state 676 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state) crtc_state 688 drivers/gpu/drm/i915/display/intel_sprite.c skl_write_plane_wm(plane, crtc_state); crtc_state 828 drivers/gpu/drm/i915/display/intel_sprite.c static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) crtc_state 832 drivers/gpu/drm/i915/display/intel_sprite.c if (crtc_state->gamma_enable) crtc_state 838 drivers/gpu/drm/i915/display/intel_sprite.c static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state, crtc_state 932 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state, crtc_state 950 drivers/gpu/drm/i915/display/intel_sprite.c sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state); crtc_state 995 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state) crtc_state 1034 drivers/gpu/drm/i915/display/intel_sprite.c static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) crtc_state 1038 drivers/gpu/drm/i915/display/intel_sprite.c if (crtc_state->gamma_enable) crtc_state 1041 drivers/gpu/drm/i915/display/intel_sprite.c if (crtc_state->csc_enable) crtc_state 1047 drivers/gpu/drm/i915/display/intel_sprite.c static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, crtc_state 1149 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state, crtc_state 1168 drivers/gpu/drm/i915/display/intel_sprite.c sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state); crtc_state 1220 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state) crtc_state 1268 drivers/gpu/drm/i915/display/intel_sprite.c static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) crtc_state 1272 drivers/gpu/drm/i915/display/intel_sprite.c if (crtc_state->gamma_enable) crtc_state 1275 drivers/gpu/drm/i915/display/intel_sprite.c if (crtc_state->csc_enable) crtc_state 1281 drivers/gpu/drm/i915/display/intel_sprite.c static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, crtc_state 1402 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state, crtc_state 1421 drivers/gpu/drm/i915/display/intel_sprite.c dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state); crtc_state 1469 drivers/gpu/drm/i915/display/intel_sprite.c const struct intel_crtc_state *crtc_state) crtc_state 1522 drivers/gpu/drm/i915/display/intel_sprite.c g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, crtc_state 1530 drivers/gpu/drm/i915/display/intel_sprite.c &crtc_state->base.adjusted_mode; crtc_state 1583 drivers/gpu/drm/i915/display/intel_sprite.c g4x_sprite_check(struct intel_crtc_state *crtc_state, crtc_state 1603 drivers/gpu/drm/i915/display/intel_sprite.c &crtc_state->base, crtc_state 1620 drivers/gpu/drm/i915/display/intel_sprite.c ret = g4x_sprite_check_scaling(crtc_state, plane_state); crtc_state 1625 drivers/gpu/drm/i915/display/intel_sprite.c plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state); crtc_state 1627 drivers/gpu/drm/i915/display/intel_sprite.c plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state); crtc_state 1650 drivers/gpu/drm/i915/display/intel_sprite.c vlv_sprite_check(struct intel_crtc_state *crtc_state, crtc_state 1660 drivers/gpu/drm/i915/display/intel_sprite.c &crtc_state->base, crtc_state 1678 drivers/gpu/drm/i915/display/intel_sprite.c plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state); crtc_state 1683 drivers/gpu/drm/i915/display/intel_sprite.c static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, crtc_state 1744 drivers/gpu/drm/i915/display/intel_sprite.c if (crtc_state->base.enable && crtc_state 1745 drivers/gpu/drm/i915/display/intel_sprite.c crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && crtc_state 1757 drivers/gpu/drm/i915/display/intel_sprite.c static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, crtc_state 1764 drivers/gpu/drm/i915/display/intel_sprite.c int pipe_src_w = crtc_state->pipe_src_w; crtc_state 1804 drivers/gpu/drm/i915/display/intel_sprite.c static int skl_plane_check(struct intel_crtc_state *crtc_state, crtc_state 1814 drivers/gpu/drm/i915/display/intel_sprite.c ret = skl_plane_check_fb(crtc_state, plane_state); crtc_state 1821 drivers/gpu/drm/i915/display/intel_sprite.c max_scale = skl_max_scale(crtc_state, fb->format->format); crtc_state 1825 drivers/gpu/drm/i915/display/intel_sprite.c &crtc_state->base, crtc_state 1838 drivers/gpu/drm/i915/display/intel_sprite.c ret = skl_plane_check_dst_coordinates(crtc_state, plane_state); crtc_state 1854 drivers/gpu/drm/i915/display/intel_sprite.c plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); crtc_state 1857 drivers/gpu/drm/i915/display/intel_sprite.c plane_state->color_ctl = glk_plane_color_ctl(crtc_state, crtc_state 460 drivers/gpu/drm/i915/display/intel_vdsc.c intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) crtc_state 462 drivers/gpu/drm/i915/display/intel_vdsc.c struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev); crtc_state 463 drivers/gpu/drm/i915/display/intel_vdsc.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 484 drivers/gpu/drm/i915/display/intel_vdsc.c const struct intel_crtc_state *crtc_state) crtc_state 486 drivers/gpu/drm/i915/display/intel_vdsc.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 488 drivers/gpu/drm/i915/display/intel_vdsc.c const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; crtc_state 490 drivers/gpu/drm/i915/display/intel_vdsc.c enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; crtc_state 494 drivers/gpu/drm/i915/display/intel_vdsc.c u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; crtc_state 517 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 521 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 536 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 540 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 556 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 560 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 576 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 580 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 596 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 600 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 616 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 620 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 638 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 642 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 658 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 662 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 678 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 682 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 698 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 702 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 720 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 724 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 743 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 747 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) crtc_state 766 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) { crtc_state 785 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) { crtc_state 827 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) { crtc_state 862 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) { crtc_state 884 drivers/gpu/drm/i915/display/intel_vdsc.c const struct intel_crtc_state *crtc_state) crtc_state 888 drivers/gpu/drm/i915/display/intel_vdsc.c const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; crtc_state 897 drivers/gpu/drm/i915/display/intel_vdsc.c intel_dig_port->write_infoframe(encoder, crtc_state, crtc_state 903 drivers/gpu/drm/i915/display/intel_vdsc.c const struct intel_crtc_state *crtc_state) crtc_state 905 drivers/gpu/drm/i915/display/intel_vdsc.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 912 drivers/gpu/drm/i915/display/intel_vdsc.c if (!crtc_state->dsc_params.compression_enable) crtc_state 917 drivers/gpu/drm/i915/display/intel_vdsc.c intel_dsc_power_domain(crtc_state)); crtc_state 919 drivers/gpu/drm/i915/display/intel_vdsc.c intel_configure_pps_for_dsc_encoder(encoder, crtc_state); crtc_state 921 drivers/gpu/drm/i915/display/intel_vdsc.c intel_dp_write_dsc_pps_sdp(encoder, crtc_state); crtc_state 923 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { crtc_state 931 drivers/gpu/drm/i915/display/intel_vdsc.c if (crtc_state->dsc_params.dsc_split) { crtc_state 14 drivers/gpu/drm/i915/display/intel_vdsc.h const struct intel_crtc_state *crtc_state); crtc_state 15 drivers/gpu/drm/i915/display/intel_vdsc.h void intel_dsc_disable(const struct intel_crtc_state *crtc_state); crtc_state 19 drivers/gpu/drm/i915/display/intel_vdsc.h intel_dsc_power_domain(const struct intel_crtc_state *crtc_state); crtc_state 624 drivers/gpu/drm/i915/display/vlv_dsi.c const struct intel_crtc_state *crtc_state) crtc_state 627 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 2968 drivers/gpu/drm/i915/i915_debugfs.c struct intel_crtc_state *crtc_state = crtc_state 2976 drivers/gpu/drm/i915/i915_debugfs.c entry = &crtc_state->wm.skl.plane_ddb_y[plane_id]; crtc_state 2982 drivers/gpu/drm/i915/i915_debugfs.c entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; crtc_state 4173 drivers/gpu/drm/i915/i915_debugfs.c struct intel_crtc_state *crtc_state; crtc_state 4182 drivers/gpu/drm/i915/i915_debugfs.c crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 4184 drivers/gpu/drm/i915/i915_debugfs.c if (!crtc_state->base.active || crtc_state 4185 drivers/gpu/drm/i915/i915_debugfs.c !crtc_state->has_drrs) crtc_state 4188 drivers/gpu/drm/i915/i915_debugfs.c commit = crtc_state->base.commit; crtc_state 4200 drivers/gpu/drm/i915/i915_debugfs.c if (!(crtc_state->base.connector_mask & crtc_state 4214 drivers/gpu/drm/i915/i915_debugfs.c crtc_state); crtc_state 4217 drivers/gpu/drm/i915/i915_debugfs.c crtc_state); crtc_state 4252 drivers/gpu/drm/i915/i915_debugfs.c struct intel_crtc_state *crtc_state; crtc_state 4258 drivers/gpu/drm/i915/i915_debugfs.c crtc_state = to_intel_crtc_state(intel_crtc->base.state); crtc_state 4259 drivers/gpu/drm/i915/i915_debugfs.c commit = crtc_state->base.commit; crtc_state 4266 drivers/gpu/drm/i915/i915_debugfs.c if (!ret && crtc_state->base.active) { crtc_state 4270 drivers/gpu/drm/i915/i915_debugfs.c intel_crtc_arm_fifo_underrun(intel_crtc, crtc_state); crtc_state 4495 drivers/gpu/drm/i915/i915_debugfs.c struct intel_crtc_state *crtc_state = NULL; crtc_state 4529 drivers/gpu/drm/i915/i915_debugfs.c crtc_state = to_intel_crtc_state(crtc->state); crtc_state 4531 drivers/gpu/drm/i915/i915_debugfs.c yesno(crtc_state->dsc_params.compression_enable)); crtc_state 264 drivers/gpu/drm/i915/i915_drv.h int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); crtc_state 265 drivers/gpu/drm/i915/i915_drv.h int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); crtc_state 267 drivers/gpu/drm/i915/i915_drv.h struct intel_crtc_state *crtc_state); crtc_state 269 drivers/gpu/drm/i915/i915_drv.h struct intel_crtc_state *crtc_state); crtc_state 271 drivers/gpu/drm/i915/i915_drv.h struct intel_crtc_state *crtc_state); crtc_state 282 drivers/gpu/drm/i915/i915_drv.h struct intel_crtc_state *crtc_state); crtc_state 289 drivers/gpu/drm/i915/i915_drv.h const struct intel_crtc_state *crtc_state, crtc_state 295 drivers/gpu/drm/i915/i915_drv.h const struct intel_crtc_state *crtc_state); crtc_state 304 drivers/gpu/drm/i915/i915_drv.h int (*color_check)(struct intel_crtc_state *crtc_state); crtc_state 311 drivers/gpu/drm/i915/i915_drv.h void (*color_commit)(const struct intel_crtc_state *crtc_state); crtc_state 318 drivers/gpu/drm/i915/i915_drv.h void (*load_luts)(const struct intel_crtc_state *crtc_state); crtc_state 319 drivers/gpu/drm/i915/i915_drv.h void (*read_luts)(struct intel_crtc_state *crtc_state); crtc_state 493 drivers/gpu/drm/i915/intel_pm.c static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) crtc_state 495 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 497 drivers/gpu/drm/i915/intel_pm.c struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; crtc_state 823 drivers/gpu/drm/i915/intel_pm.c static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state, crtc_state 829 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.active) crtc_state 1111 drivers/gpu/drm/i915/intel_pm.c static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state, crtc_state 1118 drivers/gpu/drm/i915/intel_pm.c &crtc_state->base.adjusted_mode; crtc_state 1125 drivers/gpu/drm/i915/intel_pm.c if (!intel_wm_plane_visible(crtc_state, plane_state)) crtc_state 1175 drivers/gpu/drm/i915/intel_pm.c static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state, crtc_state 1178 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 1182 drivers/gpu/drm/i915/intel_pm.c struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; crtc_state 1191 drivers/gpu/drm/i915/intel_pm.c static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state, crtc_state 1194 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 1201 drivers/gpu/drm/i915/intel_pm.c struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; crtc_state 1210 drivers/gpu/drm/i915/intel_pm.c static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state, crtc_state 1214 drivers/gpu/drm/i915/intel_pm.c static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, crtc_state 1223 drivers/gpu/drm/i915/intel_pm.c if (!intel_wm_plane_visible(crtc_state, plane_state)) { crtc_state 1224 drivers/gpu/drm/i915/intel_pm.c dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0); crtc_state 1226 drivers/gpu/drm/i915/intel_pm.c dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0); crtc_state 1231 drivers/gpu/drm/i915/intel_pm.c struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; crtc_state 1234 drivers/gpu/drm/i915/intel_pm.c wm = g4x_compute_wm(crtc_state, plane_state, level); crtc_state 1247 drivers/gpu/drm/i915/intel_pm.c wm = ilk_compute_fbc_wm(crtc_state, plane_state, crtc_state 1263 drivers/gpu/drm/i915/intel_pm.c dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); crtc_state 1266 drivers/gpu/drm/i915/intel_pm.c dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX); crtc_state 1272 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id], crtc_state 1273 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id], crtc_state 1274 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]); crtc_state 1278 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc, crtc_state 1279 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc); crtc_state 1285 drivers/gpu/drm/i915/intel_pm.c static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state, crtc_state 1288 drivers/gpu/drm/i915/intel_pm.c const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; crtc_state 1293 drivers/gpu/drm/i915/intel_pm.c static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, crtc_state 1296 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 1301 drivers/gpu/drm/i915/intel_pm.c return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) && crtc_state 1302 drivers/gpu/drm/i915/intel_pm.c g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) && crtc_state 1303 drivers/gpu/drm/i915/intel_pm.c g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level); crtc_state 1332 drivers/gpu/drm/i915/intel_pm.c static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) crtc_state 1334 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1336 drivers/gpu/drm/i915/intel_pm.c to_intel_atomic_state(crtc_state->base.state); crtc_state 1337 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; crtc_state 1338 drivers/gpu/drm/i915/intel_pm.c int num_active_planes = hweight32(crtc_state->active_planes & crtc_state 1355 drivers/gpu/drm/i915/intel_pm.c if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state)) crtc_state 1363 drivers/gpu/drm/i915/intel_pm.c if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) crtc_state 1366 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; crtc_state 1372 drivers/gpu/drm/i915/intel_pm.c if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) crtc_state 1375 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; crtc_state 1384 drivers/gpu/drm/i915/intel_pm.c if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) crtc_state 1387 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; crtc_state 1563 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state) crtc_state 1565 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 1566 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1569 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate; crtc_state 1575 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state) crtc_state 1577 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 1578 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1580 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->wm.need_postvbl_update) crtc_state 1584 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; crtc_state 1620 drivers/gpu/drm/i915/intel_pm.c static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state, crtc_state 1627 drivers/gpu/drm/i915/intel_pm.c &crtc_state->base.adjusted_mode; crtc_state 1633 drivers/gpu/drm/i915/intel_pm.c if (!intel_wm_plane_visible(crtc_state, plane_state)) crtc_state 1639 drivers/gpu/drm/i915/intel_pm.c width = crtc_state->pipe_src_w; crtc_state 1663 drivers/gpu/drm/i915/intel_pm.c static int vlv_compute_fifo(struct intel_crtc_state *crtc_state) crtc_state 1665 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1667 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; crtc_state 1668 drivers/gpu/drm/i915/intel_pm.c struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; crtc_state 1669 drivers/gpu/drm/i915/intel_pm.c unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); crtc_state 1774 drivers/gpu/drm/i915/intel_pm.c static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state, crtc_state 1777 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 1782 drivers/gpu/drm/i915/intel_pm.c struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; crtc_state 1791 drivers/gpu/drm/i915/intel_pm.c static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, crtc_state 1800 drivers/gpu/drm/i915/intel_pm.c if (!intel_wm_plane_visible(crtc_state, plane_state)) { crtc_state 1801 drivers/gpu/drm/i915/intel_pm.c dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0); crtc_state 1806 drivers/gpu/drm/i915/intel_pm.c struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; crtc_state 1807 drivers/gpu/drm/i915/intel_pm.c int wm = vlv_compute_wm_level(crtc_state, plane_state, level); crtc_state 1818 drivers/gpu/drm/i915/intel_pm.c dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); crtc_state 1824 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], crtc_state 1825 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], crtc_state 1826 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); crtc_state 1831 drivers/gpu/drm/i915/intel_pm.c static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state, crtc_state 1835 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.raw[level]; crtc_state 1837 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; crtc_state 1842 drivers/gpu/drm/i915/intel_pm.c static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level) crtc_state 1844 drivers/gpu/drm/i915/intel_pm.c return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) && crtc_state 1845 drivers/gpu/drm/i915/intel_pm.c vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) && crtc_state 1846 drivers/gpu/drm/i915/intel_pm.c vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) && crtc_state 1847 drivers/gpu/drm/i915/intel_pm.c vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level); crtc_state 1850 drivers/gpu/drm/i915/intel_pm.c static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state) crtc_state 1852 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1855 drivers/gpu/drm/i915/intel_pm.c to_intel_atomic_state(crtc_state->base.state); crtc_state 1856 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; crtc_state 1858 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; crtc_state 1859 drivers/gpu/drm/i915/intel_pm.c int num_active_planes = hweight32(crtc_state->active_planes & crtc_state 1861 drivers/gpu/drm/i915/intel_pm.c bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base); crtc_state 1876 drivers/gpu/drm/i915/intel_pm.c if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state)) crtc_state 1887 drivers/gpu/drm/i915/intel_pm.c crtc_state->fifo_changed = true; crtc_state 1899 drivers/gpu/drm/i915/intel_pm.c ret = vlv_compute_fifo(crtc_state); crtc_state 1906 drivers/gpu/drm/i915/intel_pm.c crtc_state->fifo_changed = true; crtc_state 1919 drivers/gpu/drm/i915/intel_pm.c const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; crtc_state 1922 drivers/gpu/drm/i915/intel_pm.c if (!vlv_raw_crtc_wm_is_valid(crtc_state, level)) crtc_state 1958 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state) crtc_state 1960 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 1964 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; crtc_state 1967 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->fifo_changed) crtc_state 2182 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state) crtc_state 2184 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 2185 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 2188 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; crtc_state 2194 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state) crtc_state 2196 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 2197 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 2199 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->wm.need_postvbl_update) crtc_state 2203 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; crtc_state 2505 drivers/gpu/drm/i915/intel_pm.c static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state, crtc_state 2515 drivers/gpu/drm/i915/intel_pm.c if (!intel_wm_plane_visible(crtc_state, plane_state)) crtc_state 2520 drivers/gpu/drm/i915/intel_pm.c method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value); crtc_state 2525 drivers/gpu/drm/i915/intel_pm.c method2 = ilk_wm_method2(crtc_state->pixel_rate, crtc_state 2526 drivers/gpu/drm/i915/intel_pm.c crtc_state->base.adjusted_mode.crtc_htotal, crtc_state 2537 drivers/gpu/drm/i915/intel_pm.c static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state, crtc_state 2547 drivers/gpu/drm/i915/intel_pm.c if (!intel_wm_plane_visible(crtc_state, plane_state)) crtc_state 2552 drivers/gpu/drm/i915/intel_pm.c method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value); crtc_state 2553 drivers/gpu/drm/i915/intel_pm.c method2 = ilk_wm_method2(crtc_state->pixel_rate, crtc_state 2554 drivers/gpu/drm/i915/intel_pm.c crtc_state->base.adjusted_mode.crtc_htotal, crtc_state 2564 drivers/gpu/drm/i915/intel_pm.c static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state, crtc_state 2573 drivers/gpu/drm/i915/intel_pm.c if (!intel_wm_plane_visible(crtc_state, plane_state)) crtc_state 2578 drivers/gpu/drm/i915/intel_pm.c return ilk_wm_method2(crtc_state->pixel_rate, crtc_state 2579 drivers/gpu/drm/i915/intel_pm.c crtc_state->base.adjusted_mode.crtc_htotal, crtc_state 2584 drivers/gpu/drm/i915/intel_pm.c static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state, crtc_state 2590 drivers/gpu/drm/i915/intel_pm.c if (!intel_wm_plane_visible(crtc_state, plane_state)) crtc_state 2764 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state, crtc_state 2782 drivers/gpu/drm/i915/intel_pm.c result->pri_val = ilk_compute_pri_wm(crtc_state, pristate, crtc_state 2784 drivers/gpu/drm/i915/intel_pm.c result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val); crtc_state 2788 drivers/gpu/drm/i915/intel_pm.c result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency); crtc_state 2791 drivers/gpu/drm/i915/intel_pm.c result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency); crtc_state 2797 drivers/gpu/drm/i915/intel_pm.c hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state) crtc_state 2800 drivers/gpu/drm/i915/intel_pm.c to_intel_atomic_state(crtc_state->base.state); crtc_state 2802 drivers/gpu/drm/i915/intel_pm.c &crtc_state->base.adjusted_mode; crtc_state 2805 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.active) crtc_state 3113 drivers/gpu/drm/i915/intel_pm.c static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state) crtc_state 3115 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; crtc_state 3116 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 3128 drivers/gpu/drm/i915/intel_pm.c pipe_wm = &crtc_state->wm.ilk.optimal; crtc_state 3130 drivers/gpu/drm/i915/intel_pm.c drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &crtc_state->base) { crtc_state 3141 drivers/gpu/drm/i915/intel_pm.c pipe_wm->pipe_enabled = crtc_state->base.active; crtc_state 3160 drivers/gpu/drm/i915/intel_pm.c ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state, crtc_state 3164 drivers/gpu/drm/i915/intel_pm.c pipe_wm->linetime = hsw_compute_linetime_wm(crtc_state); crtc_state 3174 drivers/gpu/drm/i915/intel_pm.c ilk_compute_wm_level(dev_priv, intel_crtc, level, crtc_state, crtc_state 3754 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state; crtc_state 3785 drivers/gpu/drm/i915/intel_pm.c crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 3792 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane->id]; crtc_state 3823 drivers/gpu/drm/i915/intel_pm.c const struct intel_crtc_state *crtc_state, crtc_state 3837 drivers/gpu/drm/i915/intel_pm.c adjusted_mode = &crtc_state->base.adjusted_mode; crtc_state 3860 drivers/gpu/drm/i915/intel_pm.c const struct intel_crtc_state *crtc_state, crtc_state 3866 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; crtc_state 3868 drivers/gpu/drm/i915/intel_pm.c struct drm_crtc *for_crtc = crtc_state->base.crtc; crtc_state 3875 drivers/gpu/drm/i915/intel_pm.c if (WARN_ON(!state) || !crtc_state->base.active) { crtc_state 3887 drivers/gpu/drm/i915/intel_pm.c ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate, crtc_state 3912 drivers/gpu/drm/i915/intel_pm.c for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { crtc_state 3914 drivers/gpu/drm/i915/intel_pm.c &crtc_state->base.adjusted_mode; crtc_state 3918 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.enable) crtc_state 3934 drivers/gpu/drm/i915/intel_pm.c static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state, crtc_state 3939 drivers/gpu/drm/i915/intel_pm.c static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, crtc_state 3946 drivers/gpu/drm/i915/intel_pm.c skl_cursor_allocation(const struct intel_crtc_state *crtc_state, crtc_state 3949 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 3955 drivers/gpu/drm/i915/intel_pm.c ret = skl_compute_wm_params(crtc_state, 256, crtc_state 3959 drivers/gpu/drm/i915/intel_pm.c crtc_state->pixel_rate, &wp, 0); crtc_state 3963 drivers/gpu/drm/i915/intel_pm.c skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm); crtc_state 4071 drivers/gpu/drm/i915/intel_pm.c skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state, crtc_state 4079 drivers/gpu/drm/i915/intel_pm.c if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state))) crtc_state 4113 drivers/gpu/drm/i915/intel_pm.c skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state) crtc_state 4117 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.enable) crtc_state 4120 drivers/gpu/drm/i915/intel_pm.c if (crtc_state->pch_pfit.enabled) { crtc_state 4122 drivers/gpu/drm/i915/intel_pm.c u32 pfit_size = crtc_state->pch_pfit.size; crtc_state 4126 drivers/gpu/drm/i915/intel_pm.c src_w = crtc_state->pipe_src_w; crtc_state 4127 drivers/gpu/drm/i915/intel_pm.c src_h = crtc_state->pipe_src_h; crtc_state 4146 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state) crtc_state 4149 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; crtc_state 4157 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.enable) crtc_state 4160 drivers/gpu/drm/i915/intel_pm.c drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) { crtc_state 4167 drivers/gpu/drm/i915/intel_pm.c if (!intel_wm_plane_visible(crtc_state, plane_state)) crtc_state 4173 drivers/gpu/drm/i915/intel_pm.c plane_downscale = skl_plane_downscale_amount(crtc_state, plane_state); crtc_state 4181 drivers/gpu/drm/i915/intel_pm.c pipe_downscale = skl_pipe_downscale_amount(crtc_state); crtc_state 4185 drivers/gpu/drm/i915/intel_pm.c crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; crtc_state 4202 drivers/gpu/drm/i915/intel_pm.c skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, crtc_state 4241 drivers/gpu/drm/i915/intel_pm.c down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state); crtc_state 4250 drivers/gpu/drm/i915/intel_pm.c skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state, crtc_state 4254 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; crtc_state 4263 drivers/gpu/drm/i915/intel_pm.c drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) { crtc_state 4270 drivers/gpu/drm/i915/intel_pm.c rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0); crtc_state 4275 drivers/gpu/drm/i915/intel_pm.c rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1); crtc_state 4284 drivers/gpu/drm/i915/intel_pm.c icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state, crtc_state 4291 drivers/gpu/drm/i915/intel_pm.c if (WARN_ON(!crtc_state->base.state)) crtc_state 4295 drivers/gpu/drm/i915/intel_pm.c drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) { crtc_state 4302 drivers/gpu/drm/i915/intel_pm.c rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0); crtc_state 4319 drivers/gpu/drm/i915/intel_pm.c rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0); crtc_state 4324 drivers/gpu/drm/i915/intel_pm.c rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1); crtc_state 4334 drivers/gpu/drm/i915/intel_pm.c skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, crtc_state 4337 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; crtc_state 4338 drivers/gpu/drm/i915/intel_pm.c struct drm_crtc *crtc = crtc_state->base.crtc; crtc_state 4341 drivers/gpu/drm/i915/intel_pm.c struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb; crtc_state 4354 drivers/gpu/drm/i915/intel_pm.c memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); crtc_state 4355 drivers/gpu/drm/i915/intel_pm.c memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv)); crtc_state 4360 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.active) { crtc_state 4367 drivers/gpu/drm/i915/intel_pm.c icl_get_total_relative_data_rate(crtc_state, crtc_state 4371 drivers/gpu/drm/i915/intel_pm.c skl_get_total_relative_data_rate(crtc_state, crtc_state 4376 drivers/gpu/drm/i915/intel_pm.c skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate, crtc_state 4383 drivers/gpu/drm/i915/intel_pm.c total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active); crtc_state 4385 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start = crtc_state 4387 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end; crtc_state 4400 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; crtc_state 4435 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; crtc_state 4474 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.plane_ddb_y[plane_id]; crtc_state 4476 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.plane_ddb_uv[plane_id]; crtc_state 4507 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; crtc_state 4544 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; crtc_state 4596 drivers/gpu/drm/i915/intel_pm.c intel_get_linetime_us(const struct intel_crtc_state *crtc_state) crtc_state 4602 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.active) crtc_state 4605 drivers/gpu/drm/i915/intel_pm.c pixel_rate = crtc_state->pixel_rate; crtc_state 4610 drivers/gpu/drm/i915/intel_pm.c crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal; crtc_state 4617 drivers/gpu/drm/i915/intel_pm.c skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state, crtc_state 4624 drivers/gpu/drm/i915/intel_pm.c if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state))) crtc_state 4631 drivers/gpu/drm/i915/intel_pm.c adjusted_pixel_rate = crtc_state->pixel_rate; crtc_state 4632 drivers/gpu/drm/i915/intel_pm.c downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state); crtc_state 4639 drivers/gpu/drm/i915/intel_pm.c skl_compute_wm_params(const struct intel_crtc_state *crtc_state, crtc_state 4645 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 4724 drivers/gpu/drm/i915/intel_pm.c intel_get_linetime_us(crtc_state)); crtc_state 4730 drivers/gpu/drm/i915/intel_pm.c skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state, crtc_state 4749 drivers/gpu/drm/i915/intel_pm.c return skl_compute_wm_params(crtc_state, width, crtc_state 4752 drivers/gpu/drm/i915/intel_pm.c skl_adjusted_plane_pixel_rate(crtc_state, plane_state), crtc_state 4765 drivers/gpu/drm/i915/intel_pm.c static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, crtc_state 4771 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 4797 drivers/gpu/drm/i915/intel_pm.c crtc_state->base.adjusted_mode.crtc_htotal, crtc_state 4804 drivers/gpu/drm/i915/intel_pm.c if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal / crtc_state 4891 drivers/gpu/drm/i915/intel_pm.c skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, crtc_state 4895 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 4902 drivers/gpu/drm/i915/intel_pm.c skl_compute_plane_wm(crtc_state, level, wm_params, crtc_state 4910 drivers/gpu/drm/i915/intel_pm.c skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state) crtc_state 4912 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; crtc_state 4917 drivers/gpu/drm/i915/intel_pm.c linetime_us = intel_get_linetime_us(crtc_state); crtc_state 4927 drivers/gpu/drm/i915/intel_pm.c static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state, crtc_state 4931 drivers/gpu/drm/i915/intel_pm.c struct drm_device *dev = crtc_state->base.crtc->dev; crtc_state 4986 drivers/gpu/drm/i915/intel_pm.c static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state, crtc_state 4990 drivers/gpu/drm/i915/intel_pm.c struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; crtc_state 4994 drivers/gpu/drm/i915/intel_pm.c ret = skl_compute_plane_wm_params(crtc_state, plane_state, crtc_state 4999 drivers/gpu/drm/i915/intel_pm.c skl_compute_wm_levels(crtc_state, &wm_params, wm->wm); crtc_state 5000 drivers/gpu/drm/i915/intel_pm.c skl_compute_transition_wm(crtc_state, &wm_params, wm); crtc_state 5005 drivers/gpu/drm/i915/intel_pm.c static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state, crtc_state 5009 drivers/gpu/drm/i915/intel_pm.c struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; crtc_state 5016 drivers/gpu/drm/i915/intel_pm.c ret = skl_compute_plane_wm_params(crtc_state, plane_state, crtc_state 5021 drivers/gpu/drm/i915/intel_pm.c skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm); crtc_state 5026 drivers/gpu/drm/i915/intel_pm.c static int skl_build_plane_wm(struct intel_crtc_state *crtc_state, crtc_state 5034 drivers/gpu/drm/i915/intel_pm.c if (!intel_wm_plane_visible(crtc_state, plane_state)) crtc_state 5037 drivers/gpu/drm/i915/intel_pm.c ret = skl_build_plane_wm_single(crtc_state, plane_state, crtc_state 5043 drivers/gpu/drm/i915/intel_pm.c ret = skl_build_plane_wm_uv(crtc_state, plane_state, crtc_state 5052 drivers/gpu/drm/i915/intel_pm.c static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, crtc_state 5066 drivers/gpu/drm/i915/intel_pm.c WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)); crtc_state 5070 drivers/gpu/drm/i915/intel_pm.c ret = skl_build_plane_wm_single(crtc_state, plane_state, crtc_state 5075 drivers/gpu/drm/i915/intel_pm.c ret = skl_build_plane_wm_single(crtc_state, plane_state, crtc_state 5079 drivers/gpu/drm/i915/intel_pm.c } else if (intel_wm_plane_visible(crtc_state, plane_state)) { crtc_state 5080 drivers/gpu/drm/i915/intel_pm.c ret = skl_build_plane_wm_single(crtc_state, plane_state, crtc_state 5089 drivers/gpu/drm/i915/intel_pm.c static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state) crtc_state 5091 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 5092 drivers/gpu/drm/i915/intel_pm.c struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; crtc_state 5104 drivers/gpu/drm/i915/intel_pm.c &crtc_state->base) { crtc_state 5109 drivers/gpu/drm/i915/intel_pm.c ret = icl_build_plane_wm(crtc_state, plane_state); crtc_state 5111 drivers/gpu/drm/i915/intel_pm.c ret = skl_build_plane_wm(crtc_state, plane_state); crtc_state 5116 drivers/gpu/drm/i915/intel_pm.c pipe_wm->linetime = skl_compute_linetime_wm(crtc_state); crtc_state 5148 drivers/gpu/drm/i915/intel_pm.c const struct intel_crtc_state *crtc_state) crtc_state 5155 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; crtc_state 5157 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.plane_ddb_y[plane_id]; crtc_state 5159 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.plane_ddb_uv[plane_id]; crtc_state 5184 drivers/gpu/drm/i915/intel_pm.c const struct intel_crtc_state *crtc_state) crtc_state 5191 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; crtc_state 5193 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.plane_ddb_y[plane_id]; crtc_state 5270 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state; crtc_state 5273 drivers/gpu/drm/i915/intel_pm.c for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) crtc_state 5460 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state; crtc_state 5479 drivers/gpu/drm/i915/intel_pm.c for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) crtc_state 5532 drivers/gpu/drm/i915/intel_pm.c crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); crtc_state 5533 drivers/gpu/drm/i915/intel_pm.c if (IS_ERR(crtc_state)) crtc_state 5534 drivers/gpu/drm/i915/intel_pm.c return PTR_ERR(crtc_state); crtc_state 5649 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state) crtc_state 5651 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5653 drivers/gpu/drm/i915/intel_pm.c struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; crtc_state 5663 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state) crtc_state 5665 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5675 drivers/gpu/drm/i915/intel_pm.c if (crtc_state->base.active_changed) crtc_state 5676 drivers/gpu/drm/i915/intel_pm.c skl_atomic_update_crtc_wm(state, crtc_state); crtc_state 5732 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state) crtc_state 5734 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 5735 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5738 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate; crtc_state 5744 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state) crtc_state 5746 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); crtc_state 5747 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); crtc_state 5749 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->wm.need_postvbl_update) crtc_state 5753 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.ilk = crtc_state->wm.ilk.optimal; crtc_state 5810 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state; crtc_state 5814 drivers/gpu/drm/i915/intel_pm.c crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 5816 drivers/gpu/drm/i915/intel_pm.c skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); crtc_state 5833 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); crtc_state 5834 drivers/gpu/drm/i915/intel_pm.c struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal; crtc_state 5996 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state = crtc_state 6024 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; crtc_state 6031 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; crtc_state 6040 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; crtc_state 6048 drivers/gpu/drm/i915/intel_pm.c g4x_raw_plane_wm_set(crtc_state, level, crtc_state 6050 drivers/gpu/drm/i915/intel_pm.c g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX); crtc_state 6052 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.optimal = *active; crtc_state 6053 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.intermediate = *active; crtc_state 6080 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state = crtc_state 6084 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; crtc_state 6093 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.g4x.raw[level]; crtc_state 6102 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.g4x.raw[level]; crtc_state 6113 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state = crtc_state 6116 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.intermediate = crtc_state 6117 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.optimal; crtc_state 6118 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; crtc_state 6172 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state = crtc_state 6176 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; crtc_state 6181 drivers/gpu/drm/i915/intel_pm.c vlv_get_fifo_size(crtc_state); crtc_state 6188 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.raw[level]; crtc_state 6204 drivers/gpu/drm/i915/intel_pm.c vlv_raw_plane_wm_set(crtc_state, level, crtc_state 6208 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.optimal = *active; crtc_state 6209 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.intermediate = *active; crtc_state 6233 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state = crtc_state 6237 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; crtc_state 6239 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; crtc_state 6248 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.raw[level]; crtc_state 6259 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state = crtc_state 6262 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.intermediate = crtc_state 6263 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.optimal; crtc_state 6264 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; crtc_state 67 drivers/gpu/drm/i915/intel_pm.h const struct intel_crtc_state *crtc_state); crtc_state 69 drivers/gpu/drm/i915/intel_pm.h const struct intel_crtc_state *crtc_state); crtc_state 128 drivers/gpu/drm/imx/dw_hdmi-imx.c struct drm_crtc_state *crtc_state, crtc_state 131 drivers/gpu/drm/imx/dw_hdmi-imx.c struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); crtc_state 246 drivers/gpu/drm/imx/imx-ldb.c struct drm_crtc_state *crtc_state, crtc_state 250 drivers/gpu/drm/imx/imx-ldb.c struct drm_display_mode *mode = &crtc_state->adjusted_mode; crtc_state 347 drivers/gpu/drm/imx/imx-ldb.c struct drm_crtc_state *crtc_state, crtc_state 350 drivers/gpu/drm/imx/imx-ldb.c struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); crtc_state 324 drivers/gpu/drm/imx/imx-tve.c struct drm_crtc_state *crtc_state, crtc_state 327 drivers/gpu/drm/imx/imx-tve.c struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); crtc_state 350 drivers/gpu/drm/imx/ipuv3-plane.c struct drm_crtc_state *crtc_state; crtc_state 365 drivers/gpu/drm/imx/ipuv3-plane.c crtc_state = crtc_state 367 drivers/gpu/drm/imx/ipuv3-plane.c if (WARN_ON(!crtc_state)) crtc_state 370 drivers/gpu/drm/imx/ipuv3-plane.c ret = drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 378 drivers/gpu/drm/imx/ipuv3-plane.c if (!crtc_state->enable) crtc_state 408 drivers/gpu/drm/imx/ipuv3-plane.c crtc_state->mode_changed = true; crtc_state 419 drivers/gpu/drm/imx/ipuv3-plane.c crtc_state->mode_changed = true; crtc_state 444 drivers/gpu/drm/imx/ipuv3-plane.c crtc_state->mode_changed = true; crtc_state 461 drivers/gpu/drm/imx/ipuv3-plane.c crtc_state->mode_changed = true; crtc_state 468 drivers/gpu/drm/imx/ipuv3-plane.c crtc_state->mode_changed = true; crtc_state 492 drivers/gpu/drm/imx/ipuv3-plane.c crtc_state->mode_changed = true; crtc_state 550 drivers/gpu/drm/imx/ipuv3-plane.c struct drm_crtc_state *crtc_state = state->crtc->state; crtc_state 599 drivers/gpu/drm/imx/ipuv3-plane.c if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) { crtc_state 746 drivers/gpu/drm/imx/ipuv3-plane.c struct drm_crtc_state *old_crtc_state, *crtc_state; crtc_state 755 drivers/gpu/drm/imx/ipuv3-plane.c for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) { crtc_state 108 drivers/gpu/drm/imx/parallel-display.c struct drm_crtc_state *crtc_state, crtc_state 111 drivers/gpu/drm/imx/parallel-display.c struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); crtc_state 389 drivers/gpu/drm/ingenic/ingenic-drm.c struct drm_crtc_state *crtc_state, crtc_state 393 drivers/gpu/drm/ingenic/ingenic-drm.c struct drm_display_mode *mode = &crtc_state->adjusted_mode; crtc_state 446 drivers/gpu/drm/ingenic/ingenic-drm.c struct drm_crtc_state *crtc_state, crtc_state 552 drivers/gpu/drm/mediatek/mtk_dpi.c struct drm_crtc_state *crtc_state, crtc_state 86 drivers/gpu/drm/mediatek/mtk_drm_plane.c struct drm_crtc_state *crtc_state; crtc_state 94 drivers/gpu/drm/mediatek/mtk_drm_plane.c crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); crtc_state 95 drivers/gpu/drm/mediatek/mtk_drm_plane.c if (IS_ERR(crtc_state)) crtc_state 96 drivers/gpu/drm/mediatek/mtk_drm_plane.c return PTR_ERR(crtc_state); crtc_state 98 drivers/gpu/drm/mediatek/mtk_drm_plane.c return drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 78 drivers/gpu/drm/meson/meson_crtc.c struct drm_crtc_state *crtc_state = crtc->state; crtc_state 83 drivers/gpu/drm/meson/meson_crtc.c if (!crtc_state) { crtc_state 93 drivers/gpu/drm/meson/meson_crtc.c writel(crtc_state->mode.hdisplay | crtc_state 94 drivers/gpu/drm/meson/meson_crtc.c crtc_state->mode.vdisplay << 16, crtc_state 98 drivers/gpu/drm/meson/meson_crtc.c (crtc_state->mode.hdisplay - 1), crtc_state 101 drivers/gpu/drm/meson/meson_crtc.c (crtc_state->mode.vdisplay - 1), crtc_state 103 drivers/gpu/drm/meson/meson_crtc.c writel_relaxed(crtc_state->mode.hdisplay << 16 | crtc_state 104 drivers/gpu/drm/meson/meson_crtc.c crtc_state->mode.vdisplay, crtc_state 114 drivers/gpu/drm/meson/meson_crtc.c struct drm_crtc_state *crtc_state = crtc->state; crtc_state 119 drivers/gpu/drm/meson/meson_crtc.c if (!crtc_state) { crtc_state 125 drivers/gpu/drm/meson/meson_crtc.c writel(crtc_state->mode.hdisplay, crtc_state 676 drivers/gpu/drm/meson/meson_dw_hdmi.c struct drm_crtc_state *crtc_state, crtc_state 90 drivers/gpu/drm/meson/meson_overlay.c struct drm_crtc_state *crtc_state; crtc_state 95 drivers/gpu/drm/meson/meson_overlay.c crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); crtc_state 96 drivers/gpu/drm/meson/meson_overlay.c if (IS_ERR(crtc_state)) crtc_state 97 drivers/gpu/drm/meson/meson_overlay.c return PTR_ERR(crtc_state); crtc_state 99 drivers/gpu/drm/meson/meson_overlay.c return drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 147 drivers/gpu/drm/meson/meson_overlay.c struct drm_crtc_state *crtc_state = priv->crtc->state; crtc_state 162 drivers/gpu/drm/meson/meson_overlay.c if (!crtc_state) { crtc_state 167 drivers/gpu/drm/meson/meson_overlay.c crtc_height = crtc_state->mode.vdisplay; crtc_state 168 drivers/gpu/drm/meson/meson_overlay.c crtc_width = crtc_state->mode.hdisplay; crtc_state 75 drivers/gpu/drm/meson/meson_plane.c struct drm_crtc_state *crtc_state; crtc_state 80 drivers/gpu/drm/meson/meson_plane.c crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); crtc_state 81 drivers/gpu/drm/meson/meson_plane.c if (IS_ERR(crtc_state)) crtc_state 82 drivers/gpu/drm/meson/meson_plane.c return PTR_ERR(crtc_state); crtc_state 89 drivers/gpu/drm/meson/meson_plane.c return drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 155 drivers/gpu/drm/meson/meson_venc_cvbs.c struct drm_crtc_state *crtc_state, crtc_state 158 drivers/gpu/drm/meson/meson_venc_cvbs.c if (meson_cvbs_get_mode(&crtc_state->mode)) crtc_state 92 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c struct dpu_crtc_state *crtc_state; crtc_state 96 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c crtc_state = to_dpu_crtc_state(crtc->state); crtc_state 99 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) { crtc_state 100 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx]; crtc_state 101 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm; crtc_state 546 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct drm_crtc_state *crtc_state, crtc_state 558 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!drm_enc || !crtc_state || !conn_state) { crtc_state 560 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c drm_enc != 0, crtc_state != 0, conn_state != 0); crtc_state 569 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c mode = &crtc_state->mode; crtc_state 570 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c adj_mode = &crtc_state->adjusted_mode; crtc_state 587 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ret = phys->ops.atomic_check(phys, crtc_state, crtc_state 608 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (drm_atomic_crtc_needs_modeset(crtc_state) crtc_state 610 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state, crtc_state 129 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h struct drm_crtc_state *crtc_state, crtc_state 286 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c struct drm_crtc_state *crtc_state; crtc_state 300 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c for_each_new_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 302 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c crtc_state->encoder_mask) { crtc_state 847 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c const struct drm_crtc_state *crtc_state = NULL; crtc_state 853 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c crtc_state = drm_atomic_get_new_crtc_state(state->state, crtc_state 857 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale, crtc_state 538 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c struct drm_crtc_state *crtc_state, crtc_state 565 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c struct drm_crtc_state *crtc_state, crtc_state 608 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c struct drm_crtc_state *crtc_state, crtc_state 616 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c if (!drm_atomic_crtc_needs_modeset(crtc_state)) crtc_state 620 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c enc->base.id, crtc_state->crtc->base.id, test_only); crtc_state 624 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c ret = _dpu_rm_populate_requirements(rm, enc, crtc_state, &reqs, crtc_state 631 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c ret = _dpu_rm_make_reservation(rm, enc, crtc_state, &reqs); crtc_state 82 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h struct drm_crtc_state *crtc_state, crtc_state 115 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c struct drm_crtc_state *crtc_state; crtc_state 118 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c for_each_new_crtc_in_state(state, crtc, crtc_state, i) crtc_state 294 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c struct drm_crtc_state *crtc_state, crtc_state 298 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state); crtc_state 313 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c if (drm_atomic_crtc_needs_modeset(crtc_state)) crtc_state 253 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state, crtc_state 301 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c ret = drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 409 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct drm_crtc_state *crtc_state; crtc_state 415 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); crtc_state 416 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c if (WARN_ON(!crtc_state)) crtc_state 419 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c return mdp5_plane_atomic_check_with_state(crtc_state, state); crtc_state 444 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct drm_crtc_state *crtc_state; crtc_state 448 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc_state 450 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c if (WARN_ON(!crtc_state)) crtc_state 453 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c if (!crtc_state->active) crtc_state 475 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c ret = drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 104 drivers/gpu/drm/msm/msm_atomic.c struct drm_crtc_state *crtc_state; crtc_state 115 drivers/gpu/drm/msm/msm_atomic.c for_each_new_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 116 drivers/gpu/drm/msm/msm_atomic.c if (drm_atomic_crtc_needs_modeset(crtc_state)) crtc_state 132 drivers/gpu/drm/msm/msm_atomic.c struct drm_crtc_state *crtc_state; crtc_state 136 drivers/gpu/drm/msm/msm_atomic.c for_each_new_crtc_in_state(state, crtc, crtc_state, i) crtc_state 101 drivers/gpu/drm/mxsfb/mxsfb_drv.c struct drm_crtc_state *crtc_state, crtc_state 664 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; crtc_state 675 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; crtc_state 677 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_state->gpio_ext = crtc_saved->gpio_ext; crtc_state 306 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_crtc_state *crtc_state, crtc_state 310 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; crtc_state 311 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_display_mode *mode = &crtc_state->mode; crtc_state 345 drivers/gpu/drm/nouveau/dispnv50/disp.c crtc_state->mode_changed = true; crtc_state 353 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_crtc_state *crtc_state, crtc_state 358 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); crtc_state 361 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, crtc_state 366 drivers/gpu/drm/nouveau/dispnv50/disp.c if (crtc_state->mode_changed || crtc_state->connectors_changed) crtc_state 774 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_crtc_state *crtc_state, crtc_state 777 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_atomic_state *state = crtc_state->state; crtc_state 781 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); crtc_state 785 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, crtc_state 790 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!crtc_state->mode_changed && !crtc_state->connectors_changed) crtc_state 799 drivers/gpu/drm/nouveau/dispnv50/disp.c const int clock = crtc_state->adjusted_mode.clock; crtc_state 994 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_crtc_state *crtc_state; crtc_state 1004 drivers/gpu/drm/nouveau/dispnv50/disp.c crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); crtc_state 1006 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!crtc_state || crtc_state 1007 drivers/gpu/drm/nouveau/dispnv50/disp.c !drm_atomic_crtc_needs_modeset(crtc_state) || crtc_state 1008 drivers/gpu/drm/nouveau/dispnv50/disp.c crtc_state->enable) crtc_state 1650 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_crtc_state *crtc_state, crtc_state 1653 drivers/gpu/drm/nouveau/dispnv50/disp.c int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); crtc_state 1656 drivers/gpu/drm/nouveau/dispnv50/disp.c crtc_state->adjusted_mode.clock *= 2; crtc_state 224 drivers/gpu/drm/omapdrm/omap_encoder.c struct drm_crtc_state *crtc_state, crtc_state 231 drivers/gpu/drm/omapdrm/omap_encoder.c &crtc_state->mode, crtc_state 232 drivers/gpu/drm/omapdrm/omap_encoder.c &crtc_state->adjusted_mode); crtc_state 102 drivers/gpu/drm/omapdrm/omap_plane.c struct drm_crtc_state *crtc_state; crtc_state 111 drivers/gpu/drm/omapdrm/omap_plane.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, state->crtc); crtc_state 113 drivers/gpu/drm/omapdrm/omap_plane.c if (WARN_ON(!crtc_state)) crtc_state 116 drivers/gpu/drm/omapdrm/omap_plane.c if (!crtc_state->enable) crtc_state 122 drivers/gpu/drm/omapdrm/omap_plane.c if (state->crtc_x + state->crtc_w > crtc_state->adjusted_mode.hdisplay) crtc_state 125 drivers/gpu/drm/omapdrm/omap_plane.c if (state->crtc_y + state->crtc_h > crtc_state->adjusted_mode.vdisplay) crtc_state 1003 drivers/gpu/drm/rcar-du/rcar_du_crtc.c struct drm_crtc_state *crtc_state; crtc_state 1027 drivers/gpu/drm/rcar-du/rcar_du_crtc.c crtc_state = drm_atomic_get_crtc_state(state, crtc); crtc_state 1028 drivers/gpu/drm/rcar-du/rcar_du_crtc.c if (!IS_ERR(crtc_state)) { crtc_state 1031 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rcrtc_state = to_rcar_crtc_state(crtc_state); crtc_state 1037 drivers/gpu/drm/rcar-du/rcar_du_crtc.c ret = PTR_ERR(crtc_state); crtc_state 389 drivers/gpu/drm/rcar-du/rcar_du_kms.c struct drm_crtc_state *crtc_state; crtc_state 399 drivers/gpu/drm/rcar-du/rcar_du_kms.c for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) { crtc_state 401 drivers/gpu/drm/rcar-du/rcar_du_kms.c to_rcar_crtc_state(crtc_state); crtc_state 570 drivers/gpu/drm/rcar-du/rcar_du_plane.c struct drm_crtc_state *crtc_state; crtc_state 583 drivers/gpu/drm/rcar-du/rcar_du_plane.c crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); crtc_state 584 drivers/gpu/drm/rcar-du/rcar_du_plane.c if (IS_ERR(crtc_state)) crtc_state 585 drivers/gpu/drm/rcar-du/rcar_du_plane.c return PTR_ERR(crtc_state); crtc_state 587 drivers/gpu/drm/rcar-du/rcar_du_plane.c ret = drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 141 drivers/gpu/drm/rcar-du/rcar_du_writeback.c struct drm_crtc_state *crtc_state, crtc_state 146 drivers/gpu/drm/rcar-du/rcar_du_writeback.c const struct drm_display_mode *mode = &crtc_state->mode; crtc_state 103 drivers/gpu/drm/rcar-du/rcar_lvds.c struct drm_crtc_state *crtc_state; crtc_state 118 drivers/gpu/drm/rcar-du/rcar_lvds.c crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); crtc_state 119 drivers/gpu/drm/rcar-du/rcar_lvds.c if (IS_ERR(crtc_state)) crtc_state 120 drivers/gpu/drm/rcar-du/rcar_lvds.c return PTR_ERR(crtc_state); crtc_state 122 drivers/gpu/drm/rcar-du/rcar_lvds.c if (crtc_state->mode.hdisplay != panel_mode->hdisplay || crtc_state 123 drivers/gpu/drm/rcar-du/rcar_lvds.c crtc_state->mode.vdisplay != panel_mode->vdisplay) crtc_state 127 drivers/gpu/drm/rcar-du/rcar_lvds.c drm_mode_copy(&crtc_state->adjusted_mode, panel_mode); crtc_state 232 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c struct drm_crtc_state *crtc_state, crtc_state 235 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); crtc_state 674 drivers/gpu/drm/rockchip/cdn-dp-core.c struct drm_crtc_state *crtc_state, crtc_state 677 drivers/gpu/drm/rockchip/cdn-dp-core.c struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); crtc_state 589 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c struct drm_crtc_state *crtc_state, crtc_state 592 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); crtc_state 297 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c struct drm_crtc_state *crtc_state, crtc_state 300 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); crtc_state 516 drivers/gpu/drm/rockchip/inno_hdmi.c struct drm_crtc_state *crtc_state, crtc_state 519 drivers/gpu/drm/rockchip/inno_hdmi.c struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); crtc_state 434 drivers/gpu/drm/rockchip/rk3066_hdmi.c struct drm_crtc_state *crtc_state, crtc_state 437 drivers/gpu/drm/rockchip/rk3066_hdmi.c struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); crtc_state 716 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_crtc_state *crtc_state; crtc_state 729 drivers/gpu/drm/rockchip/rockchip_drm_vop.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); crtc_state 730 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (WARN_ON(!crtc_state)) crtc_state 733 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 926 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_crtc_state *crtc_state; crtc_state 938 drivers/gpu/drm/rockchip/rockchip_drm_vop.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc_state 941 drivers/gpu/drm/rockchip/rockchip_drm_vop.c crtc_state = plane->crtc->state; crtc_state 943 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return drm_atomic_helper_check_plane_state(plane->state, crtc_state, crtc_state 1310 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct rockchip_crtc_state *crtc_state = crtc_state 1311 drivers/gpu/drm/rockchip/rockchip_drm_vop.c kzalloc(sizeof(*crtc_state), GFP_KERNEL); crtc_state 1316 drivers/gpu/drm/rockchip/rockchip_drm_vop.c __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); crtc_state 269 drivers/gpu/drm/rockchip/rockchip_lvds.c struct drm_crtc_state *crtc_state, crtc_state 272 drivers/gpu/drm/rockchip/rockchip_lvds.c struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); crtc_state 32 drivers/gpu/drm/rockchip/rockchip_rgb.c struct drm_crtc_state *crtc_state, crtc_state 35 drivers/gpu/drm/rockchip/rockchip_rgb.c struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); crtc_state 80 drivers/gpu/drm/selftests/test-drm_plane_helper.c const struct drm_crtc_state crtc_state = { crtc_state 103 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 114 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 127 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 133 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 145 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 150 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 160 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 164 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 175 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 186 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 197 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 209 drivers/gpu/drm/selftests/test-drm_plane_helper.c ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, crtc_state 190 drivers/gpu/drm/sti/sti_cursor.c struct drm_crtc_state *crtc_state; crtc_state 199 drivers/gpu/drm/sti/sti_cursor.c crtc_state = drm_atomic_get_crtc_state(state->state, crtc); crtc_state 200 drivers/gpu/drm/sti/sti_cursor.c mode = &crtc_state->mode; crtc_state 623 drivers/gpu/drm/sti/sti_gdp.c struct drm_crtc_state *crtc_state; crtc_state 635 drivers/gpu/drm/sti/sti_gdp.c crtc_state = drm_atomic_get_crtc_state(state->state, crtc); crtc_state 636 drivers/gpu/drm/sti/sti_gdp.c mode = &crtc_state->mode; crtc_state 1026 drivers/gpu/drm/sti/sti_hqvdp.c struct drm_crtc_state *crtc_state; crtc_state 1035 drivers/gpu/drm/sti/sti_hqvdp.c crtc_state = drm_atomic_get_crtc_state(state->state, crtc); crtc_state 1036 drivers/gpu/drm/sti/sti_hqvdp.c mode = &crtc_state->mode; crtc_state 486 drivers/gpu/drm/sun4i/sun4i_backend.c struct drm_crtc_state *crtc_state) crtc_state 490 drivers/gpu/drm/sun4i/sun4i_backend.c struct drm_atomic_state *state = crtc_state->state; crtc_state 503 drivers/gpu/drm/sun4i/sun4i_backend.c if (!crtc_state->planes_changed) crtc_state 506 drivers/gpu/drm/sun4i/sun4i_backend.c drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) { crtc_state 72 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c struct drm_crtc_state *crtc_state, crtc_state 75 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c struct drm_display_mode *mode = &crtc_state->mode; crtc_state 241 drivers/gpu/drm/sun4i/sun8i_ui_layer.c struct drm_crtc_state *crtc_state; crtc_state 247 drivers/gpu/drm/sun4i/sun8i_ui_layer.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); crtc_state 248 drivers/gpu/drm/sun4i/sun8i_ui_layer.c if (WARN_ON(!crtc_state)) crtc_state 259 drivers/gpu/drm/sun4i/sun8i_ui_layer.c return drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 326 drivers/gpu/drm/sun4i/sun8i_vi_layer.c struct drm_crtc_state *crtc_state; crtc_state 332 drivers/gpu/drm/sun4i/sun8i_vi_layer.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); crtc_state 333 drivers/gpu/drm/sun4i/sun8i_vi_layer.c if (WARN_ON(!crtc_state)) crtc_state 344 drivers/gpu/drm/sun4i/sun8i_vi_layer.c return drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 1630 drivers/gpu/drm/tegra/dc.c struct drm_crtc_state *crtc_state, crtc_state 1634 drivers/gpu/drm/tegra/dc.c struct tegra_dc_state *state = to_dc_state(crtc_state); crtc_state 152 drivers/gpu/drm/tegra/dc.h struct drm_crtc_state *crtc_state, crtc_state 946 drivers/gpu/drm/tegra/dsi.c struct drm_crtc_state *crtc_state, crtc_state 957 drivers/gpu/drm/tegra/dsi.c state->pclk = crtc_state->mode.clock * 1000; crtc_state 969 drivers/gpu/drm/tegra/dsi.c state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); crtc_state 1015 drivers/gpu/drm/tegra/dsi.c err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, crtc_state 1400 drivers/gpu/drm/tegra/hdmi.c struct drm_crtc_state *crtc_state, crtc_state 1405 drivers/gpu/drm/tegra/hdmi.c unsigned long pclk = crtc_state->mode.clock * 1000; crtc_state 1409 drivers/gpu/drm/tegra/hdmi.c err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent, crtc_state 101 drivers/gpu/drm/tegra/plane.c struct drm_crtc_state *crtc_state; crtc_state 106 drivers/gpu/drm/tegra/plane.c crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); crtc_state 107 drivers/gpu/drm/tegra/plane.c if (IS_ERR(crtc_state)) crtc_state 108 drivers/gpu/drm/tegra/plane.c return PTR_ERR(crtc_state); crtc_state 111 drivers/gpu/drm/tegra/plane.c err = drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 116 drivers/gpu/drm/tegra/plane.c tegra = to_dc_state(crtc_state); crtc_state 169 drivers/gpu/drm/tegra/rgb.c struct drm_crtc_state *crtc_state, crtc_state 174 drivers/gpu/drm/tegra/rgb.c unsigned long pclk = crtc_state->mode.clock * 1000; crtc_state 198 drivers/gpu/drm/tegra/rgb.c err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent, crtc_state 1986 drivers/gpu/drm/tegra/sor.c struct drm_crtc_state *crtc_state, crtc_state 1992 drivers/gpu/drm/tegra/sor.c unsigned long pclk = crtc_state->mode.clock * 1000; crtc_state 2011 drivers/gpu/drm/tegra/sor.c err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, crtc_state 26 drivers/gpu/drm/tilcdc/tilcdc_plane.c struct drm_crtc_state *crtc_state; crtc_state 42 drivers/gpu/drm/tilcdc/tilcdc_plane.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc_state 45 drivers/gpu/drm/tilcdc/tilcdc_plane.c if (WARN_ON(!crtc_state)) crtc_state 48 drivers/gpu/drm/tilcdc/tilcdc_plane.c if (crtc_state->mode.hdisplay != state->crtc_w || crtc_state 49 drivers/gpu/drm/tilcdc/tilcdc_plane.c crtc_state->mode.vdisplay != state->crtc_h) { crtc_state 52 drivers/gpu/drm/tilcdc/tilcdc_plane.c crtc_state->mode.hdisplay, crtc_state->mode.vdisplay, crtc_state 57 drivers/gpu/drm/tilcdc/tilcdc_plane.c pitch = crtc_state->mode.hdisplay * crtc_state 70 drivers/gpu/drm/tilcdc/tilcdc_plane.c crtc_state->mode_changed = true; crtc_state 590 drivers/gpu/drm/tiny/gm12u320.c struct drm_crtc_state *crtc_state, crtc_state 47 drivers/gpu/drm/tiny/hx8357d.c struct drm_crtc_state *crtc_state, crtc_state 177 drivers/gpu/drm/tiny/hx8357d.c mipi_dbi_enable_flush(dbidev, crtc_state, plane_state); crtc_state 183 drivers/gpu/drm/tiny/ili9225.c struct drm_crtc_state *crtc_state, crtc_state 53 drivers/gpu/drm/tiny/ili9341.c struct drm_crtc_state *crtc_state, crtc_state 133 drivers/gpu/drm/tiny/ili9341.c mipi_dbi_enable_flush(dbidev, crtc_state, plane_state); crtc_state 51 drivers/gpu/drm/tiny/mi0283qt.c struct drm_crtc_state *crtc_state, crtc_state 137 drivers/gpu/drm/tiny/mi0283qt.c mipi_dbi_enable_flush(dbidev, crtc_state, plane_state); crtc_state 654 drivers/gpu/drm/tiny/repaper.c struct drm_crtc_state *crtc_state, crtc_state 177 drivers/gpu/drm/tiny/st7586.c struct drm_crtc_state *crtc_state, crtc_state 42 drivers/gpu/drm/tiny/st7735r.c struct drm_crtc_state *crtc_state, crtc_state 107 drivers/gpu/drm/tiny/st7735r.c mipi_dbi_enable_flush(dbidev, crtc_state, plane_state); crtc_state 266 drivers/gpu/drm/vboxvideo/vbox_mode.c struct drm_crtc_state *crtc_state = NULL; crtc_state 269 drivers/gpu/drm/vboxvideo/vbox_mode.c crtc_state = drm_atomic_get_existing_crtc_state( crtc_state 271 drivers/gpu/drm/vboxvideo/vbox_mode.c if (WARN_ON(!crtc_state)) crtc_state 275 drivers/gpu/drm/vboxvideo/vbox_mode.c return drm_atomic_helper_check_plane_state(new_state, crtc_state, crtc_state 335 drivers/gpu/drm/vboxvideo/vbox_mode.c struct drm_crtc_state *crtc_state = NULL; crtc_state 341 drivers/gpu/drm/vboxvideo/vbox_mode.c crtc_state = drm_atomic_get_existing_crtc_state( crtc_state 343 drivers/gpu/drm/vboxvideo/vbox_mode.c if (WARN_ON(!crtc_state)) crtc_state 347 drivers/gpu/drm/vboxvideo/vbox_mode.c ret = drm_atomic_helper_check_plane_state(new_state, crtc_state, crtc_state 63 drivers/gpu/drm/vc4/vc4_crtc.c to_vc4_crtc_state(struct drm_crtc_state *crtc_state) crtc_state 65 drivers/gpu/drm/vc4/vc4_crtc.c return (struct vc4_crtc_state *)crtc_state; crtc_state 265 drivers/gpu/drm/vc4/vc4_plane.c struct drm_crtc_state *crtc_state; crtc_state 267 drivers/gpu/drm/vc4/vc4_plane.c crtc_state = drm_atomic_get_new_crtc_state(pstate->state, crtc_state 270 drivers/gpu/drm/vc4/vc4_plane.c vc4_crtc_get_margins(crtc_state, &left, &right, &top, &bottom); crtc_state 274 drivers/gpu/drm/vc4/vc4_plane.c if (left + right >= crtc_state->mode.hdisplay || crtc_state 275 drivers/gpu/drm/vc4/vc4_plane.c top + bottom >= crtc_state->mode.vdisplay) crtc_state 278 drivers/gpu/drm/vc4/vc4_plane.c adjhdisplay = crtc_state->mode.hdisplay - (left + right); crtc_state 281 drivers/gpu/drm/vc4/vc4_plane.c crtc_state->mode.hdisplay); crtc_state 283 drivers/gpu/drm/vc4/vc4_plane.c if (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - left) crtc_state 284 drivers/gpu/drm/vc4/vc4_plane.c vc4_pstate->crtc_x = crtc_state->mode.hdisplay - left; crtc_state 286 drivers/gpu/drm/vc4/vc4_plane.c adjvdisplay = crtc_state->mode.vdisplay - (top + bottom); crtc_state 289 drivers/gpu/drm/vc4/vc4_plane.c crtc_state->mode.vdisplay); crtc_state 291 drivers/gpu/drm/vc4/vc4_plane.c if (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - top) crtc_state 292 drivers/gpu/drm/vc4/vc4_plane.c vc4_pstate->crtc_y = crtc_state->mode.vdisplay - top; crtc_state 296 drivers/gpu/drm/vc4/vc4_plane.c crtc_state->mode.hdisplay); crtc_state 299 drivers/gpu/drm/vc4/vc4_plane.c crtc_state->mode.vdisplay); crtc_state 314 drivers/gpu/drm/vc4/vc4_plane.c struct drm_crtc_state *crtc_state; crtc_state 319 drivers/gpu/drm/vc4/vc4_plane.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc_state 321 drivers/gpu/drm/vc4/vc4_plane.c if (!crtc_state) { crtc_state 326 drivers/gpu/drm/vc4/vc4_plane.c ret = drm_atomic_helper_check_plane_state(state, crtc_state, 1, crtc_state 493 drivers/gpu/drm/vc4/vc4_plane.c struct drm_crtc_state *crtc_state; crtc_state 497 drivers/gpu/drm/vc4/vc4_plane.c crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc_state 499 drivers/gpu/drm/vc4/vc4_plane.c vrefresh = drm_mode_vrefresh(&crtc_state->adjusted_mode); crtc_state 229 drivers/gpu/drm/vc4/vc4_txp.c struct drm_crtc_state *crtc_state; crtc_state 237 drivers/gpu/drm/vc4/vc4_txp.c crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); crtc_state 240 drivers/gpu/drm/vc4/vc4_txp.c if (fb->width != crtc_state->mode.hdisplay || crtc_state 241 drivers/gpu/drm/vc4/vc4_txp.c fb->height != crtc_state->mode.vdisplay) { crtc_state 259 drivers/gpu/drm/vc4/vc4_txp.c vc4_crtc_txp_armed(crtc_state); crtc_state 481 drivers/gpu/drm/vc4/vc4_vec.c struct drm_crtc_state *crtc_state, crtc_state 491 drivers/gpu/drm/vc4/vc4_vec.c struct drm_crtc_state *crtc_state, crtc_state 499 drivers/gpu/drm/vc4/vc4_vec.c !drm_mode_equal(vec_mode->mode, &crtc_state->adjusted_mode)) crtc_state 153 drivers/gpu/drm/vkms/vkms_composer.c struct vkms_crtc_state *crtc_state = container_of(work, crtc_state 156 drivers/gpu/drm/vkms/vkms_composer.c struct drm_crtc *crtc = crtc_state->base.crtc; crtc_state 165 drivers/gpu/drm/vkms/vkms_composer.c frame_start = crtc_state->frame_start; crtc_state 166 drivers/gpu/drm/vkms/vkms_composer.c frame_end = crtc_state->frame_end; crtc_state 167 drivers/gpu/drm/vkms/vkms_composer.c crc_pending = crtc_state->crc_pending; crtc_state 168 drivers/gpu/drm/vkms/vkms_composer.c crtc_state->frame_start = 0; crtc_state 169 drivers/gpu/drm/vkms/vkms_composer.c crtc_state->frame_end = 0; crtc_state 170 drivers/gpu/drm/vkms/vkms_composer.c crtc_state->crc_pending = false; crtc_state 180 drivers/gpu/drm/vkms/vkms_composer.c if (crtc_state->num_active_planes >= 1) crtc_state 181 drivers/gpu/drm/vkms/vkms_composer.c primary_composer = crtc_state->active_planes[0]->composer; crtc_state 183 drivers/gpu/drm/vkms/vkms_composer.c if (crtc_state->num_active_planes == 2) crtc_state 184 drivers/gpu/drm/vkms/vkms_composer.c cursor_composer = crtc_state->active_planes[1]->composer; crtc_state 116 drivers/gpu/drm/vkms/vkms_plane.c struct drm_crtc_state *crtc_state; crtc_state 123 drivers/gpu/drm/vkms/vkms_plane.c crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); crtc_state 124 drivers/gpu/drm/vkms/vkms_plane.c if (IS_ERR(crtc_state)) crtc_state 125 drivers/gpu/drm/vkms/vkms_plane.c return PTR_ERR(crtc_state); crtc_state 130 drivers/gpu/drm/vkms/vkms_plane.c ret = drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 446 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_crtc_state *crtc_state = NULL; crtc_state 451 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); crtc_state 453 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = drm_atomic_helper_check_plane_state(state, crtc_state, crtc_state 486 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_crtc_state *crtc_state = NULL; crtc_state 491 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c crtc_state = drm_atomic_get_new_crtc_state(new_state->state, crtc_state 494 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = drm_atomic_helper_check_plane_state(new_state, crtc_state, crtc_state 1527 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_crtc_state *crtc_state; crtc_state 1529 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c crtc_state = drm_atomic_get_new_crtc_state(state, crtc); crtc_state 1530 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (crtc_state) { crtc_state 1538 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c crtc_state = crtc->state; crtc_state 1541 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c return crtc_state; crtc_state 1560 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_crtc_state *crtc_state; crtc_state 1569 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c crtc_state = vmw_crtc_state_and_lock(state, crtc); crtc_state 1570 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (IS_ERR(crtc_state)) crtc_state 1571 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c return PTR_ERR(crtc_state); crtc_state 1573 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (!crtc_state || !crtc_state->enable) crtc_state 1617 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_crtc_state *crtc_state; crtc_state 1621 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c crtc_state = vmw_crtc_state_and_lock(state, crtc); crtc_state 1622 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (IS_ERR(crtc_state)) { crtc_state 1623 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = PTR_ERR(crtc_state); crtc_state 1627 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (!crtc_state) crtc_state 1630 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (crtc_state->enable) { crtc_state 1633 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c rects[i].x2 = du->gui_x + crtc_state->mode.hdisplay; crtc_state 1634 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c rects[i].y2 = du->gui_y + crtc_state->mode.vdisplay; crtc_state 1700 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct drm_crtc_state *crtc_state; crtc_state 1714 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c for_each_new_crtc_in_state(state, crtc, crtc_state, i) { crtc_state 1715 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (drm_atomic_crtc_needs_modeset(crtc_state)) crtc_state 112 drivers/gpu/drm/xen/xen_drm_front_kms.c struct drm_crtc_state *crtc_state, crtc_state 53 drivers/gpu/drm/zte/zx_plane.c struct drm_crtc_state *crtc_state; crtc_state 60 drivers/gpu/drm/zte/zx_plane.c crtc_state = drm_atomic_get_existing_crtc_state(plane_state->state, crtc_state 62 drivers/gpu/drm/zte/zx_plane.c if (WARN_ON(!crtc_state)) crtc_state 66 drivers/gpu/drm/zte/zx_plane.c if (!crtc_state->enable) crtc_state 73 drivers/gpu/drm/zte/zx_plane.c return drm_atomic_helper_check_plane_state(plane_state, crtc_state, crtc_state 282 drivers/gpu/drm/zte/zx_plane.c struct drm_crtc_state *crtc_state; crtc_state 287 drivers/gpu/drm/zte/zx_plane.c crtc_state = drm_atomic_get_existing_crtc_state(plane_state->state, crtc_state 289 drivers/gpu/drm/zte/zx_plane.c if (WARN_ON(!crtc_state)) crtc_state 293 drivers/gpu/drm/zte/zx_plane.c if (!crtc_state->enable) crtc_state 300 drivers/gpu/drm/zte/zx_plane.c return drm_atomic_helper_check_plane_state(plane_state, crtc_state, crtc_state 44 include/drm/drm_atomic_helper.h const struct drm_crtc_state *crtc_state, crtc_state 176 include/drm/drm_atomic_helper.h #define drm_atomic_crtc_state_for_each_plane(plane, crtc_state) \ crtc_state 177 include/drm/drm_atomic_helper.h drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask) crtc_state 194 include/drm/drm_atomic_helper.h #define drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) \ crtc_state 195 include/drm/drm_atomic_helper.h drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask) \ crtc_state 197 include/drm/drm_atomic_helper.h __drm_atomic_get_current_plane_state((crtc_state)->state, \ crtc_state 147 include/drm/drm_mipi_dbi.h struct drm_crtc_state *crtc_state, crtc_state 645 include/drm/drm_modeset_helper_vtables.h struct drm_crtc_state *crtc_state, crtc_state 816 include/drm/drm_modeset_helper_vtables.h struct drm_crtc_state *crtc_state, crtc_state 63 include/drm/drm_simple_kms_helper.h struct drm_crtc_state *crtc_state, crtc_state 93 include/drm/drm_simple_kms_helper.h struct drm_crtc_state *crtc_state);