cpt_write_csr64 40 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), cpt_write_csr64 56 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), cpt_write_csr64 73 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), cpt_write_csr64 87 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), cpt_write_csr64 95 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull); cpt_write_csr64 101 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull); cpt_write_csr64 107 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull); cpt_write_csr64 120 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull); cpt_write_csr64 153 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, cpt_write_csr64 348 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_RESET(0), 1); cpt_write_csr64 387 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 0); cpt_write_csr64 402 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), 0); cpt_write_csr64 425 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, cpt_write_csr64 12 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1), cpt_write_csr64 14 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0), mbx->msg); cpt_write_csr64 31 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0), (1 << vf)); cpt_write_csr64 44 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u); cpt_write_csr64 56 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u); cpt_write_csr64 79 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q), pf_qx_ctl.u); cpt_write_csr64 371 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0), vqx_ctl.u); cpt_write_csr64 381 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DOORBELL(0, 0), cpt_write_csr64 391 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0), vqx_inprg.u); cpt_write_csr64 401 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0), cpt_write_csr64 412 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_WAIT(0, 0), cpt_write_csr64 424 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0), cpt_write_csr64 436 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0), cpt_write_csr64 448 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_ENA_W1S(0, 0), cpt_write_csr64 460 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), cpt_write_csr64 472 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), cpt_write_csr64 484 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, cpt_write_csr64 496 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), cpt_write_csr64 508 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0), cpt_write_csr64 584 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_DONE_ACK(0, 0), cpt_write_csr64 638 drivers/crypto/cavium/cpt/cptvf_main.c cpt_write_csr64(cptvf->reg_base, CPTX_VQX_SADDR(0, 0), vqx_saddr.u); cpt_write_csr64 11 drivers/crypto/cavium/cpt/cptvf_mbox.c cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0), cpt_write_csr64 13 drivers/crypto/cavium/cpt/cptvf_mbox.c cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1),