cpt_read_csr64 39 drivers/crypto/cavium/cpt/cptpf_main.c grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); cpt_read_csr64 43 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); cpt_read_csr64 46 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, cpt_read_csr64 55 drivers/crypto/cavium/cpt/cptpf_main.c pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); cpt_read_csr64 72 drivers/crypto/cavium/cpt/cptpf_main.c pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); cpt_read_csr64 86 drivers/crypto/cavium/cpt/cptpf_main.c pf_gx_en = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); cpt_read_csr64 355 drivers/crypto/cavium/cpt/cptpf_main.c pf_cnsts.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_CONSTANTS(0)); cpt_read_csr64 364 drivers/crypto/cavium/cpt/cptpf_main.c bist_sts.u = cpt_read_csr64(cpt->reg_base, cpt_read_csr64 374 drivers/crypto/cavium/cpt/cptpf_main.c bist_sts.u = cpt_read_csr64(cpt->reg_base, cpt_read_csr64 391 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); cpt_read_csr64 394 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, cpt_read_csr64 41 drivers/crypto/cavium/cpt/cptpf_mbox.c pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); cpt_read_csr64 54 drivers/crypto/cavium/cpt/cptpf_mbox.c pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); cpt_read_csr64 77 drivers/crypto/cavium/cpt/cptpf_mbox.c pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q)); cpt_read_csr64 96 drivers/crypto/cavium/cpt/cptpf_mbox.c mbx.msg = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0)); cpt_read_csr64 97 drivers/crypto/cavium/cpt/cptpf_mbox.c mbx.data = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1)); cpt_read_csr64 151 drivers/crypto/cavium/cpt/cptpf_mbox.c intr = cpt_read_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0)); cpt_read_csr64 369 drivers/crypto/cavium/cpt/cptvf_main.c vqx_ctl.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0)); cpt_read_csr64 378 drivers/crypto/cavium/cpt/cptvf_main.c vqx_dbell.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 389 drivers/crypto/cavium/cpt/cptvf_main.c vqx_inprg.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0)); cpt_read_csr64 398 drivers/crypto/cavium/cpt/cptvf_main.c vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 409 drivers/crypto/cavium/cpt/cptvf_main.c vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 420 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 432 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 444 drivers/crypto/cavium/cpt/cptvf_main.c vqx_done_ena.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 456 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 468 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 480 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 492 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 504 drivers/crypto/cavium/cpt/cptvf_main.c vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 514 drivers/crypto/cavium/cpt/cptvf_main.c return cpt_read_csr64(cptvf->reg_base, CPTX_VQX_MISC_INT(0, 0)); cpt_read_csr64 572 drivers/crypto/cavium/cpt/cptvf_main.c vqx_done.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_DONE(0, 0)); cpt_read_csr64 581 drivers/crypto/cavium/cpt/cptvf_main.c vqx_dack_cnt.u = cpt_read_csr64(cptvf->reg_base, cpt_read_csr64 26 drivers/crypto/cavium/cpt/cptvf_mbox.c mbx.msg = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0)); cpt_read_csr64 27 drivers/crypto/cavium/cpt/cptvf_mbox.c mbx.data = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1));