compressor 978 drivers/block/zram/zram_drv.c sz = zcomp_available_show(zram->compressor, buf); compressor 988 drivers/block/zram/zram_drv.c char compressor[ARRAY_SIZE(zram->compressor)]; compressor 991 drivers/block/zram/zram_drv.c strlcpy(compressor, buf, sizeof(compressor)); compressor 993 drivers/block/zram/zram_drv.c sz = strlen(compressor); compressor 994 drivers/block/zram/zram_drv.c if (sz > 0 && compressor[sz - 1] == '\n') compressor 995 drivers/block/zram/zram_drv.c compressor[sz - 1] = 0x00; compressor 997 drivers/block/zram/zram_drv.c if (!zcomp_available_algorithm(compressor)) compressor 1007 drivers/block/zram/zram_drv.c strcpy(zram->compressor, compressor); compressor 1730 drivers/block/zram/zram_drv.c comp = zcomp_create(zram->compressor); compressor 1733 drivers/block/zram/zram_drv.c zram->compressor); compressor 1955 drivers/block/zram/zram_drv.c strlcpy(zram->compressor, default_compressor, sizeof(zram->compressor)); compressor 110 drivers/block/zram/zram_drv.h char compressor[CRYPTO_MAX_ALG_NAME]; compressor 477 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct dm_comressor_info *compressor = &adev->dm.compressor; compressor 488 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (compressor->bo_ptr) compressor 499 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, compressor 500 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &compressor->gpu_addr, &compressor->cpu_addr); compressor 505 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; compressor 231 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h struct dm_comressor_info compressor; compressor 504 drivers/gpu/drm/amd/display/dc/dc.h struct compressor *fbc_compressor; compressor 73 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c static void reset_lb_on_vblank(struct compressor *compressor, uint32_t crtc_inst) compressor 79 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); compressor 83 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c status_pos = dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_POSITION)); compressor 87 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c if (status_pos != dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_POSITION))) { compressor 89 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c value = dm_read_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL)); compressor 92 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL), value); compressor 94 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c frame_count = dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_FRAME_COUNT)); compressor 98 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c if (frame_count != dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_FRAME_COUNT))) compressor 106 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c value = dm_read_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL)); compressor 109 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL), value); compressor 142 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c void dce110_compressor_power_up_fbc(struct compressor *compressor) compressor 148 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 152 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c if (compressor->options.bits.CLK_GATING_DISABLED == 1) { compressor 160 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 163 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 167 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 170 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 172 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 178 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 179 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1; compressor 182 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); compressor 185 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); compressor 189 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c struct compressor *compressor, compressor 192 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); compressor 194 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c if (compressor->options.bits.FBC_SUPPORT && compressor 195 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c (!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL))) { compressor 201 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 208 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 211 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->is_enabled = true; compressor 215 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->attached_inst = params->inst + CONTROLLER_ID_D0; compressor 219 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 222 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c misc_value = dm_read_reg(compressor->ctx, mmFBC_MISC); compressor 231 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, mmFBC_MISC, misc_value); compressor 235 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 241 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c void dce110_compressor_disable_fbc(struct compressor *compressor) compressor 243 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); compressor 246 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c if (compressor->options.bits.FBC_SUPPORT) { compressor 247 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c if (dce110_compressor_is_fbc_enabled_in_hw(compressor, &crtc_inst)) { compressor 250 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); compressor 252 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); compressor 255 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->attached_inst = 0; compressor 256 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->is_enabled = false; compressor 263 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c reset_lb_on_vblank(compressor, compressor 269 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c struct compressor *compressor, compressor 275 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c value = dm_read_reg(compressor->ctx, mmFBC_STATUS); compressor 278 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c *inst = compressor->attached_inst; compressor 282 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c value = dm_read_reg(compressor->ctx, mmFBC_MISC); compressor 284 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c value = dm_read_reg(compressor->ctx, mmFBC_CNTL); compressor 289 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->attached_inst; compressor 298 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c struct compressor *compressor, compressor 301 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); compressor 305 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->compr_surface_address.addr.low_part; compressor 311 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->ctx, compressor 314 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, compressor 318 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, compressor 320 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->compr_surface_address.addr.high_part); compressor 321 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, compressor 327 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1) compressor 334 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0); compressor 342 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value); compressor 347 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c struct compressor *compressor, compressor 354 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c uint32_t value = dm_read_reg(compressor->ctx, addr); compressor 361 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 388 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 394 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 397 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c struct compressor *dce110_compressor_create(struct dc_context *ctx) compressor 409 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c void dce110_compressor_destroy(struct compressor **compressor) compressor 411 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c kfree(TO_DCE110_COMPRESSOR(*compressor)); compressor 412 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c *compressor = NULL; compressor 493 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c void dce110_compressor_construct(struct dce110_compressor *compressor, compressor 497 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.options.raw = 0; compressor 498 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.options.bits.FBC_SUPPORT = true; compressor 501 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.lpt_channels_num = 1; compressor 502 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.options.bits.DUMMY_BACKEND = false; compressor 510 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.options.bits.CLK_GATING_DISABLED = false; compressor 512 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.ctx = ctx; compressor 513 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.embedded_panel_h_size = 0; compressor 514 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.embedded_panel_v_size = 0; compressor 515 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.memory_bus_width = ctx->asic_id.vram_width; compressor 516 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.allocated_size = 0; compressor 517 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.preferred_requested_size = 0; compressor 518 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; compressor 519 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.banks_num = 0; compressor 520 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.raw_size = 0; compressor 521 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.channel_interleave_size = 0; compressor 522 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.dram_channels_num = 0; compressor 523 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.lpt_channels_num = 0; compressor 524 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.attached_inst = CONTROLLER_ID_UNDEFINED; compressor 525 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.is_enabled = false; compressor 526 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.funcs = &dce110_compressor_funcs; compressor 30 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h #define TO_DCE110_COMPRESSOR(compressor)\ compressor 31 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h container_of(compressor, struct dce110_compressor, base) compressor 39 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h struct compressor base; compressor 43 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h struct compressor *dce110_compressor_create(struct dc_context *ctx); compressor 48 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h void dce110_compressor_destroy(struct compressor **cp); compressor 51 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h void dce110_compressor_power_up_fbc(struct compressor *cp); compressor 53 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h void dce110_compressor_enable_fbc(struct compressor *cp, compressor 56 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h void dce110_compressor_disable_fbc(struct compressor *cp); compressor 58 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h void dce110_compressor_set_fbc_invalidation_triggers(struct compressor *cp, compressor 62 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h struct compressor *cp, compressor 65 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h bool dce110_compressor_is_fbc_enabled_in_hw(struct compressor *cp, compressor 69 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h void dce110_compressor_enable_lpt(struct compressor *cp); compressor 71 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h void dce110_compressor_disable_lpt(struct compressor *cp); compressor 73 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h void dce110_compressor_program_lpt_control(struct compressor *cp, compressor 76 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *cp); compressor 1863 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct compressor *compr = dc->fbc_compressor; compressor 319 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c void dce112_compressor_power_up_fbc(struct compressor *compressor) compressor 325 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 329 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (compressor->options.bits.CLK_GATING_DISABLED == 1) { compressor 337 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 340 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 344 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 347 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 349 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 355 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 356 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1; compressor 359 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); compressor 362 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); compressor 366 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct compressor *compressor, compressor 370 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); compressor 372 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (compressor->options.bits.FBC_SUPPORT && compressor 373 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c (compressor->options.bits.DUMMY_BACKEND == 0) && compressor 374 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c (!dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) && compressor 386 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) && compressor 390 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dce112_compressor_enable_lpt(compressor); compressor 394 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 400 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 403 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->is_enabled = true; compressor 404 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->attached_inst = params->inst; compressor 409 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 411 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 417 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c void dce112_compressor_disable_fbc(struct compressor *compressor) compressor 419 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); compressor 421 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (compressor->options.bits.FBC_SUPPORT && compressor 422 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) { compressor 425 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); compressor 427 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); compressor 430 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->attached_inst = 0; compressor 431 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->is_enabled = false; compressor 435 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (compressor->options.bits.LPT_SUPPORT) compressor 436 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dce112_compressor_disable_lpt(compressor); compressor 443 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct compressor *compressor, compressor 449 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, mmFBC_STATUS); compressor 452 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c *inst = compressor->attached_inst; compressor 456 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, mmFBC_MISC); compressor 458 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, mmFBC_CNTL); compressor 463 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->attached_inst; compressor 470 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *compressor) compressor 473 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value = dm_read_reg(compressor->ctx, compressor 483 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct compressor *compressor, compressor 486 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); compressor 490 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->compr_surface_address.addr.low_part; compressor 494 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->ctx, compressor 497 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, compressor 500 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (compressor->options.bits.LPT_SUPPORT) { compressor 512 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, compressor 514 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->compr_surface_address.addr.high_part); compressor 515 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, compressor 523 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1) compressor 531 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0); compressor 539 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value); compressor 543 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c void dce112_compressor_disable_lpt(struct compressor *compressor) compressor 545 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); compressor 554 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->ctx, compressor 562 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->ctx, compressor 568 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 574 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 578 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 584 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 588 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 594 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value); compressor 597 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c void dce112_compressor_enable_lpt(struct compressor *compressor) compressor 599 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); compressor 606 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, compressor 613 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, compressor 618 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 624 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 630 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value_control = dm_read_reg(compressor->ctx, addr); compressor 636 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 643 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 647 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 653 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 657 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct compressor *compressor, compressor 660 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor); compressor 667 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (!compressor->options.bits.LPT_SUPPORT) compressor 670 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c lpt_control = dm_read_reg(compressor->ctx, compressor 678 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c switch (compressor->lpt_channels_num) { compressor 725 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, compressor 734 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct compressor *compressor, compressor 741 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c uint32_t value = dm_read_reg(compressor->ctx, addr); compressor 748 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 775 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(compressor->ctx, addr); compressor 787 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c dm_write_reg(compressor->ctx, addr, value); compressor 790 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c void dce112_compressor_construct(struct dce112_compressor *compressor, compressor 796 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.raw = 0; compressor 797 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.bits.FBC_SUPPORT = true; compressor 798 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.bits.LPT_SUPPORT = true; compressor 800 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.lpt_channels_num = 1; compressor 801 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.bits.DUMMY_BACKEND = false; compressor 805 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (compressor->base.memory_bus_width == 64) compressor 806 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.bits.LPT_SUPPORT = false; compressor 808 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.bits.CLK_GATING_DISABLED = false; compressor 810 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.ctx = ctx; compressor 811 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.embedded_panel_h_size = 0; compressor 812 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.embedded_panel_v_size = 0; compressor 813 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.memory_bus_width = ctx->asic_id.vram_width; compressor 814 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.allocated_size = 0; compressor 815 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.preferred_requested_size = 0; compressor 816 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; compressor 817 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.banks_num = 0; compressor 818 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.raw_size = 0; compressor 819 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.channel_interleave_size = 0; compressor 820 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.dram_channels_num = 0; compressor 821 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.lpt_channels_num = 0; compressor 822 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.attached_inst = 0; compressor 823 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.is_enabled = false; compressor 827 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.embedded_panel_h_size = compressor 829 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.embedded_panel_v_size = compressor 834 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c struct compressor *dce112_compressor_create(struct dc_context *ctx) compressor 846 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c void dce112_compressor_destroy(struct compressor **compressor) compressor 848 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c kfree(TO_DCE112_COMPRESSOR(*compressor)); compressor 849 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c *compressor = NULL; compressor 30 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h #define TO_DCE112_COMPRESSOR(compressor)\ compressor 31 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h container_of(compressor, struct dce112_compressor, base) compressor 39 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h struct compressor base; compressor 43 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h struct compressor *dce112_compressor_create(struct dc_context *ctx); compressor 48 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h void dce112_compressor_destroy(struct compressor **cp); compressor 51 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h void dce112_compressor_power_up_fbc(struct compressor *cp); compressor 53 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h void dce112_compressor_enable_fbc(struct compressor *cp, uint32_t paths_num, compressor 56 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h void dce112_compressor_disable_fbc(struct compressor *cp); compressor 58 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h void dce112_compressor_set_fbc_invalidation_triggers(struct compressor *cp, compressor 62 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h struct compressor *cp, compressor 65 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h bool dce112_compressor_is_fbc_enabled_in_hw(struct compressor *cp, compressor 69 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h void dce112_compressor_enable_lpt(struct compressor *cp); compressor 71 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h void dce112_compressor_disable_lpt(struct compressor *cp); compressor 73 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h void dce112_compressor_program_lpt_control(struct compressor *cp, compressor 76 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *cp); compressor 62 drivers/gpu/drm/amd/display/dc/inc/compressor.h struct compressor; compressor 66 drivers/gpu/drm/amd/display/dc/inc/compressor.h void (*power_up_fbc)(struct compressor *cp); compressor 67 drivers/gpu/drm/amd/display/dc/inc/compressor.h void (*enable_fbc)(struct compressor *cp, compressor 69 drivers/gpu/drm/amd/display/dc/inc/compressor.h void (*disable_fbc)(struct compressor *cp); compressor 70 drivers/gpu/drm/amd/display/dc/inc/compressor.h void (*set_fbc_invalidation_triggers)(struct compressor *cp, compressor 73 drivers/gpu/drm/amd/display/dc/inc/compressor.h struct compressor *cp, compressor 75 drivers/gpu/drm/amd/display/dc/inc/compressor.h bool (*is_fbc_enabled_in_hw)(struct compressor *cp, compressor 192 drivers/net/ppp/bsd_comp.c extern int ppp_register_compressor (struct compressor *cp); compressor 193 drivers/net/ppp/bsd_comp.c extern void ppp_unregister_compressor (struct compressor *cp); compressor 1132 drivers/net/ppp/bsd_comp.c static struct compressor ppp_bsd_compress = { compressor 566 drivers/net/ppp/ppp_deflate.c extern int ppp_register_compressor (struct compressor *cp); compressor 567 drivers/net/ppp/ppp_deflate.c extern void ppp_unregister_compressor (struct compressor *cp); compressor 572 drivers/net/ppp/ppp_deflate.c static struct compressor ppp_deflate = { compressor 590 drivers/net/ppp/ppp_deflate.c static struct compressor ppp_deflate_draft = { compressor 129 drivers/net/ppp/ppp_generic.c struct compressor *xcomp; /* transmit packet compressor 8c */ compressor 131 drivers/net/ppp/ppp_generic.c struct compressor *rcomp; /* receive decompressor 94 */ compressor 276 drivers/net/ppp/ppp_generic.c static struct compressor *find_compressor(int type); compressor 2740 drivers/net/ppp/ppp_generic.c struct compressor *cp, *ocomp; compressor 2898 drivers/net/ppp/ppp_generic.c struct compressor *xcomp, *rcomp; compressor 2928 drivers/net/ppp/ppp_generic.c struct compressor *comp; compressor 2945 drivers/net/ppp/ppp_generic.c ppp_register_compressor(struct compressor *cp) compressor 2967 drivers/net/ppp/ppp_generic.c ppp_unregister_compressor(struct compressor *cp) compressor 2981 drivers/net/ppp/ppp_generic.c static struct compressor * compressor 2985 drivers/net/ppp/ppp_generic.c struct compressor *cp = NULL; compressor 633 drivers/net/ppp/ppp_mppe.c static struct compressor ppp_mppe = { compressor 101 include/linux/ppp-comp.h extern int ppp_register_compressor(struct compressor *); compressor 102 include/linux/ppp-comp.h extern void ppp_unregister_compressor(struct compressor *); compressor 94 mm/zswap.c module_param_cb(compressor, &zswap_compressor_param_ops, compressor 484 mm/zswap.c static struct zswap_pool *zswap_pool_find_get(char *type, char *compressor) compressor 491 mm/zswap.c if (strcmp(pool->tfm_name, compressor)) compressor 504 mm/zswap.c static struct zswap_pool *zswap_pool_create(char *type, char *compressor) compressor 518 mm/zswap.c if (!strcmp(compressor, ZSWAP_PARAM_UNSET)) compressor 536 mm/zswap.c strlcpy(pool->tfm_name, compressor, sizeof(pool->tfm_name)); compressor 667 mm/zswap.c char *type, char *compressor) compressor 694 mm/zswap.c } else if (!compressor) { compressor 699 mm/zswap.c compressor = s; compressor 707 mm/zswap.c pool = zswap_pool_find_get(type, compressor); compressor 717 mm/zswap.c pool = zswap_pool_create(type, compressor);