cmd_val 847 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t cmd_val:1; cmd_val 865 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t cmd_val:1; cmd_val 1019 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t cmd_val:1; cmd_val 1065 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t cmd_val:1; cmd_val 378 drivers/gpu/drm/i915/gvt/cmd_parser.c FIELD_GET(GENMASK(end, start), cmd_val(s, dword)) cmd_val 727 drivers/gpu/drm/i915/gvt/cmd_parser.c s->ip_va, cmd_val(s, 0), cmd_val(s, 1), cmd_val 728 drivers/gpu/drm/i915/gvt/cmd_parser.c cmd_val(s, 2), cmd_val(s, 3)); cmd_val 730 drivers/gpu/drm/i915/gvt/cmd_parser.c print_opcode(cmd_val(s, 0), s->ring_id); cmd_val 737 drivers/gpu/drm/i915/gvt/cmd_parser.c gvt_dbg_cmd("%08x ", cmd_val(s, i)); cmd_val 808 drivers/gpu/drm/i915/gvt/cmd_parser.c return get_cmd_length(s->info, cmd_val(s, 0)); cmd_val 844 drivers/gpu/drm/i915/gvt/cmd_parser.c data = cmd_val(s, index + 1); cmd_val 875 drivers/gpu/drm/i915/gvt/cmd_parser.c vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1); cmd_val 934 drivers/gpu/drm/i915/gvt/cmd_parser.c u32 data = cmd_val(s, index + 1); cmd_val 950 drivers/gpu/drm/i915/gvt/cmd_parser.c (cmd_val(s, i) & GENMASK(22, 2)) cmd_val 953 drivers/gpu/drm/i915/gvt/cmd_parser.c (cmd_val(s, i) & GENMASK(22, 18)) cmd_val 956 drivers/gpu/drm/i915/gvt/cmd_parser.c (cmd_val(s, i) & GENMASK(31, 2)) cmd_val 959 drivers/gpu/drm/i915/gvt/cmd_parser.c (cmd_val(s, i) & GENMASK(15, 0)) cmd_val 1037 drivers/gpu/drm/i915/gvt/cmd_parser.c if (cmd_val(s, 0) & (1 << 22)) { cmd_val 1061 drivers/gpu/drm/i915/gvt/cmd_parser.c if (cmd_val(s, 0) & (1 << 22)) { cmd_val 1117 drivers/gpu/drm/i915/gvt/cmd_parser.c post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14; cmd_val 1120 drivers/gpu/drm/i915/gvt/cmd_parser.c if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE) cmd_val 1130 drivers/gpu/drm/i915/gvt/cmd_parser.c if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) { cmd_val 1131 drivers/gpu/drm/i915/gvt/cmd_parser.c gma = cmd_val(s, 2) & GENMASK(31, 3); cmd_val 1135 drivers/gpu/drm/i915/gvt/cmd_parser.c if (cmd_val(s, 1) & (1 << 21)) cmd_val 1145 drivers/gpu/drm/i915/gvt/cmd_parser.c val = cmd_val(s, 1) & (~(1 << 21)); cmd_val 1155 drivers/gpu/drm/i915/gvt/cmd_parser.c if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY) cmd_val 1226 drivers/gpu/drm/i915/gvt/cmd_parser.c dword0 = cmd_val(s, 0); cmd_val 1227 drivers/gpu/drm/i915/gvt/cmd_parser.c dword1 = cmd_val(s, 1); cmd_val 1228 drivers/gpu/drm/i915/gvt/cmd_parser.c dword2 = cmd_val(s, 2); cmd_val 1262 drivers/gpu/drm/i915/gvt/cmd_parser.c u32 dword0 = cmd_val(s, 0); cmd_val 1263 drivers/gpu/drm/i915/gvt/cmd_parser.c u32 dword1 = cmd_val(s, 1); cmd_val 1264 drivers/gpu/drm/i915/gvt/cmd_parser.c u32 dword2 = cmd_val(s, 2); cmd_val 1454 drivers/gpu/drm/i915/gvt/cmd_parser.c u32 cmd = cmd_val(s, 0); cmd_val 1475 drivers/gpu/drm/i915/gvt/cmd_parser.c gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK; cmd_val 1479 drivers/gpu/drm/i915/gvt/cmd_parser.c gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK; cmd_val 1518 drivers/gpu/drm/i915/gvt/cmd_parser.c pr_err("\n%08x ", cmd_val(s, i)); cmd_val 1520 drivers/gpu/drm/i915/gvt/cmd_parser.c pr_err("%08x ", cmd_val(s, i)); cmd_val 1535 drivers/gpu/drm/i915/gvt/cmd_parser.c int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0; cmd_val 1541 drivers/gpu/drm/i915/gvt/cmd_parser.c if (!(cmd_val(s, 0) & (1 << 22))) cmd_val 1552 drivers/gpu/drm/i915/gvt/cmd_parser.c gma = cmd_val(s, 2) & GENMASK(31, 2); cmd_val 1555 drivers/gpu/drm/i915/gvt/cmd_parser.c gma_low = cmd_val(s, 1) & GENMASK(31, 2); cmd_val 1556 drivers/gpu/drm/i915/gvt/cmd_parser.c gma_high = cmd_val(s, 2) & GENMASK(15, 0); cmd_val 1558 drivers/gpu/drm/i915/gvt/cmd_parser.c core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0; cmd_val 1591 drivers/gpu/drm/i915/gvt/cmd_parser.c int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) * cmd_val 1597 drivers/gpu/drm/i915/gvt/cmd_parser.c if (!(cmd_val(s, 0) & (1 << 22))) cmd_val 1601 drivers/gpu/drm/i915/gvt/cmd_parser.c if (cmd_val(s, 0) & BIT(18)) cmd_val 1608 drivers/gpu/drm/i915/gvt/cmd_parser.c gma = cmd_val(s, 1) & GENMASK(31, 2); cmd_val 1610 drivers/gpu/drm/i915/gvt/cmd_parser.c gma_high = cmd_val(s, 2) & GENMASK(15, 0); cmd_val 1657 drivers/gpu/drm/i915/gvt/cmd_parser.c if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) { cmd_val 1658 drivers/gpu/drm/i915/gvt/cmd_parser.c gma = cmd_val(s, 1) & GENMASK(31, 3); cmd_val 1660 drivers/gpu/drm/i915/gvt/cmd_parser.c gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32; cmd_val 1662 drivers/gpu/drm/i915/gvt/cmd_parser.c if (cmd_val(s, 0) & (1 << 21)) cmd_val 1671 drivers/gpu/drm/i915/gvt/cmd_parser.c val = cmd_val(s, 0) & (~(1 << 21)); cmd_val 1676 drivers/gpu/drm/i915/gvt/cmd_parser.c if ((cmd_val(s, 0) & (1 << 8))) cmd_val 1685 drivers/gpu/drm/i915/gvt/cmd_parser.c (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) { cmd_val 1726 drivers/gpu/drm/i915/gvt/cmd_parser.c if (cmd_val(s, 0) & (1 << 8) && cmd_val 1753 drivers/gpu/drm/i915/gvt/cmd_parser.c cmd = cmd_val(s, 0); cmd_val 1938 drivers/gpu/drm/i915/gvt/cmd_parser.c second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1; cmd_val 2661 drivers/gpu/drm/i915/gvt/cmd_parser.c cmd = cmd_val(s, 0); cmd_val 1554 drivers/hwmon/abituguru.c u8 cmd_val = inb_p(ABIT_UGURU_BASE + ABIT_UGURU_CMD); cmd_val 1557 drivers/hwmon/abituguru.c ((cmd_val == 0x00) || (cmd_val == 0xAC))) cmd_val 1561 drivers/hwmon/abituguru.c "0x%02X\n", (unsigned int)data_val, (unsigned int)cmd_val); cmd_val 1216 drivers/hwmon/abituguru3.c u8 cmd_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_CMD); cmd_val 1218 drivers/hwmon/abituguru3.c ((cmd_val == 0xAC) || (cmd_val == 0x05) || cmd_val 1219 drivers/hwmon/abituguru3.c (cmd_val == 0x55))) cmd_val 1223 drivers/hwmon/abituguru3.c "0x%02X\n", (unsigned int)data_val, (unsigned int)cmd_val); cmd_val 443 drivers/mmc/host/sunxi-mmc.c u32 arg, cmd_val, ri; cmd_val 446 drivers/mmc/host/sunxi-mmc.c cmd_val = SDXC_START | SDXC_RESP_EXPIRE | cmd_val 450 drivers/mmc/host/sunxi-mmc.c cmd_val |= SD_IO_RW_DIRECT; cmd_val 454 drivers/mmc/host/sunxi-mmc.c cmd_val |= MMC_STOP_TRANSMISSION; cmd_val 459 drivers/mmc/host/sunxi-mmc.c mmc_writel(host, REG_CMDR, cmd_val); cmd_val 1007 drivers/mmc/host/sunxi-mmc.c u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); cmd_val 1030 drivers/mmc/host/sunxi-mmc.c cmd_val |= SDXC_SEND_INIT_SEQUENCE; cmd_val 1035 drivers/mmc/host/sunxi-mmc.c cmd_val |= SDXC_RESP_EXPIRE; cmd_val 1037 drivers/mmc/host/sunxi-mmc.c cmd_val |= SDXC_LONG_RESPONSE; cmd_val 1039 drivers/mmc/host/sunxi-mmc.c cmd_val |= SDXC_CHECK_RESPONSE_CRC; cmd_val 1042 drivers/mmc/host/sunxi-mmc.c cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; cmd_val 1046 drivers/mmc/host/sunxi-mmc.c cmd_val |= SDXC_SEND_AUTO_STOP; cmd_val 1052 drivers/mmc/host/sunxi-mmc.c cmd_val |= SDXC_WRITE; cmd_val 1063 drivers/mmc/host/sunxi-mmc.c cmd_val & 0x3f, cmd_val, cmd->arg, imask, cmd_val 1091 drivers/mmc/host/sunxi-mmc.c mmc_writel(host, REG_CMDR, cmd_val);