clkdiv 276 arch/powerpc/include/asm/mpc52xx.h extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv); clkdiv 174 arch/powerpc/platforms/52xx/mpc52xx_common.c int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv) clkdiv 185 arch/powerpc/platforms/52xx/mpc52xx_common.c mclken_div = 0x8000 | (clkdiv & 0x1FF); clkdiv 33 drivers/clk/qcom/clk-spmi-pmic-div.c static inline struct clkdiv *to_clkdiv(struct clk_hw *hw) clkdiv 35 drivers/clk/qcom/clk-spmi-pmic-div.c return container_of(hw, struct clkdiv, hw); clkdiv 51 drivers/clk/qcom/clk-spmi-pmic-div.c static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv) clkdiv 55 drivers/clk/qcom/clk-spmi-pmic-div.c regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); clkdiv 61 drivers/clk/qcom/clk-spmi-pmic-div.c __spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable, clkdiv 65 drivers/clk/qcom/clk-spmi-pmic-div.c unsigned int ns = clkdiv->cxo_period_ns; clkdiv 68 drivers/clk/qcom/clk-spmi-pmic-div.c ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL, clkdiv 81 drivers/clk/qcom/clk-spmi-pmic-div.c static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable) clkdiv 85 drivers/clk/qcom/clk-spmi-pmic-div.c regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); clkdiv 88 drivers/clk/qcom/clk-spmi-pmic-div.c return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor); clkdiv 93 drivers/clk/qcom/clk-spmi-pmic-div.c struct clkdiv *clkdiv = to_clkdiv(hw); clkdiv 97 drivers/clk/qcom/clk-spmi-pmic-div.c spin_lock_irqsave(&clkdiv->lock, flags); clkdiv 98 drivers/clk/qcom/clk-spmi-pmic-div.c ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true); clkdiv 99 drivers/clk/qcom/clk-spmi-pmic-div.c spin_unlock_irqrestore(&clkdiv->lock, flags); clkdiv 106 drivers/clk/qcom/clk-spmi-pmic-div.c struct clkdiv *clkdiv = to_clkdiv(hw); clkdiv 109 drivers/clk/qcom/clk-spmi-pmic-div.c spin_lock_irqsave(&clkdiv->lock, flags); clkdiv 110 drivers/clk/qcom/clk-spmi-pmic-div.c spmi_pmic_clkdiv_set_enable_state(clkdiv, false); clkdiv 111 drivers/clk/qcom/clk-spmi-pmic-div.c spin_unlock_irqrestore(&clkdiv->lock, flags); clkdiv 129 drivers/clk/qcom/clk-spmi-pmic-div.c struct clkdiv *clkdiv = to_clkdiv(hw); clkdiv 132 drivers/clk/qcom/clk-spmi-pmic-div.c regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); clkdiv 141 drivers/clk/qcom/clk-spmi-pmic-div.c struct clkdiv *clkdiv = to_clkdiv(hw); clkdiv 147 drivers/clk/qcom/clk-spmi-pmic-div.c spin_lock_irqsave(&clkdiv->lock, flags); clkdiv 148 drivers/clk/qcom/clk-spmi-pmic-div.c enabled = is_spmi_pmic_clkdiv_enabled(clkdiv); clkdiv 150 drivers/clk/qcom/clk-spmi-pmic-div.c ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false); clkdiv 155 drivers/clk/qcom/clk-spmi-pmic-div.c ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, clkdiv 161 drivers/clk/qcom/clk-spmi-pmic-div.c ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true, clkdiv 165 drivers/clk/qcom/clk-spmi-pmic-div.c spin_unlock_irqrestore(&clkdiv->lock, flags); clkdiv 180 drivers/clk/qcom/clk-spmi-pmic-div.c struct clkdiv clks[]; clkdiv 202 drivers/clk/qcom/clk-spmi-pmic-div.c struct clkdiv *clkdiv; clkdiv 260 drivers/clk/qcom/clk-spmi-pmic-div.c for (i = 0, clkdiv = cc->clks; i < nclks; i++) { clkdiv 263 drivers/clk/qcom/clk-spmi-pmic-div.c spin_lock_init(&clkdiv[i].lock); clkdiv 264 drivers/clk/qcom/clk-spmi-pmic-div.c clkdiv[i].base = start + i * 0x100; clkdiv 265 drivers/clk/qcom/clk-spmi-pmic-div.c clkdiv[i].regmap = regmap; clkdiv 266 drivers/clk/qcom/clk-spmi-pmic-div.c clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz; clkdiv 267 drivers/clk/qcom/clk-spmi-pmic-div.c clkdiv[i].hw.init = &init; clkdiv 269 drivers/clk/qcom/clk-spmi-pmic-div.c ret = devm_clk_hw_register(dev, &clkdiv[i].hw); clkdiv 32 drivers/cpufreq/s3c2410-cpufreq.c u32 clkdiv = 0; clkdiv 35 drivers/cpufreq/s3c2410-cpufreq.c clkdiv |= S3C2410_CLKDIVN_HDIVN; clkdiv 38 drivers/cpufreq/s3c2410-cpufreq.c clkdiv |= S3C2410_CLKDIVN_PDIVN; clkdiv 40 drivers/cpufreq/s3c2410-cpufreq.c __raw_writel(clkdiv, S3C2410_CLKDIVN); clkdiv 117 drivers/cpufreq/s3c2412-cpufreq.c unsigned long clkdiv; clkdiv 120 drivers/cpufreq/s3c2412-cpufreq.c olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN); clkdiv 124 drivers/cpufreq/s3c2412-cpufreq.c clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN; clkdiv 125 drivers/cpufreq/s3c2412-cpufreq.c clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK; clkdiv 126 drivers/cpufreq/s3c2412-cpufreq.c clkdiv &= ~S3C2412_CLKDIVN_PDIVN; clkdiv 129 drivers/cpufreq/s3c2412-cpufreq.c clkdiv |= S3C2412_CLKDIVN_ARMDIVN; clkdiv 131 drivers/cpufreq/s3c2412-cpufreq.c clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1); clkdiv 134 drivers/cpufreq/s3c2412-cpufreq.c clkdiv |= S3C2412_CLKDIVN_PDIVN; clkdiv 136 drivers/cpufreq/s3c2412-cpufreq.c s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv); clkdiv 137 drivers/cpufreq/s3c2412-cpufreq.c __raw_writel(clkdiv, S3C2410_CLKDIVN); clkdiv 141 drivers/cpufreq/s3c2440-cpufreq.c unsigned long clkdiv, camdiv; clkdiv 146 drivers/cpufreq/s3c2440-cpufreq.c clkdiv = __raw_readl(S3C2410_CLKDIVN); clkdiv 149 drivers/cpufreq/s3c2440-cpufreq.c clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN); clkdiv 154 drivers/cpufreq/s3c2440-cpufreq.c clkdiv |= S3C2440_CLKDIVN_HDIVN_1; clkdiv 158 drivers/cpufreq/s3c2440-cpufreq.c clkdiv |= S3C2440_CLKDIVN_HDIVN_2; clkdiv 164 drivers/cpufreq/s3c2440-cpufreq.c clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6; clkdiv 170 drivers/cpufreq/s3c2440-cpufreq.c clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8; clkdiv 178 drivers/cpufreq/s3c2440-cpufreq.c clkdiv |= S3C2440_CLKDIVN_PDIVN; clkdiv 188 drivers/cpufreq/s3c2440-cpufreq.c __raw_writel(clkdiv, S3C2410_CLKDIVN); clkdiv 144 drivers/gpu/drm/exynos/exynos7_drm_decon.c u32 clkdiv; clkdiv 147 drivers/gpu/drm/exynos/exynos7_drm_decon.c clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); clkdiv 149 drivers/gpu/drm/exynos/exynos7_drm_decon.c return (clkdiv < 0x100) ? clkdiv : 0xff; clkdiv 156 drivers/gpu/drm/exynos/exynos7_drm_decon.c u32 val, clkdiv; clkdiv 205 drivers/gpu/drm/exynos/exynos7_drm_decon.c clkdiv = decon_calc_clkdiv(ctx, mode); clkdiv 206 drivers/gpu/drm/exynos/exynos7_drm_decon.c if (clkdiv > 1) { clkdiv 207 drivers/gpu/drm/exynos/exynos7_drm_decon.c val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); clkdiv 189 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 clkdiv; clkdiv 396 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 clkdiv; clkdiv 422 drivers/gpu/drm/exynos/exynos_drm_fimd.c clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk); clkdiv 423 drivers/gpu/drm/exynos/exynos_drm_fimd.c if (clkdiv >= 0x200) { clkdiv 429 drivers/gpu/drm/exynos/exynos_drm_fimd.c ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff; clkdiv 564 drivers/gpu/drm/exynos/exynos_drm_fimd.c if (ctx->clkdiv > 1) clkdiv 565 drivers/gpu/drm/exynos/exynos_drm_fimd.c val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; clkdiv 43 drivers/gpu/drm/exynos/exynos_drm_vidi.c unsigned int clkdiv; clkdiv 448 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c u16 clkdiv; clkdiv 465 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c clkdiv = calc_clkdiv(SYSTEMCLK, PWM_FREQUENCY); clkdiv 467 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c ret = intel_scu_ipc_iowrite8(PWM0CLKDIV1, (clkdiv >> 8) & 0xff); clkdiv 469 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c ret = intel_scu_ipc_iowrite8(PWM0CLKDIV0, clkdiv & 0xff); clkdiv 475 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c clkdiv, PWM_FREQUENCY); clkdiv 210 drivers/gpu/drm/tilcdc/tilcdc_crtc.c unsigned int clkdiv; clkdiv 213 drivers/gpu/drm/tilcdc/tilcdc_crtc.c clkdiv = 2; /* first try using a standard divider of 2 */ clkdiv 218 drivers/gpu/drm/tilcdc/tilcdc_crtc.c ret = clk_set_rate(priv->clk, req_rate * clkdiv); clkdiv 235 drivers/gpu/drm/tilcdc/tilcdc_crtc.c clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate); clkdiv 244 drivers/gpu/drm/tilcdc/tilcdc_crtc.c real_rate = clkdiv * req_rate; clkdiv 256 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv); clkdiv 259 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) | clkdiv 27 drivers/hwtracing/intel_th/pti.c unsigned int clkdiv; clkdiv 113 drivers/hwtracing/intel_th/pti.c return scnprintf(buf, PAGE_SIZE, "%d\n", 1u << pti->clkdiv); clkdiv 131 drivers/hwtracing/intel_th/pti.c pti->clkdiv = val; clkdiv 159 drivers/hwtracing/intel_th/pti.c ctl |= pti->clkdiv << __ffs(PTI_CLKDIV); clkdiv 183 drivers/hwtracing/intel_th/pti.c pti->clkdiv = (ctl & PTI_CLKDIV) >> __ffs(PTI_CLKDIV); clkdiv 188 drivers/hwtracing/intel_th/pti.c if (!pti->clkdiv) clkdiv 189 drivers/hwtracing/intel_th/pti.c pti->clkdiv = 1; clkdiv 313 drivers/i2c/busses/i2c-efm32.c u32 clkdiv; clkdiv 402 drivers/i2c/busses/i2c-efm32.c clkdiv = DIV_ROUND_UP(rate, 8 * ddata->frequency) - 1; clkdiv 403 drivers/i2c/busses/i2c-efm32.c if (clkdiv >= 0x200) { clkdiv 412 drivers/i2c/busses/i2c-efm32.c rate, ddata->frequency, (unsigned long)clkdiv); clkdiv 413 drivers/i2c/busses/i2c-efm32.c efm32_i2c_write32(ddata, REG_CLKDIV, REG_CLKDIV_DIV(clkdiv)); clkdiv 90 drivers/i2c/busses/i2c-ibm_iic.c in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt), clkdiv 152 drivers/i2c/busses/i2c-ibm_iic.c out_8(&iic->clkdiv, dev->clckdiv); clkdiv 33 drivers/i2c/busses/i2c-ibm_iic.h u8 clkdiv; clkdiv 123 drivers/iio/adc/lpc18xx_adc.c unsigned int clkdiv; clkdiv 148 drivers/iio/adc/lpc18xx_adc.c clkdiv = DIV_ROUND_UP(rate, LPC18XX_ADC_CLK_TARGET); clkdiv 175 drivers/iio/adc/lpc18xx_adc.c adc->cr_reg = (clkdiv << LPC18XX_ADC_CR_CLKDIV_SHIFT) | clkdiv 123 drivers/media/dvb-frontends/cx24120.c u8 clkdiv; clkdiv 1113 drivers/media/dvb-frontends/cx24120.c state->dnxt.clkdiv = (-(rate < 31000001) & 3) + 2; clkdiv 1116 drivers/media/dvb-frontends/cx24120.c state->dnxt.clkdiv = 3; clkdiv 1188 drivers/media/dvb-frontends/cx24120.c state->dcur.clkdiv, state->dcur.ratediv); clkdiv 1215 drivers/media/dvb-frontends/cx24120.c cmd.arg[13] = state->dcur.clkdiv; clkdiv 1224 drivers/media/dvb-frontends/cx24120.c ret = cx24120_writereg(state, CX24120_REG_CLKDIV, state->dcur.clkdiv); clkdiv 375 drivers/media/dvb-frontends/stv6111.c u32 clkdiv = 0; clkdiv 395 drivers/media/dvb-frontends/stv6111.c if (clkdiv <= 3) clkdiv 396 drivers/media/dvb-frontends/stv6111.c state->reg[0x00] |= (clkdiv & 0x03); clkdiv 55 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c __le16 clkdiv; clkdiv 124 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c writew(TWI_CLKDIV, &i2c->regs->clkdiv); clkdiv 162 drivers/media/rc/tango-ir.c u64 clkrate, clkdiv; clkdiv 215 drivers/media/rc/tango-ir.c clkdiv = clkrate * NEC_TIME_BASE; clkdiv 216 drivers/media/rc/tango-ir.c do_div(clkdiv, 1000000); clkdiv 218 drivers/media/rc/tango-ir.c val = NEC_CAP(31) | GPIO_SEL(12) | clkdiv; clkdiv 221 drivers/media/rc/tango-ir.c clkdiv = clkrate * RC5_TIME_BASE; clkdiv 222 drivers/media/rc/tango-ir.c do_div(clkdiv, 1000000); clkdiv 225 drivers/media/rc/tango-ir.c writel_relaxed(clkdiv, ir->rc5_base + IR_RC5_CLK_DIV); clkdiv 228 drivers/media/rc/tango-ir.c clkdiv = clkrate * RC6_TIME_BASE; clkdiv 229 drivers/media/rc/tango-ir.c do_div(clkdiv, RC6_CARRIER); clkdiv 232 drivers/media/rc/tango-ir.c writel_relaxed((clkdiv >> 2) << 18 | clkdiv, ir->rc6_base + RC6_CLKDIV); clkdiv 1393 drivers/mmc/host/atmel-mci.c int clkdiv; clkdiv 1416 drivers/mmc/host/atmel-mci.c clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2; clkdiv 1417 drivers/mmc/host/atmel-mci.c if (clkdiv < 0) { clkdiv 1421 drivers/mmc/host/atmel-mci.c clkdiv = 0; clkdiv 1422 drivers/mmc/host/atmel-mci.c } else if (clkdiv > 511) { clkdiv 1426 drivers/mmc/host/atmel-mci.c clkdiv = 511; clkdiv 1428 drivers/mmc/host/atmel-mci.c host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) clkdiv 1429 drivers/mmc/host/atmel-mci.c | ATMCI_MR_CLKODD(clkdiv & 1); clkdiv 1431 drivers/mmc/host/atmel-mci.c clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; clkdiv 1432 drivers/mmc/host/atmel-mci.c if (clkdiv > 255) { clkdiv 1436 drivers/mmc/host/atmel-mci.c clkdiv = 255; clkdiv 1438 drivers/mmc/host/atmel-mci.c host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); clkdiv 538 drivers/mmc/host/omap_hsmmc.c unsigned long clkdiv; clkdiv 546 drivers/mmc/host/omap_hsmmc.c clkdiv = calc_divisor(host, ios); clkdiv 547 drivers/mmc/host/omap_hsmmc.c regval = regval | (clkdiv << 6) | (DTO << 16); clkdiv 572 drivers/mmc/host/omap_hsmmc.c if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) clkdiv 659 drivers/mmc/host/sdhci-omap.c unsigned long clkdiv; clkdiv 666 drivers/mmc/host/sdhci-omap.c clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock); clkdiv 667 drivers/mmc/host/sdhci-omap.c clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT; clkdiv 668 drivers/mmc/host/sdhci-omap.c sdhci_enable_clk(host, clkdiv); clkdiv 480 drivers/mmc/host/sh_mmcif.c unsigned int clkdiv; clkdiv 492 drivers/mmc/host/sh_mmcif.c clkdiv = 0; clkdiv 511 drivers/mmc/host/sh_mmcif.c clkdiv = i; clkdiv 517 drivers/mmc/host/sh_mmcif.c (best_freq / (1 << (clkdiv + 1))), clk, clkdiv 518 drivers/mmc/host/sh_mmcif.c best_freq, clkdiv); clkdiv 521 drivers/mmc/host/sh_mmcif.c clkdiv = clkdiv << 16; clkdiv 523 drivers/mmc/host/sh_mmcif.c clkdiv = CLK_SUP_PCLK; clkdiv 525 drivers/mmc/host/sh_mmcif.c clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; clkdiv 528 drivers/mmc/host/sh_mmcif.c sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); clkdiv 270 drivers/net/ethernet/chelsio/cxgb/subr.c u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1; clkdiv 272 drivers/net/ethernet/chelsio/cxgb/subr.c V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv); clkdiv 198 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1; clkdiv 199 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val = F_PREEN | V_CLKDIV(clkdiv); clkdiv 1183 drivers/net/ethernet/ethoc.c u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1); clkdiv 1185 drivers/net/ethernet/ethoc.c if (!clkdiv) clkdiv 1186 drivers/net/ethernet/ethoc.c clkdiv = 2; clkdiv 1187 drivers/net/ethernet/ethoc.c dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv); clkdiv 1190 drivers/net/ethernet/ethoc.c clkdiv); clkdiv 79 drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h u32 clkdiv; /* corerev >= 3 */ clkdiv 124 drivers/pwm/pwm-mediatek.c u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, clkdiv 141 drivers/pwm/pwm-mediatek.c clkdiv++; clkdiv 146 drivers/pwm/pwm-mediatek.c if (clkdiv > PWM_CLK_DIV_MAX) { clkdiv 162 drivers/pwm/pwm-mediatek.c pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); clkdiv 153 drivers/pwm/pwm-tiehrpwm.c unsigned int clkdiv, hspclkdiv; clkdiv 155 drivers/pwm/pwm-tiehrpwm.c for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { clkdiv 168 drivers/pwm/pwm-tiehrpwm.c *prescale_div = (1 << clkdiv) * clkdiv 171 drivers/pwm/pwm-tiehrpwm.c *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | clkdiv 36 drivers/spi/spi-cavium.c unsigned int clkdiv; clkdiv 48 drivers/spi/spi-cavium.c clkdiv = p->sys_freq / (2 * xfer->speed_hz); clkdiv 52 drivers/spi/spi-cavium.c mpi_cfg.s.clkdiv = clkdiv; clkdiv 46 drivers/spi/spi-cavium.h uint64_t clkdiv:13; clkdiv 78 drivers/spi/spi-cavium.h uint64_t clkdiv:13; clkdiv 85 drivers/spi/spi-cavium.h uint64_t clkdiv:13; clkdiv 111 drivers/spi/spi-cavium.h uint64_t clkdiv:13; clkdiv 118 drivers/spi/spi-cavium.h uint64_t clkdiv:13; clkdiv 142 drivers/spi/spi-cavium.h uint64_t clkdiv:13; clkdiv 150 drivers/spi/spi-cavium.h uint64_t clkdiv:13; clkdiv 180 drivers/spi/spi-cavium.h uint64_t clkdiv:13; clkdiv 187 drivers/spi/spi-cavium.h uint64_t clkdiv:13; clkdiv 217 drivers/spi/spi-cavium.h uint64_t clkdiv:13; clkdiv 121 drivers/spi/spi-efm32.c u32 clkdiv; clkdiv 131 drivers/spi/spi-efm32.c clkdiv = 0; clkdiv 133 drivers/spi/spi-efm32.c clkdiv = 64 * (DIV_ROUND_UP(2 * clkfreq, speed) - 4); clkdiv 135 drivers/spi/spi-efm32.c if (clkdiv > (1U << 21)) clkdiv 138 drivers/spi/spi-efm32.c efm32_spi_write32(ddata, clkdiv, REG_CLKDIV); clkdiv 1953 drivers/tty/serial/amba-pl011.c unsigned int baud, quot, clkdiv; clkdiv 1956 drivers/tty/serial/amba-pl011.c clkdiv = 8; clkdiv 1958 drivers/tty/serial/amba-pl011.c clkdiv = 16; clkdiv 1964 drivers/tty/serial/amba-pl011.c port->uartclk / clkdiv); clkdiv 353 drivers/tty/serial/efm32-uart.c u32 clkdiv; clkdiv 396 drivers/tty/serial/efm32-uart.c clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6; clkdiv 421 drivers/tty/serial/efm32-uart.c efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV); clkdiv 560 drivers/tty/serial/efm32-uart.c u32 route, clkdiv, frame; clkdiv 571 drivers/tty/serial/efm32-uart.c clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV); clkdiv 574 drivers/tty/serial/efm32-uart.c 16 * (4 + (clkdiv >> 6))); clkdiv 1292 drivers/video/fbdev/s3c-fb.c int clkdiv; clkdiv 1298 drivers/video/fbdev/s3c-fb.c clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock); clkdiv 1303 drivers/video/fbdev/s3c-fb.c if (clkdiv > 1) clkdiv 1304 drivers/video/fbdev/s3c-fb.c data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR; clkdiv 379 drivers/video/fbdev/s3c2410fb.c int clkdiv; clkdiv 381 drivers/video/fbdev/s3c2410fb.c clkdiv = DIV_ROUND_UP(s3c2410fb_calc_pixclk(fbi, var->pixclock), 2); clkdiv 389 drivers/video/fbdev/s3c2410fb.c --clkdiv; clkdiv 390 drivers/video/fbdev/s3c2410fb.c if (clkdiv < 0) clkdiv 391 drivers/video/fbdev/s3c2410fb.c clkdiv = 0; clkdiv 394 drivers/video/fbdev/s3c2410fb.c if (clkdiv < 2) clkdiv 395 drivers/video/fbdev/s3c2410fb.c clkdiv = 2; clkdiv 398 drivers/video/fbdev/s3c2410fb.c fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv); clkdiv 62 drivers/video/fbdev/vga16fb.c u8 misc, pel_msk, vss, clkdiv; clkdiv 277 drivers/video/fbdev/vga16fb.c par->clkdiv = best->seq_clock_mode; clkdiv 526 drivers/video/fbdev/vga16fb.c seq[VGA_SEQ_CLOCK_MODE] = 0x01 | par->clkdiv; clkdiv 95 drivers/w1/masters/mxc_w1.c unsigned int clkdiv; clkdiv 116 drivers/w1/masters/mxc_w1.c clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000); clkdiv 117 drivers/w1/masters/mxc_w1.c clkrate /= clkdiv; clkdiv 132 drivers/w1/masters/mxc_w1.c writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER); clkdiv 80 sound/soc/adi/axi-spdif.c unsigned int clkdiv, stat; clkdiv 97 sound/soc/adi/axi-spdif.c clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), clkdiv 99 sound/soc/adi/axi-spdif.c clkdiv <<= AXI_SPDIF_CTRL_CLKDIV_OFFSET; clkdiv 103 sound/soc/adi/axi-spdif.c AXI_SPDIF_CTRL_CLKDIV_MASK, clkdiv); clkdiv 300 sound/soc/codecs/adau1701.c static int adau1701_reset(struct snd_soc_component *component, unsigned int clkdiv, clkdiv 308 sound/soc/codecs/adau1701.c if (clkdiv != ADAU1707_CLKDIV_UNSET && clkdiv 311 sound/soc/codecs/adau1701.c switch (clkdiv) { clkdiv 332 sound/soc/codecs/adau1701.c adau1701->pll_clkdiv = clkdiv; clkdiv 347 sound/soc/codecs/adau1701.c if (clkdiv != ADAU1707_CLKDIV_UNSET) { clkdiv 439 sound/soc/codecs/adau1701.c unsigned int clkdiv = adau1701->sysclk / params_rate(params); clkdiv 448 sound/soc/codecs/adau1701.c if (clkdiv != adau1701->pll_clkdiv) { clkdiv 449 sound/soc/codecs/adau1701.c ret = adau1701_reset(component, clkdiv, params_rate(params)); clkdiv 34 sound/soc/fsl/wm1133-ev1.c unsigned int clkdiv; clkdiv 129 sound/soc/fsl/wm1133-ev1.c WM8350_DAC_CLKDIV, wm8350_audio[i].clkdiv); clkdiv 132 sound/soc/fsl/wm1133-ev1.c WM8350_ADC_CLKDIV, wm8350_audio[i].clkdiv); clkdiv 298 sound/soc/intel/skylake/skl-nhlt.c u32 clkdiv, div_ratio; clkdiv 309 sound/soc/intel/skylake/skl-nhlt.c clkdiv = i2s_config->mclk.mdivr & clkdiv 314 sound/soc/intel/skylake/skl-nhlt.c clkdiv = i2s_config_ext->mclk.mdivr[0] & clkdiv 321 sound/soc/intel/skylake/skl-nhlt.c if (clkdiv != SKL_MCLK_DIV_RATIO_MASK) clkdiv 323 sound/soc/intel/skylake/skl-nhlt.c div_ratio = clkdiv + 2;