clk_type 878 drivers/clk/clk-u300.c u32 clk_type; clk_type 882 drivers/clk/clk-u300.c if (of_property_read_u32(np, "clock-type", &clk_type)) { clk_type 894 drivers/clk/clk-u300.c switch (clk_type) { clk_type 908 drivers/clk/clk-u300.c pr_err("unknown clock type %x specified\n", clk_type); clk_type 915 drivers/clk/clk-u300.c if (u3clk->type == clk_type && u3clk->id == clk_id) clk_type 931 drivers/clk/clk-u300.c if (clk_type == U300_CLK_TYPE_REST && clk_id == 5) clk_type 933 drivers/clk/clk-u300.c if (clk_type == U300_CLK_TYPE_REST && clk_id == 9) clk_type 935 drivers/clk/clk-u300.c if (clk_type == U300_CLK_TYPE_REST && clk_id == 12) clk_type 29 drivers/clk/imx/clk-scu.c u8 clk_type; clk_type 158 drivers/clk/imx/clk-scu.c msg.data.req.clk = clk->clk_type; clk_type 230 drivers/clk/imx/clk-scu.c msg.clk = clk->clk_type; clk_type 248 drivers/clk/imx/clk-scu.c msg.data.req.clk = clk->clk_type; clk_type 272 drivers/clk/imx/clk-scu.c msg.clk = clk->clk_type; clk_type 308 drivers/clk/imx/clk-scu.c clk->clk_type, true, false); clk_type 323 drivers/clk/imx/clk-scu.c clk->clk_type, false, false); clk_type 348 drivers/clk/imx/clk-scu.c int num_parents, u32 rsrc_id, u8 clk_type) clk_type 360 drivers/clk/imx/clk-scu.c clk->clk_type = clk_type; clk_type 15 drivers/clk/imx/clk-scu.h int num_parents, u32 rsrc_id, u8 clk_type); clk_type 18 drivers/clk/imx/clk-scu.h u8 clk_type) clk_type 20 drivers/clk/imx/clk-scu.h return __imx_clk_scu(name, NULL, 0, rsrc_id, clk_type); clk_type 24 drivers/clk/imx/clk-scu.h int num_parents, u32 rsrc_id, u8 clk_type) clk_type 26 drivers/clk/imx/clk-scu.h return __imx_clk_scu(name, parents, num_parents, rsrc_id, clk_type); clk_type 73 drivers/clk/zynqmp/clkc.c enum clk_type type; clk_type 527 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c u32 freq, u8 clk_type, u8 clk_src) clk_type 546 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v2_1.asParam.ucDCEClkType = clk_type; clk_type 41 drivers/gpu/drm/amd/amdgpu/atombios_crtc.h u32 freq, u8 clk_type, u8 clk_src); clk_type 120 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum dm_pp_clock_type clk_type, clk_type 129 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c switch (clk_type) { clk_type 333 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum dm_pp_clock_type clk_type, clk_type 344 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c dc_to_pp_clock_type(clk_type), &pp_clks)) { clk_type 346 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c get_default_clock_levels(clk_type, dc_clks); clk_type 351 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c dc_to_pp_clock_type(clk_type), clk_type 353 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c get_default_clock_levels(clk_type, dc_clks); clk_type 358 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); clk_type 391 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { clk_type 403 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) { clk_type 419 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum dm_pp_clock_type clk_type, clk_type 430 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c dc_to_pp_clock_type(clk_type), clk_type 436 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c dc_to_smu_clock_type(clk_type), clk_type 442 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type); clk_type 449 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum dm_pp_clock_type clk_type, clk_type 460 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c dc_to_pp_clock_type(clk_type), clk_type 466 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c dc_to_pp_clock_type(clk_type), clk_type 471 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type); clk_type 500 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c pp_clock_request.clock_type = dc_to_pp_clock_type(clock_for_voltage_req->clk_type); clk_type 98 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; clk_type 113 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; clk_type 763 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; clk_type 778 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; clk_type 200 drivers/gpu/drm/amd/display/dc/dm_services.h enum dm_pp_clock_type clk_type, clk_type 205 drivers/gpu/drm/amd/display/dc/dm_services.h enum dm_pp_clock_type clk_type, clk_type 210 drivers/gpu/drm/amd/display/dc/dm_services.h enum dm_pp_clock_type clk_type, clk_type 82 drivers/gpu/drm/amd/display/dc/dm_services_types.h #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ clk_type 83 drivers/gpu/drm/amd/display/dc/dm_services_types.h (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \ clk_type 84 drivers/gpu/drm/amd/display/dc/dm_services_types.h (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \ clk_type 85 drivers/gpu/drm/amd/display/dc/dm_services_types.h (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \ clk_type 86 drivers/gpu/drm/amd/display/dc/dm_services_types.h (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \ clk_type 87 drivers/gpu/drm/amd/display/dc/dm_services_types.h (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \ clk_type 88 drivers/gpu/drm/amd/display/dc/dm_services_types.h (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \ clk_type 89 drivers/gpu/drm/amd/display/dc/dm_services_types.h (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \ clk_type 90 drivers/gpu/drm/amd/display/dc/dm_services_types.h (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \ clk_type 91 drivers/gpu/drm/amd/display/dc/dm_services_types.h (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \ clk_type 92 drivers/gpu/drm/amd/display/dc/dm_services_types.h (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \ clk_type 253 drivers/gpu/drm/amd/display/dc/dm_services_types.h enum dm_pp_clock_type clk_type; clk_type 159 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 168 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c if (!smu_clk_dpm_is_enabled(smu, clk_type)) clk_type 171 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clk_id = smu_clk_get_index(smu, clk_type); clk_type 195 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 204 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c if (!smu_clk_dpm_is_enabled(smu, clk_type)) clk_type 207 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clk_id = smu_clk_get_index(smu, clk_type); clk_type 231 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 240 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c if (!smu_clk_dpm_is_enabled(smu, clk_type)) { clk_type 241 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c switch (clk_type) { clk_type 270 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max); clk_type 274 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 283 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c if (!smu_clk_dpm_is_enabled(smu, clk_type)) clk_type 286 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clk_id = smu_clk_get_index(smu, clk_type); clk_type 308 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 311 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value); clk_type 314 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type) clk_type 318 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c switch (clk_type) { clk_type 1095 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c enum smu_clk_type clk_type, clk_type 1104 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c clk_id = smu_clk_get_index(smu, clk_type); clk_type 60 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c enum amd_pp_clock_type clk_type = clock_req->clock_type; clk_type 64 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c switch (clk_type) { clk_type 3856 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c enum amd_pp_clock_type clk_type = clock_req->clock_type; clk_type 3861 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c switch (clk_type) { clk_type 1435 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c enum amd_pp_clock_type clk_type = clock_req->clock_type; clk_type 1441 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c switch (clk_type) { clk_type 2246 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c enum amd_pp_clock_type clk_type = clock_req->clock_type; clk_type 2252 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c switch (clk_type) { clk_type 408 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); clk_type 409 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); clk_type 411 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type); clk_type 413 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum smu_clk_type clk_type, clk_type 419 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum smu_clk_type clk_type, clk_type 454 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum smu_clk_type clk_type, clk_type 542 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); clk_type 638 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_print_clk_levels(smu, clk_type, buf) \ clk_type 639 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0) clk_type 640 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_force_clk_levels(smu, clk_type, level) \ clk_type 641 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0) clk_type 715 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \ clk_type 716 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0) clk_type 741 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \ clk_type 742 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0) clk_type 818 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 820 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 822 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 824 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 826 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 831 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type); clk_type 651 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type, clk_type 661 drivers/gpu/drm/amd/powerplay/navi10_ppt.c clk_id = smu_clk_get_index(smu, clk_type); clk_type 670 drivers/gpu/drm/amd/powerplay/navi10_ppt.c static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) clk_type 676 drivers/gpu/drm/amd/powerplay/navi10_ppt.c clk_index = smu_clk_get_index(smu, clk_type); clk_type 684 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type, char *buf) clk_type 691 drivers/gpu/drm/amd/powerplay/navi10_ppt.c switch (clk_type) { clk_type 699 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_current_clk_freq(smu, clk_type, &cur_value); clk_type 706 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_dpm_level_count(smu, clk_type, &count); clk_type 710 drivers/gpu/drm/amd/powerplay/navi10_ppt.c if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { clk_type 712 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value); clk_type 720 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); clk_type 723 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); clk_type 748 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type, uint32_t mask) clk_type 757 drivers/gpu/drm/amd/powerplay/navi10_ppt.c switch (clk_type) { clk_type 766 drivers/gpu/drm/amd/powerplay/navi10_ppt.c if (navi10_is_support_fine_grained_dpm(smu, clk_type)) { clk_type 771 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); clk_type 775 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); clk_type 779 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq); clk_type 811 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type, clk_type 817 drivers/gpu/drm/amd/powerplay/navi10_ppt.c switch (clk_type) { clk_type 821 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_dpm_level_count(smu, clk_type, &level_count); clk_type 829 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq); clk_type 894 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type; clk_type 903 drivers/gpu/drm/amd/powerplay/navi10_ppt.c clk_type = clks[i]; clk_type 904 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq); clk_type 909 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq); clk_type 921 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type; clk_type 930 drivers/gpu/drm/amd/powerplay/navi10_ppt.c clk_type = clks[i]; clk_type 931 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq); clk_type 935 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq); clk_type 181 drivers/gpu/drm/amd/powerplay/renoir_ppt.c enum smu_clk_type clk_type, char *buf) clk_type 189 drivers/gpu/drm/amd/powerplay/renoir_ppt.c if (!clk_table || clk_type >= SMU_CLK_COUNT) clk_type 199 drivers/gpu/drm/amd/powerplay/renoir_ppt.c switch (clk_type) { clk_type 244 drivers/gpu/drm/amd/powerplay/renoir_ppt.c GET_DPM_CUR_FREQ(clk_table, clk_type, i, value); clk_type 33 drivers/gpu/drm/amd/powerplay/renoir_ppt.h #define GET_DPM_CUR_FREQ(table, clk_type, dpm_level, freq) \ clk_type 35 drivers/gpu/drm/amd/powerplay/renoir_ppt.h switch (clk_type) { \ clk_type 1285 drivers/gpu/drm/amd/powerplay/smu_v11_0.c enum amd_pp_clock_type clk_type = clock_req->clock_type; clk_type 1295 drivers/gpu/drm/amd/powerplay/smu_v11_0.c switch (clk_type) { clk_type 1725 drivers/gpu/drm/amd/powerplay/smu_v11_0.c static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 1732 drivers/gpu/drm/amd/powerplay/smu_v11_0.c clk_id = smu_clk_get_index(smu, clk_type); clk_type 322 drivers/gpu/drm/amd/powerplay/smu_v12_0.c static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, clk_type 330 drivers/gpu/drm/amd/powerplay/smu_v12_0.c switch (clk_type) { clk_type 355 drivers/gpu/drm/amd/powerplay/smu_v12_0.c switch (clk_type) { clk_type 1272 drivers/gpu/drm/amd/powerplay/vega20_ppt.c enum smu_clk_type clk_type, uint32_t mask) clk_type 1292 drivers/gpu/drm/amd/powerplay/vega20_ppt.c switch (clk_type) { clk_type 1444 drivers/gpu/drm/amd/powerplay/vega20_ppt.c enum smu_clk_type clk_type, clk_type 1456 drivers/gpu/drm/amd/powerplay/vega20_ppt.c switch (clk_type) { clk_type 1750 drivers/gpu/drm/amd/powerplay/vega20_ppt.c enum smu_clk_type clk_type) clk_type 1762 drivers/gpu/drm/amd/powerplay/vega20_ppt.c switch (clk_type) { clk_type 2540 drivers/gpu/drm/amd/powerplay/vega20_ppt.c enum smu_clk_type clk_type, clk_type 2558 drivers/gpu/drm/amd/powerplay/vega20_ppt.c switch (clk_type) { clk_type 49 drivers/input/evdev.c enum input_clock_type clk_type; clk_type 146 drivers/input/evdev.c struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); clk_type 177 drivers/input/evdev.c enum input_clock_type clk_type; clk_type 182 drivers/input/evdev.c clk_type = INPUT_CLK_REAL; clk_type 185 drivers/input/evdev.c clk_type = INPUT_CLK_MONO; clk_type 188 drivers/input/evdev.c clk_type = INPUT_CLK_BOOT; clk_type 194 drivers/input/evdev.c if (client->clk_type != clk_type) { clk_type 195 drivers/input/evdev.c client->clk_type = clk_type; clk_type 257 drivers/input/evdev.c ts = ktime_to_timespec64(ev_time[client->clk_type]); clk_type 1392 drivers/media/dvb-frontends/mxl5xx.c u32 clk_type = 0; clk_type 1475 drivers/media/dvb-frontends/mxl5xx.c clk_type = 1; clk_type 1482 drivers/media/dvb-frontends/mxl5xx.c clk_type); clk_type 1484 drivers/media/dvb-frontends/mxl5xx.c update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type); clk_type 101 drivers/nfc/s3fwrn5/nci.c fw_cfg.clk_type = 0x01; clk_type 64 drivers/nfc/s3fwrn5/nci.h __u8 clk_type; clk_type 534 drivers/phy/phy-xgene.c enum clk_type_t clk_type; /* Input clock selection */ clk_type 705 drivers/phy/phy-xgene.c enum clk_type_t clk_type) clk_type 718 drivers/phy/phy-xgene.c if (clk_type == CLK_EXT_DIFF) { clk_type 728 drivers/phy/phy-xgene.c } else if (clk_type == CLK_INT_DIFF) { clk_type 738 drivers/phy/phy-xgene.c } else if (clk_type == CLK_INT_SING) { clk_type 759 drivers/phy/phy-xgene.c enum clk_type_t clk_type) clk_type 805 drivers/phy/phy-xgene.c if (clk_type == CLK_EXT_DIFF) clk_type 1135 drivers/phy/phy-xgene.c enum clk_type_t clk_type) clk_type 1235 drivers/phy/phy-xgene.c enum clk_type_t clk_type) clk_type 1252 drivers/phy/phy-xgene.c enum clk_type_t clk_type, int ssc_enable) clk_type 1282 drivers/phy/phy-xgene.c xgene_phy_cfg_cmu_clk_type(ctx, PHY_CMU, clk_type); clk_type 1285 drivers/phy/phy-xgene.c xgene_phy_sata_cfg_cmu_core(ctx, PHY_CMU, clk_type); clk_type 1303 drivers/phy/phy-xgene.c if (!xgene_phy_cal_rdy_chk(ctx, PHY_CMU, clk_type)) clk_type 1306 drivers/phy/phy-xgene.c xgene_phy_pdwn_force_vco(ctx, PHY_CMU, clk_type); clk_type 1316 drivers/phy/phy-xgene.c enum clk_type_t clk_type, clk_type 1321 drivers/phy/phy-xgene.c dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type); clk_type 1324 drivers/phy/phy-xgene.c rc = xgene_phy_hw_init_sata(ctx, clk_type, ssc_enable); clk_type 2333 drivers/video/fbdev/aty/atyfb_base.c u8 dac_type, dac_subtype, clk_type; clk_type 2341 drivers/video/fbdev/aty/atyfb_base.c clk_type = CLK_ATI18818_1; clk_type 2350 drivers/video/fbdev/aty/atyfb_base.c clk_type = CLK_IBMRGB514; clk_type 2371 drivers/video/fbdev/aty/atyfb_base.c switch (clk_type) { clk_type 332 sound/soc/codecs/wcd9335.c enum wcd_clock_type clk_type; clk_type 4131 sound/soc/codecs/wcd9335.c if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || clk_type 4132 sound/soc/codecs/wcd9335.c ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { clk_type 4134 sound/soc/codecs/wcd9335.c wcd->clk_type); clk_type 4163 sound/soc/codecs/wcd9335.c wcd->clk_type = WCD_CLK_MCLK; clk_type 4179 sound/soc/codecs/wcd9335.c wcd->clk_type = WCD_CLK_RCO; clk_type 4184 sound/soc/codecs/wcd9335.c wcd->clk_type = WCD_CLK_OFF; clk_type 57 sound/soc/intel/skylake/skl-ssp-clk.c static int skl_get_vbus_id(u32 index, u8 clk_type) clk_type 59 sound/soc/intel/skylake/skl-ssp-clk.c switch (clk_type) { clk_type 74 sound/soc/intel/skylake/skl-ssp-clk.c static void skl_fill_clk_ipc(struct skl_clk_rate_cfg_table *rcfg, u8 clk_type) clk_type 84 sound/soc/intel/skylake/skl-ssp-clk.c if (clk_type == SKL_SCLK_FS) { clk_type 107 sound/soc/intel/skylake/skl-ssp-clk.c u32 vbus_id, u8 clk_type, clk_type 125 sound/soc/intel/skylake/skl-ssp-clk.c if (clk_type == SKL_SCLK_FS) { clk_type 132 sound/soc/intel/skylake/skl-ssp-clk.c if (clk_type == SKL_SCLK) clk_type 181 sound/soc/intel/skylake/skl-ssp-clk.c int vbus_id, clk_type; clk_type 183 sound/soc/intel/skylake/skl-ssp-clk.c clk_type = skl_get_clk_type(clkdev->id); clk_type 184 sound/soc/intel/skylake/skl-ssp-clk.c if (clk_type < 0) clk_type 185 sound/soc/intel/skylake/skl-ssp-clk.c return clk_type; clk_type 187 sound/soc/intel/skylake/skl-ssp-clk.c vbus_id = skl_get_vbus_id(clkdev->id, clk_type); clk_type 197 sound/soc/intel/skylake/skl-ssp-clk.c vbus_id, clk_type, enable); clk_type 219 sound/soc/intel/skylake/skl-ssp-clk.c int clk_type; clk_type 229 sound/soc/intel/skylake/skl-ssp-clk.c clk_type = skl_get_clk_type(clkdev->id); clk_type 230 sound/soc/intel/skylake/skl-ssp-clk.c if (clk_type < 0) clk_type 231 sound/soc/intel/skylake/skl-ssp-clk.c return clk_type; clk_type 233 sound/soc/intel/skylake/skl-ssp-clk.c skl_fill_clk_ipc(rcfg, clk_type);