clk_src_regs 316 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c static const struct dce110_clk_src_regs clk_src_regs[] = { clk_src_regs 317 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c clk_src_regs(0), clk_src_regs 318 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c clk_src_regs(1), clk_src_regs 319 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c clk_src_regs(2) clk_src_regs 929 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); clk_src_regs 931 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); clk_src_regs 933 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); clk_src_regs 938 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); clk_src_regs 941 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); clk_src_regs 943 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); clk_src_regs 346 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c static const struct dce110_clk_src_regs clk_src_regs[] = { clk_src_regs 347 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c clk_src_regs(0), clk_src_regs 348 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c clk_src_regs(1), clk_src_regs 349 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c clk_src_regs(2) clk_src_regs 1309 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c &clk_src_regs[0], false); clk_src_regs 1312 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c &clk_src_regs[1], false); clk_src_regs 349 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c static const struct dce110_clk_src_regs clk_src_regs[] = { clk_src_regs 350 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c clk_src_regs(0, A), clk_src_regs 351 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c clk_src_regs(1, B), clk_src_regs 352 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c clk_src_regs(2, C), clk_src_regs 353 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c clk_src_regs(3, D), clk_src_regs 354 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c clk_src_regs(4, E), clk_src_regs 355 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c clk_src_regs(5, F) clk_src_regs 1176 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c &clk_src_regs[0], false); clk_src_regs 1181 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c &clk_src_regs[1], false); clk_src_regs 1186 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c &clk_src_regs[2], false); clk_src_regs 1191 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c &clk_src_regs[3], false); clk_src_regs 1196 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c &clk_src_regs[4], false); clk_src_regs 1201 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c &clk_src_regs[5], false); clk_src_regs 1206 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); clk_src_regs 364 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c static const struct dce110_clk_src_regs clk_src_regs[] = { clk_src_regs 365 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c clk_src_regs(0, A), clk_src_regs 366 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c clk_src_regs(1, B), clk_src_regs 367 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c clk_src_regs(2, C), clk_src_regs 368 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c clk_src_regs(3, D), clk_src_regs 369 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c clk_src_regs(4, E), clk_src_regs 370 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c clk_src_regs(5, F) clk_src_regs 1019 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c &clk_src_regs[0], false); clk_src_regs 1023 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c &clk_src_regs[1], false); clk_src_regs 1027 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c &clk_src_regs[2], false); clk_src_regs 1031 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c &clk_src_regs[3], false); clk_src_regs 1035 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c &clk_src_regs[4], false); clk_src_regs 1039 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c &clk_src_regs[5], false); clk_src_regs 1045 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c &clk_src_regs[0], true); clk_src_regs 335 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c static const struct dce110_clk_src_regs clk_src_regs[] = { clk_src_regs 336 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c clk_src_regs(0), clk_src_regs 337 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c clk_src_regs(1), clk_src_regs 338 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c clk_src_regs(2) clk_src_regs 910 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); clk_src_regs 912 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); clk_src_regs 914 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); clk_src_regs 919 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); clk_src_regs 922 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); clk_src_regs 924 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); clk_src_regs 1107 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); clk_src_regs 1109 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); clk_src_regs 1111 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); clk_src_regs 1116 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); clk_src_regs 1119 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); clk_src_regs 1121 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); clk_src_regs 1304 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); clk_src_regs 1306 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); clk_src_regs 1311 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); clk_src_regs 1314 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); clk_src_regs 479 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dce110_clk_src_regs clk_src_regs[] = { clk_src_regs 480 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c clk_src_regs(0, A), clk_src_regs 481 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c clk_src_regs(1, B), clk_src_regs 482 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c clk_src_regs(2, C), clk_src_regs 483 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c clk_src_regs(3, D) clk_src_regs 1326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &clk_src_regs[0], false); clk_src_regs 1330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &clk_src_regs[1], false); clk_src_regs 1334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &clk_src_regs[2], false); clk_src_regs 1340 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &clk_src_regs[3], false); clk_src_regs 1352 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &clk_src_regs[0], true); clk_src_regs 475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dce110_clk_src_regs clk_src_regs[] = { clk_src_regs 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c clk_src_regs(0, A), clk_src_regs 477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c clk_src_regs(1, B), clk_src_regs 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c clk_src_regs(2, C), clk_src_regs 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c clk_src_regs(3, D), clk_src_regs 480 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c clk_src_regs(4, E), clk_src_regs 481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c clk_src_regs(5, F) clk_src_regs 3496 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &clk_src_regs[0], false); clk_src_regs 3500 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &clk_src_regs[1], false); clk_src_regs 3504 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &clk_src_regs[2], false); clk_src_regs 3508 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &clk_src_regs[3], false); clk_src_regs 3512 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &clk_src_regs[4], false); clk_src_regs 3516 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &clk_src_regs[5], false); clk_src_regs 3522 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &clk_src_regs[0], true); clk_src_regs 333 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dce110_clk_src_regs clk_src_regs[] = { clk_src_regs 334 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c clk_src_regs(0, A), clk_src_regs 335 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c clk_src_regs(1, B), clk_src_regs 336 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c clk_src_regs(2, C), clk_src_regs 337 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c clk_src_regs(3, D), clk_src_regs 338 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c clk_src_regs(4, E), clk_src_regs 1492 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c &clk_src_regs[0], false); clk_src_regs 1496 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c &clk_src_regs[1], false); clk_src_regs 1500 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c &clk_src_regs[2], false); clk_src_regs 1508 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c &clk_src_regs[0], true);