clk_set_phase 2643 drivers/clk/clk.c EXPORT_SYMBOL_GPL(clk_set_phase); clk_set_phase 564 drivers/gpu/drm/sun4i/sun4i_tcon.c clk_set_phase(tcon->dclk, 240); clk_set_phase 567 drivers/gpu/drm/sun4i/sun4i_tcon.c clk_set_phase(tcon->dclk, 0); clk_set_phase 61 drivers/mmc/host/dw_mmc-hi3798cv200.c clk_set_phase(priv->drive_clk, 180); clk_set_phase 63 drivers/mmc/host/dw_mmc-hi3798cv200.c clk_set_phase(priv->drive_clk, 135); clk_set_phase 78 drivers/mmc/host/dw_mmc-hi3798cv200.c clk_set_phase(priv->sample_clk, degrees[i]); clk_set_phase 115 drivers/mmc/host/dw_mmc-hi3798cv200.c clk_set_phase(priv->sample_clk, degrees[i]); clk_set_phase 65 drivers/mmc/host/dw_mmc-rockchip.c clk_set_phase(priv->sample_clk, priv->default_sample_phase); clk_set_phase 128 drivers/mmc/host/dw_mmc-rockchip.c clk_set_phase(priv->drv_clk, phase); clk_set_phase 165 drivers/mmc/host/dw_mmc-rockchip.c clk_set_phase(priv->sample_clk, clk_set_phase 212 drivers/mmc/host/dw_mmc-rockchip.c clk_set_phase(priv->sample_clk, priv->default_sample_phase); clk_set_phase 252 drivers/mmc/host/dw_mmc-rockchip.c clk_set_phase(priv->sample_clk, clk_set_phase 749 drivers/mmc/host/sunxi-mmc.c clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); clk_set_phase 750 drivers/mmc/host/sunxi-mmc.c clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); clk_set_phase 257 drivers/mtd/nand/raw/mxic_nand.c ret = clk_set_phase(nfc->send_dly_clk, 9 * freq / 25000000); clk_set_phase 243 drivers/spi/spi-mxic.c ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000); clk_set_phase 130 include/linux/clk.h int clk_set_phase(struct clk *clk, int degrees); clk_set_phase 173 include/trace/events/clk.h DEFINE_EVENT(clk_phase, clk_set_phase, clk_set_phase 103 sound/soc/meson/axg-tdm-formatter.c ret = clk_set_phase(formatter->sclk, invert ? 180 : 0); clk_set_phase 241 sound/soc/meson/axg-tdm-interface.c ret = clk_set_phase(iface->lrclk, clk_set_phase 281 sound/soc/meson/axg-tdm-interface.c ret = clk_set_phase(iface->sclk,