clk_register_divider  239 arch/powerpc/platforms/512x/clock-commonclk.c 	return clk_register_divider(NULL, name, parent_name, clkflags,
clk_register_divider  543 drivers/clk/clk-divider.c EXPORT_SYMBOL_GPL(clk_register_divider);
clk_register_divider   73 drivers/clk/clk-tango4.c 	pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0,
clk_register_divider  561 drivers/clk/davinci/pll.c 	return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV,
clk_register_divider  234 drivers/clk/imx/clk.h 	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
clk_register_divider  251 drivers/clk/imx/clk.h 	return clk_register_divider(NULL, name, parent, flags,
clk_register_divider  276 drivers/clk/imx/clk.h 	return clk_register_divider(NULL, name, parent,
clk_register_divider  282 drivers/clk/keystone/pll.c 	clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift,
clk_register_divider 1114 drivers/clk/mediatek/clk-mt8173.c 	clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
clk_register_divider  275 drivers/clk/mediatek/clk-mtk.c 		clk = clk_register_divider(NULL, mcd->name, mcd->parent_name,
clk_register_divider  192 drivers/clk/microchip/clk-pic32mzda.c 	clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk",
clk_register_divider  335 drivers/clk/mmp/clk-mmp2.c 	clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
clk_register_divider  366 drivers/clk/mmp/clk-mmp2.c 	clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
clk_register_divider  375 drivers/clk/mmp/clk-mmp2.c 	clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
clk_register_divider  389 drivers/clk/mmp/clk-mmp2.c 	clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
clk_register_divider  408 drivers/clk/mmp/clk-mmp2.c 	clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
clk_register_divider  421 drivers/clk/mmp/clk-mmp2.c 	clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
clk_register_divider  436 drivers/clk/mmp/clk-mmp2.c 	clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
clk_register_divider  449 drivers/clk/mmp/clk-mmp2.c 	clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
clk_register_divider  348 drivers/clk/mmp/clk-pxa168.c 	clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
clk_register_divider  319 drivers/clk/mmp/clk-pxa910.c 	clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
clk_register_divider  160 drivers/clk/mmp/clk.c 		clk = clk_register_divider(NULL, clks[i].name,
clk_register_divider   99 drivers/clk/pistachio/clk.c 		clk = clk_register_divider(NULL, div[i].name, div[i].parent,
clk_register_divider   74 drivers/clk/renesas/clk-emev2.c 	clk = clk_register_divider(NULL, np->name, parent_name, 0,
clk_register_divider  475 drivers/clk/rockchip/clk.c 				clk = clk_register_divider(NULL, list->name,
clk_register_divider 1644 drivers/clk/sirf/clk-atlas7.c 		clk = clk_register_divider(NULL, div->div_name,
clk_register_divider  431 drivers/clk/spear/spear3xx_clock.c 	clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
clk_register_divider  565 drivers/clk/spear/spear3xx_clock.c 	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
clk_register_divider  157 drivers/clk/spear/spear6xx_clock.c 	clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
clk_register_divider  284 drivers/clk/spear/spear6xx_clock.c 	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
clk_register_divider   62 drivers/clk/sunxi/clk-a10-pll2.c 	prediv_clk = clk_register_divider(NULL, "pll2-prediv",
clk_register_divider   37 drivers/clk/sunxi/clk-sun8i-apb0.c 	clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
clk_register_divider  117 drivers/clk/tegra/clk-tegra-super-gen4.c 			clk = clk_register_divider(NULL, "sclk", "sclk_mux",
clk_register_divider  141 drivers/clk/tegra/clk-tegra-super-gen4.c 		clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
clk_register_divider  156 drivers/clk/tegra/clk-tegra-super-gen4.c 	clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
clk_register_divider  852 drivers/clk/tegra/clk-tegra20.c 	clk_register_divider(NULL, "dev1_osc_div", "clk_m",
clk_register_divider  858 drivers/clk/tegra/clk-tegra20.c 	clk_register_divider(NULL, "dev2_osc_div", "clk_m",
clk_register_divider  265 drivers/clk/ti/adpll.c 	clock = clk_register_divider(d->dev, child_name, parent_name, 0,
clk_register_divider  207 drivers/clk/zte/clk-zx296702.c 	return clk_register_divider(NULL, name, parent, 0,
clk_register_divider  138 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, div0_name, mux_name,
clk_register_divider  142 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, div1_name, div0_name,
clk_register_divider  195 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
clk_register_divider  283 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
clk_register_divider  327 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
clk_register_divider  333 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
clk_register_divider  340 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
clk_register_divider  343 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
clk_register_divider  391 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
clk_register_divider  394 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
clk_register_divider  416 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
clk_register_divider  419 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
clk_register_divider  448 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
clk_register_divider  451 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "can_div1", "can_div0",
clk_register_divider  488 drivers/clk/zynq/clkc.c 	clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
clk_register_divider  305 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
clk_register_divider  533 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	clks[num++] = clk_register_divider(dev, clk_name,
clk_register_divider  548 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 			clk_register_divider(dev, clk_name,
clk_register_divider  464 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c 			clk_register_divider(dev, clk_name,
clk_register_divider  486 include/linux/clk-provider.h struct clk *clk_register_divider(struct device *dev, const char *name,
clk_register_divider  712 sound/soc/mxs/mxs-saif.c 	clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk",
clk_register_divider 1307 sound/soc/samsung/i2s.c 		priv->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev,