clk_pwm 109 arch/arm/mach-ep93xx/clock.c static struct clk clk_pwm = { clk_pwm 227 arch/arm/mach-ep93xx/clock.c INIT_CK(NULL, "pwm_clk", &clk_pwm), clk_pwm 20 drivers/clk/clk-pwm.c static inline struct clk_pwm *to_clk_pwm(struct clk_hw *hw) clk_pwm 22 drivers/clk/clk-pwm.c return container_of(hw, struct clk_pwm, hw); clk_pwm 27 drivers/clk/clk-pwm.c struct clk_pwm *clk_pwm = to_clk_pwm(hw); clk_pwm 29 drivers/clk/clk-pwm.c return pwm_enable(clk_pwm->pwm); clk_pwm 34 drivers/clk/clk-pwm.c struct clk_pwm *clk_pwm = to_clk_pwm(hw); clk_pwm 36 drivers/clk/clk-pwm.c pwm_disable(clk_pwm->pwm); clk_pwm 42 drivers/clk/clk-pwm.c struct clk_pwm *clk_pwm = to_clk_pwm(hw); clk_pwm 44 drivers/clk/clk-pwm.c return clk_pwm->fixed_rate; clk_pwm 49 drivers/clk/clk-pwm.c struct clk_pwm *clk_pwm = to_clk_pwm(hw); clk_pwm 52 drivers/clk/clk-pwm.c pwm_get_state(clk_pwm->pwm, &state); clk_pwm 71 drivers/clk/clk-pwm.c struct clk_pwm *clk_pwm; clk_pwm 77 drivers/clk/clk-pwm.c clk_pwm = devm_kzalloc(&pdev->dev, sizeof(*clk_pwm), GFP_KERNEL); clk_pwm 78 drivers/clk/clk-pwm.c if (!clk_pwm) clk_pwm 91 drivers/clk/clk-pwm.c if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate)) clk_pwm 92 drivers/clk/clk-pwm.c clk_pwm->fixed_rate = NSEC_PER_SEC / pargs.period; clk_pwm 94 drivers/clk/clk-pwm.c if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate && clk_pwm 95 drivers/clk/clk-pwm.c pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) { clk_pwm 118 drivers/clk/clk-pwm.c clk_pwm->pwm = pwm; clk_pwm 119 drivers/clk/clk-pwm.c clk_pwm->hw.init = &init; clk_pwm 120 drivers/clk/clk-pwm.c ret = devm_clk_hw_register(&pdev->dev, &clk_pwm->hw); clk_pwm 124 drivers/clk/clk-pwm.c return of_clk_add_hw_provider(node, of_clk_hw_simple_get, &clk_pwm->hw); clk_pwm 214 drivers/pwm/pwm-sprd.c struct clk *clk_pwm; clk_pwm 238 drivers/pwm/pwm-sprd.c clk_pwm = chn->clks[SPRD_PWM_CHN_OUTPUT_CLK].clk; clk_pwm 239 drivers/pwm/pwm-sprd.c chn->clk_rate = clk_get_rate(clk_pwm);