clk_mgt           469 drivers/mfd/db8500-prcmu.c static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
clk_mgt          1331 drivers/mfd/db8500-prcmu.c 	val = readl(prcmu_base + clk_mgt[clock].offset);
clk_mgt          1333 drivers/mfd/db8500-prcmu.c 		val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
clk_mgt          1335 drivers/mfd/db8500-prcmu.c 		clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
clk_mgt          1338 drivers/mfd/db8500-prcmu.c 	writel(val, prcmu_base + clk_mgt[clock].offset);
clk_mgt          1514 drivers/mfd/db8500-prcmu.c 	val = readl(prcmu_base + clk_mgt[clock].offset);
clk_mgt          1517 drivers/mfd/db8500-prcmu.c 		if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
clk_mgt          1522 drivers/mfd/db8500-prcmu.c 	val |= clk_mgt[clock].pllsw;
clk_mgt          1526 drivers/mfd/db8500-prcmu.c 		rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
clk_mgt          1528 drivers/mfd/db8500-prcmu.c 		rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
clk_mgt          1530 drivers/mfd/db8500-prcmu.c 		rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
clk_mgt          1674 drivers/mfd/db8500-prcmu.c 	val = readl(prcmu_base + clk_mgt[clock].offset);
clk_mgt          1675 drivers/mfd/db8500-prcmu.c 	src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
clk_mgt          1676 drivers/mfd/db8500-prcmu.c 		clk_mgt[clock].branch);
clk_mgt          1679 drivers/mfd/db8500-prcmu.c 		if (clk_mgt[clock].clk38div) {
clk_mgt          1836 drivers/mfd/db8500-prcmu.c 	val = readl(prcmu_base + clk_mgt[clock].offset);
clk_mgt          1837 drivers/mfd/db8500-prcmu.c 	src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
clk_mgt          1838 drivers/mfd/db8500-prcmu.c 		clk_mgt[clock].branch);
clk_mgt          1841 drivers/mfd/db8500-prcmu.c 		if (clk_mgt[clock].clk38div) {
clk_mgt          1864 drivers/mfd/db8500-prcmu.c 	writel(val, prcmu_base + clk_mgt[clock].offset);