clk_mgr 69 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) clk_mgr 73 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); clk_mgr 75 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c if (clk_mgr == NULL) { clk_mgr 83 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c dce_clk_mgr_construct(ctx, clk_mgr); clk_mgr 86 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c dce110_clk_mgr_construct(ctx, clk_mgr); clk_mgr 91 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c dce_clk_mgr_construct(ctx, clk_mgr); clk_mgr 97 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c dce112_clk_mgr_construct(ctx, clk_mgr); clk_mgr 101 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c dce112_clk_mgr_construct(ctx, clk_mgr); clk_mgr 107 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c dce121_clk_mgr_construct(ctx, clk_mgr); clk_mgr 109 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c dce120_clk_mgr_construct(ctx, clk_mgr); clk_mgr 116 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); clk_mgr 121 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); clk_mgr 126 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); clk_mgr 134 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); clk_mgr 143 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c return &clk_mgr->base; clk_mgr 146 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) clk_mgr 148 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 150 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c kfree(clk_mgr); clk_mgr 47 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c (clk_mgr->regs->reg) clk_mgr 51 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name clk_mgr 129 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) clk_mgr 131 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 150 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c * clk_mgr->dentist_vco_freq_khz) / target_div; clk_mgr 152 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); clk_mgr 155 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) clk_mgr 195 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct clk_mgr *clk_mgr_base, clk_mgr 230 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct clk_mgr *clk_mgr_base, clk_mgr 395 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c static void dce_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr 436 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct clk_mgr_internal *clk_mgr) clk_mgr 438 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct clk_mgr *base = &clk_mgr->base; clk_mgr 441 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c memcpy(clk_mgr->max_clks_by_state, clk_mgr 448 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr->regs = &disp_clk_regs; clk_mgr 449 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr->clk_mgr_shift = &disp_clk_shift; clk_mgr 450 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr->clk_mgr_mask = &disp_clk_mask; clk_mgr 451 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr->dfs_bypass_disp_clk = 0; clk_mgr 453 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr->dprefclk_ss_percentage = 0; clk_mgr 454 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr->dprefclk_ss_divider = 1000; clk_mgr 455 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr->ss_on_dprefclk = false; clk_mgr 458 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr->max_clks_state = static_clk_info.max_clocks_state; clk_mgr 460 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; clk_mgr 461 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; clk_mgr 463 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c dce_clock_read_integrated_info(clk_mgr); clk_mgr 464 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c dce_clock_read_ss_info(clk_mgr); clk_mgr 34 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base); clk_mgr 36 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h struct clk_mgr *clk_mgr_base, clk_mgr 48 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg); clk_mgr 51 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h struct clk_mgr *clk_mgr_base, clk_mgr 55 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr); clk_mgr 230 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; clk_mgr 248 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr 282 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c struct clk_mgr_internal *clk_mgr) clk_mgr 284 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c dce_clk_mgr_construct(ctx, clk_mgr); clk_mgr 286 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c memcpy(clk_mgr->max_clks_by_state, clk_mgr 290 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c clk_mgr->regs = &disp_clk_regs; clk_mgr 291 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c clk_mgr->clk_mgr_shift = &disp_clk_shift; clk_mgr 292 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c clk_mgr->clk_mgr_mask = &disp_clk_mask; clk_mgr 293 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c clk_mgr->base.funcs = &dce110_funcs; clk_mgr 31 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h struct clk_mgr_internal *clk_mgr); clk_mgr 70 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) clk_mgr 125 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz) clk_mgr 128 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; clk_mgr 129 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c struct dc *core_dc = clk_mgr->base.ctx->dc; clk_mgr 138 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr->dentist_vco_freq_khz / 62); clk_mgr 152 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; clk_mgr 157 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c if (clk_mgr->dfs_bypass_disp_clk != actual_clock) clk_mgr 163 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr->dfs_bypass_disp_clk = actual_clock; clk_mgr 168 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr) clk_mgr 171 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; clk_mgr 180 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c if (!ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev)) clk_mgr 193 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr 227 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c struct clk_mgr_internal *clk_mgr) clk_mgr 229 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c dce_clk_mgr_construct(ctx, clk_mgr); clk_mgr 231 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c memcpy(clk_mgr->max_clks_by_state, clk_mgr 235 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr->regs = &disp_clk_regs; clk_mgr 236 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr->clk_mgr_shift = &disp_clk_shift; clk_mgr 237 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr->clk_mgr_mask = &disp_clk_mask; clk_mgr 238 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr->base.funcs = &dce112_funcs; clk_mgr 32 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h struct clk_mgr_internal *clk_mgr); clk_mgr 35 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz); clk_mgr 36 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz); clk_mgr 37 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr); clk_mgr 84 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr 128 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) clk_mgr 130 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c dce_clk_mgr_construct(ctx, clk_mgr); clk_mgr 132 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c memcpy(clk_mgr->max_clks_by_state, clk_mgr 136 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr->base.dprefclk_khz = 600000; clk_mgr 137 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr->base.funcs = &dce120_funcs; clk_mgr 140 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) clk_mgr 142 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c dce120_clk_mgr_construct(ctx, clk_mgr); clk_mgr 143 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr->base.dprefclk_khz = 625000; clk_mgr 150 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c dce121_clock_patch_xgmi_ss_info(clk_mgr); clk_mgr 29 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.h void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr); clk_mgr 30 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.h void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr); clk_mgr 37 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c void rv1_init_clocks(struct clk_mgr *clk_mgr) clk_mgr 39 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); clk_mgr 42 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) clk_mgr 45 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; clk_mgr 47 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; clk_mgr 77 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) clk_mgr 88 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c static void ramp_up_dispclk_with_dpp(struct clk_mgr_internal *clk_mgr, struct dc *dc, struct dc_clocks *new_clocks) clk_mgr 91 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks); clk_mgr 96 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->funcs->set_dispclk(clk_mgr, dispclk_to_dpp_threshold); clk_mgr 97 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->funcs->set_dprefclk(clk_mgr); clk_mgr 115 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->funcs->set_dispclk(clk_mgr, new_clocks->dispclk_khz); clk_mgr 116 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->funcs->set_dprefclk(clk_mgr); clk_mgr 120 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz; clk_mgr 121 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; clk_mgr 122 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; clk_mgr 125 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr 129 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 140 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c ASSERT(clk_mgr->pp_smu); clk_mgr 142 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu = &clk_mgr->pp_smu->rv_funcs; clk_mgr 209 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks); clk_mgr 226 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base) clk_mgr 228 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 231 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (clk_mgr->pp_smu) { clk_mgr 232 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu = &clk_mgr->pp_smu->rv_funcs; clk_mgr 251 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) clk_mgr 256 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.ctx = ctx; clk_mgr 257 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->pp_smu = pp_smu; clk_mgr 258 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.funcs = &rv1_clk_funcs; clk_mgr 259 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->funcs = &rv1_clk_internal_funcs; clk_mgr 261 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->dfs_bypass_disp_clk = 0; clk_mgr 263 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->dprefclk_ss_percentage = 0; clk_mgr 264 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->dprefclk_ss_divider = 1000; clk_mgr 265 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->ss_on_dprefclk = false; clk_mgr 266 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.dprefclk_khz = 600000; clk_mgr 269 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq; clk_mgr 270 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) { clk_mgr 271 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq; clk_mgr 272 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (clk_mgr->dentist_vco_freq_khz == 0) clk_mgr 273 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->dentist_vco_freq_khz = 3600000; clk_mgr 278 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->dfs_bypass_enabled = true; clk_mgr 280 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c dce_clock_read_ss_info(clk_mgr); clk_mgr 29 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.h void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu); clk_mgr 52 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk_mgr *clk_mgr_base) clk_mgr 54 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 71 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param) clk_mgr 88 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) clk_mgr 91 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c struct dc *core_dc = clk_mgr->base.ctx->dc; clk_mgr 96 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 105 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) clk_mgr 114 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) clk_mgr 119 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 121 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c clk_mgr->base.dprefclk_khz / 1000); clk_mgr 29 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); clk_mgr 30 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); clk_mgr 37 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) clk_mgr 40 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); clk_mgr 42 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c clk_mgr->funcs = &rv2_clk_internal_funcs; clk_mgr 29 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.h void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu); clk_mgr 42 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name clk_mgr 45 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c (clk_mgr->regs->reg) clk_mgr 102 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, clk_mgr 107 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { clk_mgr 115 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg->funcs->update_dpp_dto( clk_mgr 116 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg, dpp_inst, dppclk_khz, false); clk_mgr 120 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c static void update_global_dpp_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz) clk_mgr 123 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c * clk_mgr->dentist_vco_freq_khz / khz; clk_mgr 132 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c static void update_display_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz) clk_mgr 135 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c * clk_mgr->dentist_vco_freq_khz / khz; clk_mgr 143 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c static void request_voltage_and_program_disp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz) clk_mgr 145 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 148 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c bool going_up = clk_mgr->base.clks.dispclk_khz < khz; clk_mgr 153 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.clks.dispclk_khz = khz; clk_mgr 158 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c update_display_clk(clk_mgr, khz); clk_mgr 164 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c static void request_voltage_and_program_global_dpp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz) clk_mgr 166 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 169 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c bool going_up = clk_mgr->base.clks.dppclk_khz < khz; clk_mgr 174 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.clks.dppclk_khz = khz; clk_mgr 175 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg->ref_dppclk = khz; clk_mgr 180 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c update_global_dpp_clk(clk_mgr, khz); clk_mgr 186 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr 190 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 281 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { clk_mgr 290 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, true); clk_mgr 298 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { clk_mgr 307 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, false); clk_mgr 319 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, clk_mgr 323 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); clk_mgr 329 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { clk_mgr 330 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; clk_mgr 333 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) { clk_mgr 334 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; clk_mgr 338 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) { clk_mgr 339 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; clk_mgr 342 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) { clk_mgr 343 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; clk_mgr 346 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { clk_mgr 347 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; clk_mgr 350 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) { clk_mgr 351 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; clk_mgr 354 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { clk_mgr 355 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.fclk_khz = fclk_adj; clk_mgr 358 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { clk_mgr 359 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; clk_mgr 366 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) clk_mgr 367 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; clk_mgr 368 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) clk_mgr 369 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; clk_mgr 372 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; clk_mgr 374 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); clk_mgr 377 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c void dcn2_init_clocks(struct clk_mgr *clk_mgr) clk_mgr 379 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); clk_mgr 381 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.p_state_change_support = true; clk_mgr 382 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clks.prev_p_state_change_support = true; clk_mgr 385 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) clk_mgr 387 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 390 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (clk_mgr->pp_smu) { clk_mgr 391 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu = &clk_mgr->pp_smu->nv_funcs; clk_mgr 398 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c void dcn2_get_clock(struct clk_mgr *clk_mgr, clk_mgr 407 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; clk_mgr 413 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz; clk_mgr 429 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct clk_mgr_internal *clk_mgr, clk_mgr 433 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.ctx = ctx; clk_mgr 434 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->pp_smu = pp_smu; clk_mgr 435 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.funcs = &dcn2_funcs; clk_mgr 436 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->regs = &clk_mgr_regs; clk_mgr 437 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clk_mgr_shift = &clk_mgr_shift; clk_mgr 438 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->clk_mgr_mask = &clk_mgr_mask; clk_mgr 440 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dccg = dccg; clk_mgr 441 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dfs_bypass_disp_clk = 0; clk_mgr 443 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dprefclk_ss_percentage = 0; clk_mgr 444 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dprefclk_ss_divider = 1000; clk_mgr 445 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->ss_on_dprefclk = false; clk_mgr 447 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved clk_mgr 451 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dentist_vco_freq_khz = 3850000; clk_mgr 468 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); clk_mgr 469 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; clk_mgr 475 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req); clk_mgr 478 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (clk_mgr->dentist_vco_freq_khz == 0) clk_mgr 479 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dentist_vco_freq_khz = 3850000; clk_mgr 482 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR clk_mgr 483 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c * clk_mgr->dentist_vco_freq_khz) / target_div; clk_mgr 488 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->dfs_bypass_enabled = false; clk_mgr 490 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c dce_clock_read_ss_info(clk_mgr); clk_mgr 29 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h void dcn2_update_clocks(struct clk_mgr *dccg, clk_mgr 33 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, clk_mgr 36 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, clk_mgr 39 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h void dcn2_init_clocks(struct clk_mgr *clk_mgr); clk_mgr 42 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h struct clk_mgr_internal *clk_mgr, clk_mgr 48 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h void dcn2_get_clock(struct clk_mgr *clk_mgr, clk_mgr 55 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c void rn_update_clocks(struct clk_mgr *clk_mgr_base, clk_mgr 59 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 75 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_vbios_smu_set_display_count(clk_mgr, display_count); clk_mgr 80 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz); clk_mgr 85 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); clk_mgr 91 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); clk_mgr 100 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { clk_mgr 101 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) clk_mgr 109 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); clk_mgr 116 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c dcn20_update_clocks_update_dpp_dto(clk_mgr, context); clk_mgr 117 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); clk_mgr 121 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); clk_mgr 123 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c dcn20_update_clocks_update_dpp_dto(clk_mgr, context); clk_mgr 135 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) clk_mgr 160 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); clk_mgr 166 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base) clk_mgr 168 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 188 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) clk_mgr 321 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s) clk_mgr 331 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base) clk_mgr 333 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); clk_mgr 335 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_vbios_smu_enable_pme_wa(clk_mgr); clk_mgr 518 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c struct clk_mgr_internal *clk_mgr, clk_mgr 526 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.ctx = ctx; clk_mgr 527 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.funcs = &dcn21_funcs; clk_mgr 529 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->pp_smu = pp_smu; clk_mgr 531 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->dccg = dccg; clk_mgr 532 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->dfs_bypass_disp_clk = 0; clk_mgr 534 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->dprefclk_ss_percentage = 0; clk_mgr 535 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->dprefclk_ss_divider = 1000; clk_mgr 536 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->ss_on_dprefclk = false; clk_mgr 537 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->dfs_ref_freq_khz = 48000; clk_mgr 539 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr); clk_mgr 543 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->dentist_vco_freq_khz = 3600000; clk_mgr 544 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.dprefclk_khz = 600000; clk_mgr 549 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr); clk_mgr 552 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (clk_mgr->dentist_vco_freq_khz == 0) clk_mgr 553 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->dentist_vco_freq_khz = 3600000; clk_mgr 555 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_dump_clk_registers(&s, &clk_mgr->base, &log_info); clk_mgr 556 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.dprefclk_khz = s.dprefclk; clk_mgr 558 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (clk_mgr->base.dprefclk_khz != 600000) { clk_mgr 559 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.dprefclk_khz = 600000; clk_mgr 564 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (clk_mgr->base.dprefclk_khz == 0) clk_mgr 565 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.dprefclk_khz = 600000; clk_mgr 568 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c dce_clock_read_ss_info(clk_mgr); clk_mgr 570 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.bw_params = &rn_bw_params; clk_mgr 574 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id); clk_mgr 585 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c build_watermark_ranges(clk_mgr->base.bw_params, &ranges); clk_mgr 594 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr); clk_mgr 35 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h struct clk_mgr_internal *clk_mgr, clk_mgr 56 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param) clk_mgr 73 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) clk_mgr 76 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 82 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) clk_mgr 85 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c struct dc *core_dc = clk_mgr->base.ctx->dc; clk_mgr 94 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 100 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) clk_mgr 109 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) clk_mgr 114 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 116 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr->base.dprefclk_khz / 1000); clk_mgr 123 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) clk_mgr 127 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c if (clk_mgr->smu_ver < 0xFFFFFFFF) clk_mgr 131 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 138 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) clk_mgr 142 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c if (clk_mgr->smu_ver < 0xFFFFFFFF) clk_mgr 146 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 153 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz) clk_mgr 156 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 161 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) clk_mgr 171 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 178 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c void rn_vbios_smu_set_display_count(struct clk_mgr_internal *clk_mgr, int display_count) clk_mgr 181 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 186 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr) clk_mgr 189 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 194 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) clk_mgr 197 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr, clk_mgr 29 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr); clk_mgr 30 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); clk_mgr 31 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); clk_mgr 32 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); clk_mgr 33 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz); clk_mgr 34 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz); clk_mgr 35 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); clk_mgr 36 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h void rn_vbios_smu_set_display_count(struct clk_mgr_internal *clk_mgr, int display_count); clk_mgr 37 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr); clk_mgr 38 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); clk_mgr 529 drivers/gpu/drm/amd/display/dc/core/dc.c if (dc->clk_mgr) { clk_mgr 530 drivers/gpu/drm/amd/display/dc/core/dc.c dc_destroy_clk_mgr(dc->clk_mgr); clk_mgr 531 drivers/gpu/drm/amd/display/dc/core/dc.c dc->clk_mgr = NULL; clk_mgr 694 drivers/gpu/drm/amd/display/dc/core/dc.c dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); clk_mgr 695 drivers/gpu/drm/amd/display/dc/core/dc.c if (!dc->clk_mgr) clk_mgr 700 drivers/gpu/drm/amd/display/dc/core/dc.c dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); clk_mgr 1658 drivers/gpu/drm/amd/display/dc/core/dc.c if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) clk_mgr 1495 drivers/gpu/drm/amd/display/dc/core/dc_link.c state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false); clk_mgr 2022 drivers/gpu/drm/amd/display/dc/core/dc_resource.c dst_ctx->clk_mgr = dc->clk_mgr; clk_mgr 479 drivers/gpu/drm/amd/display/dc/dc.h struct clk_mgr *clk_mgr; clk_mgr 48 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr->ctx->logger clk_mgr 148 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) clk_mgr 150 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr 174 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) clk_mgr 176 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr 214 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct clk_mgr *clk_mgr, clk_mgr 217 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr 247 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct clk_mgr *clk_mgr, clk_mgr 250 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr 252 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dc_bios *bp = clk_mgr->ctx->dc_bios; clk_mgr 288 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c int dce112_set_clock(struct clk_mgr *clk_mgr, int requested_clk_khz) clk_mgr 290 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr 292 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dc_bios *bp = clk_mgr->ctx->dc_bios; clk_mgr 293 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dc *core_dc = clk_mgr->ctx->dc; clk_mgr 320 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (!ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev)) clk_mgr 464 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c void dce121_clock_patch_xgmi_ss_info(struct clk_mgr *clk_mgr) clk_mgr 466 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr 650 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz; clk_mgr 668 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c static void dce_update_clocks(struct clk_mgr *clk_mgr, clk_mgr 672 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr 680 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context); clk_mgr 684 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req)) clk_mgr 688 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { clk_mgr 689 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c patched_disp_clk = dce_set_clock(clk_mgr, patched_disp_clk); clk_mgr 690 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr->clks.dispclk_khz = patched_disp_clk; clk_mgr 692 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dce_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); clk_mgr 695 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c static void dce11_update_clocks(struct clk_mgr *clk_mgr, clk_mgr 699 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr 707 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context); clk_mgr 711 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req)) clk_mgr 715 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { clk_mgr 716 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr, patched_disp_clk); clk_mgr 717 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr->clks.dispclk_khz = patched_disp_clk; clk_mgr 719 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); clk_mgr 722 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c static void dce112_update_clocks(struct clk_mgr *clk_mgr, clk_mgr 726 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr 734 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context); clk_mgr 738 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req)) clk_mgr 742 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { clk_mgr 743 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c patched_disp_clk = dce112_set_clock(clk_mgr, patched_disp_clk); clk_mgr 744 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr->clks.dispclk_khz = patched_disp_clk; clk_mgr 746 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); clk_mgr 749 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c static void dce12_update_clocks(struct clk_mgr *clk_mgr, clk_mgr 753 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); clk_mgr 762 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { clk_mgr 772 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr->clks.dispclk_khz = dce112_set_clock(clk_mgr, patched_disp_clk); clk_mgr 774 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req); clk_mgr 777 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) { clk_mgr 780 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr->clks.phyclk_khz = max_pix_clk; clk_mgr 782 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req); clk_mgr 784 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); clk_mgr 814 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct clk_mgr *base = &clk_mgr_dce->base; clk_mgr 841 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct clk_mgr *dce_clk_mgr_create( clk_mgr 864 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct clk_mgr *dce110_clk_mgr_create( clk_mgr 889 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct clk_mgr *dce112_clk_mgr_create( clk_mgr 914 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx) clk_mgr 936 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct clk_mgr *dce121_clk_mgr_create(struct dc_context *ctx) clk_mgr 957 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr) clk_mgr 959 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(*clk_mgr); clk_mgr 962 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c *clk_mgr = NULL; clk_mgr 115 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c dc->clk_mgr->funcs->update_clocks( clk_mgr 116 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c dc->clk_mgr, clk_mgr 127 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c dc->clk_mgr->funcs->update_clocks( clk_mgr 128 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c dc->clk_mgr, clk_mgr 948 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct clk_mgr *clk_mgr; clk_mgr 955 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c clk_mgr = core_dc->clk_mgr; clk_mgr 972 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) clk_mgr 974 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c clk_mgr->funcs->enable_pme_wa(clk_mgr); clk_mgr 988 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct clk_mgr *clk_mgr; clk_mgr 994 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c clk_mgr = dc->clk_mgr; clk_mgr 1014 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (clk_mgr->funcs->enable_pme_wa) clk_mgr 1016 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c clk_mgr->funcs->enable_pme_wa(clk_mgr); clk_mgr 1175 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c state->clk_mgr->funcs->get_dp_ref_clk_frequency( clk_mgr 1176 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c state->clk_mgr); clk_mgr 2439 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct clk_mgr *dccg = dc->clk_mgr; clk_mgr 2453 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct clk_mgr *dccg = dc->clk_mgr; clk_mgr 1184 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) clk_mgr 1185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); clk_mgr 2296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr->clks.dispclk_khz / 2; clk_mgr 2310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ? clk_mgr 2311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr->clks.dispclk_khz / 2 : clk_mgr 2312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr->clks.dispclk_khz; clk_mgr 2698 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr->funcs->update_clocks( clk_mgr 2699 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr, clk_mgr 2730 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr->funcs->update_clocks( clk_mgr 2731 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr, clk_mgr 3267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock) clk_mgr 3268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr->funcs->get_clock(dc->clk_mgr, clk_mgr 3271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!dc->clk_mgr->funcs->get_clock) clk_mgr 3291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks) clk_mgr 3292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, clk_mgr 3304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock) clk_mgr 3305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg); clk_mgr 581 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true && clk_mgr 582 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false) clk_mgr 1278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->clk_mgr->funcs->update_clocks( clk_mgr 1279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->clk_mgr, clk_mgr 1302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->clk_mgr->funcs->update_clocks( clk_mgr 1303 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->clk_mgr, clk_mgr 2000 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) clk_mgr 2001 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); clk_mgr 989 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; clk_mgr 396 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct clk_mgr *clk_mgr; clk_mgr 170 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h void (*update_clocks)(struct clk_mgr *clk_mgr, clk_mgr 174 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr); clk_mgr 176 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h void (*init_clocks)(struct clk_mgr *clk_mgr); clk_mgr 178 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h void (*enable_pme_wa) (struct clk_mgr *clk_mgr); clk_mgr 179 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h void (*get_clock)(struct clk_mgr *clk_mgr, clk_mgr 198 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); clk_mgr 200 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr); clk_mgr 69 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h #define TO_CLK_MGR_INTERNAL(clk_mgr)\ clk_mgr 70 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h container_of(clk_mgr, struct clk_mgr_internal, base) clk_mgr 73 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h clk_mgr->base.ctx clk_mgr 75 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h clk_mgr->ctx->logger clk_mgr 193 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h struct clk_mgr base; clk_mgr 265 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); clk_mgr 266 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);