clk_mask 275 arch/ia64/kernel/asm-offsets.c offsetof (struct fsyscall_gtod_data_t, clk_mask)); clk_mask 19 arch/ia64/kernel/fsyscall_gtod_data.h u64 clk_mask; clk_mask 436 arch/ia64/kernel/time.c fsyscall_gtod_data.clk_mask = tk->tkr_mono.mask; clk_mask 83 drivers/clk/sunxi/clk-usb.c u32 clk_mask; clk_mask 110 drivers/clk/sunxi/clk-usb.c qty = find_last_bit((unsigned long *)&data->clk_mask, clk_mask 123 drivers/clk/sunxi/clk-usb.c for_each_set_bit(i, (unsigned long *)&data->clk_mask, clk_mask 166 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(8) | BIT(7) | BIT(6), clk_mask 179 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(8) | BIT(6), clk_mask 190 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8), clk_mask 201 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(16) | BIT(11) | BIT(10) | BIT(9) | BIT(8), clk_mask 212 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) | clk_mask 224 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1), clk_mask 238 drivers/clk/sunxi/clk-usb.c .clk_mask = BIT(10) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1), clk_mask 812 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c const struct clk_mgr_mask *clk_mask) clk_mask 822 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->clk_mgr_mask = clk_mask; clk_mask 845 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c const struct clk_mgr_mask *clk_mask) clk_mask 859 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce, ctx, regs, clk_shift, clk_mask); clk_mask 868 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c const struct clk_mgr_mask *clk_mask) clk_mask 882 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce, ctx, regs, clk_shift, clk_mask); clk_mask 893 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c const struct clk_mgr_mask *clk_mask) clk_mask 907 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce, ctx, regs, clk_shift, clk_mask); clk_mask 192 drivers/gpu/drm/msm/edp/edp_ctrl.c static int edp_clk_enable(struct edp_ctrl *ctrl, u32 clk_mask) clk_mask 196 drivers/gpu/drm/msm/edp/edp_ctrl.c DBG("mask=%x", clk_mask); clk_mask 198 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_AHB) { clk_mask 205 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_AUX) { clk_mask 218 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_LINK) { clk_mask 235 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_PIXEL) { clk_mask 252 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_MDP_CORE) { clk_mask 263 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_PIXEL) clk_mask 266 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_LINK) clk_mask 269 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_AUX) clk_mask 272 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_AHB) clk_mask 278 drivers/gpu/drm/msm/edp/edp_ctrl.c static void edp_clk_disable(struct edp_ctrl *ctrl, u32 clk_mask) clk_mask 280 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_MDP_CORE) clk_mask 282 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_PIXEL) clk_mask 284 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_LINK) clk_mask 286 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_AUX) clk_mask 288 drivers/gpu/drm/msm/edp/edp_ctrl.c if (clk_mask & EDP_CLK_MASK_AHB) clk_mask 446 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, mast, mastm, 0x00000000); clk_mask 447 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, divs, divsm, divsv); clk_mask 448 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, mast, mastm, mastv); clk_mask 454 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, mast, 0x001000b0, 0x00100080); clk_mask 456 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, mast, 0x000000b3, 0x00000081); clk_mask 463 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, nvpll[0], 0xc03f0100, clk_mask 465 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); clk_mask 474 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); clk_mask 475 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, mast, 0x00100033, 0x00000023); clk_mask 481 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, spll[0], 0xc03f0100, clk_mask 483 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); clk_mask 484 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk_mask(hwsq, mast, 0x00100033, 0x00000033); clk_mask 419 drivers/gpu/drm/radeon/radeon_combios.c u32 clk_mask, clk_mask 523 drivers/gpu/drm/radeon/radeon_combios.c if (clk_mask && data_mask) { clk_mask 525 drivers/gpu/drm/radeon/radeon_combios.c i2c.mask_clk_mask = clk_mask; clk_mask 527 drivers/gpu/drm/radeon/radeon_combios.c i2c.a_clk_mask = clk_mask; clk_mask 529 drivers/gpu/drm/radeon/radeon_combios.c i2c.en_clk_mask = clk_mask; clk_mask 531 drivers/gpu/drm/radeon/radeon_combios.c i2c.y_clk_mask = clk_mask; clk_mask 147 drivers/spi/spi-ti-qspi.c u32 clk_ctrl_reg, clk_rate, clk_mask; clk_mask 191 drivers/spi/spi-ti-qspi.c clk_mask = QSPI_CLK_EN | clk_div; clk_mask 192 drivers/spi/spi-ti-qspi.c ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); clk_mask 193 drivers/spi/spi-ti-qspi.c ctx_reg->clkctrl = clk_mask; clk_mask 128 include/linux/fs_enet_pd.h u32 clk_mask; clk_mask 77 sound/pci/ice1712/ak4xxx.c tmp &= ~priv->clk_mask; clk_mask 88 sound/pci/ice1712/ak4xxx.c tmp |= priv->clk_mask; clk_mask 447 sound/pci/ice1712/delta.c .clk_mask = ICE1712_DELTA_AP_CCLK, clk_mask 468 sound/pci/ice1712/delta.c .clk_mask = ICE1712_DELTA_AP_CCLK, clk_mask 490 sound/pci/ice1712/delta.c .clk_mask = ICE1712_DELTA_1010LT_CCLK, clk_mask 512 sound/pci/ice1712/delta.c .clk_mask = ICE1712_DELTA_66E_CCLK, clk_mask 535 sound/pci/ice1712/delta.c .clk_mask = ICE1712_DELTA_CODEC_SERIAL_CLOCK, clk_mask 557 sound/pci/ice1712/delta.c .clk_mask = ICE1712_VX442_CCLK, clk_mask 347 sound/pci/ice1712/ews.c .clk_mask = ICE1712_EWS88_SERIAL_CLOCK, clk_mask 368 sound/pci/ice1712/ews.c .clk_mask = ICE1712_EWS88_SERIAL_CLOCK, clk_mask 389 sound/pci/ice1712/ews.c .clk_mask = ICE1712_6FIRE_SERIAL_CLOCK, clk_mask 291 sound/pci/ice1712/hoontech.c .clk_mask = ICE1712_STDSP24_SERIAL_CLOCK, clk_mask 255 sound/pci/ice1712/ice1712.h unsigned int clk_mask; /* CLK gpio bit */ clk_mask 101 sound/pci/ice1712/phase.c .clk_mask = 1 << 5, clk_mask 237 sound/pci/ice1712/revo.c .clk_mask = VT1724_REVO_CCLK, clk_mask 259 sound/pci/ice1712/revo.c .clk_mask = VT1724_REVO_CCLK, clk_mask 280 sound/pci/ice1712/revo.c .clk_mask = VT1724_REVO_CCLK, clk_mask 298 sound/pci/ice1712/revo.c .clk_mask = VT1724_REVO_CCLK, clk_mask 348 sound/pci/ice1712/revo.c .clk_mask = VT1724_REVO_CCLK,