clk_bw_params     346 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c struct clk_bw_params rn_bw_params = {
clk_bw_params     414 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
clk_bw_params     471 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
clk_bw_params     989 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
clk_bw_params    1274 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
clk_bw_params      91 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct clk_bw_params;
clk_bw_params     151 drivers/gpu/drm/amd/display/dc/inc/core_types.h 			struct clk_bw_params *bw_params);
clk_bw_params     191 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 	struct clk_bw_params *bw_params;