CC_REG 17 drivers/crypto/ccree/cc_debugfs.c .offset = CC_REG(_X) \ CC_REG 54 drivers/crypto/ccree/cc_driver.c CC_REG(PERIPHERAL_ID_0), CC_REG(PERIPHERAL_ID_1), CC_REG 55 drivers/crypto/ccree/cc_driver.c CC_REG(PERIPHERAL_ID_2), CC_REG(PERIPHERAL_ID_4) CC_REG 59 drivers/crypto/ccree/cc_driver.c CC_REG(COMPONENT_ID_0), CC_REG(COMPONENT_ID_1), CC_REG 60 drivers/crypto/ccree/cc_driver.c CC_REG(COMPONENT_ID_2), CC_REG(COMPONENT_ID_3) CC_REG 141 drivers/crypto/ccree/cc_driver.c irr = cc_ioread(drvdata, CC_REG(HOST_IRR)); CC_REG 147 drivers/crypto/ccree/cc_driver.c imr = cc_ioread(drvdata, CC_REG(HOST_IMR)); CC_REG 150 drivers/crypto/ccree/cc_driver.c cc_iowrite(drvdata, CC_REG(HOST_ICR), irr); CC_REG 158 drivers/crypto/ccree/cc_driver.c cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | drvdata->comp_mask); CC_REG 168 drivers/crypto/ccree/cc_driver.c cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_GPR0_IRQ_MASK); CC_REG 178 drivers/crypto/ccree/cc_driver.c axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR)); CC_REG 207 drivers/crypto/ccree/cc_driver.c val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE)); CC_REG 227 drivers/crypto/ccree/cc_driver.c val = cc_ioread(drvdata, CC_REG(AXIM_CFG)); CC_REG 228 drivers/crypto/ccree/cc_driver.c cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK); CC_REG 230 drivers/crypto/ccree/cc_driver.c cc_ioread(drvdata, CC_REG(AXIM_CFG))); CC_REG 234 drivers/crypto/ccree/cc_driver.c val = cc_ioread(drvdata, CC_REG(HOST_IRR)); CC_REG 236 drivers/crypto/ccree/cc_driver.c cc_iowrite(drvdata, CC_REG(HOST_ICR), val); CC_REG 244 drivers/crypto/ccree/cc_driver.c cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val); CC_REG 248 drivers/crypto/ccree/cc_driver.c val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS)); CC_REG 253 drivers/crypto/ccree/cc_driver.c cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), cache_params); CC_REG 254 drivers/crypto/ccree/cc_driver.c val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS)); CC_REG 290 drivers/crypto/ccree/cc_driver.c new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP); CC_REG 291 drivers/crypto/ccree/cc_driver.c new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712); CC_REG 292 drivers/crypto/ccree/cc_driver.c new_drvdata->ver_offset = CC_REG(HOST_VERSION_712); CC_REG 294 drivers/crypto/ccree/cc_driver.c new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8); CC_REG 295 drivers/crypto/ccree/cc_driver.c new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630); CC_REG 296 drivers/crypto/ccree/cc_driver.c new_drvdata->ver_offset = CC_REG(HOST_VERSION_630); CC_REG 409 drivers/crypto/ccree/cc_driver.c val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS)); CC_REG 427 drivers/crypto/ccree/cc_driver.c val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED)); CC_REG 558 drivers/crypto/ccree/cc_driver.c cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF); CC_REG 26 drivers/crypto/ccree/cc_fips.c reg = cc_ioread(drvdata, CC_REG(GPR_HOST)); CC_REG 49 drivers/crypto/ccree/cc_fips.c cc_iowrite(drvdata, CC_REG(HOST_GPR0), val); CC_REG 126 drivers/crypto/ccree/cc_fips.c val = (CC_REG(HOST_IMR) & ~irq); CC_REG 127 drivers/crypto/ccree/cc_fips.c cc_iowrite(drvdata, CC_REG(HOST_IMR), val); CC_REG 28 drivers/crypto/ccree/cc_pm.c cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_ENABLE); CC_REG 51 drivers/crypto/ccree/cc_pm.c cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE); CC_REG 147 drivers/crypto/ccree/cc_request_mgr.c CC_REG(DSCRPTR_QUEUE_SRAM_SIZE)); CC_REG 189 drivers/crypto/ccree/cc_request_mgr.c void __iomem *reg = drvdata->cc_base + CC_REG(DSCRPTR_QUEUE_WORD0); CC_REG 248 drivers/crypto/ccree/cc_request_mgr.c cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT)); CC_REG 543 drivers/crypto/ccree/cc_request_mgr.c cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT)); CC_REG 644 drivers/crypto/ccree/cc_request_mgr.c cc_iowrite(drvdata, CC_REG(HOST_ICR), irq); CC_REG 655 drivers/crypto/ccree/cc_request_mgr.c drvdata->irq |= cc_ioread(drvdata, CC_REG(HOST_IRR)); CC_REG 666 drivers/crypto/ccree/cc_request_mgr.c cc_iowrite(drvdata, CC_REG(HOST_ICR), irq); CC_REG 674 drivers/crypto/ccree/cc_request_mgr.c cc_iowrite(drvdata, CC_REG(HOST_IMR), CC_REG 675 drivers/crypto/ccree/cc_request_mgr.c cc_ioread(drvdata, CC_REG(HOST_IMR)) & ~drvdata->comp_mask); CC_REG 41 drivers/crypto/ccree/cc_sram_mgr.c CC_REG(HOST_SEP_SRAM_THRESHOLD));