cf_port           131 drivers/ata/pata_octeon_cf.c 	struct octeon_cf_port *cf_port = ap->private_data;
cf_port           170 drivers/ata/pata_octeon_cf.c 	octeon_cf_set_boot_reg_cfg(cf_port->cs0, div);
cf_port           171 drivers/ata/pata_octeon_cf.c 	if (cf_port->is_true_ide)
cf_port           173 drivers/ata/pata_octeon_cf.c 		octeon_cf_set_boot_reg_cfg(cf_port->cs1, div);
cf_port           178 drivers/ata/pata_octeon_cf.c 	reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));
cf_port           207 drivers/ata/pata_octeon_cf.c 	cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);
cf_port           208 drivers/ata/pata_octeon_cf.c 	if (cf_port->is_true_ide)
cf_port           210 drivers/ata/pata_octeon_cf.c 		cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),
cf_port           216 drivers/ata/pata_octeon_cf.c 	struct octeon_cf_port *cf_port = ap->private_data;
cf_port           252 drivers/ata/pata_octeon_cf.c 	c = (cf_port->dma_base & 8) >> 3;
cf_port           282 drivers/ata/pata_octeon_cf.c 	cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);
cf_port           543 drivers/ata/pata_octeon_cf.c 	struct octeon_cf_port *cf_port;
cf_port           545 drivers/ata/pata_octeon_cf.c 	cf_port = ap->private_data;
cf_port           549 drivers/ata/pata_octeon_cf.c 	cf_port->dma_finished = 0;
cf_port           561 drivers/ata/pata_octeon_cf.c 	struct octeon_cf_port *cf_port = qc->ap->private_data;
cf_port           577 drivers/ata/pata_octeon_cf.c 	cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);
cf_port           580 drivers/ata/pata_octeon_cf.c 	cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);
cf_port           612 drivers/ata/pata_octeon_cf.c 	cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);
cf_port           625 drivers/ata/pata_octeon_cf.c 	struct octeon_cf_port *cf_port = ap->private_data;
cf_port           637 drivers/ata/pata_octeon_cf.c 	dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
cf_port           647 drivers/ata/pata_octeon_cf.c 	cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
cf_port           651 drivers/ata/pata_octeon_cf.c 	cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
cf_port           655 drivers/ata/pata_octeon_cf.c 	cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
cf_port           674 drivers/ata/pata_octeon_cf.c 	struct octeon_cf_port *cf_port;
cf_port           690 drivers/ata/pata_octeon_cf.c 		cf_port = ap->private_data;
cf_port           692 drivers/ata/pata_octeon_cf.c 		dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);
cf_port           693 drivers/ata/pata_octeon_cf.c 		dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
cf_port           707 drivers/ata/pata_octeon_cf.c 				cf_port->dma_finished = 1;
cf_port           710 drivers/ata/pata_octeon_cf.c 		if (!cf_port->dma_finished)
cf_port           723 drivers/ata/pata_octeon_cf.c 			cvmx_write_csr(cf_port->dma_base + DMA_INT,
cf_port           725 drivers/ata/pata_octeon_cf.c 			hrtimer_start_range_ns(&cf_port->delayed_finish,
cf_port           741 drivers/ata/pata_octeon_cf.c 	struct octeon_cf_port *cf_port = container_of(hrt,
cf_port           744 drivers/ata/pata_octeon_cf.c 	struct ata_port *ap = cf_port->ap;
cf_port           758 drivers/ata/pata_octeon_cf.c 	if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished)
cf_port           850 drivers/ata/pata_octeon_cf.c 	struct octeon_cf_port *cf_port;
cf_port           858 drivers/ata/pata_octeon_cf.c 	cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL);
cf_port           859 drivers/ata/pata_octeon_cf.c 	if (!cf_port)
cf_port           862 drivers/ata/pata_octeon_cf.c 	cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide");
cf_port           877 drivers/ata/pata_octeon_cf.c 	cf_port->cs0 = be32_to_cpup(cs_num);
cf_port           879 drivers/ata/pata_octeon_cf.c 	if (cf_port->is_true_ide) {
cf_port           894 drivers/ata/pata_octeon_cf.c 				cf_port->dma_base = (u64)devm_ioremap_nocache(&pdev->dev, res_dma->start,
cf_port           896 drivers/ata/pata_octeon_cf.c 				if (!cf_port->dma_base) {
cf_port           921 drivers/ata/pata_octeon_cf.c 		cf_port->cs1 = be32_to_cpup(cs_num);
cf_port           939 drivers/ata/pata_octeon_cf.c 	ap->private_data = cf_port;
cf_port           940 drivers/ata/pata_octeon_cf.c 	pdev->dev.platform_data = cf_port;
cf_port           941 drivers/ata/pata_octeon_cf.c 	cf_port->ap = ap;
cf_port           954 drivers/ata/pata_octeon_cf.c 	} else if (cf_port->is_true_ide) {
cf_port           974 drivers/ata/pata_octeon_cf.c 		hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,
cf_port           976 drivers/ata/pata_octeon_cf.c 		cf_port->delayed_finish.function = octeon_cf_delayed_finish;
cf_port           993 drivers/ata/pata_octeon_cf.c 	cf_port->c0 = ap->ioaddr.ctl_addr;
cf_port          1003 drivers/ata/pata_octeon_cf.c 		 cf_port->is_true_ide ? ", True IDE" : "");
cf_port          1014 drivers/ata/pata_octeon_cf.c 	struct octeon_cf_port *cf_port = dev_get_platdata(dev);
cf_port          1016 drivers/ata/pata_octeon_cf.c 	if (cf_port->dma_base) {
cf_port          1020 drivers/ata/pata_octeon_cf.c 		cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
cf_port          1024 drivers/ata/pata_octeon_cf.c 		cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
cf_port          1028 drivers/ata/pata_octeon_cf.c 		cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
cf_port          1030 drivers/ata/pata_octeon_cf.c 		__raw_writeb(0, cf_port->c0);
cf_port          1032 drivers/ata/pata_octeon_cf.c 		__raw_writeb(ATA_SRST, cf_port->c0);
cf_port          1034 drivers/ata/pata_octeon_cf.c 		__raw_writeb(0, cf_port->c0);
cf_port          3277 drivers/scsi/aha152x.c 				conf.cf_port =
cf_port          3282 drivers/scsi/aha152x.c 				conf.cf_port =