CCK_REG_DSI_PLL_CONTROL 1109 drivers/gpu/drm/i915/display/intel_display.c 	val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
CCK_REG_DSI_PLL_CONTROL  156 drivers/gpu/drm/i915/display/vlv_dsi_pll.c 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
CCK_REG_DSI_PLL_CONTROL  158 drivers/gpu/drm/i915/display/vlv_dsi_pll.c 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
CCK_REG_DSI_PLL_CONTROL  166 drivers/gpu/drm/i915/display/vlv_dsi_pll.c 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
CCK_REG_DSI_PLL_CONTROL  168 drivers/gpu/drm/i915/display/vlv_dsi_pll.c 	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
CCK_REG_DSI_PLL_CONTROL  189 drivers/gpu/drm/i915/display/vlv_dsi_pll.c 	tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
CCK_REG_DSI_PLL_CONTROL  192 drivers/gpu/drm/i915/display/vlv_dsi_pll.c 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
CCK_REG_DSI_PLL_CONTROL  269 drivers/gpu/drm/i915/display/vlv_dsi_pll.c 	pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);