cbus_writeb 330 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0xE0 + i, 0xF2); cbus_writeb 335 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0xF0 + i, 0xF2); cbus_writeb 344 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0x07, 0xF2); cbus_writeb 345 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0x40, 0x03); cbus_writeb 346 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0x42, 0x06); cbus_writeb 347 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0x36, 0x0C); cbus_writeb 348 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0x3D, 0xFD); cbus_writeb 349 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0x1C, 0x01); cbus_writeb 350 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0x1D, 0x0F); cbus_writeb 351 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0x44, 0x02); cbus_writeb 353 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEV_STATE, 0x00); cbus_writeb 354 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_MHL_VERSION, cbus_writeb 356 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_CAT, cbus_writeb 358 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_H, 0x01); cbus_writeb 359 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_L, 0x41); cbus_writeb 360 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VID_LINK_MODE, cbus_writeb 362 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VIDEO_TYPE, cbus_writeb 364 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_LOG_DEV_MAP, cbus_writeb 366 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_BANDWIDTH, 0x0F); cbus_writeb 367 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_FEATURE_FLAG, cbus_writeb 370 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_H, 0x0); cbus_writeb 371 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_L, 0x0); cbus_writeb 372 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_SCRATCHPAD_SIZE, cbus_writeb 374 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_INT_STAT_SIZE, cbus_writeb 376 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_RESERVED, 0); cbus_writeb 378 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0x30, 0x01); cbus_writeb 382 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_INTR1_ENABLE_REG, 0); cbus_writeb 383 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_INTR2_ENABLE_REG, 0); cbus_writeb 674 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, 0x07, 0x32); cbus_writeb 791 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_MHL_STATUS_REG_0, 0xFF); cbus_writeb 792 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_MHL_STATUS_REG_1, 0xFF); cbus_writeb 793 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_INT_STATUS_1_REG, cbus_intr1); cbus_writeb 794 drivers/gpu/drm/bridge/sii9234.c cbus_writeb(ctx, CBUS_INT_STATUS_2_REG, cbus_intr2);