cacheline_size    320 drivers/gpu/drm/amd/amdkfd/kfd_crat.c 			props->cacheline_size = cache->cache_line_size;
cacheline_size    341 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	sysfs_show_32bit_prop(buffer, "cache_line_size", cache->cacheline_size);
cacheline_size    120 drivers/gpu/drm/amd/amdkfd/kfd_topology.h 	uint32_t		cacheline_size;
cacheline_size   1072 drivers/gpu/drm/i915/display/intel_display_types.h 	u8 cacheline_size;
cacheline_size    586 drivers/gpu/drm/i915/intel_pm.c 	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
cacheline_size    593 drivers/gpu/drm/i915/intel_pm.c 	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
cacheline_size    600 drivers/gpu/drm/i915/intel_pm.c 	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
cacheline_size    607 drivers/gpu/drm/i915/intel_pm.c 	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
cacheline_size    614 drivers/gpu/drm/i915/intel_pm.c 	.cacheline_size = I915_FIFO_LINE_SIZE,
cacheline_size    621 drivers/gpu/drm/i915/intel_pm.c 	.cacheline_size = I915_FIFO_LINE_SIZE,
cacheline_size    628 drivers/gpu/drm/i915/intel_pm.c 	.cacheline_size = I915_FIFO_LINE_SIZE,
cacheline_size    635 drivers/gpu/drm/i915/intel_pm.c 	.cacheline_size = I830_FIFO_LINE_SIZE,
cacheline_size    642 drivers/gpu/drm/i915/intel_pm.c 	.cacheline_size = I830_FIFO_LINE_SIZE,
cacheline_size    649 drivers/gpu/drm/i915/intel_pm.c 	.cacheline_size = I830_FIFO_LINE_SIZE,
cacheline_size    782 drivers/gpu/drm/i915/intel_pm.c 	entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
cacheline_size   2245 drivers/gpu/drm/i915/intel_pm.c 				       i965_cursor_wm_info.cacheline_size) +
cacheline_size   2394 drivers/gpu/drm/i915/intel_pm.c 		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
cacheline_size   17063 drivers/net/ethernet/broadcom/tg3.c 	int cacheline_size;
cacheline_size   17069 drivers/net/ethernet/broadcom/tg3.c 		cacheline_size = 1024;
cacheline_size   17071 drivers/net/ethernet/broadcom/tg3.c 		cacheline_size = (int) byte * 4;
cacheline_size   17111 drivers/net/ethernet/broadcom/tg3.c 		switch (cacheline_size) {
cacheline_size   17136 drivers/net/ethernet/broadcom/tg3.c 		switch (cacheline_size) {
cacheline_size   17153 drivers/net/ethernet/broadcom/tg3.c 		switch (cacheline_size) {
cacheline_size   4192 drivers/pci/pci.c 	u8 cacheline_size;
cacheline_size   4199 drivers/pci/pci.c 	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
cacheline_size   4200 drivers/pci/pci.c 	if (cacheline_size >= pci_cache_line_size &&
cacheline_size   4201 drivers/pci/pci.c 	    (cacheline_size % pci_cache_line_size) == 0)
cacheline_size   4207 drivers/pci/pci.c 	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
cacheline_size   4208 drivers/pci/pci.c 	if (cacheline_size == pci_cache_line_size)
cacheline_size    297 drivers/scsi/myrb.h 	unsigned short cacheline_size;			/* Bytes 104-105 */
cacheline_size   1575 drivers/scsi/myrs.c 	if (ldev_info->cacheline_size) {
cacheline_size   1577 drivers/scsi/myrs.c 		put_unaligned_be16(1 << ldev_info->cacheline_size,
cacheline_size    413 drivers/scsi/myrs.h 	enum myrs_cacheline_size cacheline_size; /* Byte 7 */
cacheline_size      7 tools/perf/util/cacheline.h int __pure cacheline_size(void);
cacheline_size     12 tools/perf/util/cacheline.h 	return (address & ~(cacheline_size() - 1));
cacheline_size     18 tools/perf/util/cacheline.h 	return (address & (cacheline_size() - 1));
cacheline_size   2652 tools/perf/util/sort.c 		if (sd->entry == &sort_mem_dcacheline && cacheline_size() == 0)
cacheline_size   2698 tools/perf/util/sort.c 				if (!cacheline_size() && !strncasecmp(tok, "dcacheline", strlen(tok)))