bw_def_linear     261 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		tiling_mode[0] = bw_def_linear;
bw_def_linear     262 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		tiling_mode[1] = bw_def_linear;
bw_def_linear     263 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		tiling_mode[2] = bw_def_linear;
bw_def_linear     264 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		tiling_mode[3] = bw_def_linear;
bw_def_linear     326 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			tiling_mode[i] = bw_def_linear;
bw_def_linear     373 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear;
bw_def_linear     374 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear;
bw_def_linear     581 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && (tiling_mode[i] == bw_def_linear || data->stereo_mode[i] != bw_def_mono)) {
bw_def_linear     680 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			else if (tiling_mode[i] == bw_def_linear) {
bw_def_linear     865 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if ((dceip->dmif_pipe_en_fbc_chunk_tracker + 3 == i && fbc_enabled == 0 && tiling_mode[i] != bw_def_linear)) {
bw_def_linear     994 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (tiling_mode[i] == bw_def_linear) {
bw_def_linear    1098 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] != bw_def_linear) {
bw_def_linear    1101 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			else if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] == bw_def_linear && bw_equ(bw_mod((bw_mul(data->pitch_in_pixels_after_surface_type[i], bw_int_to_fixed(data->bytes_per_pixel[i]))), data->inefficient_linear_pitch_in_bytes), bw_int_to_fixed(0))) {