CBUS_DEVCAP_OFFSET  353 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEV_STATE, 0x00);
CBUS_DEVCAP_OFFSET  354 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_MHL_VERSION,
CBUS_DEVCAP_OFFSET  356 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_CAT,
CBUS_DEVCAP_OFFSET  358 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_H, 0x01);
CBUS_DEVCAP_OFFSET  359 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_L, 0x41);
CBUS_DEVCAP_OFFSET  360 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VID_LINK_MODE,
CBUS_DEVCAP_OFFSET  362 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VIDEO_TYPE,
CBUS_DEVCAP_OFFSET  364 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_LOG_DEV_MAP,
CBUS_DEVCAP_OFFSET  366 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_BANDWIDTH, 0x0F);
CBUS_DEVCAP_OFFSET  367 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_FEATURE_FLAG,
CBUS_DEVCAP_OFFSET  370 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_H, 0x0);
CBUS_DEVCAP_OFFSET  371 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_L, 0x0);
CBUS_DEVCAP_OFFSET  372 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_SCRATCHPAD_SIZE,
CBUS_DEVCAP_OFFSET  374 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_INT_STAT_SIZE,
CBUS_DEVCAP_OFFSET  376 drivers/gpu/drm/bridge/sii9234.c 	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_RESERVED, 0);