base 17 arch/alpha/boot/stdio.c # define do_div(n, base) ({ \ base 18 arch/alpha/boot/stdio.c unsigned int __base = (base); \ base 43 arch/alpha/boot/stdio.c static char * number(char * str, unsigned long long num, int base, int size, int precision, int type) base 53 arch/alpha/boot/stdio.c if (base < 2 || base > 36) base 71 arch/alpha/boot/stdio.c if (base == 16) base 73 arch/alpha/boot/stdio.c else if (base == 8) base 80 arch/alpha/boot/stdio.c tmp[i++] = digits[do_div(num, base)]; base 91 arch/alpha/boot/stdio.c if (base==8) base 93 arch/alpha/boot/stdio.c else if (base==16) { base 114 arch/alpha/boot/stdio.c int i, base; base 187 arch/alpha/boot/stdio.c base = 10; base 245 arch/alpha/boot/stdio.c base = 8; base 251 arch/alpha/boot/stdio.c base = 16; base 287 arch/alpha/boot/stdio.c str = number(str, num, base, field_width, precision, flags); base 523 arch/alpha/kernel/core_mcpcia.c unsigned long base; base 554 arch/alpha/kernel/core_mcpcia.c hose->index, iodpp->base); base 326 arch/alpha/kernel/core_t2.c t2_direct_map_window1(unsigned long base, unsigned long length) base 330 arch/alpha/kernel/core_t2.c __direct_map_base = base; base 333 arch/alpha/kernel/core_t2.c temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20); base 347 arch/alpha/kernel/core_t2.c unsigned long base, base 354 arch/alpha/kernel/core_t2.c hose->sg_isa = iommu_arena_new(hose, base, length, SMP_CACHE_BYTES); base 357 arch/alpha/kernel/core_t2.c temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20); base 140 arch/alpha/kernel/module.c void *base, *location; base 146 arch/alpha/kernel/module.c base = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr; base 151 arch/alpha/kernel/module.c gp = (u64)me->core_layout.base + me->core_layout.size - 0x8000; base 162 arch/alpha/kernel/module.c location = base + rela[i].r_offset; base 13 arch/alpha/kernel/pc873xx.c static unsigned int base, model; base 18 arch/alpha/kernel/pc873xx.c return base; base 26 arch/alpha/kernel/pc873xx.c static unsigned char __init pc873xx_read(unsigned int base, int reg) base 28 arch/alpha/kernel/pc873xx.c outb(reg, base); base 29 arch/alpha/kernel/pc873xx.c return inb(base + 1); base 32 arch/alpha/kernel/pc873xx.c static void __init pc873xx_write(unsigned int base, int reg, unsigned char data) base 37 arch/alpha/kernel/pc873xx.c outb(reg, base); base 38 arch/alpha/kernel/pc873xx.c outb(data, base + 1); base 39 arch/alpha/kernel/pc873xx.c outb(data, base + 1); /* Must be written twice */ base 47 arch/alpha/kernel/pc873xx.c while ((base = pc873xx_probelist[index++])) { base 49 arch/alpha/kernel/pc873xx.c if (request_region(base, 2, "Super IO PC873xx") == NULL) base 52 arch/alpha/kernel/pc873xx.c val = pc873xx_read(base, REG_SID); base 67 arch/alpha/kernel/pc873xx.c release_region(base, 2); base 70 arch/alpha/kernel/pc873xx.c return (base == 0) ? -1 : 1; base 78 arch/alpha/kernel/pc873xx.c data = pc873xx_read(base, REG_PCR); base 79 arch/alpha/kernel/pc873xx.c pc873xx_write(base, REG_PCR, (data & 0xFC) | 0x02); base 87 arch/alpha/kernel/pc873xx.c data = pc873xx_read(base, REG_FER); base 88 arch/alpha/kernel/pc873xx.c pc873xx_write(base, REG_FER, data | 0x40); base 22 arch/alpha/kernel/pci-sysfs.c unsigned long base; base 25 arch/alpha/kernel/pci-sysfs.c base = sparse ? hose->sparse_mem_base : hose->dense_mem_base; base 27 arch/alpha/kernel/pci-sysfs.c base = sparse ? hose->sparse_io_base : hose->dense_io_base; base 29 arch/alpha/kernel/pci-sysfs.c vma->vm_pgoff += base >> PAGE_SHIFT; base 274 arch/alpha/kernel/pci-sysfs.c unsigned long base; base 276 arch/alpha/kernel/pci-sysfs.c base = (mmap_type == pci_mmap_mem) ? hose->sparse_mem_base : base 279 arch/alpha/kernel/pci-sysfs.c return base != 0; base 59 arch/alpha/kernel/pci_iommu.c iommu_arena_new_node(int nid, struct pci_controller *hose, dma_addr_t base, base 114 arch/alpha/kernel/pci_iommu.c arena->dma_base = base; base 126 arch/alpha/kernel/pci_iommu.c iommu_arena_new(struct pci_controller *hose, dma_addr_t base, base 129 arch/alpha/kernel/pci_iommu.c return iommu_arena_new_node(0, hose, base, window_size, align); base 140 arch/alpha/kernel/pci_iommu.c unsigned long base; base 143 arch/alpha/kernel/pci_iommu.c base = arena->dma_base >> PAGE_SHIFT; base 159 arch/alpha/kernel/pci_iommu.c if (!i && iommu_is_span_boundary(p, n, base, boundary_size)) { base 368 arch/alpha/kernel/process.c unsigned long base = (unsigned long)task_stack_page(t); base 371 arch/alpha/kernel/process.c if (sp > base && sp+6*8 < base + 16*1024) { base 373 arch/alpha/kernel/process.c if (fp > sp && fp < base + 16*1024) base 250 arch/alpha/kernel/sys_marvel.c long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16; base 254 arch/alpha/kernel/sys_marvel.c io7->pe, base); base 278 arch/alpha/kernel/sys_marvel.c irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq); base 292 arch/alpha/kernel/sys_marvel.c irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq); base 170 arch/arc/include/asm/arcregs.h unsigned int base:16, pad:5, sz:3, ver:8; base 172 arch/arc/include/asm/arcregs.h unsigned int ver:8, sz:3, pad:5, base:16; base 75 arch/arc/kernel/setup.c cpu->iccm.base_addr = iccm.base << 16; base 80 arch/arc/kernel/setup.c unsigned long base; base 83 arch/arc/kernel/setup.c base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); base 84 arch/arc/kernel/setup.c cpu->dccm.base_addr = base & ~0xF; base 385 arch/arc/kernel/unwind.c module->core_layout.base, module->core_layout.size, base 386 arch/arc/kernel/unwind.c module->init_layout.base, module->init_layout.size, base 56 arch/arc/mm/init.c void __init early_init_dt_add_memory_arch(u64 base, u64 size) base 61 arch/arc/mm/init.c if (base != low_mem_start) base 68 arch/arc/mm/init.c high_mem_start = base; base 75 arch/arc/mm/init.c base, TO_MB(size), !in_use ? "Not used":""); base 229 arch/arc/plat-axs10x/axs10x.c axs101_set_memmap(void __iomem *base, const struct aperture map[16]) base 240 arch/arc/plat-axs10x/axs10x.c iowrite32(slave_select, base + 0x0); /* SLV0 */ base 241 arch/arc/plat-axs10x/axs10x.c iowrite32(slave_offset, base + 0x8); /* OFFSET0 */ base 249 arch/arc/plat-axs10x/axs10x.c iowrite32(slave_select, base + 0x4); /* SLV1 */ base 250 arch/arc/plat-axs10x/axs10x.c iowrite32(slave_offset, base + 0xC); /* OFFSET1 */ base 66 arch/arm/common/locomo.c void __iomem *base; base 147 arch/arm/common/locomo.c req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00; base 171 arch/arm/common/locomo.c r = locomo_readl(lchip->base + LOCOMO_ICR); base 173 arch/arm/common/locomo.c locomo_writel(r, lchip->base + LOCOMO_ICR); base 180 arch/arm/common/locomo.c r = locomo_readl(lchip->base + LOCOMO_ICR); base 182 arch/arm/common/locomo.c locomo_writel(r, lchip->base + LOCOMO_ICR); base 247 arch/arm/common/locomo.c dev->mapbase = lchip->base + info->offset; base 287 arch/arm/common/locomo.c save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); /* GPIO */ base 288 arch/arm/common/locomo.c locomo_writel(0x00, lchip->base + LOCOMO_GPO); base 289 arch/arm/common/locomo.c save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPICT); /* SPI */ base 290 arch/arm/common/locomo.c locomo_writel(0x40, lchip->base + LOCOMO_SPI + LOCOMO_SPICT); base 291 arch/arm/common/locomo.c save->LCM_GPE = locomo_readl(lchip->base + LOCOMO_GPE); /* GPIO */ base 292 arch/arm/common/locomo.c locomo_writel(0x00, lchip->base + LOCOMO_GPE); base 293 arch/arm/common/locomo.c save->LCM_ASD = locomo_readl(lchip->base + LOCOMO_ASD); /* ADSTART */ base 294 arch/arm/common/locomo.c locomo_writel(0x00, lchip->base + LOCOMO_ASD); base 295 arch/arm/common/locomo.c save->LCM_SPIMD = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); /* SPI */ base 296 arch/arm/common/locomo.c locomo_writel(0x3C14, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); base 298 arch/arm/common/locomo.c locomo_writel(0x00, lchip->base + LOCOMO_PAIF); base 299 arch/arm/common/locomo.c locomo_writel(0x00, lchip->base + LOCOMO_DAC); base 300 arch/arm/common/locomo.c locomo_writel(0x00, lchip->base + LOCOMO_BACKLIGHT + LOCOMO_TC); base 302 arch/arm/common/locomo.c if ((locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88)) base 303 arch/arm/common/locomo.c locomo_writel(0x00, lchip->base + LOCOMO_C32K); /* CLK32 off */ base 306 arch/arm/common/locomo.c locomo_writel(0xc1, lchip->base + LOCOMO_C32K); /* CLK32 on */ base 308 arch/arm/common/locomo.c locomo_writel(0x00, lchip->base + LOCOMO_TADC); /* 18MHz clock off*/ base 309 arch/arm/common/locomo.c locomo_writel(0x00, lchip->base + LOCOMO_AUDIO + LOCOMO_ACC); /* 22MHz/24MHz clock off */ base 310 arch/arm/common/locomo.c locomo_writel(0x00, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); /* FL */ base 330 arch/arm/common/locomo.c locomo_writel(save->LCM_GPO, lchip->base + LOCOMO_GPO); base 331 arch/arm/common/locomo.c locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPI + LOCOMO_SPICT); base 332 arch/arm/common/locomo.c locomo_writel(save->LCM_GPE, lchip->base + LOCOMO_GPE); base 333 arch/arm/common/locomo.c locomo_writel(save->LCM_ASD, lchip->base + LOCOMO_ASD); base 334 arch/arm/common/locomo.c locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); base 336 arch/arm/common/locomo.c locomo_writel(0x00, lchip->base + LOCOMO_C32K); base 337 arch/arm/common/locomo.c locomo_writel(0x90, lchip->base + LOCOMO_TADC); base 339 arch/arm/common/locomo.c locomo_writel(0, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KSC); base 340 arch/arm/common/locomo.c r = locomo_readl(lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC); base 342 arch/arm/common/locomo.c locomo_writel(r, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC); base 343 arch/arm/common/locomo.c locomo_writel(0x1, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KCMD); base 392 arch/arm/common/locomo.c lchip->base = ioremap(mem->start, PAGE_SIZE); base 393 arch/arm/common/locomo.c if (!lchip->base) { base 399 arch/arm/common/locomo.c locomo_writel(0, lchip->base + LOCOMO_ICR); base 401 arch/arm/common/locomo.c locomo_writel(0, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC); base 404 arch/arm/common/locomo.c locomo_writel(0, lchip->base + LOCOMO_GPO); base 406 arch/arm/common/locomo.c , lchip->base + LOCOMO_GPE); base 408 arch/arm/common/locomo.c , lchip->base + LOCOMO_GPD); base 409 arch/arm/common/locomo.c locomo_writel(0, lchip->base + LOCOMO_GIE); base 412 arch/arm/common/locomo.c locomo_writel(0, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); base 413 arch/arm/common/locomo.c locomo_writel(0, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALD); base 416 arch/arm/common/locomo.c locomo_writel(0, lchip->base + LOCOMO_LTINT); base 418 arch/arm/common/locomo.c locomo_writel(0, lchip->base + LOCOMO_SPI + LOCOMO_SPIIE); base 420 arch/arm/common/locomo.c locomo_writel(6 + 8 + 320 + 30 - 10, lchip->base + LOCOMO_ASD); base 421 arch/arm/common/locomo.c r = locomo_readl(lchip->base + LOCOMO_ASD); base 423 arch/arm/common/locomo.c locomo_writel(r, lchip->base + LOCOMO_ASD); base 425 arch/arm/common/locomo.c locomo_writel(6 + 8 + 320 + 30 - 10 - 128 + 4, lchip->base + LOCOMO_HSD); base 426 arch/arm/common/locomo.c r = locomo_readl(lchip->base + LOCOMO_HSD); base 428 arch/arm/common/locomo.c locomo_writel(r, lchip->base + LOCOMO_HSD); base 430 arch/arm/common/locomo.c locomo_writel(128 / 8, lchip->base + LOCOMO_HSC); base 433 arch/arm/common/locomo.c locomo_writel(0x80, lchip->base + LOCOMO_TADC); base 436 arch/arm/common/locomo.c r = locomo_readl(lchip->base + LOCOMO_TADC); base 438 arch/arm/common/locomo.c locomo_writel(r, lchip->base + LOCOMO_TADC); base 442 arch/arm/common/locomo.c r = locomo_readl(lchip->base + LOCOMO_DAC); base 444 arch/arm/common/locomo.c locomo_writel(r, lchip->base + LOCOMO_DAC); base 446 arch/arm/common/locomo.c r = locomo_readl(lchip->base + LOCOMO_VER); base 479 arch/arm/common/locomo.c iounmap(lchip->base); base 548 arch/arm/common/locomo.c r = locomo_readl(lchip->base + LOCOMO_GPD); base 553 arch/arm/common/locomo.c locomo_writel(r, lchip->base + LOCOMO_GPD); base 555 arch/arm/common/locomo.c r = locomo_readl(lchip->base + LOCOMO_GPE); base 560 arch/arm/common/locomo.c locomo_writel(r, lchip->base + LOCOMO_GPE); base 576 arch/arm/common/locomo.c ret = locomo_readl(lchip->base + LOCOMO_GPL); base 594 arch/arm/common/locomo.c ret = locomo_readl(lchip->base + LOCOMO_GPO); base 613 arch/arm/common/locomo.c r = locomo_readl(lchip->base + LOCOMO_GPO); base 618 arch/arm/common/locomo.c locomo_writel(r, lchip->base + LOCOMO_GPO); base 665 arch/arm/common/locomo.c void *mapbase = lchip->base; base 804 arch/arm/common/locomo.c locomo_writel(bpwf, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); base 806 arch/arm/common/locomo.c locomo_writel(duty, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALD); base 807 arch/arm/common/locomo.c locomo_writel(bpwf | LOCOMO_ALC_EN, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS); base 106 arch/arm/common/sa1111.c void __iomem *base; base 217 arch/arm/common/sa1111.c void __iomem *mapbase = sachip->base + SA1111_INTC; base 264 arch/arm/common/sa1111.c void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); base 275 arch/arm/common/sa1111.c void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); base 293 arch/arm/common/sa1111.c void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); base 314 arch/arm/common/sa1111.c void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); base 337 arch/arm/common/sa1111.c void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d); base 383 arch/arm/common/sa1111.c void __iomem *irqbase = sachip->base + SA1111_INTC; base 453 arch/arm/common/sa1111.c void __iomem *irqbase = sachip->base + SA1111_INTC; base 485 arch/arm/common/sa1111.c void __iomem *reg = sachip->base + SA1111_GPIO; base 586 arch/arm/common/sa1111.c void __iomem *reg = sachip->base + SA1111_GPIO; base 621 arch/arm/common/sa1111.c sachip->gc.base = -1; base 652 arch/arm/common/sa1111.c r = readl_relaxed(sachip->base + SA1111_SKCR); base 654 arch/arm/common/sa1111.c writel_relaxed(r, sachip->base + SA1111_SKCR); base 656 arch/arm/common/sa1111.c writel_relaxed(r, sachip->base + SA1111_SKCR); base 668 arch/arm/common/sa1111.c writel_relaxed(r, sachip->base + SA1111_SKCR); base 679 arch/arm/common/sa1111.c writel_relaxed(0, sachip->base + SA1111_SKPCR); base 709 arch/arm/common/sa1111.c writel_relaxed(smcr, sachip->base + SA1111_SMCR); base 754 arch/arm/common/sa1111.c dev->mapbase = sachip->base + info->offset; base 839 arch/arm/common/sa1111.c sachip->base = ioremap(mem->start, PAGE_SIZE * 2); base 840 arch/arm/common/sa1111.c if (!sachip->base) { base 848 arch/arm/common/sa1111.c id = readl_relaxed(sachip->base + SA1111_SKID); base 896 arch/arm/common/sa1111.c val = readl_relaxed(sachip->base + SA1111_SKPCR); base 897 arch/arm/common/sa1111.c writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR); base 923 arch/arm/common/sa1111.c iounmap(sachip->base); base 949 arch/arm/common/sa1111.c iounmap(sachip->base); base 981 arch/arm/common/sa1111.c void __iomem *base; base 993 arch/arm/common/sa1111.c base = sachip->base; base 994 arch/arm/common/sa1111.c save->skcr = readl_relaxed(base + SA1111_SKCR); base 995 arch/arm/common/sa1111.c save->skpcr = readl_relaxed(base + SA1111_SKPCR); base 996 arch/arm/common/sa1111.c save->skcdr = readl_relaxed(base + SA1111_SKCDR); base 997 arch/arm/common/sa1111.c save->skaud = readl_relaxed(base + SA1111_SKAUD); base 998 arch/arm/common/sa1111.c save->skpwm0 = readl_relaxed(base + SA1111_SKPWM0); base 999 arch/arm/common/sa1111.c save->skpwm1 = readl_relaxed(base + SA1111_SKPWM1); base 1001 arch/arm/common/sa1111.c writel_relaxed(0, sachip->base + SA1111_SKPWM0); base 1002 arch/arm/common/sa1111.c writel_relaxed(0, sachip->base + SA1111_SKPWM1); base 1004 arch/arm/common/sa1111.c base = sachip->base + SA1111_INTC; base 1005 arch/arm/common/sa1111.c save->intpol0 = readl_relaxed(base + SA1111_INTPOL0); base 1006 arch/arm/common/sa1111.c save->intpol1 = readl_relaxed(base + SA1111_INTPOL1); base 1007 arch/arm/common/sa1111.c save->inten0 = readl_relaxed(base + SA1111_INTEN0); base 1008 arch/arm/common/sa1111.c save->inten1 = readl_relaxed(base + SA1111_INTEN1); base 1009 arch/arm/common/sa1111.c save->wakepol0 = readl_relaxed(base + SA1111_WAKEPOL0); base 1010 arch/arm/common/sa1111.c save->wakepol1 = readl_relaxed(base + SA1111_WAKEPOL1); base 1011 arch/arm/common/sa1111.c save->wakeen0 = readl_relaxed(base + SA1111_WAKEEN0); base 1012 arch/arm/common/sa1111.c save->wakeen1 = readl_relaxed(base + SA1111_WAKEEN1); base 1017 arch/arm/common/sa1111.c val = readl_relaxed(sachip->base + SA1111_SKCR); base 1018 arch/arm/common/sa1111.c writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR); base 1045 arch/arm/common/sa1111.c void __iomem *base; base 1055 arch/arm/common/sa1111.c id = readl_relaxed(sachip->base + SA1111_SKID); base 1079 arch/arm/common/sa1111.c writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0); base 1080 arch/arm/common/sa1111.c writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1); base 1082 arch/arm/common/sa1111.c base = sachip->base; base 1083 arch/arm/common/sa1111.c writel_relaxed(save->skcr, base + SA1111_SKCR); base 1084 arch/arm/common/sa1111.c writel_relaxed(save->skpcr, base + SA1111_SKPCR); base 1085 arch/arm/common/sa1111.c writel_relaxed(save->skcdr, base + SA1111_SKCDR); base 1086 arch/arm/common/sa1111.c writel_relaxed(save->skaud, base + SA1111_SKAUD); base 1087 arch/arm/common/sa1111.c writel_relaxed(save->skpwm0, base + SA1111_SKPWM0); base 1088 arch/arm/common/sa1111.c writel_relaxed(save->skpwm1, base + SA1111_SKPWM1); base 1090 arch/arm/common/sa1111.c base = sachip->base + SA1111_INTC; base 1091 arch/arm/common/sa1111.c writel_relaxed(save->intpol0, base + SA1111_INTPOL0); base 1092 arch/arm/common/sa1111.c writel_relaxed(save->intpol1, base + SA1111_INTPOL1); base 1093 arch/arm/common/sa1111.c writel_relaxed(save->inten0, base + SA1111_INTEN0); base 1094 arch/arm/common/sa1111.c writel_relaxed(save->inten1, base + SA1111_INTEN1); base 1095 arch/arm/common/sa1111.c writel_relaxed(save->wakepol0, base + SA1111_WAKEPOL0); base 1096 arch/arm/common/sa1111.c writel_relaxed(save->wakepol1, base + SA1111_WAKEPOL1); base 1097 arch/arm/common/sa1111.c writel_relaxed(save->wakeen0, base + SA1111_WAKEEN0); base 1098 arch/arm/common/sa1111.c writel_relaxed(save->wakeen1, base + SA1111_WAKEEN1); base 1185 arch/arm/common/sa1111.c skcdr = readl_relaxed(sachip->base + SA1111_SKCDR); base 1227 arch/arm/common/sa1111.c val = readl_relaxed(sachip->base + SA1111_SKCR); base 1233 arch/arm/common/sa1111.c writel_relaxed(val, sachip->base + SA1111_SKCR); base 1258 arch/arm/common/sa1111.c writel_relaxed(div - 1, sachip->base + SA1111_SKAUD); base 1276 arch/arm/common/sa1111.c div = readl_relaxed(sachip->base + SA1111_SKAUD) + 1; base 1302 arch/arm/common/sa1111.c val = readl_relaxed(sachip->base + SA1111_SKPCR); base 1303 arch/arm/common/sa1111.c writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR); base 1321 arch/arm/common/sa1111.c val = readl_relaxed(sachip->base + SA1111_SKPCR); base 1322 arch/arm/common/sa1111.c writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR); base 32 arch/arm/common/scoop.c void __iomem *base; base 44 arch/arm/common/scoop.c iowrite16(0x0100, sdev->base + SCOOP_MCR); /* 00 */ base 45 arch/arm/common/scoop.c iowrite16(0x0000, sdev->base + SCOOP_CDR); /* 04 */ base 46 arch/arm/common/scoop.c iowrite16(0x0000, sdev->base + SCOOP_CCR); /* 10 */ base 47 arch/arm/common/scoop.c iowrite16(0x0000, sdev->base + SCOOP_IMR); /* 18 */ base 48 arch/arm/common/scoop.c iowrite16(0x00FF, sdev->base + SCOOP_IRM); /* 14 */ base 49 arch/arm/common/scoop.c iowrite16(0x0000, sdev->base + SCOOP_ISR); /* 1C */ base 50 arch/arm/common/scoop.c iowrite16(0x0000, sdev->base + SCOOP_IRM); base 58 arch/arm/common/scoop.c gpwr = ioread16(sdev->base + SCOOP_GPWR); base 63 arch/arm/common/scoop.c iowrite16(gpwr, sdev->base + SCOOP_GPWR); base 83 arch/arm/common/scoop.c return !!(ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1))); base 95 arch/arm/common/scoop.c gpcr = ioread16(sdev->base + SCOOP_GPCR); base 97 arch/arm/common/scoop.c iowrite16(gpcr, sdev->base + SCOOP_GPCR); base 115 arch/arm/common/scoop.c gpcr = ioread16(sdev->base + SCOOP_GPCR); base 117 arch/arm/common/scoop.c iowrite16(gpcr, sdev->base + SCOOP_GPCR); base 127 arch/arm/common/scoop.c return ioread16(sdev->base + reg); base 133 arch/arm/common/scoop.c iowrite16(data, sdev->base + reg); base 145 arch/arm/common/scoop.c mcr = ioread16(sdev->base + SCOOP_MCR); base 147 arch/arm/common/scoop.c iowrite16(0x0101, sdev->base + SCOOP_MCR); base 155 arch/arm/common/scoop.c sdev->scoop_gpwr = ioread16(sdev->base + SCOOP_GPWR); base 156 arch/arm/common/scoop.c iowrite16((sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set, sdev->base + SCOOP_GPWR); base 166 arch/arm/common/scoop.c iowrite16(sdev->scoop_gpwr, sdev->base + SCOOP_GPWR); base 192 arch/arm/common/scoop.c devptr->base = ioremap(mem->start, resource_size(mem)); base 194 arch/arm/common/scoop.c if (!devptr->base) { base 201 arch/arm/common/scoop.c printk("Sharp Scoop Device found at 0x%08x -> 0x%8p\n",(unsigned int)mem->start, devptr->base); base 203 arch/arm/common/scoop.c iowrite16(0x0140, devptr->base + SCOOP_MCR); base 205 arch/arm/common/scoop.c iowrite16(0x0000, devptr->base + SCOOP_CPR); base 206 arch/arm/common/scoop.c iowrite16(inf->io_dir & 0xffff, devptr->base + SCOOP_GPCR); base 207 arch/arm/common/scoop.c iowrite16(inf->io_out & 0xffff, devptr->base + SCOOP_GPWR); base 212 arch/arm/common/scoop.c devptr->gpio.base = -1; base 216 arch/arm/common/scoop.c devptr->gpio.base = inf->gpio_base; base 233 arch/arm/common/scoop.c iounmap(devptr->base); base 246 arch/arm/common/scoop.c if (sdev->gpio.base != -1) base 250 arch/arm/common/scoop.c iounmap(sdev->base); base 599 arch/arm/crypto/aes-ce-glue.c .base.cra_name = "__ecb(aes)", base 600 arch/arm/crypto/aes-ce-glue.c .base.cra_driver_name = "__ecb-aes-ce", base 601 arch/arm/crypto/aes-ce-glue.c .base.cra_priority = 300, base 602 arch/arm/crypto/aes-ce-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 603 arch/arm/crypto/aes-ce-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 604 arch/arm/crypto/aes-ce-glue.c .base.cra_ctxsize = sizeof(struct crypto_aes_ctx), base 605 arch/arm/crypto/aes-ce-glue.c .base.cra_module = THIS_MODULE, base 613 arch/arm/crypto/aes-ce-glue.c .base.cra_name = "__cbc(aes)", base 614 arch/arm/crypto/aes-ce-glue.c .base.cra_driver_name = "__cbc-aes-ce", base 615 arch/arm/crypto/aes-ce-glue.c .base.cra_priority = 300, base 616 arch/arm/crypto/aes-ce-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 617 arch/arm/crypto/aes-ce-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 618 arch/arm/crypto/aes-ce-glue.c .base.cra_ctxsize = sizeof(struct crypto_aes_ctx), base 619 arch/arm/crypto/aes-ce-glue.c .base.cra_module = THIS_MODULE, base 628 arch/arm/crypto/aes-ce-glue.c .base.cra_name = "__cts(cbc(aes))", base 629 arch/arm/crypto/aes-ce-glue.c .base.cra_driver_name = "__cts-cbc-aes-ce", base 630 arch/arm/crypto/aes-ce-glue.c .base.cra_priority = 300, base 631 arch/arm/crypto/aes-ce-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 632 arch/arm/crypto/aes-ce-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 633 arch/arm/crypto/aes-ce-glue.c .base.cra_ctxsize = sizeof(struct crypto_aes_ctx), base 634 arch/arm/crypto/aes-ce-glue.c .base.cra_module = THIS_MODULE, base 644 arch/arm/crypto/aes-ce-glue.c .base.cra_name = "__ctr(aes)", base 645 arch/arm/crypto/aes-ce-glue.c .base.cra_driver_name = "__ctr-aes-ce", base 646 arch/arm/crypto/aes-ce-glue.c .base.cra_priority = 300, base 647 arch/arm/crypto/aes-ce-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 648 arch/arm/crypto/aes-ce-glue.c .base.cra_blocksize = 1, base 649 arch/arm/crypto/aes-ce-glue.c .base.cra_ctxsize = sizeof(struct crypto_aes_ctx), base 650 arch/arm/crypto/aes-ce-glue.c .base.cra_module = THIS_MODULE, base 660 arch/arm/crypto/aes-ce-glue.c .base.cra_name = "ctr(aes)", base 661 arch/arm/crypto/aes-ce-glue.c .base.cra_driver_name = "ctr-aes-ce-sync", base 662 arch/arm/crypto/aes-ce-glue.c .base.cra_priority = 300 - 1, base 663 arch/arm/crypto/aes-ce-glue.c .base.cra_blocksize = 1, base 664 arch/arm/crypto/aes-ce-glue.c .base.cra_ctxsize = sizeof(struct crypto_aes_ctx), base 665 arch/arm/crypto/aes-ce-glue.c .base.cra_module = THIS_MODULE, base 675 arch/arm/crypto/aes-ce-glue.c .base.cra_name = "__xts(aes)", base 676 arch/arm/crypto/aes-ce-glue.c .base.cra_driver_name = "__xts-aes-ce", base 677 arch/arm/crypto/aes-ce-glue.c .base.cra_priority = 300, base 678 arch/arm/crypto/aes-ce-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 679 arch/arm/crypto/aes-ce-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 680 arch/arm/crypto/aes-ce-glue.c .base.cra_ctxsize = sizeof(struct crypto_aes_xts_ctx), base 681 arch/arm/crypto/aes-ce-glue.c .base.cra_module = THIS_MODULE, base 718 arch/arm/crypto/aes-ce-glue.c if (!(aes_algs[i].base.cra_flags & CRYPTO_ALG_INTERNAL)) base 721 arch/arm/crypto/aes-ce-glue.c algname = aes_algs[i].base.cra_name + 2; base 722 arch/arm/crypto/aes-ce-glue.c drvname = aes_algs[i].base.cra_driver_name + 2; base 723 arch/arm/crypto/aes-ce-glue.c basename = aes_algs[i].base.cra_driver_name; base 412 arch/arm/crypto/aes-neonbs-glue.c .base.cra_name = "__ecb(aes)", base 413 arch/arm/crypto/aes-neonbs-glue.c .base.cra_driver_name = "__ecb-aes-neonbs", base 414 arch/arm/crypto/aes-neonbs-glue.c .base.cra_priority = 250, base 415 arch/arm/crypto/aes-neonbs-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 416 arch/arm/crypto/aes-neonbs-glue.c .base.cra_ctxsize = sizeof(struct aesbs_ctx), base 417 arch/arm/crypto/aes-neonbs-glue.c .base.cra_module = THIS_MODULE, base 418 arch/arm/crypto/aes-neonbs-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 427 arch/arm/crypto/aes-neonbs-glue.c .base.cra_name = "__cbc(aes)", base 428 arch/arm/crypto/aes-neonbs-glue.c .base.cra_driver_name = "__cbc-aes-neonbs", base 429 arch/arm/crypto/aes-neonbs-glue.c .base.cra_priority = 250, base 430 arch/arm/crypto/aes-neonbs-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 431 arch/arm/crypto/aes-neonbs-glue.c .base.cra_ctxsize = sizeof(struct aesbs_cbc_ctx), base 432 arch/arm/crypto/aes-neonbs-glue.c .base.cra_module = THIS_MODULE, base 433 arch/arm/crypto/aes-neonbs-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 434 arch/arm/crypto/aes-neonbs-glue.c .base.cra_init = cbc_init, base 435 arch/arm/crypto/aes-neonbs-glue.c .base.cra_exit = cbc_exit, base 445 arch/arm/crypto/aes-neonbs-glue.c .base.cra_name = "__ctr(aes)", base 446 arch/arm/crypto/aes-neonbs-glue.c .base.cra_driver_name = "__ctr-aes-neonbs", base 447 arch/arm/crypto/aes-neonbs-glue.c .base.cra_priority = 250, base 448 arch/arm/crypto/aes-neonbs-glue.c .base.cra_blocksize = 1, base 449 arch/arm/crypto/aes-neonbs-glue.c .base.cra_ctxsize = sizeof(struct aesbs_ctx), base 450 arch/arm/crypto/aes-neonbs-glue.c .base.cra_module = THIS_MODULE, base 451 arch/arm/crypto/aes-neonbs-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 462 arch/arm/crypto/aes-neonbs-glue.c .base.cra_name = "ctr(aes)", base 463 arch/arm/crypto/aes-neonbs-glue.c .base.cra_driver_name = "ctr-aes-neonbs-sync", base 464 arch/arm/crypto/aes-neonbs-glue.c .base.cra_priority = 250 - 1, base 465 arch/arm/crypto/aes-neonbs-glue.c .base.cra_blocksize = 1, base 466 arch/arm/crypto/aes-neonbs-glue.c .base.cra_ctxsize = sizeof(struct aesbs_ctr_ctx), base 467 arch/arm/crypto/aes-neonbs-glue.c .base.cra_module = THIS_MODULE, base 478 arch/arm/crypto/aes-neonbs-glue.c .base.cra_name = "__xts(aes)", base 479 arch/arm/crypto/aes-neonbs-glue.c .base.cra_driver_name = "__xts-aes-neonbs", base 480 arch/arm/crypto/aes-neonbs-glue.c .base.cra_priority = 250, base 481 arch/arm/crypto/aes-neonbs-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 482 arch/arm/crypto/aes-neonbs-glue.c .base.cra_ctxsize = sizeof(struct aesbs_xts_ctx), base 483 arch/arm/crypto/aes-neonbs-glue.c .base.cra_module = THIS_MODULE, base 484 arch/arm/crypto/aes-neonbs-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 485 arch/arm/crypto/aes-neonbs-glue.c .base.cra_init = xts_init, base 486 arch/arm/crypto/aes-neonbs-glue.c .base.cra_exit = xts_exit, base 527 arch/arm/crypto/aes-neonbs-glue.c if (!(aes_algs[i].base.cra_flags & CRYPTO_ALG_INTERNAL)) base 530 arch/arm/crypto/aes-neonbs-glue.c algname = aes_algs[i].base.cra_name + 2; base 531 arch/arm/crypto/aes-neonbs-glue.c drvname = aes_algs[i].base.cra_driver_name + 2; base 532 arch/arm/crypto/aes-neonbs-glue.c basename = aes_algs[i].base.cra_driver_name; base 128 arch/arm/crypto/chacha-neon-glue.c .base.cra_name = "chacha20", base 129 arch/arm/crypto/chacha-neon-glue.c .base.cra_driver_name = "chacha20-neon", base 130 arch/arm/crypto/chacha-neon-glue.c .base.cra_priority = 300, base 131 arch/arm/crypto/chacha-neon-glue.c .base.cra_blocksize = 1, base 132 arch/arm/crypto/chacha-neon-glue.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 133 arch/arm/crypto/chacha-neon-glue.c .base.cra_module = THIS_MODULE, base 144 arch/arm/crypto/chacha-neon-glue.c .base.cra_name = "xchacha20", base 145 arch/arm/crypto/chacha-neon-glue.c .base.cra_driver_name = "xchacha20-neon", base 146 arch/arm/crypto/chacha-neon-glue.c .base.cra_priority = 300, base 147 arch/arm/crypto/chacha-neon-glue.c .base.cra_blocksize = 1, base 148 arch/arm/crypto/chacha-neon-glue.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 149 arch/arm/crypto/chacha-neon-glue.c .base.cra_module = THIS_MODULE, base 160 arch/arm/crypto/chacha-neon-glue.c .base.cra_name = "xchacha12", base 161 arch/arm/crypto/chacha-neon-glue.c .base.cra_driver_name = "xchacha12-neon", base 162 arch/arm/crypto/chacha-neon-glue.c .base.cra_priority = 300, base 163 arch/arm/crypto/chacha-neon-glue.c .base.cra_blocksize = 1, base 164 arch/arm/crypto/chacha-neon-glue.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 165 arch/arm/crypto/chacha-neon-glue.c .base.cra_module = THIS_MODULE, base 184 arch/arm/crypto/crc32-ce-glue.c .base.cra_ctxsize = sizeof(u32), base 185 arch/arm/crypto/crc32-ce-glue.c .base.cra_init = crc32_cra_init, base 186 arch/arm/crypto/crc32-ce-glue.c .base.cra_name = "crc32", base 187 arch/arm/crypto/crc32-ce-glue.c .base.cra_driver_name = "crc32-arm-ce", base 188 arch/arm/crypto/crc32-ce-glue.c .base.cra_priority = 200, base 189 arch/arm/crypto/crc32-ce-glue.c .base.cra_flags = CRYPTO_ALG_OPTIONAL_KEY, base 190 arch/arm/crypto/crc32-ce-glue.c .base.cra_blocksize = 1, base 191 arch/arm/crypto/crc32-ce-glue.c .base.cra_module = THIS_MODULE, base 200 arch/arm/crypto/crc32-ce-glue.c .base.cra_ctxsize = sizeof(u32), base 201 arch/arm/crypto/crc32-ce-glue.c .base.cra_init = crc32c_cra_init, base 202 arch/arm/crypto/crc32-ce-glue.c .base.cra_name = "crc32c", base 203 arch/arm/crypto/crc32-ce-glue.c .base.cra_driver_name = "crc32c-arm-ce", base 204 arch/arm/crypto/crc32-ce-glue.c .base.cra_priority = 200, base 205 arch/arm/crypto/crc32-ce-glue.c .base.cra_flags = CRYPTO_ALG_OPTIONAL_KEY, base 206 arch/arm/crypto/crc32-ce-glue.c .base.cra_blocksize = 1, base 207 arch/arm/crypto/crc32-ce-glue.c .base.cra_module = THIS_MODULE, base 63 arch/arm/crypto/crct10dif-ce-glue.c .base.cra_name = "crct10dif", base 64 arch/arm/crypto/crct10dif-ce-glue.c .base.cra_driver_name = "crct10dif-arm-ce", base 65 arch/arm/crypto/crct10dif-ce-glue.c .base.cra_priority = 200, base 66 arch/arm/crypto/crct10dif-ce-glue.c .base.cra_blocksize = CRC_T10DIF_BLOCK_SIZE, base 67 arch/arm/crypto/crct10dif-ce-glue.c .base.cra_module = THIS_MODULE, base 196 arch/arm/crypto/ghash-ce-glue.c .base.cra_name = "ghash", base 197 arch/arm/crypto/ghash-ce-glue.c .base.cra_driver_name = "ghash-ce-sync", base 198 arch/arm/crypto/ghash-ce-glue.c .base.cra_priority = 300 - 1, base 199 arch/arm/crypto/ghash-ce-glue.c .base.cra_blocksize = GHASH_BLOCK_SIZE, base 200 arch/arm/crypto/ghash-ce-glue.c .base.cra_ctxsize = sizeof(struct ghash_key), base 201 arch/arm/crypto/ghash-ce-glue.c .base.cra_module = THIS_MODULE, base 227 arch/arm/crypto/ghash-ce-glue.c ahash_request_set_tfm(cryptd_req, &cryptd_tfm->base); base 245 arch/arm/crypto/ghash-ce-glue.c ahash_request_set_tfm(cryptd_req, &cryptd_tfm->base); base 263 arch/arm/crypto/ghash-ce-glue.c ahash_request_set_tfm(cryptd_req, &cryptd_tfm->base); base 298 arch/arm/crypto/ghash-ce-glue.c struct crypto_ahash *child = &ctx->cryptd_tfm->base; base 322 arch/arm/crypto/ghash-ce-glue.c crypto_ahash_reqsize(&cryptd_tfm->base)); base 344 arch/arm/crypto/ghash-ce-glue.c .halg.base = { base 45 arch/arm/crypto/nhpoly1305-neon-glue.c .base.cra_name = "nhpoly1305", base 46 arch/arm/crypto/nhpoly1305-neon-glue.c .base.cra_driver_name = "nhpoly1305-neon", base 47 arch/arm/crypto/nhpoly1305-neon-glue.c .base.cra_priority = 200, base 48 arch/arm/crypto/nhpoly1305-neon-glue.c .base.cra_ctxsize = sizeof(struct nhpoly1305_key), base 49 arch/arm/crypto/nhpoly1305-neon-glue.c .base.cra_module = THIS_MODULE, base 72 arch/arm/crypto/sha1-ce-glue.c .base = { base 61 arch/arm/crypto/sha1_glue.c .base = { base 78 arch/arm/crypto/sha1_neon_glue.c .base = { base 75 arch/arm/crypto/sha2-ce-glue.c .base = { base 89 arch/arm/crypto/sha2-ce-glue.c .base = { base 65 arch/arm/crypto/sha256_glue.c .base = { base 79 arch/arm/crypto/sha256_glue.c .base = { base 74 arch/arm/crypto/sha256_neon_glue.c .base = { base 88 arch/arm/crypto/sha256_neon_glue.c .base = { base 59 arch/arm/crypto/sha512-glue.c .base = { base 73 arch/arm/crypto/sha512-glue.c .base = { base 72 arch/arm/crypto/sha512-neon-glue.c .base = { base 87 arch/arm/crypto/sha512-neon-glue.c .base = { base 50 arch/arm/include/asm/cti.h void __iomem *base; base 67 arch/arm/include/asm/cti.h void __iomem *base, int irq, int trig_out) base 69 arch/arm/include/asm/cti.h cti->base = base; base 87 arch/arm/include/asm/cti.h void __iomem *base = cti->base; base 90 arch/arm/include/asm/cti.h val = __raw_readl(base + CTIINEN + trig_in * 4); base 92 arch/arm/include/asm/cti.h __raw_writel(val, base + CTIINEN + trig_in * 4); base 94 arch/arm/include/asm/cti.h val = __raw_readl(base + CTIOUTEN + trig_out * 4); base 96 arch/arm/include/asm/cti.h __raw_writel(val, base + CTIOUTEN + trig_out * 4); base 107 arch/arm/include/asm/cti.h __raw_writel(0x1, cti->base + CTICONTROL); base 118 arch/arm/include/asm/cti.h __raw_writel(0, cti->base + CTICONTROL); base 129 arch/arm/include/asm/cti.h void __iomem *base = cti->base; base 132 arch/arm/include/asm/cti.h val = __raw_readl(base + CTIINTACK); base 134 arch/arm/include/asm/cti.h __raw_writel(val, base + CTIINTACK); base 146 arch/arm/include/asm/cti.h __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS); base 158 arch/arm/include/asm/cti.h __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS); base 33 arch/arm/include/asm/div64.h static inline uint32_t __div64_32(uint64_t *n, uint32_t base) base 35 arch/arm/include/asm/div64.h register unsigned int __base asm("r4") = base; base 60 arch/arm/include/asm/div64.h #define do_div(n, base) __div64_32(&(n), base) base 10 arch/arm/include/asm/dma-contiguous.h void dma_contiguous_early_fixup(phys_addr_t base, unsigned long size); base 21 arch/arm/include/asm/dma-iommu.h dma_addr_t base; base 28 arch/arm/include/asm/dma-iommu.h arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size); base 147 arch/arm/include/asm/hardware/cache-l2x0.h extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask); base 158 arch/arm/include/asm/hardware/cache-l2x0.h void l2x0_pmu_register(void __iomem *base, u32 part); base 162 arch/arm/include/asm/hardware/cache-l2x0.h static inline void l2x0_pmu_register(void __iomem *base, u32 part) {} base 10 arch/arm/include/asm/tls.h .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2 base 13 arch/arm/include/asm/tls.h .macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2 base 20 arch/arm/include/asm/tls.h .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2 base 32 arch/arm/include/asm/tls.h .macro switch_tls_software, base, tp, tpuser, tmp1, tmp2 base 21 arch/arm/include/asm/vfpmacros.h .macro VFPFLDMIA, base, tmp base 45 arch/arm/include/asm/vfpmacros.h .macro VFPFSTMIA, base, tmp base 184 arch/arm/include/uapi/asm/setup.h #define for_each_tag(t,base) \ base 185 arch/arm/include/uapi/asm/setup.h for (t = base; t->hdr.size; t = tag_next(t)) base 27 arch/arm/kernel/efi.c unsigned long base, size; base 29 arch/arm/kernel/efi.c base = md->virt_addr; base 38 arch/arm/kernel/efi.c if (round_down(base + size, SECTION_SIZE) < base 39 arch/arm/kernel/efi.c round_up(base, SECTION_SIZE) + SECTION_SIZE) base 40 arch/arm/kernel/efi.c return apply_to_page_range(mm, base, size, set_permissions, md); base 96 arch/arm/kernel/fiq.c void *base = vectors_page; base 99 arch/arm/kernel/fiq.c memcpy(base + offset, start, length); base 101 arch/arm/kernel/fiq.c flush_icache_range((unsigned long)base + offset, offset + base 383 arch/arm/kernel/hw_breakpoint.c int i, max_slots, base; base 387 arch/arm/kernel/hw_breakpoint.c base = ARM_BASE_BCR; base 392 arch/arm/kernel/hw_breakpoint.c base = ARM_BASE_WCR; base 416 arch/arm/kernel/hw_breakpoint.c base = ARM_BASE_BCR + core_num_brps; base 420 arch/arm/kernel/hw_breakpoint.c write_wb_reg(base + i, 0); base 33 arch/arm/kernel/module-plts.c return loc - (u32)mod->init_layout.base < mod->init_layout.size; base 90 arch/arm/kernel/module-plts.c static bool is_zero_addend_relocation(Elf32_Addr base, const Elf32_Rel *rel) base 92 arch/arm/kernel/module-plts.c u32 *tval = (u32 *)(base + rel->r_offset); base 118 arch/arm/kernel/module-plts.c static bool duplicate_rel(Elf32_Addr base, const Elf32_Rel *rel, int num) base 132 arch/arm/kernel/module-plts.c is_zero_addend_relocation(base, prev); base 136 arch/arm/kernel/module-plts.c static unsigned int count_plts(const Elf32_Sym *syms, Elf32_Addr base, base 180 arch/arm/kernel/module-plts.c if (!is_zero_addend_relocation(base, rel + i) || base 181 arch/arm/kernel/module-plts.c !duplicate_rel(base, rel, i)) base 17 arch/arm/mach-aspeed/platsmp.c void __iomem *base; base 19 arch/arm/mach-aspeed/platsmp.c base = of_iomap(secboot_node, 0); base 20 arch/arm/mach-aspeed/platsmp.c if (!base) { base 25 arch/arm/mach-aspeed/platsmp.c writel_relaxed(0, base + BOOT_ADDR); base 26 arch/arm/mach-aspeed/platsmp.c writel_relaxed(__pa_symbol(secondary_startup_arm), base + BOOT_ADDR); base 27 arch/arm/mach-aspeed/platsmp.c writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG); base 31 arch/arm/mach-aspeed/platsmp.c iounmap(base); base 38 arch/arm/mach-aspeed/platsmp.c void __iomem *base; base 46 arch/arm/mach-aspeed/platsmp.c base = of_iomap(secboot_node, 0); base 47 arch/arm/mach-aspeed/platsmp.c if (!base) { base 51 arch/arm/mach-aspeed/platsmp.c __raw_writel(0xBADABABA, base + BOOT_SIG); base 53 arch/arm/mach-aspeed/platsmp.c iounmap(base); base 87 arch/arm/mach-bcm/bcm63xx_pmb.c void __iomem **base, base 112 arch/arm/mach-bcm/bcm63xx_pmb.c *base = of_iomap(args.np, 0); base 113 arch/arm/mach-bcm/bcm63xx_pmb.c if (!*base) { base 126 arch/arm/mach-bcm/bcm63xx_pmb.c void __iomem *base; base 132 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bcm63xx_pmb_get_resources(dn, &base, &cpu, &addr); base 145 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_rd(base, addr, ARM_CONTROL, &ctrl); base 156 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_rd(base, addr, ARM_PWR_CONTROL(cpu), &val); base 162 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, base 169 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, base 176 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val); base 183 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val); base 189 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, base 196 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr_rd_mask(base, addr, ARM_PWR_CONTROL(cpu), &val, base 203 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr(base, addr, ARM_PWR_CONTROL(cpu), val); base 210 arch/arm/mach-bcm/bcm63xx_pmb.c ret = bpcm_wr(base, addr, ARM_CONTROL, ctrl); base 213 arch/arm/mach-bcm/bcm63xx_pmb.c iounmap(base); base 32 arch/arm/mach-bcm/board_bcm281xx.c void __iomem *base; base 40 arch/arm/mach-bcm/board_bcm281xx.c base = of_iomap(np_wdog, 0); base 42 arch/arm/mach-bcm/board_bcm281xx.c if (!base) { base 48 arch/arm/mach-bcm/board_bcm281xx.c val = readl(base + SECWDOG_OFFSET); base 53 arch/arm/mach-bcm/board_bcm281xx.c writel(val, base + SECWDOG_OFFSET); base 85 arch/arm/mach-bcm/platsmp-brcmstb.c void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg; base 86 arch/arm/mach-bcm/platsmp-brcmstb.c base += (cpu_logical_map(cpu) * 4); base 87 arch/arm/mach-bcm/platsmp-brcmstb.c return base; base 92 arch/arm/mach-bcm/platsmp-brcmstb.c void __iomem *base = pwr_ctrl_get_base(cpu); base 93 arch/arm/mach-bcm/platsmp-brcmstb.c return readl_relaxed(base); base 98 arch/arm/mach-bcm/platsmp-brcmstb.c void __iomem *base = pwr_ctrl_get_base(cpu); base 99 arch/arm/mach-bcm/platsmp-brcmstb.c writel((readl(base) & mask) | val, base); base 104 arch/arm/mach-bcm/platsmp-brcmstb.c void __iomem *base = pwr_ctrl_get_base(cpu); base 105 arch/arm/mach-bcm/platsmp-brcmstb.c writel((readl(base) & mask) & ~val, base); base 264 arch/arm/mach-cns3xxx/core.c void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); base 267 arch/arm/mach-cns3xxx/core.c if (WARN_ON(!base)) base 279 arch/arm/mach-cns3xxx/core.c val = readl(base + L310_TAG_LATENCY_CTRL); base 281 arch/arm/mach-cns3xxx/core.c writel(val, base + L310_TAG_LATENCY_CTRL); base 292 arch/arm/mach-cns3xxx/core.c val = readl(base + L310_DATA_LATENCY_CTRL); base 294 arch/arm/mach-cns3xxx/core.c writel(val, base + L310_DATA_LATENCY_CTRL); base 297 arch/arm/mach-cns3xxx/core.c l2x0_init(base, 0x00500000, 0xfe0f0fff); base 57 arch/arm/mach-cns3xxx/pcie.c void __iomem *base; base 71 arch/arm/mach-cns3xxx/pcie.c base = cnspci->host_regs; base 77 arch/arm/mach-cns3xxx/pcie.c base = cnspci->cfg0_regs; base 81 arch/arm/mach-cns3xxx/pcie.c base = cnspci->cfg1_regs + ((busno & 0xf) << 20); base 83 arch/arm/mach-cns3xxx/pcie.c return base + where + (devfn << 12); base 215 arch/arm/mach-cns3xxx/pcie.c void __iomem *base = cnspci->host_regs + (where & 0xffc); base 220 arch/arm/mach-cns3xxx/pcie.c v = readl_relaxed(base); base 225 arch/arm/mach-cns3xxx/pcie.c writel_relaxed(v, base); base 226 arch/arm/mach-cns3xxx/pcie.c readl_relaxed(base); base 32 arch/arm/mach-davinci/common.c void __iomem *base; base 34 arch/arm/mach-davinci/common.c base = ioremap(soc_info->jtag_id_reg, SZ_4K); base 35 arch/arm/mach-davinci/common.c if (!base) { base 40 arch/arm/mach-davinci/common.c soc_info->jtag_id = __raw_readl(base); base 41 arch/arm/mach-davinci/common.c iounmap(base); base 671 arch/arm/mach-davinci/da830.c .base = 0, base 599 arch/arm/mach-davinci/da850.c .base = 0, base 313 arch/arm/mach-davinci/devices.c .base = DAVINCI_TIMER0_BASE, base 318 arch/arm/mach-davinci/devices.c .base = DAVINCI_TIMER1_BASE, base 591 arch/arm/mach-davinci/dm355.c .base = 0, base 314 arch/arm/mach-davinci/dm365.c .base = 0, base 525 arch/arm/mach-davinci/dm644x.c .base = 0, base 465 arch/arm/mach-davinci/dm646x.c .base = 0, base 28 arch/arm/mach-davinci/include/mach/common.h u32 base; base 88 arch/arm/mach-davinci/time.c void __iomem *base; base 128 arch/arm/mach-davinci/time.c __raw_writel(__raw_readl(t->base + t->tim_off) + t->period, base 129 arch/arm/mach-davinci/time.c t->base + dtip[event_timer].cmp_off); base 131 arch/arm/mach-davinci/time.c tcr = __raw_readl(t->base + TCR); base 135 arch/arm/mach-davinci/time.c __raw_writel(tcr, t->base + TCR); base 138 arch/arm/mach-davinci/time.c __raw_writel(0, t->base + t->tim_off); base 139 arch/arm/mach-davinci/time.c __raw_writel(t->period, t->base + t->prd_off); base 147 arch/arm/mach-davinci/time.c __raw_writel(tcr, t->base + TCR); base 154 arch/arm/mach-davinci/time.c return __raw_readl(t->base + t->tim_off); base 195 arch/arm/mach-davinci/time.c void __iomem *base[2]; base 202 arch/arm/mach-davinci/time.c base[i] = ioremap(dtip[i].base, SZ_4K); base 203 arch/arm/mach-davinci/time.c if (WARN_ON(!base[i])) base 207 arch/arm/mach-davinci/time.c __raw_writel(0, base[i] + TCR); base 211 arch/arm/mach-davinci/time.c __raw_writel(tgcr, base[i] + TGCR); base 215 arch/arm/mach-davinci/time.c __raw_writel(tgcr, base[i] + TGCR); base 220 arch/arm/mach-davinci/time.c __raw_writel(tgcr, base[i] + TGCR); base 223 arch/arm/mach-davinci/time.c __raw_writel(0, base[i] + TIM12); base 224 arch/arm/mach-davinci/time.c __raw_writel(0, base[i] + TIM34); base 233 arch/arm/mach-davinci/time.c t->base = base[timer]; base 234 arch/arm/mach-davinci/time.c if (!t->base) base 28 arch/arm/mach-dove/pcie.c void __iomem *base; base 52 arch/arm/mach-dove/pcie.c orion_pcie_set_local_bus_nr(pp->base, sys->busnr); base 54 arch/arm/mach-dove/pcie.c orion_pcie_setup(pp->base); base 109 arch/arm/mach-dove/pcie.c ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); base 127 arch/arm/mach-dove/pcie.c ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); base 189 arch/arm/mach-dove/pcie.c static void __init add_pcie_port(int index, void __iomem *base) base 193 arch/arm/mach-dove/pcie.c if (orion_pcie_link_up(base)) { base 204 arch/arm/mach-dove/pcie.c pp->base = base; base 17 arch/arm/mach-ebsa110/include/mach/uncompress.h unsigned char v, *base = SERIAL_BASE; base 20 arch/arm/mach-ebsa110/include/mach/uncompress.h v = base[UART_LSR << 2]; base 24 arch/arm/mach-ebsa110/include/mach/uncompress.h base[UART_TX << 2] = c; base 29 arch/arm/mach-ebsa110/include/mach/uncompress.h unsigned char v, *base = SERIAL_BASE; base 32 arch/arm/mach-ebsa110/include/mach/uncompress.h v = base[UART_LSR << 2]; base 166 arch/arm/mach-ep93xx/core.c void __iomem *base, unsigned int mctrl) base 176 arch/arm/mach-ep93xx/core.c __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); base 30 arch/arm/mach-ep93xx/dma.c { .name = (_name), .base = (_base), .irq = (_irq) } base 485 arch/arm/mach-footbridge/netwinder-hw.c static inline void rwa010_waveartist_init(int base, int irq, int dma) base 492 arch/arm/mach-footbridge/netwinder-hw.c WRITE_RWA(0x61, base & 255); base 495 arch/arm/mach-footbridge/netwinder-hw.c WRITE_RWA(0x60, base >> 8); base 496 arch/arm/mach-footbridge/netwinder-hw.c dprintk("%02X%02X (%X),", inb(0x203), i, base); base 33 arch/arm/mach-highbank/highbank.c unsigned long base; base 36 arch/arm/mach-highbank/highbank.c asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); base 38 arch/arm/mach-highbank/highbank.c scu_base_addr = ioremap(base, SZ_4K); base 41 arch/arm/mach-hisi/platsmp.c unsigned long base = 0; base 45 arch/arm/mach-hisi/platsmp.c base = scu_a9_get_base(); base 46 arch/arm/mach-hisi/platsmp.c scu_base = ioremap(base, SZ_4K); base 149 arch/arm/mach-imx/3ds_debugboard.c int __init mxc_expio_init(u32 base, u32 intr_gpio) base 155 arch/arm/mach-imx/3ds_debugboard.c brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K); base 200 arch/arm/mach-imx/3ds_debugboard.c smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); base 201 arch/arm/mach-imx/3ds_debugboard.c smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1; base 9 arch/arm/mach-imx/3ds_debugboard.h extern int __init mxc_expio_init(u32 base, u32 intr_gpio); base 40 arch/arm/mach-imx/cpu.c void __init imx_set_aips(void __iomem *base) base 47 arch/arm/mach-imx/cpu.c imx_writel(0x77777777, base + 0x0); base 48 arch/arm/mach-imx/cpu.c imx_writel(0x77777777, base + 0x4); base 55 arch/arm/mach-imx/cpu.c imx_writel(0x0, base + 0x40); base 56 arch/arm/mach-imx/cpu.c imx_writel(0x0, base + 0x44); base 57 arch/arm/mach-imx/cpu.c imx_writel(0x0, base + 0x48); base 58 arch/arm/mach-imx/cpu.c imx_writel(0x0, base + 0x4C); base 59 arch/arm/mach-imx/cpu.c reg = imx_readl(base + 0x50) & 0x00FFFFFF; base 60 arch/arm/mach-imx/cpu.c imx_writel(reg, base + 0x50); base 168 arch/arm/mach-imx/iomux-v1.c int __init imx_iomuxv1_init(void __iomem *base, int numports) base 170 arch/arm/mach-imx/iomux-v1.c imx_iomuxv1_baseaddr = base; base 79 arch/arm/mach-imx/iomux-v1.h extern int imx_iomuxv1_init(void __iomem *base, int numports); base 20 arch/arm/mach-imx/iomux-v3.c static void __iomem *base; base 35 arch/arm/mach-imx/iomux-v3.c imx_writel(mux_mode, base + mux_ctrl_ofs); base 38 arch/arm/mach-imx/iomux-v3.c imx_writel(sel_input, base + sel_input_ofs); base 41 arch/arm/mach-imx/iomux-v3.c imx_writel(pad_ctrl, base + pad_ctrl_ofs); base 64 arch/arm/mach-imx/iomux-v3.c base = iomux_v3_base; base 171 arch/arm/mach-imx/mach-mx21ads.c .base = MX21ADS_MMGPIO_BASE, base 243 arch/arm/mach-imx/mach-mx27ads.c vchip->base = MX27ADS_LCD_GPIO; base 100 arch/arm/mach-imx/mach-mx35_3ds.c chip->base + GPIO_MC9S08DZ60_LCD_ENABLE; base 31 arch/arm/mach-imx/platsmp.c unsigned long base; base 34 arch/arm/mach-imx/platsmp.c asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); base 36 arch/arm/mach-imx/platsmp.c scu_io_desc.virtual = IMX_IO_P2V(base); base 37 arch/arm/mach-imx/platsmp.c scu_io_desc.pfn = __phys_to_pfn(base); base 40 arch/arm/mach-imx/platsmp.c scu_base = IMX_IO_ADDRESS(base); base 436 arch/arm/mach-imx/pm-imx6.c static int __init imx6_pm_get_base(struct imx6_pm_base *base, base 451 arch/arm/mach-imx/pm-imx6.c base->pbase = res.start; base 452 arch/arm/mach-imx/pm-imx6.c base->vbase = ioremap(res.start, resource_size(&res)); base 453 arch/arm/mach-imx/pm-imx6.c if (!base->vbase) base 66 arch/arm/mach-imx/system.c void __init mxc_arch_reset_init(void __iomem *base) base 68 arch/arm/mach-imx/system.c wdog_base = base; base 78 arch/arm/mach-imx/system.c void __init imx1_reset_init(void __iomem *base) base 81 arch/arm/mach-imx/system.c mxc_arch_reset_init(base); base 37 arch/arm/mach-integrator/impd1.c void __iomem *base; base 47 arch/arm/mach-integrator/impd1.c cur = readl(impd1->base + IMPD1_CTRL) & ~mask; base 48 arch/arm/mach-integrator/impd1.c writel(cur | val, impd1->base + IMPD1_CTRL); base 341 arch/arm/mach-integrator/impd1.c impd1->base = devm_ioremap(&dev->dev, dev->resource.start, SZ_4K); base 342 arch/arm/mach-integrator/impd1.c if (!impd1->base) base 345 arch/arm/mach-integrator/impd1.c integrator_impd1_clk_init(impd1->base, dev->id); base 108 arch/arm/mach-integrator/integrator_ap.c void __iomem *base, unsigned int mctrl) base 80 arch/arm/mach-mmp/devices.c static unsigned int u2o_get(void __iomem *base, unsigned int offset) base 82 arch/arm/mach-mmp/devices.c return readl_relaxed(base + offset); base 85 arch/arm/mach-mmp/devices.c static void u2o_set(void __iomem *base, unsigned int offset, base 90 arch/arm/mach-mmp/devices.c reg = readl_relaxed(base + offset); base 92 arch/arm/mach-mmp/devices.c writel_relaxed(reg, base + offset); base 93 arch/arm/mach-mmp/devices.c readl_relaxed(base + offset); base 96 arch/arm/mach-mmp/devices.c static void u2o_clear(void __iomem *base, unsigned int offset, base 101 arch/arm/mach-mmp/devices.c reg = readl_relaxed(base + offset); base 103 arch/arm/mach-mmp/devices.c writel_relaxed(reg, base + offset); base 104 arch/arm/mach-mmp/devices.c readl_relaxed(base + offset); base 107 arch/arm/mach-mmp/devices.c static void u2o_write(void __iomem *base, unsigned int offset, base 110 arch/arm/mach-mmp/devices.c writel_relaxed(value, base + offset); base 111 arch/arm/mach-mmp/devices.c readl_relaxed(base + offset); base 118 arch/arm/mach-mmp/devices.c static int usb_phy_init_internal(void __iomem *base) base 126 arch/arm/mach-mmp/devices.c u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT) base 130 arch/arm/mach-mmp/devices.c u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); base 131 arch/arm/mach-mmp/devices.c u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); base 134 arch/arm/mach-mmp/devices.c u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK base 139 arch/arm/mach-mmp/devices.c u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT base 145 arch/arm/mach-mmp/devices.c u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK base 149 arch/arm/mach-mmp/devices.c u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT base 154 arch/arm/mach-mmp/devices.c u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK base 156 arch/arm/mach-mmp/devices.c u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT base 163 arch/arm/mach-mmp/devices.c u2o_write(base, UTMI_IVREF, 0x4bf); base 167 arch/arm/mach-mmp/devices.c u2o_set(base, UTMI_PLL, VCOCAL_START); base 169 arch/arm/mach-mmp/devices.c u2o_clear(base, UTMI_PLL, VCOCAL_START); base 173 arch/arm/mach-mmp/devices.c u2o_set(base, UTMI_TX, REG_RCAL_START); base 175 arch/arm/mach-mmp/devices.c u2o_clear(base, UTMI_TX, REG_RCAL_START); base 180 arch/arm/mach-mmp/devices.c while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) { base 185 arch/arm/mach-mmp/devices.c u2o_get(base, UTMI_PLL)); base 191 arch/arm/mach-mmp/devices.c u2o_set(base, UTMI_RESERVE, 1 << 5); base 193 arch/arm/mach-mmp/devices.c u2o_write(base, UTMI_OTG_ADDON, 1); base 199 arch/arm/mach-mmp/devices.c static int usb_phy_deinit_internal(void __iomem *base) base 204 arch/arm/mach-mmp/devices.c u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON); base 206 arch/arm/mach-mmp/devices.c u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN); base 207 arch/arm/mach-mmp/devices.c u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN); base 208 arch/arm/mach-mmp/devices.c u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN); base 209 arch/arm/mach-mmp/devices.c u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); base 210 arch/arm/mach-mmp/devices.c u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); base 29 arch/arm/mach-mv78xx0/common.h void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, base 31 arch/arm/mach-mv78xx0/common.h void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, base 30 arch/arm/mach-mv78xx0/pcie.c void __iomem *base; base 115 arch/arm/mach-mv78xx0/pcie.c orion_pcie_set_local_bus_nr(pp->base, sys->busnr); base 116 arch/arm/mach-mv78xx0/pcie.c orion_pcie_setup(pp->base); base 151 arch/arm/mach-mv78xx0/pcie.c ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); base 169 arch/arm/mach-mv78xx0/pcie.c ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); base 232 arch/arm/mach-mv78xx0/pcie.c static void __init add_pcie_port(int maj, int min, void __iomem *base) base 236 arch/arm/mach-mv78xx0/pcie.c if (orion_pcie_link_up(base)) { base 244 arch/arm/mach-mv78xx0/pcie.c pp->base = base; base 87 arch/arm/mach-mvebu/board-v7.c u64 base, size; base 89 arch/arm/mach-mvebu/board-v7.c base = dt_mem_next_cell(dt_root_addr_cells, ®); base 92 arch/arm/mach-mvebu/board-v7.c memblock_reserve(base, MVEBU_DDR_TRAINING_AREA_SZ); base 199 arch/arm/mach-mvebu/platsmp.c void __iomem *base; base 206 arch/arm/mach-mvebu/platsmp.c base = of_io_request_and_map(np, 0, of_node_full_name(np)); base 208 arch/arm/mach-mvebu/platsmp.c if (IS_ERR(base)) base 209 arch/arm/mach-mvebu/platsmp.c return PTR_ERR(base); base 211 arch/arm/mach-mvebu/platsmp.c writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG); base 212 arch/arm/mach-mvebu/platsmp.c writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG); base 214 arch/arm/mach-mvebu/platsmp.c iounmap(base); base 32 arch/arm/mach-nspire/nspire.c void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K); base 33 arch/arm/mach-nspire/nspire.c if (!base) base 36 arch/arm/mach-nspire/nspire.c writel(2, base + NSPIRE_MISC_HWRESET); base 183 arch/arm/mach-omap1/board-ams-delta.c .base = -1, base 221 arch/arm/mach-omap1/board-ams-delta.c .base = -1, base 327 arch/arm/mach-omap1/board-h2.c .base = H2_TPS_GPIO_BASE, base 236 arch/arm/mach-omap1/board-osk.c .base = OSK_TPS_GPIO_BASE, base 132 arch/arm/mach-omap1/devices.c static int __init omap_mmc_add(const char *name, int id, unsigned long base, base 146 arch/arm/mach-omap1/devices.c res[0].start = base; base 147 arch/arm/mach-omap1/devices.c res[0].end = base + size - 1; base 190 arch/arm/mach-omap1/devices.c unsigned long base, size; base 201 arch/arm/mach-omap1/devices.c base = OMAP1_MMC1_BASE; base 209 arch/arm/mach-omap1/devices.c base = OMAP1_MMC2_BASE; base 219 arch/arm/mach-omap1/devices.c omap_mmc_add("mmci-omap", i, base, size, irq, base 220 arch/arm/mach-omap1/gpio16xx.c void __iomem *base; base 245 arch/arm/mach-omap1/gpio16xx.c base = ioremap(res->start, resource_size(res)); base 246 arch/arm/mach-omap1/gpio16xx.c if (unlikely(!base)) { base 251 arch/arm/mach-omap1/gpio16xx.c __raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG); base 252 arch/arm/mach-omap1/gpio16xx.c iounmap(base); base 175 arch/arm/mach-omap1/irq.c omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) base 180 arch/arm/mach-omap1/irq.c gc = irq_alloc_generic_chip("MPU", 1, irq_start, base, base 70 arch/arm/mach-omap1/timer.c u32 base, irq; base 74 arch/arm/mach-omap1/timer.c base = OMAP1610_GPTIMER1_BASE; base 78 arch/arm/mach-omap1/timer.c base = OMAP1610_GPTIMER2_BASE; base 82 arch/arm/mach-omap1/timer.c base = OMAP1610_GPTIMER3_BASE; base 86 arch/arm/mach-omap1/timer.c base = OMAP1610_GPTIMER4_BASE; base 90 arch/arm/mach-omap1/timer.c base = OMAP1610_GPTIMER5_BASE; base 94 arch/arm/mach-omap1/timer.c base = OMAP1610_GPTIMER6_BASE; base 98 arch/arm/mach-omap1/timer.c base = OMAP1610_GPTIMER7_BASE; base 102 arch/arm/mach-omap1/timer.c base = OMAP1610_GPTIMER8_BASE; base 121 arch/arm/mach-omap1/timer.c res[0].start = base; base 122 arch/arm/mach-omap1/timer.c res[0].end = base + 0x46; base 176 arch/arm/mach-omap1/timer32k.c void __iomem *base; base 179 arch/arm/mach-omap1/timer32k.c base = ioremap(OMAP1_32KSYNC_TIMER_BASE, SZ_1K); base 180 arch/arm/mach-omap1/timer32k.c if (!base) { base 189 arch/arm/mach-omap1/timer32k.c ret = omap_init_clocksource_32k(base); base 30 arch/arm/mach-omap2/omap-hotplug.c void __iomem *base = omap_get_wakeupgen_base(); base 39 arch/arm/mach-omap2/omap-hotplug.c writel_relaxed(0, base + OMAP_AUX_CORE_BOOT_0); base 53 arch/arm/mach-omap2/omap-hotplug.c readl_relaxed(base + OMAP_AUX_CORE_BOOT_0) >> 5; base 2248 arch/arm/mach-omap2/omap_hwmod.c u64 base, size; base 2285 arch/arm/mach-omap2/omap_hwmod.c base = of_translate_address(np, ranges++); base 2289 arch/arm/mach-omap2/omap_hwmod.c oh->name, np, base, size); base 2297 arch/arm/mach-omap2/omap_hwmod.c res->start = base; base 2298 arch/arm/mach-omap2/omap_hwmod.c res->end = base + size - 1; base 613 arch/arm/mach-omap2/timer.c void __iomem *base; base 619 arch/arm/mach-omap2/timer.c base = ioremap(REALTIME_COUNTER_BASE, SZ_32); base 620 arch/arm/mach-omap2/timer.c if (!base) { base 627 arch/arm/mach-omap2/timer.c iounmap(base); base 697 arch/arm/mach-omap2/timer.c reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & base 700 arch/arm/mach-omap2/timer.c writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); base 702 arch/arm/mach-omap2/timer.c reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & base 705 arch/arm/mach-omap2/timer.c writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); base 710 arch/arm/mach-omap2/timer.c iounmap(base); base 33 arch/arm/mach-omap2/wd_timer.c void __iomem *base; base 40 arch/arm/mach-omap2/wd_timer.c base = omap_hwmod_get_mpu_rt_va(oh); base 41 arch/arm/mach-omap2/wd_timer.c if (!base) { base 48 arch/arm/mach-omap2/wd_timer.c writel_relaxed(0xAAAA, base + OMAP_WDT_SPR); base 49 arch/arm/mach-omap2/wd_timer.c while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10) base 52 arch/arm/mach-omap2/wd_timer.c writel_relaxed(0x5555, base + OMAP_WDT_SPR); base 53 arch/arm/mach-omap2/wd_timer.c while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10) base 436 arch/arm/mach-orion5x/pci.c val = (cs->base & 0xfffff000) | (val & 0xfff); base 446 arch/arm/mach-orion5x/pci.c writel(cs->base & 0xfffff000, base 66 arch/arm/mach-pxa/irq.c void __iomem *base = irq_data_get_irq_chip_data(d); base 68 arch/arm/mach-pxa/irq.c uint32_t icmr = __raw_readl(base + ICMR); base 71 arch/arm/mach-pxa/irq.c __raw_writel(icmr, base + ICMR); base 76 arch/arm/mach-pxa/irq.c void __iomem *base = irq_data_get_irq_chip_data(d); base 78 arch/arm/mach-pxa/irq.c uint32_t icmr = __raw_readl(base + ICMR); base 81 arch/arm/mach-pxa/irq.c __raw_writel(icmr, base + ICMR); base 124 arch/arm/mach-pxa/irq.c void __iomem *base = irq_base(hw / 32); base 132 arch/arm/mach-pxa/irq.c irq_set_chip_data(virq, base); base 157 arch/arm/mach-pxa/irq.c void __iomem *base = irq_base(n >> 5); base 159 arch/arm/mach-pxa/irq.c __raw_writel(0, base + ICMR); /* disable all IRQs */ base 160 arch/arm/mach-pxa/irq.c __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ base 186 arch/arm/mach-pxa/irq.c void __iomem *base = irq_base(i); base 188 arch/arm/mach-pxa/irq.c saved_icmr[i] = __raw_readl(base + ICMR); base 189 arch/arm/mach-pxa/irq.c __raw_writel(0, base + ICMR); base 205 arch/arm/mach-pxa/irq.c void __iomem *base = irq_base(i); base 207 arch/arm/mach-pxa/irq.c __raw_writel(saved_icmr[i], base + ICMR); base 208 arch/arm/mach-pxa/irq.c __raw_writel(0, base + ICLR); base 137 arch/arm/mach-pxa/pcm027.c .base = -1, base 27 arch/arm/mach-pxa/pxa_cplds_irqs.c void __iomem *base; base 41 arch/arm/mach-pxa/pxa_cplds_irqs.c pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask; base 58 arch/arm/mach-pxa/pxa_cplds_irqs.c writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); base 67 arch/arm/mach-pxa/pxa_cplds_irqs.c set = readl(fpga->base + FPGA_IRQ_SET_CLR); base 68 arch/arm/mach-pxa/pxa_cplds_irqs.c writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR); base 71 arch/arm/mach-pxa/pxa_cplds_irqs.c writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); base 102 arch/arm/mach-pxa/pxa_cplds_irqs.c writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); base 128 arch/arm/mach-pxa/pxa_cplds_irqs.c fpga->base = devm_ioremap_resource(&pdev->dev, res); base 129 arch/arm/mach-pxa/pxa_cplds_irqs.c if (IS_ERR(fpga->base)) base 130 arch/arm/mach-pxa/pxa_cplds_irqs.c return PTR_ERR(fpga->base); base 134 arch/arm/mach-pxa/pxa_cplds_irqs.c writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); base 135 arch/arm/mach-pxa/pxa_cplds_irqs.c writel(0, fpga->base + FPGA_IRQ_SET_CLR); base 56 arch/arm/mach-qcom/platsmp.c void __iomem *base; base 64 arch/arm/mach-qcom/platsmp.c base = of_iomap(node, 0); base 66 arch/arm/mach-qcom/platsmp.c if (!base) base 69 arch/arm/mach-qcom/platsmp.c writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL); base 70 arch/arm/mach-qcom/platsmp.c writel_relaxed(0, base + SCSS_CPU1CORE_RESET); base 71 arch/arm/mach-qcom/platsmp.c writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP); base 73 arch/arm/mach-qcom/platsmp.c iounmap(base); base 27 arch/arm/mach-rpc/dma.c void __iomem *base; /* Controller base address */ base 98 arch/arm/mach-rpc/dma.c void __iomem *base = idma->base; base 103 arch/arm/mach-rpc/dma.c status = readb(base + ST); base 119 arch/arm/mach-rpc/dma.c writel(idma->cur_addr, base + cur); base 120 arch/arm/mach-rpc/dma.c writel(idma->cur_len, base + end); base 158 arch/arm/mach-rpc/dma.c void __iomem *base = idma->base; base 181 arch/arm/mach-rpc/dma.c writeb(DMA_CR_C, base + CR); base 188 arch/arm/mach-rpc/dma.c writeb(ctrl, base + CR); base 195 arch/arm/mach-rpc/dma.c void __iomem *base = idma->base; base 201 arch/arm/mach-rpc/dma.c writeb(0, base + CR); base 364 arch/arm/mach-rpc/dma.c iomd_dma[DMA_0].base = IOMD_BASE + IOMD_IO0CURA; base 366 arch/arm/mach-rpc/dma.c iomd_dma[DMA_1].base = IOMD_BASE + IOMD_IO1CURA; base 368 arch/arm/mach-rpc/dma.c iomd_dma[DMA_2].base = IOMD_BASE + IOMD_IO2CURA; base 370 arch/arm/mach-rpc/dma.c iomd_dma[DMA_3].base = IOMD_BASE + IOMD_IO3CURA; base 372 arch/arm/mach-rpc/dma.c iomd_dma[DMA_S0].base = IOMD_BASE + IOMD_SD0CURA; base 374 arch/arm/mach-rpc/dma.c iomd_dma[DMA_S1].base = IOMD_BASE + IOMD_SD1CURA; base 88 arch/arm/mach-rpc/ecard.c ecard_loader_reset(unsigned long base, loader_t loader); base 90 arch/arm/mach-rpc/ecard.c ecard_loader_read(int off, unsigned long base, loader_t loader); base 141 arch/arm/mach-rpc/ecard.c void __iomem *base = (void __iomem *) base 163 arch/arm/mach-rpc/ecard.c writeb(0, base); base 172 arch/arm/mach-rpc/ecard.c readb(base + page); base 177 arch/arm/mach-rpc/ecard.c *buf++ = readb(base + page); base 181 arch/arm/mach-rpc/ecard.c unsigned long base = (ec->easi base 184 arch/arm/mach-rpc/ecard.c void __iomem *pbase = (void __iomem *)base; base 199 arch/arm/mach-rpc/ecard.c *buf++ = ecard_loader_read(off++, base, base 692 arch/arm/mach-rpc/ecard.c unsigned long base; base 719 arch/arm/mach-rpc/ecard.c base = PODSLOT_IOC0_BASE + (slot << 14); base 721 arch/arm/mach-rpc/ecard.c base = PODSLOT_IOC4_BASE + ((slot - 4) << 14); base 737 arch/arm/mach-rpc/ecard.c base + (i << 19), PODSLOT_IOC_SIZE); base 24 arch/arm/mach-rpc/irq.c static void iomd_set_base_mask(unsigned int irq, void __iomem *base, u32 mask) base 29 arch/arm/mach-rpc/irq.c irq_set_chip_data(irq, (void *)(unsigned long)base); base 34 arch/arm/mach-rpc/irq.c void __iomem *base = iomd_get_base(d); base 37 arch/arm/mach-rpc/irq.c val = readb(base + MASK); base 38 arch/arm/mach-rpc/irq.c writeb(val & ~mask, base + MASK); base 39 arch/arm/mach-rpc/irq.c writeb(mask, base + CLR); base 44 arch/arm/mach-rpc/irq.c void __iomem *base = iomd_get_base(d); base 47 arch/arm/mach-rpc/irq.c val = readb(base + MASK); base 48 arch/arm/mach-rpc/irq.c writeb(val & ~mask, base + MASK); base 53 arch/arm/mach-rpc/irq.c void __iomem *base = iomd_get_base(d); base 56 arch/arm/mach-rpc/irq.c val = readb(base + MASK); base 57 arch/arm/mach-rpc/irq.c writeb(val | mask, base + MASK); base 161 arch/arm/mach-s3c24xx/mach-h1940.c .base = H1940_LATCH_GPIO(0), base 325 arch/arm/mach-s3c24xx/mach-osiris.c .base = -1, /* GPIO can go anywhere at the moment */ base 39 arch/arm/mach-s3c24xx/pm-s3c2410.c void *base = phys_to_virt(H1940_SUSPEND_CHECK); base 46 arch/arm/mach-s3c24xx/pm-s3c2410.c calc += __raw_readl(base+ptr); base 55 arch/arm/mach-s3c24xx/pm-s3c2410.c void *base = phys_to_virt(H1940_SUSPEND_CHECK); base 62 arch/arm/mach-s3c24xx/pm-s3c2410.c calc += __raw_readl(base+ptr); base 24 arch/arm/mach-s3c64xx/dev-audio.c unsigned int base; base 28 arch/arm/mach-s3c64xx/dev-audio.c base = S3C64XX_GPD(0); base 31 arch/arm/mach-s3c64xx/dev-audio.c base = S3C64XX_GPE(0); base 45 arch/arm/mach-s3c64xx/dev-audio.c s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3)); base 115 arch/arm/mach-s3c64xx/dev-audio.c unsigned int base; base 119 arch/arm/mach-s3c64xx/dev-audio.c base = S3C64XX_GPD(0); base 122 arch/arm/mach-s3c64xx/dev-audio.c base = S3C64XX_GPE(0); base 130 arch/arm/mach-s3c64xx/dev-audio.c s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2)); base 266 arch/arm/mach-s3c64xx/mach-crag6410.c .base = MMGPIO_GPIO_BASE, base 14 arch/arm/mach-s3c64xx/watchdog-reset.h extern void samsung_wdt_reset_init(void __iomem *base); base 102 arch/arm/mach-sa1100/assabet.c return gc->base; base 77 arch/arm/mach-sa1100/neponset.c void __iomem *base; base 157 arch/arm/mach-sa1100/neponset.c irr = readb_relaxed(d->base + IRR); base 285 arch/arm/mach-sa1100/neponset.c d->base = ioremap(nep_res->start, SZ_4K); base 286 arch/arm/mach-sa1100/neponset.c if (!d->base) { base 291 arch/arm/mach-sa1100/neponset.c if (readb_relaxed(d->base + WHOAMI) != 0x11) { base 293 arch/arm/mach-sa1100/neponset.c readb_relaxed(d->base + WHOAMI)); base 321 arch/arm/mach-sa1100/neponset.c writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0); base 324 arch/arm/mach-sa1100/neponset.c d->base + NCR_0, NCR_NGPIO, false, base 327 arch/arm/mach-sa1100/neponset.c d->base + MDM_CTL_0, MDM_CTL0_NGPIO, false, base 330 arch/arm/mach-sa1100/neponset.c d->base + MDM_CTL_1, MDM_CTL1_NGPIO, true, base 333 arch/arm/mach-sa1100/neponset.c d->base + AUD_CTL, AUD_NGPIO, false, base 372 arch/arm/mach-sa1100/neponset.c iounmap(d->base); base 396 arch/arm/mach-sa1100/neponset.c iounmap(d->base); base 385 arch/arm/mach-sa1100/simpad.c cs3_gpio.base = SIMPAD_CS3_GPIO_BASE; base 25 arch/arm/mach-shmobile/setup-r8a7778.c void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); base 27 arch/arm/mach-shmobile/setup-r8a7778.c BUG_ON(!base); base 32 arch/arm/mach-shmobile/setup-r8a7778.c __raw_writel(0x73ffffff, base + INT2NTSR0); base 33 arch/arm/mach-shmobile/setup-r8a7778.c __raw_writel(0xffffffff, base + INT2NTSR1); base 36 arch/arm/mach-shmobile/setup-r8a7778.c __raw_writel(0x08330773, base + INT2SMSKCR0); base 37 arch/arm/mach-shmobile/setup-r8a7778.c __raw_writel(0x00311110, base + INT2SMSKCR1); base 39 arch/arm/mach-shmobile/setup-r8a7778.c iounmap(base); base 65 arch/arm/mach-shmobile/setup-rcar-gen2.c void __iomem *base; base 100 arch/arm/mach-shmobile/setup-rcar-gen2.c base = ioremap(0xe6080000, PAGE_SIZE); base 109 arch/arm/mach-shmobile/setup-rcar-gen2.c if ((ioread32(base + CNTCR) & 1) == 0 || base 110 arch/arm/mach-shmobile/setup-rcar-gen2.c ioread32(base + CNTFID0) != freq) { base 112 arch/arm/mach-shmobile/setup-rcar-gen2.c iowrite32(freq, base + CNTFID0); base 116 arch/arm/mach-shmobile/setup-rcar-gen2.c iowrite32(1, base + CNTCR); base 119 arch/arm/mach-shmobile/setup-rcar-gen2.c iounmap(base); base 128 arch/arm/mach-shmobile/setup-rcar-gen2.c u64 base, size; base 152 arch/arm/mach-shmobile/setup-rcar-gen2.c u64 base, size; base 154 arch/arm/mach-shmobile/setup-rcar-gen2.c base = dt_mem_next_cell(dt_root_addr_cells, ®); base 157 arch/arm/mach-shmobile/setup-rcar-gen2.c if (base >= lpae_start) base 160 arch/arm/mach-shmobile/setup-rcar-gen2.c if ((base + size) >= lpae_start) base 161 arch/arm/mach-shmobile/setup-rcar-gen2.c size = lpae_start - base; base 166 arch/arm/mach-shmobile/setup-rcar-gen2.c if (base < mrc->base) base 170 arch/arm/mach-shmobile/setup-rcar-gen2.c mrc->base = base + size - mrc->reserved; base 187 arch/arm/mach-shmobile/setup-rcar-gen2.c if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) { base 190 arch/arm/mach-shmobile/setup-rcar-gen2.c dma_contiguous_reserve_area(mrc.size, mrc.base, 0, base 25 arch/arm/mach-spear/include/mach/uncompress.h void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE; base 27 arch/arm/mach-spear/include/mach/uncompress.h while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF) base 30 arch/arm/mach-spear/include/mach/uncompress.h writel_relaxed(c, base + UART01x_DR); base 43 arch/arm/mach-tegra/sleep.h .macro wait_until, rn, base, tmp base 109 arch/arm/mach-tegra/sleep.h .macro tegra_get_soc_id base, tmp1 base 11 arch/arm/mach-vexpress/spc.h int __init ve_spc_init(void __iomem *base, u32 a15_clusid, int irq); base 44 arch/arm/mach-zx/platsmp.c unsigned long base = 0; base 48 arch/arm/mach-zx/platsmp.c base = scu_a9_get_base(); base 49 arch/arm/mach-zx/platsmp.c scu_base = ioremap(base, SZ_256); base 156 arch/arm/mach-zynq/common.c unsigned long base; base 158 arch/arm/mach-zynq/common.c base = scu_a9_get_base(); base 159 arch/arm/mach-zynq/common.c zynq_cortex_a9_scu_map.pfn = __phys_to_pfn(base); base 161 arch/arm/mach-zynq/common.c zynq_cortex_a9_scu_map.virtual = base; base 163 arch/arm/mach-zynq/common.c zynq_scu_base = (void __iomem *)base; base 35 arch/arm/mach-zynq/pm.c void __iomem *base = NULL; base 39 arch/arm/mach-zynq/pm.c base = of_iomap(np, 0); base 46 arch/arm/mach-zynq/pm.c return base; base 369 arch/arm/mm/cache-feroceon-l2.c void __iomem *base; base 378 arch/arm/mm/cache-feroceon-l2.c base = of_iomap(node, 0); base 379 arch/arm/mm/cache-feroceon-l2.c if (!base) base 383 arch/arm/mm/cache-feroceon-l2.c writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base); base 385 arch/arm/mm/cache-feroceon-l2.c writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base); base 474 arch/arm/mm/cache-l2x0-pmu.c void __init l2x0_pmu_register(void __iomem *base, u32 part) base 500 arch/arm/mm/cache-l2x0-pmu.c l2x0_base = base; base 65 arch/arm/mm/cache-l2x0.c static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) base 67 arch/arm/mm/cache-l2x0.c if (val == readl_relaxed(base + reg)) base 72 arch/arm/mm/cache-l2x0.c writel_relaxed(val, base + reg); base 80 arch/arm/mm/cache-l2x0.c static inline void l2c_set_debug(void __iomem *base, unsigned long val) base 82 arch/arm/mm/cache-l2x0.c l2c_write_sec(val, base, L2X0_DEBUG_CTRL); base 91 arch/arm/mm/cache-l2x0.c static inline void l2c_unlock(void __iomem *base, unsigned num) base 96 arch/arm/mm/cache-l2x0.c writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + base 98 arch/arm/mm/cache-l2x0.c writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + base 103 arch/arm/mm/cache-l2x0.c static void l2c_configure(void __iomem *base) base 105 arch/arm/mm/cache-l2x0.c l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL); base 112 arch/arm/mm/cache-l2x0.c static void l2c_enable(void __iomem *base, unsigned num_lock) base 119 arch/arm/mm/cache-l2x0.c l2x0_data->configure(base); base 121 arch/arm/mm/cache-l2x0.c l2x0_data->unlock(base, num_lock); base 124 arch/arm/mm/cache-l2x0.c __l2c_op_way(base + L2X0_INV_WAY); base 125 arch/arm/mm/cache-l2x0.c writel_relaxed(0, base + sync_reg_offset); base 126 arch/arm/mm/cache-l2x0.c l2c_wait_mask(base + sync_reg_offset, 1); base 129 arch/arm/mm/cache-l2x0.c l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL); base 134 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 139 arch/arm/mm/cache-l2x0.c l2c_write_sec(0, base, L2X0_CTRL); base 143 arch/arm/mm/cache-l2x0.c static void l2c_save(void __iomem *base) base 150 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 153 arch/arm/mm/cache-l2x0.c if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) base 154 arch/arm/mm/cache-l2x0.c l2c_enable(base, l2x0_data->num_lock); base 173 arch/arm/mm/cache-l2x0.c static void __l2c210_cache_sync(void __iomem *base) base 175 arch/arm/mm/cache-l2x0.c writel_relaxed(0, base + sync_reg_offset); base 189 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 193 arch/arm/mm/cache-l2x0.c writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); base 199 arch/arm/mm/cache-l2x0.c writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); base 202 arch/arm/mm/cache-l2x0.c __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); base 203 arch/arm/mm/cache-l2x0.c __l2c210_cache_sync(base); base 208 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 211 arch/arm/mm/cache-l2x0.c __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end); base 212 arch/arm/mm/cache-l2x0.c __l2c210_cache_sync(base); base 217 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 220 arch/arm/mm/cache-l2x0.c __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end); base 221 arch/arm/mm/cache-l2x0.c __l2c210_cache_sync(base); base 226 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 230 arch/arm/mm/cache-l2x0.c __l2c_op_way(base + L2X0_CLEAN_INV_WAY); base 231 arch/arm/mm/cache-l2x0.c __l2c210_cache_sync(base); base 268 arch/arm/mm/cache-l2x0.c static inline void __l2c220_cache_sync(void __iomem *base) base 270 arch/arm/mm/cache-l2x0.c writel_relaxed(0, base + L2X0_CACHE_SYNC); base 271 arch/arm/mm/cache-l2x0.c l2c_wait_mask(base + L2X0_CACHE_SYNC, 1); base 274 arch/arm/mm/cache-l2x0.c static void l2c220_op_way(void __iomem *base, unsigned reg) base 279 arch/arm/mm/cache-l2x0.c __l2c_op_way(base + reg); base 280 arch/arm/mm/cache-l2x0.c __l2c220_cache_sync(base); base 309 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 316 arch/arm/mm/cache-l2x0.c writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); base 322 arch/arm/mm/cache-l2x0.c l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); base 323 arch/arm/mm/cache-l2x0.c writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); base 327 arch/arm/mm/cache-l2x0.c flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA, base 329 arch/arm/mm/cache-l2x0.c l2c_wait_mask(base + L2X0_INV_LINE_PA, 1); base 330 arch/arm/mm/cache-l2x0.c __l2c220_cache_sync(base); base 336 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 341 arch/arm/mm/cache-l2x0.c l2c220_op_way(base, L2X0_CLEAN_WAY); base 346 arch/arm/mm/cache-l2x0.c flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA, base 348 arch/arm/mm/cache-l2x0.c l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); base 349 arch/arm/mm/cache-l2x0.c __l2c220_cache_sync(base); base 355 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 360 arch/arm/mm/cache-l2x0.c l2c220_op_way(base, L2X0_CLEAN_INV_WAY); base 365 arch/arm/mm/cache-l2x0.c flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, base 367 arch/arm/mm/cache-l2x0.c l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); base 368 arch/arm/mm/cache-l2x0.c __l2c220_cache_sync(base); base 386 arch/arm/mm/cache-l2x0.c static void l2c220_enable(void __iomem *base, unsigned num_lock) base 395 arch/arm/mm/cache-l2x0.c l2c_enable(base, num_lock); base 398 arch/arm/mm/cache-l2x0.c static void l2c220_unlock(void __iomem *base, unsigned num_lock) base 400 arch/arm/mm/cache-l2x0.c if (readl_relaxed(base + L2X0_AUX_CTRL) & L220_AUX_CTRL_NS_LOCKDOWN) base 401 arch/arm/mm/cache-l2x0.c l2c_unlock(base, num_lock); base 469 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 476 arch/arm/mm/cache-l2x0.c l2c_set_debug(base, 0x03); base 480 arch/arm/mm/cache-l2x0.c writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); base 481 arch/arm/mm/cache-l2x0.c writel_relaxed(start, base + L2X0_INV_LINE_PA); base 487 arch/arm/mm/cache-l2x0.c writel_relaxed(end, base + L2X0_CLEAN_LINE_PA); base 488 arch/arm/mm/cache-l2x0.c writel_relaxed(end, base + L2X0_INV_LINE_PA); base 491 arch/arm/mm/cache-l2x0.c l2c_set_debug(base, 0x00); base 495 arch/arm/mm/cache-l2x0.c __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); base 496 arch/arm/mm/cache-l2x0.c __l2c210_cache_sync(base); base 503 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 509 arch/arm/mm/cache-l2x0.c l2c_set_debug(base, 0x03); base 511 arch/arm/mm/cache-l2x0.c writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); base 512 arch/arm/mm/cache-l2x0.c writel_relaxed(start, base + L2X0_INV_LINE_PA); base 515 arch/arm/mm/cache-l2x0.c l2c_set_debug(base, 0x00); base 523 arch/arm/mm/cache-l2x0.c __l2c210_cache_sync(base); base 528 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 532 arch/arm/mm/cache-l2x0.c l2c_set_debug(base, 0x03); base 533 arch/arm/mm/cache-l2x0.c __l2c_op_way(base + L2X0_CLEAN_INV_WAY); base 534 arch/arm/mm/cache-l2x0.c l2c_set_debug(base, 0x00); base 535 arch/arm/mm/cache-l2x0.c __l2c210_cache_sync(base); base 539 arch/arm/mm/cache-l2x0.c static void __init l2c310_save(void __iomem *base) base 543 arch/arm/mm/cache-l2x0.c l2c_save(base); base 545 arch/arm/mm/cache-l2x0.c l2x0_saved_regs.tag_latency = readl_relaxed(base + base 547 arch/arm/mm/cache-l2x0.c l2x0_saved_regs.data_latency = readl_relaxed(base + base 549 arch/arm/mm/cache-l2x0.c l2x0_saved_regs.filter_end = readl_relaxed(base + base 551 arch/arm/mm/cache-l2x0.c l2x0_saved_regs.filter_start = readl_relaxed(base + base 554 arch/arm/mm/cache-l2x0.c revision = readl_relaxed(base + L2X0_CACHE_ID) & base 559 arch/arm/mm/cache-l2x0.c l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + base 564 arch/arm/mm/cache-l2x0.c l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + base 568 arch/arm/mm/cache-l2x0.c static void l2c310_configure(void __iomem *base) base 572 arch/arm/mm/cache-l2x0.c l2c_configure(base); base 575 arch/arm/mm/cache-l2x0.c l2c_write_sec(l2x0_saved_regs.tag_latency, base, base 577 arch/arm/mm/cache-l2x0.c l2c_write_sec(l2x0_saved_regs.data_latency, base, base 579 arch/arm/mm/cache-l2x0.c l2c_write_sec(l2x0_saved_regs.filter_end, base, base 581 arch/arm/mm/cache-l2x0.c l2c_write_sec(l2x0_saved_regs.filter_start, base, base 584 arch/arm/mm/cache-l2x0.c revision = readl_relaxed(base + L2X0_CACHE_ID) & base 588 arch/arm/mm/cache-l2x0.c l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base, base 591 arch/arm/mm/cache-l2x0.c l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base, base 607 arch/arm/mm/cache-l2x0.c static void __init l2c310_enable(void __iomem *base, unsigned num_lock) base 609 arch/arm/mm/cache-l2x0.c unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK; base 624 arch/arm/mm/cache-l2x0.c u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL); base 651 arch/arm/mm/cache-l2x0.c l2c_enable(base, num_lock); base 654 arch/arm/mm/cache-l2x0.c aux = readl_relaxed(base + L2X0_AUX_CTRL); base 657 arch/arm/mm/cache-l2x0.c u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL); base 669 arch/arm/mm/cache-l2x0.c power_ctrl = readl_relaxed(base + L310_POWER_CTRL); base 681 arch/arm/mm/cache-l2x0.c static void __init l2c310_fixup(void __iomem *base, u32 cache_id, base 754 arch/arm/mm/cache-l2x0.c static void l2c310_unlock(void __iomem *base, unsigned num_lock) base 756 arch/arm/mm/cache-l2x0.c if (readl_relaxed(base + L2X0_AUX_CTRL) & L310_AUX_CTRL_NS_LOCKDOWN) base 757 arch/arm/mm/cache-l2x0.c l2c_unlock(base, num_lock); base 894 arch/arm/mm/cache-l2x0.c void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) base 899 arch/arm/mm/cache-l2x0.c l2x0_base = base; base 901 arch/arm/mm/cache-l2x0.c cache_id = readl_relaxed(base + L2X0_CACHE_ID); base 1370 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 1387 arch/arm/mm/cache-l2x0.c writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG); base 1388 arch/arm/mm/cache-l2x0.c writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset); base 1391 arch/arm/mm/cache-l2x0.c writel_relaxed(0, base + AURORA_SYNC_REG); base 1420 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 1425 arch/arm/mm/cache-l2x0.c __l2c_op_way(base + L2X0_CLEAN_INV_WAY); base 1428 arch/arm/mm/cache-l2x0.c writel_relaxed(0, base + AURORA_SYNC_REG); base 1438 arch/arm/mm/cache-l2x0.c void __iomem *base = l2x0_base; base 1442 arch/arm/mm/cache-l2x0.c __l2c_op_way(base + L2X0_CLEAN_INV_WAY); base 1443 arch/arm/mm/cache-l2x0.c writel_relaxed(0, base + AURORA_SYNC_REG); base 1444 arch/arm/mm/cache-l2x0.c l2c_write_sec(0, base, L2X0_CTRL); base 1449 arch/arm/mm/cache-l2x0.c static void aurora_save(void __iomem *base) base 1451 arch/arm/mm/cache-l2x0.c l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); base 1452 arch/arm/mm/cache-l2x0.c l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL); base 1459 arch/arm/mm/cache-l2x0.c static void __init aurora_enable_no_outer(void __iomem *base, base 1470 arch/arm/mm/cache-l2x0.c l2c_enable(base, num_lock); base 1473 arch/arm/mm/cache-l2x0.c static void __init aurora_fixup(void __iomem *base, u32 cache_id, base 1706 arch/arm/mm/cache-l2x0.c static void __init tauros3_save(void __iomem *base) base 1708 arch/arm/mm/cache-l2x0.c l2c_save(base); base 1711 arch/arm/mm/cache-l2x0.c readl_relaxed(base + TAUROS3_AUX2_CTRL); base 1713 arch/arm/mm/cache-l2x0.c readl_relaxed(base + L310_PREFETCH_CTRL); base 1716 arch/arm/mm/cache-l2x0.c static void tauros3_configure(void __iomem *base) base 1718 arch/arm/mm/cache-l2x0.c l2c_configure(base); base 1720 arch/arm/mm/cache-l2x0.c base + TAUROS3_AUX2_CTRL); base 1722 arch/arm/mm/cache-l2x0.c base + L310_PREFETCH_CTRL); base 272 arch/arm/mm/dma-mapping.c phys_addr_t base = __pfn_to_phys(page_to_pfn(page)); base 273 arch/arm/mm/dma-mapping.c phys_addr_t end = base + size; base 284 arch/arm/mm/dma-mapping.c outer_flush_range(base, end); base 410 arch/arm/mm/dma-mapping.c phys_addr_t base; base 418 arch/arm/mm/dma-mapping.c void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) base 420 arch/arm/mm/dma-mapping.c dma_mmu_remap[dma_mmu_remap_num].base = base; base 429 arch/arm/mm/dma-mapping.c phys_addr_t start = dma_mmu_remap[i].base; base 1192 arch/arm/mm/dma-mapping.c iova = mapping->base + (mapping_size * i); base 1210 arch/arm/mm/dma-mapping.c bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size; base 1211 arch/arm/mm/dma-mapping.c BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions); base 1213 arch/arm/mm/dma-mapping.c bitmap_base = mapping->base + mapping_size * bitmap_index; base 2072 arch/arm/mm/dma-mapping.c arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size) base 2108 arch/arm/mm/dma-mapping.c mapping->base = base; base 1186 arch/arm/mm/mmu.c if (!IS_ALIGNED(reg->base, PMD_SIZE)) { base 1189 arch/arm/mm/mmu.c len = round_up(reg->base, PMD_SIZE) - reg->base; base 1190 arch/arm/mm/mmu.c memblock_mark_nomap(reg->base, len); base 1197 arch/arm/mm/mmu.c phys_addr_t block_start = reg->base; base 1198 arch/arm/mm/mmu.c phys_addr_t block_end = reg->base + reg->size; base 1203 arch/arm/mm/mmu.c if (reg->base < vmalloc_limit) { base 1288 arch/arm/mm/mmu.c end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; base 1458 arch/arm/mm/mmu.c phys_addr_t start = reg->base; base 64 arch/arm/mm/nommu.c unsigned long base = 0, reg = get_cr(); base 69 arch/arm/mm/nommu.c base = CONFIG_DRAM_BASE; base 70 arch/arm/mm/nommu.c set_vbar(base); base 76 arch/arm/mm/nommu.c return base; base 20 arch/arm/mm/pmsa-v7.c phys_addr_t base; base 146 arch/arm/mm/pmsa-v7.c static bool __init try_split_region(phys_addr_t base, phys_addr_t size, struct region *region) base 149 arch/arm/mm/pmsa-v7.c phys_addr_t abase = base & ~(size - 1); base 150 arch/arm/mm/pmsa-v7.c phys_addr_t asize = base + size - abase; base 157 arch/arm/mm/pmsa-v7.c bdiff = base - abase; base 183 arch/arm/mm/pmsa-v7.c region->base = abase; base 189 arch/arm/mm/pmsa-v7.c static int __init allocate_region(phys_addr_t base, phys_addr_t size, base 198 arch/arm/mm/pmsa-v7.c if (try_split_region(base, size, ®ions[count])) { base 200 arch/arm/mm/pmsa-v7.c base += size; base 212 arch/arm/mm/pmsa-v7.c phys_addr_t asize = (base - 1) ^ base; base 272 arch/arm/mm/pmsa-v7.c if (reg->base != phys_offset) base 275 arch/arm/mm/pmsa-v7.c mem_start = reg->base; base 276 arch/arm/mm/pmsa-v7.c mem_end = reg->base + reg->size; base 286 arch/arm/mm/pmsa-v7.c &mem_end, ®->base); base 287 arch/arm/mm/pmsa-v7.c memblock_remove(reg->base, 0 - reg->base); base 301 arch/arm/mm/pmsa-v7.c &mem[i].base, &mem[i].size, PMSAv7_NR_SUBREGS, &mem[i].subreg); base 445 arch/arm/mm/pmsa-v7.c err |= mpu_setup_region(region++, xip[i].base, ilog2(xip[i].size), base 456 arch/arm/mm/pmsa-v7.c err |= mpu_setup_region(region++, mem[i].base, ilog2(mem[i].size), base 107 arch/arm/mm/pmsa-v8.c if (reg->base != phys_offset) base 109 arch/arm/mm/pmsa-v8.c mem_end = reg->base + reg->size; base 118 arch/arm/mm/pmsa-v8.c &mem_end, ®->base); base 119 arch/arm/mm/pmsa-v8.c memblock_remove(reg->base, 0 - reg->base); base 247 arch/arm/mm/pmsa-v8.c add_range(mem, ARRAY_SIZE(mem), 0, memblock.memory.regions[0].base, base 248 arch/arm/mm/pmsa-v8.c memblock.memory.regions[0].base + memblock.memory.regions[0].size); base 64 arch/arm/plat-omap/sram.c unsigned long base; base 72 arch/arm/plat-omap/sram.c base = (unsigned long)sram & PAGE_MASK; base 75 arch/arm/plat-omap/sram.c set_memory_rw(base, pages); base 79 arch/arm/plat-omap/sram.c set_memory_ro(base, pages); base 80 arch/arm/plat-omap/sram.c set_memory_x(base, pages); base 100 arch/arm/plat-omap/sram.c unsigned long base; base 124 arch/arm/plat-omap/sram.c base = (unsigned long)omap_sram_base; base 127 arch/arm/plat-omap/sram.c set_memory_ro(base, pages); base 128 arch/arm/plat-omap/sram.c set_memory_x(base, pages); base 43 arch/arm/plat-orion/gpio.c void __iomem *base; base 53 arch/arm/plat-orion/gpio.c return ochip->base + GPIO_OUT_OFF; base 58 arch/arm/plat-orion/gpio.c return ochip->base + GPIO_IO_CONF_OFF; base 63 arch/arm/plat-orion/gpio.c return ochip->base + GPIO_BLINK_EN_OFF; base 68 arch/arm/plat-orion/gpio.c return ochip->base + GPIO_IN_POL_OFF; base 73 arch/arm/plat-orion/gpio.c return ochip->base + GPIO_DATA_IN_OFF; base 78 arch/arm/plat-orion/gpio.c return ochip->base + GPIO_EDGE_CAUSE_OFF; base 83 arch/arm/plat-orion/gpio.c return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF; base 88 arch/arm/plat-orion/gpio.c return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF; base 242 arch/arm/plat-orion/gpio.c if (pin >= chip->base && pin < chip->base + chip->ngpio) base 256 arch/arm/plat-orion/gpio.c pin -= ochip->chip.base; base 270 arch/arm/plat-orion/gpio.c pin -= ochip->chip.base; base 468 arch/arm/plat-orion/gpio.c seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); base 525 arch/arm/plat-orion/gpio.c void __iomem *base, int mask_offset, base 549 arch/arm/plat-orion/gpio.c ochip->chip.base = gpio_base; base 558 arch/arm/plat-orion/gpio.c ochip->base = (void __iomem *)base; base 587 arch/arm/plat-orion/gpio.c ochip->base, handle_level_irq); base 37 arch/arm/plat-orion/include/plat/addr-map.h const u32 base; base 48 arch/arm/plat-orion/include/plat/addr-map.h const int win, const u32 base, base 35 arch/arm/plat-orion/include/plat/orion-gpio.h void __iomem *base, int mask_offset, base 16 arch/arm/plat-orion/include/plat/pcie.h u32 orion_pcie_dev_id(void __iomem *base); base 17 arch/arm/plat-orion/include/plat/pcie.h u32 orion_pcie_rev(void __iomem *base); base 18 arch/arm/plat-orion/include/plat/pcie.h int orion_pcie_link_up(void __iomem *base); base 19 arch/arm/plat-orion/include/plat/pcie.h int orion_pcie_x4_mode(void __iomem *base); base 20 arch/arm/plat-orion/include/plat/pcie.h int orion_pcie_get_local_bus_nr(void __iomem *base); base 21 arch/arm/plat-orion/include/plat/pcie.h void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); base 22 arch/arm/plat-orion/include/plat/pcie.h void orion_pcie_reset(void __iomem *base); base 23 arch/arm/plat-orion/include/plat/pcie.h void orion_pcie_setup(void __iomem *base); base 24 arch/arm/plat-orion/include/plat/pcie.h int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, base 26 arch/arm/plat-orion/include/plat/pcie.h int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, base 30 arch/arm/plat-orion/include/plat/pcie.h int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, base 55 arch/arm/plat-orion/pcie.c u32 orion_pcie_dev_id(void __iomem *base) base 57 arch/arm/plat-orion/pcie.c return readl(base + PCIE_DEV_ID_OFF) >> 16; base 60 arch/arm/plat-orion/pcie.c u32 orion_pcie_rev(void __iomem *base) base 62 arch/arm/plat-orion/pcie.c return readl(base + PCIE_DEV_REV_OFF) & 0xff; base 65 arch/arm/plat-orion/pcie.c int orion_pcie_link_up(void __iomem *base) base 67 arch/arm/plat-orion/pcie.c return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); base 70 arch/arm/plat-orion/pcie.c int __init orion_pcie_x4_mode(void __iomem *base) base 72 arch/arm/plat-orion/pcie.c return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); base 75 arch/arm/plat-orion/pcie.c int orion_pcie_get_local_bus_nr(void __iomem *base) base 77 arch/arm/plat-orion/pcie.c u32 stat = readl(base + PCIE_STAT_OFF); base 82 arch/arm/plat-orion/pcie.c void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr) base 86 arch/arm/plat-orion/pcie.c stat = readl(base + PCIE_STAT_OFF); base 89 arch/arm/plat-orion/pcie.c writel(stat, base + PCIE_STAT_OFF); base 92 arch/arm/plat-orion/pcie.c void __init orion_pcie_reset(void __iomem *base) base 103 arch/arm/plat-orion/pcie.c reg = readl(base + PCIE_DEBUG_CTRL); base 105 arch/arm/plat-orion/pcie.c writel(reg, base + PCIE_DEBUG_CTRL); base 110 arch/arm/plat-orion/pcie.c if (orion_pcie_link_up(base)) base 115 arch/arm/plat-orion/pcie.c writel(reg, base + PCIE_DEBUG_CTRL); base 123 arch/arm/plat-orion/pcie.c static void __init orion_pcie_setup_wins(void __iomem *base) base 135 arch/arm/plat-orion/pcie.c writel(0, base + PCIE_BAR_CTRL_OFF(i)); base 136 arch/arm/plat-orion/pcie.c writel(0, base + PCIE_BAR_LO_OFF(i)); base 137 arch/arm/plat-orion/pcie.c writel(0, base + PCIE_BAR_HI_OFF(i)); base 141 arch/arm/plat-orion/pcie.c writel(0, base + PCIE_WIN04_CTRL_OFF(i)); base 142 arch/arm/plat-orion/pcie.c writel(0, base + PCIE_WIN04_BASE_OFF(i)); base 143 arch/arm/plat-orion/pcie.c writel(0, base + PCIE_WIN04_REMAP_OFF(i)); base 146 arch/arm/plat-orion/pcie.c writel(0, base + PCIE_WIN5_CTRL_OFF); base 147 arch/arm/plat-orion/pcie.c writel(0, base + PCIE_WIN5_BASE_OFF); base 148 arch/arm/plat-orion/pcie.c writel(0, base + PCIE_WIN5_REMAP_OFF); base 157 arch/arm/plat-orion/pcie.c writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); base 158 arch/arm/plat-orion/pcie.c writel(0, base + PCIE_WIN04_REMAP_OFF(i)); base 162 arch/arm/plat-orion/pcie.c base + PCIE_WIN04_CTRL_OFF(i)); base 176 arch/arm/plat-orion/pcie.c writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); base 177 arch/arm/plat-orion/pcie.c writel(0, base + PCIE_BAR_HI_OFF(1)); base 178 arch/arm/plat-orion/pcie.c writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); base 181 arch/arm/plat-orion/pcie.c void __init orion_pcie_setup(void __iomem *base) base 189 arch/arm/plat-orion/pcie.c orion_pcie_setup_wins(base); base 194 arch/arm/plat-orion/pcie.c cmd = readw(base + PCIE_CMD_OFF); base 198 arch/arm/plat-orion/pcie.c writew(cmd, base + PCIE_CMD_OFF); base 203 arch/arm/plat-orion/pcie.c mask = readl(base + PCIE_MASK_OFF); base 205 arch/arm/plat-orion/pcie.c writel(mask, base + PCIE_MASK_OFF); base 208 arch/arm/plat-orion/pcie.c int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, base 215 arch/arm/plat-orion/pcie.c base + PCIE_CONF_ADDR_OFF); base 217 arch/arm/plat-orion/pcie.c *val = readl(base + PCIE_CONF_DATA_OFF); base 227 arch/arm/plat-orion/pcie.c int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, base 234 arch/arm/plat-orion/pcie.c base + PCIE_CONF_ADDR_OFF); base 236 arch/arm/plat-orion/pcie.c *val = readl(base + PCIE_CONF_DATA_OFF); base 238 arch/arm/plat-orion/pcie.c if (bus->number != orion_pcie_get_local_bus_nr(base) || base 240 arch/arm/plat-orion/pcie.c *val = readl(base + PCIE_HEADER_LOG_4_OFF); base 266 arch/arm/plat-orion/pcie.c int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, base 275 arch/arm/plat-orion/pcie.c base + PCIE_CONF_ADDR_OFF); base 278 arch/arm/plat-orion/pcie.c writel(val, base + PCIE_CONF_DATA_OFF); base 280 arch/arm/plat-orion/pcie.c writew(val, base + PCIE_CONF_DATA_OFF + (where & 3)); base 282 arch/arm/plat-orion/pcie.c writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3)); base 43 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base + 0x08; base 58 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base + 0x08; base 112 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base + 0x08; base 130 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base + 0x08; base 178 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base; base 213 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(chip->base); base 241 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base; base 276 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base; base 306 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base; base 346 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(chip->base); base 431 arch/arm/plat-samsung/gpio-samsung.c void __iomem *base = ourchip->base; base 437 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(base + 0x00); base 440 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(con, base + 0x00); base 450 arch/arm/plat-samsung/gpio-samsung.c void __iomem *base = ourchip->base; base 457 arch/arm/plat-samsung/gpio-samsung.c dat = __raw_readl(base + 0x04); base 461 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(dat, base + 0x04); base 463 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(base + 0x00); base 467 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(con, base + 0x00); base 468 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(dat, base + 0x04); base 494 arch/arm/plat-samsung/gpio-samsung.c void __iomem *base = ourchip->base; base 497 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(base + GPIOCON_OFF); base 502 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(con, base + GPIOCON_OFF); base 504 arch/arm/plat-samsung/gpio-samsung.c pr_debug("%s: %p: CON now %08lx\n", __func__, base, con); base 513 arch/arm/plat-samsung/gpio-samsung.c void __iomem *base = ourchip->base; base 517 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(base + GPIOCON_OFF); base 521 arch/arm/plat-samsung/gpio-samsung.c dat = __raw_readl(base + GPIODAT_OFF); base 528 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(dat, base + GPIODAT_OFF); base 529 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(con, base + GPIOCON_OFF); base 530 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(dat, base + GPIODAT_OFF); base 532 arch/arm/plat-samsung/gpio-samsung.c pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); base 563 arch/arm/plat-samsung/gpio-samsung.c void __iomem *base = ourchip->base; base 564 arch/arm/plat-samsung/gpio-samsung.c void __iomem *regcon = base; base 576 arch/arm/plat-samsung/gpio-samsung.c pr_debug("%s: %p: CON %08lx\n", __func__, base, con); base 585 arch/arm/plat-samsung/gpio-samsung.c void __iomem *base = ourchip->base; base 586 arch/arm/plat-samsung/gpio-samsung.c void __iomem *regcon = base; base 600 arch/arm/plat-samsung/gpio-samsung.c dat = __raw_readl(base + GPIODAT_OFF); base 607 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(dat, base + GPIODAT_OFF); base 609 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(dat, base + GPIODAT_OFF); base 611 arch/arm/plat-samsung/gpio-samsung.c pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); base 628 arch/arm/plat-samsung/gpio-samsung.c void __iomem *base = ourchip->base; base 635 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(base + 0x00); base 636 arch/arm/plat-samsung/gpio-samsung.c dat = __raw_readl(base + 0x04); base 642 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(dat, base + 0x04); base 646 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(con, base + 0x00); base 647 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(dat, base + 0x04); base 658 arch/arm/plat-samsung/gpio-samsung.c void __iomem *base = ourchip->base; base 664 arch/arm/plat-samsung/gpio-samsung.c dat = __raw_readl(base + 0x04); base 668 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(dat, base + 0x04); base 678 arch/arm/plat-samsung/gpio-samsung.c val = __raw_readl(ourchip->base + 0x04); base 705 arch/arm/plat-samsung/gpio-samsung.c gpn = chip->chip.base; base 728 arch/arm/plat-samsung/gpio-samsung.c BUG_ON(!chip->base); base 759 arch/arm/plat-samsung/gpio-samsung.c int nr_chips, void __iomem *base) base 766 arch/arm/plat-samsung/gpio-samsung.c if (chip->chip.base >= S3C_GPIO_END) base 773 arch/arm/plat-samsung/gpio-samsung.c if ((base != NULL) && (chip->base == NULL)) base 774 arch/arm/plat-samsung/gpio-samsung.c chip->base = base + ((i) * 0x10); base 786 arch/arm/plat-samsung/gpio-samsung.c int nr_chips, void __iomem *base, base 799 arch/arm/plat-samsung/gpio-samsung.c if ((base != NULL) && (chip->base == NULL)) base 800 arch/arm/plat-samsung/gpio-samsung.c chip->base = base + ((i) * offset); base 823 arch/arm/plat-samsung/gpio-samsung.c int nr_chips, void __iomem *base) base 835 arch/arm/plat-samsung/gpio-samsung.c if ((base != NULL) && (chip->base == NULL)) base 836 arch/arm/plat-samsung/gpio-samsung.c chip->base = base + ((i) * 0x20); base 901 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPA(0), base 910 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPB(0), base 917 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPC(0), base 924 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPD(0), base 931 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPE(0), base 938 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPF(0), base 947 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPG(0), base 955 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPH(0), base 963 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2440_GPJCON, base 965 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPJ(0), base 971 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2443_GPKCON, base 973 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPK(0), base 979 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2443_GPLCON, base 981 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPL(0), base 987 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2443_GPMCON, base 989 arch/arm/plat-samsung/gpio-samsung.c .base = S3C2410_GPM(0), base 1028 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPA(0), base 1034 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPB(0), base 1040 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPC(0), base 1046 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPD(0), base 1053 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPE(0), base 1058 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPG_BASE, base 1060 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPG(0), base 1065 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPM_BASE, base 1068 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPM(0), base 1080 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPH_BASE + 0x4, base 1082 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPH(0), base 1087 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPK_BASE + 0x4, base 1090 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPK(0), base 1095 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPL_BASE + 0x4, base 1098 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPL(0), base 1110 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPF_BASE, base 1113 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPF(0), base 1120 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPI(0), base 1127 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPJ(0), base 1134 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPO(0), base 1141 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPP(0), base 1148 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPQ(0), base 1153 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPN_BASE, base 1157 arch/arm/plat-samsung/gpio-samsung.c .base = S3C64XX_GPN(0), base 1210 arch/arm/plat-samsung/gpio-samsung.c offset = pin - chip->chip.base; base 1259 arch/arm/plat-samsung/gpio-samsung.c offset = pin - chip->chip.base; base 1279 arch/arm/plat-samsung/gpio-samsung.c offset = pin - chip->chip.base; base 1297 arch/arm/plat-samsung/gpio-samsung.c offset = pin - chip->chip.base; base 71 arch/arm/plat-samsung/include/plat/gpio-core.h void __iomem *base; base 119 arch/arm/plat-samsung/include/plat/gpio-core.h return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL; base 29 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); base 30 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); base 35 arch/arm/plat-samsung/pm-gpio.c void __iomem *base = chip->base; base 36 arch/arm/plat-samsung/pm-gpio.c u32 old_gpcon = __raw_readl(base + OFFS_CON); base 37 arch/arm/plat-samsung/pm-gpio.c u32 old_gpdat = __raw_readl(base + OFFS_DAT); base 48 arch/arm/plat-samsung/pm-gpio.c __raw_writel(gpcon, base + OFFS_CON); base 52 arch/arm/plat-samsung/pm-gpio.c __raw_writel(gps_gpdat, base + OFFS_DAT); base 53 arch/arm/plat-samsung/pm-gpio.c __raw_writel(gps_gpcon, base + OFFS_CON); base 66 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); base 67 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); base 68 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); base 122 arch/arm/plat-samsung/pm-gpio.c void __iomem *base = chip->base; base 123 arch/arm/plat-samsung/pm-gpio.c u32 old_gpcon = __raw_readl(base + OFFS_CON); base 124 arch/arm/plat-samsung/pm-gpio.c u32 old_gpdat = __raw_readl(base + OFFS_DAT); base 132 arch/arm/plat-samsung/pm-gpio.c __raw_writel(chip->pm_save[2], base + OFFS_UP); base 175 arch/arm/plat-samsung/pm-gpio.c __raw_writel(gpcon, base + OFFS_CON); base 179 arch/arm/plat-samsung/pm-gpio.c __raw_writel(gps_gpdat, base + OFFS_DAT); base 180 arch/arm/plat-samsung/pm-gpio.c __raw_writel(gps_gpcon, base + OFFS_CON); base 194 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); base 195 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); base 196 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP); base 199 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[0] = __raw_readl(chip->base - 4); base 243 arch/arm/plat-samsung/pm-gpio.c void __iomem *con = chip->base + (index * 4); base 258 arch/arm/plat-samsung/pm-gpio.c void __iomem *base = chip->base; base 260 arch/arm/plat-samsung/pm-gpio.c u32 old_gpdat = __raw_readl(base + OFFS_DAT); base 266 arch/arm/plat-samsung/pm-gpio.c old_gpcon[1] = __raw_readl(base + OFFS_CON); base 270 arch/arm/plat-samsung/pm-gpio.c old_gpcon[0] = __raw_readl(base - 4); base 276 arch/arm/plat-samsung/pm-gpio.c __raw_writel(chip->pm_save[2], base + OFFS_DAT); base 277 arch/arm/plat-samsung/pm-gpio.c __raw_writel(chip->pm_save[1], base + OFFS_CON); base 279 arch/arm/plat-samsung/pm-gpio.c __raw_writel(chip->pm_save[0], base - 4); base 281 arch/arm/plat-samsung/pm-gpio.c __raw_writel(chip->pm_save[2], base + OFFS_DAT); base 282 arch/arm/plat-samsung/pm-gpio.c __raw_writel(chip->pm_save[3], base + OFFS_UP); base 287 arch/arm/plat-samsung/pm-gpio.c __raw_readl(base - 4), base 288 arch/arm/plat-samsung/pm-gpio.c __raw_readl(base + OFFS_CON), base 293 arch/arm/plat-samsung/pm-gpio.c __raw_readl(base + OFFS_CON), base 89 arch/arm/plat-samsung/watchdog-reset.c void __init samsung_wdt_reset_init(void __iomem *base) base 91 arch/arm/plat-samsung/watchdog-reset.c wdt_base = base; base 323 arch/arm/probes/kprobes/actions-thumb.c unsigned long *base = (unsigned long *)((regs->ARM_pc + 2) & ~3); base 326 arch/arm/probes/kprobes/actions-thumb.c regs->uregs[rt] = base[index]; base 333 arch/arm/probes/kprobes/actions-thumb.c unsigned long* base = (unsigned long *)regs->ARM_sp; base 337 arch/arm/probes/kprobes/actions-thumb.c regs->uregs[rt] = base[index]; base 339 arch/arm/probes/kprobes/actions-thumb.c base[index] = regs->uregs[rt]; base 346 arch/arm/probes/kprobes/actions-thumb.c unsigned long base = (insn & 0x800) ? regs->ARM_sp base 350 arch/arm/probes/kprobes/actions-thumb.c regs->uregs[rt] = base + offset * 4; base 698 arch/arm/probes/kprobes/test-core.c struct coverage_entry *base; base 738 arch/arm/probes/kprobes/test-core.c struct coverage_entry *entry = coverage->base + coverage->num_entries; base 766 arch/arm/probes/kprobes/test-core.c coverage.base = kmalloc_array(MAX_COVERAGE_ENTRIES, base 844 arch/arm/probes/kprobes/test-core.c struct coverage_entry *entry = coverage.base; base 845 arch/arm/probes/kprobes/test-core.c struct coverage_entry *end = coverage.base + coverage.num_entries; base 891 arch/arm/probes/kprobes/test-core.c struct coverage_entry *entry = coverage.base; base 892 arch/arm/probes/kprobes/test-core.c struct coverage_entry *end = coverage.base + coverage.num_entries; base 910 arch/arm/probes/kprobes/test-core.c kfree(coverage.base); base 30 arch/arm/xen/mm.c if (reg->base < (phys_addr_t)0xffffffff) { base 56 arch/arm64/crypto/aes-ce-ccm-glue.c tfm->base.crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; base 348 arch/arm64/crypto/aes-ce-ccm-glue.c .base = { base 672 arch/arm64/crypto/aes-glue.c .base = { base 687 arch/arm64/crypto/aes-glue.c .base = { base 703 arch/arm64/crypto/aes-glue.c .base = { base 720 arch/arm64/crypto/aes-glue.c .base = { base 736 arch/arm64/crypto/aes-glue.c .base = { base 754 arch/arm64/crypto/aes-glue.c .base = { base 771 arch/arm64/crypto/aes-glue.c .base = { base 967 arch/arm64/crypto/aes-glue.c .base.cra_name = "cmac(aes)", base 968 arch/arm64/crypto/aes-glue.c .base.cra_driver_name = "cmac-aes-" MODE, base 969 arch/arm64/crypto/aes-glue.c .base.cra_priority = PRIO, base 970 arch/arm64/crypto/aes-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 971 arch/arm64/crypto/aes-glue.c .base.cra_ctxsize = sizeof(struct mac_tfm_ctx) + base 973 arch/arm64/crypto/aes-glue.c .base.cra_module = THIS_MODULE, base 982 arch/arm64/crypto/aes-glue.c .base.cra_name = "xcbc(aes)", base 983 arch/arm64/crypto/aes-glue.c .base.cra_driver_name = "xcbc-aes-" MODE, base 984 arch/arm64/crypto/aes-glue.c .base.cra_priority = PRIO, base 985 arch/arm64/crypto/aes-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 986 arch/arm64/crypto/aes-glue.c .base.cra_ctxsize = sizeof(struct mac_tfm_ctx) + base 988 arch/arm64/crypto/aes-glue.c .base.cra_module = THIS_MODULE, base 997 arch/arm64/crypto/aes-glue.c .base.cra_name = "cbcmac(aes)", base 998 arch/arm64/crypto/aes-glue.c .base.cra_driver_name = "cbcmac-aes-" MODE, base 999 arch/arm64/crypto/aes-glue.c .base.cra_priority = PRIO, base 1000 arch/arm64/crypto/aes-glue.c .base.cra_blocksize = 1, base 1001 arch/arm64/crypto/aes-glue.c .base.cra_ctxsize = sizeof(struct mac_tfm_ctx), base 1002 arch/arm64/crypto/aes-glue.c .base.cra_module = THIS_MODULE, base 1044 arch/arm64/crypto/aes-glue.c if (!(aes_algs[i].base.cra_flags & CRYPTO_ALG_INTERNAL)) base 1047 arch/arm64/crypto/aes-glue.c algname = aes_algs[i].base.cra_name + 2; base 1048 arch/arm64/crypto/aes-glue.c drvname = aes_algs[i].base.cra_driver_name + 2; base 1049 arch/arm64/crypto/aes-glue.c basename = aes_algs[i].base.cra_driver_name; base 433 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_name = "__ecb(aes)", base 434 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_driver_name = "__ecb-aes-neonbs", base 435 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_priority = 250, base 436 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 437 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_ctxsize = sizeof(struct aesbs_ctx), base 438 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_module = THIS_MODULE, base 439 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 448 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_name = "__cbc(aes)", base 449 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_driver_name = "__cbc-aes-neonbs", base 450 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_priority = 250, base 451 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 452 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_ctxsize = sizeof(struct aesbs_cbc_ctx), base 453 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_module = THIS_MODULE, base 454 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 464 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_name = "__ctr(aes)", base 465 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_driver_name = "__ctr-aes-neonbs", base 466 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_priority = 250, base 467 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_blocksize = 1, base 468 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_ctxsize = sizeof(struct aesbs_ctx), base 469 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_module = THIS_MODULE, base 470 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 481 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_name = "ctr(aes)", base 482 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_driver_name = "ctr-aes-neonbs", base 483 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_priority = 250 - 1, base 484 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_blocksize = 1, base 485 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_ctxsize = sizeof(struct aesbs_ctr_ctx), base 486 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_module = THIS_MODULE, base 497 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_name = "__xts(aes)", base 498 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_driver_name = "__xts-aes-neonbs", base 499 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_priority = 250, base 500 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_blocksize = AES_BLOCK_SIZE, base 501 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_ctxsize = sizeof(struct aesbs_xts_ctx), base 502 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_module = THIS_MODULE, base 503 arch/arm64/crypto/aes-neonbs-glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 544 arch/arm64/crypto/aes-neonbs-glue.c if (!(aes_algs[i].base.cra_flags & CRYPTO_ALG_INTERNAL)) base 547 arch/arm64/crypto/aes-neonbs-glue.c algname = aes_algs[i].base.cra_name + 2; base 548 arch/arm64/crypto/aes-neonbs-glue.c drvname = aes_algs[i].base.cra_driver_name + 2; base 549 arch/arm64/crypto/aes-neonbs-glue.c basename = aes_algs[i].base.cra_driver_name; base 125 arch/arm64/crypto/chacha-neon-glue.c .base.cra_name = "chacha20", base 126 arch/arm64/crypto/chacha-neon-glue.c .base.cra_driver_name = "chacha20-neon", base 127 arch/arm64/crypto/chacha-neon-glue.c .base.cra_priority = 300, base 128 arch/arm64/crypto/chacha-neon-glue.c .base.cra_blocksize = 1, base 129 arch/arm64/crypto/chacha-neon-glue.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 130 arch/arm64/crypto/chacha-neon-glue.c .base.cra_module = THIS_MODULE, base 141 arch/arm64/crypto/chacha-neon-glue.c .base.cra_name = "xchacha20", base 142 arch/arm64/crypto/chacha-neon-glue.c .base.cra_driver_name = "xchacha20-neon", base 143 arch/arm64/crypto/chacha-neon-glue.c .base.cra_priority = 300, base 144 arch/arm64/crypto/chacha-neon-glue.c .base.cra_blocksize = 1, base 145 arch/arm64/crypto/chacha-neon-glue.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 146 arch/arm64/crypto/chacha-neon-glue.c .base.cra_module = THIS_MODULE, base 157 arch/arm64/crypto/chacha-neon-glue.c .base.cra_name = "xchacha12", base 158 arch/arm64/crypto/chacha-neon-glue.c .base.cra_driver_name = "xchacha12-neon", base 159 arch/arm64/crypto/chacha-neon-glue.c .base.cra_priority = 300, base 160 arch/arm64/crypto/chacha-neon-glue.c .base.cra_blocksize = 1, base 161 arch/arm64/crypto/chacha-neon-glue.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 162 arch/arm64/crypto/chacha-neon-glue.c .base.cra_module = THIS_MODULE, base 81 arch/arm64/crypto/crct10dif-ce-glue.c .base.cra_name = "crct10dif", base 82 arch/arm64/crypto/crct10dif-ce-glue.c .base.cra_driver_name = "crct10dif-arm64-neon", base 83 arch/arm64/crypto/crct10dif-ce-glue.c .base.cra_priority = 100, base 84 arch/arm64/crypto/crct10dif-ce-glue.c .base.cra_blocksize = CRC_T10DIF_BLOCK_SIZE, base 85 arch/arm64/crypto/crct10dif-ce-glue.c .base.cra_module = THIS_MODULE, base 93 arch/arm64/crypto/crct10dif-ce-glue.c .base.cra_name = "crct10dif", base 94 arch/arm64/crypto/crct10dif-ce-glue.c .base.cra_driver_name = "crct10dif-arm64-ce", base 95 arch/arm64/crypto/crct10dif-ce-glue.c .base.cra_priority = 200, base 96 arch/arm64/crypto/crct10dif-ce-glue.c .base.cra_blocksize = CRC_T10DIF_BLOCK_SIZE, base 97 arch/arm64/crypto/crct10dif-ce-glue.c .base.cra_module = THIS_MODULE, base 262 arch/arm64/crypto/ghash-ce-glue.c .base.cra_name = "ghash", base 263 arch/arm64/crypto/ghash-ce-glue.c .base.cra_driver_name = "ghash-neon", base 264 arch/arm64/crypto/ghash-ce-glue.c .base.cra_priority = 150, base 265 arch/arm64/crypto/ghash-ce-glue.c .base.cra_blocksize = GHASH_BLOCK_SIZE, base 266 arch/arm64/crypto/ghash-ce-glue.c .base.cra_ctxsize = sizeof(struct ghash_key), base 267 arch/arm64/crypto/ghash-ce-glue.c .base.cra_module = THIS_MODULE, base 276 arch/arm64/crypto/ghash-ce-glue.c .base.cra_name = "ghash", base 277 arch/arm64/crypto/ghash-ce-glue.c .base.cra_driver_name = "ghash-ce", base 278 arch/arm64/crypto/ghash-ce-glue.c .base.cra_priority = 200, base 279 arch/arm64/crypto/ghash-ce-glue.c .base.cra_blocksize = GHASH_BLOCK_SIZE, base 280 arch/arm64/crypto/ghash-ce-glue.c .base.cra_ctxsize = sizeof(struct ghash_key), base 281 arch/arm64/crypto/ghash-ce-glue.c .base.cra_module = THIS_MODULE, base 312 arch/arm64/crypto/ghash-ce-glue.c tfm->base.crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; base 685 arch/arm64/crypto/ghash-ce-glue.c .base.cra_name = "gcm(aes)", base 686 arch/arm64/crypto/ghash-ce-glue.c .base.cra_driver_name = "gcm-aes-ce", base 687 arch/arm64/crypto/ghash-ce-glue.c .base.cra_priority = 300, base 688 arch/arm64/crypto/ghash-ce-glue.c .base.cra_blocksize = 1, base 689 arch/arm64/crypto/ghash-ce-glue.c .base.cra_ctxsize = sizeof(struct gcm_aes_ctx), base 690 arch/arm64/crypto/ghash-ce-glue.c .base.cra_module = THIS_MODULE, base 45 arch/arm64/crypto/nhpoly1305-neon-glue.c .base.cra_name = "nhpoly1305", base 46 arch/arm64/crypto/nhpoly1305-neon-glue.c .base.cra_driver_name = "nhpoly1305-neon", base 47 arch/arm64/crypto/nhpoly1305-neon-glue.c .base.cra_priority = 200, base 48 arch/arm64/crypto/nhpoly1305-neon-glue.c .base.cra_ctxsize = sizeof(struct nhpoly1305_key), base 49 arch/arm64/crypto/nhpoly1305-neon-glue.c .base.cra_module = THIS_MODULE, base 96 arch/arm64/crypto/sha1-ce-glue.c .base = { base 111 arch/arm64/crypto/sha2-ce-glue.c .base = { base 125 arch/arm64/crypto/sha2-ce-glue.c .base = { base 64 arch/arm64/crypto/sha256-glue.c .base.cra_name = "sha256", base 65 arch/arm64/crypto/sha256-glue.c .base.cra_driver_name = "sha256-arm64", base 66 arch/arm64/crypto/sha256-glue.c .base.cra_priority = 125, base 67 arch/arm64/crypto/sha256-glue.c .base.cra_blocksize = SHA256_BLOCK_SIZE, base 68 arch/arm64/crypto/sha256-glue.c .base.cra_module = THIS_MODULE, base 76 arch/arm64/crypto/sha256-glue.c .base.cra_name = "sha224", base 77 arch/arm64/crypto/sha256-glue.c .base.cra_driver_name = "sha224-arm64", base 78 arch/arm64/crypto/sha256-glue.c .base.cra_priority = 125, base 79 arch/arm64/crypto/sha256-glue.c .base.cra_blocksize = SHA224_BLOCK_SIZE, base 80 arch/arm64/crypto/sha256-glue.c .base.cra_module = THIS_MODULE, base 147 arch/arm64/crypto/sha256-glue.c .base.cra_name = "sha256", base 148 arch/arm64/crypto/sha256-glue.c .base.cra_driver_name = "sha256-arm64-neon", base 149 arch/arm64/crypto/sha256-glue.c .base.cra_priority = 150, base 150 arch/arm64/crypto/sha256-glue.c .base.cra_blocksize = SHA256_BLOCK_SIZE, base 151 arch/arm64/crypto/sha256-glue.c .base.cra_module = THIS_MODULE, base 159 arch/arm64/crypto/sha256-glue.c .base.cra_name = "sha224", base 160 arch/arm64/crypto/sha256-glue.c .base.cra_driver_name = "sha224-arm64-neon", base 161 arch/arm64/crypto/sha256-glue.c .base.cra_priority = 150, base 162 arch/arm64/crypto/sha256-glue.c .base.cra_blocksize = SHA224_BLOCK_SIZE, base 163 arch/arm64/crypto/sha256-glue.c .base.cra_module = THIS_MODULE, base 107 arch/arm64/crypto/sha3-ce-glue.c .base.cra_name = "sha3-224", base 108 arch/arm64/crypto/sha3-ce-glue.c .base.cra_driver_name = "sha3-224-ce", base 109 arch/arm64/crypto/sha3-ce-glue.c .base.cra_blocksize = SHA3_224_BLOCK_SIZE, base 110 arch/arm64/crypto/sha3-ce-glue.c .base.cra_module = THIS_MODULE, base 111 arch/arm64/crypto/sha3-ce-glue.c .base.cra_priority = 200, base 118 arch/arm64/crypto/sha3-ce-glue.c .base.cra_name = "sha3-256", base 119 arch/arm64/crypto/sha3-ce-glue.c .base.cra_driver_name = "sha3-256-ce", base 120 arch/arm64/crypto/sha3-ce-glue.c .base.cra_blocksize = SHA3_256_BLOCK_SIZE, base 121 arch/arm64/crypto/sha3-ce-glue.c .base.cra_module = THIS_MODULE, base 122 arch/arm64/crypto/sha3-ce-glue.c .base.cra_priority = 200, base 129 arch/arm64/crypto/sha3-ce-glue.c .base.cra_name = "sha3-384", base 130 arch/arm64/crypto/sha3-ce-glue.c .base.cra_driver_name = "sha3-384-ce", base 131 arch/arm64/crypto/sha3-ce-glue.c .base.cra_blocksize = SHA3_384_BLOCK_SIZE, base 132 arch/arm64/crypto/sha3-ce-glue.c .base.cra_module = THIS_MODULE, base 133 arch/arm64/crypto/sha3-ce-glue.c .base.cra_priority = 200, base 140 arch/arm64/crypto/sha3-ce-glue.c .base.cra_name = "sha3-512", base 141 arch/arm64/crypto/sha3-ce-glue.c .base.cra_driver_name = "sha3-512-ce", base 142 arch/arm64/crypto/sha3-ce-glue.c .base.cra_blocksize = SHA3_512_BLOCK_SIZE, base 143 arch/arm64/crypto/sha3-ce-glue.c .base.cra_module = THIS_MODULE, base 144 arch/arm64/crypto/sha3-ce-glue.c .base.cra_priority = 200, base 88 arch/arm64/crypto/sha512-ce-glue.c .base.cra_name = "sha384", base 89 arch/arm64/crypto/sha512-ce-glue.c .base.cra_driver_name = "sha384-ce", base 90 arch/arm64/crypto/sha512-ce-glue.c .base.cra_priority = 200, base 91 arch/arm64/crypto/sha512-ce-glue.c .base.cra_blocksize = SHA512_BLOCK_SIZE, base 92 arch/arm64/crypto/sha512-ce-glue.c .base.cra_module = THIS_MODULE, base 100 arch/arm64/crypto/sha512-ce-glue.c .base.cra_name = "sha512", base 101 arch/arm64/crypto/sha512-ce-glue.c .base.cra_driver_name = "sha512-ce", base 102 arch/arm64/crypto/sha512-ce-glue.c .base.cra_priority = 200, base 103 arch/arm64/crypto/sha512-ce-glue.c .base.cra_blocksize = SHA512_BLOCK_SIZE, base 104 arch/arm64/crypto/sha512-ce-glue.c .base.cra_module = THIS_MODULE, base 58 arch/arm64/crypto/sha512-glue.c .base.cra_name = "sha512", base 59 arch/arm64/crypto/sha512-glue.c .base.cra_driver_name = "sha512-arm64", base 60 arch/arm64/crypto/sha512-glue.c .base.cra_priority = 150, base 61 arch/arm64/crypto/sha512-glue.c .base.cra_blocksize = SHA512_BLOCK_SIZE, base 62 arch/arm64/crypto/sha512-glue.c .base.cra_module = THIS_MODULE, base 70 arch/arm64/crypto/sha512-glue.c .base.cra_name = "sha384", base 71 arch/arm64/crypto/sha512-glue.c .base.cra_driver_name = "sha384-arm64", base 72 arch/arm64/crypto/sha512-glue.c .base.cra_priority = 150, base 73 arch/arm64/crypto/sha512-glue.c .base.cra_blocksize = SHA384_BLOCK_SIZE, base 74 arch/arm64/crypto/sha512-glue.c .base.cra_module = THIS_MODULE, base 71 arch/arm64/crypto/sm3-ce-glue.c .base.cra_name = "sm3", base 72 arch/arm64/crypto/sm3-ce-glue.c .base.cra_driver_name = "sm3-ce", base 73 arch/arm64/crypto/sm3-ce-glue.c .base.cra_blocksize = SM3_BLOCK_SIZE, base 74 arch/arm64/crypto/sm3-ce-glue.c .base.cra_module = THIS_MODULE, base 75 arch/arm64/crypto/sm3-ce-glue.c .base.cra_priority = 200, base 378 arch/arm64/include/asm/insn.h enum aarch64_insn_register base, base 384 arch/arm64/include/asm/insn.h enum aarch64_insn_register base, base 389 arch/arm64/include/asm/insn.h enum aarch64_insn_register base, base 453 arch/arm64/include/asm/insn.h u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base, base 26 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_save_state base, reg1, reg2 base 44 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_restore_state base, reg1, reg2 base 88 arch/arm64/include/asm/processor.h #define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \ base 89 arch/arm64/include/asm/processor.h base + TASK_SIZE - DEFAULT_MAP_WINDOW :\ base 90 arch/arm64/include/asm/processor.h base) base 22 arch/arm64/include/asm/vdso.h #define VDSO_SYMBOL(base, name) \ base 24 arch/arm64/include/asm/vdso.h (void *)(vdso_offset_##name - VDSO_LBASE + (unsigned long)(base)); \ base 597 arch/arm64/kernel/insn.c enum aarch64_insn_register base, base 621 arch/arm64/kernel/insn.c base); base 629 arch/arm64/kernel/insn.c enum aarch64_insn_register base, base 685 arch/arm64/kernel/insn.c base); base 692 arch/arm64/kernel/insn.c enum aarch64_insn_register base, base 717 arch/arm64/kernel/insn.c base); base 819 arch/arm64/kernel/insn.c u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base, base 831 arch/arm64/kernel/insn.c base); base 68 arch/arm64/kernel/module-plts.c return (u64)loc - (u64)mod->init_layout.base < mod->init_layout.size; base 165 arch/arm64/kernel/signal.c char __user *base = (char __user *)user->sigframe; base 167 arch/arm64/kernel/signal.c return base + offset; base 329 arch/arm64/kernel/signal.c char __user *base = (char __user *)&sc->__reserved; base 338 arch/arm64/kernel/signal.c if (!IS_ALIGNED((unsigned long)base, 16)) base 357 arch/arm64/kernel/signal.c head = (struct _aarch64_ctx __user *)(base + offset); base 436 arch/arm64/kernel/signal.c base = (__force void __user *)extra_datap; base 437 arch/arm64/kernel/signal.c if (!IS_ALIGNED((unsigned long)base, 16)) base 443 arch/arm64/kernel/signal.c if (base != userp) base 457 arch/arm64/kernel/signal.c if (!access_ok(base, limit)) base 290 arch/arm64/mm/init.c usablemem->base = dt_mem_next_cell(dt_root_addr_cells, ®); base 305 arch/arm64/mm/init.c memblock_cap_memory_range(reg.base, reg.size); base 368 arch/arm64/mm/init.c u64 base = phys_initrd_start & PAGE_MASK; base 369 arch/arm64/mm/init.c u64 size = PAGE_ALIGN(phys_initrd_start + phys_initrd_size) - base; base 379 arch/arm64/mm/init.c if (WARN(base < memblock_start_of_DRAM() || base 380 arch/arm64/mm/init.c base + size > memblock_start_of_DRAM() + base 385 arch/arm64/mm/init.c memblock_remove(base, size); /* clear MEMBLOCK_ flags */ base 386 arch/arm64/mm/init.c memblock_add(base, size); base 387 arch/arm64/mm/init.c memblock_reserve(base, size); base 497 arch/arm64/mm/init.c start = __phys_to_pfn(reg->base); base 518 arch/arm64/mm/init.c prev_end = ALIGN(__phys_to_pfn(reg->base + reg->size), base 239 arch/arm64/mm/kasan_init.c void *start = (void *)__phys_to_virt(reg->base); base 240 arch/arm64/mm/kasan_init.c void *end = (void *)__phys_to_virt(reg->base + reg->size); base 484 arch/arm64/mm/mmu.c phys_addr_t start = reg->base; base 356 arch/arm64/mm/numa.c mblk->nid, mblk->base, base 357 arch/arm64/mm/numa.c mblk->base + mblk->size - 1); base 432 arch/arm64/mm/numa.c ret = numa_add_memblk(0, mblk->base, mblk->base + mblk->size); base 106 arch/c6x/include/asm/clock.h void __iomem *base; base 11 arch/c6x/kernel/devicetree.c void __init early_init_dt_add_memory_arch(u64 base, u64 size) base 13 arch/c6x/kernel/devicetree.c c6x_add_memory(base, size); base 355 arch/c6x/kernel/setup.c enable_caching(CACHE_REGION_START(reg->base), base 356 arch/c6x/kernel/setup.c CACHE_REGION_START(reg->base + reg->size - 1)); base 104 arch/c6x/platforms/dscr.c void __iomem *base; base 132 arch/c6x/platforms/dscr.c void __iomem *reg_addr = dscr.base + reg; base 133 arch/c6x/platforms/dscr.c void __iomem *lock_addr = dscr.base + lock; base 162 arch/c6x/platforms/dscr.c soc_writel(key0, dscr.base + lock0); base 163 arch/c6x/platforms/dscr.c soc_writel(key1, dscr.base + lock1); base 164 arch/c6x/platforms/dscr.c soc_writel(val, dscr.base + reg); base 165 arch/c6x/platforms/dscr.c soc_writel(0, dscr.base + lock0); base 166 arch/c6x/platforms/dscr.c soc_writel(0, dscr.base + lock1); base 180 arch/c6x/platforms/dscr.c soc_writel(val, dscr.base + reg); base 196 arch/c6x/platforms/dscr.c if (!dscr.base) base 227 arch/c6x/platforms/dscr.c val = soc_readl(dscr.base + ctl->reg); base 246 arch/c6x/platforms/dscr.c val = soc_readl(dscr.base + stat->reg); base 271 arch/c6x/platforms/dscr.c val = soc_readl(dscr.base + r->reg); base 282 arch/c6x/platforms/dscr.c void __iomem *base) base 289 arch/c6x/platforms/dscr.c c6x_devstat = soc_readl(base + val); base 294 arch/c6x/platforms/dscr.c void __iomem *base) base 301 arch/c6x/platforms/dscr.c c6x_silicon_rev = soc_readl(base + vals[0]); base 325 arch/c6x/platforms/dscr.c void __iomem *base) base 336 arch/c6x/platforms/dscr.c fuse = soc_readl(base + vals[f * 5]); base 344 arch/c6x/platforms/dscr.c void __iomem *base) base 366 arch/c6x/platforms/dscr.c void __iomem *base) base 394 arch/c6x/platforms/dscr.c void __iomem *base) base 429 arch/c6x/platforms/dscr.c void __iomem *base) base 467 arch/c6x/platforms/dscr.c void __iomem *base) base 523 arch/c6x/platforms/dscr.c void __iomem *base) base 570 arch/c6x/platforms/dscr.c void __iomem *base; base 578 arch/c6x/platforms/dscr.c base = of_iomap(node, 0); base 579 arch/c6x/platforms/dscr.c if (!base) { base 584 arch/c6x/platforms/dscr.c dscr.base = base; base 586 arch/c6x/platforms/dscr.c dscr_parse_devstat(node, base); base 587 arch/c6x/platforms/dscr.c dscr_parse_silicon_rev(node, base); base 588 arch/c6x/platforms/dscr.c dscr_parse_mac_fuse(node, base); base 589 arch/c6x/platforms/dscr.c dscr_parse_rmii_resets(node, base); base 590 arch/c6x/platforms/dscr.c dscr_parse_locked_regs(node, base); base 591 arch/c6x/platforms/dscr.c dscr_parse_kick_regs(node, base); base 592 arch/c6x/platforms/dscr.c dscr_parse_devstate_ctl_regs(node, base); base 593 arch/c6x/platforms/dscr.c dscr_parse_devstate_stat_regs(node, base); base 594 arch/c6x/platforms/dscr.c dscr_parse_privperm(node, base); base 202 arch/c6x/platforms/pll.c return soc_readl(pll->base + reg); base 431 arch/c6x/platforms/plldata.c pll->base = of_iomap(node, 0); base 432 arch/c6x/platforms/plldata.c if (!pll->base) base 31 arch/h8300/kernel/irq.c unsigned long base, tmp; base 34 arch/h8300/kernel/irq.c base = rom_vector[EXT_IRQ0] & ADDR_MASK; base 38 arch/h8300/kernel/irq.c if ((base+(vec_no - EXT_IRQ0)*4) != base 44 arch/h8300/kernel/irq.c base -= EXT_IRQ0*4; base 47 arch/h8300/kernel/irq.c tmp = ~(*(volatile unsigned long *)base); base 48 arch/h8300/kernel/irq.c (*(volatile unsigned long *)base) = tmp; base 49 arch/h8300/kernel/irq.c if ((*(volatile unsigned long *)base) != tmp) base 51 arch/h8300/kernel/irq.c return (unsigned long *)base; base 79 arch/h8300/kernel/setup.c memory_start = region->base; base 80 arch/h8300/kernel/setup.c memory_end = region->base + region->size; base 171 arch/h8300/kernel/setup.c #define get_wait(base, addr) ({ \ base 174 arch/h8300/kernel/setup.c w *= (readw((base) + 2) & (3 << baddr)) + 1; \ base 178 arch/h8300/kernel/setup.c #define get_wait(base, addr) ({ \ base 181 arch/h8300/kernel/setup.c w *= (readl((base) + 2) & (7 << baddr)) + 1; \ base 188 arch/h8300/kernel/setup.c void __iomem *base; base 194 arch/h8300/kernel/setup.c base = of_iomap(bsc, 0); base 195 arch/h8300/kernel/setup.c w = (readb(base + 0) & bit)?2:1; base 196 arch/h8300/kernel/setup.c if (readb(base + 1) & bit) base 197 arch/h8300/kernel/setup.c w *= get_wait(base, addr); base 15 arch/ia64/include/asm/acpi-ext.h extern acpi_status hp_acpi_csr_space (acpi_handle, u64 *base, u64 *length); base 1440 arch/ia64/include/asm/pal.h unsigned long base; base 1458 arch/ia64/include/asm/pal.h ptce->base = iprv.v0; base 550 arch/ia64/include/asm/uv/uv_mmrs.h unsigned long base : 18; /* RW */ base 576 arch/ia64/include/asm/uv/uv_mmrs.h unsigned long base : 20; /* RW */ base 768 arch/ia64/include/asm/uv/uv_mmrs.h unsigned long base : 8; /* RW */ base 792 arch/ia64/include/asm/uv/uv_mmrs.h unsigned long base : 8; /* RW */ base 816 arch/ia64/include/asm/uv/uv_mmrs.h unsigned long base : 8; /* RW */ base 29 arch/ia64/kernel/acpi-ext.c static acpi_status hp_ccsr_locate(acpi_handle obj, u64 *base, u64 *length) base 47 arch/ia64/kernel/acpi-ext.c memcpy(base, vendor->byte_data, sizeof(*base)); base 56 arch/ia64/kernel/acpi-ext.c u64 base; base 71 arch/ia64/kernel/acpi-ext.c space->base = addr.address.minimum; base 78 arch/ia64/kernel/acpi-ext.c static acpi_status hp_crs_locate(acpi_handle obj, u64 *base, u64 *length) base 86 arch/ia64/kernel/acpi-ext.c *base = space.base; base 41 arch/ia64/kernel/cyclone.c u64 base; /* saved cyclone base address */ base 60 arch/ia64/kernel/cyclone.c base = readq(reg); base 62 arch/ia64/kernel/cyclone.c if(!base){ base 70 arch/ia64/kernel/cyclone.c offset = (base + CYCLONE_PMCC_OFFSET); base 82 arch/ia64/kernel/cyclone.c offset = (base + CYCLONE_MPCS_OFFSET); base 94 arch/ia64/kernel/cyclone.c offset = (base + CYCLONE_MPMC_OFFSET); base 989 arch/ia64/kernel/iosapic.c unsigned int gsi_end, base, end; base 997 arch/ia64/kernel/iosapic.c base = iosapic_lists[index].gsi_base; base 998 arch/ia64/kernel/iosapic.c end = base + iosapic_lists[index].num_rte - 1; base 1000 arch/ia64/kernel/iosapic.c if (gsi_end < base || end < gsi_base) base 491 arch/ia64/kernel/module.c return addr - (uint64_t) mod->init_layout.base < mod->init_layout.size; base 497 arch/ia64/kernel/module.c return addr - (uint64_t) mod->core_layout.base < mod->core_layout.size; base 680 arch/ia64/kernel/module.c val -= (uint64_t) (in_init(mod, val) ? mod->init_layout.base : mod->core_layout.base); base 823 arch/ia64/kernel/module.c gp = (uint64_t) mod->core_layout.base + ((gp + 7) & -8); base 369 arch/ia64/kernel/palinfo.c ptce.base, ptce.count[0], ptce.count[1], base 694 arch/ia64/kernel/palinfo.c unsigned long base; base 696 arch/ia64/kernel/palinfo.c if (ia64_pal_freq_base(&base) == -1) base 699 arch/ia64/kernel/palinfo.c seq_printf(m, "Output clock : %ld ticks/s\n", base); base 278 arch/ia64/kernel/setup.c unsigned long long base = 0, size = 0; base 282 arch/ia64/kernel/setup.c &size, &base); base 284 arch/ia64/kernel/setup.c if (!base) { base 287 arch/ia64/kernel/setup.c base = kdump_find_rsvd_region(size, base 291 arch/ia64/kernel/setup.c if (!check_crashkernel_memory(base, size)) { base 296 arch/ia64/kernel/setup.c (unsigned long)(base >> 30)); base 300 arch/ia64/kernel/setup.c if (base != ~0UL) { base 304 arch/ia64/kernel/setup.c (unsigned long)(base >> 20), base 307 arch/ia64/kernel/setup.c (unsigned long)__va(base); base 309 arch/ia64/kernel/setup.c (unsigned long)__va(base + size); base 311 arch/ia64/kernel/setup.c crashk_res.start = base; base 312 arch/ia64/kernel/setup.c crashk_res.end = base + size - 1; base 908 arch/ia64/kernel/unwind.c int base = (i < 4) ? UNW_REG_F2 : UNW_REG_F16 - 4; base 909 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + base + i, UNW_WHERE_SPILL_HOME, base 185 arch/ia64/mm/discontig.c void *base; base 197 arch/ia64/mm/discontig.c base = (void *)ULONG_MAX; base 199 arch/ia64/mm/discontig.c base = min(base, base 201 arch/ia64/mm/discontig.c base_offset = (void *)__per_cpu_start - base; base 248 arch/ia64/mm/discontig.c pcpu_setup_first_chunk(ai, base); base 356 arch/ia64/mm/discontig.c unsigned long base, size; base 365 arch/ia64/mm/discontig.c base = __pa(mem_data[node].pernode_addr); base 366 arch/ia64/mm/discontig.c memblock_reserve(base, size); base 387 arch/ia64/mm/tlb.c local_cpu_data->ptce_base = ptce_info.base; base 157 arch/ia64/pci/pci.c unsigned long base, min, max, base_port; base 177 arch/ia64/pci/pci.c base = __pa(io_space[space_nr].mmio_base); base 193 arch/ia64/pci/pci.c resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min); base 194 arch/ia64/pci/pci.c resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max); base 38 arch/ia64/uv/kernel/setup.c static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) base 46 arch/ia64/uv/kernel/setup.c if (alias.s.base == 0) { base 49 arch/ia64/uv/kernel/setup.c *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; base 51 arch/m68k/amiga/cia.c unsigned char cia_set_irq(struct ciabase *base, unsigned char mask) base 55 arch/m68k/amiga/cia.c old = (base->icr_data |= base->cia->icr); base 57 arch/m68k/amiga/cia.c base->icr_data |= mask; base 59 arch/m68k/amiga/cia.c base->icr_data &= ~mask; base 60 arch/m68k/amiga/cia.c if (base->icr_data & base->icr_mask) base 61 arch/m68k/amiga/cia.c amiga_custom.intreq = IF_SETCLR | base->int_mask; base 62 arch/m68k/amiga/cia.c return old & base->icr_mask; base 69 arch/m68k/amiga/cia.c unsigned char cia_able_irq(struct ciabase *base, unsigned char mask) base 73 arch/m68k/amiga/cia.c old = base->icr_mask; base 74 arch/m68k/amiga/cia.c base->icr_data |= base->cia->icr; base 75 arch/m68k/amiga/cia.c base->cia->icr = mask; base 77 arch/m68k/amiga/cia.c base->icr_mask |= mask; base 79 arch/m68k/amiga/cia.c base->icr_mask &= ~mask; base 80 arch/m68k/amiga/cia.c base->icr_mask &= CIA_ICR_ALL; base 81 arch/m68k/amiga/cia.c if (base->icr_data & base->icr_mask) base 82 arch/m68k/amiga/cia.c amiga_custom.intreq = IF_SETCLR | base->int_mask; base 88 arch/m68k/amiga/cia.c struct ciabase *base = dev_id; base 96 arch/m68k/amiga/cia.c mach_irq = base->cia_irq; base 98 arch/m68k/amiga/cia.c ints = cia_set_irq(base, CIA_ICR_ALL); base 99 arch/m68k/amiga/cia.c amiga_custom.intreq = base->int_mask; base 179 arch/m68k/amiga/cia.c void __init cia_init_IRQ(struct ciabase *base) base 182 arch/m68k/amiga/cia.c base->cia_irq, CIA_IRQS); base 185 arch/m68k/amiga/cia.c cia_set_irq(base, CIA_ICR_ALL); base 186 arch/m68k/amiga/cia.c cia_able_irq(base, CIA_ICR_ALL); base 190 arch/m68k/amiga/cia.c base->handler_irq, 1); base 191 arch/m68k/amiga/cia.c m68k_irq_startup_irq(base->handler_irq); base 192 arch/m68k/amiga/cia.c if (request_irq(base->handler_irq, cia_handler, IRQF_SHARED, base 193 arch/m68k/amiga/cia.c base->name, base)) base 194 arch/m68k/amiga/cia.c pr_err("Couldn't register %s interrupt\n", base->name); base 108 arch/m68k/amiga/platform.c .base = 0xda0000, base 121 arch/m68k/amiga/platform.c .base = 0xdd2020, base 147 arch/m68k/atari/ataints.c struct mfptimerbase *base = dev_id; base 151 arch/m68k/atari/ataints.c mach_irq = base->mfptimer_irq; base 152 arch/m68k/atari/ataints.c ints = base->int_mask; base 163 arch/m68k/coldfire/gpio.c .base = 0, base 80 arch/m68k/fpsp040/fpsp.h .set LV,-LOCAL_SIZE | convenient base value base 109 arch/m68k/include/asm/amigaints.h extern void cia_init_IRQ(struct ciabase *base); base 110 arch/m68k/include/asm/amigaints.h extern unsigned char cia_set_irq(struct ciabase *base, unsigned char mask); base 111 arch/m68k/include/asm/amigaints.h extern unsigned char cia_able_irq(struct ciabase *base, unsigned char mask); base 108 arch/m68k/include/asm/amigayle.h unsigned long base; base 13 arch/m68k/include/asm/div64.h #define do_div(n, base) ({ \ base 19 arch/m68k/include/asm/div64.h unsigned long __base = (base); \ base 167 arch/m68k/math-emu/fp_decode.h | decode the base displacement size base 196 arch/m68k/math-emu/fp_decode.h | test if %pc is the base register for the indirect addr mode base 202 arch/m68k/math-emu/fp_decode.h | test if %pc is the base register for one of the extended modes base 356 arch/m68k/math-emu/fp_decode.h | with base and/or outer displacement base 357 arch/m68k/math-emu/fp_decode.h btst #7,%d2 | base register suppressed? base 368 arch/m68k/math-emu/fp_decode.h 1: printf PDECODE,"0" | null base displacement base 371 arch/m68k/math-emu/fp_decode.h 2: fp_get_instr_word %a0,fp_err_ua1 | 16bit base displacement base 374 arch/m68k/math-emu/fp_decode.h 3: fp_get_instr_long %a0,fp_err_ua1 | 32bit base displacement base 123 arch/microblaze/mm/init.c memory_start = (u32)reg->base; base 295 arch/microblaze/mm/init.c memory_start = (u32) memblock.memory.regions[0].base; base 148 arch/microblaze/pci/indirect_pci.c resource_size_t base = cfg_addr & PAGE_MASK; base 151 arch/microblaze/pci/indirect_pci.c mbase = ioremap(base, PAGE_SIZE); base 153 arch/microblaze/pci/indirect_pci.c if ((cfg_data & PAGE_MASK) != base) base 113 arch/microblaze/pci/pci-common.c unsigned long base = base 115 arch/microblaze/pci/pci-common.c ret = base + (address - hose->io_base_phys); base 89 arch/mips/alchemy/common/clock.c char *base; base 1098 arch/mips/alchemy/common/clock.c while (t->base) { base 1100 arch/mips/alchemy/common/clock.c clk_add_alias(t->alias, NULL, t->base, NULL); base 241 arch/mips/alchemy/common/dma.c int base, i; base 245 arch/mips/alchemy/common/dma.c base = AU1000_DMA_INT_BASE; base 248 arch/mips/alchemy/common/dma.c base = AU1500_DMA_INT_BASE; base 251 arch/mips/alchemy/common/dma.c base = AU1100_DMA_INT_BASE; base 258 arch/mips/alchemy/common/dma.c au1000_dma_table[i].irq = base + i; base 104 arch/mips/alchemy/common/gpiolib.c .base = ALCHEMY_GPIO1_BASE, base 114 arch/mips/alchemy/common/gpiolib.c .base = ALCHEMY_GPIO2_BASE, base 152 arch/mips/alchemy/common/gpiolib.c .base = AU1300_GPIO_BASE, base 291 arch/mips/alchemy/common/irq.c void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); base 293 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_MASKSET); base 294 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_WAKESET); base 301 arch/mips/alchemy/common/irq.c void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); base 303 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_MASKSET); base 304 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_WAKESET); base 311 arch/mips/alchemy/common/irq.c void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); base 313 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_MASKCLR); base 314 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_WAKECLR); base 321 arch/mips/alchemy/common/irq.c void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); base 323 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_MASKCLR); base 324 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_WAKECLR); base 331 arch/mips/alchemy/common/irq.c void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); base 337 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_FALLINGCLR); base 338 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_RISINGCLR); base 345 arch/mips/alchemy/common/irq.c void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); base 351 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_FALLINGCLR); base 352 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_RISINGCLR); base 359 arch/mips/alchemy/common/irq.c void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); base 361 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_WAKECLR); base 362 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_MASKCLR); base 363 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_RISINGCLR); base 364 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_FALLINGCLR); base 371 arch/mips/alchemy/common/irq.c void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); base 373 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_WAKECLR); base 374 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_MASKCLR); base 375 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_RISINGCLR); base 376 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_FALLINGCLR); base 432 arch/mips/alchemy/common/irq.c void __iomem *base; base 438 arch/mips/alchemy/common/irq.c base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); base 442 arch/mips/alchemy/common/irq.c base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); base 452 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG2CLR); base 453 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG1CLR); base 454 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG0SET); base 459 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG2CLR); base 460 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG1SET); base 461 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG0CLR); base 466 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG2CLR); base 467 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG1SET); base 468 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG0SET); base 473 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG2SET); base 474 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG1CLR); base 475 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG0SET); base 480 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG2SET); base 481 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG1SET); base 482 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG0CLR); base 487 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG2CLR); base 488 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG1CLR); base 489 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_CFG0CLR); base 715 arch/mips/alchemy/common/irq.c static inline void ic_init(void __iomem *base) base 718 arch/mips/alchemy/common/irq.c __raw_writel(0xffffffff, base + IC_CFG0CLR); base 719 arch/mips/alchemy/common/irq.c __raw_writel(0xffffffff, base + IC_CFG1CLR); base 720 arch/mips/alchemy/common/irq.c __raw_writel(0xffffffff, base + IC_CFG2CLR); base 721 arch/mips/alchemy/common/irq.c __raw_writel(0xffffffff, base + IC_MASKCLR); base 722 arch/mips/alchemy/common/irq.c __raw_writel(0xffffffff, base + IC_ASSIGNCLR); base 723 arch/mips/alchemy/common/irq.c __raw_writel(0xffffffff, base + IC_WAKECLR); base 724 arch/mips/alchemy/common/irq.c __raw_writel(0xffffffff, base + IC_SRCSET); base 725 arch/mips/alchemy/common/irq.c __raw_writel(0xffffffff, base + IC_FALLINGCLR); base 726 arch/mips/alchemy/common/irq.c __raw_writel(0xffffffff, base + IC_RISINGCLR); base 727 arch/mips/alchemy/common/irq.c __raw_writel(0x00000000, base + IC_TESTBIT); base 733 arch/mips/alchemy/common/irq.c static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d) base 735 arch/mips/alchemy/common/irq.c d[0] = __raw_readl(base + IC_CFG0RD); base 736 arch/mips/alchemy/common/irq.c d[1] = __raw_readl(base + IC_CFG1RD); base 737 arch/mips/alchemy/common/irq.c d[2] = __raw_readl(base + IC_CFG2RD); base 738 arch/mips/alchemy/common/irq.c d[3] = __raw_readl(base + IC_SRCRD); base 739 arch/mips/alchemy/common/irq.c d[4] = __raw_readl(base + IC_ASSIGNRD); base 740 arch/mips/alchemy/common/irq.c d[5] = __raw_readl(base + IC_WAKERD); base 741 arch/mips/alchemy/common/irq.c d[6] = __raw_readl(base + IC_MASKRD); base 742 arch/mips/alchemy/common/irq.c ic_init(base); /* shut it up too while at it */ base 745 arch/mips/alchemy/common/irq.c static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) base 747 arch/mips/alchemy/common/irq.c ic_init(base); base 749 arch/mips/alchemy/common/irq.c __raw_writel(d[0], base + IC_CFG0SET); base 750 arch/mips/alchemy/common/irq.c __raw_writel(d[1], base + IC_CFG1SET); base 751 arch/mips/alchemy/common/irq.c __raw_writel(d[2], base + IC_CFG2SET); base 752 arch/mips/alchemy/common/irq.c __raw_writel(d[3], base + IC_SRCSET); base 753 arch/mips/alchemy/common/irq.c __raw_writel(d[4], base + IC_ASSIGNSET); base 754 arch/mips/alchemy/common/irq.c __raw_writel(d[5], base + IC_WAKESET); base 757 arch/mips/alchemy/common/irq.c __raw_writel(d[6], base + IC_MASKSET); base 780 arch/mips/alchemy/common/irq.c void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); base 784 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0); base 785 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4); base 786 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8); base 787 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc); base 790 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL); base 793 arch/mips/alchemy/common/irq.c __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); base 794 arch/mips/alchemy/common/irq.c __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); base 795 arch/mips/alchemy/common/irq.c __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); base 796 arch/mips/alchemy/common/irq.c __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); base 800 arch/mips/alchemy/common/irq.c base += AU1300_GPIC_PINCFG; base 802 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2)); base 811 arch/mips/alchemy/common/irq.c void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); base 815 arch/mips/alchemy/common/irq.c __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); base 816 arch/mips/alchemy/common/irq.c __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); base 817 arch/mips/alchemy/common/irq.c __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); base 818 arch/mips/alchemy/common/irq.c __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); base 822 arch/mips/alchemy/common/irq.c base += AU1300_GPIC_PINCFG; base 824 arch/mips/alchemy/common/irq.c __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2)); base 828 arch/mips/alchemy/common/irq.c base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); base 829 arch/mips/alchemy/common/irq.c __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL); base 833 arch/mips/alchemy/common/irq.c __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0); base 834 arch/mips/alchemy/common/irq.c __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4); base 835 arch/mips/alchemy/common/irq.c __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8); base 836 arch/mips/alchemy/common/irq.c __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc); base 853 arch/mips/alchemy/common/irq.c #define DISP(name, base, addr) \ base 858 arch/mips/alchemy/common/irq.c generic_handle_irq(base + __ffs(r)); \ base 879 arch/mips/alchemy/common/irq.c void __iomem *base; base 905 arch/mips/alchemy/common/irq.c base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); base 908 arch/mips/alchemy/common/irq.c base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); base 911 arch/mips/alchemy/common/irq.c __raw_writel(1 << bit, base + IC_ASSIGNSET); base 98 arch/mips/alchemy/common/usb.c static inline void __au1300_usb_phyctl(void __iomem *base, int enable) base 102 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL2); base 103 arch/mips/alchemy/common/usb.c s = __raw_readl(base + USB_DWC_CTRL3); base 112 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL2); base 118 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL2); base 123 arch/mips/alchemy/common/usb.c static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) base 128 arch/mips/alchemy/common/usb.c __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ base 131 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ base 134 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL3); base 137 arch/mips/alchemy/common/usb.c __au1300_usb_phyctl(base, enable); /* power up the PHYs */ base 139 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); base 141 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_INT_ENABLE); base 145 arch/mips/alchemy/common/usb.c __raw_writel(0, base + USB_DWC_CTRL7); base 148 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); base 150 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_INT_ENABLE); base 153 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); base 156 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL3); base 159 arch/mips/alchemy/common/usb.c __au1300_usb_phyctl(base, enable); base 163 arch/mips/alchemy/common/usb.c static inline void __au1300_ehci_control(void __iomem *base, int enable) base 168 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); base 170 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL3); base 173 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); base 175 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL1); base 178 arch/mips/alchemy/common/usb.c __au1300_usb_phyctl(base, enable); base 180 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); base 182 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_INT_ENABLE); base 185 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); base 187 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_INT_ENABLE); base 190 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); base 192 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL1); base 195 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); base 197 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL3); base 200 arch/mips/alchemy/common/usb.c __au1300_usb_phyctl(base, enable); base 204 arch/mips/alchemy/common/usb.c static inline void __au1300_udc_control(void __iomem *base, int enable) base 209 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); base 211 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL1); base 214 arch/mips/alchemy/common/usb.c __au1300_usb_phyctl(base, enable); base 216 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); base 218 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_INT_ENABLE); base 221 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); base 223 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_INT_ENABLE); base 226 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); base 228 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL1); base 231 arch/mips/alchemy/common/usb.c __au1300_usb_phyctl(base, enable); base 235 arch/mips/alchemy/common/usb.c static inline void __au1300_otg_control(void __iomem *base, int enable) base 239 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); base 241 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL3); base 244 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); base 246 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL1); base 249 arch/mips/alchemy/common/usb.c __au1300_usb_phyctl(base, enable); base 251 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); base 253 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL1); base 256 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); base 258 arch/mips/alchemy/common/usb.c __raw_writel(r, base + USB_DWC_CTRL3); base 261 arch/mips/alchemy/common/usb.c __au1300_usb_phyctl(base, enable); base 267 arch/mips/alchemy/common/usb.c void __iomem *base = base 273 arch/mips/alchemy/common/usb.c __au1300_ohci_control(base, enable, 0); base 276 arch/mips/alchemy/common/usb.c __au1300_ohci_control(base, enable, 1); base 279 arch/mips/alchemy/common/usb.c __au1300_ehci_control(base, enable); base 282 arch/mips/alchemy/common/usb.c __au1300_udc_control(base, enable); base 285 arch/mips/alchemy/common/usb.c __au1300_otg_control(base, enable); base 295 arch/mips/alchemy/common/usb.c void __iomem *base = base 303 arch/mips/alchemy/common/usb.c __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */ base 305 arch/mips/alchemy/common/usb.c __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */ base 307 arch/mips/alchemy/common/usb.c __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */ base 309 arch/mips/alchemy/common/usb.c __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */ base 312 arch/mips/alchemy/common/usb.c __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL); base 316 arch/mips/alchemy/common/usb.c static inline void __au1200_ohci_control(void __iomem *base, int enable) base 318 arch/mips/alchemy/common/usb.c unsigned long r = __raw_readl(base + AU1200_USBCFG); base 320 arch/mips/alchemy/common/usb.c __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG); base 324 arch/mips/alchemy/common/usb.c __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG); base 330 arch/mips/alchemy/common/usb.c static inline void __au1200_ehci_control(void __iomem *base, int enable) base 332 arch/mips/alchemy/common/usb.c unsigned long r = __raw_readl(base + AU1200_USBCFG); base 334 arch/mips/alchemy/common/usb.c __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG); base 340 arch/mips/alchemy/common/usb.c __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG); base 346 arch/mips/alchemy/common/usb.c static inline void __au1200_udc_control(void __iomem *base, int enable) base 348 arch/mips/alchemy/common/usb.c unsigned long r = __raw_readl(base + AU1200_USBCFG); base 350 arch/mips/alchemy/common/usb.c __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG); base 355 arch/mips/alchemy/common/usb.c __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG); base 362 arch/mips/alchemy/common/usb.c void __iomem *base = base 367 arch/mips/alchemy/common/usb.c __au1200_ohci_control(base, enable); base 370 arch/mips/alchemy/common/usb.c __au1200_udc_control(base, enable); base 373 arch/mips/alchemy/common/usb.c __au1200_ehci_control(base, enable); base 385 arch/mips/alchemy/common/usb.c void __iomem *base = base 387 arch/mips/alchemy/common/usb.c __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG); base 394 arch/mips/alchemy/common/usb.c void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); base 395 arch/mips/alchemy/common/usb.c unsigned long r = __raw_readl(base); base 417 arch/mips/alchemy/common/usb.c __raw_writel(r, base); base 427 arch/mips/alchemy/common/usb.c void __iomem *base = (void __iomem *)KSEG1ADDR(rb); base 428 arch/mips/alchemy/common/usb.c unsigned long r = __raw_readl(base + creg); base 438 arch/mips/alchemy/common/usb.c __raw_writel(r | USBHEN_CE, base + creg); base 441 arch/mips/alchemy/common/usb.c __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg); base 446 arch/mips/alchemy/common/usb.c while (__raw_readl(base + creg), base 447 arch/mips/alchemy/common/usb.c !(__raw_readl(base + creg) & USBHEN_RD)) base 450 arch/mips/alchemy/common/usb.c __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg); base 514 arch/mips/alchemy/common/usb.c void __iomem *base = (void __iomem *)KSEG1ADDR(br); base 517 arch/mips/alchemy/common/usb.c alchemy_usb_pmdata[0] = __raw_readl(base + creg); base 519 arch/mips/alchemy/common/usb.c __raw_writel(0, base + 0x04); base 521 arch/mips/alchemy/common/usb.c __raw_writel(0, base + creg); base 524 arch/mips/alchemy/common/usb.c __raw_writel(alchemy_usb_pmdata[0], base + creg); base 531 arch/mips/alchemy/common/usb.c void __iomem *base = base 536 arch/mips/alchemy/common/usb.c alchemy_usb_pmdata[0] = __raw_readl(base + 0x00); base 537 arch/mips/alchemy/common/usb.c alchemy_usb_pmdata[1] = __raw_readl(base + 0x04); base 543 arch/mips/alchemy/common/usb.c __raw_writel(alchemy_usb_pmdata[0], base + 0x00); base 544 arch/mips/alchemy/common/usb.c __raw_writel(alchemy_usb_pmdata[1], base + 0x04); base 551 arch/mips/alchemy/common/usb.c void __iomem *base = base 555 arch/mips/alchemy/common/usb.c alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4); base 558 arch/mips/alchemy/common/usb.c __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4); base 25 arch/mips/alchemy/common/vss.c void __iomem *base = (void __iomem *)VSS_ADDR(block); base 27 arch/mips/alchemy/common/vss.c __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ base 30 arch/mips/alchemy/common/vss.c __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ base 34 arch/mips/alchemy/common/vss.c __raw_writel(0x01, base + VSS_FTR); base 36 arch/mips/alchemy/common/vss.c __raw_writel(0x03, base + VSS_FTR); base 38 arch/mips/alchemy/common/vss.c __raw_writel(0x07, base + VSS_FTR); base 40 arch/mips/alchemy/common/vss.c __raw_writel(0x0f, base + VSS_FTR); base 43 arch/mips/alchemy/common/vss.c __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ base 46 arch/mips/alchemy/common/vss.c __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ base 49 arch/mips/alchemy/common/vss.c __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ base 56 arch/mips/alchemy/common/vss.c void __iomem *base = (void __iomem *)VSS_ADDR(block); base 58 arch/mips/alchemy/common/vss.c __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */ base 60 arch/mips/alchemy/common/vss.c __raw_writel(0, base + VSS_GATE); /* disable FSM */ base 62 arch/mips/alchemy/common/vss.c __raw_writel(3, base + VSS_CLKRST); /* assert reset */ base 64 arch/mips/alchemy/common/vss.c __raw_writel(1, base + VSS_CLKRST); /* disable clock */ base 66 arch/mips/alchemy/common/vss.c __raw_writel(0, base + VSS_FTR); /* disable all footers */ base 35 arch/mips/alchemy/devboards/db1550.c void __iomem *base; base 47 arch/mips/alchemy/devboards/db1550.c base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR); base 49 arch/mips/alchemy/devboards/db1550.c base + PSC_SEL_OFFSET); base 50 arch/mips/alchemy/devboards/db1550.c __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET); base 52 arch/mips/alchemy/devboards/db1550.c __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET); base 98 arch/mips/ar7/clock.c static void approximate(int base, int target, int *prediv, base 105 arch/mips/ar7/clock.c freq = abs(base / j * i / k - target); base 115 arch/mips/ar7/clock.c static void calculate(int base, int target, int *prediv, int *postdiv, base 121 arch/mips/ar7/clock.c tmp_base = base / *prediv; base 131 arch/mips/ar7/clock.c if (base / *prediv * *mul / *postdiv != target) { base 132 arch/mips/ar7/clock.c approximate(base, target, prediv, postdiv, mul); base 133 arch/mips/ar7/clock.c tmp_freq = base / *prediv * *mul / *postdiv; base 261 arch/mips/ar7/clock.c static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock, base 267 arch/mips/ar7/clock.c base, frequency, prediv, postdiv, postdiv2, mul); base 126 arch/mips/ar7/gpio.c .base = 0, base 138 arch/mips/ar7/gpio.c .base = 0, base 92 arch/mips/ar7/irq.c static void __init ar7_irq_init(int base) base 105 arch/mips/ar7/irq.c ar7_irq_base = base; base 110 arch/mips/ar7/irq.c irq_set_chip_and_handler(base + i, &ar7_irq_type, base 114 arch/mips/ar7/irq.c irq_set_chip_and_handler(base + i + 40, base 102 arch/mips/ath25/board.c int __init ath25_find_config(phys_addr_t base, unsigned long size) base 114 arch/mips/ath25/board.c flash_base = ioremap_nocache(base, size); base 92 arch/mips/ath25/devices.c int __init ath25_add_wmac(int nr, u32 base, int irq) base 98 arch/mips/ath25/devices.c res->start = base; base 99 arch/mips/ath25/devices.c res->end = base + 0x10000 - 1; base 32 arch/mips/ath25/devices.h int ath25_add_wmac(int nr, u32 base, int irq); base 18 arch/mips/ath25/early_printk.c static inline void prom_uart_wr(void __iomem *base, unsigned reg, base 21 arch/mips/ath25/early_printk.c __raw_writel(ch, base + 4 * reg); base 24 arch/mips/ath25/early_printk.c static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) base 26 arch/mips/ath25/early_printk.c return __raw_readl(base + 4 * reg); base 31 arch/mips/ath25/early_printk.c static void __iomem *base; base 33 arch/mips/ath25/early_printk.c if (unlikely(base == NULL)) { base 35 arch/mips/ath25/early_printk.c base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE)); base 37 arch/mips/ath25/early_printk.c base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE)); base 40 arch/mips/ath25/early_printk.c while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) base 42 arch/mips/ath25/early_printk.c prom_uart_wr(base, UART_TX, (unsigned char)ch); base 43 arch/mips/ath25/early_printk.c while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) base 36 arch/mips/ath79/early_printk.c void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); base 38 arch/mips/ath79/early_printk.c prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY); base 39 arch/mips/ath79/early_printk.c __raw_writel((unsigned char)ch, base + UART_TX * 4); base 40 arch/mips/ath79/early_printk.c prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY); base 45 arch/mips/ath79/early_printk.c void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE)); base 47 arch/mips/ath79/early_printk.c prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, base 50 arch/mips/ath79/early_printk.c base + AR933X_UART_DATA_REG); base 51 arch/mips/ath79/early_printk.c prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, base 102 arch/mips/ath79/early_printk.c void __iomem *base; base 105 arch/mips/ath79/early_printk.c base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE)); base 106 arch/mips/ath79/early_printk.c id = __raw_readl(base + AR71XX_RESET_REG_REV_ID); base 35 arch/mips/bcm63xx/cs.c int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size) base 50 arch/mips/bcm63xx/cs.c val = (base & MPI_CSBASE_BASE_MASK); base 70 arch/mips/bcm63xx/dev-pcmcia.c u32 base, unsigned int size) base 76 arch/mips/bcm63xx/dev-pcmcia.c ret = bcm63xx_set_cs_base(cs, base, size); base 84 arch/mips/bcm63xx/dev-pcmcia.c unsigned int base; base 89 arch/mips/bcm63xx/dev-pcmcia.c .base = BCM_PCMCIA_COMMON_BASE_PA, base 94 arch/mips/bcm63xx/dev-pcmcia.c .base = BCM_PCMCIA_ATTR_BASE_PA, base 99 arch/mips/bcm63xx/dev-pcmcia.c .base = BCM_PCMCIA_IO_BASE_PA, base 133 arch/mips/bcm63xx/dev-pcmcia.c pcmcia_cs[i].base, base 137 arch/mips/bcm63xx/gpio.c .base = 0, base 102 arch/mips/boot/elf2ecoff.c static void combine(struct sect *base, struct sect *new, int pad) base 104 arch/mips/boot/elf2ecoff.c if (!base->len) base 105 arch/mips/boot/elf2ecoff.c *base = *new; base 107 arch/mips/boot/elf2ecoff.c if (base->vaddr + base->len != new->vaddr) { base 109 arch/mips/boot/elf2ecoff.c base->len = new->vaddr - base->vaddr; base 116 arch/mips/boot/elf2ecoff.c base->len += new->len; base 354 arch/mips/boot/tools/relocs.c static unsigned long base = 0; base 357 arch/mips/boot/tools/relocs.c if (!base) { base 363 arch/mips/boot/tools/relocs.c base = sec->shdr.sh_addr; base 390 arch/mips/boot/tools/relocs.c rel->r_offset -= base; base 181 arch/mips/cavium-octeon/crypto/octeon-md5.c .base = { base 210 arch/mips/cavium-octeon/crypto/octeon-sha1.c .base = { base 234 arch/mips/cavium-octeon/crypto/octeon-sha256.c .base = { base 247 arch/mips/cavium-octeon/crypto/octeon-sha256.c .base = { base 230 arch/mips/cavium-octeon/crypto/octeon-sha512.c .base = { base 243 arch/mips/cavium-octeon/crypto/octeon-sha512.c .base = { base 204 arch/mips/cavium-octeon/dma-octeon.c if (mem->base > 0x410000000ull && !OCTEON_IS_OCTEON2()) base 209 arch/mips/cavium-octeon/dma-octeon.c if (max_addr < mem->base + mem->size) base 210 arch/mips/cavium-octeon/dma-octeon.c max_addr = mem->base + mem->size; base 82 arch/mips/cavium-octeon/executive/cvmx-bootmem.c static inline uint64_t __cvmx_bootmem_desc_get(uint64_t base, int offset, base 85 arch/mips/cavium-octeon/executive/cvmx-bootmem.c base = (1ull << 63) | (base + offset); base 88 arch/mips/cavium-octeon/executive/cvmx-bootmem.c return cvmx_read64_uint32(base); base 90 arch/mips/cavium-octeon/executive/cvmx-bootmem.c return cvmx_read64_uint64(base); base 97 arch/mips/cavium-octeon/flash_setup.c flash_map.phys = region_cfg.s.base << 16; base 1400 arch/mips/cavium-octeon/octeon-irq.c u64 base = CVMX_CIU2_EN_PPX_IP2_WRKQ(coreid); base 1412 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(base + regx + ipx, 0); base 952 arch/mips/cavium-octeon/octeon-platform.c region_base = mio_boot_reg_cfg.s.base << 16; base 975 arch/mips/cavium-octeon/octeon-platform.c region1_base = mio_boot_reg_cfg.s.base << 16; base 1042 arch/mips/cavium-octeon/octeon-platform.c region_base = mio_boot_reg_cfg.s.base << 16; base 228 arch/mips/cavium-octeon/octeon-usb.c static int dwc3_octeon_config_power(struct device *dev, u64 base) base 236 arch/mips/cavium-octeon/octeon-usb.c int index = (base >> 24) & 1; base 271 arch/mips/cavium-octeon/octeon-usb.c uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); base 274 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); base 277 arch/mips/cavium-octeon/octeon-usb.c uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); base 280 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); base 286 arch/mips/cavium-octeon/octeon-usb.c static int dwc3_octeon_clocks_start(struct device *dev, u64 base) base 295 arch/mips/cavium-octeon/octeon-usb.c u64 uctl_ctl_reg = base; base 441 arch/mips/cavium-octeon/octeon-usb.c if (dwc3_octeon_config_power(dev, base)) { base 467 arch/mips/cavium-octeon/octeon-usb.c static void __init dwc3_octeon_set_endian_mode(u64 base) base 472 arch/mips/cavium-octeon/octeon-usb.c shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG); base 480 arch/mips/cavium-octeon/octeon-usb.c cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64); base 486 arch/mips/cavium-octeon/octeon-usb.c static void __init dwc3_octeon_phy_reset(u64 base) base 489 arch/mips/cavium-octeon/octeon-usb.c int index = (base >> 24) & 1; base 502 arch/mips/cavium-octeon/octeon-usb.c void __iomem *base; base 531 arch/mips/cavium-octeon/octeon-usb.c base = devm_ioremap_resource(&pdev->dev, res); base 532 arch/mips/cavium-octeon/octeon-usb.c if (IS_ERR(base)) base 533 arch/mips/cavium-octeon/octeon-usb.c return PTR_ERR(base); base 536 arch/mips/cavium-octeon/octeon-usb.c dwc3_octeon_clocks_start(&pdev->dev, (u64)base); base 537 arch/mips/cavium-octeon/octeon-usb.c dwc3_octeon_set_endian_mode((u64)base); base 538 arch/mips/cavium-octeon/octeon-usb.c dwc3_octeon_phy_reset((u64)base); base 541 arch/mips/cavium-octeon/octeon-usb.c devm_iounmap(&pdev->dev, base); base 283 arch/mips/crypto/crc32-mips.c .base = { base 305 arch/mips/crypto/crc32-mips.c .base = { base 95 arch/mips/dec/ioasic-irq.c void __init init_ioasic_irqs(int base) base 103 arch/mips/dec/ioasic-irq.c for (i = base; i < base + IO_INR_DMA; i++) base 106 arch/mips/dec/ioasic-irq.c for (; i < base + IO_IRQ_LINES; i++) base 108 arch/mips/dec/ioasic-irq.c 1 << (i - base) & IO_IRQ_DMA_INFO ? base 111 arch/mips/dec/ioasic-irq.c ioasic_irq_base = base; base 60 arch/mips/dec/kn02-irq.c void __init init_kn02_irqs(int base) base 71 arch/mips/dec/kn02-irq.c for (i = base; i < base + KN02_IRQ_LINES; i++) base 74 arch/mips/dec/kn02-irq.c kn02_irq_base = base; base 131 arch/mips/fw/arc/memory.c i, p, p->base, p->pages, mtypes(p->type)); base 140 arch/mips/fw/arc/memory.c unsigned long base, size; base 143 arch/mips/fw/arc/memory.c base = p->base << ARC_PAGE_SHIFT; base 147 arch/mips/fw/arc/memory.c add_memory_region(base, size, type); base 154 arch/mips/fw/arc/memory.c prom_mem_base[nr_prom_mem] = base; base 108 arch/mips/fw/sni/sniprom.c u32 base; base 128 arch/mips/fw/sni/sniprom.c if (memconf[i].base >= 0x20000000 && base 129 arch/mips/fw/sni/sniprom.c memconf[i].base < 0x30000000) base 130 arch/mips/fw/sni/sniprom.c memconf[i].base -= 0x20000000; base 133 arch/mips/fw/sni/sniprom.c memconf[i].size, memconf[i].base); base 134 arch/mips/fw/sni/sniprom.c add_memory_region(memconf[i].base, memconf[i].size, base 18 arch/mips/generic/board-ranchu.c static __init u64 read_rtc_time(void __iomem *base) base 28 arch/mips/generic/board-ranchu.c time_low = readl(base + GOLDFISH_TIMER_LOW); base 29 arch/mips/generic/board-ranchu.c time_high = readl(base + GOLDFISH_TIMER_HIGH); base 17 arch/mips/include/asm/asm-eva.h #define kernel_cache(op, base) "cache " op ", " base "\n" base 18 arch/mips/include/asm/asm-eva.h #define kernel_pref(hint, base) "pref " hint ", " base "\n" base 54 arch/mips/include/asm/asm-eva.h #define user_cache(op, base) __BUILD_EVA_INSN("cachee", op, base) base 55 arch/mips/include/asm/asm-eva.h #define user_pref(hint, base) __BUILD_EVA_INSN("prefe", hint, base) base 76 arch/mips/include/asm/asm-eva.h #define user_cache(op, base) kernel_cache(op, base) base 77 arch/mips/include/asm/asm-eva.h #define user_pref(hint, base) kernel_pref(hint, base) base 104 arch/mips/include/asm/asm-eva.h #define kernel_cache(op, base) cache op, base base 105 arch/mips/include/asm/asm-eva.h #define kernel_pref(hint, base) pref hint, base base 141 arch/mips/include/asm/asm-eva.h #define user_cache(op, base) __BUILD_EVA_INSN(cachee, op, base) base 142 arch/mips/include/asm/asm-eva.h #define user_pref(hint, base) __BUILD_EVA_INSN(prefe, hint, base) base 162 arch/mips/include/asm/asm-eva.h #define user_cache(op, base) kernel_cache(op, base) base 163 arch/mips/include/asm/asm-eva.h #define user_pref(hint, base) kernel_pref(hint, base) base 260 arch/mips/include/asm/asmmacro.h .macro ld_b wd, off, base base 269 arch/mips/include/asm/asmmacro.h .macro ld_h wd, off, base base 278 arch/mips/include/asm/asmmacro.h .macro ld_w wd, off, base base 287 arch/mips/include/asm/asmmacro.h .macro ld_d wd, off, base base 296 arch/mips/include/asm/asmmacro.h .macro st_b wd, off, base base 305 arch/mips/include/asm/asmmacro.h .macro st_h wd, off, base base 314 arch/mips/include/asm/asmmacro.h .macro st_w wd, off, base base 323 arch/mips/include/asm/asmmacro.h .macro st_d wd, off, base base 392 arch/mips/include/asm/asmmacro.h .macro ld_b wd, off, base base 402 arch/mips/include/asm/asmmacro.h .macro ld_h wd, off, base base 412 arch/mips/include/asm/asmmacro.h .macro ld_w wd, off, base base 422 arch/mips/include/asm/asmmacro.h .macro ld_d wd, off, base base 432 arch/mips/include/asm/asmmacro.h .macro st_b wd, off, base base 442 arch/mips/include/asm/asmmacro.h .macro st_h wd, off, base base 452 arch/mips/include/asm/asmmacro.h .macro st_w wd, off, base base 462 arch/mips/include/asm/asmmacro.h .macro st_d wd, off, base base 30 arch/mips/include/asm/dec/ioasic.h extern void init_ioasic_irqs(int base); base 88 arch/mips/include/asm/dec/kn02.h extern void init_kn02_irqs(int base); base 22 arch/mips/include/asm/div64.h #define __div64_32(n, base) \ base 60 arch/mips/include/asm/div64.h : "Jr" (base), "0" (__high), "1" (__low)); \ base 68 arch/mips/include/asm/io.h static inline void set_io_port_base(unsigned long base) base 70 arch/mips/include/asm/io.h mips_io_port_base = base; base 170 arch/mips/include/asm/io.h u64 base = UNCAC_BASE; base 177 arch/mips/include/asm/io.h base = (u64) IO_BASE; base 178 arch/mips/include/asm/io.h return (void __iomem *) (unsigned long) (base + offset); base 749 arch/mips/include/asm/mach-au1x00/au1000.h void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys); base 755 arch/mips/include/asm/mach-au1x00/au1000.h if (__raw_readl(base + 0x1c) & 0x20) base 762 arch/mips/include/asm/mach-au1x00/au1000.h __raw_writel(c, base + 0x04); /* tx */ base 275 arch/mips/include/asm/mach-au1x00/gpio-au1000.h void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); base 276 arch/mips/include/asm/mach-au1x00/gpio-au1000.h __raw_writel(0, base + 0x110); /* the write op is key */ base 286 arch/mips/include/asm/mach-au1x00/gpio-au1000.h void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); base 288 arch/mips/include/asm/mach-au1x00/gpio-au1000.h unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR); base 294 arch/mips/include/asm/mach-au1x00/gpio-au1000.h __raw_writel(d, base + AU1000_GPIO2_DIR); base 300 arch/mips/include/asm/mach-au1x00/gpio-au1000.h void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); base 303 arch/mips/include/asm/mach-au1x00/gpio-au1000.h __raw_writel(mask, base + AU1000_GPIO2_OUTPUT); base 309 arch/mips/include/asm/mach-au1x00/gpio-au1000.h void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); base 310 arch/mips/include/asm/mach-au1x00/gpio-au1000.h return __raw_readl(base + AU1000_GPIO2_PINSTATE) & base 361 arch/mips/include/asm/mach-au1x00/gpio-au1000.h void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); base 362 arch/mips/include/asm/mach-au1x00/gpio-au1000.h unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE); base 367 arch/mips/include/asm/mach-au1x00/gpio-au1000.h __raw_writel(r, base + AU1000_GPIO2_INTENABLE); base 443 arch/mips/include/asm/mach-au1x00/gpio-au1000.h void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); base 444 arch/mips/include/asm/mach-au1x00/gpio-au1000.h __raw_writel(3, base + AU1000_GPIO2_ENABLE); /* reset, clock enabled */ base 446 arch/mips/include/asm/mach-au1x00/gpio-au1000.h __raw_writel(1, base + AU1000_GPIO2_ENABLE); /* clock enabled */ base 457 arch/mips/include/asm/mach-au1x00/gpio-au1000.h void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); base 458 arch/mips/include/asm/mach-au1x00/gpio-au1000.h __raw_writel(2, base + AU1000_GPIO2_ENABLE); /* reset, clock disabled */ base 5 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size); base 61 arch/mips/include/asm/mach-loongson64/loongson.h #define LOONGSON3_REG8(base, x) \ base 62 arch/mips/include/asm/mach-loongson64/loongson.h (*(volatile u8 *)((char *)TO_UNCAC(base) + (x))) base 64 arch/mips/include/asm/mach-loongson64/loongson.h #define LOONGSON3_REG32(base, x) \ base 65 arch/mips/include/asm/mach-loongson64/loongson.h (*(volatile u32 *)((char *)TO_UNCAC(base) + (x))) base 148 arch/mips/include/asm/mach-pmcs-msp71xx/msp_prom.h unsigned long base; /* Within KSEG0. */ base 54 arch/mips/include/asm/mach-rc32434/rb.h u32 base; base 69 arch/mips/include/asm/mach-rc32434/rb.h void __iomem *base; base 138 arch/mips/include/asm/mips-cm.h GCR_ACCESSOR_RW(64, 0x008, base) base 144 arch/mips/include/asm/msc01_ic.h extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq); base 46 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg(uint64_t base, uint32_t reg) base 48 arch/mips/include/asm/netlogic/haldefs.h volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; base 54 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) base 56 arch/mips/include/asm/netlogic/haldefs.h volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; base 71 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg64(uint64_t base, uint32_t reg) base 73 arch/mips/include/asm/netlogic/haldefs.h uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); base 98 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) base 100 arch/mips/include/asm/netlogic/haldefs.h uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); base 129 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg_xkphys(uint64_t base, uint32_t reg) base 131 arch/mips/include/asm/netlogic/haldefs.h return nlm_read_reg(base, reg); base 135 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) base 137 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg(base, reg, val); base 141 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg64_xkphys(uint64_t base, uint32_t reg) base 143 arch/mips/include/asm/netlogic/haldefs.h return nlm_read_reg64(base, reg); base 147 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) base 149 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg64(base, reg, val); base 228 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, base 238 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val); base 242 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, base 252 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_IRT(irt_num), val); base 256 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, base 260 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec, base 263 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, base 269 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_read_timer(uint64_t base, int timer) base 271 arch/mips/include/asm/netlogic/xlp-hal/pic.h return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); base 275 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_read_timer32(uint64_t base, int timer) base 277 arch/mips/include/asm/netlogic/xlp-hal/pic.h return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); base 281 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_write_timer(uint64_t base, int timer, uint64_t value) base 283 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value); base 287 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) base 289 arch/mips/include/asm/netlogic/xlp-hal/pic.h uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL); base 293 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value); base 294 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer), base 299 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl); base 303 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_enable_irt(uint64_t base, int irt) base 308 arch/mips/include/asm/netlogic/xlp-hal/pic.h reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); base 309 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22)); base 311 arch/mips/include/asm/netlogic/xlp-hal/pic.h reg = nlm_read_pic_reg(base, PIC_IRT(irt)); base 312 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); base 317 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_disable_irt(uint64_t base, int irt) base 322 arch/mips/include/asm/netlogic/xlp-hal/pic.h reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); base 324 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg); base 326 arch/mips/include/asm/netlogic/xlp-hal/pic.h reg = nlm_read_pic_reg(base, PIC_IRT(irt)); base 328 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_IRT(irt), reg); base 333 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) base 344 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); base 348 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_ack(uint64_t base, int irt_num) base 350 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_INT_ACK, irt_num); base 354 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num)); base 358 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) base 360 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt); base 103 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_uart_set_baudrate(uint64_t base, int baud) base 107 arch/mips/include/asm/netlogic/xlp-hal/uart.h lcr = nlm_read_uart_reg(base, UART_LINE_CTL); base 110 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7)); base 111 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_write_uart_reg(base, UART_DIVISOR0, base 113 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_write_uart_reg(base, UART_DIVISOR1, base 117 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_write_uart_reg(base, UART_LINE_CTL, lcr); base 121 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_uart_outbyte(uint64_t base, char c) base 126 arch/mips/include/asm/netlogic/xlp-hal/uart.h lsr = nlm_read_uart_reg(base, UART_LINE_STS); base 131 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_write_uart_reg(base, UART_TX_DATA, (int)c); base 135 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_uart_inbyte(uint64_t base) base 140 arch/mips/include/asm/netlogic/xlp-hal/uart.h lsr = nlm_read_uart_reg(base, UART_LINE_STS); base 146 arch/mips/include/asm/netlogic/xlp-hal/uart.h data = nlm_read_uart_reg(base, UART_RX_DATA); base 155 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_uart_init(uint64_t base, int baud, int databits, int stopbits, base 176 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_write_uart_reg(base, UART_LINE_CTL, lcr); base 179 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST); base 181 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_uart_set_baudrate(base, baud); base 184 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f); base 187 arch/mips/include/asm/netlogic/xlp-hal/uart.h nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY); base 223 arch/mips/include/asm/netlogic/xlr/pic.h nlm_pic_enable_irt(uint64_t base, int irt) base 227 arch/mips/include/asm/netlogic/xlr/pic.h reg = nlm_read_reg(base, PIC_IRT_1(irt)); base 228 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31)); base 232 arch/mips/include/asm/netlogic/xlr/pic.h nlm_pic_disable_irt(uint64_t base, int irt) base 236 arch/mips/include/asm/netlogic/xlr/pic.h reg = nlm_read_reg(base, PIC_IRT_1(irt)); base 237 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31)); base 241 arch/mips/include/asm/netlogic/xlr/pic.h nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) base 247 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IPI, base 252 arch/mips/include/asm/netlogic/xlr/pic.h nlm_pic_ack(uint64_t base, int irt) base 254 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_INT_ACK, 1u << irt); base 258 arch/mips/include/asm/netlogic/xlr/pic.h nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) base 260 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt)); base 262 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IRT_1(irt), base 267 arch/mips/include/asm/netlogic/xlr/pic.h nlm_pic_read_timer(uint64_t base, int timer) base 271 arch/mips/include/asm/netlogic/xlr/pic.h up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); base 272 arch/mips/include/asm/netlogic/xlr/pic.h low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); base 273 arch/mips/include/asm/netlogic/xlr/pic.h up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); base 276 arch/mips/include/asm/netlogic/xlr/pic.h low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); base 282 arch/mips/include/asm/netlogic/xlr/pic.h nlm_pic_read_timer32(uint64_t base, int timer) base 284 arch/mips/include/asm/netlogic/xlr/pic.h return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); base 288 arch/mips/include/asm/netlogic/xlr/pic.h nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) base 291 arch/mips/include/asm/netlogic/xlr/pic.h uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL); base 297 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low); base 298 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up); base 299 arch/mips/include/asm/netlogic/xlr/pic.h nlm_pic_init_irt(base, PIC_IRT_TIMER_INDEX(timer), irq, cpu, 0); base 303 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_CTRL, pic_ctrl); base 438 arch/mips/include/asm/octeon/cvmx-dpi-defs.h uint64_t base:5; base 442 arch/mips/include/asm/octeon/cvmx-dpi-defs.h uint64_t base:5; base 451 arch/mips/include/asm/octeon/cvmx-dpi-defs.h uint64_t base:4; base 455 arch/mips/include/asm/octeon/cvmx-dpi-defs.h uint64_t base:4; base 87 arch/mips/include/asm/octeon/cvmx-fpa.h void *base; base 119 arch/mips/include/asm/octeon/cvmx-fpa.h return cvmx_fpa_pool_info[pool].base; base 133 arch/mips/include/asm/octeon/cvmx-fpa.h return ((ptr >= cvmx_fpa_pool_info[pool].base) && base 135 arch/mips/include/asm/octeon/cvmx-fpa.h ((char *)(cvmx_fpa_pool_info[pool].base)) + base 467 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t base:25; base 471 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t base:25; base 604 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t base:16; base 606 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t base:16; base 632 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t base:16; base 634 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t base:16; base 653 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t base:16; base 655 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t base:16; base 676 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t base:16; base 678 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t base:16; base 1692 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t base:8; base 1698 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t base:8; base 1743 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t base:8; base 1749 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t base:8; base 805 arch/mips/include/asm/pci/bridge.h struct bridge_regs *base; base 816 arch/mips/include/asm/pci/bridge.h #define bridge_read(bc, reg) __raw_readl(&bc->base->reg) base 817 arch/mips/include/asm/pci/bridge.h #define bridge_write(bc, reg, val) __raw_writel(val, &bc->base->reg) base 819 arch/mips/include/asm/pci/bridge.h __raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg) base 821 arch/mips/include/asm/pci/bridge.h __raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg) base 197 arch/mips/include/asm/r4kcache.h #define cache16_unroll32(base,op) \ base 220 arch/mips/include/asm/r4kcache.h : "r" (base), \ base 223 arch/mips/include/asm/r4kcache.h #define cache32_unroll32(base,op) \ base 246 arch/mips/include/asm/r4kcache.h : "r" (base), \ base 249 arch/mips/include/asm/r4kcache.h #define cache64_unroll32(base,op) \ base 272 arch/mips/include/asm/r4kcache.h : "r" (base), \ base 275 arch/mips/include/asm/r4kcache.h #define cache128_unroll32(base,op) \ base 298 arch/mips/include/asm/r4kcache.h : "r" (base), \ base 307 arch/mips/include/asm/r4kcache.h #define cache16_unroll32(base,op) \ base 332 arch/mips/include/asm/r4kcache.h : "r" (base), \ base 335 arch/mips/include/asm/r4kcache.h #define cache32_unroll32(base,op) \ base 362 arch/mips/include/asm/r4kcache.h : "r" (base), \ base 365 arch/mips/include/asm/r4kcache.h #define cache64_unroll32(base,op) \ base 396 arch/mips/include/asm/r4kcache.h : "r" (base), \ base 399 arch/mips/include/asm/r4kcache.h #define cache128_unroll32(base,op) \ base 440 arch/mips/include/asm/r4kcache.h : "r" (base), \ base 448 arch/mips/include/asm/r4kcache.h #define cache16_unroll32_user(base,op) \ base 472 arch/mips/include/asm/r4kcache.h : "r" (base), \ base 475 arch/mips/include/asm/r4kcache.h #define cache32_unroll32_user(base, op) \ base 499 arch/mips/include/asm/r4kcache.h : "r" (base), \ base 502 arch/mips/include/asm/r4kcache.h #define cache64_unroll32_user(base, op) \ base 526 arch/mips/include/asm/r4kcache.h : "r" (base), \ base 12 arch/mips/include/asm/setup.h extern void setup_8250_early_printk_port(unsigned long base, base 15 arch/mips/include/asm/setup.h static inline void setup_8250_early_printk_port(unsigned long base, base 128 arch/mips/include/asm/sgiarcs.h ULONG base; base 8 arch/mips/include/asm/tlb.h #define _UNIQUE_ENTRYHI(base, idx) \ base 9 arch/mips/include/asm/tlb.h (((base) + ((idx) << (PAGE_SHIFT + 1))) | \ base 18 arch/mips/include/asm/txx9/generic.h void txx9_reg_res_init(unsigned int pcode, unsigned long base, base 46 arch/mips/include/asm/txx9/generic.h void txx9_wdt_init(unsigned long base); base 47 arch/mips/include/asm/txx9/generic.h void txx9_wdt_now(unsigned long base); base 48 arch/mips/include/asm/txx9/generic.h void txx9_spi_init(int busid, unsigned long base, int irq); base 27 arch/mips/include/asm/txx9pio.h unsigned int base, unsigned int num); base 769 arch/mips/include/uapi/asm/inst.h __BITFIELD_FIELD(unsigned int base : 5, base 879 arch/mips/include/uapi/asm/inst.h __BITFIELD_FIELD(unsigned int base : 5, base 917 arch/mips/include/uapi/asm/inst.h __BITFIELD_FIELD(unsigned int base : 5, base 926 arch/mips/include/uapi/asm/inst.h __BITFIELD_FIELD(unsigned int base : 5, base 969 arch/mips/include/uapi/asm/inst.h __BITFIELD_FIELD(unsigned int base : 3, base 11 arch/mips/kernel/8250-platform.c #define PORT(base, int) \ base 13 arch/mips/kernel/8250-platform.c .iobase = base, \ base 16 arch/mips/kernel/early_printk_8250.c void setup_8250_early_printk_port(unsigned long base, unsigned int reg_shift, base 19 arch/mips/kernel/early_printk_8250.c serial8250_base = (void __iomem *)base; base 78 arch/mips/kernel/gpio_txx9.c unsigned int base, unsigned int num) base 83 arch/mips/kernel/gpio_txx9.c txx9_gpio_chip.base = base; base 37 arch/mips/kernel/irq-rm7000.c int base = RM7K_CPU_IRQ_BASE; base 42 arch/mips/kernel/irq-rm7000.c for (i = base; i < base + 4; i++) base 45 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela) base 51 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela) base 53 arch/mips/kernel/module.c *location = base + v; base 59 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela) base 74 arch/mips/kernel/module.c ((base + (v >> 2)) & 0x03ffffff); base 80 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela) base 119 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela) base 121 arch/mips/kernel/module.c unsigned long insnlo = base; base 190 arch/mips/kernel/module.c static int apply_r_mips_pc(struct module *me, u32 *location, u32 base, base 204 arch/mips/kernel/module.c offset = base & mask; base 222 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela) base 224 arch/mips/kernel/module.c return apply_r_mips_pc(me, location, base, v, 16); base 228 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela) base 230 arch/mips/kernel/module.c return apply_r_mips_pc(me, location, base, v, 21); base 234 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela) base 236 arch/mips/kernel/module.c return apply_r_mips_pc(me, location, base, v, 26); base 240 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela) base 251 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela) base 263 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela) base 290 arch/mips/kernel/module.c u32 base, Elf_Addr v, bool rela); base 317 arch/mips/kernel/module.c u32 *location, base; base 361 arch/mips/kernel/module.c base = 0; base 365 arch/mips/kernel/module.c base = *location; base 369 arch/mips/kernel/module.c err = handler(me, location, base, v, rela); base 257 arch/mips/kernel/process.c if (ip->mm_m_format.base != 29) base 39 arch/mips/kernel/prom.c void __init early_init_dt_add_memory_arch(u64 base, u64 size) base 41 arch/mips/kernel/prom.c if (base >= PHYS_ADDR_MAX) { base 47 arch/mips/kernel/prom.c if (base + size - 1 >= PHYS_ADDR_MAX || base + size < base) { base 49 arch/mips/kernel/prom.c size, base, PHYS_ADDR_MAX - base); base 50 arch/mips/kernel/prom.c size = PHYS_ADDR_MAX - base; base 53 arch/mips/kernel/prom.c add_memory_region(base, size, BOOT_MEM_RAM); base 56 arch/mips/kernel/prom.c int __init early_init_dt_reserve_memory_arch(phys_addr_t base, base 59 arch/mips/kernel/prom.c add_memory_region(base, size, base 463 arch/mips/kernel/setup.c unsigned long start = mem->base; base 114 arch/mips/kernel/spram.c unsigned int base, base 149 arch/mips/kernel/spram.c base = (base + size - 1) & ~(size-1); base 152 arch/mips/kernel/spram.c tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE; base 155 arch/mips/kernel/spram.c base += size; base 74 arch/mips/kernel/vdso.c unsigned long base; base 77 arch/mips/kernel/vdso.c base = STACK_TOP + PAGE_SIZE; base 80 arch/mips/kernel/vdso.c base += get_random_int() & (VDSO_RANDOMIZE_SIZE - 1); base 81 arch/mips/kernel/vdso.c base = PAGE_ALIGN(base); base 84 arch/mips/kernel/vdso.c return base; base 91 arch/mips/kernel/vdso.c unsigned long gic_size, vvar_size, size, base, data_addr, vdso_addr, gic_pfn; base 99 arch/mips/kernel/vdso.c base = mmap_region(NULL, STACK_TOP, PAGE_SIZE, base 103 arch/mips/kernel/vdso.c if (IS_ERR_VALUE(base)) { base 104 arch/mips/kernel/vdso.c ret = base; base 127 arch/mips/kernel/vdso.c base = get_unmapped_area(NULL, vdso_base(), size, 0, 0); base 128 arch/mips/kernel/vdso.c if (IS_ERR_VALUE(base)) { base 129 arch/mips/kernel/vdso.c ret = base; base 140 arch/mips/kernel/vdso.c base = __ALIGN_MASK(base, shm_align_mask); base 141 arch/mips/kernel/vdso.c base += ((unsigned long)vdso_data - gic_size) & shm_align_mask; base 144 arch/mips/kernel/vdso.c data_addr = base + gic_size; base 147 arch/mips/kernel/vdso.c vma = _install_special_mapping(mm, base, vvar_size, base 159 arch/mips/kernel/vdso.c ret = io_remap_pfn_range(vma, base, gic_pfn, gic_size, base 1803 arch/mips/kvm/emulate.c u32 cache, op_inst, op, base; base 1818 arch/mips/kvm/emulate.c base = inst.i_format.rs; base 1827 arch/mips/kvm/emulate.c va = arch->gprs[base] + offset; base 1830 arch/mips/kvm/emulate.c cache, op, base, arch->gprs[base], offset); base 1839 arch/mips/kvm/emulate.c vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base, base 1840 arch/mips/kvm/emulate.c arch->gprs[base], offset); base 1916 arch/mips/kvm/emulate.c cache, op, base, arch->gprs[base], offset); base 1069 arch/mips/kvm/vz.c u32 cache, op_inst, op, base; base 1083 arch/mips/kvm/vz.c base = inst.i_format.rs; base 1092 arch/mips/kvm/vz.c va = arch->gprs[base] + offset; base 1095 arch/mips/kvm/vz.c cache, op, base, arch->gprs[base], offset); base 1124 arch/mips/kvm/vz.c curr_pc, vcpu->arch.gprs[31], cache, op, base, arch->gprs[base], base 20 arch/mips/lib/iomap-pci.c unsigned long base = ctrl->io_map_base; base 30 arch/mips/lib/iomap-pci.c ctrl->io_map_base = base = mips_io_port_base; base 158 arch/mips/loongson32/common/irq.c static void __init ls1x_irq_init(int base) base 174 arch/mips/loongson32/common/irq.c for (n = base; n < NR_IRQS; n++) { base 13 arch/mips/loongson64/common/early_printk.c #define PORT(base, offset) (u8 *)(base + offset) base 15 arch/mips/loongson64/common/early_printk.c static inline unsigned int serial_in(unsigned char *base, int offset) base 17 arch/mips/loongson64/common/early_printk.c return readb(PORT(base, offset)); base 20 arch/mips/loongson64/common/early_printk.c static inline void serial_out(unsigned char *base, int offset, int value) base 22 arch/mips/loongson64/common/early_printk.c writeb(value, PORT(base, offset)); base 20 arch/mips/loongson64/common/init.c void *base; base 23 arch/mips/loongson64/common/init.c base = (void *)(CAC_BASE + 0x380); base 24 arch/mips/loongson64/common/init.c memcpy(base, &except_vec_nmi, 0x80); base 25 arch/mips/loongson64/common/init.c flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); base 457 arch/mips/loongson64/loongson-3/smp.c register void *addr, *base, *initfunc; base 509 arch/mips/loongson64/loongson-3/smp.c [base] "=&r" (base), [cpuid] "=&r" (cpuid), base 519 arch/mips/loongson64/loongson-3/smp.c register void *addr, *base, *initfunc; base 592 arch/mips/loongson64/loongson-3/smp.c [base] "=&r" (base), [cpuid] "=&r" (cpuid), base 602 arch/mips/loongson64/loongson-3/smp.c register void *addr, *base, *initfunc; base 656 arch/mips/loongson64/loongson-3/smp.c [base] "=&r" (base), [cpuid] "=&r" (cpuid), base 169 arch/mips/math-emu/cp1emu.c insn.mm_fp5_format.base; base 142 arch/mips/math-emu/dsemul.c unsigned long base = (unsigned long)dsemul_page(); base 144 arch/mips/math-emu/dsemul.c if (regs->cp0_epc < base) base 146 arch/mips/math-emu/dsemul.c if (regs->cp0_epc >= (base + PAGE_SIZE)) base 92 arch/mips/mti-malta/malta-init.c void *base; base 95 arch/mips/mti-malta/malta-init.c base = cpu_has_veic ? base 98 arch/mips/mti-malta/malta-init.c memcpy(base, &except_vec_nmi, 0x80); base 99 arch/mips/mti-malta/malta-init.c flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); base 104 arch/mips/mti-malta/malta-init.c void *base; base 107 arch/mips/mti-malta/malta-init.c base = cpu_has_veic ? base 110 arch/mips/mti-malta/malta-init.c memcpy(base, &except_vec_ejtag_debug, 0x80); base 111 arch/mips/mti-malta/malta-init.c flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); base 30 arch/mips/mti-malta/malta-platform.c #define SMC_PORT(base, int) \ base 32 arch/mips/mti-malta/malta-platform.c .iobase = base, \ base 468 arch/mips/netlogic/xlp/nlm_hal.c uint64_t bridgebase, base, lim; base 497 arch/mips/netlogic/xlp/nlm_hal.c base = (uint64_t) val << 20; base 503 arch/mips/netlogic/xlp/nlm_hal.c dram_map[rv] = base; base 74 arch/mips/netlogic/xlp/setup.c memblock_remove(mem->base + mem->size - pref_backup, base 145 arch/mips/netlogic/xlr/platform-flash.c u32 base, mask; base 147 arch/mips/netlogic/xlr/platform-flash.c base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs)); base 150 arch/mips/netlogic/xlr/platform-flash.c res->start = flash_map_base + ((unsigned long)base << 16); base 214 arch/mips/paravirt/paravirt-irq.c static void irq_mbox_all(struct irq_data *data, void __iomem *base) base 225 arch/mips/paravirt/paravirt-irq.c __raw_writel(mask, base + (cpuid * mips_irq_cpu_stride)); base 261 arch/mips/paravirt/paravirt-irq.c static void irq_mbox_cpu_onoffline(struct irq_data *data, void __iomem *base) base 270 arch/mips/paravirt/paravirt-irq.c __raw_writel(mask, base + (cpuid * mips_irq_cpu_stride)); base 73 arch/mips/pci/ops-emma2rh.c u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE); base 88 arch/mips/pci/ops-emma2rh.c *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) + base 118 arch/mips/pci/ops-emma2rh.c u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE); base 133 arch/mips/pci/ops-emma2rh.c *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) + base 154 arch/mips/pci/ops-emma2rh.c *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) + base 109 arch/mips/pci/pci-ar71xx.c void __iomem *base = apc->cfg_base; base 113 arch/mips/pci/pci-ar71xx.c pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; base 118 arch/mips/pci/pci-ar71xx.c addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); base 124 arch/mips/pci/pci-ar71xx.c __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR); base 127 arch/mips/pci/pci-ar71xx.c ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; base 132 arch/mips/pci/pci-ar71xx.c addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); base 138 arch/mips/pci/pci-ar71xx.c __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR); base 147 arch/mips/pci/pci-ar71xx.c void __iomem *base = apc->cfg_base; base 155 arch/mips/pci/pci-ar71xx.c __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE); base 156 arch/mips/pci/pci-ar71xx.c __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA); base 164 arch/mips/pci/pci-ar71xx.c void __iomem *base = apc->cfg_base; base 169 arch/mips/pci/pci-ar71xx.c __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD); base 171 arch/mips/pci/pci-ar71xx.c base + AR71XX_PCI_REG_CFG_CBE); base 180 arch/mips/pci/pci-ar71xx.c void __iomem *base = apc->cfg_base; base 193 arch/mips/pci/pci-ar71xx.c data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); base 204 arch/mips/pci/pci-ar71xx.c void __iomem *base = apc->cfg_base; base 216 arch/mips/pci/pci-ar71xx.c __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); base 229 arch/mips/pci/pci-ar71xx.c void __iomem *base = ath79_reset_base; base 234 arch/mips/pci/pci-ar71xx.c pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & base 235 arch/mips/pci/pci-ar71xx.c __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); base 257 arch/mips/pci/pci-ar71xx.c void __iomem *base = ath79_reset_base; base 263 arch/mips/pci/pci-ar71xx.c t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); base 264 arch/mips/pci/pci-ar71xx.c __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); base 267 arch/mips/pci/pci-ar71xx.c __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); base 274 arch/mips/pci/pci-ar71xx.c void __iomem *base = ath79_reset_base; base 280 arch/mips/pci/pci-ar71xx.c t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); base 281 arch/mips/pci/pci-ar71xx.c __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); base 284 arch/mips/pci/pci-ar71xx.c __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); base 296 arch/mips/pci/pci-ar71xx.c void __iomem *base = ath79_reset_base; base 299 arch/mips/pci/pci-ar71xx.c __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); base 300 arch/mips/pci/pci-ar71xx.c __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); base 76 arch/mips/pci/pci-ar724x.c void __iomem *base; base 85 arch/mips/pci/pci-ar724x.c base = apc->crp_base; base 86 arch/mips/pci/pci-ar724x.c data = __raw_readl(base + (where & ~3)); base 106 arch/mips/pci/pci-ar724x.c __raw_writel(data, base + (where & ~3)); base 108 arch/mips/pci/pci-ar724x.c __raw_readl(base + (where & ~3)); base 117 arch/mips/pci/pci-ar724x.c void __iomem *base; base 127 arch/mips/pci/pci-ar724x.c base = apc->devcfg_base; base 128 arch/mips/pci/pci-ar724x.c data = __raw_readl(base + (where & ~3)); base 164 arch/mips/pci/pci-ar724x.c void __iomem *base; base 196 arch/mips/pci/pci-ar724x.c base = apc->devcfg_base; base 197 arch/mips/pci/pci-ar724x.c data = __raw_readl(base + (where & ~3)); base 217 arch/mips/pci/pci-ar724x.c __raw_writel(data, base + (where & ~3)); base 219 arch/mips/pci/pci-ar724x.c __raw_readl(base + (where & ~3)); base 232 arch/mips/pci/pci-ar724x.c void __iomem *base; base 236 arch/mips/pci/pci-ar724x.c base = apc->ctrl_base; base 238 arch/mips/pci/pci-ar724x.c pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & base 239 arch/mips/pci/pci-ar724x.c __raw_readl(base + AR724X_PCI_REG_INT_MASK); base 251 arch/mips/pci/pci-ar724x.c void __iomem *base; base 256 arch/mips/pci/pci-ar724x.c base = apc->ctrl_base; base 261 arch/mips/pci/pci-ar724x.c t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); base 263 arch/mips/pci/pci-ar724x.c base + AR724X_PCI_REG_INT_MASK); base 265 arch/mips/pci/pci-ar724x.c __raw_readl(base + AR724X_PCI_REG_INT_MASK); base 272 arch/mips/pci/pci-ar724x.c void __iomem *base; base 277 arch/mips/pci/pci-ar724x.c base = apc->ctrl_base; base 282 arch/mips/pci/pci-ar724x.c t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); base 284 arch/mips/pci/pci-ar724x.c base + AR724X_PCI_REG_INT_MASK); base 287 arch/mips/pci/pci-ar724x.c __raw_readl(base + AR724X_PCI_REG_INT_MASK); base 289 arch/mips/pci/pci-ar724x.c t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); base 291 arch/mips/pci/pci-ar724x.c base + AR724X_PCI_REG_INT_STATUS); base 294 arch/mips/pci/pci-ar724x.c __raw_readl(base + AR724X_PCI_REG_INT_STATUS); base 308 arch/mips/pci/pci-ar724x.c void __iomem *base; base 311 arch/mips/pci/pci-ar724x.c base = apc->ctrl_base; base 313 arch/mips/pci/pci-ar724x.c __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); base 314 arch/mips/pci/pci-ar724x.c __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); base 59 arch/mips/pci/pci-rt3883.c void __iomem *base; base 83 arch/mips/pci/pci-rt3883.c return ioread32(rpc->base + reg); base 89 arch/mips/pci/pci-rt3883.c iowrite32(val, rpc->base + reg); base 424 arch/mips/pci/pci-rt3883.c rpc->base = devm_ioremap_resource(dev, res); base 425 arch/mips/pci/pci-rt3883.c if (IS_ERR(rpc->base)) base 426 arch/mips/pci/pci-rt3883.c return PTR_ERR(rpc->base); base 88 arch/mips/pci/pci-vr41xx.h #define MBADD(base) ((base) & 0xfffff800U) base 89 arch/mips/pci/pci-vr41xx.h #define PMBA(base) ((base) & 0xffe00000U) base 97 arch/mips/pci/pci-xtalk-bridge.c struct bridge_regs *bridge = bc->base; base 133 arch/mips/pci/pci-xtalk-bridge.c struct bridge_regs *bridge = bc->base; base 180 arch/mips/pci/pci-xtalk-bridge.c struct bridge_regs *bridge = bc->base; base 219 arch/mips/pci/pci-xtalk-bridge.c struct bridge_regs *bridge = bc->base; base 479 arch/mips/pci/pci-xtalk-bridge.c bc->base = (struct bridge_regs *)bd->bridge_addr; base 694 arch/mips/pci/pcie-octeon.c int base; base 931 arch/mips/pci/pcie-octeon.c base = pcie_port ? 16 : 0; base 940 arch/mips/pci/pcie-octeon.c cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle), base 942 arch/mips/pci/pcie-octeon.c base++; base 85 arch/mips/pistachio/init.c void *base; base 88 arch/mips/pistachio/init.c base = cpu_has_veic ? base 91 arch/mips/pistachio/init.c memcpy(base, &except_vec_nmi, 0x80); base 92 arch/mips/pistachio/init.c flush_icache_range((unsigned long)base, base 93 arch/mips/pistachio/init.c (unsigned long)base + 0x80); base 98 arch/mips/pistachio/init.c void *base; base 101 arch/mips/pistachio/init.c base = cpu_has_veic ? base 104 arch/mips/pistachio/init.c memcpy(base, &except_vec_ejtag_debug, 0x80); base 105 arch/mips/pistachio/init.c flush_icache_range((unsigned long)base, base 106 arch/mips/pistachio/init.c (unsigned long)base + 0x80); base 352 arch/mips/pmcs-msp71xx/msp_prom.c unsigned long base, size; base 355 arch/mips/pmcs-msp71xx/msp_prom.c base = p->base; base 358 arch/mips/pmcs-msp71xx/msp_prom.c add_memory_region(base, size, type); base 366 arch/mips/pmcs-msp71xx/msp_prom.c prom_mem_base[nr_prom_mem] = base; base 480 arch/mips/pmcs-msp71xx/msp_prom.c mdesc[i].base = 0x00000000; base 485 arch/mips/pmcs-msp71xx/msp_prom.c if (heaptop > mdesc[i].base + mdesc[i].size) { base 488 arch/mips/pmcs-msp71xx/msp_prom.c mdesc[i].base = mdesc[i-1].base + mdesc[i-1].size; base 489 arch/mips/pmcs-msp71xx/msp_prom.c mdesc[i].size = heaptop - mdesc[i].base; base 496 arch/mips/pmcs-msp71xx/msp_prom.c mdesc[i].base = heaptop; base 497 arch/mips/pmcs-msp71xx/msp_prom.c mdesc[i].size = CPHYSADDR((u32)_text) - mdesc[i].base; base 503 arch/mips/pmcs-msp71xx/msp_prom.c mdesc[i].base = CPHYSADDR((u32)_text); base 504 arch/mips/pmcs-msp71xx/msp_prom.c mdesc[i].size = CPHYSADDR(PAGE_ALIGN((u32)_end)) - mdesc[i].base; base 509 arch/mips/pmcs-msp71xx/msp_prom.c mdesc[i].base = mdesc[i-1].base + mdesc[i-1].size; base 510 arch/mips/pmcs-msp71xx/msp_prom.c mdesc[i].size = memsize - mdesc[i].base; base 47 arch/mips/rb532/devices.c writeb(dev3.state, dev3.base); base 289 arch/mips/rb532/devices.c dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1); base 291 arch/mips/rb532/devices.c if (!dev3.base) { base 157 arch/mips/rb532/gpio.c .base = 0, base 77 arch/mips/rb532/irq.c #define READ_PEND(base) (*(base)) base 78 arch/mips/rb532/irq.c #define READ_MASK(base) (*(base + 2)) base 79 arch/mips/rb532/irq.c #define WRITE_MASK(base, val) (*(base + 2) = (val)) base 24 arch/mips/sgi-ip32/ip32-memory.c u64 base, size; base 31 arch/mips/sgi-ip32/ip32-memory.c base = (bankctl & CRIME_MEM_BANK_CONTROL_ADDR) << 25; base 32 arch/mips/sgi-ip32/ip32-memory.c if (bank != 0 && base == 0) base 36 arch/mips/sgi-ip32/ip32-memory.c if (base + size > (256 << 20)) base 37 arch/mips/sgi-ip32/ip32-memory.c base += CRIME_HI_MEM_BASE; base 40 arch/mips/sgi-ip32/ip32-memory.c bank, base, size >> 20); base 41 arch/mips/sgi-ip32/ip32-memory.c add_memory_region(base, size, BOOT_MEM_RAM); base 311 arch/mips/sibyte/bcm1480/irq.c unsigned long base; base 318 arch/mips/sibyte/bcm1480/irq.c base = A_BCM1480_IMR_MAPPER(cpu); base 320 arch/mips/sibyte/bcm1480/irq.c IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H)); base 322 arch/mips/sibyte/bcm1480/irq.c IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L)); base 53 arch/mips/sibyte/swarm/platform.c u8 __iomem *base; base 60 arch/mips/sibyte/swarm/platform.c base = ioremap(A_IO_EXT_BASE, 0x800); base 61 arch/mips/sibyte/swarm/platform.c offset = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_START_ADDR, IDE_CS)); base 62 arch/mips/sibyte/swarm/platform.c size = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_MULT_SIZE, IDE_CS)); base 63 arch/mips/sibyte/swarm/platform.c iounmap(base); base 57 arch/mips/txx9/generic/setup.c txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size) base 69 arch/mips/txx9/generic/setup.c if (base) { base 70 arch/mips/txx9/generic/setup.c txx9_reg_res.start = base & 0xfffffffffULL; base 71 arch/mips/txx9/generic/setup.c txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1); base 389 arch/mips/txx9/generic/setup.c void __init txx9_wdt_init(unsigned long base) base 392 arch/mips/txx9/generic/setup.c .start = base, base 393 arch/mips/txx9/generic/setup.c .end = base + 0x100 - 1, base 399 arch/mips/txx9/generic/setup.c void txx9_wdt_now(unsigned long base) base 402 arch/mips/txx9/generic/setup.c ioremap(base, sizeof(struct txx9_tmr_reg)); base 414 arch/mips/txx9/generic/setup.c void __init txx9_spi_init(int busid, unsigned long base, int irq) base 418 arch/mips/txx9/generic/setup.c .start = base, base 419 arch/mips/txx9/generic/setup.c .end = base + 0x20 - 1, base 744 arch/mips/txx9/generic/setup.c iocled->chip.base = basenum; base 749 arch/mips/txx9/generic/setup.c basenum = iocled->chip.base; base 885 arch/mips/txx9/generic/setup.c void __iomem *base; base 899 arch/mips/txx9/generic/setup.c memcpy_fromio(buf, dev->base + pos, size); base 914 arch/mips/txx9/generic/setup.c memcpy_toio(dev->base + pos, buf, size); base 939 arch/mips/txx9/generic/setup.c dev->base = ioremap(r->start, size); base 940 arch/mips/txx9/generic/setup.c if (!dev->base) { base 958 arch/mips/txx9/generic/setup.c iounmap(dev->base); base 963 arch/mips/txx9/generic/setup.c iounmap(dev->base); base 196 arch/mips/txx9/generic/setup_tx4927.c unsigned long base, size; base 199 arch/mips/txx9/generic/setup_tx4927.c base = (unsigned long)(cr >> 49) << 21; base 203 arch/mips/txx9/generic/setup_tx4927.c tx4927_sdram_resource[i].start = base; base 204 arch/mips/txx9/generic/setup_tx4927.c tx4927_sdram_resource[i].end = base + size - 1; base 209 arch/mips/txx9/generic/setup_tx4938.c unsigned long base, size; base 212 arch/mips/txx9/generic/setup_tx4938.c base = (unsigned long)(cr >> 49) << 21; base 216 arch/mips/txx9/generic/setup_tx4938.c tx4938_sdram_resource[i].start = base; base 217 arch/mips/txx9/generic/setup_tx4938.c tx4938_sdram_resource[i].end = base + size - 1; base 328 arch/mips/txx9/generic/setup_tx4939.c return cmd.base.speed; base 271 arch/mips/txx9/rbtx4938/setup.c .base = 16, base 15 arch/nds32/include/asm/vdso.h #define VDSO_SYMBOL(base, name) \ base 17 arch/nds32/include/asm/vdso.h (unsigned long)(vdso_offset_##name + (unsigned long)(base)); \ base 253 arch/nds32/kernel/setup.c memory_start = region->base; base 254 arch/nds32/kernel/setup.c memory_end = region->base + region->size; base 237 arch/nds32/kernel/traps.c unsigned long base = PAGE_OFFSET; base 239 arch/nds32/kernel/traps.c memcpy((unsigned long *)base, (unsigned long *)&exception_vector, base 255 arch/nds32/kernel/traps.c cpu_cache_wbinval_page(base, true); base 37 arch/nios2/kernel/time.c void __iomem *base; base 65 arch/nios2/kernel/time.c return readw(timer->base + offs); base 70 arch/nios2/kernel/time.c writew(val, timer->base + offs); base 111 arch/nios2/kernel/time.c if (nios2_cs.timer.base) base 213 arch/nios2/kernel/time.c void __iomem **base, u32 *freq) base 215 arch/nios2/kernel/time.c *base = of_iomap(np, 0); base 216 arch/nios2/kernel/time.c if (!*base) { base 259 arch/nios2/kernel/time.c nios2_ce.timer.base = iobase; base 292 arch/nios2/kernel/time.c nios2_cs.timer.base = iobase; base 58 arch/openrisc/kernel/setup.c memory_start = region->base; base 59 arch/openrisc/kernel/setup.c memory_end = region->base + region->size; base 85 arch/openrisc/mm/init.c p = (u32) region->base & PAGE_MASK; base 125 arch/openrisc/mm/init.c region->base, region->base + region->size); base 154 arch/parisc/boot/compressed/misc.c static int print_num(unsigned long num, int base) base 162 arch/parisc/boot/compressed/misc.c str[i--] = hex[num % base]; base 163 arch/parisc/boot/compressed/misc.c num = num / base; base 166 arch/parisc/boot/compressed/misc.c if (base == 16) { base 83 arch/parisc/kernel/module.c return (loc >= me->init_layout.base && base 84 arch/parisc/kernel/module.c loc <= (me->init_layout.base + me->init_layout.size)); base 89 arch/parisc/kernel/module.c return (loc >= me->core_layout.base && base 90 arch/parisc/kernel/module.c loc <= (me->core_layout.base + me->core_layout.size)); base 374 arch/parisc/kernel/module.c got = me->core_layout.base + me->arch.got_offset; base 392 arch/parisc/kernel/module.c Elf_Fdesc *fdesc = me->core_layout.base + me->arch.fdesc_offset; base 410 arch/parisc/kernel/module.c fdesc->gp = (Elf_Addr)me->core_layout.base + me->arch.got_offset; base 842 arch/parisc/kernel/module.c gp = (Elf_Addr)me->core_layout.base + me->arch.got_offset; base 977 arch/parisc/kernel/module.c unsigned long start_opd = (Elf64_Addr)mod->core_layout.base + base 48 arch/parisc/kernel/sys_parisc.c unsigned long base = (addr+SHM_COLOUR-1) & ~(SHM_COLOUR-1); base 52 arch/parisc/kernel/sys_parisc.c return base + off; base 68 arch/powerpc/boot/4xx.c u64 base = ((u64)(bas & 0xFFE00000u)) << 2; base 75 arch/powerpc/boot/4xx.c return base + 0x000800000ull; base 77 arch/powerpc/boot/4xx.c return base + 0x001000000ull; base 79 arch/powerpc/boot/4xx.c return base + 0x002000000ull; base 81 arch/powerpc/boot/4xx.c return base + 0x004000000ull; base 83 arch/powerpc/boot/4xx.c return base + 0x008000000ull; base 85 arch/powerpc/boot/4xx.c return base + 0x010000000ull; base 87 arch/powerpc/boot/4xx.c return base + 0x020000000ull; base 89 arch/powerpc/boot/4xx.c return base + 0x040000000ull; base 91 arch/powerpc/boot/4xx.c return base + 0x080000000ull; base 93 arch/powerpc/boot/4xx.c return base + 0x100000000ull; base 25 arch/powerpc/boot/cuboot-pq2.c u32 base; /* must be zero */ base 80 arch/powerpc/boot/cuboot-pq2.c u32 base, option; base 85 arch/powerpc/boot/cuboot-pq2.c if (cs_ranges_buf[i].base != 0) base 88 arch/powerpc/boot/cuboot-pq2.c base = in_be32(&ctrl_addr[cs * 2]); base 93 arch/powerpc/boot/cuboot-pq2.c if (base & 1) { base 94 arch/powerpc/boot/cuboot-pq2.c base &= 0x7fff; base 97 arch/powerpc/boot/cuboot-pq2.c base = 0x1801; base 104 arch/powerpc/boot/cuboot-pq2.c out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr); base 14 arch/powerpc/boot/opal.c u64 base; base 72 arch/powerpc/boot/opal.c if (getprop(opal_node, "opal-base-address", &opal.base, sizeof(u64)) < 0) base 74 arch/powerpc/boot/opal.c opal.base = be64_to_cpu(opal.base); base 93 arch/powerpc/boot/ops.h void *simple_alloc_init(char *base, unsigned long heap_size, base 23 arch/powerpc/boot/simple_alloc.c unsigned long base; base 50 arch/powerpc/boot/simple_alloc.c p->base = next_base; base 55 arch/powerpc/boot/simple_alloc.c return (void *)p->base; base 62 arch/powerpc/boot/simple_alloc.c return (void *)p->base; base 77 arch/powerpc/boot/simple_alloc.c (p->base == (unsigned long)ptr)) base 126 arch/powerpc/boot/simple_alloc.c void *simple_alloc_init(char *base, unsigned long heap_size, base 137 arch/powerpc/boot/simple_alloc.c alloc_tbl = (struct alloc_info *)_ALIGN_UP((unsigned long)base, 8); base 32 arch/powerpc/boot/stdio.c # define do_div(n, base) ({ \ base 33 arch/powerpc/boot/stdio.c unsigned int __base = (base); \ base 48 arch/powerpc/boot/stdio.c # define do_div(n,base) ({ \ base 49 arch/powerpc/boot/stdio.c unsigned int __base = (base); \ base 79 arch/powerpc/boot/stdio.c static char * number(char * str, unsigned long long num, int base, int size, int precision, int type) base 89 arch/powerpc/boot/stdio.c if (base < 2 || base > 36) base 107 arch/powerpc/boot/stdio.c if (base == 16) base 109 arch/powerpc/boot/stdio.c else if (base == 8) base 116 arch/powerpc/boot/stdio.c tmp[i++] = digits[do_div(num, base)]; base 127 arch/powerpc/boot/stdio.c if (base==8) base 129 arch/powerpc/boot/stdio.c else if (base==16) { base 150 arch/powerpc/boot/stdio.c int i, base; base 223 arch/powerpc/boot/stdio.c base = 10; base 281 arch/powerpc/boot/stdio.c base = 8; base 287 arch/powerpc/boot/stdio.c base = 16; base 323 arch/powerpc/boot/stdio.c str = number(str, num, base, field_width, precision, flags); base 13 arch/powerpc/boot/stdlib.c unsigned long long int strtoull(const char *ptr, char **end, int base) base 17 arch/powerpc/boot/stdlib.c if (base > 36) base 23 arch/powerpc/boot/stdlib.c if (*ptr >= '0' && *ptr <= '9' && *ptr < '0' + base) base 25 arch/powerpc/boot/stdlib.c else if (*ptr >= 'A' && *ptr < 'A' + base - 10) base 27 arch/powerpc/boot/stdlib.c else if (*ptr >= 'a' && *ptr < 'a' + base - 10) base 32 arch/powerpc/boot/stdlib.c ret *= base; base 5 arch/powerpc/boot/stdlib.h unsigned long long int strtoull(const char *ptr, char **end, int base); base 143 arch/powerpc/crypto/crc32c-vpmsum_glue.c .base = { base 97 arch/powerpc/crypto/crct10dif-vpmsum_glue.c .base = { base 133 arch/powerpc/crypto/md5-glue.c .base = { base 179 arch/powerpc/crypto/sha1-spe-glue.c .base = { base 127 arch/powerpc/crypto/sha1.c .base = { base 225 arch/powerpc/crypto/sha256-spe-glue.c .base = { base 241 arch/powerpc/crypto/sha256-spe-glue.c .base = { base 16 arch/powerpc/include/asm/dcr-mmio.h unsigned int base; base 31 arch/powerpc/include/asm/dcr-mmio.h return in_be32(host.token + ((host.base + dcr_n) * host.stride)); base 38 arch/powerpc/include/asm/dcr-mmio.h out_be32(host.token + ((host.base + dcr_n) * host.stride), value); base 18 arch/powerpc/include/asm/dcr-native.h unsigned int base; base 27 arch/powerpc/include/asm/dcr-native.h ((dcr_host_native_t){ .base = (dcr_n) }) base 29 arch/powerpc/include/asm/dcr-native.h #define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base) base 30 arch/powerpc/include/asm/dcr-native.h #define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value) base 130 arch/powerpc/include/asm/dcr-native.h #define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \ base 131 arch/powerpc/include/asm/dcr-native.h DCRN_ ## base ## _CONFIG_DATA, \ base 134 arch/powerpc/include/asm/dcr-native.h #define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \ base 135 arch/powerpc/include/asm/dcr-native.h DCRN_ ## base ## _CONFIG_DATA, \ base 138 arch/powerpc/include/asm/dcr-native.h #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ base 139 arch/powerpc/include/asm/dcr-native.h DCRN_ ## base ## _CONFIG_DATA, \ base 62 arch/powerpc/include/asm/fadump-internal.h u64 base; base 137 arch/powerpc/include/asm/iommu.h struct iommu_table *base) base 139 arch/powerpc/include/asm/iommu.h dev->archdata.iommu_table_base = base; base 224 arch/powerpc/include/asm/mpic.h u8 __iomem *base; base 241 arch/powerpc/include/asm/mpic.h u32 __iomem *base; base 15 arch/powerpc/include/asm/mpic_msgr.h u32 __iomem *base; base 75 arch/powerpc/include/asm/mpic_msgr.h out_be32(msgr->base, message); base 88 arch/powerpc/include/asm/mpic_msgr.h return in_be32(msgr->base); base 113 arch/powerpc/include/asm/mpic_msgr.h out_be32(msgr->base, 1 << get_hard_smp_processor_id(cpu_num)); base 350 arch/powerpc/include/asm/pmac_feature.h volatile u32 __iomem *base; base 367 arch/powerpc/include/asm/pmac_feature.h #define MACIO_FCR32(macio, r) ((macio)->base + ((r) >> 2)) base 368 arch/powerpc/include/asm/pmac_feature.h #define MACIO_FCR8(macio, r) (((volatile u8 __iomem *)((macio)->base)) + (r)) base 12 arch/powerpc/include/asm/pnv-ocxl.h extern int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled, base 77 arch/powerpc/include/asm/ppc_asm.h #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) base 78 arch/powerpc/include/asm/ppc_asm.h #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) base 79 arch/powerpc/include/asm/ppc_asm.h #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) base 80 arch/powerpc/include/asm/ppc_asm.h #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) base 82 arch/powerpc/include/asm/ppc_asm.h #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) base 83 arch/powerpc/include/asm/ppc_asm.h #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) base 84 arch/powerpc/include/asm/ppc_asm.h #define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base) base 85 arch/powerpc/include/asm/ppc_asm.h #define REST_NVGPRS(base) lmw 13, GPR0+4*13(base) base 88 arch/powerpc/include/asm/ppc_asm.h #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) base 89 arch/powerpc/include/asm/ppc_asm.h #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) base 90 arch/powerpc/include/asm/ppc_asm.h #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) base 91 arch/powerpc/include/asm/ppc_asm.h #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) base 92 arch/powerpc/include/asm/ppc_asm.h #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) base 93 arch/powerpc/include/asm/ppc_asm.h #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) base 94 arch/powerpc/include/asm/ppc_asm.h #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) base 95 arch/powerpc/include/asm/ppc_asm.h #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) base 97 arch/powerpc/include/asm/ppc_asm.h #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) base 98 arch/powerpc/include/asm/ppc_asm.h #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) base 99 arch/powerpc/include/asm/ppc_asm.h #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) base 100 arch/powerpc/include/asm/ppc_asm.h #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) base 101 arch/powerpc/include/asm/ppc_asm.h #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) base 102 arch/powerpc/include/asm/ppc_asm.h #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) base 103 arch/powerpc/include/asm/ppc_asm.h #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) base 104 arch/powerpc/include/asm/ppc_asm.h #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) base 105 arch/powerpc/include/asm/ppc_asm.h #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) base 106 arch/powerpc/include/asm/ppc_asm.h #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) base 107 arch/powerpc/include/asm/ppc_asm.h #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) base 108 arch/powerpc/include/asm/ppc_asm.h #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) base 110 arch/powerpc/include/asm/ppc_asm.h #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b base 111 arch/powerpc/include/asm/ppc_asm.h #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) base 112 arch/powerpc/include/asm/ppc_asm.h #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) base 113 arch/powerpc/include/asm/ppc_asm.h #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) base 114 arch/powerpc/include/asm/ppc_asm.h #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) base 115 arch/powerpc/include/asm/ppc_asm.h #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) base 116 arch/powerpc/include/asm/ppc_asm.h #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b base 117 arch/powerpc/include/asm/ppc_asm.h #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) base 118 arch/powerpc/include/asm/ppc_asm.h #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) base 119 arch/powerpc/include/asm/ppc_asm.h #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) base 120 arch/powerpc/include/asm/ppc_asm.h #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) base 121 arch/powerpc/include/asm/ppc_asm.h #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) base 124 arch/powerpc/include/asm/ppc_asm.h #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) base 125 arch/powerpc/include/asm/ppc_asm.h #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) base 127 arch/powerpc/include/asm/ppc_asm.h #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ base 128 arch/powerpc/include/asm/ppc_asm.h STXVD2X(n,b,base); \ base 131 arch/powerpc/include/asm/ppc_asm.h #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ base 135 arch/powerpc/include/asm/ppc_asm.h #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) base 136 arch/powerpc/include/asm/ppc_asm.h #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) base 137 arch/powerpc/include/asm/ppc_asm.h #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) base 138 arch/powerpc/include/asm/ppc_asm.h #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) base 139 arch/powerpc/include/asm/ppc_asm.h #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) base 140 arch/powerpc/include/asm/ppc_asm.h #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) base 141 arch/powerpc/include/asm/ppc_asm.h #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) base 142 arch/powerpc/include/asm/ppc_asm.h #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) base 143 arch/powerpc/include/asm/ppc_asm.h #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) base 144 arch/powerpc/include/asm/ppc_asm.h #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) base 145 arch/powerpc/include/asm/ppc_asm.h #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) base 146 arch/powerpc/include/asm/ppc_asm.h #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) base 57 arch/powerpc/include/asm/rtas.h unsigned long base; /* physical address pointer */ base 283 arch/powerpc/kernel/asm-offsets.c OFFSET(RTASBASE, rtas_t, base); base 155 arch/powerpc/kernel/btext.c unsigned long base, offset, size; base 162 arch/powerpc/kernel/btext.c base = ((unsigned long) dispDeviceBase) & 0xFFFFF000UL; base 163 arch/powerpc/kernel/btext.c offset = ((unsigned long) dispDeviceBase) - base; base 166 arch/powerpc/kernel/btext.c vbase = ioremap_wc(base, size); base 262 arch/powerpc/kernel/btext.c unsigned char *base; base 264 arch/powerpc/kernel/btext.c base = logicalDisplayBase; base 265 arch/powerpc/kernel/btext.c if (!base) base 266 arch/powerpc/kernel/btext.c base = dispDeviceBase; base 267 arch/powerpc/kernel/btext.c base += (x + dispDeviceRect[0]) * (dispDeviceDepth >> 3); base 268 arch/powerpc/kernel/btext.c base += (y + dispDeviceRect[1]) * dispDeviceRowBytes; base 269 arch/powerpc/kernel/btext.c return base; base 304 arch/powerpc/kernel/btext.c unsigned int *base = (unsigned int *)calc_base(0, 0); base 312 arch/powerpc/kernel/btext.c unsigned int *ptr = base; base 315 arch/powerpc/kernel/btext.c base += (dispDeviceRowBytes >> 2); base 322 arch/powerpc/kernel/btext.c unsigned int *base = (unsigned int *)calc_base(0, 0); base 329 arch/powerpc/kernel/btext.c unsigned int *ptr = base; base 334 arch/powerpc/kernel/btext.c base += (dispDeviceRowBytes >> 2); base 341 arch/powerpc/kernel/btext.c unsigned int *base = (unsigned int *)calc_base(0, g_loc_Y << 4); base 348 arch/powerpc/kernel/btext.c unsigned int *ptr = base; base 353 arch/powerpc/kernel/btext.c base += (dispDeviceRowBytes >> 2); base 418 arch/powerpc/kernel/btext.c static void draw_byte_32(unsigned char *font, unsigned int *base, int rb) base 427 arch/powerpc/kernel/btext.c base[0] = (-(bits >> 7) & fg) ^ bg; base 428 arch/powerpc/kernel/btext.c base[1] = (-((bits >> 6) & 1) & fg) ^ bg; base 429 arch/powerpc/kernel/btext.c base[2] = (-((bits >> 5) & 1) & fg) ^ bg; base 430 arch/powerpc/kernel/btext.c base[3] = (-((bits >> 4) & 1) & fg) ^ bg; base 431 arch/powerpc/kernel/btext.c base[4] = (-((bits >> 3) & 1) & fg) ^ bg; base 432 arch/powerpc/kernel/btext.c base[5] = (-((bits >> 2) & 1) & fg) ^ bg; base 433 arch/powerpc/kernel/btext.c base[6] = (-((bits >> 1) & 1) & fg) ^ bg; base 434 arch/powerpc/kernel/btext.c base[7] = (-(bits & 1) & fg) ^ bg; base 435 arch/powerpc/kernel/btext.c base = (unsigned int *) ((char *)base + rb); base 439 arch/powerpc/kernel/btext.c static inline void draw_byte_16(unsigned char *font, unsigned int *base, int rb) base 449 arch/powerpc/kernel/btext.c base[0] = (eb[bits >> 6] & fg) ^ bg; base 450 arch/powerpc/kernel/btext.c base[1] = (eb[(bits >> 4) & 3] & fg) ^ bg; base 451 arch/powerpc/kernel/btext.c base[2] = (eb[(bits >> 2) & 3] & fg) ^ bg; base 452 arch/powerpc/kernel/btext.c base[3] = (eb[bits & 3] & fg) ^ bg; base 453 arch/powerpc/kernel/btext.c base = (unsigned int *) ((char *)base + rb); base 457 arch/powerpc/kernel/btext.c static inline void draw_byte_8(unsigned char *font, unsigned int *base, int rb) base 467 arch/powerpc/kernel/btext.c base[0] = (eb[bits >> 4] & fg) ^ bg; base 468 arch/powerpc/kernel/btext.c base[1] = (eb[bits & 0xf] & fg) ^ bg; base 469 arch/powerpc/kernel/btext.c base = (unsigned int *) ((char *)base + rb); base 475 arch/powerpc/kernel/btext.c unsigned char *base = calc_base(locX << 3, locY << 4); base 483 arch/powerpc/kernel/btext.c draw_byte_32(font, (unsigned int *)base, rb); base 487 arch/powerpc/kernel/btext.c draw_byte_16(font, (unsigned int *)base, rb); base 490 arch/powerpc/kernel/btext.c draw_byte_8(font, (unsigned int *)base, rb); base 37 arch/powerpc/kernel/fadump.c static void __init fadump_reserve_crash_area(u64 base); base 62 arch/powerpc/kernel/fadump.c unsigned long long base, size; base 75 arch/powerpc/kernel/fadump.c base = fw_dump.reserve_dump_area_start; base 81 arch/powerpc/kernel/fadump.c rc = cma_init_reserved_mem(base, size, 0, "fadump_cma", &fadump_cma); base 172 arch/powerpc/kernel/fadump.c start = max_t(u64, d_start, reg->base); base 173 arch/powerpc/kernel/fadump.c end = min_t(u64, d_end, (reg->base + reg->size)); base 270 arch/powerpc/kernel/fadump.c u64 base, size, bootmem_min; base 282 arch/powerpc/kernel/fadump.c &size, &base); base 398 arch/powerpc/kernel/fadump.c unsigned long base, size, cur_size, hole_size, last_end; base 409 arch/powerpc/kernel/fadump.c base = reg->base; base 411 arch/powerpc/kernel/fadump.c hole_size += (base - last_end); base 415 arch/powerpc/kernel/fadump.c ret = add_boot_mem_regions(base, size); base 421 arch/powerpc/kernel/fadump.c ret = add_boot_mem_regions(base, size); base 425 arch/powerpc/kernel/fadump.c last_end = base + size; base 434 arch/powerpc/kernel/fadump.c u64 base, size, mem_boundary, bootmem_min, align = PAGE_SIZE; base 496 arch/powerpc/kernel/fadump.c base = fw_dump.boot_mem_top; base 516 arch/powerpc/kernel/fadump.c fadump_reserve_crash_area(base); base 527 arch/powerpc/kernel/fadump.c base = memblock_find_in_range(base, mem_boundary, size, align); base 532 arch/powerpc/kernel/fadump.c if (!base) { base 536 arch/powerpc/kernel/fadump.c fw_dump.reserve_dump_area_start = base; base 546 arch/powerpc/kernel/fadump.c if (memblock_reserve(base, size)) { base 552 arch/powerpc/kernel/fadump.c (size >> 20), base, (memblock_phys_mem_size() >> 20)); base 764 arch/powerpc/kernel/fadump.c u64 base, u64 end) base 770 arch/powerpc/kernel/fadump.c if (base == end) base 778 arch/powerpc/kernel/fadump.c start = mem_ranges[mrange_info->mem_range_cnt - 1].base; base 781 arch/powerpc/kernel/fadump.c if ((start + size) == base) base 797 arch/powerpc/kernel/fadump.c start = base; base 798 arch/powerpc/kernel/fadump.c mem_ranges[mrange_info->mem_range_cnt].base = start; base 899 arch/powerpc/kernel/fadump.c start = (u64)reg->base; base 1006 arch/powerpc/kernel/fadump.c mbase = crash_mrange_info.mem_ranges[i].base; base 1162 arch/powerpc/kernel/fadump.c u64 base, size; base 1173 arch/powerpc/kernel/fadump.c if (mem_ranges[idx].base > mem_ranges[j].base) base 1186 arch/powerpc/kernel/fadump.c base = mem_ranges[i-1].base; base 1188 arch/powerpc/kernel/fadump.c if (mem_ranges[i].base == (base + size)) base 1225 arch/powerpc/kernel/fadump.c u64 base, size; base 1227 arch/powerpc/kernel/fadump.c base = of_read_number(prop + (i * 4) + 0, 2); base 1232 arch/powerpc/kernel/fadump.c base, base + size); base 1287 arch/powerpc/kernel/fadump.c ra_start = reserved_mrange_info.mem_ranges[i].base; base 1535 arch/powerpc/kernel/fadump.c static void __init fadump_reserve_crash_area(u64 base) base 1541 arch/powerpc/kernel/fadump.c mstart = reg->base; base 1544 arch/powerpc/kernel/fadump.c if ((mstart + msize) < base) base 1547 arch/powerpc/kernel/fadump.c if (mstart < base) { base 1548 arch/powerpc/kernel/fadump.c msize -= (base - mstart); base 1549 arch/powerpc/kernel/fadump.c mstart = base; base 74 arch/powerpc/kernel/legacy_serial.c int iotype, phys_addr_t base, base 131 arch/powerpc/kernel/legacy_serial.c legacy_serial_ports[index].iobase = base; base 133 arch/powerpc/kernel/legacy_serial.c legacy_serial_ports[index].mapbase = base; base 155 arch/powerpc/kernel/legacy_serial.c (unsigned long long)base, (unsigned long long)taddr, irq, base 255 arch/powerpc/kernel/legacy_serial.c u64 addr, base; base 287 arch/powerpc/kernel/legacy_serial.c base = addr; base 289 arch/powerpc/kernel/legacy_serial.c base = of_read_number(&addrp[2], 1); base 310 arch/powerpc/kernel/legacy_serial.c base += 0x200 * lindex; base 313 arch/powerpc/kernel/legacy_serial.c base += 8 * lindex; base 319 arch/powerpc/kernel/legacy_serial.c return add_legacy_port(np, index, iotype, base, addr, 0, base 181 arch/powerpc/kernel/module_32.c if (location >= mod->core_layout.base base 182 arch/powerpc/kernel/module_32.c && location < mod->core_layout.base + mod->core_layout.size) base 300 arch/powerpc/kernel/module_32.c module->arch.tramp = do_plt_call(module->core_layout.base, base 309 arch/powerpc/kernel/pci-common.c unsigned long base = base 311 arch/powerpc/kernel/pci-common.c ret = base + (address - hose->io_base_phys); base 119 arch/powerpc/kernel/pci_of_scan.c u64 base, size; base 141 arch/powerpc/kernel/pci_of_scan.c base = of_read_number(&addrs[1], 2); base 147 arch/powerpc/kernel/pci_of_scan.c (unsigned long long)base, base 163 arch/powerpc/kernel/pci_of_scan.c region.start = base; base 164 arch/powerpc/kernel/pci_of_scan.c region.end = base + size - 1; base 2167 arch/powerpc/kernel/process.c unsigned long base = mm->brk; base 2180 arch/powerpc/kernel/process.c base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); base 2183 arch/powerpc/kernel/process.c ret = PAGE_ALIGN(base + brk_rnd()); base 448 arch/powerpc/kernel/prom.c static bool validate_mem_limit(u64 base, u64 *size) base 452 arch/powerpc/kernel/prom.c if (base >= max_mem) base 454 arch/powerpc/kernel/prom.c if ((base + *size) > max_mem) base 455 arch/powerpc/kernel/prom.c *size = max_mem - base; base 459 arch/powerpc/kernel/prom.c static bool validate_mem_limit(u64 base, u64 *size) base 474 arch/powerpc/kernel/prom.c u64 base, size; base 477 arch/powerpc/kernel/prom.c base = lmb->base_addr; base 507 arch/powerpc/kernel/prom.c base = dt_mem_next_cell(dt_root_addr_cells, usm); base 512 arch/powerpc/kernel/prom.c if (base >= 0x80000000ul) base 514 arch/powerpc/kernel/prom.c if ((base + size) > 0x80000000ul) base 515 arch/powerpc/kernel/prom.c size = 0x80000000ul - base; base 518 arch/powerpc/kernel/prom.c DBG("Adding: %llx -> %llx\n", base, size); base 519 arch/powerpc/kernel/prom.c if (validate_mem_limit(base, &size)) base 520 arch/powerpc/kernel/prom.c memblock_add(base, size); base 554 arch/powerpc/kernel/prom.c void __init early_init_dt_add_memory_arch(u64 base, u64 size) base 558 arch/powerpc/kernel/prom.c if (base >= 0x80000000ul) base 560 arch/powerpc/kernel/prom.c if ((base + size) > 0x80000000ul) base 561 arch/powerpc/kernel/prom.c size = 0x80000000ul - base; base 568 arch/powerpc/kernel/prom.c if (base < memstart_addr) { base 569 arch/powerpc/kernel/prom.c memstart_addr = base; base 575 arch/powerpc/kernel/prom.c if (validate_mem_limit(base, &size)) base 576 arch/powerpc/kernel/prom.c memblock_add(base, size); base 601 arch/powerpc/kernel/prom.c u64 base, size; base 603 arch/powerpc/kernel/prom.c base = of_read_number(prop + (i * 4) + 0, 2); base 607 arch/powerpc/kernel/prom.c DBG("reserving: %llx -> %llx\n", base, size); base 608 arch/powerpc/kernel/prom.c memblock_reserve(base, size); base 127 arch/powerpc/kernel/prom_init.c __be64 base; base 704 arch/powerpc/kernel/prom_init.c unsigned long result = 0, base = 10, value; base 707 arch/powerpc/kernel/prom_init.c base = 8; base 711 arch/powerpc/kernel/prom_init.c base = 16; base 716 arch/powerpc/kernel/prom_init.c (value = isdigit(*cp) ? *cp - '0' : toupper(*cp) - 'A' + 10) < base) { base 717 arch/powerpc/kernel/prom_init.c result = result * base + value; base 1436 arch/powerpc/kernel/prom_init.c unsigned long base = alloc_bottom; base 1440 arch/powerpc/kernel/prom_init.c base = _ALIGN_UP(base, align); base 1446 arch/powerpc/kernel/prom_init.c base = _ALIGN_UP(alloc_bottom, align); base 1448 arch/powerpc/kernel/prom_init.c base = alloc_bottom; base 1450 arch/powerpc/kernel/prom_init.c for(; (base + size) <= alloc_top; base 1451 arch/powerpc/kernel/prom_init.c base = _ALIGN_UP(base + 0x100000, align)) { base 1452 arch/powerpc/kernel/prom_init.c prom_debug(" trying: 0x%lx\n\r", base); base 1453 arch/powerpc/kernel/prom_init.c addr = (unsigned long)prom_claim(base, size, 0); base 1482 arch/powerpc/kernel/prom_init.c unsigned long base, addr = 0; base 1509 arch/powerpc/kernel/prom_init.c base = _ALIGN_DOWN(alloc_top - size, align); base 1510 arch/powerpc/kernel/prom_init.c for (; base > alloc_bottom; base 1511 arch/powerpc/kernel/prom_init.c base = _ALIGN_DOWN(base - 0x100000, align)) { base 1512 arch/powerpc/kernel/prom_init.c prom_debug(" trying: 0x%lx\n\r", base); base 1513 arch/powerpc/kernel/prom_init.c addr = (unsigned long)prom_claim(base, size, 0); base 1565 arch/powerpc/kernel/prom_init.c static void __init reserve_mem(u64 base, u64 size) base 1567 arch/powerpc/kernel/prom_init.c u64 top = base + size; base 1577 arch/powerpc/kernel/prom_init.c base = _ALIGN_DOWN(base, PAGE_SIZE); base 1579 arch/powerpc/kernel/prom_init.c size = top - base; base 1583 arch/powerpc/kernel/prom_init.c mem_reserve_map[cnt].base = cpu_to_be64(base); base 1647 arch/powerpc/kernel/prom_init.c unsigned long base, size; base 1649 arch/powerpc/kernel/prom_init.c base = prom_next_cell(rac, &p); base 1654 arch/powerpc/kernel/prom_init.c prom_debug(" %lx %lx\n", base, size); base 1655 arch/powerpc/kernel/prom_init.c if (base == 0 && (of_platform & PLATFORM_LPAR)) base 1657 arch/powerpc/kernel/prom_init.c if ((base + size) > ram_top) base 1658 arch/powerpc/kernel/prom_init.c ram_top = base + size; base 1778 arch/powerpc/kernel/prom_init.c u32 base, entry = 0; base 1795 arch/powerpc/kernel/prom_init.c base = alloc_down(size, PAGE_SIZE, 0); base 1796 arch/powerpc/kernel/prom_init.c if (base == 0) base 1805 arch/powerpc/kernel/prom_init.c prom_printf("instantiating rtas at 0x%x...", base); base 1809 arch/powerpc/kernel/prom_init.c rtas_inst, base) != 0 base 1816 arch/powerpc/kernel/prom_init.c reserve_mem(base, size); base 1818 arch/powerpc/kernel/prom_init.c val = cpu_to_be32(base); base 1830 arch/powerpc/kernel/prom_init.c prom_debug("rtas base = 0x%x\n", base); base 1846 arch/powerpc/kernel/prom_init.c u64 base; base 1886 arch/powerpc/kernel/prom_init.c base = alloc_down(size, PAGE_SIZE, 0); base 1887 arch/powerpc/kernel/prom_init.c if (base == 0) base 1890 arch/powerpc/kernel/prom_init.c prom_printf("instantiating sml at 0x%llx...", base); base 1892 arch/powerpc/kernel/prom_init.c memset((void *)base, 0, size); base 1896 arch/powerpc/kernel/prom_init.c ibmvtpm_inst, size, base) != 0 || entry == 0) { base 1902 arch/powerpc/kernel/prom_init.c reserve_mem(base, size); base 1905 arch/powerpc/kernel/prom_init.c &base, sizeof(base)); base 1909 arch/powerpc/kernel/prom_init.c prom_debug("sml base = 0x%llx\n", base); base 1925 arch/powerpc/kernel/prom_init.c u64 base, align; base 1983 arch/powerpc/kernel/prom_init.c base = alloc_down(minsize, align, 1); base 1984 arch/powerpc/kernel/prom_init.c if (base == 0) base 1986 arch/powerpc/kernel/prom_init.c if (base < local_alloc_bottom) base 1987 arch/powerpc/kernel/prom_init.c local_alloc_bottom = base; base 1998 arch/powerpc/kernel/prom_init.c prom_setprop(node, path, "linux,tce-base", &base, sizeof(base)); base 2003 arch/powerpc/kernel/prom_init.c prom_debug("\tbase = 0x%llx\n", base); base 2009 arch/powerpc/kernel/prom_init.c tce_entryp = (u64 *)base; base 2025 arch/powerpc/kernel/prom_init.c (u32) base, (u32) (base >> 32)); base 2708 arch/powerpc/kernel/prom_init.c be64_to_cpu(mem_reserve_map[i].base), base 99 arch/powerpc/kernel/rtas.c if (!rtas.base) base 149 arch/powerpc/kernel/rtas.c if (!rtas.base) base 168 arch/powerpc/kernel/rtas.c if (!rtas.base) base 209 arch/powerpc/kernel/rtas.c if (!rtas.base) base 1157 arch/powerpc/kernel/rtas.c u32 base, size, entry; base 1167 arch/powerpc/kernel/rtas.c no_base = of_property_read_u32(rtas.dev, "linux,rtas-base", &base); base 1175 arch/powerpc/kernel/rtas.c rtas.base = base; base 1178 arch/powerpc/kernel/rtas.c rtas.entry = no_entry ? rtas.base : entry; base 1213 arch/powerpc/kernel/rtas.c rtas.base = *basep; base 134 arch/powerpc/kvm/book3s_64_mmu_radix.c u64 pte, base, gpa; base 140 arch/powerpc/kvm/book3s_64_mmu_radix.c base = root & RPDB_MASK; base 159 arch/powerpc/kvm/book3s_64_mmu_radix.c if (base & ((1UL << (bits + 3)) - 1)) base 162 arch/powerpc/kvm/book3s_64_mmu_radix.c addr = base + (index * sizeof(rpte)); base 176 arch/powerpc/kvm/book3s_64_mmu_radix.c base = pte & RPDB_MASK; base 1462 arch/powerpc/kvm/mpic.c u64 base; base 1464 arch/powerpc/kvm/mpic.c if (copy_from_user(&base, (u64 __user *)(long)attr->addr, sizeof(u64))) base 1467 arch/powerpc/kvm/mpic.c if (base & 0x3ffff) { base 1469 arch/powerpc/kvm/mpic.c __func__, base); base 1473 arch/powerpc/kvm/mpic.c if (base == opp->reg_base) base 1479 arch/powerpc/kvm/mpic.c opp->reg_base = base; base 1482 arch/powerpc/kvm/mpic.c __func__, base); base 1484 arch/powerpc/kvm/mpic.c if (base == 0) base 21 arch/powerpc/lib/test_emulate_step.c #define TEST_LD(r, base, i) (PPC_INST_LD | ___PPC_RT(r) | \ base 22 arch/powerpc/lib/test_emulate_step.c ___PPC_RA(base) | IMM_L(i)) base 23 arch/powerpc/lib/test_emulate_step.c #define TEST_LWZ(r, base, i) (PPC_INST_LWZ | ___PPC_RT(r) | \ base 24 arch/powerpc/lib/test_emulate_step.c ___PPC_RA(base) | IMM_L(i)) base 27 arch/powerpc/lib/test_emulate_step.c #define TEST_STD(r, base, i) (PPC_INST_STD | ___PPC_RS(r) | \ base 28 arch/powerpc/lib/test_emulate_step.c ___PPC_RA(base) | ((i) & 0xfffc)) base 107 arch/powerpc/mm/book3s32/mmu.c static unsigned int block_size(unsigned long base, unsigned long top) base 110 arch/powerpc/mm/book3s32/mmu.c unsigned int base_shift = (ffs(base) - 1) & 31; base 111 arch/powerpc/mm/book3s32/mmu.c unsigned int block_shift = (fls(top - base) - 1) & 31; base 148 arch/powerpc/mm/book3s32/mmu.c static unsigned long __init __mmu_mapin_ram(unsigned long base, unsigned long top) base 152 arch/powerpc/mm/book3s32/mmu.c while ((idx = find_free_bat()) != -1 && base != top) { base 153 arch/powerpc/mm/book3s32/mmu.c unsigned int size = block_size(base, top); base 157 arch/powerpc/mm/book3s32/mmu.c setbat(idx, PAGE_OFFSET + base, base, size, PAGE_KERNEL_X); base 158 arch/powerpc/mm/book3s32/mmu.c base += size; base 161 arch/powerpc/mm/book3s32/mmu.c return base; base 164 arch/powerpc/mm/book3s32/mmu.c unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) base 171 arch/powerpc/mm/book3s32/mmu.c return base; base 174 arch/powerpc/mm/book3s32/mmu.c if (!strict_kernel_rwx_enabled() || base >= border || top <= border) base 175 arch/powerpc/mm/book3s32/mmu.c return __mmu_mapin_ram(base, top); base 177 arch/powerpc/mm/book3s32/mmu.c done = __mmu_mapin_ram(base, border); base 188 arch/powerpc/mm/book3s32/mmu.c unsigned long base = (unsigned long)_stext - PAGE_OFFSET; base 195 arch/powerpc/mm/book3s32/mmu.c for (i = 0; i < nb - 1 && base < top && top - base > (128 << 10);) { base 196 arch/powerpc/mm/book3s32/mmu.c size = block_size(base, top); base 197 arch/powerpc/mm/book3s32/mmu.c setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT); base 198 arch/powerpc/mm/book3s32/mmu.c base += size; base 200 arch/powerpc/mm/book3s32/mmu.c if (base < top) { base 201 arch/powerpc/mm/book3s32/mmu.c size = block_size(base, top); base 203 arch/powerpc/mm/book3s32/mmu.c if ((top - base) > size) { base 208 arch/powerpc/mm/book3s32/mmu.c setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT); base 209 arch/powerpc/mm/book3s32/mmu.c base += size; base 841 arch/powerpc/mm/book3s64/hash_utils.c unsigned long base = 0, size = 0; base 932 arch/powerpc/mm/book3s64/hash_utils.c base = (unsigned long)__va(reg->base); base 936 arch/powerpc/mm/book3s64/hash_utils.c base, size, prot); base 938 arch/powerpc/mm/book3s64/hash_utils.c if ((base + size) >= H_VMALLOC_START) { base 943 arch/powerpc/mm/book3s64/hash_utils.c BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), base 959 arch/powerpc/mm/book3s64/hash_utils.c if (base + size >= tce_alloc_start) base 960 arch/powerpc/mm/book3s64/hash_utils.c tce_alloc_start = base + size + 1; base 328 arch/powerpc/mm/book3s64/radix_pgtable.c if ((reg->base + reg->size) >= RADIX_VMALLOC_START) { base 333 arch/powerpc/mm/book3s64/radix_pgtable.c WARN_ON(create_physical_mapping(reg->base, base 334 arch/powerpc/mm/book3s64/radix_pgtable.c reg->base + reg->size, base 145 arch/powerpc/mm/kasan/kasan_init_32.c phys_addr_t base = reg->base; base 146 arch/powerpc/mm/kasan/kasan_init_32.c phys_addr_t top = min(base + reg->size, total_lowmem); base 148 arch/powerpc/mm/kasan/kasan_init_32.c if (base >= top) base 151 arch/powerpc/mm/kasan/kasan_init_32.c ret = kasan_init_region(__va(base), top - base); base 171 arch/powerpc/mm/kasan/kasan_init_32.c void *base; base 173 arch/powerpc/mm/kasan/kasan_init_32.c base = __vmalloc_node_range(size, MODULE_ALIGN, VMALLOC_START, VMALLOC_END, base 177 arch/powerpc/mm/kasan/kasan_init_32.c if (!base) base 180 arch/powerpc/mm/kasan/kasan_init_32.c if (!kasan_init_region(base, size)) base 181 arch/powerpc/mm/kasan/kasan_init_32.c return base; base 183 arch/powerpc/mm/kasan/kasan_init_32.c vfree(base); base 596 arch/powerpc/mm/mem.c unsigned long base = reg->base; base 604 arch/powerpc/mm/mem.c res->start = base; base 605 arch/powerpc/mm/mem.c res->end = base + size - 1; base 130 arch/powerpc/mm/mmu_decl.h unsigned long mmu_mapin_ram(unsigned long base, unsigned long top); base 91 arch/powerpc/mm/nohash/40x.c unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) base 168 arch/powerpc/mm/nohash/44x.c unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) base 106 arch/powerpc/mm/nohash/8xx.c unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) base 219 arch/powerpc/mm/nohash/fsl_booke.c unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) base 266 arch/powerpc/mm/nohash/fsl_booke.c unsigned long base = KERNELBASE; base 292 arch/powerpc/mm/nohash/fsl_booke.c base &= ~0x3ffffff; base 293 arch/powerpc/mm/nohash/fsl_booke.c virt_phys_offset = base - start; base 507 arch/powerpc/mm/numa.c int base, sibling, i; base 510 arch/powerpc/mm/numa.c base = cpu_first_thread_sibling(cpu); base 513 arch/powerpc/mm/numa.c sibling = base + i; base 594 arch/powerpc/mm/numa.c unsigned long base, size, sz; base 608 arch/powerpc/mm/numa.c base = lmb->base_addr; base 620 arch/powerpc/mm/numa.c base = read_n_cells(n_mem_addr_cells, usm); base 625 arch/powerpc/mm/numa.c fake_numa_create_new_node(((base + size) >> PAGE_SHIFT), base 628 arch/powerpc/mm/numa.c sz = numa_enforce_memory_limit(base, size); base 630 arch/powerpc/mm/numa.c memblock_set_node(base, sz, &memblock.memory, nid); base 1297 arch/powerpc/mm/numa.c int nid, base, j; base 1300 arch/powerpc/mm/numa.c base = cpu_first_thread_sibling(update->cpu); base 1303 arch/powerpc/mm/numa.c update_numa_cpu_lookup_table(base + j, nid); base 114 arch/powerpc/mm/pgtable_32.c phys_addr_t base = reg->base; base 115 arch/powerpc/mm/pgtable_32.c phys_addr_t top = min(base + reg->size, total_lowmem); base 117 arch/powerpc/mm/pgtable_32.c if (base >= top) base 119 arch/powerpc/mm/pgtable_32.c base = mmu_mapin_ram(base, top); base 121 arch/powerpc/mm/pgtable_32.c __mapin_ram_chunk(reg->base, top); base 123 arch/powerpc/mm/pgtable_32.c __mapin_ram_chunk(base, top); base 48 arch/powerpc/net/bpf_jit.h #define PPC_STD(r, base, i) EMIT(PPC_INST_STD | ___PPC_RS(r) | \ base 49 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | ((i) & 0xfffc)) base 50 arch/powerpc/net/bpf_jit.h #define PPC_STDX(r, base, b) EMIT(PPC_INST_STDX | ___PPC_RS(r) | \ base 51 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | ___PPC_RB(b)) base 52 arch/powerpc/net/bpf_jit.h #define PPC_STDU(r, base, i) EMIT(PPC_INST_STDU | ___PPC_RS(r) | \ base 53 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | ((i) & 0xfffc)) base 54 arch/powerpc/net/bpf_jit.h #define PPC_STW(r, base, i) EMIT(PPC_INST_STW | ___PPC_RS(r) | \ base 55 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | IMM_L(i)) base 56 arch/powerpc/net/bpf_jit.h #define PPC_STWU(r, base, i) EMIT(PPC_INST_STWU | ___PPC_RS(r) | \ base 57 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | IMM_L(i)) base 58 arch/powerpc/net/bpf_jit.h #define PPC_STH(r, base, i) EMIT(PPC_INST_STH | ___PPC_RS(r) | \ base 59 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | IMM_L(i)) base 60 arch/powerpc/net/bpf_jit.h #define PPC_STB(r, base, i) EMIT(PPC_INST_STB | ___PPC_RS(r) | \ base 61 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | IMM_L(i)) base 63 arch/powerpc/net/bpf_jit.h #define PPC_LBZ(r, base, i) EMIT(PPC_INST_LBZ | ___PPC_RT(r) | \ base 64 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | IMM_L(i)) base 65 arch/powerpc/net/bpf_jit.h #define PPC_LD(r, base, i) EMIT(PPC_INST_LD | ___PPC_RT(r) | \ base 66 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | ((i) & 0xfffc)) base 67 arch/powerpc/net/bpf_jit.h #define PPC_LDX(r, base, b) EMIT(PPC_INST_LDX | ___PPC_RT(r) | \ base 68 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | ___PPC_RB(b)) base 69 arch/powerpc/net/bpf_jit.h #define PPC_LWZ(r, base, i) EMIT(PPC_INST_LWZ | ___PPC_RT(r) | \ base 70 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | IMM_L(i)) base 71 arch/powerpc/net/bpf_jit.h #define PPC_LHZ(r, base, i) EMIT(PPC_INST_LHZ | ___PPC_RT(r) | \ base 72 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | IMM_L(i)) base 73 arch/powerpc/net/bpf_jit.h #define PPC_LHBRX(r, base, b) EMIT(PPC_INST_LHBRX | ___PPC_RT(r) | \ base 74 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | ___PPC_RB(b)) base 75 arch/powerpc/net/bpf_jit.h #define PPC_LDBRX(r, base, b) EMIT(PPC_INST_LDBRX | ___PPC_RT(r) | \ base 76 arch/powerpc/net/bpf_jit.h ___PPC_RA(base) | ___PPC_RB(b)) base 75 arch/powerpc/net/bpf_jit32.h #define PPC_LBZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LBZ(r, base, i); \ base 76 arch/powerpc/net/bpf_jit32.h else { PPC_ADDIS(r, base, IMM_HA(i)); \ base 79 arch/powerpc/net/bpf_jit32.h #define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i); \ base 80 arch/powerpc/net/bpf_jit32.h else { PPC_ADDIS(r, base, IMM_HA(i)); \ base 83 arch/powerpc/net/bpf_jit32.h #define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LWZ(r, base, i); \ base 84 arch/powerpc/net/bpf_jit32.h else { PPC_ADDIS(r, base, IMM_HA(i)); \ base 87 arch/powerpc/net/bpf_jit32.h #define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LHZ(r, base, i); \ base 88 arch/powerpc/net/bpf_jit32.h else { PPC_ADDIS(r, base, IMM_HA(i)); \ base 92 arch/powerpc/net/bpf_jit32.h #define PPC_LL_OFFS(r, base, i) do { PPC_LD_OFFS(r, base, i); } while(0) base 94 arch/powerpc/net/bpf_jit32.h #define PPC_LL_OFFS(r, base, i) do { PPC_LWZ_OFFS(r, base, i); } while(0) base 113 arch/powerpc/net/bpf_jit32.h #define PPC_LHBRX_OFFS(r, base, i) \ base 114 arch/powerpc/net/bpf_jit32.h do { PPC_LI32(r, i); PPC_LHBRX(r, r, base); } while(0) base 116 arch/powerpc/net/bpf_jit32.h #define PPC_NTOHS_OFFS(r, base, i) PPC_LHBRX_OFFS(r, base, i) base 118 arch/powerpc/net/bpf_jit32.h #define PPC_NTOHS_OFFS(r, base, i) PPC_LHZ_OFFS(r, base, i) base 121 arch/powerpc/net/bpf_jit32.h #define PPC_BPF_LL(r, base, i) do { PPC_LWZ(r, base, i); } while(0) base 122 arch/powerpc/net/bpf_jit32.h #define PPC_BPF_STL(r, base, i) do { PPC_STW(r, base, i); } while(0) base 123 arch/powerpc/net/bpf_jit32.h #define PPC_BPF_STLU(r, base, i) do { PPC_STWU(r, base, i); } while(0) base 71 arch/powerpc/net/bpf_jit64.h #define PPC_BPF_LL(r, base, i) do { \ base 74 arch/powerpc/net/bpf_jit64.h PPC_LDX(r, base, b2p[TMP_REG_2]); \ base 76 arch/powerpc/net/bpf_jit64.h PPC_LD(r, base, i); \ base 78 arch/powerpc/net/bpf_jit64.h #define PPC_BPF_STL(r, base, i) do { \ base 81 arch/powerpc/net/bpf_jit64.h PPC_STDX(r, base, b2p[TMP_REG_2]); \ base 83 arch/powerpc/net/bpf_jit64.h PPC_STD(r, base, i); \ base 85 arch/powerpc/net/bpf_jit64.h #define PPC_BPF_STLU(r, base, i) do { PPC_STDU(r, base, i); } while(0) base 182 arch/powerpc/oprofile/cell/spu_profiler.c hrtimer_forward(timer, timer->base->get_time(), kt); base 307 arch/powerpc/oprofile/op_model_power4.c if (pc >= rtas.base && pc < (rtas.base + rtas.size)) base 142 arch/powerpc/perf/imc-pmu.c u32 base, struct imc_events *event) base 150 arch/powerpc/perf/imc-pmu.c event->value = base + reg; base 69 arch/powerpc/platforms/44x/fsp2.c static void show_plbopb_regs(u32 base, int num) base 72 arch/powerpc/platforms/44x/fsp2.c pr_err("GESR0: 0x%08x\n", mfdcr(base + PLB4OPB_GESR0)); base 73 arch/powerpc/platforms/44x/fsp2.c pr_err("GESR1: 0x%08x\n", mfdcr(base + PLB4OPB_GESR1)); base 74 arch/powerpc/platforms/44x/fsp2.c pr_err("GESR2: 0x%08x\n", mfdcr(base + PLB4OPB_GESR2)); base 75 arch/powerpc/platforms/44x/fsp2.c pr_err("GEARU: 0x%08x\n", mfdcr(base + PLB4OPB_GEARU)); base 76 arch/powerpc/platforms/44x/fsp2.c pr_err("GEAR: 0x%08x\n", mfdcr(base + PLB4OPB_GEAR)); base 28 arch/powerpc/platforms/512x/mpc512x_lpbfifo.c u32 base; /* must be zero */ base 418 arch/powerpc/platforms/512x/mpc512x_lpbfifo.c if (lpbfifo.cs_ranges[i].base != 0) base 341 arch/powerpc/platforms/52xx/mpc52xx_gpt.c gpt->gc.base = -1; base 52 arch/powerpc/platforms/83xx/km83xx.c void __iomem *base; base 67 arch/powerpc/platforms/83xx/km83xx.c base = ioremap(res.start, res.end - res.start + 1); base 77 arch/powerpc/platforms/83xx/km83xx.c clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000); base 87 arch/powerpc/platforms/83xx/km83xx.c clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550); base 94 arch/powerpc/platforms/83xx/km83xx.c clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0); base 100 arch/powerpc/platforms/83xx/km83xx.c setbits32((base + 0xa8), 0x00003000); base 106 arch/powerpc/platforms/83xx/km83xx.c setbits32((base + 0xa8), 0x0c000000); base 112 arch/powerpc/platforms/83xx/km83xx.c setbits32((base + 0xac), 0x0000c000); base 114 arch/powerpc/platforms/83xx/km83xx.c iounmap(base); base 130 arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c gc->base = -1; base 95 arch/powerpc/platforms/cell/interrupt.c unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC; base 112 arch/powerpc/platforms/cell/interrupt.c base | cascade); base 256 arch/powerpc/platforms/cell/iommu.c static int cell_iommu_find_ioc(int nid, unsigned long *base) base 261 arch/powerpc/platforms/cell/iommu.c *base = 0; base 272 arch/powerpc/platforms/cell/iommu.c *base = r.start; base 286 arch/powerpc/platforms/cell/iommu.c *base = *tmp; base 317 arch/powerpc/platforms/cell/iommu.c unsigned long base, unsigned long size, unsigned long gap_base, base 325 arch/powerpc/platforms/cell/iommu.c start_seg = base >> IO_SEGMENT_SHIFT; base 417 arch/powerpc/platforms/cell/iommu.c unsigned long base, unsigned long size) base 419 arch/powerpc/platforms/cell/iommu.c cell_iommu_setup_stab(iommu, base, size, 0, 0); base 420 arch/powerpc/platforms/cell/iommu.c iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0, base 599 arch/powerpc/platforms/cell/iommu.c unsigned long *base, base 608 arch/powerpc/platforms/cell/iommu.c *base = 0; base 613 arch/powerpc/platforms/cell/iommu.c of_parse_dma_window(np, dma_window, &index, base, size); base 661 arch/powerpc/platforms/cell/iommu.c unsigned long base, size; base 668 arch/powerpc/platforms/cell/iommu.c cell_iommu_get_window(np, &base, &size); base 671 arch/powerpc/platforms/cell/iommu.c base, base + size - 1); base 674 arch/powerpc/platforms/cell/iommu.c cell_iommu_setup_hardware(iommu, base, size); base 677 arch/powerpc/platforms/cell/iommu.c cell_iommu_setup_window(iommu, np, base, size, base 684 arch/powerpc/platforms/cell/iommu.c unsigned long base, val; base 689 arch/powerpc/platforms/cell/iommu.c if (cell_iommu_find_ioc(node, &base)) base 691 arch/powerpc/platforms/cell/iommu.c xregs = ioremap(base, IOC_Reg_Size); base 712 arch/powerpc/platforms/cell/iommu.c unsigned long base = 0, size; base 732 arch/powerpc/platforms/cell/iommu.c if (cell_iommu_get_window(np, &base, &size) == 0) base 739 arch/powerpc/platforms/cell/iommu.c if (cell_iommu_get_window(np, &base, &size) == 0) base 755 arch/powerpc/platforms/cell/iommu.c cell_dma_nommu_offset += base; base 47 arch/powerpc/platforms/chrp/time.c int base; base 60 arch/powerpc/platforms/chrp/time.c base = r.start; base 62 arch/powerpc/platforms/chrp/time.c nvram_as0 = base; base 63 arch/powerpc/platforms/chrp/time.c nvram_data = base + 1; base 62 arch/powerpc/platforms/embedded6xx/wii.c BUG_ON(!page_aligned(p[0].base) || !page_aligned(p[1].base)); base 89 arch/powerpc/platforms/powermac/bootx_init.c static void * __init bootx_early_getprop(unsigned long base, base 93 arch/powerpc/platforms/powermac/bootx_init.c struct bootx_dt_node *np = (struct bootx_dt_node *)(base + node); base 98 arch/powerpc/platforms/powermac/bootx_init.c (struct bootx_dt_prop *)(base + *ppp); base 100 arch/powerpc/platforms/powermac/bootx_init.c if (strcmp((char *)((unsigned long)pp->name + base), base 102 arch/powerpc/platforms/powermac/bootx_init.c return (void *)((unsigned long)pp->value + base); base 157 arch/powerpc/platforms/powermac/bootx_init.c static void __init bootx_add_chosen_props(unsigned long base, base 180 arch/powerpc/platforms/powermac/bootx_init.c static void __init bootx_add_display_props(unsigned long base, base 216 arch/powerpc/platforms/powermac/bootx_init.c static void __init bootx_scan_dt_build_strings(unsigned long base, base 220 arch/powerpc/platforms/powermac/bootx_init.c struct bootx_dt_node *np = (struct bootx_dt_node *)(base + node); base 226 arch/powerpc/platforms/powermac/bootx_init.c namep = np->full_name ? (char *)(base + np->full_name) : NULL; base 252 arch/powerpc/platforms/powermac/bootx_init.c (struct bootx_dt_prop *)(base + *ppp); base 254 arch/powerpc/platforms/powermac/bootx_init.c namep = pp->name ? (char *)(base + pp->name) : NULL; base 268 arch/powerpc/platforms/powermac/bootx_init.c np = (struct bootx_dt_node *)(base + *cpp); base 269 arch/powerpc/platforms/powermac/bootx_init.c bootx_scan_dt_build_strings(base, *cpp, mem_end); base 274 arch/powerpc/platforms/powermac/bootx_init.c static void __init bootx_scan_dt_build_struct(unsigned long base, base 278 arch/powerpc/platforms/powermac/bootx_init.c struct bootx_dt_node *np = (struct bootx_dt_node *)(base + node); base 286 arch/powerpc/platforms/powermac/bootx_init.c namep = np->full_name ? (char *)(base + np->full_name) : NULL; base 311 arch/powerpc/platforms/powermac/bootx_init.c (struct bootx_dt_prop *)(base + *ppp); base 313 arch/powerpc/platforms/powermac/bootx_init.c namep = pp->name ? (char *)(base + pp->name) : NULL; base 323 arch/powerpc/platforms/powermac/bootx_init.c pp->value ? (void *)(base + pp->value): NULL, base 330 arch/powerpc/platforms/powermac/bootx_init.c bootx_add_chosen_props(base, mem_end); base 332 arch/powerpc/platforms/powermac/bootx_init.c bootx_add_display_props(base, mem_end, 0); base 335 arch/powerpc/platforms/powermac/bootx_init.c bootx_add_display_props(base, mem_end, 1); base 340 arch/powerpc/platforms/powermac/bootx_init.c np = (struct bootx_dt_node *)(base + *cpp); base 341 arch/powerpc/platforms/powermac/bootx_init.c bootx_scan_dt_build_struct(base, *cpp, mem_end); base 353 arch/powerpc/platforms/powermac/bootx_init.c unsigned long base; base 368 arch/powerpc/platforms/powermac/bootx_init.c base = ((unsigned long)bi) + bi->deviceTreeOffset; base 372 arch/powerpc/platforms/powermac/bootx_init.c DBG("Device Tree Base=%x\n", base); base 376 arch/powerpc/platforms/powermac/bootx_init.c bootx_scan_dt_build_strings(base, 4, &mem_end); base 392 arch/powerpc/platforms/powermac/bootx_init.c bootx_scan_dt_build_struct(base, 4, &mem_end); base 497 arch/powerpc/platforms/powermac/feature.c (macio->base + ((0x8000+i*0x100)>>2)); base 513 arch/powerpc/platforms/powermac/feature.c (macio->base + ((0x8000+i*0x100)>>2)); base 2619 arch/powerpc/platforms/powermac/feature.c volatile u32 __iomem *base; base 2656 arch/powerpc/platforms/powermac/feature.c base = ioremap(addr, (unsigned long)size); base 2657 arch/powerpc/platforms/powermac/feature.c if (!base) { base 2673 arch/powerpc/platforms/powermac/feature.c macio_chips[i].base = base; base 2680 arch/powerpc/platforms/powermac/feature.c macio_names[type], macio_chips[i].rev, macio_chips[i].base); base 108 arch/powerpc/platforms/powermac/low_i2c.c void __iomem *base; /* register base address */ base 196 arch/powerpc/platforms/powermac/low_i2c.c return readb(host->base + (((unsigned int)reg) << host->bsteps)); base 202 arch/powerpc/platforms/powermac/low_i2c.c writeb(val, host->base + (((unsigned)reg) << host->bsteps)); base 538 arch/powerpc/platforms/powermac/low_i2c.c host->base = ioremap((*addrp), 0x1000); base 539 arch/powerpc/platforms/powermac/low_i2c.c if (host->base == NULL) { base 285 arch/powerpc/platforms/powermac/nvram.c u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; base 289 arch/powerpc/platforms/powermac/nvram.c out_8(base, SM_FLASH_CMD_ERASE_SETUP); base 290 arch/powerpc/platforms/powermac/nvram.c out_8(base, SM_FLASH_CMD_ERASE_CONFIRM); base 297 arch/powerpc/platforms/powermac/nvram.c out_8(base, SM_FLASH_CMD_READ_STATUS); base 298 arch/powerpc/platforms/powermac/nvram.c stat = in_8(base); base 301 arch/powerpc/platforms/powermac/nvram.c out_8(base, SM_FLASH_CMD_CLEAR_STATUS); base 302 arch/powerpc/platforms/powermac/nvram.c out_8(base, SM_FLASH_CMD_RESET); base 304 arch/powerpc/platforms/powermac/nvram.c if (memchr_inv(base, 0xff, NVRAM_SIZE)) { base 316 arch/powerpc/platforms/powermac/nvram.c u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; base 321 arch/powerpc/platforms/powermac/nvram.c out_8(base+i, SM_FLASH_CMD_WRITE_SETUP); base 323 arch/powerpc/platforms/powermac/nvram.c out_8(base+i, datas[i]); base 330 arch/powerpc/platforms/powermac/nvram.c out_8(base, SM_FLASH_CMD_READ_STATUS); base 331 arch/powerpc/platforms/powermac/nvram.c stat = in_8(base); base 336 arch/powerpc/platforms/powermac/nvram.c out_8(base, SM_FLASH_CMD_CLEAR_STATUS); base 337 arch/powerpc/platforms/powermac/nvram.c out_8(base, SM_FLASH_CMD_RESET); base 338 arch/powerpc/platforms/powermac/nvram.c if (memcmp(base, datas, NVRAM_SIZE)) { base 350 arch/powerpc/platforms/powermac/nvram.c u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; base 355 arch/powerpc/platforms/powermac/nvram.c out_8(base+0x555, 0xaa); base 358 arch/powerpc/platforms/powermac/nvram.c out_8(base+0x2aa, 0x55); base 362 arch/powerpc/platforms/powermac/nvram.c out_8(base+0x555, 0x80); base 364 arch/powerpc/platforms/powermac/nvram.c out_8(base+0x555, 0xaa); base 366 arch/powerpc/platforms/powermac/nvram.c out_8(base+0x2aa, 0x55); base 368 arch/powerpc/platforms/powermac/nvram.c out_8(base, 0x30); base 377 arch/powerpc/platforms/powermac/nvram.c stat = in_8(base) ^ in_8(base); base 381 arch/powerpc/platforms/powermac/nvram.c out_8(base, 0xf0); base 384 arch/powerpc/platforms/powermac/nvram.c if (memchr_inv(base, 0xff, NVRAM_SIZE)) { base 396 arch/powerpc/platforms/powermac/nvram.c u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; base 402 arch/powerpc/platforms/powermac/nvram.c out_8(base+0x555, 0xaa); base 405 arch/powerpc/platforms/powermac/nvram.c out_8(base+0x2aa, 0x55); base 409 arch/powerpc/platforms/powermac/nvram.c out_8(base+0x555, 0xa0); base 411 arch/powerpc/platforms/powermac/nvram.c out_8(base+i, datas[i]); base 419 arch/powerpc/platforms/powermac/nvram.c stat = in_8(base) ^ in_8(base); base 426 arch/powerpc/platforms/powermac/nvram.c out_8(base, 0xf0); base 429 arch/powerpc/platforms/powermac/nvram.c if (memcmp(base, datas, NVRAM_SIZE)) { base 666 arch/powerpc/platforms/powermac/pci.c unsigned long base, end, next = -1; base 676 arch/powerpc/platforms/powermac/pci.c base = 0xf0000000 | (((u32)i) << 24); base 677 arch/powerpc/platforms/powermac/pci.c end = base + 0x00ffffff; base 679 arch/powerpc/platforms/powermac/pci.c base = ((u32)i-16) << 28; base 680 arch/powerpc/platforms/powermac/pci.c end = base + 0x0fffffff; base 682 arch/powerpc/platforms/powermac/pci.c if (base != next) { base 689 arch/powerpc/platforms/powermac/pci.c hose->mem_resources[cur].start = base; base 692 arch/powerpc/platforms/powermac/pci.c DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end); base 128 arch/powerpc/platforms/powermac/pfunc_base.c offset += (unsigned long)macio->base; base 251 arch/powerpc/platforms/powernv/ocxl.c int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled, base 273 arch/powerpc/platforms/powernv/ocxl.c *base = link->fn_actags[PCI_FUNC(dev->devfn)].start; base 118 arch/powerpc/platforms/powernv/opal-fadump.c unsigned long base, size, last_end, hole_size; base 130 arch/powerpc/platforms/powernv/opal-fadump.c base = fdm->rgn[i].src; base 132 arch/powerpc/platforms/powernv/opal-fadump.c pr_debug("\t[%03d] base: 0x%lx, size: 0x%lx\n", i, base, size); base 134 arch/powerpc/platforms/powernv/opal-fadump.c fadump_conf->boot_mem_addr[i] = base; base 137 arch/powerpc/platforms/powernv/opal-fadump.c hole_size += (base - last_end); base 139 arch/powerpc/platforms/powernv/opal-fadump.c last_end = base + size; base 653 arch/powerpc/platforms/powernv/opal-fadump.c u64 base, end; base 655 arch/powerpc/platforms/powernv/opal-fadump.c base = of_read_number(prop + (i * 4) + 0, 2); base 656 arch/powerpc/platforms/powernv/opal-fadump.c end = base; base 660 arch/powerpc/platforms/powernv/opal-fadump.c base, end); base 42 arch/powerpc/platforms/powernv/opal.c u64 base; base 114 arch/powerpc/platforms/powernv/opal.c opal.base = of_read_number(basep, basesz/4); base 119 arch/powerpc/platforms/powernv/opal.c opal.base, basep, basesz); base 683 arch/powerpc/platforms/powernv/opal.c if (!opal.base || !opal.size) base 686 arch/powerpc/platforms/powernv/opal.c if ((regs->nip >= opal.base) && base 687 arch/powerpc/platforms/powernv/opal.c (regs->nip < (opal.base + opal.size))) base 257 arch/powerpc/platforms/powernv/pci-ioda.c resource_size_t base, sgsz, start, end; base 260 arch/powerpc/platforms/powernv/pci-ioda.c base = phb->ioda.m64_base; base 267 arch/powerpc/platforms/powernv/pci-ioda.c start = _ALIGN_DOWN(r->start - base, sgsz); base 268 arch/powerpc/platforms/powernv/pci-ioda.c end = _ALIGN_UP(r->end - base, sgsz); base 289 arch/powerpc/platforms/powernv/pci-ioda.c unsigned long base, segsz = phb->ioda.m64_segsize; base 292 arch/powerpc/platforms/powernv/pci-ioda.c base = phb->ioda.m64_base + base 295 arch/powerpc/platforms/powernv/pci-ioda.c OPAL_M64_WINDOW_TYPE, index, base, 0, base 2178 arch/powerpc/platforms/powernv/pci-ioda.c unsigned int tce32_segsz, base, segs, avail, i; base 2202 arch/powerpc/platforms/powernv/pci-ioda.c for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { base 2203 arch/powerpc/platforms/powernv/pci-ioda.c for (avail = 0, i = base; i < base + segs; i++) { base 2230 arch/powerpc/platforms/powernv/pci-ioda.c weight, total_weight, base, segs); base 2232 arch/powerpc/platforms/powernv/pci-ioda.c base * PNV_IODA1_DMA32_SEGSIZE, base 2233 arch/powerpc/platforms/powernv/pci-ioda.c (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); base 2257 arch/powerpc/platforms/powernv/pci-ioda.c base + i, 1, base 2268 arch/powerpc/platforms/powernv/pci-ioda.c for (i = base; i < base + segs; i++) base 2273 arch/powerpc/platforms/powernv/pci-ioda.c base * PNV_IODA1_DMA32_SEGSIZE, base 30 arch/powerpc/platforms/powernv/vas-window.c u64 base, shift; base 32 arch/powerpc/platforms/powernv/vas-window.c base = window->vinst->paste_base_addr; base 36 arch/powerpc/platforms/powernv/vas-window.c *addr = base + (winid << shift); base 73 arch/powerpc/platforms/ps3/mm.c u64 base; base 113 arch/powerpc/platforms/ps3/mm.c DBG("%s:%d: map.r1.base = %llxh\n", func, line, m->r1.base); base 220 arch/powerpc/platforms/ps3/mm.c result = ps3_repository_read_highmem_info(0, &r->base, &r->size); base 225 arch/powerpc/platforms/ps3/mm.c if (!r->base || !r->size) { base 230 arch/powerpc/platforms/ps3/mm.c r->offset = r->base - map.rm.size; base 233 arch/powerpc/platforms/ps3/mm.c __func__, __LINE__, r->base, r->size); base 240 arch/powerpc/platforms/ps3/mm.c r->size = r->base = r->offset = 0; base 248 arch/powerpc/platforms/ps3/mm.c return r ? ps3_repository_write_highmem_info(0, r->base, r->size) : base 280 arch/powerpc/platforms/ps3/mm.c ALLOCATE_MEMORY_TRY_ALT_UNIT, &r->base, &muid); base 282 arch/powerpc/platforms/ps3/mm.c if (result || r->base < map.rm.size) { base 289 arch/powerpc/platforms/ps3/mm.c r->offset = r->base - map.rm.size; base 293 arch/powerpc/platforms/ps3/mm.c r->size = r->base = r->offset = 0; base 308 arch/powerpc/platforms/ps3/mm.c __func__, __LINE__, r->base, r->size); base 312 arch/powerpc/platforms/ps3/mm.c DBG("%s:%d: r->base = %llxh\n", __func__, __LINE__, r->base); base 314 arch/powerpc/platforms/ps3/mm.c if (r->base) { base 315 arch/powerpc/platforms/ps3/mm.c result = lv1_release_memory(r->base); base 317 arch/powerpc/platforms/ps3/mm.c r->size = r->base = r->offset = 0; base 986 arch/powerpc/platforms/ps3/mm.c virt_addr = map.rm.base + r->offset; base 1028 arch/powerpc/platforms/ps3/mm.c lpar_addr = map.rm.base + r->offset; base 1039 arch/powerpc/platforms/ps3/mm.c lpar_addr = map.r1.base; base 1192 arch/powerpc/platforms/ps3/mm.c result = ps3_repository_read_mm_info(&map.rm.base, &map.rm.size, base 1198 arch/powerpc/platforms/ps3/mm.c map.rm.offset = map.rm.base; base 1203 arch/powerpc/platforms/ps3/mm.c BUG_ON(map.rm.base); base 282 arch/powerpc/platforms/pseries/hotplug-memory.c static int pseries_remove_memblock(unsigned long base, unsigned int memblock_size) base 288 arch/powerpc/platforms/pseries/hotplug-memory.c start_pfn = base >> PAGE_SHIFT; base 297 arch/powerpc/platforms/pseries/hotplug-memory.c nid = memory_add_physaddr_to_nid(base); base 300 arch/powerpc/platforms/pseries/hotplug-memory.c __remove_memory(nid, base, MIN_MEMORY_BLOCK_SIZE); base 301 arch/powerpc/platforms/pseries/hotplug-memory.c base += MIN_MEMORY_BLOCK_SIZE; base 306 arch/powerpc/platforms/pseries/hotplug-memory.c memblock_remove(base, memblock_size); base 314 arch/powerpc/platforms/pseries/hotplug-memory.c unsigned long base; base 331 arch/powerpc/platforms/pseries/hotplug-memory.c base = be64_to_cpu(*(unsigned long *)regs); base 334 arch/powerpc/platforms/pseries/hotplug-memory.c pseries_remove_memblock(base, lmb_size); base 615 arch/powerpc/platforms/pseries/hotplug-memory.c static inline int pseries_remove_memblock(unsigned long base, base 949 arch/powerpc/platforms/pseries/hotplug-memory.c unsigned long base; base 966 arch/powerpc/platforms/pseries/hotplug-memory.c base = be64_to_cpu(*(unsigned long *)regs); base 972 arch/powerpc/platforms/pseries/hotplug-memory.c ret = memblock_add(base, lmb_size); base 1659 arch/powerpc/platforms/pseries/lpar.c static int pseries_lpar_register_process_table(unsigned long base, base 1672 arch/powerpc/platforms/pseries/lpar.c rc = plpar_hcall_norets(H_REGISTER_PROC_TBL, flags, base, base 401 arch/powerpc/platforms/pseries/ras.c (((A) >= rtas.base) && ((A) < (rtas.base + rtas.size - 16)))) base 621 arch/powerpc/platforms/pseries/setup.c resource_size_t base, size; base 629 arch/powerpc/platforms/pseries/setup.c base = of_read_number(&indexes[i], 2); base 635 arch/powerpc/platforms/pseries/setup.c res->start = base; base 636 arch/powerpc/platforms/pseries/setup.c res->end = base + size - 1; base 643 arch/powerpc/platforms/pseries/setup.c resource_size_t base, size; base 655 arch/powerpc/platforms/pseries/setup.c base = of_read_number(&indexes[i], 2); base 658 arch/powerpc/platforms/pseries/setup.c res->start = base; base 659 arch/powerpc/platforms/pseries/setup.c res->end = base + size - 1; base 135 arch/powerpc/sysdev/dart_iommu.c static void dart_cache_sync(unsigned int *base, unsigned int count) base 142 arch/powerpc/sysdev/dart_iommu.c unsigned long start = (unsigned long)base; base 266 arch/powerpc/sysdev/dart_iommu.c unsigned long base, size; base 304 arch/powerpc/sysdev/dart_iommu.c base = ((unsigned long)dart_tablebase) >> DART_PAGE_SHIFT; base 308 arch/powerpc/sysdev/dart_iommu.c DART_OUT(DART_BASE_U4, base); base 315 arch/powerpc/sysdev/dart_iommu.c (base << DART_CNTL_U3_BASE_SHIFT) | base 182 arch/powerpc/sysdev/dcr.c dcr_host_mmio_t ret = { .token = NULL, .stride = 0, .base = dcr_n }; base 210 arch/powerpc/sysdev/dcr.c h.token += host.base * h.stride; base 22 arch/powerpc/sysdev/fsl_mpic_err.c static inline u32 mpic_fsl_err_read(u32 __iomem *base, unsigned int err_reg) base 24 arch/powerpc/sysdev/fsl_mpic_err.c return in_be32(base + (err_reg >> 2)); base 27 arch/powerpc/sysdev/fsl_mpic_err.c static inline void mpic_fsl_err_write(u32 __iomem *base, u32 value) base 29 arch/powerpc/sysdev/fsl_mpic_err.c out_be32(base + (MPIC_ERR_INT_EIMR >> 2), value); base 52 arch/powerpc/sysdev/fsl_msi.c static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) base 54 arch/powerpc/sysdev/fsl_msi.c return in_be32(base + (reg >> 2)); base 913 arch/powerpc/sysdev/fsl_pci.c u32 base; base 916 arch/powerpc/sysdev/fsl_pci.c PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); base 923 arch/powerpc/sysdev/fsl_pci.c base &= PCI_BASE_ADDRESS_MEM_MASK; base 925 arch/powerpc/sysdev/fsl_pci.c return base; base 360 arch/powerpc/sysdev/fsl_rcpm.c void __iomem *base; base 366 arch/powerpc/sysdev/fsl_rcpm.c base = of_iomap(np, 0); base 368 arch/powerpc/sysdev/fsl_rcpm.c if (!base) { base 373 arch/powerpc/sysdev/fsl_rcpm.c rcpm_v1_regs = base; base 374 arch/powerpc/sysdev/fsl_rcpm.c rcpm_v2_regs = base; base 163 arch/powerpc/sysdev/indirect_pci.c resource_size_t base = cfg_addr & PAGE_MASK; base 166 arch/powerpc/sysdev/indirect_pci.c mbase = ioremap(base, PAGE_SIZE); base 168 arch/powerpc/sysdev/indirect_pci.c if ((cfg_data & PAGE_MASK) != base) base 505 arch/powerpc/sysdev/ipic.c static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg) base 507 arch/powerpc/sysdev/ipic.c return in_be32(base + (reg >> 2)); base 510 arch/powerpc/sysdev/ipic.c static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value) base 512 arch/powerpc/sysdev/ipic.c out_be32(base + (reg >> 2), value); base 183 arch/powerpc/sysdev/mpic.c return in_be32(rb->base + (reg >> 2)); base 186 arch/powerpc/sysdev/mpic.c return in_le32(rb->base + (reg >> 2)); base 201 arch/powerpc/sysdev/mpic.c out_be32(rb->base + (reg >> 2), value); base 205 arch/powerpc/sysdev/mpic.c out_le32(rb->base + (reg >> 2), value); base 318 arch/powerpc/sysdev/mpic.c rb->base = ioremap(phys_addr + offset, size); base 319 arch/powerpc/sysdev/mpic.c BUG_ON(rb->base == NULL); base 371 arch/powerpc/sysdev/mpic.c return mpic->fixups[source].base != NULL; base 385 arch/powerpc/sysdev/mpic.c writeb(0x11 + 2 * fixup->index, fixup->base + 2); base 386 arch/powerpc/sysdev/mpic.c writel(fixup->data, fixup->base + 4); base 398 arch/powerpc/sysdev/mpic.c if (fixup->base == NULL) base 405 arch/powerpc/sysdev/mpic.c writeb(0x10 + 2 * fixup->index, fixup->base + 2); base 406 arch/powerpc/sysdev/mpic.c tmp = readl(fixup->base + 4); base 410 arch/powerpc/sysdev/mpic.c writel(tmp, fixup->base + 4); base 426 arch/powerpc/sysdev/mpic.c if (fixup->base == NULL) base 433 arch/powerpc/sysdev/mpic.c writeb(0x10 + 2 * fixup->index, fixup->base + 2); base 434 arch/powerpc/sysdev/mpic.c tmp = readl(fixup->base + 4); base 436 arch/powerpc/sysdev/mpic.c writel(tmp, fixup->base + 4); base 450 arch/powerpc/sysdev/mpic.c u8 __iomem *base; base 467 arch/powerpc/sysdev/mpic.c base = devbase + pos; base 469 arch/powerpc/sysdev/mpic.c flags = readb(base + HT_MSI_FLAGS); base 471 arch/powerpc/sysdev/mpic.c addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; base 472 arch/powerpc/sysdev/mpic.c addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); base 480 arch/powerpc/sysdev/mpic.c writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); base 494 arch/powerpc/sysdev/mpic.c u8 __iomem *base; base 510 arch/powerpc/sysdev/mpic.c base = devbase + pos; base 511 arch/powerpc/sysdev/mpic.c writeb(0x01, base + 2); base 512 arch/powerpc/sysdev/mpic.c n = (readl(base + 4) >> 16) & 0xff; base 519 arch/powerpc/sysdev/mpic.c writeb(0x10 + 2 * i, base + 2); base 520 arch/powerpc/sysdev/mpic.c tmp = readl(base + 4); base 525 arch/powerpc/sysdev/mpic.c writel(tmp, base + 4); base 527 arch/powerpc/sysdev/mpic.c mpic->fixups[irq].base = base; base 533 arch/powerpc/sysdev/mpic.c writeb(0x11 + 2 * i, base + 2); base 534 arch/powerpc/sysdev/mpic.c mpic->fixups[irq].data = readl(base + 4) | 0x80000000; base 1973 arch/powerpc/sysdev/mpic.c if (fixup->base) { base 1979 arch/powerpc/sysdev/mpic.c writeb(0x10 + 2 * fixup->index, fixup->base + 2); base 1982 arch/powerpc/sysdev/mpic.c fixup->base + 4); base 228 arch/powerpc/sysdev/mpic_msgr.c msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE; base 229 arch/powerpc/sysdev/mpic_msgr.c msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET); base 36 arch/powerpc/sysdev/xive/spapr.c unsigned int base; base 44 arch/powerpc/sysdev/xive/spapr.c static int xive_irq_bitmap_add(int base, int count) base 53 arch/powerpc/sysdev/xive/spapr.c xibm->base = base; base 62 arch/powerpc/sysdev/xive/spapr.c pr_info("Using IRQ range [%x-%x]", xibm->base, base 63 arch/powerpc/sysdev/xive/spapr.c xibm->base + xibm->count - 1); base 74 arch/powerpc/sysdev/xive/spapr.c irq += xibm->base; base 104 arch/powerpc/sysdev/xive/spapr.c if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) { base 106 arch/powerpc/sysdev/xive/spapr.c clear_bit(irq - xibm->base, xibm->bitmap); base 706 arch/powerpc/sysdev/xive/spapr.c int base = be32_to_cpu(reg[2 * i]); base 709 arch/powerpc/sysdev/xive/spapr.c if (prio >= base && prio < base + range) base 1727 arch/powerpc/xmon/xmon.c unsigned long base; base 1730 arch/powerpc/xmon/xmon.c if (scanhex(&base)) { base 1734 arch/powerpc/xmon/xmon.c regs = *(struct pt_regs *)base; base 1740 arch/powerpc/xmon/xmon.c base); base 24 arch/riscv/include/asm/vdso.h #define VDSO_SYMBOL(base, name) \ base 27 arch/riscv/include/asm/vdso.h (void __user *)((unsigned long)(base) + __vdso_##name); \ base 99 arch/riscv/mm/init.c phys_addr_t end = reg->base + reg->size; base 101 arch/riscv/mm/init.c if (reg->base <= vmlinux_start && vmlinux_end <= end) { base 108 arch/riscv/mm/init.c if (reg->base + mem_size < end) base 109 arch/riscv/mm/init.c memblock_remove(reg->base + mem_size, base 110 arch/riscv/mm/init.c end - reg->base - mem_size); base 316 arch/riscv/mm/init.c static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size) base 321 arch/riscv/mm/init.c if (!(base & (PTE_PARENT_SIZE - 1)) && base 426 arch/riscv/mm/init.c start = reg->base; base 95 arch/s390/boot/kaslr.c unsigned long base, start, end, kernel_size; base 146 arch/s390/boot/kaslr.c base = get_random(block_sum); base 147 arch/s390/boot/kaslr.c if (base == 0) base 149 arch/s390/boot/kaslr.c if (base < safe_addr) base 150 arch/s390/boot/kaslr.c base = safe_addr; base 162 arch/s390/boot/kaslr.c if (base <= block_sum) { base 163 arch/s390/boot/kaslr.c base = start + base - offset; base 164 arch/s390/boot/kaslr.c base = ALIGN_DOWN(base, THREAD_SIZE); base 169 arch/s390/boot/kaslr.c return base; base 71 arch/s390/boot/string.c unsigned int base) base 75 arch/s390/boot/string.c if (!base) base 76 arch/s390/boot/string.c base = simple_guess_base(cp); base 78 arch/s390/boot/string.c if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x') base 85 arch/s390/boot/string.c if (value >= base) base 87 arch/s390/boot/string.c result = result * base + value; base 96 arch/s390/boot/string.c long simple_strtol(const char *cp, char **endp, unsigned int base) base 99 arch/s390/boot/string.c return -simple_strtoull(cp + 1, endp, base); base 101 arch/s390/boot/string.c return simple_strtoull(cp, endp, base); base 77 arch/s390/crypto/aes_s390.c sctx->fallback.cip->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; base 78 arch/s390/crypto/aes_s390.c sctx->fallback.cip->base.crt_flags |= (tfm->crt_flags & base 84 arch/s390/crypto/aes_s390.c tfm->crt_flags |= (sctx->fallback.cip->base.crt_flags & base 1109 arch/s390/crypto/aes_s390.c .base = { base 238 arch/s390/crypto/crc32-vx.c .base = { base 259 arch/s390/crypto/crc32-vx.c .base = { base 280 arch/s390/crypto/crc32-vx.c .base = { base 127 arch/s390/crypto/ghash_s390.c .base = { base 77 arch/s390/crypto/sha1_s390.c .base = { base 70 arch/s390/crypto/sha256_s390.c .base = { base 106 arch/s390/crypto/sha256_s390.c .base = { base 79 arch/s390/crypto/sha3_256_s390.c .base = { base 108 arch/s390/crypto/sha3_256_s390.c .base = { base 86 arch/s390/crypto/sha3_512_s390.c .base = { base 117 arch/s390/crypto/sha3_512_s390.c .base = { base 75 arch/s390/crypto/sha512_s390.c .base = { base 113 arch/s390/crypto/sha512_s390.c .base = { base 408 arch/s390/hypfs/hypfs_diag.c void *base; base 411 arch/s390/hypfs/hypfs_diag.c base = vzalloc(buf_size); base 412 arch/s390/hypfs/hypfs_diag.c if (!base) base 414 arch/s390/hypfs/hypfs_diag.c d204 = page_align_ptr(base + sizeof(d204->hdr)) - sizeof(d204->hdr); base 417 arch/s390/hypfs/hypfs_diag.c vfree(base); base 424 arch/s390/hypfs/hypfs_diag.c *data_free_ptr = base; base 37 arch/s390/include/asm/os_info.h void os_info_crashkernel_add(unsigned long base, unsigned long size); base 269 arch/s390/include/asm/vx-insn.h .macro VLVGB v, gr, index, base base 292 arch/s390/include/asm/vx-insn.h .macro VL v, disp, index="%r0", base base 302 arch/s390/include/asm/vx-insn.h .macro VLEx vr1, disp, index="%r0", base, m3, opc base 310 arch/s390/include/asm/vx-insn.h .macro VLEB vr1, disp, index="%r0", base, m3 base 313 arch/s390/include/asm/vx-insn.h .macro VLEH vr1, disp, index="%r0", base, m3 base 316 arch/s390/include/asm/vx-insn.h .macro VLEF vr1, disp, index="%r0", base, m3 base 319 arch/s390/include/asm/vx-insn.h .macro VLEG vr1, disp, index="%r0", base, m3 base 344 arch/s390/include/asm/vx-insn.h .macro VLGV gr, vr, disp, base="%r0", m base 352 arch/s390/include/asm/vx-insn.h .macro VLGVB gr, vr, disp, base="%r0" base 355 arch/s390/include/asm/vx-insn.h .macro VLGVH gr, vr, disp, base="%r0" base 358 arch/s390/include/asm/vx-insn.h .macro VLGVF gr, vr, disp, base="%r0" base 361 arch/s390/include/asm/vx-insn.h .macro VLGVG gr, vr, disp, base="%r0" base 366 arch/s390/include/asm/vx-insn.h .macro VLM vfrom, vto, disp, base, hint=3 base 376 arch/s390/include/asm/vx-insn.h .macro VSTM vfrom, vto, disp, base, hint=3 base 646 arch/s390/kernel/crash_dump.c oldmem_region.base = OLDMEM_BASE; base 1442 arch/s390/kernel/debug.c unsigned long base, sec, usec; base 1449 arch/s390/kernel/debug.c base = (*(unsigned long *) &tod_clock_base[0]) >> 4; base 1450 arch/s390/kernel/debug.c sec = (entry->id.stck >> 12) + base - (TOD_UNIX_EPOCH >> 12); base 215 arch/s390/kernel/module.c static int apply_rela(Elf_Rela *rela, Elf_Addr base, Elf_Sym *symtab, base 224 arch/s390/kernel/module.c loc = base + rela->r_offset; base 288 arch/s390/kernel/module.c gotent = me->core_layout.base + me->arch.got_offset + base 311 arch/s390/kernel/module.c val += (Elf_Addr) me->core_layout.base - loc; base 324 arch/s390/kernel/module.c ip = me->core_layout.base + me->arch.plt_offset + base 330 arch/s390/kernel/module.c ij = me->core_layout.base + base 354 arch/s390/kernel/module.c val = (Elf_Addr) me->core_layout.base + base 376 arch/s390/kernel/module.c ((Elf_Addr) me->core_layout.base + me->arch.got_offset); base 386 arch/s390/kernel/module.c val = (Elf_Addr) me->core_layout.base + me->arch.got_offset + base 419 arch/s390/kernel/module.c Elf_Addr base; base 427 arch/s390/kernel/module.c base = sechdrs[sechdrs[relsec].sh_info].sh_addr; base 433 arch/s390/kernel/module.c rc = apply_rela(rela, base, symtab, strtab, me); base 452 arch/s390/kernel/module.c ij = me->core_layout.base + me->arch.plt_offset + base 36 arch/s390/kernel/os_info.c void os_info_crashkernel_add(unsigned long base, unsigned long size) base 38 arch/s390/kernel/os_info.c os_info.crashkernel_addr = (u64)(unsigned long)base; base 429 arch/s390/kernel/perf_cpum_sf.c static unsigned long min_percent(unsigned int percent, unsigned long base, base 432 arch/s390/kernel/perf_cpum_sf.c return min_t(unsigned long, min, DIV_ROUND_UP(percent * base, 100)); base 435 arch/s390/kernel/perf_cpum_sf.c static unsigned long compute_sfb_extent(unsigned long ratio, unsigned long base) base 445 arch/s390/kernel/perf_cpum_sf.c return min_percent(1, base, 1); base 447 arch/s390/kernel/perf_cpum_sf.c return min_percent(1, base, 1); base 449 arch/s390/kernel/perf_cpum_sf.c return min_percent(2, base, 2); base 451 arch/s390/kernel/perf_cpum_sf.c return min_percent(3, base, 3); base 453 arch/s390/kernel/perf_cpum_sf.c return min_percent(4, base, 4); base 455 arch/s390/kernel/perf_cpum_sf.c return min_percent(5, base, 8); base 1412 arch/s390/kernel/perf_cpum_sf.c unsigned long head, base, offset; base 1447 arch/s390/kernel/perf_cpum_sf.c base = aux->sdbt_index[head / CPUM_SF_SDB_PER_TABLE]; base 1449 arch/s390/kernel/perf_cpum_sf.c cpuhw->lsctl.tear = base + offset * sizeof(unsigned long); base 520 arch/s390/kernel/setup.c res->start = reg->base; base 521 arch/s390/kernel/setup.c res->end = reg->base + reg->size - 1; base 848 arch/s390/kernel/setup.c storage_key_init_range(reg->base, reg->base + reg->size); base 888 arch/s390/kernel/smp.c int base, i, rc; base 893 arch/s390/kernel/smp.c base = smp_get_base_cpu(cpu); base 895 arch/s390/kernel/smp.c if (base + i < nr_cpu_ids) base 896 arch/s390/kernel/smp.c if (cpu_online(base + i)) base 904 arch/s390/kernel/smp.c pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) != base 481 arch/s390/kvm/guestdbg.c u32 base = (opcode[1] & 0xf000) >> 12; base 485 arch/s390/kvm/guestdbg.c *addr = base ? vcpu->run->s.regs.gprs[base] : 0; base 406 arch/s390/mm/vmem.c vmem_add_mem(reg->base, reg->size); base 440 arch/s390/mm/vmem.c seg->start = reg->base; base 111 arch/s390/pci/pci.c u64 base, u64 limit, u64 iota) base 118 arch/s390/pci/pci.c fib.pba = base; base 27 arch/sh/boards/mach-sdk7786/fpga.c void __iomem *base; base 35 arch/sh/boards/mach-sdk7786/fpga.c base = ioremap_nocache(area + FPGA_REGS_OFFSET, FPGA_REGS_SIZE); base 36 arch/sh/boards/mach-sdk7786/fpga.c if (!base) { base 41 arch/sh/boards/mach-sdk7786/fpga.c if (ioread16(base + SRSTR) == SRSTR_MAGIC) base 42 arch/sh/boards/mach-sdk7786/fpga.c return base; /* Found it! */ base 44 arch/sh/boards/mach-sdk7786/fpga.c iounmap(base); base 38 arch/sh/boards/mach-sdk7786/gpio.c .base = -1, /* don't care */ base 27 arch/sh/boards/mach-se/7724/irq.c unsigned int base; base 51 arch/sh/boards/mach-se/7724/irq.c set.base = IRQ0_BASE; base 57 arch/sh/boards/mach-se/7724/irq.c set.base = IRQ1_BASE; base 63 arch/sh/boards/mach-se/7724/irq.c set.base = IRQ2_BASE; base 74 arch/sh/boards/mach-se/7724/irq.c unsigned int bit = irq - set.base; base 82 arch/sh/boards/mach-se/7724/irq.c unsigned int bit = irq - set.base; base 97 arch/sh/boards/mach-se/7724/irq.c unsigned int ext_irq = set.base; base 81 arch/sh/boards/mach-x3proto/gpio.c .base = -1, base 118 arch/sh/boards/mach-x3proto/gpio.c x3proto_gpio_chip.label, x3proto_gpio_chip.base, base 119 arch/sh/boards/mach-x3proto/gpio.c x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio, base 246 arch/sh/boards/mach-x3proto/setup.c baseboard_buttons[i].gpio = x3proto_gpio_chip.base + i; base 29 arch/sh/drivers/dma/dma-sh.c unsigned long base = SH_DMAC_BASE0; base 33 arch/sh/drivers/dma/dma-sh.c base = SH_DMAC_BASE1; base 36 arch/sh/drivers/dma/dma-sh.c return base; base 41 arch/sh/drivers/dma/dma-sh.c unsigned long base = dma_find_base(chan); base 47 arch/sh/drivers/dma/dma-sh.c base += 0x10; base 49 arch/sh/drivers/dma/dma-sh.c return base + (chan * 0x10); base 45 arch/sh/drivers/heartbeat.c new |= ioread32(hd->base) & ~hd->mask; base 46 arch/sh/drivers/heartbeat.c iowrite32(new, hd->base); base 49 arch/sh/drivers/heartbeat.c new |= ioread16(hd->base) & ~hd->mask; base 50 arch/sh/drivers/heartbeat.c iowrite16(new, hd->base); base 53 arch/sh/drivers/heartbeat.c new |= ioread8(hd->base) & ~hd->mask; base 54 arch/sh/drivers/heartbeat.c iowrite8(new, hd->base); base 99 arch/sh/drivers/heartbeat.c hd->base = ioremap_nocache(res->start, resource_size(res)); base 100 arch/sh/drivers/heartbeat.c if (unlikely(!hd->base)) { base 161 arch/sh/drivers/pci/pci-sh4.h unsigned long base; base 70 arch/sh/drivers/pci/pci-sh7751.c .base = SH7751_CS3_BASE_ADDR, base 122 arch/sh/drivers/pci/pci-sh7751.c word = P2SEGADDR(sh7751_pci_map.window0.base); base 142 arch/sh/drivers/pci/pci-sh7751.c switch (sh7751_pci_map.window0.base) { base 117 arch/sh/drivers/superhyway/ops-sh4-202.c static int sh4202_read_vcr(unsigned long base, struct superhyway_vcr_info *vcr) base 134 arch/sh/drivers/superhyway/ops-sh4-202.c vcrh = __raw_readl(base); base 135 arch/sh/drivers/superhyway/ops-sh4-202.c vcrl = __raw_readl(base + sizeof(u32)); base 143 arch/sh/drivers/superhyway/ops-sh4-202.c static int sh4202_write_vcr(unsigned long base, struct superhyway_vcr_info vcr) base 147 arch/sh/drivers/superhyway/ops-sh4-202.c __raw_writel((tmp >> 32) & 0xffffffff, base); base 148 arch/sh/drivers/superhyway/ops-sh4-202.c __raw_writel(tmp & 0xffffffff, base + sizeof(u32)); base 10 arch/sh/include/asm/heartbeat.h void __iomem *base; base 303 arch/sh/kernel/cpu/sh4/sq.c unsigned long base = 0, len = 0; base 305 arch/sh/kernel/cpu/sh4/sq.c sscanf(buf, "%lx %lx", &base, &len); base 306 arch/sh/kernel/cpu/sh4/sq.c if (!base) base 310 arch/sh/kernel/cpu/sh4/sq.c int ret = sq_remap(base, len, "Userspace", PAGE_SHARED); base 314 arch/sh/kernel/cpu/sh4/sq.c sq_unmap(base); base 59 arch/sh/mm/extable_64.c search_extable(const struct exception_table_entry *base, base 69 arch/sh/mm/extable_64.c return bsearch(&value, base, num, base 28 arch/sh/mm/mmap.c unsigned long base = (addr + shm_align_mask) & ~shm_align_mask; base 31 arch/sh/mm/mmap.c return base + off; base 133 arch/sparc/crypto/crc32c_glue.c .base = { base 144 arch/sparc/crypto/md5_glue.c .base = { base 139 arch/sparc/crypto/sha1_glue.c .base = { base 169 arch/sparc/crypto/sha256_glue.c .base = { base 184 arch/sparc/crypto/sha256_glue.c .base = { base 154 arch/sparc/crypto/sha512_glue.c .base = { base 169 arch/sparc/crypto/sha512_glue.c .base = { base 3378 arch/sparc/include/asm/hypervisor.h unsigned long base; /* Real address base of queue */ base 25 arch/sparc/include/asm/iommu_32.h volatile unsigned long base; /* Physical base of iopte page table */ base 42 arch/sparc/include/asm/iommu_64.h u64 base; base 50 arch/sparc/include/asm/iommu_64.h u64 base; base 111 arch/sparc/include/asm/parport.h unsigned long base = op->resource[0].start; base 121 arch/sparc/include/asm/parport.h p = parport_pc_probe_port(base, base + 0x400, base 159 arch/sparc/include/asm/parport.h outb(0x04, base + 0x02); base 171 arch/sparc/include/asm/parport.h p = parport_pc_probe_port(base, base + 0x400, base 46 arch/sparc/include/asm/prom.h void of_iounmap(struct resource *res, void __iomem *base, unsigned long size); base 275 arch/sparc/include/asm/vio.h void *base; base 297 arch/sparc/include/asm/vio.h return dr->base + (dr->entry_size * dr->prod); base 303 arch/sparc/include/asm/vio.h return dr->base + (dr->entry_size * index); base 23 arch/sparc/kernel/btext.c static void draw_byte_32(unsigned char *bits, unsigned int *base, int rb); base 24 arch/sparc/kernel/btext.c static void draw_byte_16(unsigned char *bits, unsigned int *base, int rb); base 25 arch/sparc/kernel/btext.c static void draw_byte_8(unsigned char *bits, unsigned int *base, int rb); base 90 arch/sparc/kernel/btext.c unsigned char *base = dispDeviceBase; base 92 arch/sparc/kernel/btext.c base += (x + dispDeviceRect[0]) * (dispDeviceDepth >> 3); base 93 arch/sparc/kernel/btext.c base += (y + dispDeviceRect[1]) * dispDeviceRowBytes; base 94 arch/sparc/kernel/btext.c return base; base 99 arch/sparc/kernel/btext.c unsigned int *base = (unsigned int *)calc_base(0, 0); base 106 arch/sparc/kernel/btext.c unsigned int *ptr = base; base 109 arch/sparc/kernel/btext.c base += (dispDeviceRowBytes >> 2); base 196 arch/sparc/kernel/btext.c unsigned char *base = calc_base(locX << 3, locY << 4); base 203 arch/sparc/kernel/btext.c draw_byte_32(font, (unsigned int *)base, rb); base 207 arch/sparc/kernel/btext.c draw_byte_16(font, (unsigned int *)base, rb); base 210 arch/sparc/kernel/btext.c draw_byte_8(font, (unsigned int *)base, rb); base 242 arch/sparc/kernel/btext.c static void draw_byte_32(unsigned char *font, unsigned int *base, int rb) base 251 arch/sparc/kernel/btext.c base[0] = (-(bits >> 7) & fg) ^ bg; base 252 arch/sparc/kernel/btext.c base[1] = (-((bits >> 6) & 1) & fg) ^ bg; base 253 arch/sparc/kernel/btext.c base[2] = (-((bits >> 5) & 1) & fg) ^ bg; base 254 arch/sparc/kernel/btext.c base[3] = (-((bits >> 4) & 1) & fg) ^ bg; base 255 arch/sparc/kernel/btext.c base[4] = (-((bits >> 3) & 1) & fg) ^ bg; base 256 arch/sparc/kernel/btext.c base[5] = (-((bits >> 2) & 1) & fg) ^ bg; base 257 arch/sparc/kernel/btext.c base[6] = (-((bits >> 1) & 1) & fg) ^ bg; base 258 arch/sparc/kernel/btext.c base[7] = (-(bits & 1) & fg) ^ bg; base 259 arch/sparc/kernel/btext.c base = (unsigned int *) ((char *)base + rb); base 263 arch/sparc/kernel/btext.c static void draw_byte_16(unsigned char *font, unsigned int *base, int rb) base 273 arch/sparc/kernel/btext.c base[0] = (eb[bits >> 6] & fg) ^ bg; base 274 arch/sparc/kernel/btext.c base[1] = (eb[(bits >> 4) & 3] & fg) ^ bg; base 275 arch/sparc/kernel/btext.c base[2] = (eb[(bits >> 2) & 3] & fg) ^ bg; base 276 arch/sparc/kernel/btext.c base[3] = (eb[bits & 3] & fg) ^ bg; base 277 arch/sparc/kernel/btext.c base = (unsigned int *) ((char *)base + rb); base 281 arch/sparc/kernel/btext.c static void draw_byte_8(unsigned char *font, unsigned int *base, int rb) base 291 arch/sparc/kernel/btext.c base[0] = (eb[bits >> 4] & fg) ^ bg; base 292 arch/sparc/kernel/btext.c base[1] = (eb[bits & 0xf] & fg) ^ bg; base 293 arch/sparc/kernel/btext.c base = (unsigned int *) ((char *)base + rb); base 84 arch/sparc/kernel/chmc.c unsigned long base; base 340 arch/sparc/kernel/chmc.c static u64 jbusmc_dimm_group_size(u64 base, base 344 arch/sparc/kernel/chmc.c u64 max = base + (8UL * 1024 * 1024 * 1024); base 345 arch/sparc/kernel/chmc.c u64 max_seen = base; base 356 arch/sparc/kernel/chmc.c if (base < this_base || base >= this_end) base 364 arch/sparc/kernel/chmc.c return max_seen - base; base 643 arch/sparc/kernel/chmc.c bp->base = (bp->um); base 644 arch/sparc/kernel/chmc.c bp->base &= ~(bp->uk); base 645 arch/sparc/kernel/chmc.c bp->base <<= PA_UPPER_BITS_SHIFT; base 782 arch/sparc/kernel/ds.c char *base, *p; base 799 arch/sparc/kernel/ds.c base = p = &pkt.header.msg.name_and_value[0]; base 807 arch/sparc/kernel/ds.c (p - base)); base 270 arch/sparc/kernel/iommu.c iopte_t *base; base 286 arch/sparc/kernel/iommu.c base = alloc_npages(dev, iommu, npages); base 293 arch/sparc/kernel/iommu.c if (unlikely(!base)) base 297 arch/sparc/kernel/iommu.c ((base - iommu->page_table) << IO_PAGE_SHIFT)); base 307 arch/sparc/kernel/iommu.c for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE) base 308 arch/sparc/kernel/iommu.c iopte_val(*base) = iopte_protection | base_paddr; base 392 arch/sparc/kernel/iommu.c iopte_t *base; base 406 arch/sparc/kernel/iommu.c base = iommu->page_table + base 415 arch/sparc/kernel/iommu.c ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; base 424 arch/sparc/kernel/iommu.c iopte_make_dummy(iommu, base + i); base 480 arch/sparc/kernel/iommu.c iopte_t *base; base 502 arch/sparc/kernel/iommu.c base = iommu->page_table + entry; base 512 arch/sparc/kernel/iommu.c iopte_val(*base) = prot | paddr; base 513 arch/sparc/kernel/iommu.c base++; base 560 arch/sparc/kernel/iommu.c iopte_t *base; base 568 arch/sparc/kernel/iommu.c base = iommu->page_table + entry; base 571 arch/sparc/kernel/iommu.c iopte_make_dummy(iommu, base + j); base 595 arch/sparc/kernel/iommu.c iopte_t *base; base 600 arch/sparc/kernel/iommu.c base = iommu->page_table + base 603 arch/sparc/kernel/iommu.c ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; base 631 arch/sparc/kernel/iommu.c iopte_t *base; base 640 arch/sparc/kernel/iommu.c base = iommu->page_table + entry; base 648 arch/sparc/kernel/iommu.c iopte_make_dummy(iommu, base + i); base 168 arch/sparc/kernel/ioport.c void of_iounmap(struct resource *res, void __iomem *base, unsigned long size) base 170 arch/sparc/kernel/ioport.c iounmap(base); base 13 arch/sparc/kernel/kstack.h unsigned long base = (unsigned long) tp; base 19 arch/sparc/kernel/kstack.h if (sp >= (base + sizeof(struct thread_info)) && base 20 arch/sparc/kernel/kstack.h sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) base 24 arch/sparc/kernel/kstack.h base = (unsigned long) hardirq_stack[tp->cpu]; base 25 arch/sparc/kernel/kstack.h if (sp >= base && base 26 arch/sparc/kernel/kstack.h sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) base 28 arch/sparc/kernel/kstack.h base = (unsigned long) softirq_stack[tp->cpu]; base 29 arch/sparc/kernel/kstack.h if (sp >= base && base 30 arch/sparc/kernel/kstack.h sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) base 39 arch/sparc/kernel/kstack.h unsigned long base = (unsigned long) tp; base 42 arch/sparc/kernel/kstack.h if (addr >= base && base 43 arch/sparc/kernel/kstack.h addr <= (base + THREAD_SIZE - sizeof(*regs))) base 47 arch/sparc/kernel/kstack.h base = (unsigned long) hardirq_stack[tp->cpu]; base 48 arch/sparc/kernel/kstack.h if (addr >= base && base 49 arch/sparc/kernel/kstack.h addr <= (base + THREAD_SIZE - sizeof(*regs))) base 51 arch/sparc/kernel/kstack.h base = (unsigned long) softirq_stack[tp->cpu]; base 52 arch/sparc/kernel/kstack.h if (addr >= base && base 53 arch/sparc/kernel/kstack.h addr <= (base + THREAD_SIZE - sizeof(*regs))) base 976 arch/sparc/kernel/ldc.c struct ldc_packet **base, unsigned long *ra) base 993 arch/sparc/kernel/ldc.c *base = q; base 1025 arch/sparc/kernel/ldc.c struct ldc_mtable_entry *base; base 1029 arch/sparc/kernel/ldc.c base = iommu->page_table + entry; base 1031 arch/sparc/kernel/ldc.c if (base->cookie) base 1033 arch/sparc/kernel/ldc.c base->cookie); base 1034 arch/sparc/kernel/ldc.c base->mte = 0; base 2060 arch/sparc/kernel/ldc.c static int pages_in_region(unsigned long base, long len) base 2065 arch/sparc/kernel/ldc.c unsigned long new = (base + PAGE_SIZE) & PAGE_MASK; base 2067 arch/sparc/kernel/ldc.c len -= (new - base); base 2068 arch/sparc/kernel/ldc.c base = new; base 2122 arch/sparc/kernel/ldc.c unsigned long base = page_to_pfn(sg_page(sg)) << PAGE_SHIFT; base 2128 arch/sparc/kernel/ldc.c return pages_in_region(base + sg->offset, len); base 2153 arch/sparc/kernel/ldc.c struct ldc_mtable_entry *base; base 2172 arch/sparc/kernel/ldc.c base = alloc_npages(iommu, npages); base 2174 arch/sparc/kernel/ldc.c if (!base) base 2181 arch/sparc/kernel/ldc.c state.pte_idx = (base - iommu->page_table); base 2199 arch/sparc/kernel/ldc.c struct ldc_mtable_entry *base; base 2214 arch/sparc/kernel/ldc.c base = alloc_npages(iommu, npages); base 2216 arch/sparc/kernel/ldc.c if (!base) base 2223 arch/sparc/kernel/ldc.c state.pte_idx = (base - iommu->page_table); base 150 arch/sparc/kernel/mdesc.c void *base) base 156 arch/sparc/kernel/mdesc.c hp->self_base = base; base 205 arch/sparc/kernel/mdesc.c void *base; base 210 arch/sparc/kernel/mdesc.c base = kmalloc(handle_size + 15, GFP_KERNEL | __GFP_RETRY_MAYFAIL); base 211 arch/sparc/kernel/mdesc.c if (!base) base 214 arch/sparc/kernel/mdesc.c addr = (unsigned long)base; base 218 arch/sparc/kernel/mdesc.c mdesc_handle_init(hp, handle_size, base); base 705 arch/sparc/kernel/mdesc.c struct mdesc_elem *ep, *base = node_block(&hp->mdesc); base 712 arch/sparc/kernel/mdesc.c ep = base + from; base 722 arch/sparc/kernel/mdesc.c return ep - base; base 731 arch/sparc/kernel/mdesc.c struct mdesc_elem *ep, *base = node_block(&hp->mdesc); base 733 arch/sparc/kernel/mdesc.c ep = base + arc; base 741 arch/sparc/kernel/mdesc.c struct mdesc_elem *ep, *base = node_block(&hp->mdesc); base 748 arch/sparc/kernel/mdesc.c ep = base + node; base 34 arch/sparc/kernel/of_device_64.c void of_iounmap(struct resource *res, void __iomem *base, unsigned long size) base 37 arch/sparc/kernel/of_device_64.c release_mem_region((unsigned long) base, size); base 39 arch/sparc/kernel/of_device_64.c release_region((unsigned long) base, size); base 96 arch/sparc/kernel/of_device_common.c int of_out_of_range(const u32 *addr, const u32 *base, base 100 arch/sparc/kernel/of_device_common.c u64 b = of_read_addr(base, na); base 15 arch/sparc/kernel/of_device_common.h int of_out_of_range(const u32 *addr, const u32 *base, base 161 arch/sparc/kernel/pci_fire.c struct pci_msiq_entry *base, *ep; base 163 arch/sparc/kernel/pci_fire.c base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192)); base 164 arch/sparc/kernel/pci_fire.c ep = &base[*head]; base 291 arch/sparc/kernel/pci_psycho.c unsigned long base = pbm->controller_regs; base 332 arch/sparc/kernel/pci_psycho.c PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL); base 337 arch/sparc/kernel/pci_psycho.c tmp = upa_readq(base + PSYCHO_PCIA_CTRL); base 342 arch/sparc/kernel/pci_psycho.c upa_writeq(tmp, base + PSYCHO_PCIA_CTRL); base 344 arch/sparc/kernel/pci_psycho.c tmp = upa_readq(base + PSYCHO_PCIB_CTRL); base 349 arch/sparc/kernel/pci_psycho.c upa_writeq(tmp, base + PSYCHO_PCIB_CTRL); base 426 arch/sparc/kernel/pci_psycho.c unsigned long base = pbm->controller_regs; base 430 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A; base 431 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A; base 432 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A; base 433 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A; base 434 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A; base 435 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A; base 437 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B; base 438 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B; base 439 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B; base 440 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B; base 441 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B; base 442 arch/sparc/kernel/pci_psycho.c pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B; base 317 arch/sparc/kernel/pci_sabre.c unsigned long base = pbm->controller_regs; base 344 arch/sparc/kernel/pci_sabre.c base + SABRE_UE_AFSR); base 353 arch/sparc/kernel/pci_sabre.c base + SABRE_CE_AFSR); base 366 arch/sparc/kernel/pci_sabre.c tmp = upa_readq(base + SABRE_PCICTRL); base 368 arch/sparc/kernel/pci_sabre.c upa_writeq(tmp, base + SABRE_PCICTRL); base 249 arch/sparc/kernel/pci_schizo.c unsigned long base; base 287 arch/sparc/kernel/pci_schizo.c base = pbm->pbm_regs; base 291 arch/sparc/kernel/pci_schizo.c upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL)); base 293 arch/sparc/kernel/pci_schizo.c upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL)); base 296 arch/sparc/kernel/pci_schizo.c upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL)); base 297 arch/sparc/kernel/pci_schizo.c upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL)); base 639 arch/sparc/kernel/pci_schizo.c unsigned long afsr_reg, afar_reg, base; base 643 arch/sparc/kernel/pci_schizo.c base = pbm->pbm_regs; base 645 arch/sparc/kernel/pci_schizo.c afsr_reg = base + SCHIZO_PCI_AFSR; base 646 arch/sparc/kernel/pci_schizo.c afar_reg = base + SCHIZO_PCI_AFAR; base 1092 arch/sparc/kernel/pci_schizo.c unsigned long base = pbm->pbm_regs; base 1101 arch/sparc/kernel/pci_schizo.c pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL; base 1102 arch/sparc/kernel/pci_schizo.c pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH; base 1103 arch/sparc/kernel/pci_schizo.c pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC; base 1104 arch/sparc/kernel/pci_schizo.c pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH; base 1105 arch/sparc/kernel/pci_schizo.c pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH; base 769 arch/sparc/kernel/pci_sun4v.c iotsb->dvma_base = atu->base; base 837 arch/sparc/kernel/pci_sun4v.c atu->base = atu->ranges[3].base; base 853 arch/sparc/kernel/pci_sun4v.c atu->tbl.table_map_base = atu->base; base 1074 arch/sparc/kernel/pci_sun4v.c unsigned long err, base = __pa(pages + (i * q_size)); base 1079 arch/sparc/kernel/pci_sun4v.c base, pbm->msiq_ent_count); base 1094 arch/sparc/kernel/pci_sun4v.c if (ret1 != base || ret2 != pbm->msiq_ent_count) { base 1097 arch/sparc/kernel/pci_sun4v.c base, pbm->msiq_ent_count, base 132 arch/sparc/kernel/psycho_common.c unsigned long base = pbm->controller_regs; base 135 arch/sparc/kernel/psycho_common.c tag[i] = upa_readq(base + PSYCHO_IOMMU_TAG+off); base 136 arch/sparc/kernel/psycho_common.c data[i] = upa_readq(base + PSYCHO_IOMMU_DATA+off); base 139 arch/sparc/kernel/psycho_common.c upa_writeq(0, base + PSYCHO_IOMMU_TAG + off); base 140 arch/sparc/kernel/psycho_common.c upa_writeq(0, base + PSYCHO_IOMMU_DATA + off); base 84 arch/sparc/kernel/sys_sparc_64.c unsigned long base = (addr+SHMLBA-1)&~(SHMLBA-1); base 87 arch/sparc/kernel/sys_sparc_64.c return base + off; base 17 arch/sparc/mm/extable.c search_extable(const struct exception_table_entry *base, base 42 arch/sparc/mm/extable.c if (base[i].fixup == 0) { base 49 arch/sparc/mm/extable.c if (base[i].fixup == -1) base 52 arch/sparc/mm/extable.c if (base[i].insn == value) base 53 arch/sparc/mm/extable.c return &base[i]; base 58 arch/sparc/mm/extable.c if (base[i].fixup) base 61 arch/sparc/mm/extable.c if (base[i].insn <= value && base[i + 1].insn > value) base 62 arch/sparc/mm/extable.c return &base[i]; base 136 arch/sparc/mm/init_64.c unsigned long base, size; base 138 arch/sparc/mm/init_64.c base = regs[i].phys_addr; base 142 arch/sparc/mm/init_64.c if (base & ~PAGE_MASK) { base 143 arch/sparc/mm/init_64.c unsigned long new_base = PAGE_ALIGN(base); base 145 arch/sparc/mm/init_64.c size -= new_base - base; base 148 arch/sparc/mm/init_64.c base = new_base; base 161 arch/sparc/mm/init_64.c regs[i].phys_addr = base; base 951 arch/sparc/mm/init_64.c u64 base; base 966 arch/sparc/mm/init_64.c if (addr >= m->base && base 967 arch/sparc/mm/init_64.c addr < (m->base + m->size)) { base 1234 arch/sparc/mm/init_64.c start = reg->base; base 1321 arch/sparc/mm/init_64.c m->base = *val; base 1336 arch/sparc/mm/init_64.c count - 1, m->base, m->size, m->offset); base 63 arch/sparc/mm/iommu.c unsigned long base; base 108 arch/sparc/mm/iommu.c base = __pa((unsigned long)iommu->page_table) >> 4; base 109 arch/sparc/mm/iommu.c sbus_writel(base, &iommu->regs->base); base 122 arch/sparc/mm/tsb.c unsigned long nentries, base, flags; base 127 arch/sparc/mm/tsb.c base = (unsigned long) mm->context.tsb_block[MM_TSB_BASE].tsb; base 130 arch/sparc/mm/tsb.c base = __pa(base); base 132 arch/sparc/mm/tsb.c __flush_tsb_one(tb, PAGE_SHIFT, base, nentries); base 135 arch/sparc/mm/tsb.c __flush_huge_tsb_one(tb, PAGE_SHIFT, base, nentries, base 141 arch/sparc/mm/tsb.c base = (unsigned long) mm->context.tsb_block[MM_TSB_HUGE].tsb; base 144 arch/sparc/mm/tsb.c base = __pa(base); base 145 arch/sparc/mm/tsb.c __flush_huge_tsb_one(tb, REAL_HPAGE_SHIFT, base, nentries, base 155 arch/sparc/mm/tsb.c unsigned long nentries, base, flags; base 160 arch/sparc/mm/tsb.c base = (unsigned long) mm->context.tsb_block[MM_TSB_BASE].tsb; base 163 arch/sparc/mm/tsb.c base = __pa(base); base 165 arch/sparc/mm/tsb.c __flush_tsb_one_entry(base, vaddr, PAGE_SHIFT, base 169 arch/sparc/mm/tsb.c __flush_huge_tsb_one_entry(base, vaddr, PAGE_SHIFT, base 175 arch/sparc/mm/tsb.c base = (unsigned long) mm->context.tsb_block[MM_TSB_HUGE].tsb; base 178 arch/sparc/mm/tsb.c base = __pa(base); base 179 arch/sparc/mm/tsb.c __flush_huge_tsb_one_entry(base, vaddr, REAL_HPAGE_SHIFT, base 196 arch/sparc/mm/tsb.c unsigned long tsb_reg, base, tsb_paddr; base 204 arch/sparc/mm/tsb.c base = TSBMAP_8K_BASE; base 208 arch/sparc/mm/tsb.c base = TSBMAP_4M_BASE; base 226 arch/sparc/mm/tsb.c base += (tsb_paddr & 8192); base 281 arch/sparc/mm/tsb.c tsb_reg |= base; base 286 arch/sparc/mm/tsb.c mm->context.tsb_block[tsb_idx].tsb_map_vaddr = base; base 741 arch/um/drivers/line.c char *add_xterm_umid(char *base) base 748 arch/um/drivers/line.c return base; base 750 arch/um/drivers/line.c len = strlen(base) + strlen(" ()") + strlen(umid) + 1; base 754 arch/um/drivers/line.c return base; base 757 arch/um/drivers/line.c snprintf(title, len, "%s (%s)", base, umid); base 78 arch/um/drivers/line.h extern char *add_xterm_umid(char *base); base 93 arch/unicore32/kernel/gpio.c .base = 0, base 312 arch/unicore32/mm/mmu.c end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; base 398 arch/unicore32/mm/mmu.c phys_addr_t start = reg->base; base 330 arch/x86/boot/boot.h unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base); base 35 arch/x86/boot/printf.c #define __do_div(n, base) ({ \ base 37 arch/x86/boot/printf.c __res = ((unsigned long) n) % (unsigned) base; \ base 38 arch/x86/boot/printf.c n = ((unsigned long) n) / (unsigned) base; \ base 41 arch/x86/boot/printf.c static char *number(char *str, long num, int base, int size, int precision, base 56 arch/x86/boot/printf.c if (base < 2 || base > 16) base 74 arch/x86/boot/printf.c if (base == 16) base 76 arch/x86/boot/printf.c else if (base == 8) base 84 arch/x86/boot/printf.c tmp[i++] = (digits[__do_div(num, base)] | locase); base 94 arch/x86/boot/printf.c if (base == 8) base 96 arch/x86/boot/printf.c else if (base == 16) { base 117 arch/x86/boot/printf.c int i, base; base 193 arch/x86/boot/printf.c base = 10; base 244 arch/x86/boot/printf.c base = 8; base 250 arch/x86/boot/printf.c base = 16; base 277 arch/x86/boot/printf.c str = number(str, num, base, field_width, precision, flags); base 121 arch/x86/boot/string.c unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base) base 125 arch/x86/boot/string.c if (!base) base 126 arch/x86/boot/string.c base = simple_guess_base(cp); base 128 arch/x86/boot/string.c if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x') base 135 arch/x86/boot/string.c if (value >= base) base 137 arch/x86/boot/string.c result = result * base + value; base 146 arch/x86/boot/string.c long simple_strtol(const char *cp, char **endp, unsigned int base) base 149 arch/x86/boot/string.c return -simple_strtoull(cp + 1, endp, base); base 151 arch/x86/boot/string.c return simple_strtoull(cp, endp, base); base 233 arch/x86/boot/string.c static const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) base 235 arch/x86/boot/string.c if (*base == 0) { base 238 arch/x86/boot/string.c *base = 16; base 240 arch/x86/boot/string.c *base = 8; base 242 arch/x86/boot/string.c *base = 10; base 244 arch/x86/boot/string.c if (*base == 16 && s[0] == '0' && _tolower(s[1]) == 'x') base 258 arch/x86/boot/string.c unsigned int base, base 278 arch/x86/boot/string.c if (val >= base) base 285 arch/x86/boot/string.c if (res > __div_u64(ULLONG_MAX - val, base)) base 288 arch/x86/boot/string.c res = res * base + val; base 296 arch/x86/boot/string.c static int _kstrtoull(const char *s, unsigned int base, unsigned long long *res) base 301 arch/x86/boot/string.c s = _parse_integer_fixup_radix(s, &base); base 302 arch/x86/boot/string.c rv = _parse_integer(s, base, &_res); base 332 arch/x86/boot/string.c int kstrtoull(const char *s, unsigned int base, unsigned long long *res) base 336 arch/x86/boot/string.c return _kstrtoull(s, base, res); base 30 arch/x86/boot/string.h unsigned int base); base 32 arch/x86/boot/string.h int kstrtoull(const char *s, unsigned int base, unsigned long long *res); base 253 arch/x86/crypto/aegis128-aesni-glue.c .base = { base 926 arch/x86/crypto/aesni-intel_glue.c .base = { base 941 arch/x86/crypto/aesni-intel_glue.c .base = { base 958 arch/x86/crypto/aesni-intel_glue.c .base = { base 975 arch/x86/crypto/aesni-intel_glue.c .base = { base 1045 arch/x86/crypto/aesni-intel_glue.c .base = { base 1062 arch/x86/crypto/aesni-intel_glue.c .base = { base 68 arch/x86/crypto/blowfish_glue.c return blowfish_setkey(&tfm->base, key, keylen); base 363 arch/x86/crypto/blowfish_glue.c .base.cra_name = "ecb(blowfish)", base 364 arch/x86/crypto/blowfish_glue.c .base.cra_driver_name = "ecb-blowfish-asm", base 365 arch/x86/crypto/blowfish_glue.c .base.cra_priority = 300, base 366 arch/x86/crypto/blowfish_glue.c .base.cra_blocksize = BF_BLOCK_SIZE, base 367 arch/x86/crypto/blowfish_glue.c .base.cra_ctxsize = sizeof(struct bf_ctx), base 368 arch/x86/crypto/blowfish_glue.c .base.cra_module = THIS_MODULE, base 375 arch/x86/crypto/blowfish_glue.c .base.cra_name = "cbc(blowfish)", base 376 arch/x86/crypto/blowfish_glue.c .base.cra_driver_name = "cbc-blowfish-asm", base 377 arch/x86/crypto/blowfish_glue.c .base.cra_priority = 300, base 378 arch/x86/crypto/blowfish_glue.c .base.cra_blocksize = BF_BLOCK_SIZE, base 379 arch/x86/crypto/blowfish_glue.c .base.cra_ctxsize = sizeof(struct bf_ctx), base 380 arch/x86/crypto/blowfish_glue.c .base.cra_module = THIS_MODULE, base 388 arch/x86/crypto/blowfish_glue.c .base.cra_name = "ctr(blowfish)", base 389 arch/x86/crypto/blowfish_glue.c .base.cra_driver_name = "ctr-blowfish-asm", base 390 arch/x86/crypto/blowfish_glue.c .base.cra_priority = 300, base 391 arch/x86/crypto/blowfish_glue.c .base.cra_blocksize = 1, base 392 arch/x86/crypto/blowfish_glue.c .base.cra_ctxsize = sizeof(struct bf_ctx), base 393 arch/x86/crypto/blowfish_glue.c .base.cra_module = THIS_MODULE, base 149 arch/x86/crypto/camellia_aesni_avx2_glue.c &tfm->base.crt_flags); base 200 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_name = "__ecb(camellia)", base 201 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_driver_name = "__ecb-camellia-aesni-avx2", base 202 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_priority = 500, base 203 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 204 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_blocksize = CAMELLIA_BLOCK_SIZE, base 205 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_ctxsize = sizeof(struct camellia_ctx), base 206 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_module = THIS_MODULE, base 213 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_name = "__cbc(camellia)", base 214 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_driver_name = "__cbc-camellia-aesni-avx2", base 215 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_priority = 500, base 216 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 217 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_blocksize = CAMELLIA_BLOCK_SIZE, base 218 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_ctxsize = sizeof(struct camellia_ctx), base 219 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_module = THIS_MODULE, base 227 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_name = "__ctr(camellia)", base 228 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_driver_name = "__ctr-camellia-aesni-avx2", base 229 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_priority = 500, base 230 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 231 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_blocksize = 1, base 232 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_ctxsize = sizeof(struct camellia_ctx), base 233 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_module = THIS_MODULE, base 242 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_name = "__xts(camellia)", base 243 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_driver_name = "__xts-camellia-aesni-avx2", base 244 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_priority = 500, base 245 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 246 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_blocksize = CAMELLIA_BLOCK_SIZE, base 247 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_ctxsize = sizeof(struct camellia_xts_ctx), base 248 arch/x86/crypto/camellia_aesni_avx2_glue.c .base.cra_module = THIS_MODULE, base 153 arch/x86/crypto/camellia_aesni_avx_glue.c &tfm->base.crt_flags); base 186 arch/x86/crypto/camellia_aesni_avx_glue.c u32 *flags = &tfm->base.crt_flags; base 226 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_name = "__ecb(camellia)", base 227 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_driver_name = "__ecb-camellia-aesni", base 228 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_priority = 400, base 229 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 230 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_blocksize = CAMELLIA_BLOCK_SIZE, base 231 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_ctxsize = sizeof(struct camellia_ctx), base 232 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_module = THIS_MODULE, base 239 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_name = "__cbc(camellia)", base 240 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_driver_name = "__cbc-camellia-aesni", base 241 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_priority = 400, base 242 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 243 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_blocksize = CAMELLIA_BLOCK_SIZE, base 244 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_ctxsize = sizeof(struct camellia_ctx), base 245 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_module = THIS_MODULE, base 253 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_name = "__ctr(camellia)", base 254 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_driver_name = "__ctr-camellia-aesni", base 255 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_priority = 400, base 256 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 257 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_blocksize = 1, base 258 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_ctxsize = sizeof(struct camellia_ctx), base 259 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_module = THIS_MODULE, base 268 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_name = "__xts(camellia)", base 269 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_driver_name = "__xts-camellia-aesni", base 270 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_priority = 400, base 271 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 272 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_blocksize = CAMELLIA_BLOCK_SIZE, base 273 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_ctxsize = sizeof(struct camellia_xts_ctx), base 274 arch/x86/crypto/camellia_aesni_avx_glue.c .base.cra_module = THIS_MODULE, base 1267 arch/x86/crypto/camellia_glue.c return camellia_setkey(&tfm->base, key, key_len); base 1412 arch/x86/crypto/camellia_glue.c .base.cra_name = "ecb(camellia)", base 1413 arch/x86/crypto/camellia_glue.c .base.cra_driver_name = "ecb-camellia-asm", base 1414 arch/x86/crypto/camellia_glue.c .base.cra_priority = 300, base 1415 arch/x86/crypto/camellia_glue.c .base.cra_blocksize = CAMELLIA_BLOCK_SIZE, base 1416 arch/x86/crypto/camellia_glue.c .base.cra_ctxsize = sizeof(struct camellia_ctx), base 1417 arch/x86/crypto/camellia_glue.c .base.cra_module = THIS_MODULE, base 1424 arch/x86/crypto/camellia_glue.c .base.cra_name = "cbc(camellia)", base 1425 arch/x86/crypto/camellia_glue.c .base.cra_driver_name = "cbc-camellia-asm", base 1426 arch/x86/crypto/camellia_glue.c .base.cra_priority = 300, base 1427 arch/x86/crypto/camellia_glue.c .base.cra_blocksize = CAMELLIA_BLOCK_SIZE, base 1428 arch/x86/crypto/camellia_glue.c .base.cra_ctxsize = sizeof(struct camellia_ctx), base 1429 arch/x86/crypto/camellia_glue.c .base.cra_module = THIS_MODULE, base 1437 arch/x86/crypto/camellia_glue.c .base.cra_name = "ctr(camellia)", base 1438 arch/x86/crypto/camellia_glue.c .base.cra_driver_name = "ctr-camellia-asm", base 1439 arch/x86/crypto/camellia_glue.c .base.cra_priority = 300, base 1440 arch/x86/crypto/camellia_glue.c .base.cra_blocksize = 1, base 1441 arch/x86/crypto/camellia_glue.c .base.cra_ctxsize = sizeof(struct camellia_ctx), base 1442 arch/x86/crypto/camellia_glue.c .base.cra_module = THIS_MODULE, base 32 arch/x86/crypto/cast5_avx_glue.c return cast5_setkey(&tfm->base, key, keylen); base 305 arch/x86/crypto/cast5_avx_glue.c .base.cra_name = "__ecb(cast5)", base 306 arch/x86/crypto/cast5_avx_glue.c .base.cra_driver_name = "__ecb-cast5-avx", base 307 arch/x86/crypto/cast5_avx_glue.c .base.cra_priority = 200, base 308 arch/x86/crypto/cast5_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 309 arch/x86/crypto/cast5_avx_glue.c .base.cra_blocksize = CAST5_BLOCK_SIZE, base 310 arch/x86/crypto/cast5_avx_glue.c .base.cra_ctxsize = sizeof(struct cast5_ctx), base 311 arch/x86/crypto/cast5_avx_glue.c .base.cra_module = THIS_MODULE, base 318 arch/x86/crypto/cast5_avx_glue.c .base.cra_name = "__cbc(cast5)", base 319 arch/x86/crypto/cast5_avx_glue.c .base.cra_driver_name = "__cbc-cast5-avx", base 320 arch/x86/crypto/cast5_avx_glue.c .base.cra_priority = 200, base 321 arch/x86/crypto/cast5_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 322 arch/x86/crypto/cast5_avx_glue.c .base.cra_blocksize = CAST5_BLOCK_SIZE, base 323 arch/x86/crypto/cast5_avx_glue.c .base.cra_ctxsize = sizeof(struct cast5_ctx), base 324 arch/x86/crypto/cast5_avx_glue.c .base.cra_module = THIS_MODULE, base 332 arch/x86/crypto/cast5_avx_glue.c .base.cra_name = "__ctr(cast5)", base 333 arch/x86/crypto/cast5_avx_glue.c .base.cra_driver_name = "__ctr-cast5-avx", base 334 arch/x86/crypto/cast5_avx_glue.c .base.cra_priority = 200, base 335 arch/x86/crypto/cast5_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 336 arch/x86/crypto/cast5_avx_glue.c .base.cra_blocksize = 1, base 337 arch/x86/crypto/cast5_avx_glue.c .base.cra_ctxsize = sizeof(struct cast5_ctx), base 338 arch/x86/crypto/cast5_avx_glue.c .base.cra_module = THIS_MODULE, base 41 arch/x86/crypto/cast6_avx_glue.c return cast6_setkey(&tfm->base, key, keylen); base 180 arch/x86/crypto/cast6_avx_glue.c u32 *flags = &tfm->base.crt_flags; base 219 arch/x86/crypto/cast6_avx_glue.c .base.cra_name = "__ecb(cast6)", base 220 arch/x86/crypto/cast6_avx_glue.c .base.cra_driver_name = "__ecb-cast6-avx", base 221 arch/x86/crypto/cast6_avx_glue.c .base.cra_priority = 200, base 222 arch/x86/crypto/cast6_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 223 arch/x86/crypto/cast6_avx_glue.c .base.cra_blocksize = CAST6_BLOCK_SIZE, base 224 arch/x86/crypto/cast6_avx_glue.c .base.cra_ctxsize = sizeof(struct cast6_ctx), base 225 arch/x86/crypto/cast6_avx_glue.c .base.cra_module = THIS_MODULE, base 232 arch/x86/crypto/cast6_avx_glue.c .base.cra_name = "__cbc(cast6)", base 233 arch/x86/crypto/cast6_avx_glue.c .base.cra_driver_name = "__cbc-cast6-avx", base 234 arch/x86/crypto/cast6_avx_glue.c .base.cra_priority = 200, base 235 arch/x86/crypto/cast6_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 236 arch/x86/crypto/cast6_avx_glue.c .base.cra_blocksize = CAST6_BLOCK_SIZE, base 237 arch/x86/crypto/cast6_avx_glue.c .base.cra_ctxsize = sizeof(struct cast6_ctx), base 238 arch/x86/crypto/cast6_avx_glue.c .base.cra_module = THIS_MODULE, base 246 arch/x86/crypto/cast6_avx_glue.c .base.cra_name = "__ctr(cast6)", base 247 arch/x86/crypto/cast6_avx_glue.c .base.cra_driver_name = "__ctr-cast6-avx", base 248 arch/x86/crypto/cast6_avx_glue.c .base.cra_priority = 200, base 249 arch/x86/crypto/cast6_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 250 arch/x86/crypto/cast6_avx_glue.c .base.cra_blocksize = 1, base 251 arch/x86/crypto/cast6_avx_glue.c .base.cra_ctxsize = sizeof(struct cast6_ctx), base 252 arch/x86/crypto/cast6_avx_glue.c .base.cra_module = THIS_MODULE, base 261 arch/x86/crypto/cast6_avx_glue.c .base.cra_name = "__xts(cast6)", base 262 arch/x86/crypto/cast6_avx_glue.c .base.cra_driver_name = "__xts-cast6-avx", base 263 arch/x86/crypto/cast6_avx_glue.c .base.cra_priority = 200, base 264 arch/x86/crypto/cast6_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 265 arch/x86/crypto/cast6_avx_glue.c .base.cra_blocksize = CAST6_BLOCK_SIZE, base 266 arch/x86/crypto/cast6_avx_glue.c .base.cra_ctxsize = sizeof(struct cast6_xts_ctx), base 267 arch/x86/crypto/cast6_avx_glue.c .base.cra_module = THIS_MODULE, base 219 arch/x86/crypto/chacha_glue.c .base.cra_name = "chacha20", base 220 arch/x86/crypto/chacha_glue.c .base.cra_driver_name = "chacha20-simd", base 221 arch/x86/crypto/chacha_glue.c .base.cra_priority = 300, base 222 arch/x86/crypto/chacha_glue.c .base.cra_blocksize = 1, base 223 arch/x86/crypto/chacha_glue.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 224 arch/x86/crypto/chacha_glue.c .base.cra_module = THIS_MODULE, base 234 arch/x86/crypto/chacha_glue.c .base.cra_name = "xchacha20", base 235 arch/x86/crypto/chacha_glue.c .base.cra_driver_name = "xchacha20-simd", base 236 arch/x86/crypto/chacha_glue.c .base.cra_priority = 300, base 237 arch/x86/crypto/chacha_glue.c .base.cra_blocksize = 1, base 238 arch/x86/crypto/chacha_glue.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 239 arch/x86/crypto/chacha_glue.c .base.cra_module = THIS_MODULE, base 249 arch/x86/crypto/chacha_glue.c .base.cra_name = "xchacha12", base 250 arch/x86/crypto/chacha_glue.c .base.cra_driver_name = "xchacha12-simd", base 251 arch/x86/crypto/chacha_glue.c .base.cra_priority = 300, base 252 arch/x86/crypto/chacha_glue.c .base.cra_blocksize = 1, base 253 arch/x86/crypto/chacha_glue.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 254 arch/x86/crypto/chacha_glue.c .base.cra_module = THIS_MODULE, base 162 arch/x86/crypto/crc32-pclmul_glue.c .base = { base 213 arch/x86/crypto/crc32c-intel_glue.c .base = { base 107 arch/x86/crypto/crct10dif-pclmul_glue.c .base = { base 382 arch/x86/crypto/des3_ede_glue.c return des3_ede_x86_setkey(&tfm->base, key, keylen); base 407 arch/x86/crypto/des3_ede_glue.c .base.cra_name = "ecb(des3_ede)", base 408 arch/x86/crypto/des3_ede_glue.c .base.cra_driver_name = "ecb-des3_ede-asm", base 409 arch/x86/crypto/des3_ede_glue.c .base.cra_priority = 300, base 410 arch/x86/crypto/des3_ede_glue.c .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, base 411 arch/x86/crypto/des3_ede_glue.c .base.cra_ctxsize = sizeof(struct des3_ede_x86_ctx), base 412 arch/x86/crypto/des3_ede_glue.c .base.cra_module = THIS_MODULE, base 419 arch/x86/crypto/des3_ede_glue.c .base.cra_name = "cbc(des3_ede)", base 420 arch/x86/crypto/des3_ede_glue.c .base.cra_driver_name = "cbc-des3_ede-asm", base 421 arch/x86/crypto/des3_ede_glue.c .base.cra_priority = 300, base 422 arch/x86/crypto/des3_ede_glue.c .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, base 423 arch/x86/crypto/des3_ede_glue.c .base.cra_ctxsize = sizeof(struct des3_ede_x86_ctx), base 424 arch/x86/crypto/des3_ede_glue.c .base.cra_module = THIS_MODULE, base 432 arch/x86/crypto/des3_ede_glue.c .base.cra_name = "ctr(des3_ede)", base 433 arch/x86/crypto/des3_ede_glue.c .base.cra_driver_name = "ctr-des3_ede-asm", base 434 arch/x86/crypto/des3_ede_glue.c .base.cra_priority = 300, base 435 arch/x86/crypto/des3_ede_glue.c .base.cra_blocksize = 1, base 436 arch/x86/crypto/des3_ede_glue.c .base.cra_ctxsize = sizeof(struct des3_ede_x86_ctx), base 437 arch/x86/crypto/des3_ede_glue.c .base.cra_module = THIS_MODULE, base 151 arch/x86/crypto/ghash-clmulni-intel_glue.c .base = { base 185 arch/x86/crypto/ghash-clmulni-intel_glue.c ahash_request_set_tfm(cryptd_req, &cryptd_tfm->base); base 203 arch/x86/crypto/ghash-clmulni-intel_glue.c ahash_request_set_tfm(cryptd_req, &cryptd_tfm->base); base 244 arch/x86/crypto/ghash-clmulni-intel_glue.c ahash_request_set_tfm(cryptd_req, &cryptd_tfm->base); base 259 arch/x86/crypto/ghash-clmulni-intel_glue.c struct crypto_ahash *child = &ctx->cryptd_tfm->base; base 285 arch/x86/crypto/ghash-clmulni-intel_glue.c crypto_ahash_reqsize(&cryptd_tfm->base)); base 308 arch/x86/crypto/ghash-clmulni-intel_glue.c .base = { base 44 arch/x86/crypto/nhpoly1305-avx2-glue.c .base.cra_name = "nhpoly1305", base 45 arch/x86/crypto/nhpoly1305-avx2-glue.c .base.cra_driver_name = "nhpoly1305-avx2", base 46 arch/x86/crypto/nhpoly1305-avx2-glue.c .base.cra_priority = 300, base 47 arch/x86/crypto/nhpoly1305-avx2-glue.c .base.cra_ctxsize = sizeof(struct nhpoly1305_key), base 48 arch/x86/crypto/nhpoly1305-avx2-glue.c .base.cra_module = THIS_MODULE, base 44 arch/x86/crypto/nhpoly1305-sse2-glue.c .base.cra_name = "nhpoly1305", base 45 arch/x86/crypto/nhpoly1305-sse2-glue.c .base.cra_driver_name = "nhpoly1305-sse2", base 46 arch/x86/crypto/nhpoly1305-sse2-glue.c .base.cra_priority = 200, base 47 arch/x86/crypto/nhpoly1305-sse2-glue.c .base.cra_ctxsize = sizeof(struct nhpoly1305_key), base 48 arch/x86/crypto/nhpoly1305-sse2-glue.c .base.cra_module = THIS_MODULE, base 18 arch/x86/crypto/poly1305_glue.c struct poly1305_desc_ctx base; base 69 arch/x86/crypto/poly1305_glue.c BUILD_BUG_ON(offsetof(struct poly1305_simd_desc_ctx, base)); base 70 arch/x86/crypto/poly1305_glue.c sctx = container_of(dctx, struct poly1305_simd_desc_ctx, base); base 166 arch/x86/crypto/poly1305_glue.c .base = { base 185 arch/x86/crypto/serpent_avx2_glue.c .base.cra_name = "__ecb(serpent)", base 186 arch/x86/crypto/serpent_avx2_glue.c .base.cra_driver_name = "__ecb-serpent-avx2", base 187 arch/x86/crypto/serpent_avx2_glue.c .base.cra_priority = 600, base 188 arch/x86/crypto/serpent_avx2_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 189 arch/x86/crypto/serpent_avx2_glue.c .base.cra_blocksize = SERPENT_BLOCK_SIZE, base 190 arch/x86/crypto/serpent_avx2_glue.c .base.cra_ctxsize = sizeof(struct serpent_ctx), base 191 arch/x86/crypto/serpent_avx2_glue.c .base.cra_module = THIS_MODULE, base 198 arch/x86/crypto/serpent_avx2_glue.c .base.cra_name = "__cbc(serpent)", base 199 arch/x86/crypto/serpent_avx2_glue.c .base.cra_driver_name = "__cbc-serpent-avx2", base 200 arch/x86/crypto/serpent_avx2_glue.c .base.cra_priority = 600, base 201 arch/x86/crypto/serpent_avx2_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 202 arch/x86/crypto/serpent_avx2_glue.c .base.cra_blocksize = SERPENT_BLOCK_SIZE, base 203 arch/x86/crypto/serpent_avx2_glue.c .base.cra_ctxsize = sizeof(struct serpent_ctx), base 204 arch/x86/crypto/serpent_avx2_glue.c .base.cra_module = THIS_MODULE, base 212 arch/x86/crypto/serpent_avx2_glue.c .base.cra_name = "__ctr(serpent)", base 213 arch/x86/crypto/serpent_avx2_glue.c .base.cra_driver_name = "__ctr-serpent-avx2", base 214 arch/x86/crypto/serpent_avx2_glue.c .base.cra_priority = 600, base 215 arch/x86/crypto/serpent_avx2_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 216 arch/x86/crypto/serpent_avx2_glue.c .base.cra_blocksize = 1, base 217 arch/x86/crypto/serpent_avx2_glue.c .base.cra_ctxsize = sizeof(struct serpent_ctx), base 218 arch/x86/crypto/serpent_avx2_glue.c .base.cra_module = THIS_MODULE, base 227 arch/x86/crypto/serpent_avx2_glue.c .base.cra_name = "__xts(serpent)", base 228 arch/x86/crypto/serpent_avx2_glue.c .base.cra_driver_name = "__xts-serpent-avx2", base 229 arch/x86/crypto/serpent_avx2_glue.c .base.cra_priority = 600, base 230 arch/x86/crypto/serpent_avx2_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 231 arch/x86/crypto/serpent_avx2_glue.c .base.cra_blocksize = SERPENT_BLOCK_SIZE, base 232 arch/x86/crypto/serpent_avx2_glue.c .base.cra_ctxsize = sizeof(struct serpent_xts_ctx), base 233 arch/x86/crypto/serpent_avx2_glue.c .base.cra_module = THIS_MODULE, base 225 arch/x86/crypto/serpent_avx_glue.c .base.cra_name = "__ecb(serpent)", base 226 arch/x86/crypto/serpent_avx_glue.c .base.cra_driver_name = "__ecb-serpent-avx", base 227 arch/x86/crypto/serpent_avx_glue.c .base.cra_priority = 500, base 228 arch/x86/crypto/serpent_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 229 arch/x86/crypto/serpent_avx_glue.c .base.cra_blocksize = SERPENT_BLOCK_SIZE, base 230 arch/x86/crypto/serpent_avx_glue.c .base.cra_ctxsize = sizeof(struct serpent_ctx), base 231 arch/x86/crypto/serpent_avx_glue.c .base.cra_module = THIS_MODULE, base 238 arch/x86/crypto/serpent_avx_glue.c .base.cra_name = "__cbc(serpent)", base 239 arch/x86/crypto/serpent_avx_glue.c .base.cra_driver_name = "__cbc-serpent-avx", base 240 arch/x86/crypto/serpent_avx_glue.c .base.cra_priority = 500, base 241 arch/x86/crypto/serpent_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 242 arch/x86/crypto/serpent_avx_glue.c .base.cra_blocksize = SERPENT_BLOCK_SIZE, base 243 arch/x86/crypto/serpent_avx_glue.c .base.cra_ctxsize = sizeof(struct serpent_ctx), base 244 arch/x86/crypto/serpent_avx_glue.c .base.cra_module = THIS_MODULE, base 252 arch/x86/crypto/serpent_avx_glue.c .base.cra_name = "__ctr(serpent)", base 253 arch/x86/crypto/serpent_avx_glue.c .base.cra_driver_name = "__ctr-serpent-avx", base 254 arch/x86/crypto/serpent_avx_glue.c .base.cra_priority = 500, base 255 arch/x86/crypto/serpent_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 256 arch/x86/crypto/serpent_avx_glue.c .base.cra_blocksize = 1, base 257 arch/x86/crypto/serpent_avx_glue.c .base.cra_ctxsize = sizeof(struct serpent_ctx), base 258 arch/x86/crypto/serpent_avx_glue.c .base.cra_module = THIS_MODULE, base 267 arch/x86/crypto/serpent_avx_glue.c .base.cra_name = "__xts(serpent)", base 268 arch/x86/crypto/serpent_avx_glue.c .base.cra_driver_name = "__xts-serpent-avx", base 269 arch/x86/crypto/serpent_avx_glue.c .base.cra_priority = 500, base 270 arch/x86/crypto/serpent_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 271 arch/x86/crypto/serpent_avx_glue.c .base.cra_blocksize = SERPENT_BLOCK_SIZE, base 272 arch/x86/crypto/serpent_avx_glue.c .base.cra_ctxsize = sizeof(struct serpent_xts_ctx), base 273 arch/x86/crypto/serpent_avx_glue.c .base.cra_module = THIS_MODULE, base 156 arch/x86/crypto/serpent_sse2_glue.c .base.cra_name = "__ecb(serpent)", base 157 arch/x86/crypto/serpent_sse2_glue.c .base.cra_driver_name = "__ecb-serpent-sse2", base 158 arch/x86/crypto/serpent_sse2_glue.c .base.cra_priority = 400, base 159 arch/x86/crypto/serpent_sse2_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 160 arch/x86/crypto/serpent_sse2_glue.c .base.cra_blocksize = SERPENT_BLOCK_SIZE, base 161 arch/x86/crypto/serpent_sse2_glue.c .base.cra_ctxsize = sizeof(struct serpent_ctx), base 162 arch/x86/crypto/serpent_sse2_glue.c .base.cra_module = THIS_MODULE, base 169 arch/x86/crypto/serpent_sse2_glue.c .base.cra_name = "__cbc(serpent)", base 170 arch/x86/crypto/serpent_sse2_glue.c .base.cra_driver_name = "__cbc-serpent-sse2", base 171 arch/x86/crypto/serpent_sse2_glue.c .base.cra_priority = 400, base 172 arch/x86/crypto/serpent_sse2_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 173 arch/x86/crypto/serpent_sse2_glue.c .base.cra_blocksize = SERPENT_BLOCK_SIZE, base 174 arch/x86/crypto/serpent_sse2_glue.c .base.cra_ctxsize = sizeof(struct serpent_ctx), base 175 arch/x86/crypto/serpent_sse2_glue.c .base.cra_module = THIS_MODULE, base 183 arch/x86/crypto/serpent_sse2_glue.c .base.cra_name = "__ctr(serpent)", base 184 arch/x86/crypto/serpent_sse2_glue.c .base.cra_driver_name = "__ctr-serpent-sse2", base 185 arch/x86/crypto/serpent_sse2_glue.c .base.cra_priority = 400, base 186 arch/x86/crypto/serpent_sse2_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 187 arch/x86/crypto/serpent_sse2_glue.c .base.cra_blocksize = 1, base 188 arch/x86/crypto/serpent_sse2_glue.c .base.cra_ctxsize = sizeof(struct serpent_ctx), base 189 arch/x86/crypto/serpent_sse2_glue.c .base.cra_module = THIS_MODULE, base 99 arch/x86/crypto/sha1_ssse3_glue.c .base = { base 151 arch/x86/crypto/sha1_ssse3_glue.c .base = { base 242 arch/x86/crypto/sha1_ssse3_glue.c .base = { base 299 arch/x86/crypto/sha1_ssse3_glue.c .base = { base 109 arch/x86/crypto/sha256_ssse3_glue.c .base = { base 123 arch/x86/crypto/sha256_ssse3_glue.c .base = { base 175 arch/x86/crypto/sha256_ssse3_glue.c .base = { base 189 arch/x86/crypto/sha256_ssse3_glue.c .base = { base 257 arch/x86/crypto/sha256_ssse3_glue.c .base = { base 271 arch/x86/crypto/sha256_ssse3_glue.c .base = { base 337 arch/x86/crypto/sha256_ssse3_glue.c .base = { base 351 arch/x86/crypto/sha256_ssse3_glue.c .base = { base 108 arch/x86/crypto/sha512_ssse3_glue.c .base = { base 122 arch/x86/crypto/sha512_ssse3_glue.c .base = { base 185 arch/x86/crypto/sha512_ssse3_glue.c .base = { base 199 arch/x86/crypto/sha512_ssse3_glue.c .base = { base 256 arch/x86/crypto/sha512_ssse3_glue.c .base = { base 270 arch/x86/crypto/sha512_ssse3_glue.c .base = { base 43 arch/x86/crypto/twofish_avx_glue.c return twofish_setkey(&tfm->base, key, keylen); base 73 arch/x86/crypto/twofish_avx_glue.c u32 *flags = &tfm->base.crt_flags; base 228 arch/x86/crypto/twofish_avx_glue.c .base.cra_name = "__ecb(twofish)", base 229 arch/x86/crypto/twofish_avx_glue.c .base.cra_driver_name = "__ecb-twofish-avx", base 230 arch/x86/crypto/twofish_avx_glue.c .base.cra_priority = 400, base 231 arch/x86/crypto/twofish_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 232 arch/x86/crypto/twofish_avx_glue.c .base.cra_blocksize = TF_BLOCK_SIZE, base 233 arch/x86/crypto/twofish_avx_glue.c .base.cra_ctxsize = sizeof(struct twofish_ctx), base 234 arch/x86/crypto/twofish_avx_glue.c .base.cra_module = THIS_MODULE, base 241 arch/x86/crypto/twofish_avx_glue.c .base.cra_name = "__cbc(twofish)", base 242 arch/x86/crypto/twofish_avx_glue.c .base.cra_driver_name = "__cbc-twofish-avx", base 243 arch/x86/crypto/twofish_avx_glue.c .base.cra_priority = 400, base 244 arch/x86/crypto/twofish_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 245 arch/x86/crypto/twofish_avx_glue.c .base.cra_blocksize = TF_BLOCK_SIZE, base 246 arch/x86/crypto/twofish_avx_glue.c .base.cra_ctxsize = sizeof(struct twofish_ctx), base 247 arch/x86/crypto/twofish_avx_glue.c .base.cra_module = THIS_MODULE, base 255 arch/x86/crypto/twofish_avx_glue.c .base.cra_name = "__ctr(twofish)", base 256 arch/x86/crypto/twofish_avx_glue.c .base.cra_driver_name = "__ctr-twofish-avx", base 257 arch/x86/crypto/twofish_avx_glue.c .base.cra_priority = 400, base 258 arch/x86/crypto/twofish_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 259 arch/x86/crypto/twofish_avx_glue.c .base.cra_blocksize = 1, base 260 arch/x86/crypto/twofish_avx_glue.c .base.cra_ctxsize = sizeof(struct twofish_ctx), base 261 arch/x86/crypto/twofish_avx_glue.c .base.cra_module = THIS_MODULE, base 270 arch/x86/crypto/twofish_avx_glue.c .base.cra_name = "__xts(twofish)", base 271 arch/x86/crypto/twofish_avx_glue.c .base.cra_driver_name = "__xts-twofish-avx", base 272 arch/x86/crypto/twofish_avx_glue.c .base.cra_priority = 400, base 273 arch/x86/crypto/twofish_avx_glue.c .base.cra_flags = CRYPTO_ALG_INTERNAL, base 274 arch/x86/crypto/twofish_avx_glue.c .base.cra_blocksize = TF_BLOCK_SIZE, base 275 arch/x86/crypto/twofish_avx_glue.c .base.cra_ctxsize = sizeof(struct twofish_xts_ctx), base 276 arch/x86/crypto/twofish_avx_glue.c .base.cra_module = THIS_MODULE, base 25 arch/x86/crypto/twofish_glue_3way.c return twofish_setkey(&tfm->base, key, keylen); base 171 arch/x86/crypto/twofish_glue_3way.c .base.cra_name = "ecb(twofish)", base 172 arch/x86/crypto/twofish_glue_3way.c .base.cra_driver_name = "ecb-twofish-3way", base 173 arch/x86/crypto/twofish_glue_3way.c .base.cra_priority = 300, base 174 arch/x86/crypto/twofish_glue_3way.c .base.cra_blocksize = TF_BLOCK_SIZE, base 175 arch/x86/crypto/twofish_glue_3way.c .base.cra_ctxsize = sizeof(struct twofish_ctx), base 176 arch/x86/crypto/twofish_glue_3way.c .base.cra_module = THIS_MODULE, base 183 arch/x86/crypto/twofish_glue_3way.c .base.cra_name = "cbc(twofish)", base 184 arch/x86/crypto/twofish_glue_3way.c .base.cra_driver_name = "cbc-twofish-3way", base 185 arch/x86/crypto/twofish_glue_3way.c .base.cra_priority = 300, base 186 arch/x86/crypto/twofish_glue_3way.c .base.cra_blocksize = TF_BLOCK_SIZE, base 187 arch/x86/crypto/twofish_glue_3way.c .base.cra_ctxsize = sizeof(struct twofish_ctx), base 188 arch/x86/crypto/twofish_glue_3way.c .base.cra_module = THIS_MODULE, base 196 arch/x86/crypto/twofish_glue_3way.c .base.cra_name = "ctr(twofish)", base 197 arch/x86/crypto/twofish_glue_3way.c .base.cra_driver_name = "ctr-twofish-3way", base 198 arch/x86/crypto/twofish_glue_3way.c .base.cra_priority = 300, base 199 arch/x86/crypto/twofish_glue_3way.c .base.cra_blocksize = 1, base 200 arch/x86/crypto/twofish_glue_3way.c .base.cra_ctxsize = sizeof(struct twofish_ctx), base 201 arch/x86/crypto/twofish_glue_3way.c .base.cra_module = THIS_MODULE, base 590 arch/x86/events/intel/ds.c struct bts_record *at, *base, *top; base 603 arch/x86/events/intel/ds.c base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; base 606 arch/x86/events/intel/ds.c if (top <= base) base 625 arch/x86/events/intel/ds.c for (at = base; at < top; at++) { base 645 arch/x86/events/intel/ds.c (top - base - skip))) base 648 arch/x86/events/intel/ds.c for (at = base; at < top; at++) { base 1616 arch/x86/events/intel/ds.c get_next_pebs_record_by_bit(void *base, void *top, int bit) base 1627 arch/x86/events/intel/ds.c return base; base 1629 arch/x86/events/intel/ds.c if (base == NULL) base 1632 arch/x86/events/intel/ds.c for (at = base; at < top; at += cpuc->pebs_record_size) { base 1725 arch/x86/events/intel/ds.c void *base, void *top, base 1738 arch/x86/events/intel/ds.c void *at = get_next_pebs_record_by_bit(base, top, bit); base 1834 arch/x86/events/intel/ds.c void *base, *at, *top; base 1843 arch/x86/events/intel/ds.c base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; base 1855 arch/x86/events/intel/ds.c if (unlikely(base >= top)) { base 1860 arch/x86/events/intel/ds.c for (at = base; at < top; at += x86_pmu.pebs_record_size) { base 1936 arch/x86/events/intel/ds.c __intel_pmu_pebs_event(event, iregs, base, base 1949 arch/x86/events/intel/ds.c void *base, *at, *top; base 1956 arch/x86/events/intel/ds.c base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base; base 1965 arch/x86/events/intel/ds.c if (unlikely(base >= top)) { base 1970 arch/x86/events/intel/ds.c for (at = base; at < top; at += cpuc->pebs_record_size) { base 1991 arch/x86/events/intel/ds.c __intel_pmu_pebs_event(event, iregs, base, base 630 arch/x86/events/intel/pt.c TOPA_ENTRY(&tp->topa, 1)->base = page_to_phys(p) >> TOPA_SHIFT; base 674 arch/x86/events/intel/pt.c TOPA_ENTRY(last, -1)->base = topa_pfn(topa); base 724 arch/x86/events/intel/pt.c TOPA_ENTRY(topa, -1)->base = page_to_phys(p) >> TOPA_SHIFT; base 757 arch/x86/events/intel/pt.c (unsigned long)tp->table[i].base << TOPA_SHIFT, base 803 arch/x86/events/intel/pt.c u64 topa_idx, base, old; base 806 arch/x86/events/intel/pt.c base = buf->cur->offset + buf->output_off; base 810 arch/x86/events/intel/pt.c base += TOPA_ENTRY_SIZE(buf->cur, topa_idx); base 813 arch/x86/events/intel/pt.c local_set(&buf->data_size, base); base 815 arch/x86/events/intel/pt.c old = (local64_xchg(&buf->head, base) & base 817 arch/x86/events/intel/pt.c if (base < old) base 818 arch/x86/events/intel/pt.c base += buf->nr_pages << PAGE_SHIFT; base 820 arch/x86/events/intel/pt.c local_add(base - old, &buf->data_size); base 830 arch/x86/events/intel/pt.c return phys_to_virt(TOPA_ENTRY(buf->cur, buf->cur_idx)->base << TOPA_SHIFT); base 1171 arch/x86/events/intel/pt.c TOPA_ENTRY(buf->last, -1)->base = topa_pfn(buf->first); base 36 arch/x86/events/intel/pt.h u64 base : 36; base 454 arch/x86/events/intel/uncore_snb.c int idx, base; base 501 arch/x86/events/intel/uncore_snb.c base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE; base 505 arch/x86/events/intel/uncore_snb.c base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE; base 513 arch/x86/events/intel/uncore_snb.c event->hw.event_base = base; base 371 arch/x86/include/asm/desc.h static inline void set_desc_base(struct desc_struct *desc, unsigned long base) base 373 arch/x86/include/asm/desc.h desc->base0 = base & 0xffff; base 374 arch/x86/include/asm/desc.h desc->base1 = (base >> 16) & 0xff; base 375 arch/x86/include/asm/desc.h desc->base2 = (base >> 24) & 0xff; base 23 arch/x86/include/asm/desc_defs.h #define GDT_ENTRY_INIT(flags, base, limit) \ base 27 arch/x86/include/asm/desc_defs.h .base0 = (u16) (base), \ base 28 arch/x86/include/asm/desc_defs.h .base1 = ((base) >> 16) & 0xFF, \ base 29 arch/x86/include/asm/desc_defs.h .base2 = ((base) >> 24) & 0xFF, \ base 22 arch/x86/include/asm/div64.h #define do_div(n, base) \ base 25 arch/x86/include/asm/div64.h __base = (base); \ base 51 arch/x86/include/asm/imr.h int imr_add_range(phys_addr_t base, size_t size, base 54 arch/x86/include/asm/imr.h int imr_remove_range(phys_addr_t base, size_t size); base 387 arch/x86/include/asm/io.h extern int __must_check arch_phys_wc_add(unsigned long base, base 23 arch/x86/include/asm/iomap.h iomap_create_wc(resource_size_t base, unsigned long size, pgprot_t *prot); base 26 arch/x86/include/asm/iomap.h iomap_free(resource_size_t base, unsigned long size); base 303 arch/x86/include/asm/kvm_host.h union kvm_mmu_page_role base; base 487 arch/x86/include/asm/kvm_host.h u64 base; base 38 arch/x86/include/asm/mtrr.h extern int mtrr_add(unsigned long base, unsigned long size, base 40 arch/x86/include/asm/mtrr.h extern int mtrr_add_page(unsigned long base, unsigned long size, base 42 arch/x86/include/asm/mtrr.h extern int mtrr_del(int reg, unsigned long base, unsigned long size); base 43 arch/x86/include/asm/mtrr.h extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); base 62 arch/x86/include/asm/mtrr.h static inline int mtrr_add(unsigned long base, unsigned long size, base 67 arch/x86/include/asm/mtrr.h static inline int mtrr_add_page(unsigned long base, unsigned long size, base 72 arch/x86/include/asm/mtrr.h static inline int mtrr_del(int reg, unsigned long base, unsigned long size) base 76 arch/x86/include/asm/mtrr.h static inline int mtrr_del_page(int reg, unsigned long base, unsigned long size) base 102 arch/x86/include/asm/mtrr.h compat_ulong_t base; /* Base address */ base 109 arch/x86/include/asm/mtrr.h compat_uint_t base; /* Base address */ base 17 arch/x86/include/asm/pat.h extern int kernel_map_sync_memtype(u64 base, unsigned long size, base 946 arch/x86/include/asm/processor.h uint32_t base, eax, signature[3]; base 948 arch/x86/include/asm/processor.h for (base = 0x40000000; base < 0x40010000; base += 0x100) { base 949 arch/x86/include/asm/processor.h cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); base 952 arch/x86/include/asm/processor.h (leaves == 0 || ((eax - base) >= leaves))) base 953 arch/x86/include/asm/processor.h return base; base 12 arch/x86/include/asm/segment.h #define GDT_ENTRY(flags, base, limit) \ base 13 arch/x86/include/asm/segment.h ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \ base 16 arch/x86/include/asm/segment.h (((base) & _AC(0x00ffffff,ULL)) << 16) | \ base 158 arch/x86/include/asm/svm.h u64 base; base 51 arch/x86/include/asm/sysfb.h unsigned long base; base 48 arch/x86/include/asm/unwind_hints.h .macro UNWIND_HINT_REGS base=%rsp offset=0 indirect=0 extra=1 iret=0 base 81 arch/x86/include/asm/unwind_hints.h .macro UNWIND_HINT_IRET_REGS base=%rsp offset=0 base 82 arch/x86/include/asm/unwind_hints.h UNWIND_HINT_REGS base=\base offset=\offset iret=1 base 146 arch/x86/include/asm/uv/uv_hub.h s8 base; /* entry index of node's base addr */ base 474 arch/x86/include/asm/uv/uv_hub.h int base = gr->base; base 476 arch/x86/include/asm/uv/uv_hub.h if (base < 0) base 479 arch/x86/include/asm/uv/uv_hub.h return uv_hub_info->gr_table[base].limit; base 590 arch/x86/include/asm/uv/uv_hub.h unsigned long base; base 604 arch/x86/include/asm/uv/uv_hub.h base = (unsigned long)(uv_hub_info->gr_table[node - 1].limit); base 605 arch/x86/include/asm/uv/uv_hub.h return __va(base << UV_GAM_RANGE_SHFT | offset); base 3092 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3100 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3108 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3116 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3124 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3132 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3200 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3208 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3216 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3224 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3232 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3240 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3308 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3316 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3324 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3332 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3340 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3348 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:8; /* RW */ base 3706 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:18; /* RW */ base 3723 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:18; /* RW */ base 3731 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:18; /* RW */ base 3741 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:20; /* RW */ base 3806 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:20; /* RW */ base 3814 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:20; /* RW */ base 3822 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:26; /* RW */ base 3881 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:20; /* RW */ base 3889 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:20; /* RW */ base 3897 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:26; /* RW */ base 3943 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:16; /* RW */ base 3951 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:19; /* RW */ base 4115 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:20; /* RW */ base 4121 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:20; /* RW */ base 4128 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:20; /* RW */ base 4134 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:20; /* RW */ base 4140 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:20; /* RW */ base 4146 arch/x86/include/asm/uv/uv_mmrs.h unsigned long base:20; /* RW */ base 132 arch/x86/include/uapi/asm/kvm.h __u64 base; base 142 arch/x86/include/uapi/asm/kvm.h __u64 base; base 40 arch/x86/include/uapi/asm/mtrr.h unsigned long base; /* Base address */ base 47 arch/x86/include/uapi/asm/mtrr.h unsigned long base; /* Base address */ base 55 arch/x86/include/uapi/asm/mtrr.h __u64 base; /* Base address */ base 61 arch/x86/include/uapi/asm/mtrr.h __u64 base; /* Base address */ base 350 arch/x86/kernel/amd_nb.c u64 base, msr; base 368 arch/x86/kernel/amd_nb.c base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); base 374 arch/x86/kernel/amd_nb.c res->start = base; base 375 arch/x86/kernel/amd_nb.c res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1; base 1054 arch/x86/kernel/apic/vector.c static void __init print_APIC_field(int base) base 1061 arch/x86/kernel/apic/vector.c pr_cont("%08x", apic_read(base + i*0x10)); base 393 arch/x86/kernel/apic/x2apic_uv_x.c unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT; base 397 arch/x86/kernel/apic/x2apic_uv_x.c if (IS_ALIGNED(base, size)) base 459 arch/x86/kernel/apic/x2apic_uv_x.c grt->base = lindx; base 477 arch/x86/kernel/apic/x2apic_uv_x.c grt->base = lindx; base 485 arch/x86/kernel/apic/x2apic_uv_x.c grt->base = grt - _gr_table; base 508 arch/x86/kernel/apic/x2apic_uv_x.c int gb = grt->base; base 698 arch/x86/kernel/apic/x2apic_uv_x.c static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) base 722 arch/x86/kernel/apic/x2apic_uv_x.c if (alias.s.enable && alias.s.base == 0) { base 725 arch/x86/kernel/apic/x2apic_uv_x.c *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; base 729 arch/x86/kernel/apic/x2apic_uv_x.c *base = *size = 0; base 734 arch/x86/kernel/apic/x2apic_uv_x.c static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type) base 738 arch/x86/kernel/apic/x2apic_uv_x.c paddr = base << pshift; base 792 arch/x86/kernel/apic/x2apic_uv_x.c unsigned long base; base 806 arch/x86/kernel/apic/x2apic_uv_x.c base = (gru.v & mask) >> shift; base 807 arch/x86/kernel/apic/x2apic_uv_x.c map_high("GRU", base, shift, shift, max_pnode, map_wb); base 808 arch/x86/kernel/apic/x2apic_uv_x.c gru_start_paddr = ((u64)base << shift); base 819 arch/x86/kernel/apic/x2apic_uv_x.c map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); base 829 arch/x86/kernel/apic/x2apic_uv_x.c unsigned long base; base 840 arch/x86/kernel/apic/x2apic_uv_x.c base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK; base 851 arch/x86/kernel/apic/x2apic_uv_x.c base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK; base 859 arch/x86/kernel/apic/x2apic_uv_x.c pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io); base 902 arch/x86/kernel/apic/x2apic_uv_x.c addr1 = (base << shift) + f * (1ULL << m_io); base 903 arch/x86/kernel/apic/x2apic_uv_x.c addr2 = (base << shift) + (l + 1) * (1ULL << m_io); base 912 arch/x86/kernel/apic/x2apic_uv_x.c pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io); base 915 arch/x86/kernel/apic/x2apic_uv_x.c map_high(id, base, shift, m_io, max_io, map_uc); base 921 arch/x86/kernel/apic/x2apic_uv_x.c unsigned long mmr, base; base 936 arch/x86/kernel/apic/x2apic_uv_x.c base = mmioh.s1.base; base 944 arch/x86/kernel/apic/x2apic_uv_x.c base = mmioh.s2.base; base 953 arch/x86/kernel/apic/x2apic_uv_x.c pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode); base 954 arch/x86/kernel/apic/x2apic_uv_x.c map_high("MMIOH", base, shift, m_io, max_pnode, map_uc); base 878 arch/x86/kernel/cpu/cacheinfo.c struct _cpuid4_info_regs *base) base 904 arch/x86/kernel/cpu/cacheinfo.c nshared = base->eax.split.num_threads_sharing + 1; base 935 arch/x86/kernel/cpu/cacheinfo.c struct _cpuid4_info_regs *base) base 945 arch/x86/kernel/cpu/cacheinfo.c if (__cache_amd_cpumap_setup(cpu, index, base)) base 950 arch/x86/kernel/cpu/cacheinfo.c num_threads_sharing = 1 + base->eax.split.num_threads_sharing; base 971 arch/x86/kernel/cpu/cacheinfo.c struct _cpuid4_info_regs *base) base 973 arch/x86/kernel/cpu/cacheinfo.c this_leaf->id = base->id; base 975 arch/x86/kernel/cpu/cacheinfo.c this_leaf->level = base->eax.split.level; base 976 arch/x86/kernel/cpu/cacheinfo.c this_leaf->type = cache_type_map[base->eax.split.type]; base 978 arch/x86/kernel/cpu/cacheinfo.c base->ebx.split.coherency_line_size + 1; base 980 arch/x86/kernel/cpu/cacheinfo.c base->ebx.split.ways_of_associativity + 1; base 981 arch/x86/kernel/cpu/cacheinfo.c this_leaf->size = base->size; base 982 arch/x86/kernel/cpu/cacheinfo.c this_leaf->number_of_sets = base->ecx.split.number_of_sets + 1; base 984 arch/x86/kernel/cpu/cacheinfo.c base->ebx.split.physical_line_partition + 1; base 985 arch/x86/kernel/cpu/cacheinfo.c this_leaf->priv = base->nb; base 674 arch/x86/kernel/cpu/mce/amd.c u8 lgcy_mmio_hole_en, base = 0; base 688 arch/x86/kernel/cpu/mce/amd.c base = 1; base 693 arch/x86/kernel/cpu/mce/amd.c if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) base 716 arch/x86/kernel/cpu/mce/amd.c if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) base 10 arch/x86/kernel/cpu/mtrr/amd.c amd_get_mtrr(unsigned int reg, unsigned long *base, base 20 arch/x86/kernel/cpu/mtrr/amd.c *base = (low & 0xFFFE0000) >> PAGE_SHIFT; base 60 arch/x86/kernel/cpu/mtrr/amd.c amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) base 84 arch/x86/kernel/cpu/mtrr/amd.c | (base << PAGE_SHIFT) | (type + 1); base 96 arch/x86/kernel/cpu/mtrr/amd.c amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type) base 107 arch/x86/kernel/cpu/mtrr/amd.c || (size & ~(size - 1)) - size || (base & (size - 1))) base 27 arch/x86/kernel/cpu/mtrr/centaur.c centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg) base 58 arch/x86/kernel/cpu/mtrr/centaur.c centaur_get_mcr(unsigned int reg, unsigned long *base, base 61 arch/x86/kernel/cpu/mtrr/centaur.c *base = centaur_mcr[reg].high >> PAGE_SHIFT; base 74 arch/x86/kernel/cpu/mtrr/centaur.c centaur_set_mcr(unsigned int reg, unsigned long base, base 83 arch/x86/kernel/cpu/mtrr/centaur.c high = base << PAGE_SHIFT; base 100 arch/x86/kernel/cpu/mtrr/centaur.c centaur_validate_add_page(unsigned long base, unsigned long size, unsigned int type) base 69 arch/x86/kernel/cpu/mtrr/cleanup.c unsigned long base, size; base 77 arch/x86/kernel/cpu/mtrr/cleanup.c base = range_state[i].base_pfn; base 80 arch/x86/kernel/cpu/mtrr/cleanup.c base, base + size); base 98 arch/x86/kernel/cpu/mtrr/cleanup.c base = range_state[i].base_pfn; base 99 arch/x86/kernel/cpu/mtrr/cleanup.c if (base < (1<<(20-PAGE_SHIFT)) && mtrr_state.have_fixed && base 104 arch/x86/kernel/cpu/mtrr/cleanup.c if (base + size <= (1<<(20-PAGE_SHIFT))) base 106 arch/x86/kernel/cpu/mtrr/cleanup.c size -= (1<<(20-PAGE_SHIFT)) - base; base 107 arch/x86/kernel/cpu/mtrr/cleanup.c base = 1<<(20-PAGE_SHIFT); base 109 arch/x86/kernel/cpu/mtrr/cleanup.c subtract_range(range, RANGE_NUM, base, base + size); base 179 arch/x86/kernel/cpu/mtrr/cleanup.c u64 base, mask; base 189 arch/x86/kernel/cpu/mtrr/cleanup.c base = ((u64)basek) << 10; base 191 arch/x86/kernel/cpu/mtrr/cleanup.c base |= type; base 194 arch/x86/kernel/cpu/mtrr/cleanup.c base_lo = base & ((1ULL<<32) - 1); base 195 arch/x86/kernel/cpu/mtrr/cleanup.c base_hi = base >> 32; base 229 arch/x86/kernel/cpu/mtrr/cleanup.c unsigned long base = sizek; base 232 arch/x86/kernel/cpu/mtrr/cleanup.c if (base & ((1<<10) - 1)) { base 235 arch/x86/kernel/cpu/mtrr/cleanup.c } else if (base & ((1<<20) - 1)) { base 237 arch/x86/kernel/cpu/mtrr/cleanup.c base >>= 10; base 240 arch/x86/kernel/cpu/mtrr/cleanup.c base >>= 20; base 245 arch/x86/kernel/cpu/mtrr/cleanup.c return base; base 686 arch/x86/kernel/cpu/mtrr/cleanup.c unsigned long base, size, def, dummy; base 703 arch/x86/kernel/cpu/mtrr/cleanup.c mtrr_if->get(i, &base, &size, &type); base 704 arch/x86/kernel/cpu/mtrr/cleanup.c range_state[i].base_pfn = base; base 879 arch/x86/kernel/cpu/mtrr/cleanup.c unsigned long i, base, size, highest_pfn = 0, def, dummy; base 900 arch/x86/kernel/cpu/mtrr/cleanup.c mtrr_if->get(i, &base, &size, &type); base 901 arch/x86/kernel/cpu/mtrr/cleanup.c range_state[i].base_pfn = base; base 911 arch/x86/kernel/cpu/mtrr/cleanup.c base = range_state[i].base_pfn; base 913 arch/x86/kernel/cpu/mtrr/cleanup.c if (highest_pfn < base + size) base 914 arch/x86/kernel/cpu/mtrr/cleanup.c highest_pfn = base + size; base 14 arch/x86/kernel/cpu/mtrr/cyrix.c cyrix_get_arr(unsigned int reg, unsigned long *base, base 26 arch/x86/kernel/cpu/mtrr/cyrix.c ((unsigned char *)base)[3] = getCx86(arr); base 27 arch/x86/kernel/cpu/mtrr/cyrix.c ((unsigned char *)base)[2] = getCx86(arr + 1); base 28 arch/x86/kernel/cpu/mtrr/cyrix.c ((unsigned char *)base)[1] = getCx86(arr + 2); base 34 arch/x86/kernel/cpu/mtrr/cyrix.c shift = ((unsigned char *) base)[1] & 0x0f; base 35 arch/x86/kernel/cpu/mtrr/cyrix.c *base >>= PAGE_SHIFT; base 91 arch/x86/kernel/cpu/mtrr/cyrix.c cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg) base 179 arch/x86/kernel/cpu/mtrr/cyrix.c static void cyrix_set_arr(unsigned int reg, unsigned long base, base 228 arch/x86/kernel/cpu/mtrr/cyrix.c base <<= PAGE_SHIFT; base 229 arch/x86/kernel/cpu/mtrr/cyrix.c setCx86(arr + 0, ((unsigned char *)&base)[3]); base 230 arch/x86/kernel/cpu/mtrr/cyrix.c setCx86(arr + 1, ((unsigned char *)&base)[2]); base 231 arch/x86/kernel/cpu/mtrr/cyrix.c setCx86(arr + 2, (((unsigned char *)&base)[1]) | arr_size); base 238 arch/x86/kernel/cpu/mtrr/cyrix.c unsigned long base; base 263 arch/x86/kernel/cpu/mtrr/cyrix.c cyrix_set_arr(i, arr_state[i].base, base 164 arch/x86/kernel/cpu/mtrr/generic.c u64 base, mask; base 180 arch/x86/kernel/cpu/mtrr/generic.c base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + base 185 arch/x86/kernel/cpu/mtrr/generic.c start_state = ((start & mask) == (base & mask)); base 186 arch/x86/kernel/cpu/mtrr/generic.c end_state = ((end & mask) == (base & mask)); base 187 arch/x86/kernel/cpu/mtrr/generic.c inclusive = ((start < base) && (end > base)); base 212 arch/x86/kernel/cpu/mtrr/generic.c *partial_end = base + get_mtrr_size(mask); base 214 arch/x86/kernel/cpu/mtrr/generic.c *partial_end = base; base 226 arch/x86/kernel/cpu/mtrr/generic.c if ((start & mask) != (base & mask)) base 372 arch/x86/kernel/cpu/mtrr/generic.c static void __init update_fixed_last(unsigned base, unsigned end, base 375 arch/x86/kernel/cpu/mtrr/generic.c last_fixed_start = base; base 381 arch/x86/kernel/cpu/mtrr/generic.c print_fixed(unsigned base, unsigned step, const mtrr_type *types) base 385 arch/x86/kernel/cpu/mtrr/generic.c for (i = 0; i < 8; ++i, ++types, base += step) { base 387 arch/x86/kernel/cpu/mtrr/generic.c update_fixed_last(base, base + step, *types); base 390 arch/x86/kernel/cpu/mtrr/generic.c if (last_fixed_end == base && last_fixed_type == *types) { base 391 arch/x86/kernel/cpu/mtrr/generic.c last_fixed_end = base + step; base 396 arch/x86/kernel/cpu/mtrr/generic.c update_fixed_last(base, base + step, *types); base 560 arch/x86/kernel/cpu/mtrr/generic.c generic_get_free_region(unsigned long base, unsigned long size, int replace_reg) base 579 arch/x86/kernel/cpu/mtrr/generic.c static void generic_get_mtrr(unsigned int reg, unsigned long *base, base 596 arch/x86/kernel/cpu/mtrr/generic.c *base = 0; base 625 arch/x86/kernel/cpu/mtrr/generic.c *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; base 831 arch/x86/kernel/cpu/mtrr/generic.c static void generic_set_mtrr(unsigned int reg, unsigned long base, base 850 arch/x86/kernel/cpu/mtrr/generic.c vr->base_lo = base << PAGE_SHIFT | type; base 851 arch/x86/kernel/cpu/mtrr/generic.c vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT); base 863 arch/x86/kernel/cpu/mtrr/generic.c int generic_validate_add_page(unsigned long base, unsigned long size, base 875 arch/x86/kernel/cpu/mtrr/generic.c if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { base 876 arch/x86/kernel/cpu/mtrr/generic.c pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base); base 879 arch/x86/kernel/cpu/mtrr/generic.c if (!(base + size < 0x70000 || base > 0x7003F) && base 891 arch/x86/kernel/cpu/mtrr/generic.c last = base + size - 1; base 892 arch/x86/kernel/cpu/mtrr/generic.c for (lbase = base; !(lbase & 1) && (last & 1); base 896 arch/x86/kernel/cpu/mtrr/generic.c pr_warn("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size); base 38 arch/x86/kernel/cpu/mtrr/if.c mtrr_file_add(unsigned long base, unsigned long size, base 52 arch/x86/kernel/cpu/mtrr/if.c if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) base 54 arch/x86/kernel/cpu/mtrr/if.c base >>= PAGE_SHIFT; base 57 arch/x86/kernel/cpu/mtrr/if.c reg = mtrr_add_page(base, size, type, true); base 64 arch/x86/kernel/cpu/mtrr/if.c mtrr_file_del(unsigned long base, unsigned long size, base 71 arch/x86/kernel/cpu/mtrr/if.c if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) base 73 arch/x86/kernel/cpu/mtrr/if.c base >>= PAGE_SHIFT; base 76 arch/x86/kernel/cpu/mtrr/if.c reg = mtrr_del_page(-1, base, size); base 98 arch/x86/kernel/cpu/mtrr/if.c unsigned long long base, size; base 130 arch/x86/kernel/cpu/mtrr/if.c base = simple_strtoull(line + 5, &ptr, 0); base 137 arch/x86/kernel/cpu/mtrr/if.c if ((base & 0xfff) || (size & 0xfff)) base 149 arch/x86/kernel/cpu/mtrr/if.c base >>= PAGE_SHIFT; base 151 arch/x86/kernel/cpu/mtrr/if.c err = mtrr_add_page((unsigned long)base, (unsigned long)size, i, true); base 162 arch/x86/kernel/cpu/mtrr/if.c unsigned long base; base 199 arch/x86/kernel/cpu/mtrr/if.c err = get_user(sentry.base, &s32->base); base 212 arch/x86/kernel/cpu/mtrr/if.c err |= get_user(gentry.base, &g32->base); base 232 arch/x86/kernel/cpu/mtrr/if.c mtrr_file_add(sentry.base, sentry.size, sentry.type, true, base 241 arch/x86/kernel/cpu/mtrr/if.c err = mtrr_add(sentry.base, sentry.size, sentry.type, false); base 249 arch/x86/kernel/cpu/mtrr/if.c err = mtrr_file_del(sentry.base, sentry.size, file, 0); base 257 arch/x86/kernel/cpu/mtrr/if.c err = mtrr_del(-1, sentry.base, sentry.size); base 265 arch/x86/kernel/cpu/mtrr/if.c mtrr_if->get(gentry.regnum, &base, &size, &type); base 268 arch/x86/kernel/cpu/mtrr/if.c if (base + size - 1 >= (1UL << (8 * sizeof(gentry.size) - PAGE_SHIFT)) base 270 arch/x86/kernel/cpu/mtrr/if.c gentry.base = gentry.size = gentry.type = 0; base 272 arch/x86/kernel/cpu/mtrr/if.c gentry.base = base << PAGE_SHIFT; base 285 arch/x86/kernel/cpu/mtrr/if.c mtrr_file_add(sentry.base, sentry.size, sentry.type, true, base 295 arch/x86/kernel/cpu/mtrr/if.c mtrr_add_page(sentry.base, sentry.size, sentry.type, false); base 303 arch/x86/kernel/cpu/mtrr/if.c err = mtrr_file_del(sentry.base, sentry.size, file, 1); base 311 arch/x86/kernel/cpu/mtrr/if.c err = mtrr_del_page(-1, sentry.base, sentry.size); base 319 arch/x86/kernel/cpu/mtrr/if.c mtrr_if->get(gentry.regnum, &base, &size, &type); base 322 arch/x86/kernel/cpu/mtrr/if.c gentry.base = gentry.size = gentry.type = 0; base 324 arch/x86/kernel/cpu/mtrr/if.c gentry.base = base; base 346 arch/x86/kernel/cpu/mtrr/if.c err = put_user(gentry.base, &g32->base); base 403 arch/x86/kernel/cpu/mtrr/if.c unsigned long base, size; base 407 arch/x86/kernel/cpu/mtrr/if.c mtrr_if->get(i, &base, &size, &type); base 422 arch/x86/kernel/cpu/mtrr/if.c i, base, base >> (20 - PAGE_SHIFT), base 80 arch/x86/kernel/cpu/mtrr/mtrr.c static void set_mtrr(unsigned int reg, unsigned long base, base 230 arch/x86/kernel/cpu/mtrr/mtrr.c set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) base 233 arch/x86/kernel/cpu/mtrr/mtrr.c .smp_base = base, base 241 arch/x86/kernel/cpu/mtrr/mtrr.c static void set_mtrr_cpuslocked(unsigned int reg, unsigned long base, base 245 arch/x86/kernel/cpu/mtrr/mtrr.c .smp_base = base, base 253 arch/x86/kernel/cpu/mtrr/mtrr.c static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base, base 257 arch/x86/kernel/cpu/mtrr/mtrr.c .smp_base = base, base 301 arch/x86/kernel/cpu/mtrr/mtrr.c int mtrr_add_page(unsigned long base, unsigned long size, base 311 arch/x86/kernel/cpu/mtrr/mtrr.c error = mtrr_if->validate_add_page(base, size, type); base 331 arch/x86/kernel/cpu/mtrr/mtrr.c if ((base | (base + size - 1)) >> base 347 arch/x86/kernel/cpu/mtrr/mtrr.c if (!lsize || base > lbase + lsize - 1 || base 348 arch/x86/kernel/cpu/mtrr/mtrr.c base + size - 1 < lbase) base 354 arch/x86/kernel/cpu/mtrr/mtrr.c if (base < lbase || base + size - 1 > lbase + lsize - 1) { base 355 arch/x86/kernel/cpu/mtrr/mtrr.c if (base <= lbase && base 356 arch/x86/kernel/cpu/mtrr/mtrr.c base + size - 1 >= lbase + lsize - 1) { base 364 arch/x86/kernel/cpu/mtrr/mtrr.c pr_warn("0x%lx000,0x%lx000 overlaps existing 0x%lx000,0x%lx000\n", base, size, lbase, base 373 arch/x86/kernel/cpu/mtrr/mtrr.c base, size, mtrr_attrib_to_str(ltype), base 383 arch/x86/kernel/cpu/mtrr/mtrr.c i = mtrr_if->get_free_region(base, size, replace); base 385 arch/x86/kernel/cpu/mtrr/mtrr.c set_mtrr_cpuslocked(i, base, size, type); base 407 arch/x86/kernel/cpu/mtrr/mtrr.c static int mtrr_check(unsigned long base, unsigned long size) base 409 arch/x86/kernel/cpu/mtrr/mtrr.c if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { base 411 arch/x86/kernel/cpu/mtrr/mtrr.c pr_debug("size: 0x%lx base: 0x%lx\n", size, base); base 453 arch/x86/kernel/cpu/mtrr/mtrr.c int mtrr_add(unsigned long base, unsigned long size, unsigned int type, base 458 arch/x86/kernel/cpu/mtrr/mtrr.c if (mtrr_check(base, size)) base 460 arch/x86/kernel/cpu/mtrr/mtrr.c return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, base 478 arch/x86/kernel/cpu/mtrr/mtrr.c int mtrr_del_page(int reg, unsigned long base, unsigned long size) base 496 arch/x86/kernel/cpu/mtrr/mtrr.c if (lbase == base && lsize == size) { base 503 arch/x86/kernel/cpu/mtrr/mtrr.c base, size); base 543 arch/x86/kernel/cpu/mtrr/mtrr.c int mtrr_del(int reg, unsigned long base, unsigned long size) base 547 arch/x86/kernel/cpu/mtrr/mtrr.c if (mtrr_check(base, size)) base 549 arch/x86/kernel/cpu/mtrr/mtrr.c return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); base 567 arch/x86/kernel/cpu/mtrr/mtrr.c int arch_phys_wc_add(unsigned long base, unsigned long size) base 574 arch/x86/kernel/cpu/mtrr/mtrr.c ret = mtrr_add(base, size, MTRR_TYPE_WRCOMB, true); base 577 arch/x86/kernel/cpu/mtrr/mtrr.c (void *)base, (void *)(base + size - 1)); base 18 arch/x86/kernel/cpu/mtrr/mtrr.h void (*set)(unsigned int reg, unsigned long base, base 22 arch/x86/kernel/cpu/mtrr/mtrr.h void (*get)(unsigned int reg, unsigned long *base, base 24 arch/x86/kernel/cpu/mtrr/mtrr.h int (*get_free_region)(unsigned long base, unsigned long size, base 26 arch/x86/kernel/cpu/mtrr/mtrr.h int (*validate_add_page)(unsigned long base, unsigned long size, base 31 arch/x86/kernel/cpu/mtrr/mtrr.h extern int generic_get_free_region(unsigned long base, unsigned long size, base 33 arch/x86/kernel/cpu/mtrr/mtrr.h extern int generic_validate_add_page(unsigned long base, unsigned long size, base 38 arch/x86/kernel/devicetree.c void __init early_init_dt_add_memory_arch(u64 base, u64 size) base 562 arch/x86/kernel/early-quirks.c resource_size_t base, size; base 566 arch/x86/kernel/early-quirks.c base = early_ops->stolen_base(num, slot, func, size); base 568 arch/x86/kernel/early-quirks.c if (!size || !base) base 571 arch/x86/kernel/early-quirks.c end = base + size - 1; base 573 arch/x86/kernel/early-quirks.c intel_graphics_stolen_res.start = base; base 580 arch/x86/kernel/early-quirks.c e820__range_add(base, size, E820_TYPE_RESERVED); base 63 arch/x86/kernel/mmconf-fam10h_64.c u64 base = FAM10H_PCI_MMCONF_BASE; base 111 arch/x86/kernel/mmconf-fam10h_64.c if (base <= tom2) base 112 arch/x86/kernel/mmconf-fam10h_64.c base = (tom2 + 2 * MMCONF_UNIT - 1) & MMCONF_MASK; base 145 arch/x86/kernel/mmconf-fam10h_64.c if (range[hi_mmio_num - 1].end < base) base 147 arch/x86/kernel/mmconf-fam10h_64.c if (range[0].start > base + MMCONF_SIZE) base 151 arch/x86/kernel/mmconf-fam10h_64.c base = (range[0].start & MMCONF_MASK) - MMCONF_UNIT; base 152 arch/x86/kernel/mmconf-fam10h_64.c if ((base > tom2) && BASE_VALID(base)) base 154 arch/x86/kernel/mmconf-fam10h_64.c base = (range[hi_mmio_num - 1].end + MMCONF_UNIT) & MMCONF_MASK; base 155 arch/x86/kernel/mmconf-fam10h_64.c if (BASE_VALID(base)) base 159 arch/x86/kernel/mmconf-fam10h_64.c base = (range[i - 1].end + MMCONF_UNIT) & MMCONF_MASK; base 161 arch/x86/kernel/mmconf-fam10h_64.c if (val >= base + MMCONF_SIZE && BASE_VALID(base)) base 167 arch/x86/kernel/mmconf-fam10h_64.c fam10h_pci_mmconf_base = base; base 189 arch/x86/kernel/mmconf-fam10h_64.c u64 base = val & MMCONF_MASK; base 192 arch/x86/kernel/mmconf-fam10h_64.c fam10h_pci_mmconf_base = base; base 194 arch/x86/kernel/mmconf-fam10h_64.c } else if (fam10h_pci_mmconf_base == base) base 575 arch/x86/kernel/mpparse.c static int __init smp_scan_config(unsigned long base, unsigned long length) base 582 arch/x86/kernel/mpparse.c base, base + length - 1); base 586 arch/x86/kernel/mpparse.c bp = early_memremap(base, length); base 596 arch/x86/kernel/mpparse.c mpf_base = base; base 600 arch/x86/kernel/mpparse.c base, base + sizeof(*mpf) - 1); base 602 arch/x86/kernel/mpparse.c memblock_reserve(base, sizeof(*mpf)); base 613 arch/x86/kernel/mpparse.c base += 16; base 293 arch/x86/kernel/process_64.c unsigned long base; base 307 arch/x86/kernel/process_64.c base = get_desc_base(&task->thread.tls_array[idx]); base 320 arch/x86/kernel/process_64.c base = 0; base 322 arch/x86/kernel/process_64.c base = get_desc_base(ldt->entries + idx); base 325 arch/x86/kernel/process_64.c base = 0; base 329 arch/x86/kernel/process_64.c return base; base 766 arch/x86/kernel/process_64.c unsigned long base = x86_fsbase_read_task(task); base 768 arch/x86/kernel/process_64.c ret = put_user(base, (unsigned long __user *)arg2); base 772 arch/x86/kernel/process_64.c unsigned long base = x86_gsbase_read_task(task); base 774 arch/x86/kernel/process_64.c ret = put_user(base, (unsigned long __user *)arg2); base 479 arch/x86/kernel/setup.c unsigned long long base, low_base = 0, low_size = 0; base 486 arch/x86/kernel/setup.c ret = parse_crashkernel_low(boot_command_line, total_low_mem, &low_size, &base); base 32 arch/x86/kernel/step.c unsigned long base; base 42 arch/x86/kernel/step.c base = get_desc_base(desc); base 47 arch/x86/kernel/step.c addr += base; base 75 arch/x86/kernel/sysfb_efi.c if (efifb_dmi_list[i].base != 0 && base 77 arch/x86/kernel/sysfb_efi.c si->lfb_base = efifb_dmi_list[i].base; base 98 arch/x86/kernel/sysfb_efi.c if (info->base == 0 && info->height == 0 && info->width == 0 && base 108 arch/x86/kernel/sysfb_efi.c if (info->base) { base 109 arch/x86/kernel/sysfb_efi.c screen_info.lfb_base = choose_value(info->base, base 65 arch/x86/kernel/sysfb_simplefb.c u64 base, size; base 73 arch/x86/kernel/sysfb_simplefb.c base = si->lfb_base; base 75 arch/x86/kernel/sysfb_simplefb.c base |= (u64)si->ext_lfb_base << 32; base 76 arch/x86/kernel/sysfb_simplefb.c if (!base || (u64)(resource_size_t)base != base) { base 103 arch/x86/kernel/sysfb_simplefb.c res.start = base; base 457 arch/x86/kernel/vm86_32.c #define pushb(base, ptr, val, err_label) \ base 461 arch/x86/kernel/vm86_32.c if (put_user(__val, base + ptr) < 0) \ base 465 arch/x86/kernel/vm86_32.c #define pushw(base, ptr, val, err_label) \ base 469 arch/x86/kernel/vm86_32.c if (put_user(val_byte(__val, 1), base + ptr) < 0) \ base 472 arch/x86/kernel/vm86_32.c if (put_user(val_byte(__val, 0), base + ptr) < 0) \ base 476 arch/x86/kernel/vm86_32.c #define pushl(base, ptr, val, err_label) \ base 480 arch/x86/kernel/vm86_32.c if (put_user(val_byte(__val, 3), base + ptr) < 0) \ base 483 arch/x86/kernel/vm86_32.c if (put_user(val_byte(__val, 2), base + ptr) < 0) \ base 486 arch/x86/kernel/vm86_32.c if (put_user(val_byte(__val, 1), base + ptr) < 0) \ base 489 arch/x86/kernel/vm86_32.c if (put_user(val_byte(__val, 0), base + ptr) < 0) \ base 493 arch/x86/kernel/vm86_32.c #define popb(base, ptr, err_label) \ base 496 arch/x86/kernel/vm86_32.c if (get_user(__res, base + ptr) < 0) \ base 502 arch/x86/kernel/vm86_32.c #define popw(base, ptr, err_label) \ base 505 arch/x86/kernel/vm86_32.c if (get_user(val_byte(__res, 0), base + ptr) < 0) \ base 508 arch/x86/kernel/vm86_32.c if (get_user(val_byte(__res, 1), base + ptr) < 0) \ base 514 arch/x86/kernel/vm86_32.c #define popl(base, ptr, err_label) \ base 517 arch/x86/kernel/vm86_32.c if (get_user(val_byte(__res, 0), base + ptr) < 0) \ base 520 arch/x86/kernel/vm86_32.c if (get_user(val_byte(__res, 1), base + ptr) < 0) \ base 523 arch/x86/kernel/vm86_32.c if (get_user(val_byte(__res, 2), base + ptr) < 0) \ base 526 arch/x86/kernel/vm86_32.c if (get_user(val_byte(__res, 3), base + ptr) < 0) \ base 2979 arch/x86/kvm/emulate.c unsigned long base; base 2994 arch/x86/kvm/emulate.c base = get_desc_base(&tr_seg); base 2996 arch/x86/kvm/emulate.c base |= ((u64)base3) << 32; base 2998 arch/x86/kvm/emulate.c r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true); base 3003 arch/x86/kvm/emulate.c r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true); base 2565 arch/x86/kvm/mmu.c role = vcpu->arch.mmu->mmu_role.base; base 4666 arch/x86/kvm/mmu.c context->mmu_role.base.smep_andnot_wp; base 4989 arch/x86/kvm/mmu.c role.base.access = ACC_ALL; base 4990 arch/x86/kvm/mmu.c role.base.nxe = !!is_nx(vcpu); base 4991 arch/x86/kvm/mmu.c role.base.cr0_wp = is_write_protection(vcpu); base 4992 arch/x86/kvm/mmu.c role.base.smm = is_smm(vcpu); base 4993 arch/x86/kvm/mmu.c role.base.guest_mode = is_guest_mode(vcpu); base 5008 arch/x86/kvm/mmu.c role.base.ad_disabled = (shadow_accessed_mask == 0); base 5009 arch/x86/kvm/mmu.c role.base.level = kvm_x86_ops->get_tdp_level(vcpu); base 5010 arch/x86/kvm/mmu.c role.base.direct = true; base 5011 arch/x86/kvm/mmu.c role.base.gpte_is_8_bytes = true; base 5022 arch/x86/kvm/mmu.c new_role.base.word &= mmu_base_role_mask.word; base 5071 arch/x86/kvm/mmu.c role.base.smep_andnot_wp = role.ext.cr4_smep && base 5073 arch/x86/kvm/mmu.c role.base.smap_andnot_wp = role.ext.cr4_smap && base 5075 arch/x86/kvm/mmu.c role.base.direct = !is_paging(vcpu); base 5076 arch/x86/kvm/mmu.c role.base.gpte_is_8_bytes = !!is_pae(vcpu); base 5079 arch/x86/kvm/mmu.c role.base.level = PT32E_ROOT_LEVEL; base 5081 arch/x86/kvm/mmu.c role.base.level = PT64_ROOT_5LEVEL; base 5083 arch/x86/kvm/mmu.c role.base.level = PT64_ROOT_4LEVEL; base 5094 arch/x86/kvm/mmu.c new_role.base.word &= mmu_base_role_mask.word; base 5119 arch/x86/kvm/mmu.c role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm; base 5121 arch/x86/kvm/mmu.c role.base.level = PT64_ROOT_4LEVEL; base 5122 arch/x86/kvm/mmu.c role.base.gpte_is_8_bytes = true; base 5123 arch/x86/kvm/mmu.c role.base.direct = false; base 5124 arch/x86/kvm/mmu.c role.base.ad_disabled = !accessed_dirty; base 5125 arch/x86/kvm/mmu.c role.base.guest_mode = true; base 5126 arch/x86/kvm/mmu.c role.base.access = ACC_ALL; base 5132 arch/x86/kvm/mmu.c role.base.cr0_wp = true; base 5133 arch/x86/kvm/mmu.c role.base.smap_andnot_wp = true; base 5149 arch/x86/kvm/mmu.c __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, false); base 5151 arch/x86/kvm/mmu.c new_role.base.word &= mmu_base_role_mask.word; base 5192 arch/x86/kvm/mmu.c new_role.base.word &= mmu_base_role_mask.word; base 5266 arch/x86/kvm/mmu.c return role.base; base 5481 arch/x86/kvm/mmu.c u32 base_role = vcpu->arch.mmu->mmu_role.base.word; base 300 arch/x86/kvm/mtrr.c *start = range->base & PAGE_MASK; base 363 arch/x86/kvm/mtrr.c cur->base = data; base 370 arch/x86/kvm/mtrr.c if (cur->base >= tmp->base) base 429 arch/x86/kvm/mtrr.c *pdata = vcpu->arch.mtrr_state.var_ranges[index].base; base 600 arch/x86/kvm/mtrr.c iter->mem_type = iter->range->base & 0xff; base 89 arch/x86/kvm/pmu.h u32 base) base 91 arch/x86/kvm/pmu.h if (msr >= base && msr < base + pmu->nr_arch_gp_counters) { base 92 arch/x86/kvm/pmu.h u32 index = array_index_nospec(msr - base, base 104 arch/x86/kvm/pmu.h int base = MSR_CORE_PERF_FIXED_CTR0; base 106 arch/x86/kvm/pmu.h if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) { base 107 arch/x86/kvm/pmu.h u32 index = array_index_nospec(msr - base, base 162 arch/x86/kvm/pmu_amd.c unsigned int base = get_msr_base(pmu, PMU_TYPE_COUNTER); base 173 arch/x86/kvm/pmu_amd.c return get_gp_pmc_amd(pmu, base + pmc_idx, PMU_TYPE_COUNTER); base 830 arch/x86/kvm/svm.c svm->int3_rip = rip + svm->vmcb->save.cs.base; base 1479 arch/x86/kvm/svm.c seg->base = 0; base 1487 arch/x86/kvm/svm.c seg->base = 0; base 1613 arch/x86/kvm/svm.c save->cs.base = 0xffff0000; base 2455 arch/x86/kvm/svm.c return s->base; base 2463 arch/x86/kvm/svm.c var->base = s->base; base 2539 arch/x86/kvm/svm.c dt->address = svm->vmcb->save.idtr.base; base 2547 arch/x86/kvm/svm.c svm->vmcb->save.idtr.base = dt->address ; base 2556 arch/x86/kvm/svm.c dt->address = svm->vmcb->save.gdtr.base; base 2564 arch/x86/kvm/svm.c svm->vmcb->save.gdtr.base = dt->address ; base 2659 arch/x86/kvm/svm.c s->base = var->base; base 2792 arch/x86/kvm/svm.c svm->vmcb->save.cs.base + svm->vmcb->save.rip; base 2805 arch/x86/kvm/svm.c kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; base 4900 arch/x86/kvm/svm.c save->es.limit, save->es.base); base 4904 arch/x86/kvm/svm.c save->cs.limit, save->cs.base); base 4908 arch/x86/kvm/svm.c save->ss.limit, save->ss.base); base 4912 arch/x86/kvm/svm.c save->ds.limit, save->ds.base); base 4916 arch/x86/kvm/svm.c save->fs.limit, save->fs.base); base 4920 arch/x86/kvm/svm.c save->gs.limit, save->gs.base); base 4924 arch/x86/kvm/svm.c save->gdtr.limit, save->gdtr.base); base 4928 arch/x86/kvm/svm.c save->ldtr.limit, save->ldtr.base); base 4932 arch/x86/kvm/svm.c save->idtr.limit, save->idtr.base); base 4936 arch/x86/kvm/svm.c save->tr.limit, save->tr.base); base 5357 arch/x86/kvm/svm.c pi.base = __sme_set(page_to_phys(svm->avic_backing_page) & base 3883 arch/x86/kvm/vmx/nested.c .base = 0, base 3897 arch/x86/kvm/vmx/nested.c .base = 0, base 3912 arch/x86/kvm/vmx/nested.c seg.base = vmcs12->host_fs_base; base 3915 arch/x86/kvm/vmx/nested.c seg.base = vmcs12->host_gs_base; base 3918 arch/x86/kvm/vmx/nested.c .base = vmcs12->host_tr_base, base 4269 arch/x86/kvm/vmx/nested.c *ret = s.base + off; base 4284 arch/x86/kvm/vmx/nested.c *ret = (s.base + off) & 0xffffffff; base 4316 arch/x86/kvm/vmx/nested.c if (!(s.base == 0 && s.limit == 0xffffffff && base 5068 arch/x86/kvm/vmx/nested.c mmu->mmu_role.base.ad_disabled = !accessed_dirty; base 417 arch/x86/kvm/vmx/vmx.c .base = GUEST_##seg##_BASE, \ base 424 arch/x86/kvm/vmx/vmx.c unsigned base; base 726 arch/x86/kvm/vmx/vmx.c ulong *p = &vmx->segment_cache.seg[seg].base; base 729 arch/x86/kvm/vmx/vmx.c *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); base 2693 arch/x86/kvm/vmx/vmx.c var.selector = var.base >> 4; base 2694 arch/x86/kvm/vmx/vmx.c var.base = var.base & 0xffff0; base 2704 arch/x86/kvm/vmx/vmx.c if (save->base & 0xf) base 2711 arch/x86/kvm/vmx/vmx.c vmcs_writel(sf->base, var.base); base 3089 arch/x86/kvm/vmx/vmx.c var->base = vmx_read_guest_seg_base(vmx, seg); base 3093 arch/x86/kvm/vmx/vmx.c var->base = vmx_read_guest_seg_base(vmx, seg); base 3121 arch/x86/kvm/vmx/vmx.c return s.base; base 3174 arch/x86/kvm/vmx/vmx.c vmcs_writel(sf->base, var->base); base 3241 arch/x86/kvm/vmx/vmx.c if (var.base != (var.selector << 4)) base 3508 arch/x86/kvm/vmx/vmx.c vmcs_writel(sf->base, 0); base 242 arch/x86/kvm/vmx/vmx.h unsigned long base; base 1642 arch/x86/kvm/x86.c boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); base 6138 arch/x86/kvm/x86.c set_desc_base(desc, (unsigned long)var.base); base 6141 arch/x86/kvm/x86.c *base3 = var.base >> 32; base 6163 arch/x86/kvm/x86.c var.base = get_desc_base(desc); base 6165 arch/x86/kvm/x86.c var.base |= ((u64)base3) << 32; base 7728 arch/x86/kvm/x86.c put_smstate(u32, buf, offset + 8, seg.base); base 7747 arch/x86/kvm/x86.c put_smstate(u64, buf, offset + 8, seg.base); base 7773 arch/x86/kvm/x86.c put_smstate(u32, buf, 0x7f64, seg.base); base 7779 arch/x86/kvm/x86.c put_smstate(u32, buf, 0x7f80, seg.base); base 7835 arch/x86/kvm/x86.c put_smstate(u64, buf, 0x7e98, seg.base); base 7845 arch/x86/kvm/x86.c put_smstate(u64, buf, 0x7e78, seg.base); base 7903 arch/x86/kvm/x86.c cs.base = vcpu->arch.smbase; base 7906 arch/x86/kvm/x86.c ds.base = 0; base 8738 arch/x86/kvm/x86.c sregs->idt.base = dt.address; base 8741 arch/x86/kvm/x86.c sregs->gdt.base = dt.address; base 8882 arch/x86/kvm/x86.c dt.address = sregs->idt.base; base 8885 arch/x86/kvm/x86.c dt.address = sregs->gdt.base; base 8941 arch/x86/kvm/x86.c sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && base 9291 arch/x86/kvm/x86.c cs.base = vector << 12; base 18 arch/x86/kvm/x86.h unsigned int base, unsigned int modifier, unsigned int max) base 23 arch/x86/kvm/x86.h return base; base 25 arch/x86/kvm/x86.h if (modifier < base) base 34 arch/x86/kvm/x86.h unsigned int base, unsigned int modifier, unsigned int min) base 37 arch/x86/kvm/x86.h return base; base 39 arch/x86/kvm/x86.h if (modifier < base) base 319 arch/x86/kvm/x86.h #define do_shl32_div32(n, base) \ base 323 arch/x86/kvm/x86.h : "rm" (base), "0" (0), "1" ((u32) n)); \ base 654 arch/x86/lib/insn-eval.c unsigned long base; base 657 arch/x86/lib/insn-eval.c rdmsrl(MSR_FS_BASE, base); base 663 arch/x86/lib/insn-eval.c rdmsrl(MSR_KERNEL_GS_BASE, base); base 665 arch/x86/lib/insn-eval.c base = 0; base 666 arch/x86/lib/insn-eval.c return base; base 830 arch/x86/lib/insn-eval.c int regoff, unsigned long *base, base 835 arch/x86/lib/insn-eval.c if (!base) base 842 arch/x86/lib/insn-eval.c *base = insn_get_seg_base(regs, seg_reg_idx); base 843 arch/x86/lib/insn-eval.c if (*base == -1L) base 1065 arch/x86/lib/insn-eval.c long base, indx; base 1093 arch/x86/lib/insn-eval.c base = 0; base 1097 arch/x86/lib/insn-eval.c base = regs_get_register(regs, *base_offset); base 1109 arch/x86/lib/insn-eval.c base32 = base & 0xffffffff; base 1117 arch/x86/lib/insn-eval.c *eff_addr = base + indx * (1 << X86_SIB_SCALE(insn->sib.value)); base 346 arch/x86/lib/insn.c insn_byte_t mod, rm, base; base 372 arch/x86/lib/insn.c base = X86_SIB_BASE(insn->sib.value); base 386 arch/x86/lib/insn.c (mod == 0 && base == 5)) { base 46 arch/x86/math-emu/fpu_system.h unsigned long base = (unsigned long)d->base2 << 24; base 48 arch/x86/math-emu/fpu_system.h return base | ((unsigned long)d->base1 << 16) | d->base0; base 74 arch/x86/math-emu/get_address.c u_char ss, index, base; base 79 arch/x86/math-emu/get_address.c FPU_get_user(base, (u_char __user *) (*fpu_eip)); /* The SIB byte */ base 82 arch/x86/math-emu/get_address.c ss = base >> 6; base 83 arch/x86/math-emu/get_address.c index = (base >> 3) & 7; base 84 arch/x86/math-emu/get_address.c base &= 7; base 86 arch/x86/math-emu/get_address.c if ((mod == 0) && (base == 5)) base 89 arch/x86/math-emu/get_address.c offset = REG_(base); base 109 arch/x86/math-emu/get_address.c } else if (mod == 2 || base == 5) { /* The second condition also has mod==0 */ base 83 arch/x86/mm/amdtopology.c u64 base, limit; base 85 arch/x86/mm/amdtopology.c base = read_pci_config(0, nb, 1, 0x40 + i*8); base 89 arch/x86/mm/amdtopology.c if ((base & 3) == 0) { base 96 arch/x86/mm/amdtopology.c base, limit); base 102 arch/x86/mm/amdtopology.c i, base); base 105 arch/x86/mm/amdtopology.c if ((base >> 8) & 3 || (limit >> 8) & 3) { base 107 arch/x86/mm/amdtopology.c nodeid, (base >> 8) & 3, (limit >> 8) & 3); base 122 arch/x86/mm/amdtopology.c if (limit <= base) base 125 arch/x86/mm/amdtopology.c base >>= 16; base 126 arch/x86/mm/amdtopology.c base <<= 24; base 128 arch/x86/mm/amdtopology.c if (base < start) base 129 arch/x86/mm/amdtopology.c base = start; base 132 arch/x86/mm/amdtopology.c if (limit == base) { base 136 arch/x86/mm/amdtopology.c if (limit < base) { base 138 arch/x86/mm/amdtopology.c nodeid, base, limit); base 143 arch/x86/mm/amdtopology.c if (prevbase > base) { base 145 arch/x86/mm/amdtopology.c prevbase, base); base 150 arch/x86/mm/amdtopology.c nodeid, base, limit); base 152 arch/x86/mm/amdtopology.c prevbase = base; base 153 arch/x86/mm/amdtopology.c numa_add_memblk(nodeid, base, limit); base 293 arch/x86/mm/fault.c pgd_t *base = __va(read_cr3_pa()); base 294 arch/x86/mm/fault.c pgd_t *pgd = &base[pgd_index(address)]; base 448 arch/x86/mm/fault.c pgd_t *base = __va(read_cr3_pa()); base 449 arch/x86/mm/fault.c pgd_t *pgd = base + pgd_index(address); base 154 arch/x86/mm/init.c phys_addr_t base; base 156 arch/x86/mm/init.c base = __pa(extend_brk(tables, PAGE_SIZE)); base 158 arch/x86/mm/init.c pgt_buf_start = base >> PAGE_SHIFT; base 474 arch/x86/mm/init_32.c pgd_t *pgd, *base = swapper_pg_dir; base 491 arch/x86/mm/init_32.c pgd = base + pgd_index(va); base 516 arch/x86/mm/init_32.c paravirt_alloc_pmd(&init_mm, __pa(base) >> PAGE_SHIFT); base 11 arch/x86/mm/iomap_32.c static int is_io_mapping_possible(resource_size_t base, unsigned long size) base 15 arch/x86/mm/iomap_32.c if (base + size > 0x100000000ULL) base 21 arch/x86/mm/iomap_32.c int iomap_create_wc(resource_size_t base, unsigned long size, pgprot_t *prot) base 26 arch/x86/mm/iomap_32.c if (!is_io_mapping_possible(base, size)) base 29 arch/x86/mm/iomap_32.c ret = io_reserve_memtype(base, base + size, &pcm); base 41 arch/x86/mm/iomap_32.c void iomap_free(resource_size_t base, unsigned long size) base 43 arch/x86/mm/iomap_32.c io_free_memtype(base, base + size); base 804 arch/x86/mm/ioremap.c pgd_t *base = __va(read_cr3_pa()); base 805 arch/x86/mm/ioremap.c pgd_t *pgd = &base[pgd_index(addr)]; base 50 arch/x86/mm/kaslr.c unsigned long *base; base 105 arch/x86/mm/kaslr.c BUG_ON(kaslr_regions[0].base != &page_offset_base); base 139 arch/x86/mm/kaslr.c *kaslr_regions[i].base = vaddr; base 116 arch/x86/mm/mmap.c static void arch_pick_mmap_base(unsigned long *base, unsigned long *legacy_base, base 122 arch/x86/mm/mmap.c *base = *legacy_base; base 124 arch/x86/mm/mmap.c *base = mmap_base(random_factor, task_size, rlim_stack); base 200 arch/x86/mm/numa_emulation.c static u64 uniform_size(u64 max_addr, u64 base, u64 hole, int nr_nodes) base 203 arch/x86/mm/numa_emulation.c unsigned long base_pfn = PHYS_PFN(base); base 942 arch/x86/mm/pageattr.c struct page *base) base 945 arch/x86/mm/pageattr.c pte_t *pbase = (pte_t *)page_address(base); base 961 arch/x86/mm/pageattr.c paravirt_alloc_pte(&init_mm, page_to_pfn(base)); base 1019 arch/x86/mm/pageattr.c __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); base 1048 arch/x86/mm/pageattr.c struct page *base; base 1052 arch/x86/mm/pageattr.c base = alloc_pages(GFP_KERNEL, 0); base 1055 arch/x86/mm/pageattr.c if (!base) base 1058 arch/x86/mm/pageattr.c if (__split_large_page(cpa, kpte, address, base)) base 1059 arch/x86/mm/pageattr.c __free_page(base); base 845 arch/x86/mm/pat.c int kernel_map_sync_memtype(u64 base, unsigned long size, base 850 arch/x86/mm/pat.c if (base > __pa(high_memory-1)) base 857 arch/x86/mm/pat.c if (!page_is_ram(base >> PAGE_SHIFT)) base 860 arch/x86/mm/pat.c id_sz = (__pa(high_memory-1) <= base + size) ? base 861 arch/x86/mm/pat.c __pa(high_memory) - base : base 864 arch/x86/mm/pat.c if (ioremap_change_attr((unsigned long)__va(base), id_sz, pcm) < 0) { base 868 arch/x86/mm/pat.c base, (unsigned long long)(base + size-1)); base 696 arch/x86/pci/fixup.c u32 base, limit, high; base 713 arch/x86/pci/fixup.c pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base); base 717 arch/x86/pci/fixup.c if (!(base & (AMD_141b_MMIO_BASE_RE_MASK | base 721 arch/x86/pci/fixup.c base >>= 8; base 722 arch/x86/pci/fixup.c base |= high << 24; base 725 arch/x86/pci/fixup.c if (base > 0x10000) base 760 arch/x86/pci/fixup.c base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) | base 769 arch/x86/pci/fixup.c pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base); base 192 arch/x86/pci/mmconfig-shared.c u64 base, msr; base 211 arch/x86/pci/mmconfig-shared.c base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); base 231 arch/x86/pci/mmconfig-shared.c base + (1<<28) * i) == NULL) { base 268 arch/x86/pci/mmconfig-shared.c u64 base; base 287 arch/x86/pci/mmconfig-shared.c base = extcfg & extcfg_base_mask[size_index]; base 289 arch/x86/pci/mmconfig-shared.c base <<= extcfg_base_lshift; base 292 arch/x86/pci/mmconfig-shared.c if (pci_mmconfig_add(0, start, end, base) == NULL) base 39 arch/x86/pci/mmconfig_32.c static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn) base 41 arch/x86/pci/mmconfig_32.c u32 dev_base = base | PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12); base 55 arch/x86/pci/mmconfig_32.c u32 base; base 63 arch/x86/pci/mmconfig_32.c base = get_base_addr(seg, bus, devfn); base 64 arch/x86/pci/mmconfig_32.c if (!base) { base 71 arch/x86/pci/mmconfig_32.c pci_exp_set_dev_base(base, bus, devfn); base 94 arch/x86/pci/mmconfig_32.c u32 base; base 100 arch/x86/pci/mmconfig_32.c base = get_base_addr(seg, bus, devfn); base 101 arch/x86/pci/mmconfig_32.c if (!base) { base 108 arch/x86/pci/mmconfig_32.c pci_exp_set_dev_base(base, bus, devfn); base 29 arch/x86/pci/sta2x11-fixup.c u32 base, pexlbase, pexhbase, crw; base 279 arch/x86/pci/sta2x11-fixup.c pci_read_config_dword(pdev, AHB_BASE(i), ®s->base); base 304 arch/x86/pci/sta2x11-fixup.c pci_write_config_dword(pdev, AHB_BASE(i), regs->base); base 187 arch/x86/platform/intel-quark/imr.c phys_addr_t base; base 209 arch/x86/platform/intel-quark/imr.c base = imr_to_phys(imr.addr_lo); base 211 arch/x86/platform/intel-quark/imr.c size = end - base + 1; base 213 arch/x86/platform/intel-quark/imr.c base = 0; base 219 arch/x86/platform/intel-quark/imr.c &base, &end, size, imr.rmask, imr.wmask, base 247 arch/x86/platform/intel-quark/imr.c static int imr_check_params(phys_addr_t base, size_t size) base 249 arch/x86/platform/intel-quark/imr.c if ((base & IMR_MASK) || (size & IMR_MASK)) { base 251 arch/x86/platform/intel-quark/imr.c &base, size); base 296 arch/x86/platform/intel-quark/imr.c int imr_add_range(phys_addr_t base, size_t size, base 310 arch/x86/platform/intel-quark/imr.c ret = imr_check_params(base, size); base 316 arch/x86/platform/intel-quark/imr.c end = base + raw_size; base 322 arch/x86/platform/intel-quark/imr.c imr.addr_lo = phys_to_imr(base); base 346 arch/x86/platform/intel-quark/imr.c if (imr_address_overlap(base, &imr)) base 362 arch/x86/platform/intel-quark/imr.c reg, &base, &end, raw_size, rmask, wmask); base 365 arch/x86/platform/intel-quark/imr.c imr.addr_lo = phys_to_imr(base); base 405 arch/x86/platform/intel-quark/imr.c static int __imr_remove_range(int reg, phys_addr_t base, size_t size) base 423 arch/x86/platform/intel-quark/imr.c ret = imr_check_params(base, size); base 430 arch/x86/platform/intel-quark/imr.c end = base + raw_size; base 455 arch/x86/platform/intel-quark/imr.c if ((imr_to_phys(imr.addr_lo) == base) && base 469 arch/x86/platform/intel-quark/imr.c pr_debug("remove %d phys %pa-%pa size %zx\n", reg, &base, &end, raw_size); base 497 arch/x86/platform/intel-quark/imr.c int imr_remove_range(phys_addr_t base, size_t size) base 499 arch/x86/platform/intel-quark/imr.c return __imr_remove_range(-1, base, size); base 537 arch/x86/platform/intel-quark/imr.c phys_addr_t base = virt_to_phys(&_text); base 538 arch/x86/platform/intel-quark/imr.c size_t size = virt_to_phys(&__end_rodata) - base; base 558 arch/x86/platform/intel-quark/imr.c ret = imr_add_range(base, size, IMR_CPU, IMR_CPU); base 59 arch/x86/platform/intel-quark/imr_selftest.c phys_addr_t base = virt_to_phys(&_text); base 60 arch/x86/platform/intel-quark/imr_selftest.c size_t size = virt_to_phys(&__end_rodata) - base; base 69 arch/x86/platform/intel-quark/imr_selftest.c ret = imr_add_range(base, size, IMR_CPU, IMR_CPU); base 70 arch/x86/platform/intel-quark/imr_selftest.c imr_self_test_result(ret < 0, fmt_over, __va(base), __va(base + size)); base 73 arch/x86/platform/intel-quark/imr_selftest.c base += size - IMR_ALIGN; base 74 arch/x86/platform/intel-quark/imr_selftest.c ret = imr_add_range(base, size, IMR_CPU, IMR_CPU); base 75 arch/x86/platform/intel-quark/imr_selftest.c imr_self_test_result(ret < 0, fmt_over, __va(base), __va(base + size)); base 78 arch/x86/platform/intel-quark/imr_selftest.c base -= size + IMR_ALIGN * 2; base 79 arch/x86/platform/intel-quark/imr_selftest.c ret = imr_add_range(base, size, IMR_CPU, IMR_CPU); base 80 arch/x86/platform/intel-quark/imr_selftest.c imr_self_test_result(ret < 0, fmt_over, __va(base), __va(base + size)); base 26 arch/x86/platform/olpc/olpc_ofw.c pgd_t *base, *ofw_pde; base 32 arch/x86/platform/olpc/olpc_ofw.c base = early_ioremap(olpc_ofw_pgd, sizeof(olpc_ofw_pgd) * PTRS_PER_PGD); base 33 arch/x86/platform/olpc/olpc_ofw.c if (!base) { base 38 arch/x86/platform/olpc/olpc_ofw.c ofw_pde = &base[OLPC_OFW_PDE_NR]; base 44 arch/x86/platform/olpc/olpc_ofw.c early_iounmap(base, sizeof(olpc_ofw_pgd) * PTRS_PER_PGD); base 19 arch/x86/platform/scx200/scx200_32.c #define scx200_cb_probe(base) (inw((base) + SCx200_CBA) == (base)) base 60 arch/x86/platform/scx200/scx200_32.c unsigned base; base 64 arch/x86/platform/scx200/scx200_32.c base = pci_resource_start(pdev, 0); base 65 arch/x86/platform/scx200/scx200_32.c pr_info("GPIO base 0x%x\n", base); base 67 arch/x86/platform/scx200/scx200_32.c if (!request_region(base, SCx200_GPIO_SIZE, base 73 arch/x86/platform/scx200/scx200_32.c scx200_gpio_base = base; base 81 arch/x86/platform/scx200/scx200_32.c pci_read_config_dword(pdev, SCx200_CBA_SCRATCH, &base); base 82 arch/x86/platform/scx200/scx200_32.c if (scx200_cb_probe(base)) { base 83 arch/x86/platform/scx200/scx200_32.c scx200_cb_base = base; base 1879 arch/x86/platform/uv/tlb_uv.c int base; base 1898 arch/x86/platform/uv/tlb_uv.c base = 80; base 1900 arch/x86/platform/uv/tlb_uv.c base = 10; base 1902 arch/x86/platform/uv/tlb_uv.c ret = mult1 * base; base 44 arch/x86/realmode/init.c unsigned char *base; base 53 arch/x86/realmode/init.c base = (unsigned char *)real_mode_header; base 61 arch/x86/realmode/init.c set_memory_decrypted((unsigned long)base, size >> PAGE_SHIFT); base 63 arch/x86/realmode/init.c memcpy(base, real_mode_blob, size); base 65 arch/x86/realmode/init.c phys_base = __pa(base); base 73 arch/x86/realmode/init.c u16 *seg = (u16 *) (base + *rel++); base 80 arch/x86/realmode/init.c u32 *ptr = (u32 *) (base + *rel++); base 124 arch/x86/realmode/init.c unsigned char *base = (unsigned char *) real_mode_header; base 129 arch/x86/realmode/init.c __pa(base); base 138 arch/x86/realmode/init.c set_memory_nx((unsigned long) base, size >> PAGE_SHIFT); base 139 arch/x86/realmode/init.c set_memory_ro((unsigned long) base, ro_size >> PAGE_SHIFT); base 88 arch/x86/xen/enlighten_hvm.c uint32_t eax, ebx, ecx, edx, base; base 90 arch/x86/xen/enlighten_hvm.c base = xen_cpuid_base(); base 91 arch/x86/xen/enlighten_hvm.c eax = cpuid_eax(base + 1); base 107 arch/x86/xen/enlighten_hvm.c msr = cpuid_ebx(base + 2); base 114 arch/x86/xen/enlighten_hvm.c cpuid(base + 4, &eax, &ebx, &ecx, &edx); base 910 arch/x86/xen/enlighten_pv.c u64 base; base 922 arch/x86/xen/enlighten_pv.c base = ((u64)high << 32) | low; base 923 arch/x86/xen/enlighten_pv.c if (HYPERVISOR_set_segment_base(which, base) != 0) base 26 arch/xtensa/include/asm/pci-bridge.h unsigned long base; base 83 arch/xtensa/kernel/pci.c ioaddr -= (unsigned long)pci_ctrl->io_space.base; base 61 arch/xtensa/kernel/signal.c int base; base 71 arch/xtensa/kernel/signal.c base = (XCHAL_NUM_AREGS / 4) - (regs->wmask >> 4); base 76 arch/xtensa/kernel/signal.c if (__get_user(sp, (int*)(regs->areg[base * 4 + 1] - 12))) base 81 arch/xtensa/kernel/signal.c while (base < XCHAL_NUM_AREGS / 4) { base 83 arch/xtensa/kernel/signal.c int m = (wm >> base); base 93 arch/xtensa/kernel/signal.c ®s->areg[(base + 1) * 4], 16)) base 99 arch/xtensa/kernel/signal.c ®s->areg[(base + 1) * 4], 32)) base 106 arch/xtensa/kernel/signal.c sp = regs->areg[((base + inc) * 4 + 1) % XCHAL_NUM_AREGS]; base 107 arch/xtensa/kernel/signal.c if (copy_to_user(&SPILL_SLOT(sp, 0), ®s->areg[base * 4], 16)) base 112 arch/xtensa/kernel/signal.c sp = regs->areg[base * 4 + 1]; base 113 arch/xtensa/kernel/signal.c base += inc; base 339 arch/xtensa/kernel/signal.c unsigned int base; base 395 arch/xtensa/kernel/signal.c base = 4; base 396 arch/xtensa/kernel/signal.c regs->areg[base] = base 401 arch/xtensa/kernel/signal.c base = 0; base 402 arch/xtensa/kernel/signal.c regs->areg[base] = (unsigned long) ra; base 404 arch/xtensa/kernel/signal.c regs->areg[base + 2] = (unsigned long) sig; base 405 arch/xtensa/kernel/signal.c regs->areg[base + 3] = (unsigned long) &frame->info; base 406 arch/xtensa/kernel/signal.c regs->areg[base + 4] = (unsigned long) &frame->uc; base 80 arch/xtensa/mm/cache.c static inline void *coherent_kvaddr(struct page *page, unsigned long base, base 85 arch/xtensa/mm/cache.c return (void *)(base + (vaddr & DCACHE_ALIAS_MASK)); base 88 arch/xtensa/platforms/xtfpga/setup.c void __iomem *base = of_iomap(np, 0); base 92 arch/xtensa/platforms/xtfpga/setup.c if (!base) { base 97 arch/xtensa/platforms/xtfpga/setup.c freq = __raw_readl(base); base 98 arch/xtensa/platforms/xtfpga/setup.c iounmap(base); base 354 block/partitions/ldm.c unsigned long base, struct ldmdb *ldb) base 381 block/partitions/ldm.c data = read_part_sector(state, base + off[i], §); base 428 block/partitions/ldm.c unsigned long base, struct ldmdb *ldb) base 441 block/partitions/ldm.c data = read_part_sector(state, base + OFF_VMDB, §); base 621 block/partitions/ldm.c static int ldm_relative(const u8 *buffer, int buflen, int base, int offset) base 624 block/partitions/ldm.c base += offset; base 625 block/partitions/ldm.c if (!buffer || offset < 0 || base > buflen) { base 630 block/partitions/ldm.c if (base > buflen) base 631 block/partitions/ldm.c ldm_error("base (%d) > buflen (%d)", base, buflen); base 634 block/partitions/ldm.c if (base + buffer[base] >= buflen) { base 635 block/partitions/ldm.c ldm_error("base (%d) + buffer[base] (%d) >= buflen (%d)", base, base 636 block/partitions/ldm.c buffer[base], buflen); base 639 block/partitions/ldm.c return buffer[base] + offset + 1; base 1352 block/partitions/ldm.c static bool ldm_get_vblks(struct parsed_partitions *state, unsigned long base, base 1369 block/partitions/ldm.c data = read_part_sector(state, base + OFF_VMDB + s, §); base 1443 block/partitions/ldm.c unsigned long base; base 1463 block/partitions/ldm.c base = ldb->ph.config_start; base 1466 block/partitions/ldm.c if (!ldm_validate_tocblocks(state, base, ldb) || base 1467 block/partitions/ldm.c !ldm_validate_vmdb(state, base, ldb)) base 1477 block/partitions/ldm.c if (!ldm_get_vblks(state, base, ldb)) { base 114 crypto/842.c .base = { base 98 crypto/ablkcipher.c struct crypto_tfm *tfm = req->base.tfm; base 124 crypto/ablkcipher.c crypto_yield(req->base.flags); base 145 crypto/ablkcipher.c void *src, *dst, *base; base 156 crypto/ablkcipher.c base = p + 1; base 158 crypto/ablkcipher.c dst = (u8 *)ALIGN((unsigned long)base, alignmask + 1); base 216 crypto/ablkcipher.c struct crypto_tfm *tfm = req->base.tfm; base 224 crypto/ablkcipher.c req->base.flags |= CRYPTO_TFM_RES_BAD_BLOCK_LEN; base 261 crypto/ablkcipher.c struct crypto_tfm *tfm = req->base.tfm; base 290 crypto/ablkcipher.c walk->blocksize = crypto_tfm_alg_blocksize(req->base.tfm); base 352 crypto/ablkcipher.c crt->base = __crypto_ablkcipher_cast(tfm); base 74 crypto/acompress.c acomp->base.exit = crypto_acomp_exit_tfm; base 102 crypto/acompress.c .tfmsize = offsetof(struct crypto_acomp, base), base 144 crypto/acompress.c struct crypto_alg *base = &alg->base; base 146 crypto/acompress.c base->cra_type = &crypto_acomp_type; base 147 crypto/acompress.c base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; base 148 crypto/acompress.c base->cra_flags |= CRYPTO_ALG_TYPE_ACOMPRESS; base 150 crypto/acompress.c return crypto_register_alg(base); base 156 crypto/acompress.c return crypto_unregister_alg(&alg->base); base 389 crypto/adiantum.c req->base.flags, base 484 crypto/adiantum.c if (strcmp(streamcipher_alg->base.cra_name, "xchacha12") != 0 && base 485 crypto/adiantum.c strcmp(streamcipher_alg->base.cra_name, "xchacha20") != 0) base 494 crypto/adiantum.c if (strcmp(hash_alg->base.cra_name, "nhpoly1305") != 0) base 577 crypto/adiantum.c streamcipher_alg->base.cra_name, base 578 crypto/adiantum.c blockcipher_alg->cra_name, hash_alg->base.cra_name); base 586 crypto/adiantum.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 587 crypto/adiantum.c "adiantum(%s,%s)", streamcipher_alg->base.cra_name, base 590 crypto/adiantum.c if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 592 crypto/adiantum.c streamcipher_alg->base.cra_driver_name, base 594 crypto/adiantum.c hash_alg->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME) base 597 crypto/adiantum.c inst->alg.base.cra_flags = streamcipher_alg->base.cra_flags & base 599 crypto/adiantum.c inst->alg.base.cra_blocksize = BLOCKCIPHER_BLOCK_SIZE; base 600 crypto/adiantum.c inst->alg.base.cra_ctxsize = sizeof(struct adiantum_tfm_ctx); base 601 crypto/adiantum.c inst->alg.base.cra_alignmask = streamcipher_alg->base.cra_alignmask | base 602 crypto/adiantum.c hash_alg->base.cra_alignmask; base 609 crypto/adiantum.c inst->alg.base.cra_priority = (4 * streamcipher_alg->base.cra_priority + base 610 crypto/adiantum.c 2 * hash_alg->base.cra_priority + base 91 crypto/aead.c struct crypto_alg *alg = aead->base.__crt_alg; base 108 crypto/aead.c struct crypto_alg *alg = aead->base.__crt_alg; base 142 crypto/aead.c aead->base.exit = crypto_aead_exit_tfm; base 154 crypto/aead.c struct aead_alg *aead = container_of(alg, struct aead_alg, base); base 178 crypto/aead.c struct aead_alg *aead = container_of(alg, struct aead_alg, base); base 212 crypto/aead.c .tfmsize = offsetof(struct crypto_aead, base), base 278 crypto/aead.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 279 crypto/aead.c "%s(%s)", tmpl->name, alg->base.cra_name) >= base 282 crypto/aead.c if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 283 crypto/aead.c "%s(%s)", tmpl->name, alg->base.cra_driver_name) >= base 287 crypto/aead.c inst->alg.base.cra_flags = alg->base.cra_flags & CRYPTO_ALG_ASYNC; base 288 crypto/aead.c inst->alg.base.cra_priority = alg->base.cra_priority; base 289 crypto/aead.c inst->alg.base.cra_blocksize = alg->base.cra_blocksize; base 290 crypto/aead.c inst->alg.base.cra_alignmask = alg->base.cra_alignmask; base 291 crypto/aead.c inst->alg.base.cra_ctxsize = sizeof(struct aead_geniv_ctx); base 374 crypto/aead.c spawn->base.frontend = &crypto_aead_type; base 375 crypto/aead.c return crypto_grab_spawn(&spawn->base, name, type, mask); base 387 crypto/aead.c struct crypto_alg *base = &alg->base; base 394 crypto/aead.c alg->chunksize = base->cra_blocksize; base 396 crypto/aead.c base->cra_type = &crypto_aead_type; base 397 crypto/aead.c base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; base 398 crypto/aead.c base->cra_flags |= CRYPTO_ALG_TYPE_AEAD; base 405 crypto/aead.c struct crypto_alg *base = &alg->base; base 412 crypto/aead.c return crypto_register_alg(base); base 418 crypto/aead.c crypto_unregister_alg(&alg->base); base 468 crypto/aegis128-core.c .base = { base 141 crypto/ahash.c walk->flags = req->base.flags & CRYPTO_TFM_REQ_MASK; base 159 crypto/ahash.c walk->flags = req->base.flags & CRYPTO_TFM_REQ_MASK; base 199 crypto/ahash.c !(alg->base.cra_flags & CRYPTO_ALG_OPTIONAL_KEY)) base 238 crypto/ahash.c (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 269 crypto/ahash.c priv->complete = req->base.complete; base 270 crypto/ahash.c priv->data = req->base.data; base 271 crypto/ahash.c priv->flags = req->base.flags; base 280 crypto/ahash.c req->base.complete = cplt; base 281 crypto/ahash.c req->base.data = req; base 338 crypto/ahash.c areq->base.complete(&areq->base, err); base 374 crypto/ahash.c struct crypto_alg *alg = tfm->base.__crt_alg; base 388 crypto/ahash.c struct crypto_alg *alg = tfm->base.__crt_alg; base 402 crypto/ahash.c struct crypto_alg *alg = tfm->base.__crt_alg; base 425 crypto/ahash.c areq->base.complete(&areq->base, err); base 433 crypto/ahash.c req->base.complete = ahash_def_finup_done2; base 453 crypto/ahash.c areq->base.flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; base 459 crypto/ahash.c areq->base.complete(&areq->base, err); base 555 crypto/ahash.c .tfmsize = offsetof(struct crypto_ahash, base), base 574 crypto/ahash.c struct crypto_alg *base = &alg->halg.base; base 581 crypto/ahash.c base->cra_type = &crypto_ahash_type; base 582 crypto/ahash.c base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; base 583 crypto/ahash.c base->cra_flags |= CRYPTO_ALG_TYPE_AHASH; base 590 crypto/ahash.c struct crypto_alg *base = &alg->halg.base; base 597 crypto/ahash.c return crypto_register_alg(base); base 603 crypto/ahash.c return crypto_unregister_alg(&alg->halg.base); base 660 crypto/ahash.c return crypto_init_spawn2(&spawn->base, &alg->base, inst, base 676 crypto/ahash.c struct crypto_alg *alg = &halg->base; base 64 crypto/akcipher.c akcipher->base.exit = crypto_akcipher_exit_tfm; base 90 crypto/akcipher.c .tfmsize = offsetof(struct crypto_akcipher, base), base 96 crypto/akcipher.c spawn->base.frontend = &crypto_akcipher_type; base 97 crypto/akcipher.c return crypto_grab_spawn(&spawn->base, name, type, mask); base 110 crypto/akcipher.c struct crypto_alg *base = &alg->base; base 112 crypto/akcipher.c base->cra_type = &crypto_akcipher_type; base 113 crypto/akcipher.c base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; base 114 crypto/akcipher.c base->cra_flags |= CRYPTO_ALG_TYPE_AKCIPHER; base 124 crypto/akcipher.c struct crypto_alg *base = &alg->base; base 136 crypto/akcipher.c return crypto_register_alg(base); base 142 crypto/akcipher.c crypto_unregister_alg(&alg->base); base 427 crypto/ansi_cprng.c .base = { base 441 crypto/ansi_cprng.c .base = { base 47 crypto/arc4.c .base.cra_name = "ecb(arc4)", base 48 crypto/arc4.c .base.cra_driver_name = "ecb(arc4)-generic", base 49 crypto/arc4.c .base.cra_priority = 100, base 50 crypto/arc4.c .base.cra_blocksize = ARC4_BLOCK_SIZE, base 51 crypto/arc4.c .base.cra_ctxsize = sizeof(struct arc4_ctx), base 52 crypto/arc4.c .base.cra_module = THIS_MODULE, base 36 crypto/asymmetric_keys/verify_pefile.c #define chkaddr(base, x, s) \ base 38 crypto/asymmetric_keys/verify_pefile.c if ((x) < base || (s) >= datalen || (x) > datalen - (s)) \ base 267 crypto/authenc.c req->base.complete, req->base.data); base 407 crypto/authenc.c auth_base = &auth->base; base 439 crypto/authenc.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 441 crypto/authenc.c enc->base.cra_name) >= base 445 crypto/authenc.c if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 447 crypto/authenc.c enc->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME) base 450 crypto/authenc.c inst->alg.base.cra_flags = (auth_base->cra_flags | base 451 crypto/authenc.c enc->base.cra_flags) & CRYPTO_ALG_ASYNC; base 452 crypto/authenc.c inst->alg.base.cra_priority = enc->base.cra_priority * 10 + base 454 crypto/authenc.c inst->alg.base.cra_blocksize = enc->base.cra_blocksize; base 455 crypto/authenc.c inst->alg.base.cra_alignmask = auth_base->cra_alignmask | base 456 crypto/authenc.c enc->base.cra_alignmask; base 457 crypto/authenc.c inst->alg.base.cra_ctxsize = sizeof(struct crypto_authenc_ctx); base 265 crypto/authencesn.c req->base.complete, req->base.data); base 425 crypto/authencesn.c auth_base = &auth->base; base 454 crypto/authencesn.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 456 crypto/authencesn.c enc->base.cra_name) >= CRYPTO_MAX_ALG_NAME) base 459 crypto/authencesn.c if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 461 crypto/authencesn.c enc->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME) base 464 crypto/authencesn.c inst->alg.base.cra_flags = (auth_base->cra_flags | base 465 crypto/authencesn.c enc->base.cra_flags) & CRYPTO_ALG_ASYNC; base 466 crypto/authencesn.c inst->alg.base.cra_priority = enc->base.cra_priority * 10 + base 468 crypto/authencesn.c inst->alg.base.cra_blocksize = enc->base.cra_blocksize; base 469 crypto/authencesn.c inst->alg.base.cra_alignmask = auth_base->cra_alignmask | base 470 crypto/authencesn.c enc->base.cra_alignmask; base 471 crypto/authencesn.c inst->alg.base.cra_ctxsize = sizeof(struct crypto_authenc_esn_ctx); base 414 crypto/blkcipher.c struct crypto_tfm *tfm = req->base.tfm; base 419 crypto/blkcipher.c .flags = req->base.flags, base 428 crypto/blkcipher.c struct crypto_tfm *tfm = req->base.tfm; base 433 crypto/blkcipher.c .flags = req->base.flags, base 462 crypto/blkcipher.c crt->base = __crypto_ablkcipher_cast(tfm); base 483 crypto/ccm.c if (strncmp(mac->base.cra_name, "cbcmac(", 7) != 0 || base 509 crypto/ccm.c if (strncmp(ctr->base.cra_name, "ctr(", 4) != 0 || base 511 crypto/ccm.c ctr->base.cra_blocksize != 1) base 515 crypto/ccm.c if (strcmp(ctr->base.cra_name + 4, mac->base.cra_name + 7) != 0) base 519 crypto/ccm.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 520 crypto/ccm.c "ccm(%s", ctr->base.cra_name + 4) >= CRYPTO_MAX_ALG_NAME) base 523 crypto/ccm.c if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 524 crypto/ccm.c "ccm_base(%s,%s)", ctr->base.cra_driver_name, base 525 crypto/ccm.c mac->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME) base 528 crypto/ccm.c inst->alg.base.cra_flags = ctr->base.cra_flags & CRYPTO_ALG_ASYNC; base 529 crypto/ccm.c inst->alg.base.cra_priority = (mac->base.cra_priority + base 530 crypto/ccm.c ctr->base.cra_priority) / 2; base 531 crypto/ccm.c inst->alg.base.cra_blocksize = 1; base 532 crypto/ccm.c inst->alg.base.cra_alignmask = mac->base.cra_alignmask | base 533 crypto/ccm.c ctr->base.cra_alignmask; base 537 crypto/ccm.c inst->alg.base.cra_ctxsize = sizeof(struct crypto_ccm_ctx); base 676 crypto/ccm.c aead_request_set_callback(subreq, req->base.flags, req->base.complete, base 677 crypto/ccm.c req->base.data); base 785 crypto/ccm.c if (alg->base.cra_blocksize != 1) base 789 crypto/ccm.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 790 crypto/ccm.c "rfc4309(%s)", alg->base.cra_name) >= base 792 crypto/ccm.c snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 793 crypto/ccm.c "rfc4309(%s)", alg->base.cra_driver_name) >= base 797 crypto/ccm.c inst->alg.base.cra_flags = alg->base.cra_flags & CRYPTO_ALG_ASYNC; base 798 crypto/ccm.c inst->alg.base.cra_priority = alg->base.cra_priority; base 799 crypto/ccm.c inst->alg.base.cra_blocksize = 1; base 800 crypto/ccm.c inst->alg.base.cra_alignmask = alg->base.cra_alignmask; base 806 crypto/ccm.c inst->alg.base.cra_ctxsize = sizeof(struct crypto_rfc4309_ctx); base 943 crypto/ccm.c inst->alg.base.cra_priority = alg->cra_priority; base 944 crypto/ccm.c inst->alg.base.cra_blocksize = 1; base 951 crypto/ccm.c inst->alg.base.cra_ctxsize = sizeof(struct cbcmac_tfm_ctx); base 952 crypto/ccm.c inst->alg.base.cra_init = cbcmac_init_tfm; base 953 crypto/ccm.c inst->alg.base.cra_exit = cbcmac_exit_tfm; base 211 crypto/cfb.c inst->alg.base.cra_blocksize = 1; base 630 crypto/chacha20poly1305.c if (chacha->base.cra_blocksize != 1) base 634 crypto/chacha20poly1305.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 635 crypto/chacha20poly1305.c "%s(%s,%s)", name, chacha->base.cra_name, base 638 crypto/chacha20poly1305.c if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 639 crypto/chacha20poly1305.c "%s(%s,%s)", name, chacha->base.cra_driver_name, base 643 crypto/chacha20poly1305.c inst->alg.base.cra_flags = (chacha->base.cra_flags | poly->cra_flags) & base 645 crypto/chacha20poly1305.c inst->alg.base.cra_priority = (chacha->base.cra_priority + base 647 crypto/chacha20poly1305.c inst->alg.base.cra_blocksize = 1; base 648 crypto/chacha20poly1305.c inst->alg.base.cra_alignmask = chacha->base.cra_alignmask | base 650 crypto/chacha20poly1305.c inst->alg.base.cra_ctxsize = sizeof(struct chachapoly_ctx) + base 143 crypto/chacha_generic.c .base.cra_name = "chacha20", base 144 crypto/chacha_generic.c .base.cra_driver_name = "chacha20-generic", base 145 crypto/chacha_generic.c .base.cra_priority = 100, base 146 crypto/chacha_generic.c .base.cra_blocksize = 1, base 147 crypto/chacha_generic.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 148 crypto/chacha_generic.c .base.cra_module = THIS_MODULE, base 158 crypto/chacha_generic.c .base.cra_name = "xchacha20", base 159 crypto/chacha_generic.c .base.cra_driver_name = "xchacha20-generic", base 160 crypto/chacha_generic.c .base.cra_priority = 100, base 161 crypto/chacha_generic.c .base.cra_blocksize = 1, base 162 crypto/chacha_generic.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 163 crypto/chacha_generic.c .base.cra_module = THIS_MODULE, base 173 crypto/chacha_generic.c .base.cra_name = "xchacha12", base 174 crypto/chacha_generic.c .base.cra_driver_name = "xchacha12-generic", base 175 crypto/chacha_generic.c .base.cra_priority = 100, base 176 crypto/chacha_generic.c .base.cra_blocksize = 1, base 177 crypto/chacha_generic.c .base.cra_ctxsize = sizeof(struct chacha_ctx), base 178 crypto/chacha_generic.c .base.cra_module = THIS_MODULE, base 259 crypto/cmac.c inst->alg.base.cra_alignmask = alignmask; base 260 crypto/cmac.c inst->alg.base.cra_priority = alg->cra_priority; base 261 crypto/cmac.c inst->alg.base.cra_blocksize = alg->cra_blocksize; base 269 crypto/cmac.c inst->alg.base.cra_ctxsize = base 275 crypto/cmac.c inst->alg.base.cra_init = cmac_init_tfm; base 276 crypto/cmac.c inst->alg.base.cra_exit = cmac_exit_tfm; base 127 crypto/crc32_generic.c .base = { base 141 crypto/crc32c_generic.c .base = { base 96 crypto/crct10dif_generic.c .base = { base 276 crypto/cryptd.c rctx->complete(&req->base, err); base 283 crypto/cryptd.c static void cryptd_skcipher_encrypt(struct crypto_async_request *base, base 286 crypto/cryptd.c struct skcipher_request *req = skcipher_request_cast(base); base 305 crypto/cryptd.c req->base.complete = rctx->complete; base 311 crypto/cryptd.c static void cryptd_skcipher_decrypt(struct crypto_async_request *base, base 314 crypto/cryptd.c struct skcipher_request *req = skcipher_request_cast(base); base 333 crypto/cryptd.c req->base.complete = rctx->complete; base 347 crypto/cryptd.c rctx->complete = req->base.complete; base 348 crypto/cryptd.c req->base.complete = compl; base 350 crypto/cryptd.c return cryptd_enqueue_request(queue, &req->base); base 430 crypto/cryptd.c err = cryptd_init_instance(skcipher_crypto_instance(inst), &alg->base); base 434 crypto/cryptd.c inst->alg.base.cra_flags = CRYPTO_ALG_ASYNC | base 435 crypto/cryptd.c (alg->base.cra_flags & CRYPTO_ALG_INTERNAL); base 442 crypto/cryptd.c inst->alg.base.cra_ctxsize = sizeof(struct cryptd_skcipher_ctx); base 513 crypto/cryptd.c rctx->complete = req->base.complete; base 514 crypto/cryptd.c req->base.complete = compl; base 516 crypto/cryptd.c return cryptd_enqueue_request(queue, &req->base); base 527 crypto/cryptd.c rctx->complete(&req->base, err); base 549 crypto/cryptd.c req->base.complete = rctx->complete; base 572 crypto/cryptd.c req->base.complete = rctx->complete; base 593 crypto/cryptd.c req->base.complete = rctx->complete; base 614 crypto/cryptd.c req->base.complete = rctx->complete; base 640 crypto/cryptd.c req->base.complete = rctx->complete; base 686 crypto/cryptd.c alg = &salg->base; base 701 crypto/cryptd.c inst->alg.halg.base.cra_flags = CRYPTO_ALG_ASYNC | base 707 crypto/cryptd.c inst->alg.halg.base.cra_ctxsize = sizeof(struct cryptd_hash_ctx); base 709 crypto/cryptd.c inst->alg.halg.base.cra_init = cryptd_hash_init_tfm; base 710 crypto/cryptd.c inst->alg.halg.base.cra_exit = cryptd_hash_exit_tfm; base 778 crypto/cryptd.c compl(&req->base, err); base 791 crypto/cryptd.c req = container_of(areq, struct aead_request, base); base 801 crypto/cryptd.c req = container_of(areq, struct aead_request, base); base 812 crypto/cryptd.c rctx->complete = req->base.complete; base 813 crypto/cryptd.c req->base.complete = compl; base 814 crypto/cryptd.c return cryptd_enqueue_request(queue, &req->base); base 883 crypto/cryptd.c err = cryptd_init_instance(aead_crypto_instance(inst), &alg->base); base 887 crypto/cryptd.c inst->alg.base.cra_flags = CRYPTO_ALG_ASYNC | base 888 crypto/cryptd.c (alg->base.cra_flags & CRYPTO_ALG_INTERNAL); base 889 crypto/cryptd.c inst->alg.base.cra_ctxsize = sizeof(struct cryptd_aead_ctx); base 976 crypto/cryptd.c if (tfm->base.__crt_alg->cra_module != THIS_MODULE) { base 984 crypto/cryptd.c return container_of(tfm, struct cryptd_skcipher, base); base 990 crypto/cryptd.c struct cryptd_skcipher_ctx *ctx = crypto_skcipher_ctx(&tfm->base); base 992 crypto/cryptd.c return &ctx->child->base; base 998 crypto/cryptd.c struct cryptd_skcipher_ctx *ctx = crypto_skcipher_ctx(&tfm->base); base 1006 crypto/cryptd.c struct cryptd_skcipher_ctx *ctx = crypto_skcipher_ctx(&tfm->base); base 1009 crypto/cryptd.c crypto_free_skcipher(&tfm->base); base 1026 crypto/cryptd.c if (tfm->base.__crt_alg->cra_module != THIS_MODULE) { base 1040 crypto/cryptd.c struct cryptd_hash_ctx *ctx = crypto_ahash_ctx(&tfm->base); base 1055 crypto/cryptd.c struct cryptd_hash_ctx *ctx = crypto_ahash_ctx(&tfm->base); base 1063 crypto/cryptd.c struct cryptd_hash_ctx *ctx = crypto_ahash_ctx(&tfm->base); base 1066 crypto/cryptd.c crypto_free_ahash(&tfm->base); base 1083 crypto/cryptd.c if (tfm->base.__crt_alg->cra_module != THIS_MODULE) { base 1098 crypto/cryptd.c ctx = crypto_aead_ctx(&tfm->base); base 1105 crypto/cryptd.c struct cryptd_aead_ctx *ctx = crypto_aead_ctx(&tfm->base); base 1113 crypto/cryptd.c struct cryptd_aead_ctx *ctx = crypto_aead_ctx(&tfm->base); base 1116 crypto/cryptd.c crypto_free_aead(&tfm->base); base 226 crypto/crypto_engine.c return crypto_transfer_request_to_engine(engine, &req->base); base 239 crypto/crypto_engine.c return crypto_transfer_request_to_engine(engine, &req->base); base 252 crypto/crypto_engine.c return crypto_transfer_request_to_engine(engine, &req->base); base 265 crypto/crypto_engine.c return crypto_transfer_request_to_engine(engine, &req->base); base 278 crypto/crypto_engine.c return crypto_transfer_request_to_engine(engine, &req->base); base 293 crypto/crypto_engine.c return crypto_finalize_request(engine, &req->base, err); base 307 crypto/crypto_engine.c return crypto_finalize_request(engine, &req->base, err); base 321 crypto/crypto_engine.c return crypto_finalize_request(engine, &req->base, err); base 335 crypto/crypto_engine.c return crypto_finalize_request(engine, &req->base, err); base 349 crypto/crypto_engine.c return crypto_finalize_request(engine, &req->base, err); base 101 crypto/crypto_null.c .base = { base 110 crypto/crypto_null.c .base.cra_name = "ecb(cipher_null)", base 111 crypto/crypto_null.c .base.cra_driver_name = "ecb-cipher_null", base 112 crypto/crypto_null.c .base.cra_priority = 100, base 113 crypto/crypto_null.c .base.cra_blocksize = NULL_BLOCK_SIZE, base 114 crypto/crypto_null.c .base.cra_ctxsize = 0, base 115 crypto/crypto_null.c .base.cra_module = THIS_MODULE, base 146 crypto/ctr.c inst->alg.base.cra_blocksize = 1; base 215 crypto/ctr.c skcipher_request_set_callback(subreq, req->base.flags, base 216 crypto/ctr.c req->base.complete, req->base.data); base 308 crypto/ctr.c if (alg->base.cra_blocksize != 1) base 312 crypto/ctr.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 313 crypto/ctr.c "rfc3686(%s)", alg->base.cra_name) >= CRYPTO_MAX_ALG_NAME) base 315 crypto/ctr.c if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 316 crypto/ctr.c "rfc3686(%s)", alg->base.cra_driver_name) >= base 320 crypto/ctr.c inst->alg.base.cra_priority = alg->base.cra_priority; base 321 crypto/ctr.c inst->alg.base.cra_blocksize = 1; base 322 crypto/ctr.c inst->alg.base.cra_alignmask = alg->base.cra_alignmask; base 324 crypto/ctr.c inst->alg.base.cra_flags = alg->base.cra_flags & CRYPTO_ALG_ASYNC; base 337 crypto/ctr.c inst->alg.base.cra_ctxsize = sizeof(struct crypto_rfc3686_ctx); base 125 crypto/cts.c skcipher_request_set_callback(subreq, req->base.flags & base 163 crypto/cts.c skcipher_request_set_callback(subreq, req->base.flags, base 164 crypto/cts.c req->base.complete, base 165 crypto/cts.c req->base.data); base 174 crypto/cts.c skcipher_request_set_callback(subreq, req->base.flags, base 218 crypto/cts.c skcipher_request_set_callback(subreq, req->base.flags & base 258 crypto/cts.c skcipher_request_set_callback(subreq, req->base.flags, base 259 crypto/cts.c req->base.complete, base 260 crypto/cts.c req->base.data); base 266 crypto/cts.c skcipher_request_set_callback(subreq, req->base.flags, base 364 crypto/cts.c if (crypto_skcipher_alg_ivsize(alg) != alg->base.cra_blocksize) base 367 crypto/cts.c if (strncmp(alg->base.cra_name, "cbc(", 4)) base 371 crypto/cts.c &alg->base); base 375 crypto/cts.c inst->alg.base.cra_flags = alg->base.cra_flags & CRYPTO_ALG_ASYNC; base 376 crypto/cts.c inst->alg.base.cra_priority = alg->base.cra_priority; base 377 crypto/cts.c inst->alg.base.cra_blocksize = alg->base.cra_blocksize; base 378 crypto/cts.c inst->alg.base.cra_alignmask = alg->base.cra_alignmask; base 380 crypto/cts.c inst->alg.ivsize = alg->base.cra_blocksize; base 385 crypto/cts.c inst->alg.base.cra_ctxsize = sizeof(struct crypto_cts_ctx); base 294 crypto/deflate.c .base = { base 304 crypto/deflate.c .base = { base 36 crypto/dh.c static int _compute_val(const struct dh_ctx *ctx, MPI base, MPI val) base 39 crypto/dh.c return mpi_powm(val, base, ctx->xa, ctx->p); base 153 crypto/dh.c MPI base, val = mpi_alloc(0); base 166 crypto/dh.c base = mpi_read_raw_from_sgl(req->src, req->src_len); base 167 crypto/dh.c if (!base) { base 171 crypto/dh.c ret = dh_is_pubkey_valid(ctx, base); base 175 crypto/dh.c base = ctx->g; base 178 crypto/dh.c ret = _compute_val(ctx, base, val); base 190 crypto/dh.c mpi_free(base); base 216 crypto/dh.c .base = { base 2062 crypto/drbg.c memcpy(alg->base.cra_name, "stdrng", 6); base 2064 crypto/drbg.c memcpy(alg->base.cra_driver_name, "drbg_pr_", 8); base 2067 crypto/drbg.c memcpy(alg->base.cra_driver_name, "drbg_nopr_", 10); base 2070 crypto/drbg.c memcpy(alg->base.cra_driver_name + pos, core->cra_name, base 2073 crypto/drbg.c alg->base.cra_priority = priority; base 2081 crypto/drbg.c alg->base.cra_priority += 200; base 2083 crypto/drbg.c alg->base.cra_ctxsize = sizeof(struct drbg_state); base 2084 crypto/drbg.c alg->base.cra_module = THIS_MODULE; base 2085 crypto/drbg.c alg->base.cra_init = drbg_kcapi_init; base 2086 crypto/drbg.c alg->base.cra_exit = drbg_kcapi_cleanup; base 146 crypto/ecdh.c .base = { base 48 crypto/echainiv.c skcipher_request_set_callback(nreq, req->base.flags, base 59 crypto/echainiv.c aead_request_set_callback(subreq, req->base.flags, base 60 crypto/echainiv.c req->base.complete, req->base.data); base 99 crypto/echainiv.c compl = req->base.complete; base 100 crypto/echainiv.c data = req->base.data; base 102 crypto/echainiv.c aead_request_set_callback(subreq, req->base.flags, compl, data); base 133 crypto/echainiv.c inst->alg.base.cra_ctxsize = sizeof(struct aead_geniv_ctx); base 134 crypto/echainiv.c inst->alg.base.cra_ctxsize += inst->alg.ivsize; base 271 crypto/ecrdsa.c .base = { base 464 crypto/essiv.c struct crypto_alg *base, *block_base; base 495 crypto/essiv.c base = &skcipher_inst->alg.base; base 507 crypto/essiv.c block_base = &skcipher_alg->base; base 517 crypto/essiv.c base = &aead_inst->alg.base; base 529 crypto/essiv.c block_base = &aead_alg->base; base 562 crypto/essiv.c block_base->cra_name, hash_alg->base.cra_name); base 568 crypto/essiv.c strlcpy(ictx->shash_driver_name, hash_alg->base.cra_driver_name, base 574 crypto/essiv.c if (snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, base 576 crypto/essiv.c hash_alg->base.cra_name) >= CRYPTO_MAX_ALG_NAME) base 578 crypto/essiv.c if (snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, base 580 crypto/essiv.c hash_alg->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME) base 583 crypto/essiv.c base->cra_flags = block_base->cra_flags & CRYPTO_ALG_ASYNC; base 584 crypto/essiv.c base->cra_blocksize = block_base->cra_blocksize; base 585 crypto/essiv.c base->cra_ctxsize = sizeof(struct essiv_tfm_ctx); base 586 crypto/essiv.c base->cra_alignmask = block_base->cra_alignmask; base 587 crypto/essiv.c base->cra_priority = block_base->cra_priority; base 624 crypto/gcm.c if (strcmp(ghash->base.cra_name, "ghash") != 0 || base 639 crypto/gcm.c if (strncmp(ctr->base.cra_name, "ctr(", 4) != 0 || base 641 crypto/gcm.c ctr->base.cra_blocksize != 1) base 645 crypto/gcm.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 646 crypto/gcm.c "gcm(%s", ctr->base.cra_name + 4) >= CRYPTO_MAX_ALG_NAME) base 649 crypto/gcm.c if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 650 crypto/gcm.c "gcm_base(%s,%s)", ctr->base.cra_driver_name, base 655 crypto/gcm.c inst->alg.base.cra_flags = (ghash->base.cra_flags | base 656 crypto/gcm.c ctr->base.cra_flags) & CRYPTO_ALG_ASYNC; base 657 crypto/gcm.c inst->alg.base.cra_priority = (ghash->base.cra_priority + base 658 crypto/gcm.c ctr->base.cra_priority) / 2; base 659 crypto/gcm.c inst->alg.base.cra_blocksize = 1; base 660 crypto/gcm.c inst->alg.base.cra_alignmask = ghash->base.cra_alignmask | base 661 crypto/gcm.c ctr->base.cra_alignmask; base 662 crypto/gcm.c inst->alg.base.cra_ctxsize = sizeof(struct crypto_gcm_ctx); base 792 crypto/gcm.c aead_request_set_callback(subreq, req->base.flags, req->base.complete, base 793 crypto/gcm.c req->base.data); base 907 crypto/gcm.c if (alg->base.cra_blocksize != 1) base 911 crypto/gcm.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 912 crypto/gcm.c "rfc4106(%s)", alg->base.cra_name) >= base 914 crypto/gcm.c snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 915 crypto/gcm.c "rfc4106(%s)", alg->base.cra_driver_name) >= base 919 crypto/gcm.c inst->alg.base.cra_flags = alg->base.cra_flags & CRYPTO_ALG_ASYNC; base 920 crypto/gcm.c inst->alg.base.cra_priority = alg->base.cra_priority; base 921 crypto/gcm.c inst->alg.base.cra_blocksize = 1; base 922 crypto/gcm.c inst->alg.base.cra_alignmask = alg->base.cra_alignmask; base 924 crypto/gcm.c inst->alg.base.cra_ctxsize = sizeof(struct crypto_rfc4106_ctx); base 1009 crypto/gcm.c aead_request_set_callback(subreq, req->base.flags, base 1010 crypto/gcm.c req->base.complete, req->base.data); base 1029 crypto/gcm.c skcipher_request_set_callback(nreq, req->base.flags, NULL, NULL); base 1145 crypto/gcm.c if (alg->base.cra_blocksize != 1) base 1149 crypto/gcm.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 1150 crypto/gcm.c "rfc4543(%s)", alg->base.cra_name) >= base 1152 crypto/gcm.c snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 1153 crypto/gcm.c "rfc4543(%s)", alg->base.cra_driver_name) >= base 1157 crypto/gcm.c inst->alg.base.cra_flags = alg->base.cra_flags & CRYPTO_ALG_ASYNC; base 1158 crypto/gcm.c inst->alg.base.cra_priority = alg->base.cra_priority; base 1159 crypto/gcm.c inst->alg.base.cra_blocksize = 1; base 1160 crypto/gcm.c inst->alg.base.cra_alignmask = alg->base.cra_alignmask; base 1162 crypto/gcm.c inst->alg.base.cra_ctxsize = sizeof(struct crypto_rfc4543_ctx); base 159 crypto/ghash-generic.c .base = { base 186 crypto/hmac.c alg = &salg->base; base 209 crypto/hmac.c inst->alg.base.cra_priority = alg->cra_priority; base 210 crypto/hmac.c inst->alg.base.cra_blocksize = alg->cra_blocksize; base 211 crypto/hmac.c inst->alg.base.cra_alignmask = alg->cra_alignmask; base 217 crypto/hmac.c inst->alg.base.cra_ctxsize = sizeof(struct hmac_ctx) + base 220 crypto/hmac.c inst->alg.base.cra_init = hmac_init_tfm; base 221 crypto/hmac.c inst->alg.base.cra_exit = hmac_exit_tfm; base 167 crypto/jitterentropy-kcapi.c .base = { base 278 crypto/keywrap.c inst->alg.base.cra_blocksize = SEMIBSIZE; base 279 crypto/keywrap.c inst->alg.base.cra_alignmask = 0; base 63 crypto/kpp.c kpp->base.exit = crypto_kpp_exit_tfm; base 81 crypto/kpp.c .tfmsize = offsetof(struct crypto_kpp, base), base 92 crypto/kpp.c struct crypto_alg *base = &alg->base; base 94 crypto/kpp.c base->cra_type = &crypto_kpp_type; base 95 crypto/kpp.c base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; base 96 crypto/kpp.c base->cra_flags |= CRYPTO_ALG_TYPE_KPP; base 101 crypto/kpp.c struct crypto_alg *base = &alg->base; base 104 crypto/kpp.c return crypto_register_alg(base); base 110 crypto/kpp.c crypto_unregister_alg(&alg->base); base 216 crypto/lrw.c rctx->subreq.base.flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; base 230 crypto/lrw.c skcipher_request_set_callback(subreq, req->base.flags, crypt_done, req); base 346 crypto/lrw.c if (alg->base.cra_blocksize != LRW_BLOCK_SIZE) base 353 crypto/lrw.c &alg->base); base 358 crypto/lrw.c cipher_name = alg->base.cra_name; base 375 crypto/lrw.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 383 crypto/lrw.c inst->alg.base.cra_flags = alg->base.cra_flags & CRYPTO_ALG_ASYNC; base 384 crypto/lrw.c inst->alg.base.cra_priority = alg->base.cra_priority; base 385 crypto/lrw.c inst->alg.base.cra_blocksize = LRW_BLOCK_SIZE; base 386 crypto/lrw.c inst->alg.base.cra_alignmask = alg->base.cra_alignmask | base 395 crypto/lrw.c inst->alg.base.cra_ctxsize = sizeof(struct priv); base 125 crypto/lz4.c .base = { base 126 crypto/lz4hc.c .base = { base 128 crypto/lzo-rle.c .base = { base 128 crypto/lzo.c .base = { base 218 crypto/md4.c .base = { base 230 crypto/md5.c .base = { base 157 crypto/michael_mic.c .base = { base 224 crypto/nhpoly1305.c .base.cra_name = "nhpoly1305", base 225 crypto/nhpoly1305.c .base.cra_driver_name = "nhpoly1305-generic", base 226 crypto/nhpoly1305.c .base.cra_priority = 100, base 227 crypto/nhpoly1305.c .base.cra_ctxsize = sizeof(struct nhpoly1305_key), base 228 crypto/nhpoly1305.c .base.cra_module = THIS_MODULE, base 63 crypto/ofb.c inst->alg.base.cra_blocksize = 1; base 64 crypto/pcrypt.c aead_request_complete(req->base.data, padata->info); base 269 crypto/pcrypt.c err = pcrypt_init_instance(aead_crypto_instance(inst), &alg->base); base 273 crypto/pcrypt.c inst->alg.base.cra_flags = CRYPTO_ALG_ASYNC; base 278 crypto/pcrypt.c inst->alg.base.cra_ctxsize = sizeof(struct pcrypt_aead_ctx); base 302 crypto/poly1305_generic.c .base = { base 299 crypto/rmd128.c .base = { base 343 crypto/rmd160.c .base = { base 318 crypto/rmd256.c .base = { base 367 crypto/rmd320.c .base = { base 33 crypto/rng.c struct crypto_alg *alg = tfm->base.__crt_alg; base 68 crypto/rng.c struct rng_alg *ralg = container_of(alg, struct rng_alg, base); base 111 crypto/rng.c .tfmsize = offsetof(struct crypto_rng, base), base 183 crypto/rng.c struct crypto_alg *base = &alg->base; base 188 crypto/rng.c base->cra_type = &crypto_rng_type; base 189 crypto/rng.c base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; base 190 crypto/rng.c base->cra_flags |= CRYPTO_ALG_TYPE_RNG; base 192 crypto/rng.c return crypto_register_alg(base); base 198 crypto/rng.c crypto_unregister_alg(&alg->base); base 221 crypto/rsa-pkcs1pad.c async_req.data = req->base.data; base 224 crypto/rsa-pkcs1pad.c req->base.complete(&async_req, base 262 crypto/rsa-pkcs1pad.c akcipher_request_set_callback(&req_ctx->child_req, req->base.flags, base 339 crypto/rsa-pkcs1pad.c async_req.data = req->base.data; base 342 crypto/rsa-pkcs1pad.c req->base.complete(&async_req, pkcs1pad_decrypt_complete(req, err)); base 363 crypto/rsa-pkcs1pad.c akcipher_request_set_callback(&req_ctx->child_req, req->base.flags, base 421 crypto/rsa-pkcs1pad.c akcipher_request_set_callback(&req_ctx->child_req, req->base.flags, base 517 crypto/rsa-pkcs1pad.c async_req.data = req->base.data; base 520 crypto/rsa-pkcs1pad.c req->base.complete(&async_req, pkcs1pad_verify_complete(req, err)); base 551 crypto/rsa-pkcs1pad.c akcipher_request_set_callback(&req_ctx->child_req, req->base.flags, base 639 crypto/rsa-pkcs1pad.c crypto_set_spawn(&spawn->base, akcipher_crypto_instance(inst)); base 650 crypto/rsa-pkcs1pad.c if (snprintf(inst->alg.base.cra_name, base 652 crypto/rsa-pkcs1pad.c rsa_alg->base.cra_name) >= CRYPTO_MAX_ALG_NAME) base 655 crypto/rsa-pkcs1pad.c if (snprintf(inst->alg.base.cra_driver_name, base 657 crypto/rsa-pkcs1pad.c rsa_alg->base.cra_driver_name) >= base 661 crypto/rsa-pkcs1pad.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 662 crypto/rsa-pkcs1pad.c "pkcs1pad(%s,%s)", rsa_alg->base.cra_name, base 666 crypto/rsa-pkcs1pad.c if (snprintf(inst->alg.base.cra_driver_name, base 668 crypto/rsa-pkcs1pad.c rsa_alg->base.cra_driver_name, base 673 crypto/rsa-pkcs1pad.c inst->alg.base.cra_flags = rsa_alg->base.cra_flags & CRYPTO_ALG_ASYNC; base 674 crypto/rsa-pkcs1pad.c inst->alg.base.cra_priority = rsa_alg->base.cra_priority; base 675 crypto/rsa-pkcs1pad.c inst->alg.base.cra_ctxsize = sizeof(struct pkcs1pad_ctx); base 249 crypto/rsa.c .base = { base 180 crypto/salsa20_generic.c .base.cra_name = "salsa20", base 181 crypto/salsa20_generic.c .base.cra_driver_name = "salsa20-generic", base 182 crypto/salsa20_generic.c .base.cra_priority = 100, base 183 crypto/salsa20_generic.c .base.cra_blocksize = 1, base 184 crypto/salsa20_generic.c .base.cra_ctxsize = sizeof(struct salsa20_ctx), base 185 crypto/salsa20_generic.c .base.cra_module = THIS_MODULE, base 254 crypto/scompress.c .tfmsize = offsetof(struct crypto_scomp, base), base 259 crypto/scompress.c struct crypto_alg *base = &alg->base; base 261 crypto/scompress.c base->cra_type = &crypto_scomp_type; base 262 crypto/scompress.c base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; base 263 crypto/scompress.c base->cra_flags |= CRYPTO_ALG_TYPE_SCOMPRESS; base 265 crypto/scompress.c return crypto_register_alg(base); base 271 crypto/scompress.c return crypto_unregister_alg(&alg->base); base 41 crypto/seqiv.c static void seqiv_aead_encrypt_complete(struct crypto_async_request *base, base 44 crypto/seqiv.c struct aead_request *req = base->data; base 66 crypto/seqiv.c compl = req->base.complete; base 67 crypto/seqiv.c data = req->base.data; base 74 crypto/seqiv.c skcipher_request_set_callback(nreq, req->base.flags, base 87 crypto/seqiv.c info = kmemdup(req->iv, ivsize, req->base.flags & base 97 crypto/seqiv.c aead_request_set_callback(subreq, req->base.flags, compl, data); base 125 crypto/seqiv.c compl = req->base.complete; base 126 crypto/seqiv.c data = req->base.data; base 128 crypto/seqiv.c aead_request_set_callback(subreq, req->base.flags, compl, data); base 158 crypto/seqiv.c inst->alg.base.cra_ctxsize = sizeof(struct aead_geniv_ctx); base 159 crypto/seqiv.c inst->alg.base.cra_ctxsize += inst->alg.ivsize; base 71 crypto/sha1_generic.c .base = { base 76 crypto/sha256_generic.c .base = { base 90 crypto/sha256_generic.c .base = { base 246 crypto/sha3_generic.c .base.cra_name = "sha3-224", base 247 crypto/sha3_generic.c .base.cra_driver_name = "sha3-224-generic", base 248 crypto/sha3_generic.c .base.cra_blocksize = SHA3_224_BLOCK_SIZE, base 249 crypto/sha3_generic.c .base.cra_module = THIS_MODULE, base 256 crypto/sha3_generic.c .base.cra_name = "sha3-256", base 257 crypto/sha3_generic.c .base.cra_driver_name = "sha3-256-generic", base 258 crypto/sha3_generic.c .base.cra_blocksize = SHA3_256_BLOCK_SIZE, base 259 crypto/sha3_generic.c .base.cra_module = THIS_MODULE, base 266 crypto/sha3_generic.c .base.cra_name = "sha3-384", base 267 crypto/sha3_generic.c .base.cra_driver_name = "sha3-384-generic", base 268 crypto/sha3_generic.c .base.cra_blocksize = SHA3_384_BLOCK_SIZE, base 269 crypto/sha3_generic.c .base.cra_module = THIS_MODULE, base 276 crypto/sha3_generic.c .base.cra_name = "sha3-512", base 277 crypto/sha3_generic.c .base.cra_driver_name = "sha3-512-generic", base 278 crypto/sha3_generic.c .base.cra_blocksize = SHA3_512_BLOCK_SIZE, base 279 crypto/sha3_generic.c .base.cra_module = THIS_MODULE, base 188 crypto/sha512_generic.c .base = { base 202 crypto/sha512_generic.c .base = { base 54 crypto/shash.c !(alg->base.cra_flags & CRYPTO_ALG_OPTIONAL_KEY)) base 444 crypto/shash.c .tfmsize = offsetof(struct crypto_shash, base), base 456 crypto/shash.c struct crypto_alg *base = &alg->base; base 466 crypto/shash.c base->cra_type = &crypto_shash_type; base 467 crypto/shash.c base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; base 468 crypto/shash.c base->cra_flags |= CRYPTO_ALG_TYPE_SHASH; base 487 crypto/shash.c struct crypto_alg *base = &alg->base; base 494 crypto/shash.c return crypto_register_alg(base); base 500 crypto/shash.c return crypto_unregister_alg(&alg->base); base 532 crypto/shash.c algs[i].base.cra_driver_name, base 533 crypto/shash.c algs[i].base.cra_name, ret); base 564 crypto/shash.c return crypto_init_spawn2(&spawn->base, &alg->base, inst, base 575 crypto/shash.c container_of(alg, struct shash_alg, base); base 54 crypto/simd.c struct crypto_skcipher *child = &ctx->cryptd_tfm->base; base 78 crypto/simd.c child = &ctx->cryptd_tfm->base; base 99 crypto/simd.c child = &ctx->cryptd_tfm->base; base 135 crypto/simd.c reqsize = max(reqsize, crypto_skcipher_reqsize(&cryptd_tfm->base)); base 170 crypto/simd.c if (snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", algname) >= base 174 crypto/simd.c if (snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", base 178 crypto/simd.c alg->base.cra_flags = CRYPTO_ALG_ASYNC; base 179 crypto/simd.c alg->base.cra_priority = ialg->base.cra_priority; base 180 crypto/simd.c alg->base.cra_blocksize = ialg->base.cra_blocksize; base 181 crypto/simd.c alg->base.cra_alignmask = ialg->base.cra_alignmask; base 182 crypto/simd.c alg->base.cra_module = ialg->base.cra_module; base 183 crypto/simd.c alg->base.cra_ctxsize = sizeof(struct simd_skcipher_ctx); base 247 crypto/simd.c WARN_ON(strncmp(algs[i].base.cra_name, "__", 2)); base 248 crypto/simd.c WARN_ON(strncmp(algs[i].base.cra_driver_name, "__", 2)); base 249 crypto/simd.c algname = algs[i].base.cra_name + 2; base 250 crypto/simd.c drvname = algs[i].base.cra_driver_name + 2; base 251 crypto/simd.c basename = algs[i].base.cra_driver_name; base 297 crypto/simd.c struct crypto_aead *child = &ctx->cryptd_tfm->base; base 312 crypto/simd.c struct crypto_aead *child = &ctx->cryptd_tfm->base; base 329 crypto/simd.c child = &ctx->cryptd_tfm->base; base 350 crypto/simd.c child = &ctx->cryptd_tfm->base; base 385 crypto/simd.c reqsize = max(reqsize, crypto_aead_reqsize(&cryptd_tfm->base)); base 420 crypto/simd.c if (snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", algname) >= base 424 crypto/simd.c if (snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", base 428 crypto/simd.c alg->base.cra_flags = CRYPTO_ALG_ASYNC; base 429 crypto/simd.c alg->base.cra_priority = ialg->base.cra_priority; base 430 crypto/simd.c alg->base.cra_blocksize = ialg->base.cra_blocksize; base 431 crypto/simd.c alg->base.cra_alignmask = ialg->base.cra_alignmask; base 432 crypto/simd.c alg->base.cra_module = ialg->base.cra_module; base 433 crypto/simd.c alg->base.cra_ctxsize = sizeof(struct simd_aead_ctx); base 497 crypto/simd.c WARN_ON(strncmp(algs[i].base.cra_name, "__", 2)); base 498 crypto/simd.c WARN_ON(strncmp(algs[i].base.cra_driver_name, "__", 2)); base 499 crypto/simd.c algname = algs[i].base.cra_name + 2; base 500 crypto/simd.c drvname = algs[i].base.cra_driver_name + 2; base 501 crypto/simd.c basename = algs[i].base.cra_driver_name; base 465 crypto/skcipher.c walk->flags |= req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? base 481 crypto/skcipher.c might_sleep_if(req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP); base 534 crypto/skcipher.c if (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) base 631 crypto/skcipher.c .flags = req->base.flags, base 730 crypto/skcipher.c req->base.complete, req->base.data); base 847 crypto/skcipher.c struct crypto_alg *alg = tfm->base.__crt_alg; base 864 crypto/skcipher.c struct crypto_alg *alg = tfm->base.__crt_alg; base 906 crypto/skcipher.c skcipher->base.exit = crypto_skcipher_exit_tfm; base 917 crypto/skcipher.c container_of(inst, struct skcipher_instance, s.base); base 927 crypto/skcipher.c base); base 945 crypto/skcipher.c base); base 978 crypto/skcipher.c .tfmsize = offsetof(struct crypto_skcipher, base), base 984 crypto/skcipher.c spawn->base.frontend = &crypto_skcipher_type2; base 985 crypto/skcipher.c return crypto_grab_spawn(&spawn->base, name, type, mask); base 1029 crypto/skcipher.c struct crypto_alg *base = &alg->base; base 1036 crypto/skcipher.c alg->chunksize = base->cra_blocksize; base 1040 crypto/skcipher.c base->cra_type = &crypto_skcipher_type2; base 1041 crypto/skcipher.c base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; base 1042 crypto/skcipher.c base->cra_flags |= CRYPTO_ALG_TYPE_SKCIPHER; base 1049 crypto/skcipher.c struct crypto_alg *base = &alg->base; base 1056 crypto/skcipher.c return crypto_register_alg(base); base 1062 crypto/skcipher.c crypto_unregister_alg(&alg->base); base 1215 crypto/skcipher.c inst->alg.base.cra_blocksize = cipher_alg->cra_blocksize; base 1216 crypto/skcipher.c inst->alg.base.cra_alignmask = cipher_alg->cra_alignmask; base 1217 crypto/skcipher.c inst->alg.base.cra_priority = cipher_alg->cra_priority; base 1223 crypto/skcipher.c inst->alg.base.cra_ctxsize = sizeof(struct skcipher_ctx_simple); base 173 crypto/sm3_generic.c .base = { base 1055 crypto/streebog_generic.c .base = { base 1067 crypto/streebog_generic.c .base = { base 141 crypto/tcrypt.c struct crypto_wait *wait = req->base.data; base 708 crypto/tcrypt.c struct crypto_wait *wait = req->base.data; base 1412 crypto/tcrypt.c struct crypto_wait *wait = req->base.data; base 1559 crypto/testmgr.c const char *algname = crypto_hash_alg_common(tfm)->base.cra_name; base 1938 crypto/testmgr.c req->base.complete != crypto_req_done || base 1939 crypto/testmgr.c req->base.flags != req_flags || base 1940 crypto/testmgr.c req->base.data != &wait) { base 1955 crypto/testmgr.c if (req->base.complete != crypto_req_done) base 1957 crypto/testmgr.c if (req->base.flags != req_flags) base 1959 crypto/testmgr.c if (req->base.data != &wait) base 2144 crypto/testmgr.c const char *algname = crypto_aead_alg(tfm)->base.cra_name; base 2526 crypto/testmgr.c req->base.complete != crypto_req_done || base 2527 crypto/testmgr.c req->base.flags != req_flags || base 2528 crypto/testmgr.c req->base.data != &wait) { base 2541 crypto/testmgr.c if (req->base.complete != crypto_req_done) base 2543 crypto/testmgr.c if (req->base.flags != req_flags) base 2545 crypto/testmgr.c if (req->base.data != &wait) base 2711 crypto/testmgr.c const char *algname = crypto_skcipher_alg(tfm)->base.cra_name; base 632 crypto/tgr192.c .base = { base 644 crypto/tgr192.c .base = { base 656 crypto/tgr192.c .base = { base 650 crypto/vmac.c inst->alg.base.cra_priority = alg->cra_priority; base 651 crypto/vmac.c inst->alg.base.cra_blocksize = alg->cra_blocksize; base 652 crypto/vmac.c inst->alg.base.cra_alignmask = alg->cra_alignmask; base 654 crypto/vmac.c inst->alg.base.cra_ctxsize = sizeof(struct vmac_tfm_ctx); base 655 crypto/vmac.c inst->alg.base.cra_init = vmac_init_tfm; base 656 crypto/vmac.c inst->alg.base.cra_exit = vmac_exit_tfm; base 1128 crypto/wp512.c .base = { base 1140 crypto/wp512.c .base = { base 1152 crypto/wp512.c .base = { base 223 crypto/xcbc.c inst->alg.base.cra_alignmask = alignmask; base 224 crypto/xcbc.c inst->alg.base.cra_priority = alg->cra_priority; base 225 crypto/xcbc.c inst->alg.base.cra_blocksize = alg->cra_blocksize; base 234 crypto/xcbc.c inst->alg.base.cra_ctxsize = ALIGN(sizeof(struct xcbc_tfm_ctx), base 237 crypto/xcbc.c inst->alg.base.cra_init = xcbc_init_tfm; base 238 crypto/xcbc.c inst->alg.base.cra_exit = xcbc_exit_tfm; base 186 crypto/xts.c skcipher_request_set_callback(subreq, req->base.flags, cts_done, req); base 208 crypto/xts.c rctx->subreq.base.flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; base 228 crypto/xts.c rctx->subreq.base.flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; base 251 crypto/xts.c skcipher_request_set_callback(subreq, req->base.flags, compl, req); base 386 crypto/xts.c if (alg->base.cra_blocksize != XTS_BLOCK_SIZE) base 393 crypto/xts.c &alg->base); base 398 crypto/xts.c cipher_name = alg->base.cra_name; base 415 crypto/xts.c if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, base 423 crypto/xts.c inst->alg.base.cra_flags = alg->base.cra_flags & CRYPTO_ALG_ASYNC; base 424 crypto/xts.c inst->alg.base.cra_priority = alg->base.cra_priority; base 425 crypto/xts.c inst->alg.base.cra_blocksize = XTS_BLOCK_SIZE; base 426 crypto/xts.c inst->alg.base.cra_alignmask = alg->base.cra_alignmask | base 433 crypto/xts.c inst->alg.base.cra_ctxsize = sizeof(struct priv); base 80 crypto/xxhash_generic.c .base = { base 225 crypto/zstd.c .base = { base 102 drivers/acpi/acpi_apd.c clk_data->base = devm_ioremap(&adev->dev, rentry->res->start, base 20 drivers/acpi/acpica/exconvrt.c acpi_ex_convert_to_ascii(u64 integer, u16 base, u8 *string, u8 max_length); base 260 drivers/acpi/acpica/exconvrt.c acpi_ex_convert_to_ascii(u64 integer, u16 base, u8 *string, u8 data_width) base 273 drivers/acpi/acpica/exconvrt.c switch (base) { base 380 drivers/acpi/acpica/exconvrt.c u16 base = 16; base 403 drivers/acpi/acpica/exconvrt.c base = 10; base 429 drivers/acpi/acpica/exconvrt.c acpi_ex_convert_to_ascii(obj_desc->integer.value, base, base 451 drivers/acpi/acpica/exconvrt.c base = 10; base 521 drivers/acpi/acpica/exconvrt.c if (base == 16) { base 531 drivers/acpi/acpica/exconvrt.c base, new_buf, 1); base 35 drivers/acpi/acpica/exutils.c static u32 acpi_ex_digits_needed(u64 value, u32 base); base 246 drivers/acpi/acpica/exutils.c static u32 acpi_ex_digits_needed(u64 value, u32 base) base 265 drivers/acpi/acpica/exutils.c (void)acpi_ut_short_divide(current_value, base, ¤t_value, base 32 drivers/acpi/acpica/utprint.c u8 base, s32 width, s32 precision, u8 type); base 34 drivers/acpi/acpica/utprint.c static char *acpi_ut_put_number(char *string, u64 number, u8 base, u8 upper); base 104 drivers/acpi/acpica/utprint.c static char *acpi_ut_put_number(char *string, u64 number, u8 base, u8 upper) base 117 drivers/acpi/acpica/utprint.c (void)acpi_ut_divide(number, base, &number, base 204 drivers/acpi/acpica/utprint.c u8 base, s32 width, s32 precision, u8 type) base 216 drivers/acpi/acpica/utprint.c if (base < 2 || base > 16) { base 225 drivers/acpi/acpica/utprint.c && base != 10) ? TRUE : FALSE; base 247 drivers/acpi/acpica/utprint.c if (base == 16) { base 254 drivers/acpi/acpica/utprint.c pos = acpi_ut_put_number(reversed_string, number, base, upper); base 277 drivers/acpi/acpica/utprint.c if (base == 16) { base 320 drivers/acpi/acpica/utprint.c u8 base; base 344 drivers/acpi/acpica/utprint.c base = 10; base 467 drivers/acpi/acpica/utprint.c base = 8; base 477 drivers/acpi/acpica/utprint.c base = 16; base 537 drivers/acpi/acpica/utprint.c pos = acpi_ut_format_number(pos, end, number, base, base 16 drivers/acpi/acpica/utstrsuppt.c acpi_ut_insert_digit(u64 *accumulated_value, u32 base, int ascii_digit); base 19 drivers/acpi/acpica/utstrsuppt.c acpi_ut_strtoul_multiply64(u64 multiplicand, u32 base, u64 *out_product); base 316 drivers/acpi/acpica/utstrsuppt.c acpi_ut_insert_digit(u64 *accumulated_value, u32 base, int ascii_digit) base 323 drivers/acpi/acpica/utstrsuppt.c status = acpi_ut_strtoul_multiply64(*accumulated_value, base, &product); base 355 drivers/acpi/acpica/utstrsuppt.c acpi_ut_strtoul_multiply64(u64 multiplicand, u32 base, u64 *out_product) base 363 drivers/acpi/acpica/utstrsuppt.c if (!multiplicand || !base) { base 375 drivers/acpi/acpica/utstrsuppt.c acpi_ut_short_divide(ACPI_UINT64_MAX, base, "ient, NULL); base 380 drivers/acpi/acpica/utstrsuppt.c product = multiplicand * base; base 84 drivers/acpi/acpica/utstrtoul64.c u32 base = 10; /* Default is decimal */ base 104 drivers/acpi/acpica/utstrtoul64.c base = 16; base 112 drivers/acpi/acpica/utstrtoul64.c base = 8; base 131 drivers/acpi/acpica/utstrtoul64.c switch (base) { base 290 drivers/acpi/acpica/utstrtoul64.c u32 base = 10; /* Default is decimal */ base 303 drivers/acpi/acpica/utstrtoul64.c base = 16; base 315 drivers/acpi/acpica/utstrtoul64.c switch (base) { base 67 drivers/acpi/apei/erst.c u64 base; base 383 drivers/acpi/apei/erst.c range->base = apei_exec_ctx_get_output(&ctx); base 1150 drivers/acpi/apei/erst.c r = request_mem_region(erst_erange.base, erst_erange.size, "APEI ERST"); base 1153 drivers/acpi/apei/erst.c (unsigned long long)erst_erange.base, base 1154 drivers/acpi/apei/erst.c (unsigned long long)erst_erange.base + erst_erange.size - 1); base 1159 drivers/acpi/apei/erst.c erst_erange.vaddr = ioremap_cache(erst_erange.base, base 1192 drivers/acpi/apei/erst.c release_mem_region(erst_erange.base, erst_erange.size); base 160 drivers/acpi/arm64/iort.c int iort_register_domain_token(int trans_id, phys_addr_t base, base 171 drivers/acpi/arm64/iort.c its_msi_chip->base_addr = base; base 571 drivers/acpi/arm64/iort.c static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base) base 579 drivers/acpi/arm64/iort.c *base = its_msi_chip->base_addr; base 831 drivers/acpi/arm64/iort.c phys_addr_t base; base 833 drivers/acpi/arm64/iort.c if (!iort_find_its_base(its->identifiers[i], &base)) { base 837 drivers/acpi/arm64/iort.c region = iommu_alloc_resv_region(base + SZ_64K, SZ_64K, base 161 drivers/acpi/hmat/hmat.c static u32 hmat_normalize(u16 entry, u64 base, u8 type) base 170 drivers/acpi/hmat/hmat.c else if (base > (UINT_MAX / (entry))) base 177 drivers/acpi/hmat/hmat.c value = entry * base; base 2404 drivers/acpi/nfit/core.c return readl(mmio->addr.base + offset) & STATUS_MASK; base 2429 drivers/acpi/nfit/core.c writeq(cmd, mmio->addr.base + offset); base 2433 drivers/acpi/nfit/core.c readq(mmio->addr.base + offset); base 2578 drivers/acpi/nfit/core.c mmio->addr.base = devm_nvdimm_memremap(dev, nfit_mem->spa_bdw->address, base 2580 drivers/acpi/nfit/core.c if (!mmio->addr.base) { base 2601 drivers/acpi/nfit/core.c mmio->addr.base = devm_nvdimm_ioremap(dev, nfit_mem->spa_dcr->address, base 2603 drivers/acpi/nfit/core.c if (!mmio->addr.base) { base 260 drivers/acpi/nfit/nfit.h void __iomem *base; base 441 drivers/acpi/sysfs.c void __iomem *base; base 446 drivers/acpi/sysfs.c base = acpi_os_map_memory(data_attr->addr, data_attr->attr.size); base 447 drivers/acpi/sysfs.c if (!base) base 449 drivers/acpi/sysfs.c rc = memory_read_from_buffer(buf, count, &offset, base, base 451 drivers/acpi/sysfs.c acpi_os_unmap_memory(base, data_attr->attr.size); base 570 drivers/amba/bus.c resource_size_t base, size_t size, int irq1, int irq2, base 577 drivers/amba/bus.c dev = amba_device_alloc(name, base, size); base 599 drivers/amba/bus.c resource_size_t base, size_t size, int irq1, int irq2, base 602 drivers/amba/bus.c return amba_aphb_device_add(parent, name, base, size, irq1, irq2, pdata, base 609 drivers/amba/bus.c resource_size_t base, size_t size, int irq1, int irq2, base 612 drivers/amba/bus.c return amba_aphb_device_add(parent, name, base, size, irq1, irq2, pdata, base 619 drivers/amba/bus.c resource_size_t base, size_t size, int irq1, base 623 drivers/amba/bus.c return amba_aphb_device_add(parent, name, base, size, irq1, irq2, pdata, base 630 drivers/amba/bus.c resource_size_t base, size_t size, int irq1, base 634 drivers/amba/bus.c return amba_aphb_device_add(parent, name, base, size, irq1, irq2, pdata, base 660 drivers/amba/bus.c struct amba_device *amba_device_alloc(const char *name, resource_size_t base, base 668 drivers/amba/bus.c dev->res.start = base; base 669 drivers/amba/bus.c dev->res.end = base + size - 1; base 53 drivers/ata/ahci_mvebu.c writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i)); base 36 drivers/ata/ahci_octeon.c void __iomem *base; base 41 drivers/ata/ahci_octeon.c base = devm_ioremap_resource(&pdev->dev, res); base 42 drivers/ata/ahci_octeon.c if (IS_ERR(base)) base 43 drivers/ata/ahci_octeon.c return PTR_ERR(base); base 45 drivers/ata/ahci_octeon.c cfg = cvmx_readq_csr(base + CVMX_SATA_UCTL_SHIM_CFG); base 60 drivers/ata/ahci_octeon.c cvmx_writeq_csr(base + CVMX_SATA_UCTL_SHIM_CFG, cfg); base 895 drivers/ata/libata-core.c u8 base; base 923 drivers/ata/libata-core.c return ent->base + highbit - ent->shift; base 944 drivers/ata/libata-core.c if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits) base 945 drivers/ata/libata-core.c return ((2 << (ent->shift + xfer_mode - ent->base)) - 1) base 967 drivers/ata/libata-core.c if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits) base 3368 drivers/ata/libata-core.c base_mode = ent->base; base 1826 drivers/ata/libata-eh.c int base = 0; base 1832 drivers/ata/libata-eh.c base = ATA_ECAT_DUBIOUS_NONE; base 1835 drivers/ata/libata-eh.c return base + ATA_ECAT_ATA_BUS; base 1838 drivers/ata/libata-eh.c return base + ATA_ECAT_TOUT_HSM; base 1842 drivers/ata/libata-eh.c return base + ATA_ECAT_TOUT_HSM; base 1845 drivers/ata/libata-eh.c return base + ATA_ECAT_UNK_DEV; base 2236 drivers/ata/libata-sff.c int base = i * 2; base 2251 drivers/ata/libata-sff.c rc = pcim_iomap_regions(pdev, 0x3 << base, base 2264 drivers/ata/libata-sff.c ap->ioaddr.cmd_addr = iomap[base]; base 2267 drivers/ata/libata-sff.c ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); base 2271 drivers/ata/libata-sff.c (unsigned long long)pci_resource_start(pdev, base), base 2272 drivers/ata/libata-sff.c (unsigned long long)pci_resource_start(pdev, base + 1)); base 67 drivers/ata/pata_bk3710.c static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev, base 82 drivers/ata/pata_bk3710.c val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); base 84 drivers/ata/pata_bk3710.c iowrite32(val32, base + BK3710_UDMASTB); base 87 drivers/ata/pata_bk3710.c val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); base 89 drivers/ata/pata_bk3710.c iowrite32(val32, base + BK3710_UDMATRP); base 92 drivers/ata/pata_bk3710.c val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); base 94 drivers/ata/pata_bk3710.c iowrite32(val32, base + BK3710_UDMAENV); base 97 drivers/ata/pata_bk3710.c val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev); base 98 drivers/ata/pata_bk3710.c iowrite16(val16, base + BK3710_UDMACTL); base 101 drivers/ata/pata_bk3710.c static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev, base 120 drivers/ata/pata_bk3710.c val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8)); base 122 drivers/ata/pata_bk3710.c iowrite32(val32, base + BK3710_DMASTB); base 124 drivers/ata/pata_bk3710.c val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8)); base 126 drivers/ata/pata_bk3710.c iowrite32(val32, base + BK3710_DMARCVR); base 129 drivers/ata/pata_bk3710.c val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev); base 130 drivers/ata/pata_bk3710.c iowrite16(val16, base + BK3710_UDMACTL); base 136 drivers/ata/pata_bk3710.c void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr; base 141 drivers/ata/pata_bk3710.c pata_bk3710_setudmamode(base, is_slave, base 144 drivers/ata/pata_bk3710.c pata_bk3710_setmwdmamode(base, is_slave, base 149 drivers/ata/pata_bk3710.c static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair, base 166 drivers/ata/pata_bk3710.c val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8)); base 168 drivers/ata/pata_bk3710.c iowrite32(val32, base + BK3710_DATSTB); base 170 drivers/ata/pata_bk3710.c val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8)); base 172 drivers/ata/pata_bk3710.c iowrite32(val32, base + BK3710_DATRCVR); base 189 drivers/ata/pata_bk3710.c val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8)); base 191 drivers/ata/pata_bk3710.c iowrite32(val32, base + BK3710_REGSTB); base 193 drivers/ata/pata_bk3710.c val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8)); base 195 drivers/ata/pata_bk3710.c iowrite32(val32, base + BK3710_REGRCVR); base 201 drivers/ata/pata_bk3710.c void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr; base 223 drivers/ata/pata_bk3710.c pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio); base 226 drivers/ata/pata_bk3710.c static void pata_bk3710_chipinit(void __iomem *base) base 245 drivers/ata/pata_bk3710.c iowrite16(BIT(15), base + BK3710_IDETIMP); base 253 drivers/ata/pata_bk3710.c iowrite16(0, base + BK3710_UDMACTL); base 261 drivers/ata/pata_bk3710.c iowrite32(0x001, base + BK3710_MISCCTL); base 267 drivers/ata/pata_bk3710.c iowrite32(0, base + BK3710_IORDYTMP); base 277 drivers/ata/pata_bk3710.c iowrite16(0xE, base + BK3710_BMISP); base 279 drivers/ata/pata_bk3710.c pata_bk3710_setpiomode(base, NULL, 0, 600, 0); base 280 drivers/ata/pata_bk3710.c pata_bk3710_setpiomode(base, NULL, 1, 600, 0); base 297 drivers/ata/pata_bk3710.c void __iomem *base; base 321 drivers/ata/pata_bk3710.c base = devm_ioremap_resource(&pdev->dev, mem); base 322 drivers/ata/pata_bk3710.c if (IS_ERR(base)) base 323 drivers/ata/pata_bk3710.c return PTR_ERR(base); base 326 drivers/ata/pata_bk3710.c pata_bk3710_chipinit(base); base 340 drivers/ata/pata_bk3710.c ap->ioaddr.data_addr = base + BK3710_TF_OFFSET; base 341 drivers/ata/pata_bk3710.c ap->ioaddr.error_addr = base + BK3710_TF_OFFSET + 1; base 342 drivers/ata/pata_bk3710.c ap->ioaddr.feature_addr = base + BK3710_TF_OFFSET + 1; base 343 drivers/ata/pata_bk3710.c ap->ioaddr.nsect_addr = base + BK3710_TF_OFFSET + 2; base 344 drivers/ata/pata_bk3710.c ap->ioaddr.lbal_addr = base + BK3710_TF_OFFSET + 3; base 345 drivers/ata/pata_bk3710.c ap->ioaddr.lbam_addr = base + BK3710_TF_OFFSET + 4; base 346 drivers/ata/pata_bk3710.c ap->ioaddr.lbah_addr = base + BK3710_TF_OFFSET + 5; base 347 drivers/ata/pata_bk3710.c ap->ioaddr.device_addr = base + BK3710_TF_OFFSET + 6; base 348 drivers/ata/pata_bk3710.c ap->ioaddr.status_addr = base + BK3710_TF_OFFSET + 7; base 349 drivers/ata/pata_bk3710.c ap->ioaddr.command_addr = base + BK3710_TF_OFFSET + 7; base 351 drivers/ata/pata_bk3710.c ap->ioaddr.altstatus_addr = base + BK3710_CTL_OFFSET; base 352 drivers/ata/pata_bk3710.c ap->ioaddr.ctl_addr = base + BK3710_CTL_OFFSET; base 354 drivers/ata/pata_bk3710.c ap->ioaddr.bmdma_addr = base; base 357 drivers/ata/pata_bk3710.c (unsigned long)base + BK3710_TF_OFFSET, base 358 drivers/ata/pata_bk3710.c (unsigned long)base + BK3710_CTL_OFFSET); base 203 drivers/ata/pata_buddha.c void __iomem *base, *irqport; base 208 drivers/ata/pata_buddha.c base = buddha_board + buddha_bases[i]; base 213 drivers/ata/pata_buddha.c base = buddha_board + xsurf_bases[i]; base 221 drivers/ata/pata_buddha.c ap->ioaddr.data_addr = base; base 222 drivers/ata/pata_buddha.c ap->ioaddr.error_addr = base + 2 + 1 * 4; base 223 drivers/ata/pata_buddha.c ap->ioaddr.feature_addr = base + 2 + 1 * 4; base 224 drivers/ata/pata_buddha.c ap->ioaddr.nsect_addr = base + 2 + 2 * 4; base 225 drivers/ata/pata_buddha.c ap->ioaddr.lbal_addr = base + 2 + 3 * 4; base 226 drivers/ata/pata_buddha.c ap->ioaddr.lbam_addr = base + 2 + 4 * 4; base 227 drivers/ata/pata_buddha.c ap->ioaddr.lbah_addr = base + 2 + 5 * 4; base 228 drivers/ata/pata_buddha.c ap->ioaddr.device_addr = base + 2 + 6 * 4; base 229 drivers/ata/pata_buddha.c ap->ioaddr.status_addr = base + 2 + 7 * 4; base 230 drivers/ata/pata_buddha.c ap->ioaddr.command_addr = base + 2 + 7 * 4; base 233 drivers/ata/pata_buddha.c ap->ioaddr.altstatus_addr = base + ctl; base 234 drivers/ata/pata_buddha.c ap->ioaddr.ctl_addr = base + ctl; base 281 drivers/ata/pata_cmd64x.c unsigned long base = pci_resource_start(pdev, 4); base 283 drivers/ata/pata_cmd64x.c u8 mrdmode = inb(base + 1); base 298 drivers/ata/pata_cmd64x.c unsigned long base = pci_resource_start(pdev, 4); base 305 drivers/ata/pata_cmd64x.c mrdmode = inb(base + 1); base 307 drivers/ata/pata_cmd64x.c outb(mrdmode | irq_mask, base + 1); base 48 drivers/ata/pata_cs5530.c void __iomem *base = cs5530_port_base(ap); base 53 drivers/ata/pata_cs5530.c tuning = ioread32(base + 0x04); base 58 drivers/ata/pata_cs5530.c base += 0x08; base 60 drivers/ata/pata_cs5530.c iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base); base 75 drivers/ata/pata_cs5530.c void __iomem *base = cs5530_port_base(ap); base 80 drivers/ata/pata_cs5530.c tuning = ioread32(base + 0x04); base 101 drivers/ata/pata_cs5530.c iowrite32(timing, base + 0x04); base 107 drivers/ata/pata_cs5530.c iowrite32(tuning, base + 0x04); base 108 drivers/ata/pata_cs5530.c iowrite32(timing, base + 0x0C); base 142 drivers/ata/pata_ep93xx.c static void ep93xx_pata_clear_regs(void __iomem *base) base 145 drivers/ata/pata_ep93xx.c IDECTRL_DIOWN, base + IDECTRL); base 147 drivers/ata/pata_ep93xx.c writel(0, base + IDECFG); base 148 drivers/ata/pata_ep93xx.c writel(0, base + IDEMDMAOP); base 149 drivers/ata/pata_ep93xx.c writel(0, base + IDEUDMAOP); base 150 drivers/ata/pata_ep93xx.c writel(0, base + IDEDATAOUT); base 151 drivers/ata/pata_ep93xx.c writel(0, base + IDEDATAIN); base 152 drivers/ata/pata_ep93xx.c writel(0, base + IDEMDMADATAOUT); base 153 drivers/ata/pata_ep93xx.c writel(0, base + IDEMDMADATAIN); base 154 drivers/ata/pata_ep93xx.c writel(0, base + IDEUDMADATAOUT); base 155 drivers/ata/pata_ep93xx.c writel(0, base + IDEUDMADATAIN); base 156 drivers/ata/pata_ep93xx.c writel(0, base + IDEUDMADEBUG); base 159 drivers/ata/pata_ep93xx.c static bool ep93xx_pata_check_iordy(void __iomem *base) base 161 drivers/ata/pata_ep93xx.c return !!(readl(base + IDECTRL) & IDECTRL_IORDY); base 192 drivers/ata/pata_ep93xx.c static void ep93xx_pata_enable_pio(void __iomem *base, int pio_mode) base 196 drivers/ata/pata_ep93xx.c (pio_mode << IDECFG_MODE_SHIFT), base + IDECFG); base 218 drivers/ata/pata_ep93xx.c static unsigned long ep93xx_pata_wait_for_iordy(void __iomem *base, base 233 drivers/ata/pata_ep93xx.c while (!ep93xx_pata_check_iordy(base) && counter--) base 239 drivers/ata/pata_ep93xx.c static void ep93xx_pata_rw_begin(void __iomem *base, unsigned long addr, base 242 drivers/ata/pata_ep93xx.c writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL); base 247 drivers/ata/pata_ep93xx.c static void ep93xx_pata_rw_end(void __iomem *base, unsigned long addr, base 254 drivers/ata/pata_ep93xx.c t2 += ep93xx_pata_wait_for_iordy(base, t2); base 255 drivers/ata/pata_ep93xx.c writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL); base 266 drivers/ata/pata_ep93xx.c void __iomem *base = drv_data->ide_base; base 272 drivers/ata/pata_ep93xx.c ep93xx_pata_rw_begin(base, addr, t->setup); base 273 drivers/ata/pata_ep93xx.c writel(IDECTRL_DIOWN | addr, base + IDECTRL); base 278 drivers/ata/pata_ep93xx.c ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i); base 279 drivers/ata/pata_ep93xx.c return readl(base + IDEDATAIN); base 300 drivers/ata/pata_ep93xx.c void __iomem *base = drv_data->ide_base; base 306 drivers/ata/pata_ep93xx.c ep93xx_pata_rw_begin(base, addr, t->setup); base 311 drivers/ata/pata_ep93xx.c writel(value, base + IDEDATAOUT); base 312 drivers/ata/pata_ep93xx.c writel(IDECTRL_DIORN | addr, base + IDECTRL); base 313 drivers/ata/pata_ep93xx.c ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i); base 706 drivers/ata/pata_ep93xx.c void __iomem *base = drv_data->ide_base; base 734 drivers/ata/pata_ep93xx.c writel(v, base + IDEUDMAOP); base 735 drivers/ata/pata_ep93xx.c readl(base + IDEUDMAOP); base 736 drivers/ata/pata_ep93xx.c writel(v | IDEUDMAOP_UEN, base + IDEUDMAOP); base 740 drivers/ata/pata_ep93xx.c base + IDECFG); base 746 drivers/ata/pata_ep93xx.c void __iomem *base = drv_data->ide_base; base 756 drivers/ata/pata_ep93xx.c writel(0, base + IDEUDMAOP); base 757 drivers/ata/pata_ep93xx.c writel(readl(base + IDECTRL) | IDECTRL_DIOWN | IDECTRL_DIORN | base 758 drivers/ata/pata_ep93xx.c IDECTRL_CS0N | IDECTRL_CS1N, base + IDECTRL); base 128 drivers/ata/pata_falcon.c void __iomem *base; base 155 drivers/ata/pata_falcon.c base = (void __iomem *)ATA_HD_BASE; base 156 drivers/ata/pata_falcon.c ap->ioaddr.data_addr = base; base 157 drivers/ata/pata_falcon.c ap->ioaddr.error_addr = base + 1 + 1 * 4; base 158 drivers/ata/pata_falcon.c ap->ioaddr.feature_addr = base + 1 + 1 * 4; base 159 drivers/ata/pata_falcon.c ap->ioaddr.nsect_addr = base + 1 + 2 * 4; base 160 drivers/ata/pata_falcon.c ap->ioaddr.lbal_addr = base + 1 + 3 * 4; base 161 drivers/ata/pata_falcon.c ap->ioaddr.lbam_addr = base + 1 + 4 * 4; base 162 drivers/ata/pata_falcon.c ap->ioaddr.lbah_addr = base + 1 + 5 * 4; base 163 drivers/ata/pata_falcon.c ap->ioaddr.device_addr = base + 1 + 6 * 4; base 164 drivers/ata/pata_falcon.c ap->ioaddr.status_addr = base + 1 + 7 * 4; base 165 drivers/ata/pata_falcon.c ap->ioaddr.command_addr = base + 1 + 7 * 4; base 167 drivers/ata/pata_falcon.c ap->ioaddr.altstatus_addr = base + ATA_HD_CONTROL; base 168 drivers/ata/pata_falcon.c ap->ioaddr.ctl_addr = base + ATA_HD_CONTROL; base 170 drivers/ata/pata_falcon.c ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", (unsigned long)base, base 171 drivers/ata/pata_falcon.c (unsigned long)base + ATA_HD_CONTROL); base 44 drivers/ata/pata_ftide010.c void __iomem *base; base 161 drivers/ata/pata_ftide010.c clkreg = readb(ftide->base + FTIDE010_CLK_MOD); base 187 drivers/ata/pata_ftide010.c writeb(clkreg, ftide->base + FTIDE010_CLK_MOD); base 188 drivers/ata/pata_ftide010.c writeb(timreg, ftide->base + FTIDE010_UDMA_TIMING0 + devno); base 206 drivers/ata/pata_ftide010.c writeb(clkreg, ftide->base + FTIDE010_CLK_MOD); base 207 drivers/ata/pata_ftide010.c writeb(timreg, ftide->base + FTIDE010_MWDMA_TIMING); base 228 drivers/ata/pata_ftide010.c ftide->base + FTIDE010_PIO_TIMING); base 477 drivers/ata/pata_ftide010.c ftide->base = devm_ioremap_resource(dev, res); base 478 drivers/ata/pata_ftide010.c if (IS_ERR(ftide->base)) base 479 drivers/ata/pata_ftide010.c return PTR_ERR(ftide->base); base 521 drivers/ata/pata_ftide010.c ioaddr->bmdma_addr = ftide->base + FTIDE010_DMA_REG; base 522 drivers/ata/pata_ftide010.c ioaddr->cmd_addr = ftide->base + FTIDE010_CMD_DATA; base 523 drivers/ata/pata_ftide010.c ioaddr->ctl_addr = ftide->base + FTIDE010_ALTSTAT_CTRL; base 524 drivers/ata/pata_ftide010.c ioaddr->altstatus_addr = ftide->base + FTIDE010_ALTSTAT_CTRL; base 529 drivers/ata/pata_ftide010.c readl(ftide->base + FTIDE010_IDE_DEVICE_ID), irq, res); base 134 drivers/ata/pata_gayle.c void __iomem *base; base 167 drivers/ata/pata_gayle.c base = ZTWO_VADDR(pdata->base); base 168 drivers/ata/pata_gayle.c ap->ioaddr.data_addr = base; base 169 drivers/ata/pata_gayle.c ap->ioaddr.error_addr = base + 2 + 1 * 4; base 170 drivers/ata/pata_gayle.c ap->ioaddr.feature_addr = base + 2 + 1 * 4; base 171 drivers/ata/pata_gayle.c ap->ioaddr.nsect_addr = base + 2 + 2 * 4; base 172 drivers/ata/pata_gayle.c ap->ioaddr.lbal_addr = base + 2 + 3 * 4; base 173 drivers/ata/pata_gayle.c ap->ioaddr.lbam_addr = base + 2 + 4 * 4; base 174 drivers/ata/pata_gayle.c ap->ioaddr.lbah_addr = base + 2 + 5 * 4; base 175 drivers/ata/pata_gayle.c ap->ioaddr.device_addr = base + 2 + 6 * 4; base 176 drivers/ata/pata_gayle.c ap->ioaddr.status_addr = base + 2 + 7 * 4; base 177 drivers/ata/pata_gayle.c ap->ioaddr.command_addr = base + 2 + 7 * 4; base 179 drivers/ata/pata_gayle.c ap->ioaddr.altstatus_addr = base + GAYLE_CONTROL; base 180 drivers/ata/pata_gayle.c ap->ioaddr.ctl_addr = base + GAYLE_CONTROL; base 184 drivers/ata/pata_gayle.c ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", pdata->base, base 185 drivers/ata/pata_gayle.c pdata->base + GAYLE_CONTROL); base 38 drivers/ata/pata_hpt37x.c unsigned int base; base 655 drivers/ata/pata_hpt37x.c static int hpt37x_clock_slot(unsigned int freq, unsigned int base) base 657 drivers/ata/pata_hpt37x.c unsigned int f = (base * freq) / 192; /* Mhz */ base 971 drivers/ata/pata_hpt37x.c clock_slot = hpt37x_clock_slot(freq, chip_table->base); base 203 drivers/ata/pata_hpt3x3.c void __iomem *base; base 228 drivers/ata/pata_hpt3x3.c base = host->iomap[4]; /* Bus mastering base */ base 234 drivers/ata/pata_hpt3x3.c ioaddr->cmd_addr = base + offset_cmd[i]; base 236 drivers/ata/pata_hpt3x3.c ioaddr->ctl_addr = base + offset_ctl[i]; base 239 drivers/ata/pata_hpt3x3.c ioaddr->bmdma_addr = base + 8 * i; base 65 drivers/ata/pata_icside.c void __iomem *base; base 116 drivers/ata/pata_icside.c void __iomem *base = state->irq_port; base 119 drivers/ata/pata_icside.c writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); base 121 drivers/ata/pata_icside.c writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); base 341 drivers/ata/pata_icside.c static void pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base, base 346 drivers/ata/pata_icside.c void __iomem *cmd = base + port->dataoffset; base 360 drivers/ata/pata_icside.c ioaddr->ctl_addr = base + port->ctrloffset; base 374 drivers/ata/pata_icside.c void __iomem *base; base 376 drivers/ata/pata_icside.c base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0); base 377 drivers/ata/pata_icside.c if (!base) base 380 drivers/ata/pata_icside.c state->irq_port = base; base 382 drivers/ata/pata_icside.c info->base = base; base 383 drivers/ata/pata_icside.c info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; base 425 drivers/ata/pata_icside.c info->base = easi_base; base 470 drivers/ata/pata_icside.c pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]); base 985 drivers/ata/pata_macio.c void __iomem * base, void __iomem * dma) base 988 drivers/ata/pata_macio.c ioaddr->cmd_addr = base; base 991 drivers/ata/pata_macio.c ioaddr->data_addr = base + (ATA_REG_DATA << 4); base 992 drivers/ata/pata_macio.c ioaddr->error_addr = base + (ATA_REG_ERR << 4); base 993 drivers/ata/pata_macio.c ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4); base 994 drivers/ata/pata_macio.c ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4); base 995 drivers/ata/pata_macio.c ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4); base 996 drivers/ata/pata_macio.c ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4); base 997 drivers/ata/pata_macio.c ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4); base 998 drivers/ata/pata_macio.c ioaddr->device_addr = base + (ATA_REG_DEVICE << 4); base 999 drivers/ata/pata_macio.c ioaddr->status_addr = base + (ATA_REG_STATUS << 4); base 1000 drivers/ata/pata_macio.c ioaddr->command_addr = base + (ATA_REG_CMD << 4); base 1001 drivers/ata/pata_macio.c ioaddr->altstatus_addr = base + 0x160; base 1002 drivers/ata/pata_macio.c ioaddr->ctl_addr = base + 0x160; base 92 drivers/ata/pata_ninja32.c static void ninja32_program(void __iomem *base) base 94 drivers/ata/pata_ninja32.c iowrite8(0x05, base + 0x01); /* Enable interrupt lines */ base 95 drivers/ata/pata_ninja32.c iowrite8(0xBE, base + 0x02); /* Burst, ?? setup */ base 96 drivers/ata/pata_ninja32.c iowrite8(0x01, base + 0x03); /* Unknown */ base 97 drivers/ata/pata_ninja32.c iowrite8(0x20, base + 0x04); /* WAIT0 */ base 98 drivers/ata/pata_ninja32.c iowrite8(0x8f, base + 0x05); /* Unknown */ base 99 drivers/ata/pata_ninja32.c iowrite8(0xa4, base + 0x1c); /* Unknown */ base 100 drivers/ata/pata_ninja32.c iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */ base 107 drivers/ata/pata_ninja32.c void __iomem *base; base 133 drivers/ata/pata_ninja32.c base = host->iomap[0]; base 134 drivers/ata/pata_ninja32.c if (!base) base 140 drivers/ata/pata_ninja32.c ap->ioaddr.cmd_addr = base + 0x10; base 141 drivers/ata/pata_ninja32.c ap->ioaddr.ctl_addr = base + 0x1E; base 142 drivers/ata/pata_ninja32.c ap->ioaddr.altstatus_addr = base + 0x1E; base 143 drivers/ata/pata_ninja32.c ap->ioaddr.bmdma_addr = base; base 147 drivers/ata/pata_ninja32.c ninja32_program(base); base 386 drivers/ata/pata_octeon_cf.c void __iomem *base = ap->ioaddr.data_addr; base 388 drivers/ata/pata_octeon_cf.c blob = __raw_readw(base + 0xc); base 391 drivers/ata/pata_octeon_cf.c blob = __raw_readw(base + 2); base 395 drivers/ata/pata_octeon_cf.c blob = __raw_readw(base + 4); base 399 drivers/ata/pata_octeon_cf.c blob = __raw_readw(base + 6); base 407 drivers/ata/pata_octeon_cf.c blob = __raw_readw(base + 0xc); base 410 drivers/ata/pata_octeon_cf.c blob = __raw_readw(base + 2); base 414 drivers/ata/pata_octeon_cf.c blob = __raw_readw(base + 4); base 429 drivers/ata/pata_octeon_cf.c void __iomem *base = ap->ioaddr.data_addr; base 431 drivers/ata/pata_octeon_cf.c blob = __raw_readw(base + 6); base 439 drivers/ata/pata_octeon_cf.c void __iomem *base = ap->ioaddr.data_addr; base 444 drivers/ata/pata_octeon_cf.c __raw_writew(ap->ctl, base + 0xe); base 446 drivers/ata/pata_octeon_cf.c __raw_writew(ap->ctl | ATA_SRST, base + 0xe); base 448 drivers/ata/pata_octeon_cf.c __raw_writew(ap->ctl, base + 0xe); base 471 drivers/ata/pata_octeon_cf.c void __iomem *base = ap->ioaddr.data_addr; base 479 drivers/ata/pata_octeon_cf.c __raw_writew(tf->hob_feature << 8, base + 0xc); base 480 drivers/ata/pata_octeon_cf.c __raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2); base 481 drivers/ata/pata_octeon_cf.c __raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4); base 490 drivers/ata/pata_octeon_cf.c __raw_writew(tf->feature << 8, base + 0xc); base 491 drivers/ata/pata_octeon_cf.c __raw_writew(tf->nsect | tf->lbal << 8, base + 2); base 492 drivers/ata/pata_octeon_cf.c __raw_writew(tf->lbam | tf->lbah << 8, base + 4); base 518 drivers/ata/pata_octeon_cf.c void __iomem *base = ap->ioaddr.data_addr; base 530 drivers/ata/pata_octeon_cf.c __raw_writew(blob, base + 6); base 849 drivers/ata/pata_octeon_cf.c void __iomem *base; base 947 drivers/ata/pata_octeon_cf.c base = cs0 + 0x800; base 948 drivers/ata/pata_octeon_cf.c ap->ioaddr.cmd_addr = base; base 951 drivers/ata/pata_octeon_cf.c ap->ioaddr.altstatus_addr = base + 0xe; base 952 drivers/ata/pata_octeon_cf.c ap->ioaddr.ctl_addr = base + 0xe; base 955 drivers/ata/pata_octeon_cf.c base = cs0; base 956 drivers/ata/pata_octeon_cf.c ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1; base 957 drivers/ata/pata_octeon_cf.c ap->ioaddr.data_addr = base + (ATA_REG_DATA << 1); base 958 drivers/ata/pata_octeon_cf.c ap->ioaddr.error_addr = base + (ATA_REG_ERR << 1) + 1; base 959 drivers/ata/pata_octeon_cf.c ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1; base 960 drivers/ata/pata_octeon_cf.c ap->ioaddr.nsect_addr = base + (ATA_REG_NSECT << 1) + 1; base 961 drivers/ata/pata_octeon_cf.c ap->ioaddr.lbal_addr = base + (ATA_REG_LBAL << 1) + 1; base 962 drivers/ata/pata_octeon_cf.c ap->ioaddr.lbam_addr = base + (ATA_REG_LBAM << 1) + 1; base 963 drivers/ata/pata_octeon_cf.c ap->ioaddr.lbah_addr = base + (ATA_REG_LBAH << 1) + 1; base 964 drivers/ata/pata_octeon_cf.c ap->ioaddr.device_addr = base + (ATA_REG_DEVICE << 1) + 1; base 965 drivers/ata/pata_octeon_cf.c ap->ioaddr.status_addr = base + (ATA_REG_STATUS << 1) + 1; base 966 drivers/ata/pata_octeon_cf.c ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1; base 979 drivers/ata/pata_octeon_cf.c base = cs0 + 0x800; base 987 drivers/ata/pata_octeon_cf.c ap->ioaddr.data_addr = base + ATA_REG_DATA; base 988 drivers/ata/pata_octeon_cf.c ap->ioaddr.nsect_addr = base + ATA_REG_NSECT; base 989 drivers/ata/pata_octeon_cf.c ap->ioaddr.lbal_addr = base + ATA_REG_LBAL; base 990 drivers/ata/pata_octeon_cf.c ap->ioaddr.ctl_addr = base + 0xe; base 991 drivers/ata/pata_octeon_cf.c ap->ioaddr.altstatus_addr = base + 0xe; base 999 drivers/ata/pata_octeon_cf.c ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr); base 669 drivers/ata/pata_pdc2027x.c static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base) base 672 drivers/ata/pata_pdc2027x.c port->data_addr = base; base 674 drivers/ata/pata_pdc2027x.c port->error_addr = base + 0x05; base 675 drivers/ata/pata_pdc2027x.c port->nsect_addr = base + 0x0a; base 676 drivers/ata/pata_pdc2027x.c port->lbal_addr = base + 0x0f; base 677 drivers/ata/pata_pdc2027x.c port->lbam_addr = base + 0x10; base 678 drivers/ata/pata_pdc2027x.c port->lbah_addr = base + 0x15; base 679 drivers/ata/pata_pdc2027x.c port->device_addr = base + 0x1a; base 681 drivers/ata/pata_pdc2027x.c port->status_addr = base + 0x1f; base 683 drivers/ata/pata_pdc2027x.c port->ctl_addr = base + 0x81a; base 52 drivers/ata/pata_sil680.c unsigned long base = 0xA0 + r; base 53 drivers/ata/pata_sil680.c base += (ap->port_no << 4); base 54 drivers/ata/pata_sil680.c return base; base 69 drivers/ata/pata_sil680.c unsigned long base = 0xA0 + r; base 70 drivers/ata/pata_sil680.c base += (ap->port_no << 4); base 71 drivers/ata/pata_sil680.c base |= adev->devno ? 2 : 0; base 72 drivers/ata/pata_sil680.c return base; base 34 drivers/ata/pdc_adma.c #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40)) base 37 drivers/ata/pdc_adma.c #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20)) base 517 drivers/ata/pdc_adma.c static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base) base 520 drivers/ata/pdc_adma.c port->data_addr = base + 0x000; base 522 drivers/ata/pdc_adma.c port->feature_addr = base + 0x004; base 523 drivers/ata/pdc_adma.c port->nsect_addr = base + 0x008; base 524 drivers/ata/pdc_adma.c port->lbal_addr = base + 0x00c; base 525 drivers/ata/pdc_adma.c port->lbam_addr = base + 0x010; base 526 drivers/ata/pdc_adma.c port->lbah_addr = base + 0x014; base 527 drivers/ata/pdc_adma.c port->device_addr = base + 0x018; base 529 drivers/ata/pdc_adma.c port->command_addr = base + 0x01c; base 531 drivers/ata/pdc_adma.c port->ctl_addr = base + 0x038; base 829 drivers/ata/sata_dwc_460ex.c static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base) base 831 drivers/ata/sata_dwc_460ex.c port->cmd_addr = base + 0x00; base 832 drivers/ata/sata_dwc_460ex.c port->data_addr = base + 0x00; base 834 drivers/ata/sata_dwc_460ex.c port->error_addr = base + 0x04; base 835 drivers/ata/sata_dwc_460ex.c port->feature_addr = base + 0x04; base 837 drivers/ata/sata_dwc_460ex.c port->nsect_addr = base + 0x08; base 839 drivers/ata/sata_dwc_460ex.c port->lbal_addr = base + 0x0c; base 840 drivers/ata/sata_dwc_460ex.c port->lbam_addr = base + 0x10; base 841 drivers/ata/sata_dwc_460ex.c port->lbah_addr = base + 0x14; base 843 drivers/ata/sata_dwc_460ex.c port->device_addr = base + 0x18; base 844 drivers/ata/sata_dwc_460ex.c port->command_addr = base + 0x1c; base 845 drivers/ata/sata_dwc_460ex.c port->status_addr = base + 0x1c; base 847 drivers/ata/sata_dwc_460ex.c port->altstatus_addr = base + 0x20; base 848 drivers/ata/sata_dwc_460ex.c port->ctl_addr = base + 0x20; base 1203 drivers/ata/sata_dwc_460ex.c void __iomem *base; base 1222 drivers/ata/sata_dwc_460ex.c base = devm_ioremap_resource(&ofdev->dev, res); base 1223 drivers/ata/sata_dwc_460ex.c if (IS_ERR(base)) base 1224 drivers/ata/sata_dwc_460ex.c return PTR_ERR(base); base 1228 drivers/ata/sata_dwc_460ex.c hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET; base 1232 drivers/ata/sata_dwc_460ex.c host->ports[0]->ioaddr.cmd_addr = base; base 1233 drivers/ata/sata_dwc_460ex.c host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET; base 1234 drivers/ata/sata_dwc_460ex.c sata_dwc_setup_port(&host->ports[0]->ioaddr, base); base 38 drivers/ata/sata_gemini.c void __iomem *base; base 163 drivers/ata/sata_gemini.c writel(val, sg->base + GEMINI_SATA0_CTRL); base 169 drivers/ata/sata_gemini.c writel(val, sg->base + GEMINI_SATA1_CTRL); base 180 drivers/ata/sata_gemini.c val = readl(sg->base + GEMINI_SATA0_STATUS); base 182 drivers/ata/sata_gemini.c val = readl(sg->base + GEMINI_SATA1_STATUS); base 281 drivers/ata/sata_gemini.c sata_id = readl(sg->base + GEMINI_SATA_ID); base 282 drivers/ata/sata_gemini.c sata_phy_id = readl(sg->base + GEMINI_SATA_PHY_ID); base 336 drivers/ata/sata_gemini.c sg->base = devm_ioremap_resource(dev, res); base 337 drivers/ata/sata_gemini.c if (IS_ERR(sg->base)) base 338 drivers/ata/sata_gemini.c return PTR_ERR(sg->base); base 544 drivers/ata/sata_mv.c void __iomem *base; base 890 drivers/ata/sata_mv.c static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) base 892 drivers/ata/sata_mv.c return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); base 895 drivers/ata/sata_mv.c static inline void __iomem *mv_hc_base_from_port(void __iomem *base, base 898 drivers/ata/sata_mv.c return mv_hc_base(base, mv_hc_from_port(port)); base 901 drivers/ata/sata_mv.c static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) base 903 drivers/ata/sata_mv.c return mv_hc_base_from_port(base, port) + base 919 drivers/ata/sata_mv.c return hpriv->base; base 1091 drivers/ata/sata_mv.c void __iomem *mmio = hpriv->base, *hc_mmio; base 1513 drivers/ata/sata_mv.c old = readl(hpriv->base + GPIO_PORT_CTL); base 1519 drivers/ata/sata_mv.c writel(new, hpriv->base + GPIO_PORT_CTL); base 2884 drivers/ata/sata_mv.c void __iomem *mmio = hpriv->base, *hc_mmio; base 3022 drivers/ata/sata_mv.c handled = mv_pci_error(host, hpriv->base); base 3056 drivers/ata/sata_mv.c void __iomem *mmio = hpriv->base; base 3070 drivers/ata/sata_mv.c void __iomem *mmio = hpriv->base; base 3540 drivers/ata/sata_mv.c void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); base 3623 drivers/ata/sata_mv.c void __iomem *mmio = hpriv->base; base 3668 drivers/ata/sata_mv.c void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); base 3730 drivers/ata/sata_mv.c void __iomem *mmio = hpriv->base; base 3744 drivers/ata/sata_mv.c void __iomem *mmio = hpriv->base; base 3758 drivers/ata/sata_mv.c void __iomem *mmio = hpriv->base; base 3925 drivers/ata/sata_mv.c void __iomem *mmio = hpriv->base; base 4023 drivers/ata/sata_mv.c writel(0, hpriv->base + WINDOW_CTRL(i)); base 4024 drivers/ata/sata_mv.c writel(0, hpriv->base + WINDOW_BASE(i)); base 4033 drivers/ata/sata_mv.c hpriv->base + WINDOW_CTRL(i)); base 4034 drivers/ata/sata_mv.c writel(cs->base, hpriv->base + WINDOW_BASE(i)); base 4118 drivers/ata/sata_mv.c hpriv->base = devm_ioremap(&pdev->dev, res->start, base 4120 drivers/ata/sata_mv.c if (!hpriv->base) base 4123 drivers/ata/sata_mv.c hpriv->base -= SATAHC0_REG_BASE; base 4399 drivers/ata/sata_mv.c hpriv->base = host->iomap[MV_PRIMARY_BAR]; base 4413 drivers/ata/sata_mv.c void __iomem *port_mmio = mv_port_base(hpriv->base, port); base 4414 drivers/ata/sata_mv.c unsigned int offset = port_mmio - hpriv->base; base 2322 drivers/ata/sata_nv.c void __iomem *base; base 2365 drivers/ata/sata_nv.c base = host->iomap[NV_MMIO_BAR]; base 2366 drivers/ata/sata_nv.c host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET; base 2367 drivers/ata/sata_nv.c host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET; base 1094 drivers/ata/sata_promise.c void __iomem *base, void __iomem *scr_addr) base 1096 drivers/ata/sata_promise.c ap->ioaddr.cmd_addr = base; base 1097 drivers/ata/sata_promise.c ap->ioaddr.data_addr = base; base 1099 drivers/ata/sata_promise.c ap->ioaddr.error_addr = base + 0x4; base 1100 drivers/ata/sata_promise.c ap->ioaddr.nsect_addr = base + 0x8; base 1101 drivers/ata/sata_promise.c ap->ioaddr.lbal_addr = base + 0xc; base 1102 drivers/ata/sata_promise.c ap->ioaddr.lbam_addr = base + 0x10; base 1103 drivers/ata/sata_promise.c ap->ioaddr.lbah_addr = base + 0x14; base 1104 drivers/ata/sata_promise.c ap->ioaddr.device_addr = base + 0x18; base 1106 drivers/ata/sata_promise.c ap->ioaddr.status_addr = base + 0x1c; base 1108 drivers/ata/sata_promise.c ap->ioaddr.ctl_addr = base + 0x38; base 447 drivers/ata/sata_qstor.c static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base) base 450 drivers/ata/sata_qstor.c port->data_addr = base + 0x400; base 452 drivers/ata/sata_qstor.c port->feature_addr = base + 0x408; /* hob_feature = 0x409 */ base 453 drivers/ata/sata_qstor.c port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */ base 454 drivers/ata/sata_qstor.c port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */ base 455 drivers/ata/sata_qstor.c port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */ base 456 drivers/ata/sata_qstor.c port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */ base 457 drivers/ata/sata_qstor.c port->device_addr = base + 0x430; base 459 drivers/ata/sata_qstor.c port->command_addr = base + 0x438; base 461 drivers/ata/sata_qstor.c port->ctl_addr = base + 0x440; base 462 drivers/ata/sata_qstor.c port->scr_addr = base + 0xc00; base 152 drivers/ata/sata_rcar.c void __iomem *base; base 159 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 162 drivers/ata/sata_rcar.c iowrite32(0, base + SATAPHYADDR_REG); base 164 drivers/ata/sata_rcar.c iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); base 167 drivers/ata/sata_rcar.c iowrite32(0, base + SATAPHYRESET_REG); base 173 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 177 drivers/ata/sata_rcar.c iowrite32(0, base + SATAPHYRESET_REG); base 179 drivers/ata/sata_rcar.c iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); base 181 drivers/ata/sata_rcar.c iowrite32(val, base + SATAPHYWDATA_REG); base 186 drivers/ata/sata_rcar.c iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); base 189 drivers/ata/sata_rcar.c val = ioread32(base + SATAPHYACK_REG); base 196 drivers/ata/sata_rcar.c iowrite32(0, base + SATAPHYADDR_REG); base 212 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 214 drivers/ata/sata_rcar.c iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG); base 215 drivers/ata/sata_rcar.c iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG); base 216 drivers/ata/sata_rcar.c iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG); base 217 drivers/ata/sata_rcar.c iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG); base 219 drivers/ata/sata_rcar.c RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG); base 227 drivers/ata/sata_rcar.c iowrite32(priv->sataint_mask, priv->base + SATAINTMASK_REG); base 235 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 238 drivers/ata/sata_rcar.c iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); base 243 drivers/ata/sata_rcar.c iowrite32(priv->sataint_mask & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG); base 566 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 571 drivers/ata/sata_rcar.c iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG); base 574 drivers/ata/sata_rcar.c dmactl = ioread32(base + ATAPI_CONTROL1_REG); base 582 drivers/ata/sata_rcar.c iowrite32(dmactl, base + ATAPI_CONTROL1_REG); base 592 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 596 drivers/ata/sata_rcar.c dmactl = ioread32(base + ATAPI_CONTROL1_REG); base 599 drivers/ata/sata_rcar.c iowrite32(dmactl, base + ATAPI_CONTROL1_REG); base 606 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 610 drivers/ata/sata_rcar.c dmactl = ioread32(base + ATAPI_CONTROL1_REG); base 614 drivers/ata/sata_rcar.c iowrite32(dmactl, base + ATAPI_CONTROL1_REG); base 627 drivers/ata/sata_rcar.c status = ioread32(priv->base + ATAPI_STATUS_REG); base 682 drivers/ata/sata_rcar.c serror = ioread32(priv->base + SCRSERR_REG); base 724 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 732 drivers/ata/sata_rcar.c sataintstat = ioread32(base + SATAINTSTAT_REG); base 737 drivers/ata/sata_rcar.c iowrite32(~sataintstat & priv->sataint_mask, base + SATAINTSTAT_REG); base 759 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 769 drivers/ata/sata_rcar.c ioaddr->cmd_addr = base + SDATA_REG; base 770 drivers/ata/sata_rcar.c ioaddr->ctl_addr = base + SSDEVCON_REG; base 771 drivers/ata/sata_rcar.c ioaddr->scr_addr = base + SCRSSTS_REG; base 788 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 792 drivers/ata/sata_rcar.c val = ioread32(base + ATAPI_CONTROL1_REG); base 794 drivers/ata/sata_rcar.c iowrite32(val, base + ATAPI_CONTROL1_REG); base 797 drivers/ata/sata_rcar.c val = ioread32(base + ATAPI_CONTROL1_REG); base 801 drivers/ata/sata_rcar.c iowrite32(val, base + ATAPI_CONTROL1_REG); base 804 drivers/ata/sata_rcar.c val = ioread32(base + ATAPI_CONTROL1_REG); base 806 drivers/ata/sata_rcar.c iowrite32(val, base + ATAPI_CONTROL1_REG); base 809 drivers/ata/sata_rcar.c iowrite32(0, base + SATAINTSTAT_REG); base 810 drivers/ata/sata_rcar.c iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); base 813 drivers/ata/sata_rcar.c iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); base 919 drivers/ata/sata_rcar.c priv->base = devm_ioremap_resource(dev, mem); base 920 drivers/ata/sata_rcar.c if (IS_ERR(priv->base)) { base 921 drivers/ata/sata_rcar.c ret = PTR_ERR(priv->base); base 947 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 952 drivers/ata/sata_rcar.c iowrite32(0, base + ATAPI_INT_ENABLE_REG); base 954 drivers/ata/sata_rcar.c iowrite32(0, base + SATAINTSTAT_REG); base 955 drivers/ata/sata_rcar.c iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); base 968 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 974 drivers/ata/sata_rcar.c iowrite32(0, base + ATAPI_INT_ENABLE_REG); base 976 drivers/ata/sata_rcar.c iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); base 988 drivers/ata/sata_rcar.c void __iomem *base = priv->base; base 999 drivers/ata/sata_rcar.c iowrite32(0, base + SATAINTSTAT_REG); base 1000 drivers/ata/sata_rcar.c iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); base 1004 drivers/ata/sata_rcar.c base + ATAPI_INT_ENABLE_REG); base 154 drivers/ata/sata_sis.c void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10; base 162 drivers/ata/sata_sis.c *val = ioread32(base + sc_reg * 4); base 169 drivers/ata/sata_sis.c void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10; base 177 drivers/ata/sata_sis.c iowrite32(val, base + (sc_reg * 4)); base 389 drivers/ata/sata_svw.c static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) base 391 drivers/ata/sata_svw.c port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; base 392 drivers/ata/sata_svw.c port->data_addr = base + K2_SATA_TF_DATA_OFFSET; base 394 drivers/ata/sata_svw.c port->error_addr = base + K2_SATA_TF_ERROR_OFFSET; base 395 drivers/ata/sata_svw.c port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET; base 396 drivers/ata/sata_svw.c port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET; base 397 drivers/ata/sata_svw.c port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET; base 398 drivers/ata/sata_svw.c port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET; base 399 drivers/ata/sata_svw.c port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET; base 401 drivers/ata/sata_svw.c port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET; base 403 drivers/ata/sata_svw.c port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET; base 404 drivers/ata/sata_svw.c port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET; base 405 drivers/ata/sata_svw.c port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET; base 962 drivers/ata/sata_sx4.c static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base) base 964 drivers/ata/sata_sx4.c port->cmd_addr = base; base 965 drivers/ata/sata_sx4.c port->data_addr = base; base 967 drivers/ata/sata_sx4.c port->error_addr = base + 0x4; base 968 drivers/ata/sata_sx4.c port->nsect_addr = base + 0x8; base 969 drivers/ata/sata_sx4.c port->lbal_addr = base + 0xc; base 970 drivers/ata/sata_sx4.c port->lbam_addr = base + 0x10; base 971 drivers/ata/sata_sx4.c port->lbah_addr = base + 0x14; base 972 drivers/ata/sata_sx4.c port->device_addr = base + 0x18; base 974 drivers/ata/sata_sx4.c port->status_addr = base + 0x1c; base 976 drivers/ata/sata_sx4.c port->ctl_addr = base + 0x38; base 1462 drivers/ata/sata_sx4.c void __iomem *base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS; base 1465 drivers/ata/sata_sx4.c pdc_sata_setup_port(&ap->ioaddr, base + offset); base 298 drivers/ata/sata_vsc.c static void vsc_sata_setup_port(struct ata_ioports *port, void __iomem *base) base 300 drivers/ata/sata_vsc.c port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET; base 301 drivers/ata/sata_vsc.c port->data_addr = base + VSC_SATA_TF_DATA_OFFSET; base 302 drivers/ata/sata_vsc.c port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET; base 303 drivers/ata/sata_vsc.c port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET; base 304 drivers/ata/sata_vsc.c port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET; base 305 drivers/ata/sata_vsc.c port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET; base 306 drivers/ata/sata_vsc.c port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET; base 307 drivers/ata/sata_vsc.c port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET; base 308 drivers/ata/sata_vsc.c port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET; base 309 drivers/ata/sata_vsc.c port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET; base 310 drivers/ata/sata_vsc.c port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET; base 311 drivers/ata/sata_vsc.c port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET; base 312 drivers/ata/sata_vsc.c port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET; base 313 drivers/ata/sata_vsc.c port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET; base 314 drivers/ata/sata_vsc.c port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET; base 315 drivers/ata/sata_vsc.c writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET); base 316 drivers/ata/sata_vsc.c writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET); base 1691 drivers/atm/eni.c static int get_esi_fpga(struct atm_dev *dev, void __iomem *base) base 1696 drivers/atm/eni.c mac_base = base+EPROM_SIZE-sizeof(struct midway_eprom); base 1708 drivers/atm/eni.c void __iomem *base; base 1728 drivers/atm/eni.c if (!(base = ioremap_nocache(real_base,MAP_MAX_SIZE))) { base 1734 drivers/atm/eni.c eni_dev->ioaddr = base; base 1735 drivers/atm/eni.c eni_dev->base_diff = real_base - (unsigned long) base; base 1738 drivers/atm/eni.c eprom = (base+EPROM_SIZE-sizeof(struct midway_eprom)); base 1749 drivers/atm/eni.c eni_dev->phy = base+PHY_BASE; base 1750 drivers/atm/eni.c eni_dev->reg = base+REG_BASE; base 1751 drivers/atm/eni.c eni_dev->ram = base+RAM_BASE; base 1776 drivers/atm/eni.c error = eni_dev->asic ? get_esi_asic(dev) : get_esi_fpga(dev,base); base 1792 drivers/atm/eni.c iounmap(base); base 566 drivers/atm/firestream.c writel (val, dev->base + offset); base 572 drivers/atm/firestream.c return readl (dev->base + offset); base 1678 drivers/atm/firestream.c dev->base = ioremap(dev->hw_base, 0x1000); base 1886 drivers/atm/firestream.c iounmap(dev->base); base 2010 drivers/atm/firestream.c iounmap(dev->base); base 464 drivers/atm/firestream.h void __iomem *base; /* Mapping of base address */ base 94 drivers/atm/he.h #define NEXT_ENTRY(base, tail, mask) \ base 95 drivers/atm/he.h (((unsigned long)base)|(((unsigned long)(tail+1))&mask)) base 644 drivers/atm/idt77252.c scq->base = dma_alloc_coherent(&card->pcidev->dev, SCQ_SIZE, base 646 drivers/atm/idt77252.c if (scq->base == NULL) { base 651 drivers/atm/idt77252.c scq->next = scq->base; base 652 drivers/atm/idt77252.c scq->last = scq->base + (SCQ_ENTRIES - 1); base 662 drivers/atm/idt77252.c scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); base 674 drivers/atm/idt77252.c scq->base, scq->paddr); base 752 drivers/atm/idt77252.c scq->next = scq->base; base 758 drivers/atm/idt77252.c (u32)((unsigned long)scq->next - (unsigned long)scq->base)); base 974 drivers/atm/idt77252.c card->rsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE, base 976 drivers/atm/idt77252.c if (card->rsq.base == NULL) { base 981 drivers/atm/idt77252.c card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; base 983 drivers/atm/idt77252.c for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) base 986 drivers/atm/idt77252.c writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, base 991 drivers/atm/idt77252.c (unsigned long) card->rsq.base, base 1006 drivers/atm/idt77252.c card->rsq.base, card->rsq.paddr); base 1212 drivers/atm/idt77252.c rsqe = card->rsq.base; base 1226 drivers/atm/idt77252.c rsqe = card->rsq.base; base 1231 drivers/atm/idt77252.c writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, base 1376 drivers/atm/idt77252.c card->tsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE, base 1378 drivers/atm/idt77252.c if (card->tsq.base == NULL) { base 1383 drivers/atm/idt77252.c card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; base 1385 drivers/atm/idt77252.c for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) base 1389 drivers/atm/idt77252.c writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, base 1399 drivers/atm/idt77252.c card->tsq.base, card->tsq.paddr); base 1411 drivers/atm/idt77252.c tsqe = card->tsq.base; base 1416 drivers/atm/idt77252.c card->tsq.base, card->tsq.next, card->tsq.last); base 1509 drivers/atm/idt77252.c tsqe = card->tsq.base; base 1514 drivers/atm/idt77252.c card->tsq.base, card->tsq.next, card->tsq.last); base 1520 drivers/atm/idt77252.c writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, base 1533 drivers/atm/idt77252.c unsigned long base, idle, jump; base 1540 drivers/atm/idt77252.c base = card->tst[card->tst_index]; base 1544 drivers/atm/idt77252.c jump = base + card->tst_size - 2; base 1555 drivers/atm/idt77252.c write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); base 1557 drivers/atm/idt77252.c base = card->tst[card->tst_index]; base 1580 drivers/atm/idt77252.c jump = base + card->tst_size - 2; base 3079 drivers/atm/idt77252.c if (card->rsq.base) { base 3084 drivers/atm/idt77252.c if (card->tsq.base) { base 162 drivers/atm/idt77252.h struct scqe *base; base 271 drivers/atm/idt77252.h struct rsq_entry *base; base 306 drivers/atm/idt77252.h struct tsq_entry *base; base 2315 drivers/atm/iphase.c void __iomem *base; base 2368 drivers/atm/iphase.c base = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */ base 2370 drivers/atm/iphase.c if (!base) base 2377 drivers/atm/iphase.c dev->number, iadev->pci->revision, base, iadev->irq);) base 2382 drivers/atm/iphase.c iadev->base = base; base 2385 drivers/atm/iphase.c iadev->reg = base + REG_BASE; base 2387 drivers/atm/iphase.c iadev->seg_reg = base + SEG_BASE; base 2389 drivers/atm/iphase.c iadev->reass_reg = base + REASS_BASE; base 2391 drivers/atm/iphase.c iadev->phy = base + PHY_BASE; base 2392 drivers/atm/iphase.c iadev->dma = base + PHY_BASE; base 2394 drivers/atm/iphase.c iadev->ram = base + ACTUAL_RAM_BASE; base 2395 drivers/atm/iphase.c iadev->seg_ram = base + ACTUAL_SEG_RAM_BASE; base 2396 drivers/atm/iphase.c iadev->reass_ram = base + ACTUAL_REASS_RAM_BASE; base 2407 drivers/atm/iphase.c iounmap(iadev->base); base 2417 drivers/atm/iphase.c iounmap(iadev->base); base 3258 drivers/atm/iphase.c iounmap(iadev->base); base 1026 drivers/atm/iphase.h void __iomem *base; base 268 drivers/atm/lanai.c bus_addr_t base; base 471 drivers/atm/lanai.c return lanai->base + reg; base 479 drivers/atm/lanai.c RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base, base 487 drivers/atm/lanai.c RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base, base 537 drivers/atm/lanai.c return lanai->base + SRAM_START + offset; base 2137 drivers/atm/lanai.c lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE); base 2138 drivers/atm/lanai.c if (lanai->base == NULL) { base 2219 drivers/atm/lanai.c lanai->base, lanai->pci->irq, atmdev->esi); base 2236 drivers/atm/lanai.c iounmap(lanai->base); base 2266 drivers/atm/lanai.c iounmap(lanai->base); base 538 drivers/atm/nicstar.c card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT); base 539 drivers/atm/nicstar.c card->tsq.next = card->tsq.base; base 540 drivers/atm/nicstar.c card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1); base 542 drivers/atm/nicstar.c ns_tsi_init(card->tsq.base + j); base 545 drivers/atm/nicstar.c PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base); base 557 drivers/atm/nicstar.c card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT); base 558 drivers/atm/nicstar.c card->rsq.next = card->rsq.base; base 559 drivers/atm/nicstar.c card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1); base 561 drivers/atm/nicstar.c ns_rsqe_init(card->rsq.base + j); base 564 drivers/atm/nicstar.c PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base); base 576 drivers/atm/nicstar.c u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base); base 584 drivers/atm/nicstar.c PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base); base 884 drivers/atm/nicstar.c scq->base = PTR_ALIGN(scq->org, size); base 885 drivers/atm/nicstar.c scq->next = scq->base; base 886 drivers/atm/nicstar.c scq->last = scq->base + (scq->num_entries - 1); base 1366 drivers/atm/nicstar.c u32d[0] = scq_virt_to_bus(scq, scq->base); base 1474 drivers/atm/nicstar.c if (scqep == scq->base) base 1492 drivers/atm/nicstar.c scqi = scq->next - scq->base; base 1500 drivers/atm/nicstar.c scq->next = scq->base; base 1556 drivers/atm/nicstar.c card->tsq.base, card->tsq.next, base 1560 drivers/atm/nicstar.c card->rsq.base, card->rsq.next, base 1749 drivers/atm/nicstar.c index = (int)(scq->next - scq->base); base 1758 drivers/atm/nicstar.c scq->next = scq->base; base 1798 drivers/atm/nicstar.c scqi = scq->next - scq->base; base 1812 drivers/atm/nicstar.c scq->next = scq->base; base 1839 drivers/atm/nicstar.c one_ahead = card->tsq.base; base 1844 drivers/atm/nicstar.c two_ahead = card->tsq.base; base 1857 drivers/atm/nicstar.c card->tsq.next = card->tsq.base; base 1884 drivers/atm/nicstar.c card->tsq.next = card->tsq.base; base 1889 drivers/atm/nicstar.c one_ahead = card->tsq.base; base 1894 drivers/atm/nicstar.c two_ahead = card->tsq.base; base 1900 drivers/atm/nicstar.c writel(PTR_DIFF(previous, card->tsq.base), base 1919 drivers/atm/nicstar.c i = (int)(scq->tail - scq->base); base 1942 drivers/atm/nicstar.c scq->tail = scq->base + pos; base 1957 drivers/atm/nicstar.c card->rsq.next = card->rsq.base; base 1961 drivers/atm/nicstar.c writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH); base 657 drivers/atm/nicstar.h ns_tsi *base; base 665 drivers/atm/nicstar.h ns_scqe *base; base 683 drivers/atm/nicstar.h ns_rsqe *base; base 111 drivers/atm/nicstarmac.c writel((val),(base)+(reg)) base 113 drivers/atm/nicstarmac.c readl((base)+(reg)) base 122 drivers/atm/nicstarmac.c u_int32_t nicstar_read_eprom_status(virt_addr_t base) base 129 drivers/atm/nicstarmac.c val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; base 132 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 142 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 144 drivers/atm/nicstarmac.c rbyte |= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) base 146 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 150 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2); base 162 drivers/atm/nicstarmac.c static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_t offset) base 168 drivers/atm/nicstarmac.c val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; base 172 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 179 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 182 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 191 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 195 drivers/atm/nicstarmac.c (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) base 197 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 202 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2); base 207 drivers/atm/nicstarmac.c static void nicstar_init_eprom(virt_addr_t base) base 214 drivers/atm/nicstarmac.c val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; base 216 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 220 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 224 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 228 drivers/atm/nicstarmac.c NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, base 239 drivers/atm/nicstarmac.c nicstar_read_eprom(virt_addr_t base, base 245 drivers/atm/nicstarmac.c buffer[i] = read_eprom_byte(base, prom_offset); base 127 drivers/atm/zatm.c #define zin_n(r) inl(zatm_dev->base+r*4) base 128 drivers/atm/zatm.c #define zin(r) inl(zatm_dev->base+uPD98401_##r*4) base 129 drivers/atm/zatm.c #define zout(v,r) outl(v,zatm_dev->base+uPD98401_##r*4) base 1198 drivers/atm/zatm.c zatm_dev->base = pci_resource_start(pci_dev, 0); base 1213 drivers/atm/zatm.c dev->number,pci_dev->revision,zatm_dev->base,zatm_dev->irq); base 87 drivers/atm/zatm.h unsigned int base; /* IO base address */ base 180 drivers/auxdisplay/hd44780.c unsigned int i, base; base 192 drivers/auxdisplay/hd44780.c base = PIN_DATA4; base 195 drivers/auxdisplay/hd44780.c base = PIN_DATA0; base 208 drivers/auxdisplay/hd44780.c hd->pins[base + i] = devm_gpiod_get_index(dev, "data", i, base 210 drivers/auxdisplay/hd44780.c if (IS_ERR(hd->pins[base + i])) { base 211 drivers/auxdisplay/hd44780.c ret = PTR_ERR(hd->pins[base + i]); base 50 drivers/auxdisplay/img-ascii-lcd.c void __iomem *base; base 73 drivers/auxdisplay/img-ascii-lcd.c __raw_writeq(val, ctx->base); base 76 drivers/auxdisplay/img-ascii-lcd.c __raw_writel(val, ctx->base); base 78 drivers/auxdisplay/img-ascii-lcd.c __raw_writel(val, ctx->base + 4); base 382 drivers/auxdisplay/img-ascii-lcd.c ctx->base = devm_ioremap_resource(&pdev->dev, res); base 383 drivers/auxdisplay/img-ascii-lcd.c if (IS_ERR(ctx->base)) base 384 drivers/auxdisplay/img-ascii-lcd.c return PTR_ERR(ctx->base); base 118 drivers/auxdisplay/ks0108.c if (port->base != ks0108_port) base 146 drivers/auxdisplay/ks0108.c if (port->base != ks0108_port) base 1776 drivers/auxdisplay/panel.c parport, pprt->port->base); base 276 drivers/base/devtmpfs.c char *base; base 278 drivers/base/devtmpfs.c base = strrchr(path, '/'); base 279 drivers/base/devtmpfs.c if (!base) base 281 drivers/base/devtmpfs.c base[0] = '\0'; base 138 drivers/base/map.c struct probe *base = kzalloc(sizeof(*base), GFP_KERNEL); base 141 drivers/base/map.c if ((p == NULL) || (base == NULL)) { base 143 drivers/base/map.c kfree(base); base 147 drivers/base/map.c base->dev = 1; base 148 drivers/base/map.c base->range = ~0; base 149 drivers/base/map.c base->get = base_probe; base 151 drivers/base/map.c p->probes[i] = base; base 109 drivers/base/platform-msi.c static void platform_msi_free_descs(struct device *dev, int base, int nvec) base 114 drivers/base/platform-msi.c if (desc->platform.msi_index >= base && base 115 drivers/base/platform-msi.c desc->platform.msi_index < (base + nvec)) { base 128 drivers/base/platform-msi.c int i, base = 0; base 133 drivers/base/platform-msi.c base = desc->platform.msi_index + 1; base 142 drivers/base/platform-msi.c desc->platform.msi_index = base + i; base 150 drivers/base/platform-msi.c platform_msi_free_descs(dev, base, nvec); base 644 drivers/base/power/domain.c dev = gpd_data->base.dev; base 1410 drivers/base/power/domain.c gpd_data->base.dev = dev; base 1422 drivers/base/power/domain.c dev->power.subsys_data->domain_data = &gpd_data->base; base 1527 drivers/base/power/domain.c list_add_tail(&gpd_data->base.list_node, &genpd->dev_list); base 249 drivers/base/regmap/internal.h const void *base, base 252 drivers/base/regmap/internal.h return base + (map->cache_word_size * idx); base 255 drivers/base/regmap/internal.h unsigned int regcache_get_val(struct regmap *map, const void *base, base 257 drivers/base/regmap/internal.h bool regcache_set_val(struct regmap *map, void *base, unsigned int idx, base 42 drivers/base/regmap/regcache-rbtree.c unsigned int *base, unsigned int *top) base 44 drivers/base/regmap/regcache-rbtree.c *base = rbnode->base_reg; base 138 drivers/base/regmap/regcache-rbtree.c unsigned int base, top; base 155 drivers/base/regmap/regcache-rbtree.c regcache_rbtree_get_base_top_reg(map, n, &base, &top); base 156 drivers/base/regmap/regcache-rbtree.c this_registers = ((top - base) / map->reg_stride) + 1; base 157 drivers/base/regmap/regcache-rbtree.c seq_printf(s, "%x-%x (%d)\n", base, top, this_registers); base 548 drivers/base/regmap/regcache.c bool regcache_set_val(struct regmap *map, void *base, unsigned int idx, base 551 drivers/base/regmap/regcache.c if (regcache_get_val(map, base, idx) == val) base 556 drivers/base/regmap/regcache.c map->format.format_val(base + (map->cache_word_size * idx), base 563 drivers/base/regmap/regcache.c u8 *cache = base; base 569 drivers/base/regmap/regcache.c u16 *cache = base; base 575 drivers/base/regmap/regcache.c u32 *cache = base; base 582 drivers/base/regmap/regcache.c u64 *cache = base; base 594 drivers/base/regmap/regcache.c unsigned int regcache_get_val(struct regmap *map, const void *base, base 597 drivers/base/regmap/regcache.c if (!base) base 602 drivers/base/regmap/regcache.c return map->format.parse_val(regcache_get_val_addr(map, base, base 607 drivers/base/regmap/regcache.c const u8 *cache = base; base 612 drivers/base/regmap/regcache.c const u16 *cache = base; base 617 drivers/base/regmap/regcache.c const u32 *cache = base; base 623 drivers/base/regmap/regcache.c const u64 *cache = base; base 705 drivers/base/regmap/regcache.c unsigned int base, unsigned int cur) base 713 drivers/base/regmap/regcache.c count = (cur - base) / map->reg_stride; base 716 drivers/base/regmap/regcache.c count * val_bytes, count, base, cur - map->reg_stride); base 720 drivers/base/regmap/regcache.c ret = _regmap_raw_write(map, base, *data, count * val_bytes); base 723 drivers/base/regmap/regcache.c base, cur - map->reg_stride, ret); base 739 drivers/base/regmap/regcache.c unsigned int base = 0; base 749 drivers/base/regmap/regcache.c base, regtmp); base 758 drivers/base/regmap/regcache.c base, regtmp); base 766 drivers/base/regmap/regcache.c base = regtmp; base 770 drivers/base/regmap/regcache.c return regcache_sync_block_raw_flush(map, &data, base, regtmp + base 97 drivers/base/regmap/regmap-debugfs.c unsigned int base, base 108 drivers/base/regmap/regmap-debugfs.c if (base) base 109 drivers/base/regmap/regmap-debugfs.c return base; base 116 drivers/base/regmap/regmap-debugfs.c i = base; base 138 drivers/base/regmap/regmap-debugfs.c return base; base 162 drivers/base/regmap/regmap-debugfs.c ret = base; base 2197 drivers/base/regmap/regmap.c struct reg_sequence *base; base 2206 drivers/base/regmap/regmap.c base = regs; base 2240 drivers/base/regmap/regmap.c ret = _regmap_raw_multi_reg_write(map, base, n); base 2247 drivers/base/regmap/regmap.c base += n; base 2252 drivers/base/regmap/regmap.c &base[n].reg, base 2264 drivers/base/regmap/regmap.c return _regmap_raw_multi_reg_write(map, base, n); base 2329 drivers/base/regmap/regmap.c struct reg_sequence *base = kmemdup(regs, len, base 2331 drivers/base/regmap/regmap.c if (!base) base 2333 drivers/base/regmap/regmap.c ret = _regmap_range_multi_paged_reg_write(map, base, base 2335 drivers/base/regmap/regmap.c kfree(base); base 211 drivers/bcma/driver_gpio.c chip->base = bus->num * BCMA_GPIO_MAX_PINS; base 213 drivers/bcma/driver_gpio.c chip->base = -1; base 874 drivers/block/drbd/drbd_nl.c int base = 0; base 875 drivers/block/drbd/drbd_nl.c while (size >= 10000 && base < sizeof(units)-1) { base 878 drivers/block/drbd/drbd_nl.c base++; base 880 drivers/block/drbd/drbd_nl.c sprintf(buf, "%u %cB", (unsigned)size, units[base]); base 2376 drivers/block/floppy.c char *base; base 2378 drivers/block/floppy.c base = bio_data(current_req->bio); base 2382 drivers/block/floppy.c if (page_address(bv.bv_page) + bv.bv_offset != base + size) base 3166 drivers/block/mtip32xx/mtip32xx.c const int base = 'z' - 'a' + 1; base 3174 drivers/block/mtip32xx/mtip32xx.c unit = base; base 131 drivers/block/paride/bpck6.c ((struct pardevice *)(pi->pardev))->port->base); base 375 drivers/block/ps3vram.c unsigned int base; base 381 drivers/block/ps3vram.c base = (unsigned int) (address - offset); base 386 drivers/block/ps3vram.c cache->tags[i].address == base) { base 399 drivers/block/ps3vram.c ps3vram_cache_load(dev, i, base); base 730 drivers/block/sunvdc.c dr->base = dring; base 744 drivers/block/sunvdc.c if (dr->base) { base 745 drivers/block/sunvdc.c ldc_free_exp_dring(port->vio.lp, dr->base, base 748 drivers/block/sunvdc.c dr->base = NULL; base 62 drivers/block/swim.c #define swim_write(base, reg, v) out_8(&(base)->write_##reg, (v)) base 63 drivers/block/swim.c #define swim_read(base, reg) in_8(&(base)->read_##reg) base 86 drivers/block/swim.c #define iwm_write(base, reg, v) out_8(&(base)->reg, (v)) base 87 drivers/block/swim.c #define iwm_read(base, reg) in_8(&(base)->reg) base 209 drivers/block/swim.c struct swim __iomem *base; base 215 drivers/block/swim.c extern int swim_read_sector_header(struct swim __iomem *base, base 217 drivers/block/swim.c extern int swim_read_sector_data(struct swim __iomem *base, base 221 drivers/block/swim.c static inline void set_swim_mode(struct swim __iomem *base, int enable) base 227 drivers/block/swim.c swim_write(base, mode0, 0xf8); base 231 drivers/block/swim.c iwm_base = (struct iwm __iomem *)base; base 246 drivers/block/swim.c static inline int get_swim_mode(struct swim __iomem *base) base 252 drivers/block/swim.c swim_write(base, phase, 0xf5); base 253 drivers/block/swim.c if (swim_read(base, phase) != 0xf5) base 255 drivers/block/swim.c swim_write(base, phase, 0xf6); base 256 drivers/block/swim.c if (swim_read(base, phase) != 0xf6) base 258 drivers/block/swim.c swim_write(base, phase, 0xf7); base 259 drivers/block/swim.c if (swim_read(base, phase) != 0xf7) base 268 drivers/block/swim.c static inline void swim_select(struct swim __iomem *base, int sel) base 270 drivers/block/swim.c swim_write(base, phase, RELAX); base 274 drivers/block/swim.c swim_write(base, phase, sel & CA_MASK); base 277 drivers/block/swim.c static inline void swim_action(struct swim __iomem *base, int action) base 283 drivers/block/swim.c swim_select(base, action); base 285 drivers/block/swim.c swim_write(base, phase, (LSTRB<<4) | LSTRB); base 287 drivers/block/swim.c swim_write(base, phase, (LSTRB<<4) | ((~LSTRB) & 0x0F)); base 293 drivers/block/swim.c static inline int swim_readbit(struct swim __iomem *base, int bit) base 297 drivers/block/swim.c swim_select(base, bit); base 301 drivers/block/swim.c stat = swim_read(base, handshake); base 306 drivers/block/swim.c static inline void swim_drive(struct swim __iomem *base, base 310 drivers/block/swim.c swim_write(base, mode0, EXTERNAL_DRIVE); /* clear drive 1 bit */ base 311 drivers/block/swim.c swim_write(base, mode1, INTERNAL_DRIVE); /* set drive 0 bit */ base 313 drivers/block/swim.c swim_write(base, mode0, INTERNAL_DRIVE); /* clear drive 0 bit */ base 314 drivers/block/swim.c swim_write(base, mode1, EXTERNAL_DRIVE); /* set drive 1 bit */ base 318 drivers/block/swim.c static inline void swim_motor(struct swim __iomem *base, base 324 drivers/block/swim.c swim_action(base, MOTOR_ON); base 327 drivers/block/swim.c swim_select(base, RELAX); base 328 drivers/block/swim.c if (swim_readbit(base, MOTOR_ON)) base 334 drivers/block/swim.c swim_action(base, MOTOR_OFF); base 335 drivers/block/swim.c swim_select(base, RELAX); base 339 drivers/block/swim.c static inline void swim_eject(struct swim __iomem *base) base 343 drivers/block/swim.c swim_action(base, EJECT); base 346 drivers/block/swim.c swim_select(base, RELAX); base 347 drivers/block/swim.c if (!swim_readbit(base, DISK_IN)) base 352 drivers/block/swim.c swim_select(base, RELAX); base 355 drivers/block/swim.c static inline void swim_head(struct swim __iomem *base, enum head head) base 360 drivers/block/swim.c swim_select(base, READ_DATA_1); base 362 drivers/block/swim.c swim_select(base, READ_DATA_0); base 365 drivers/block/swim.c static inline int swim_step(struct swim __iomem *base) base 369 drivers/block/swim.c swim_action(base, STEP); base 376 drivers/block/swim.c swim_select(base, RELAX); base 377 drivers/block/swim.c if (!swim_readbit(base, STEP)) base 383 drivers/block/swim.c static inline int swim_track00(struct swim __iomem *base) base 387 drivers/block/swim.c swim_action(base, SEEK_NEGATIVE); base 391 drivers/block/swim.c swim_select(base, RELAX); base 392 drivers/block/swim.c if (swim_readbit(base, TRACK_ZERO)) base 395 drivers/block/swim.c if (swim_step(base)) base 399 drivers/block/swim.c if (swim_readbit(base, TRACK_ZERO)) base 405 drivers/block/swim.c static inline int swim_seek(struct swim __iomem *base, int step) base 411 drivers/block/swim.c swim_action(base, SEEK_NEGATIVE); base 414 drivers/block/swim.c swim_action(base, SEEK_POSITIVE); base 417 drivers/block/swim.c if (swim_step(base)) base 426 drivers/block/swim.c struct swim __iomem *base = fs->swd->base; base 429 drivers/block/swim.c ret = swim_seek(base, track - fs->track); base 434 drivers/block/swim.c swim_track00(base); base 443 drivers/block/swim.c struct swim __iomem *base = fs->swd->base; base 445 drivers/block/swim.c swim_drive(base, fs->location); base 446 drivers/block/swim.c swim_motor(base, OFF); base 447 drivers/block/swim.c swim_eject(base); base 459 drivers/block/swim.c struct swim __iomem *base = fs->swd->base; base 467 drivers/block/swim.c swim_write(base, mode1, MOTON); base 468 drivers/block/swim.c swim_head(base, side); base 469 drivers/block/swim.c swim_write(base, mode0, side); base 473 drivers/block/swim.c ret = swim_read_sector_header(base, &header); base 477 drivers/block/swim.c ret = swim_read_sector_data(base, buffer); base 483 drivers/block/swim.c swim_write(base, mode0, MOTON); base 496 drivers/block/swim.c struct swim __iomem *base = fs->swd->base; base 502 drivers/block/swim.c swim_drive(base, fs->location); base 583 drivers/block/swim.c struct swim __iomem *base = fs->swd->base; base 585 drivers/block/swim.c if (swim_readbit(base, DISK_IN)) { base 588 drivers/block/swim.c fs->write_protected = swim_readbit(base, WRITE_PROT); base 590 drivers/block/swim.c if (swim_track00(base)) base 594 drivers/block/swim.c swim_track00(base); base 596 drivers/block/swim.c fs->type = swim_readbit(base, TWOMEG_MEDIA) ? base 598 drivers/block/swim.c fs->head_number = swim_readbit(base, SINGLE_SIDED) ? 1 : 2; base 612 drivers/block/swim.c struct swim __iomem *base = fs->swd->base; base 623 drivers/block/swim.c swim_write(base, setup, S_IBM_DRIVE | S_FCLK_DIV2); base 625 drivers/block/swim.c swim_drive(base, fs->location); base 626 drivers/block/swim.c swim_motor(base, ON); base 627 drivers/block/swim.c swim_action(base, SETMFM); base 655 drivers/block/swim.c swim_motor(base, OFF); base 673 drivers/block/swim.c struct swim __iomem *base = fs->swd->base; base 682 drivers/block/swim.c swim_motor(base, OFF); base 741 drivers/block/swim.c struct swim __iomem *base = fs->swd->base; base 743 drivers/block/swim.c swim_drive(base, fs->location); base 749 drivers/block/swim.c swim_motor(base, OFF); base 781 drivers/block/swim.c struct swim __iomem *base = swd->base; base 785 drivers/block/swim.c swim_drive(base, location); base 787 drivers/block/swim.c swim_motor(base, OFF); base 808 drivers/block/swim.c struct swim __iomem *base = swd->base; base 812 drivers/block/swim.c swim_drive(base, INTERNAL_DRIVE); base 813 drivers/block/swim.c if (swim_readbit(base, DRIVE_PRESENT) && base 814 drivers/block/swim.c !swim_readbit(base, ONEMEG_DRIVE)) base 816 drivers/block/swim.c swim_drive(base, EXTERNAL_DRIVE); base 817 drivers/block/swim.c if (swim_readbit(base, DRIVE_PRESENT) && base 818 drivers/block/swim.c !swim_readbit(base, ONEMEG_DRIVE)) base 931 drivers/block/swim.c swd->base = swim_base; base 635 drivers/block/virtio_blk.c const int base = 'z' - 'a' + 1; base 643 drivers/block/virtio_blk.c unit = base; base 369 drivers/block/xsysace.c static void ace_dump_mem(void *base, int len) base 371 drivers/block/xsysace.c const char *ptr = base; base 388 drivers/block/xsysace.c static inline void ace_dump_mem(void *base, int len) base 664 drivers/bluetooth/bt3c_cs.c static unsigned int base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 }; base 675 drivers/bluetooth/bt3c_cs.c p_dev->resource[0]->start = base[j]; base 676 drivers/bluetooth/bt3c_cs.c p_dev->io_lines = base[j] ? 16 : 3; base 107 drivers/bus/arm-cci.c void __iomem *base; base 235 drivers/bus/arm-cci.c void __iomem *base = ports[port].base; base 237 drivers/bus/arm-cci.c writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL); base 482 drivers/bus/arm-cci.c ports[i].base = ioremap(res.start, resource_size(&res)); base 485 drivers/bus/arm-cci.c if (ret || !ports[i].base) { base 88 drivers/bus/brcmstb_gisb.c void __iomem *base; base 113 drivers/bus/brcmstb_gisb.c return ioread32be(gdev->base + offset); base 115 drivers/bus/brcmstb_gisb.c return ioread32(gdev->base + offset); base 136 drivers/bus/brcmstb_gisb.c iowrite32be(val, gdev->base + offset); base 138 drivers/bus/brcmstb_gisb.c iowrite32(val, gdev->base + offset); base 335 drivers/bus/brcmstb_gisb.c gdev->base = devm_ioremap_resource(&pdev->dev, r); base 336 drivers/bus/brcmstb_gisb.c if (IS_ERR(gdev->base)) base 337 drivers/bus/brcmstb_gisb.c return PTR_ERR(gdev->base); base 130 drivers/bus/imx-weim.c struct device_node *np, void __iomem *base, base 179 drivers/bus/imx-weim.c base + cs_idx * devtype->cs_stride + i * 4); base 190 drivers/bus/imx-weim.c static int weim_parse_dt(struct platform_device *pdev, void __iomem *base) base 208 drivers/bus/imx-weim.c reg = readl(base + devtype->wcr_offset); base 210 drivers/bus/imx-weim.c base + devtype->wcr_offset); base 218 drivers/bus/imx-weim.c ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts); base 239 drivers/bus/imx-weim.c void __iomem *base; base 244 drivers/bus/imx-weim.c base = devm_ioremap_resource(&pdev->dev, res); base 245 drivers/bus/imx-weim.c if (IS_ERR(base)) base 246 drivers/bus/imx-weim.c return PTR_ERR(base); base 258 drivers/bus/imx-weim.c ret = weim_parse_dt(pdev, base); base 130 drivers/bus/mvebu-mbus.c u32 base; base 201 drivers/bus/mvebu-mbus.c int win, int *enabled, u64 *base, base 216 drivers/bus/mvebu-mbus.c *base = ((u64)basereg & WIN_BASE_HIGH) << 32; base 217 drivers/bus/mvebu-mbus.c *base |= (basereg & WIN_BASE_LOW); base 272 drivers/bus/mvebu-mbus.c phys_addr_t base, size_t size, base 275 drivers/bus/mvebu-mbus.c u64 end = (u64)base + size; base 297 drivers/bus/mvebu-mbus.c if ((u64)base < wend && end > wbase) base 305 drivers/bus/mvebu-mbus.c phys_addr_t base, size_t size) base 321 drivers/bus/mvebu-mbus.c if (base == wbase && size == wsize) base 329 drivers/bus/mvebu-mbus.c int win, phys_addr_t base, size_t size, base 342 drivers/bus/mvebu-mbus.c if ((base & (phys_addr_t)(size - 1)) != 0) { base 343 drivers/bus/mvebu-mbus.c WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base, base 355 drivers/bus/mvebu-mbus.c writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF); base 363 drivers/bus/mvebu-mbus.c remap_addr = base; base 374 drivers/bus/mvebu-mbus.c phys_addr_t base, size_t size, base 386 drivers/bus/mvebu-mbus.c return mvebu_mbus_setup_window(mbus, win, base, base 399 drivers/bus/mvebu-mbus.c return mvebu_mbus_setup_window(mbus, win, base, size, base 419 drivers/bus/mvebu-mbus.c u64 base; base 427 drivers/bus/mvebu-mbus.c base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32; base 428 drivers/bus/mvebu-mbus.c base |= basereg & DDR_BASE_CS_LOW_MASK; base 432 drivers/bus/mvebu-mbus.c i, (unsigned long long)base, base 433 drivers/bus/mvebu-mbus.c (unsigned long long)base + size + 1, base 448 drivers/bus/mvebu-mbus.c u64 base; base 456 drivers/bus/mvebu-mbus.c base = map & 0xff800000; base 460 drivers/bus/mvebu-mbus.c i, (unsigned long long)base, base 461 drivers/bus/mvebu-mbus.c (unsigned long long)base + size, i); base 621 drivers/bus/mvebu-mbus.c if (r->base >= 0x100000000ULL) base 628 drivers/bus/mvebu-mbus.c if (r->base + r->size > s) base 629 drivers/bus/mvebu-mbus.c s = r->base + r->size; base 652 drivers/bus/mvebu-mbus.c u64 base, size, end; base 655 drivers/bus/mvebu-mbus.c base = w->base; base 657 drivers/bus/mvebu-mbus.c end = base + size; base 663 drivers/bus/mvebu-mbus.c if (base >= mbus_bridge_base && end <= mbus_bridge_end) base 670 drivers/bus/mvebu-mbus.c if (base >= mbus_bridge_base && end > mbus_bridge_end) { base 671 drivers/bus/mvebu-mbus.c size -= mbus_bridge_end - base; base 672 drivers/bus/mvebu-mbus.c base = mbus_bridge_end; base 679 drivers/bus/mvebu-mbus.c if (base < mbus_bridge_base && end > mbus_bridge_base) base 687 drivers/bus/mvebu-mbus.c w->base = base; base 704 drivers/bus/mvebu-mbus.c u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); base 714 drivers/bus/mvebu-mbus.c !(base & DDR_BASE_CS_HIGH_MASK)) { base 722 drivers/bus/mvebu-mbus.c w->base = base & DDR_BASE_CS_LOW_MASK; base 736 drivers/bus/mvebu-mbus.c u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); base 741 drivers/bus/mvebu-mbus.c writel(base, store_addr++); base 773 drivers/bus/mvebu-mbus.c w->base = map & 0xff800000; base 904 drivers/bus/mvebu-mbus.c phys_addr_t base, size_t size, base 909 drivers/bus/mvebu-mbus.c if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) { base 915 drivers/bus/mvebu-mbus.c return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute); base 919 drivers/bus/mvebu-mbus.c phys_addr_t base, size_t size) base 921 drivers/bus/mvebu-mbus.c return mvebu_mbus_add_window_remap_by_id(target, attribute, base, base 925 drivers/bus/mvebu-mbus.c int mvebu_mbus_del_window(phys_addr_t base, size_t size) base 929 drivers/bus/mvebu-mbus.c win = mvebu_mbus_find_window(&mbus_state, base, size); base 967 drivers/bus/mvebu-mbus.c if (cs->base <= phyaddr && base 968 drivers/bus/mvebu-mbus.c phyaddr <= (cs->base + cs->size - 1)) { base 1042 drivers/bus/mvebu-mbus.c s->wins[win].base = readl(addr + WIN_BASE_OFF); base 1078 drivers/bus/mvebu-mbus.c writel(s->wins[win].base, addr + WIN_BASE_OFF); base 1184 drivers/bus/mvebu-mbus.c u32 base, u32 size, base 1187 drivers/bus/mvebu-mbus.c if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) { base 1193 drivers/bus/mvebu-mbus.c if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP, base 1252 drivers/bus/mvebu-mbus.c u32 windowid, base, size; base 1266 drivers/bus/mvebu-mbus.c base = of_read_number(r + c_addr_cells, addr_cells); base 1269 drivers/bus/mvebu-mbus.c ret = mbus_dt_setup_win(mbus, base, size, target, attr); base 58 drivers/bus/omap_l3_noc.c static int l3_handle_target(struct omap_l3 *l3, void __iomem *base, base 80 drivers/bus/omap_l3_noc.c l3_targ_base = base + l3_targ_inst->offset; base 173 drivers/bus/omap_l3_noc.c void __iomem *base, *mask_reg; base 184 drivers/bus/omap_l3_noc.c base = l3->l3_base[i]; base 186 drivers/bus/omap_l3_noc.c err_reg = readl_relaxed(base + flag_mux->offset + base 197 drivers/bus/omap_l3_noc.c ret = l3_handle_target(l3, base, flag_mux, err_src); base 211 drivers/bus/omap_l3_noc.c mask_reg = base + flag_mux->offset + base 319 drivers/bus/omap_l3_noc.c void __iomem *base, *mask_regx = NULL; base 323 drivers/bus/omap_l3_noc.c base = l3->l3_base[i]; base 328 drivers/bus/omap_l3_noc.c mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 + base 334 drivers/bus/omap_l3_noc.c mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 + base 22 drivers/bus/omap_l3_smx.c static inline u64 omap3_l3_readll(void __iomem *base, u16 reg) base 24 drivers/bus/omap_l3_smx.c return __raw_readll(base + reg); base 27 drivers/bus/omap_l3_smx.c static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value) base 29 drivers/bus/omap_l3_smx.c __raw_writell(value, base + reg); base 164 drivers/bus/omap_l3_smx.c void __iomem *base; base 186 drivers/bus/omap_l3_smx.c base = l3->rt + omap3_l3_bases[int_type][err_source]; base 187 drivers/bus/omap_l3_smx.c error = omap3_l3_readll(base, L3_ERROR_LOG); base 189 drivers/bus/omap_l3_smx.c error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR); base 196 drivers/bus/omap_l3_smx.c omap3_l3_writell(base, L3_AGENT_STATUS, clear); base 199 drivers/bus/omap_l3_smx.c omap3_l3_writell(base, L3_ERROR_LOG, error); base 44 drivers/bus/tegra-gmi.c void __iomem *base; base 67 drivers/bus/tegra-gmi.c writel(gmi->snor_timing0, gmi->base + TEGRA_GMI_TIMING0); base 68 drivers/bus/tegra-gmi.c writel(gmi->snor_timing1, gmi->base + TEGRA_GMI_TIMING1); base 71 drivers/bus/tegra-gmi.c writel(gmi->snor_config, gmi->base + TEGRA_GMI_CONFIG); base 81 drivers/bus/tegra-gmi.c config = readl(gmi->base + TEGRA_GMI_CONFIG); base 83 drivers/bus/tegra-gmi.c writel(config, gmi->base + TEGRA_GMI_CONFIG); base 219 drivers/bus/tegra-gmi.c gmi->base = devm_ioremap_resource(dev, res); base 220 drivers/bus/tegra-gmi.c if (IS_ERR(gmi->base)) base 221 drivers/bus/tegra-gmi.c return PTR_ERR(gmi->base); base 1193 drivers/bus/ti-sysc.c u32 base; base 1206 drivers/bus/ti-sysc.c .base = (optbase), \ base 1352 drivers/bus/ti-sysc.c if (!q->base) base 1355 drivers/bus/ti-sysc.c if (q->base != ddata->module_pa) base 1384 drivers/bus/ti-sysc.c if (q->base && q->base != ddata->module_pa) base 28 drivers/bus/uniphier-system-bus.c u32 base; base 52 drivers/bus/uniphier-system-bus.c if (priv->bank[bank].base || priv->bank[bank].end) { base 86 drivers/bus/uniphier-system-bus.c priv->bank[bank].base = paddr; base 90 drivers/bus/uniphier-system-bus.c bank, priv->bank[bank].base, priv->bank[bank].end); base 102 drivers/bus/uniphier-system-bus.c if (priv->bank[i].end > priv->bank[j].base && base 103 drivers/bus/uniphier-system-bus.c priv->bank[i].base < priv->bank[j].end) { base 137 drivers/bus/uniphier-system-bus.c u32 base, end, mask, val; base 141 drivers/bus/uniphier-system-bus.c base = priv->bank[i].base; base 144 drivers/bus/uniphier-system-bus.c if (base == end) { base 163 drivers/bus/uniphier-system-bus.c mask = base ^ (end - 1); base 165 drivers/bus/uniphier-system-bus.c val = base & 0xfffe0000; base 1795 drivers/cdrom/cdrom.c unsigned char buf[21], *base; base 1818 drivers/cdrom/cdrom.c base = &buf[4]; base 1826 drivers/cdrom/cdrom.c layer->book_version = base[0] & 0xf; base 1827 drivers/cdrom/cdrom.c layer->book_type = base[0] >> 4; base 1828 drivers/cdrom/cdrom.c layer->min_rate = base[1] & 0xf; base 1829 drivers/cdrom/cdrom.c layer->disc_size = base[1] >> 4; base 1830 drivers/cdrom/cdrom.c layer->layer_type = base[2] & 0xf; base 1831 drivers/cdrom/cdrom.c layer->track_path = (base[2] >> 4) & 1; base 1832 drivers/cdrom/cdrom.c layer->nlayers = (base[2] >> 5) & 3; base 1833 drivers/cdrom/cdrom.c layer->track_density = base[3] & 0xf; base 1834 drivers/cdrom/cdrom.c layer->linear_density = base[3] >> 4; base 1835 drivers/cdrom/cdrom.c layer->start_sector = base[5] << 16 | base[6] << 8 | base[7]; base 1836 drivers/cdrom/cdrom.c layer->end_sector = base[9] << 16 | base[10] << 8 | base[11]; base 1837 drivers/cdrom/cdrom.c layer->end_sector_l0 = base[13] << 16 | base[14] << 8 | base[15]; base 1838 drivers/cdrom/cdrom.c layer->bca = base[16] >> 7; base 65 drivers/char/agp/nvidia-agp.c static int nvidia_init_iorr(u32 base, u32 size) base 79 drivers/char/agp/nvidia-agp.c if ((base_lo & 0xfffff000) == (base & 0xfffff000)) base 92 drivers/char/agp/nvidia-agp.c base_lo = (base & ~0xfff) | 0x18; base 159 drivers/char/hpet.c unsigned long m, t, mc, base, k; base 181 drivers/char/hpet.c base = mc % t; base 182 drivers/char/hpet.c k = (mc - base + hpetp->hp_delta) / t; base 183 drivers/char/hpet.c write_counter(t * (k + 1) + base, base 27 drivers/char/hw_random/atmel-rng.c void __iomem *base; base 38 drivers/char/hw_random/atmel-rng.c if (readl(trng->base + TRNG_ISR) & 1) { base 39 drivers/char/hw_random/atmel-rng.c *data = readl(trng->base + TRNG_ODATA); base 46 drivers/char/hw_random/atmel-rng.c readl(trng->base + TRNG_ISR); base 54 drivers/char/hw_random/atmel-rng.c writel(TRNG_KEY | 1, trng->base + TRNG_CR); base 59 drivers/char/hw_random/atmel-rng.c writel(TRNG_KEY, trng->base + TRNG_CR); base 73 drivers/char/hw_random/atmel-rng.c trng->base = devm_ioremap_resource(&pdev->dev, res); base 74 drivers/char/hw_random/atmel-rng.c if (IS_ERR(trng->base)) base 75 drivers/char/hw_random/atmel-rng.c return PTR_ERR(trng->base); base 32 drivers/char/hw_random/bcm2835-rng.c void __iomem *base; base 48 drivers/char/hw_random/bcm2835-rng.c return __raw_readl(priv->base + offset); base 50 drivers/char/hw_random/bcm2835-rng.c return readl(priv->base + offset); base 57 drivers/char/hw_random/bcm2835-rng.c __raw_writel(val, priv->base + offset); base 59 drivers/char/hw_random/bcm2835-rng.c writel(val, priv->base + offset); base 157 drivers/char/hw_random/bcm2835-rng.c priv->base = devm_ioremap_resource(dev, r); base 158 drivers/char/hw_random/bcm2835-rng.c if (IS_ERR(priv->base)) base 159 drivers/char/hw_random/bcm2835-rng.c return PTR_ERR(priv->base); base 30 drivers/char/hw_random/hisi-rng.c void __iomem *base; base 43 drivers/char/hw_random/hisi-rng.c writel_relaxed(seed, hrng->base + RNG_SEED); base 53 drivers/char/hw_random/hisi-rng.c writel_relaxed(val, hrng->base + RNG_CTRL); base 61 drivers/char/hw_random/hisi-rng.c writel_relaxed(0, hrng->base + RNG_CTRL); base 69 drivers/char/hw_random/hisi-rng.c *data = readl_relaxed(hrng->base + RNG_RAN_NUM); base 86 drivers/char/hw_random/hisi-rng.c rng->base = devm_ioremap_resource(&pdev->dev, res); base 87 drivers/char/hw_random/hisi-rng.c if (IS_ERR(rng->base)) base 88 drivers/char/hw_random/hisi-rng.c return PTR_ERR(rng->base); base 52 drivers/char/hw_random/imx-rngc.c void __iomem *base; base 68 drivers/char/hw_random/imx-rngc.c ctrl = readl(rngc->base + RNGC_CONTROL); base 70 drivers/char/hw_random/imx-rngc.c writel(ctrl, rngc->base + RNGC_CONTROL); base 77 drivers/char/hw_random/imx-rngc.c cmd = readl(rngc->base + RNGC_COMMAND); base 79 drivers/char/hw_random/imx-rngc.c writel(cmd, rngc->base + RNGC_COMMAND); base 86 drivers/char/hw_random/imx-rngc.c ctrl = readl(rngc->base + RNGC_CONTROL); base 88 drivers/char/hw_random/imx-rngc.c writel(ctrl, rngc->base + RNGC_CONTROL); base 99 drivers/char/hw_random/imx-rngc.c cmd = readl(rngc->base + RNGC_COMMAND); base 100 drivers/char/hw_random/imx-rngc.c writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND); base 124 drivers/char/hw_random/imx-rngc.c status = readl(rngc->base + RNGC_STATUS); base 136 drivers/char/hw_random/imx-rngc.c *(u32 *)data = readl(rngc->base + RNGC_FIFO); base 156 drivers/char/hw_random/imx-rngc.c status = readl(rngc->base + RNGC_STATUS); base 157 drivers/char/hw_random/imx-rngc.c rngc->err_reg = readl(rngc->base + RNGC_ERROR); base 174 drivers/char/hw_random/imx-rngc.c cmd = readl(rngc->base + RNGC_COMMAND); base 175 drivers/char/hw_random/imx-rngc.c writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND); base 182 drivers/char/hw_random/imx-rngc.c cmd = readl(rngc->base + RNGC_COMMAND); base 183 drivers/char/hw_random/imx-rngc.c writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND); base 208 drivers/char/hw_random/imx-rngc.c rngc->base = devm_platform_ioremap_resource(pdev, 0); base 209 drivers/char/hw_random/imx-rngc.c if (IS_ERR(rngc->base)) base 210 drivers/char/hw_random/imx-rngc.c return PTR_ERR(rngc->base); base 52 drivers/char/hw_random/iproc-rng200.c void __iomem *base; base 110 drivers/char/hw_random/iproc-rng200.c status = ioread32(priv->base + RNG_INT_STATUS_OFFSET); base 117 drivers/char/hw_random/iproc-rng200.c iproc_rng200_restart(priv->base); base 122 drivers/char/hw_random/iproc-rng200.c if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) & base 127 drivers/char/hw_random/iproc-rng200.c *(uint32_t *)buf = ioread32(priv->base + base 133 drivers/char/hw_random/iproc-rng200.c uint32_t rnd_number = ioread32(priv->base + base 161 drivers/char/hw_random/iproc-rng200.c val = ioread32(priv->base + RNG_CTRL_OFFSET); base 164 drivers/char/hw_random/iproc-rng200.c iowrite32(val, priv->base + RNG_CTRL_OFFSET); base 175 drivers/char/hw_random/iproc-rng200.c val = ioread32(priv->base + RNG_CTRL_OFFSET); base 178 drivers/char/hw_random/iproc-rng200.c iowrite32(val, priv->base + RNG_CTRL_OFFSET); base 199 drivers/char/hw_random/iproc-rng200.c priv->base = devm_ioremap_resource(dev, res); base 200 drivers/char/hw_random/iproc-rng200.c if (IS_ERR(priv->base)) { base 202 drivers/char/hw_random/iproc-rng200.c return PTR_ERR(priv->base); base 20 drivers/char/hw_random/meson-rng.c void __iomem *base; base 31 drivers/char/hw_random/meson-rng.c *(u32 *)buf = readl_relaxed(data->base + RNG_DATA); base 55 drivers/char/hw_random/meson-rng.c data->base = devm_ioremap_resource(dev, res); base 56 drivers/char/hw_random/meson-rng.c if (IS_ERR(data->base)) base 57 drivers/char/hw_random/meson-rng.c return PTR_ERR(data->base); base 36 drivers/char/hw_random/mtk-rng.c void __iomem *base; base 51 drivers/char/hw_random/mtk-rng.c val = readl(priv->base + RNG_CTRL); base 53 drivers/char/hw_random/mtk-rng.c writel(val, priv->base + RNG_CTRL); base 63 drivers/char/hw_random/mtk-rng.c val = readl(priv->base + RNG_CTRL); base 65 drivers/char/hw_random/mtk-rng.c writel(val, priv->base + RNG_CTRL); base 75 drivers/char/hw_random/mtk-rng.c ready = readl(priv->base + RNG_CTRL) & RNG_READY; base 77 drivers/char/hw_random/mtk-rng.c readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready, base 94 drivers/char/hw_random/mtk-rng.c *(u32 *)buf = readl(priv->base + RNG_DATA); base 138 drivers/char/hw_random/mtk-rng.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 139 drivers/char/hw_random/mtk-rng.c if (IS_ERR(priv->base)) base 140 drivers/char/hw_random/mtk-rng.c return PTR_ERR(priv->base); base 560 drivers/char/hw_random/n2-drv.c u64 base, base3; base 566 drivers/char/hw_random/n2-drv.c base = RNG_v1_CTL_ASEL_NOOUT << RNG_v1_CTL_ASEL_SHIFT; base 567 drivers/char/hw_random/n2-drv.c base3 = base | RNG_CTL_LFSR | base 571 drivers/char/hw_random/n2-drv.c base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT; base 572 drivers/char/hw_random/n2-drv.c base3 = base | RNG_CTL_LFSR | base 576 drivers/char/hw_random/n2-drv.c base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT; base 577 drivers/char/hw_random/n2-drv.c base3 = base | RNG_CTL_LFSR | base 582 drivers/char/hw_random/n2-drv.c np->test_control[0] = base; base 583 drivers/char/hw_random/n2-drv.c np->test_control[1] = base; base 584 drivers/char/hw_random/n2-drv.c np->test_control[2] = base; base 623 drivers/char/hw_random/n2-drv.c u64 base, shift; base 626 drivers/char/hw_random/n2-drv.c base = ((np->accum_cycles << RNG_v1_CTL_WAIT_SHIFT) | base 631 drivers/char/hw_random/n2-drv.c base = ((np->accum_cycles << RNG_v2_CTL_WAIT_SHIFT) | base 643 drivers/char/hw_random/n2-drv.c up->control[esrc] = base | base 647 drivers/char/hw_random/n2-drv.c up->control[3] = base | base 20 drivers/char/hw_random/nomadik-rng.c void __iomem *base = (void __iomem *)rng->priv; base 27 drivers/char/hw_random/nomadik-rng.c *(u16 *)data = __raw_readl(base + 8) & 0xffff; base 39 drivers/char/hw_random/nomadik-rng.c void __iomem *base; base 55 drivers/char/hw_random/nomadik-rng.c base = devm_ioremap(&dev->dev, dev->res.start, base 57 drivers/char/hw_random/nomadik-rng.c if (!base) base 59 drivers/char/hw_random/nomadik-rng.c nmk_rng.priv = (unsigned long)base; base 155 drivers/char/hw_random/omap-rng.c void __iomem *base; base 165 drivers/char/hw_random/omap-rng.c return __raw_readl(priv->base + priv->pdata->regs[reg]); base 171 drivers/char/hw_random/omap-rng.c __raw_writel(val, priv->base + priv->pdata->regs[reg]); base 196 drivers/char/hw_random/omap-rng.c memcpy_fromio(data, priv->base + priv->pdata->regs[RNG_OUTPUT_0_REG], base 460 drivers/char/hw_random/omap-rng.c priv->base = devm_ioremap_resource(dev, res); base 461 drivers/char/hw_random/omap-rng.c if (IS_ERR(priv->base)) { base 462 drivers/char/hw_random/omap-rng.c ret = PTR_ERR(priv->base); base 520 drivers/char/hw_random/omap-rng.c priv->base = NULL; base 37 drivers/char/hw_random/pic32-rng.c void __iomem *base; base 58 drivers/char/hw_random/pic32-rng.c t = readl(priv->base + RNGRCNT) & RCNT_MASK; base 61 drivers/char/hw_random/pic32-rng.c *data = ((u64)readl(priv->base + RNGSEED2) << 32) + base 62 drivers/char/hw_random/pic32-rng.c readl(priv->base + RNGSEED1); base 82 drivers/char/hw_random/pic32-rng.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 83 drivers/char/hw_random/pic32-rng.c if (IS_ERR(priv->base)) base 84 drivers/char/hw_random/pic32-rng.c return PTR_ERR(priv->base); base 96 drivers/char/hw_random/pic32-rng.c writel(v, priv->base + RNGCON); base 119 drivers/char/hw_random/pic32-rng.c writel(0, rng->base + RNGCON); base 43 drivers/char/hw_random/st-rng.c void __iomem *base; base 56 drivers/char/hw_random/st-rng.c status = readl_relaxed(ddata->base + ST_RNG_STATUS_REG); base 67 drivers/char/hw_random/st-rng.c readl_relaxed(ddata->base + ST_RNG_DATA_REG); base 77 drivers/char/hw_random/st-rng.c void __iomem *base; base 85 drivers/char/hw_random/st-rng.c base = devm_ioremap_resource(&pdev->dev, res); base 86 drivers/char/hw_random/st-rng.c if (IS_ERR(base)) base 87 drivers/char/hw_random/st-rng.c return PTR_ERR(base); base 100 drivers/char/hw_random/st-rng.c ddata->base = base; base 32 drivers/char/hw_random/stm32-rng.c void __iomem *base; base 48 drivers/char/hw_random/stm32-rng.c sr = readl_relaxed(priv->base + RNG_SR); base 52 drivers/char/hw_random/stm32-rng.c retval = readl_relaxed_poll_timeout_atomic(priv->base base 65 drivers/char/hw_random/stm32-rng.c writel_relaxed(0, priv->base + RNG_SR); base 69 drivers/char/hw_random/stm32-rng.c *(u32 *)data = readl_relaxed(priv->base + RNG_DR); base 93 drivers/char/hw_random/stm32-rng.c writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR); base 96 drivers/char/hw_random/stm32-rng.c priv->base + RNG_CR); base 99 drivers/char/hw_random/stm32-rng.c writel_relaxed(0, priv->base + RNG_SR); base 109 drivers/char/hw_random/stm32-rng.c writel_relaxed(0, priv->base + RNG_CR); base 129 drivers/char/hw_random/stm32-rng.c priv->base = devm_ioremap_resource(dev, &res); base 130 drivers/char/hw_random/stm32-rng.c if (IS_ERR(priv->base)) base 131 drivers/char/hw_random/stm32-rng.c return PTR_ERR(priv->base); base 30 drivers/char/hw_random/tx4939-rng.c void __iomem *base; base 55 drivers/char/hw_random/tx4939-rng.c static u64 read_rng(void __iomem *base, unsigned int offset) base 57 drivers/char/hw_random/tx4939-rng.c return ____raw_readq(base + offset); base 60 drivers/char/hw_random/tx4939-rng.c static void write_rng(u64 val, void __iomem *base, unsigned int offset) base 62 drivers/char/hw_random/tx4939-rng.c return ____raw_writeq(val, base + offset); base 74 drivers/char/hw_random/tx4939-rng.c if (!(read_rng(rngdev->base, TX4939_RNG_RCSR) base 77 drivers/char/hw_random/tx4939-rng.c read_rng(rngdev->base, TX4939_RNG_ROR(0)); base 79 drivers/char/hw_random/tx4939-rng.c read_rng(rngdev->base, TX4939_RNG_ROR(1)); base 81 drivers/char/hw_random/tx4939-rng.c read_rng(rngdev->base, TX4939_RNG_ROR(2)); base 86 drivers/char/hw_random/tx4939-rng.c rngdev->base, TX4939_RNG_RCSR); base 117 drivers/char/hw_random/tx4939-rng.c rngdev->base = devm_ioremap_resource(&dev->dev, r); base 118 drivers/char/hw_random/tx4939-rng.c if (IS_ERR(rngdev->base)) base 119 drivers/char/hw_random/tx4939-rng.c return PTR_ERR(rngdev->base); base 127 drivers/char/hw_random/tx4939-rng.c write_rng(TX4939_RNG_RCSR_RST, rngdev->base, TX4939_RNG_RCSR); base 128 drivers/char/hw_random/tx4939-rng.c write_rng(0, rngdev->base, TX4939_RNG_RCSR); base 130 drivers/char/hw_random/tx4939-rng.c write_rng(TX4939_RNG_RCSR_ST, rngdev->base, TX4939_RNG_RCSR); base 448 drivers/char/ipmi/bt-bmc.c void __iomem *base; base 455 drivers/char/ipmi/bt-bmc.c base = devm_ioremap_resource(&pdev->dev, res); base 456 drivers/char/ipmi/bt-bmc.c if (IS_ERR(base)) base 457 drivers/char/ipmi/bt-bmc.c return PTR_ERR(base); base 459 drivers/char/ipmi/bt-bmc.c bt_bmc->map = devm_regmap_init_mmio(dev, base, &bt_regmap_cfg); base 497 drivers/char/ipmi/ipmi_si_intf.c static u8 current_global_enables(struct smi_info *smi_info, u8 base, base 27 drivers/char/tpm/eventlog/of.c u64 base; base 56 drivers/char/tpm/eventlog/of.c base = be64_to_cpup((__force __be64 *)basep); base 59 drivers/char/tpm/eventlog/of.c base = *basep; base 67 drivers/char/tpm/eventlog/of.c log->bios_event_log = kmemdup(__va(base), size, GFP_KERNEL); base 144 drivers/char/tpm/tpm_atmel.c atmel_release_region(priv->base, priv->region_size); base 163 drivers/char/tpm/tpm_atmel.c unsigned long base; base 171 drivers/char/tpm/tpm_atmel.c if ((iobase = atmel_get_base_addr(&base, ®ion_size)) == NULL) { base 178 drivers/char/tpm/tpm_atmel.c (base, region_size, "tpm_atmel0") == NULL) ? 0 : 1; base 193 drivers/char/tpm/tpm_atmel.c priv->base = base; base 216 drivers/char/tpm/tpm_atmel.c atmel_release_region(base, base 23 drivers/char/tpm/tpm_atmel.h unsigned long base; base 41 drivers/char/tpm/tpm_atmel.h static void __iomem * atmel_get_base_addr(unsigned long *base, int *region_size) base 78 drivers/char/tpm/tpm_atmel.h *base = address; base 80 drivers/char/tpm/tpm_atmel.h return ioremap(*base, *region_size); base 83 drivers/char/tpm/tpm_atmel.h #define atmel_getb(chip, offset) inb(atmel_get_priv(chip)->base + offset) base 85 drivers/char/tpm/tpm_atmel.h outb(val, atmel_get_priv(chip)->base + offset) base 94 drivers/char/tpm/tpm_atmel.h static inline int tpm_read_index(int base, int index) base 96 drivers/char/tpm/tpm_atmel.h outb(index, base); base 97 drivers/char/tpm/tpm_atmel.h return inb(base+1) & 0xFF; base 125 drivers/char/tpm/tpm_atmel.h static void __iomem * atmel_get_base_addr(unsigned long *base, int *region_size) base 135 drivers/char/tpm/tpm_atmel.h *base = (hi << 8) | lo; base 138 drivers/char/tpm/tpm_atmel.h return ioport_map(*base, *region_size); base 64 drivers/char/tpm/tpm_nsc.c unsigned long base; base 76 drivers/char/tpm/tpm_nsc.c *data = inb(priv->base + NSC_STATUS); base 84 drivers/char/tpm/tpm_nsc.c *data = inb(priv->base + 1); base 100 drivers/char/tpm/tpm_nsc.c status = inb(priv->base + NSC_STATUS); base 102 drivers/char/tpm/tpm_nsc.c status = inb(priv->base + NSC_DATA); base 110 drivers/char/tpm/tpm_nsc.c status = inb(priv->base + NSC_STATUS); base 112 drivers/char/tpm/tpm_nsc.c status = inb(priv->base + NSC_DATA); base 139 drivers/char/tpm/tpm_nsc.c data = inb(priv->base + NSC_DATA); base 156 drivers/char/tpm/tpm_nsc.c *p = inb(priv->base + NSC_DATA); base 165 drivers/char/tpm/tpm_nsc.c data = inb(priv->base + NSC_DATA); base 193 drivers/char/tpm/tpm_nsc.c outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND); base 203 drivers/char/tpm/tpm_nsc.c outb(NSC_COMMAND_NORMAL, priv->base + NSC_COMMAND); base 215 drivers/char/tpm/tpm_nsc.c outb(buf[i], priv->base + NSC_DATA); base 222 drivers/char/tpm/tpm_nsc.c outb(NSC_COMMAND_EOC, priv->base + NSC_COMMAND); base 231 drivers/char/tpm/tpm_nsc.c outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND); base 238 drivers/char/tpm/tpm_nsc.c return inb(priv->base + NSC_STATUS); base 264 drivers/char/tpm/tpm_nsc.c release_region(priv->base, 2); base 276 drivers/char/tpm/tpm_nsc.c static inline int tpm_read_index(int base, int index) base 278 drivers/char/tpm/tpm_nsc.c outb(index, base); base 279 drivers/char/tpm/tpm_nsc.c return inb(base+1) & 0xFF; base 282 drivers/char/tpm/tpm_nsc.c static inline void tpm_write_index(int base, int index, int value) base 284 drivers/char/tpm/tpm_nsc.c outb(index, base); base 285 drivers/char/tpm/tpm_nsc.c outb(value & 0xFF, base+1); base 294 drivers/char/tpm/tpm_nsc.c unsigned long base; base 311 drivers/char/tpm/tpm_nsc.c base = (hi<<8) | lo; base 335 drivers/char/tpm/tpm_nsc.c priv->base = base; base 337 drivers/char/tpm/tpm_nsc.c if (request_region(base, 2, "tpm_nsc0") == NULL ) { base 390 drivers/char/tpm/tpm_nsc.c release_region(base, 2); base 44 drivers/clk/actions/owl-common.c void __iomem *base; base 49 drivers/clk/actions/owl-common.c base = devm_ioremap_resource(&pdev->dev, res); base 50 drivers/clk/actions/owl-common.c if (IS_ERR(base)) base 51 drivers/clk/actions/owl-common.c return PTR_ERR(base); base 53 drivers/clk/actions/owl-common.c regmap = devm_regmap_init_mmio(&pdev->dev, base, &owl_regmap_config); base 62 drivers/clk/axs10x/i2s_pll_clock.c void __iomem *base; base 70 drivers/clk/axs10x/i2s_pll_clock.c writel_relaxed(val, clk->base + reg); base 76 drivers/clk/axs10x/i2s_pll_clock.c return readl_relaxed(clk->base + reg); base 182 drivers/clk/axs10x/i2s_pll_clock.c pll_clk->base = devm_ioremap_resource(dev, mem); base 183 drivers/clk/axs10x/i2s_pll_clock.c if (IS_ERR(pll_clk->base)) base 184 drivers/clk/axs10x/i2s_pll_clock.c return PTR_ERR(pll_clk->base); base 96 drivers/clk/axs10x/pll_clock.c void __iomem *base; base 105 drivers/clk/axs10x/pll_clock.c iowrite32(val, clk->base + reg); base 110 drivers/clk/axs10x/pll_clock.c return ioread32(clk->base + reg); base 233 drivers/clk/axs10x/pll_clock.c pll_clk->base = devm_ioremap_resource(dev, mem); base 234 drivers/clk/axs10x/pll_clock.c if (IS_ERR(pll_clk->base)) base 235 drivers/clk/axs10x/pll_clock.c return PTR_ERR(pll_clk->base); base 283 drivers/clk/axs10x/pll_clock.c pll_clk->base = of_iomap(node, 0); base 284 drivers/clk/axs10x/pll_clock.c if (!pll_clk->base) { base 322 drivers/clk/axs10x/pll_clock.c iounmap(pll_clk->base); base 398 drivers/clk/bcm/clk-bcm2835.c static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, base 410 drivers/clk/bcm/clk-bcm2835.c regset->base = cprman->regs + base; base 70 drivers/clk/bcm/clk-iproc-armpll.c void __iomem *base; base 81 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); base 90 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); base 94 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); base 131 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); base 138 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET); base 156 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET); base 170 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET); base 176 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET); base 205 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); base 212 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET); base 255 drivers/clk/bcm/clk-iproc-armpll.c pll->base = of_iomap(node, 0); base 256 drivers/clk/bcm/clk-iproc-armpll.c if (WARN_ON(!pll->base)) base 280 drivers/clk/bcm/clk-iproc-armpll.c iounmap(pll->base); base 173 drivers/clk/bcm/clk-iproc-pll.c static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, base 178 drivers/clk/bcm/clk-iproc-pll.c writel(val, base + offset); base 181 drivers/clk/bcm/clk-iproc-pll.c (base == pll->status_base || base == pll->control_base))) base 182 drivers/clk/bcm/clk-iproc-pll.c val = readl(base + offset); base 757 drivers/clk/bcm/clk-kona-setup.c if (!ccu->base) base 764 drivers/clk/bcm/clk-kona-setup.c iounmap(ccu->base); base 765 drivers/clk/bcm/clk-kona-setup.c ccu->base = NULL; base 830 drivers/clk/bcm/clk-kona-setup.c ccu->base = ioremap(res.start, ccu->range); base 831 drivers/clk/bcm/clk-kona-setup.c if (!ccu->base) { base 132 drivers/clk/bcm/clk-kona.c return readl(ccu->base + reg_offset); base 139 drivers/clk/bcm/clk-kona.c writel(reg_val, ccu->base + reg_offset); base 479 drivers/clk/bcm/clk-kona.h void __iomem *base; /* base of mapped address space */ base 107 drivers/clk/berlin/berlin2-avpll.c void __iomem *base; base 118 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL0); base 130 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL0); base 135 drivers/clk/berlin/berlin2-avpll.c writel_relaxed(reg, vco->base + VCO_CTRL0); base 145 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL0); base 150 drivers/clk/berlin/berlin2-avpll.c writel_relaxed(reg, vco->base + VCO_CTRL0); base 163 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL1); base 180 drivers/clk/berlin/berlin2-avpll.c int __init berlin2_avpll_vco_register(void __iomem *base, base 191 drivers/clk/berlin/berlin2-avpll.c vco->base = base; base 205 drivers/clk/berlin/berlin2-avpll.c void __iomem *base; base 220 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL10); base 231 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL10); base 233 drivers/clk/berlin/berlin2-avpll.c writel_relaxed(reg, ch->base + VCO_CTRL10); base 243 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL10); base 245 drivers/clk/berlin/berlin2-avpll.c writel_relaxed(reg, ch->base + VCO_CTRL10); base 258 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL30); base 267 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index)); base 273 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index)); base 284 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL11) >> 7; base 294 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL11); base 297 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL12); base 308 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL12); base 311 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL13); base 314 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL14); base 326 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL14); base 329 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL15); base 356 drivers/clk/berlin/berlin2-avpll.c int __init berlin2_avpll_channel_register(void __iomem *base, base 367 drivers/clk/berlin/berlin2-avpll.c ch->base = base; base 14 drivers/clk/berlin/berlin2-avpll.h int berlin2_avpll_vco_register(void __iomem *base, const char *name, base 17 drivers/clk/berlin/berlin2-avpll.h int berlin2_avpll_channel_register(void __iomem *base, const char *name, base 56 drivers/clk/berlin/berlin2-div.c void __iomem *base; base 74 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->gate_offs); base 92 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->gate_offs); base 94 drivers/clk/berlin/berlin2-div.c writel_relaxed(reg, div->base + map->gate_offs); base 111 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->gate_offs); base 113 drivers/clk/berlin/berlin2-div.c writel_relaxed(reg, div->base + map->gate_offs); base 129 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->pll_switch_offs); base 134 drivers/clk/berlin/berlin2-div.c writel_relaxed(reg, div->base + map->pll_switch_offs); base 138 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->pll_select_offs); base 141 drivers/clk/berlin/berlin2-div.c writel_relaxed(reg, div->base + map->pll_select_offs); base 161 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->pll_switch_offs); base 164 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->pll_select_offs); base 186 drivers/clk/berlin/berlin2-div.c divsw = readl_relaxed(div->base + map->div_switch_offs) & base 188 drivers/clk/berlin/berlin2-div.c div3sw = readl_relaxed(div->base + map->div3_switch_offs) & base 200 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->div_select_offs); base 229 drivers/clk/berlin/berlin2-div.c void __iomem *base, const char *name, u8 div_flags, base 244 drivers/clk/berlin/berlin2-div.c div->base = base; base 74 drivers/clk/berlin/berlin2-div.h void __iomem *base, const char *name, u8 div_flags, base 21 drivers/clk/berlin/berlin2-pll.c void __iomem *base; base 49 drivers/clk/berlin/berlin2-pll.c val = readl_relaxed(pll->base + SPLL_CTRL0); base 57 drivers/clk/berlin/berlin2-pll.c val = readl_relaxed(pll->base + SPLL_CTRL1); base 78 drivers/clk/berlin/berlin2-pll.c void __iomem *base, const char *name, base 90 drivers/clk/berlin/berlin2-pll.c pll->base = base; base 20 drivers/clk/berlin/berlin2-pll.h void __iomem *base, const char *name, base 89 drivers/clk/clk-asm9260.c static void __iomem *base; base 271 drivers/clk/clk-asm9260.c base = of_io_request_and_map(np, 0, np->name); base 272 drivers/clk/clk-asm9260.c if (IS_ERR(base)) base 276 drivers/clk/clk-asm9260.c rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000; base 292 drivers/clk/clk-asm9260.c mc->num_parents, mc->flags, base + mc->offset, base 302 drivers/clk/clk-asm9260.c base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock); base 311 drivers/clk/clk-asm9260.c base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED, base 320 drivers/clk/clk-asm9260.c gd->parent_name, gd->flags, base + gd->reg, base 338 drivers/clk/clk-asm9260.c iounmap(base); base 46 drivers/clk/clk-axi-clkgen.c void __iomem *base; base 163 drivers/clk/clk-axi-clkgen.c writel(val, axi_clkgen->base + reg); base 169 drivers/clk/clk-axi-clkgen.c *val = readl(axi_clkgen->base + reg); base 431 drivers/clk/clk-axi-clkgen.c axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem); base 432 drivers/clk/clk-axi-clkgen.c if (IS_ERR(axi_clkgen->base)) base 433 drivers/clk/clk-axi-clkgen.c return PTR_ERR(axi_clkgen->base); base 543 drivers/clk/clk-axm5516.c void __iomem *base; base 551 drivers/clk/clk-axm5516.c base = devm_ioremap_resource(dev, res); base 552 drivers/clk/clk-axm5516.c if (IS_ERR(base)) base 553 drivers/clk/clk-axm5516.c return PTR_ERR(base); base 555 drivers/clk/clk-axm5516.c regmap = devm_regmap_init_mmio(dev, base, &axmclk_regmap_config); base 47 drivers/clk/clk-clps711x.c void __iomem *base; base 51 drivers/clk/clk-clps711x.c base = of_iomap(np, 0); base 52 drivers/clk/clk-clps711x.c BUG_ON(!base); base 62 drivers/clk/clk-clps711x.c tmp = readl(base + CLPS711X_PLLR) >> 24; base 68 drivers/clk/clk-clps711x.c tmp = readl(base + CLPS711X_SYSFLG2); base 86 drivers/clk/clk-clps711x.c if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB) base 93 drivers/clk/clk-clps711x.c tmp = readl(base + CLPS711X_SYSCON1); base 104 drivers/clk/clk-clps711x.c writel(tmp, base + CLPS711X_SYSCON1); base 118 drivers/clk/clk-clps711x.c base + CLPS711X_SYSCON1, 5, 1, 0, base 122 drivers/clk/clk-clps711x.c base + CLPS711X_SYSCON1, 7, 1, 0, base 130 drivers/clk/clk-clps711x.c base + CLPS711X_SYSCON1, 16, 2, 0, base 22 drivers/clk/clk-efm32gg.c void __iomem *base; base 36 drivers/clk/clk-efm32gg.c base = of_iomap(np, 0); base 37 drivers/clk/clk-efm32gg.c if (!base) { base 46 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL); base 48 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL); base 50 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL); base 52 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL); base 54 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL); base 56 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL); base 58 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL); base 60 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 7, 0, NULL); base 62 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 8, 0, NULL); base 64 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 9, 0, NULL); base 66 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 10, 0, NULL); base 68 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 11, 0, NULL); base 70 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 12, 0, NULL); base 72 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 13, 0, NULL); base 74 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 14, 0, NULL); base 76 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 15, 0, NULL); base 78 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 16, 0, NULL); base 80 drivers/clk/clk-efm32gg.c "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL); base 22 drivers/clk/clk-fixed-mmio.c void __iomem *base; base 26 drivers/clk/clk-fixed-mmio.c base = of_iomap(node, 0); base 27 drivers/clk/clk-fixed-mmio.c if (!base) { base 32 drivers/clk/clk-fixed-mmio.c freq = readl(base); base 33 drivers/clk/clk-fixed-mmio.c iounmap(base); base 272 drivers/clk/clk-gemini.c void __iomem *base; base 290 drivers/clk/clk-gemini.c base = devm_ioremap_resource(dev, res); base 291 drivers/clk/clk-gemini.c if (IS_ERR(base)) base 292 drivers/clk/clk-gemini.c return PTR_ERR(base); base 347 drivers/clk/clk-gemini.c base + GEMINI_GLOBAL_CLOCK_CONTROL, base 500 drivers/clk/clk-milbeaut.c void __iomem *base) base 510 drivers/clk/clk-milbeaut.c write_valid_reg = base + CLKSEL(11); base 517 drivers/clk/clk-milbeaut.c base + factors->offset, base 544 drivers/clk/clk-milbeaut.c void __iomem *base) base 552 drivers/clk/clk-milbeaut.c base + factors->offset, factors->shift, base 566 drivers/clk/clk-milbeaut.c void __iomem *base; base 570 drivers/clk/clk-milbeaut.c base = devm_ioremap_resource(dev, res); base 571 drivers/clk/clk-milbeaut.c if (IS_ERR(base)) base 572 drivers/clk/clk-milbeaut.c return PTR_ERR(base); base 578 drivers/clk/clk-milbeaut.c m10v_clk_data, base); base 586 drivers/clk/clk-milbeaut.c m10v_clk_data, base); base 613 drivers/clk/clk-milbeaut.c void __iomem *base; base 624 drivers/clk/clk-milbeaut.c base = of_iomap(np, 0); base 625 drivers/clk/clk-milbeaut.c if (!base) { base 633 drivers/clk/clk-milbeaut.c iounmap(base); base 656 drivers/clk/clk-milbeaut.c base + CLKSEL(1), 0, 3, 0, rclk_table, base 21 drivers/clk/clk-moxart.c void __iomem *base; base 31 drivers/clk/clk-moxart.c base = of_iomap(node, 0); base 32 drivers/clk/clk-moxart.c if (!base) { base 37 drivers/clk/clk-moxart.c mul = readl(base + 0x30) >> 3 & 0x3f; base 38 drivers/clk/clk-moxart.c iounmap(base); base 60 drivers/clk/clk-moxart.c void __iomem *base; base 71 drivers/clk/clk-moxart.c base = of_iomap(node, 0); base 72 drivers/clk/clk-moxart.c if (!base) { base 77 drivers/clk/clk-moxart.c val = readl(base + 0xc) >> 4 & 0x7; base 78 drivers/clk/clk-moxart.c iounmap(base); base 398 drivers/clk/clk-stm32f4.c static void __iomem *base; base 424 drivers/clk/clk-stm32f4.c if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) base 436 drivers/clk/clk-stm32f4.c if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) base 641 drivers/clk/clk-stm32f4.c n = (readl(base + pll->offset) >> 6) & 0x1ff; base 680 drivers/clk/clk-stm32f4.c val = readl(base + pll->offset) & ~(0x1ff << 6); base 682 drivers/clk/clk-stm32f4.c writel(val | ((n & 0x1ff) << 6), base + pll->offset); base 814 drivers/clk/clk-stm32f4.c pll->gate.reg = base + STM32F4_RCC_CR; base 821 drivers/clk/clk-stm32f4.c pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; base 823 drivers/clk/clk-stm32f4.c reg = base + pll->offset; base 907 drivers/clk/clk-stm32f4.c val = readl(base + STM32F4_RCC_BDCR); base 908 drivers/clk/clk-stm32f4.c writel(val | BIT(16), base + STM32F4_RCC_BDCR); base 909 drivers/clk/clk-stm32f4.c writel(val & ~BIT(16), base + STM32F4_RCC_BDCR); base 1645 drivers/clk/clk-stm32f4.c gate->reg = base + offset_gate; base 1660 drivers/clk/clk-stm32f4.c mux->reg = base + offset_mux; base 1697 drivers/clk/clk-stm32f4.c base = of_iomap(np, 0); base 1698 drivers/clk/clk-stm32f4.c if (!base) { base 1735 drivers/clk/clk-stm32f4.c base + STM32F4_RCC_APB2ENR, 29, base 1746 drivers/clk/clk-stm32f4.c base + STM32F4_RCC_PLLCFGR, 22, 1, 0, base 1749 drivers/clk/clk-stm32f4.c pllm = readl(base + STM32F4_RCC_PLLCFGR) & 0x3f; base 1772 drivers/clk/clk-stm32f4.c base + post_div->offset, base 1788 drivers/clk/clk-stm32f4.c base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock); base 1791 drivers/clk/clk-stm32f4.c CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, base 1795 drivers/clk/clk-stm32f4.c CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, base 1801 drivers/clk/clk-stm32f4.c CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, base 1826 drivers/clk/clk-stm32f4.c base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock); base 1836 drivers/clk/clk-stm32f4.c base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock); base 1844 drivers/clk/clk-stm32f4.c base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock); base 1852 drivers/clk/clk-stm32f4.c 0, base + STM32F4_RCC_CFGR, 16, 5, 0, base 1861 drivers/clk/clk-stm32f4.c base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock); base 1903 drivers/clk/clk-stm32f4.c iounmap(base); base 52 drivers/clk/clk-stm32h7.c static void __iomem *base; base 375 drivers/clk/clk-stm32h7.c mux = _get_cmux(base + cfg->mux->offset, base 388 drivers/clk/clk-stm32h7.c div = _get_cdiv(base + cfg->div->offset, base 401 drivers/clk/clk-stm32h7.c gate = _get_cgate(base + cfg->gate->offset, base 440 drivers/clk/clk-stm32h7.c timpre = (readl(base + RCC_CFGR) >> 15) & 0x01; base 442 drivers/clk/clk-stm32h7.c prescaler = (readl(base + RCC_D2CFGR) >> dppre_shift) & 0x03; base 514 drivers/clk/clk-stm32h7.c "sys_ck", CLK_IGNORE_UNUSED, base + RCC_D1CFGR, 8, 4, 0, base 518 drivers/clk/clk-stm32h7.c CLK_IGNORE_UNUSED, base + RCC_D1CFGR, 0, 4, 0, base 528 drivers/clk/clk-stm32h7.c base + RCC_D1CFGR, 4, 3, 0, base 534 drivers/clk/clk-stm32h7.c base + RCC_D2CFGR, 4, 3, 0, base 543 drivers/clk/clk-stm32h7.c base + RCC_D2CFGR, 8, 3, 0, ppre_div_table, base 552 drivers/clk/clk-stm32h7.c base + RCC_D3CFGR, 4, 3, 0, base 812 drivers/clk/clk-stm32h7.c rgate->gate.reg = base + RCC_CR; base 817 drivers/clk/clk-stm32h7.c div->mreg = base + RCC_PLLCKSELR; base 820 drivers/clk/clk-stm32h7.c div->nreg = base + cfg->offset_divr; base 824 drivers/clk/clk-stm32h7.c div->freg_status = base + RCC_PLLCFGR; base 826 drivers/clk/clk-stm32h7.c div->freg_value = base + cfg->offset_frac; base 1217 drivers/clk/clk-stm32h7.c base = of_iomap(np, 0); base 1218 drivers/clk/clk-stm32h7.c if (!base) { base 1252 drivers/clk/clk-stm32h7.c base + RCC_CR, 3, 2, CLK_DIVIDER_POWER_OF_TWO, base 1256 drivers/clk/clk-stm32h7.c base + RCC_CFGR, 8, 6, CLK_DIVIDER_ONE_BASED | base 1267 drivers/clk/clk-stm32h7.c stm32_mclk[n].offset + base, base 1280 drivers/clk/clk-stm32h7.c stm32_oclk[n].gate_offset + base, base 1289 drivers/clk/clk-stm32h7.c RCC_CR + base, base 1297 drivers/clk/clk-stm32h7.c RCC_BDCR + base, base 1337 drivers/clk/clk-stm32h7.c pclk[n].flags, base + pclk[n].gate_offset, base 322 drivers/clk/clk-stm32mp1.c void __iomem *base, spinlock_t *lock, base 382 drivers/clk/clk-stm32mp1.c void __iomem *base, spinlock_t *lock, base 391 drivers/clk/clk-stm32mp1.c gate_cfg->reg_off + base, base 400 drivers/clk/clk-stm32mp1.c void __iomem *base, spinlock_t *lock, base 413 drivers/clk/clk-stm32mp1.c void __iomem *base, spinlock_t *lock, base 422 drivers/clk/clk-stm32mp1.c div_cfg->reg_off + base, base 433 drivers/clk/clk-stm32mp1.c void __iomem *base, spinlock_t *lock, base 440 drivers/clk/clk-stm32mp1.c mux_cfg->reg_off + base, mux_cfg->shift, base 472 drivers/clk/clk-stm32mp1.c static struct clk_hw *_get_stm32_mux(void __iomem *base, base 485 drivers/clk/clk-stm32mp1.c mmux->mux.reg = cfg->mux->reg_off + base; base 500 drivers/clk/clk-stm32mp1.c mux->reg = cfg->mux->reg_off + base; base 512 drivers/clk/clk-stm32mp1.c static struct clk_hw *_get_stm32_div(void __iomem *base, base 523 drivers/clk/clk-stm32mp1.c div->reg = cfg->div->reg_off + base; base 534 drivers/clk/clk-stm32mp1.c _get_stm32_gate(void __iomem *base, base 546 drivers/clk/clk-stm32mp1.c mgate->gate.reg = cfg->gate->reg_off + base; base 561 drivers/clk/clk-stm32mp1.c gate->reg = cfg->gate->reg_off + base; base 577 drivers/clk/clk-stm32mp1.c void __iomem *base, base 595 drivers/clk/clk-stm32mp1.c hw = _get_stm32_gate(base, cfg, lock); base 611 drivers/clk/clk-stm32mp1.c int num_parents, void __iomem *base, base 626 drivers/clk/clk-stm32mp1.c mux_hw = _get_stm32_mux(base, cfg->mux, lock); base 637 drivers/clk/clk-stm32mp1.c div_hw = _get_stm32_div(base, cfg->div, lock); base 648 drivers/clk/clk-stm32mp1.c gate_hw = _get_stm32_gate(base, cfg->gate, lock); base 1040 drivers/clk/clk-stm32mp1.c void __iomem *base, spinlock_t *lock, base 1046 drivers/clk/clk-stm32mp1.c base + stm_pll_cfg->offset, cfg->flags, lock); base 1056 drivers/clk/clk-stm32mp1.c void __iomem *base, spinlock_t *lock, base 1062 drivers/clk/clk-stm32mp1.c cktim_cfg->offset_apbdiv + base, base 1063 drivers/clk/clk-stm32mp1.c cktim_cfg->offset_timpre + base, lock); base 1069 drivers/clk/clk-stm32mp1.c void __iomem *base, spinlock_t *lock, base 1076 drivers/clk/clk-stm32mp1.c base, base 1084 drivers/clk/clk-stm32mp1.c void __iomem *base, spinlock_t *lock, base 1088 drivers/clk/clk-stm32mp1.c cfg->num_parents, base, cfg->cfg, base 2021 drivers/clk/clk-stm32mp1.c void __iomem *base, spinlock_t *lock, base 2030 drivers/clk/clk-stm32mp1.c hw = (*cfg->func)(dev, clk_data, base, lock, cfg); base 2044 drivers/clk/clk-stm32mp1.c void __iomem *base, base 2076 drivers/clk/clk-stm32mp1.c err = stm32_register_hw_clk(NULL, clk_data, base, &rlock, base 2093 drivers/clk/clk-stm32mp1.c void __iomem *base; base 2095 drivers/clk/clk-stm32mp1.c base = of_iomap(np, 0); base 2096 drivers/clk/clk-stm32mp1.c if (!base) { base 2102 drivers/clk/clk-stm32mp1.c if (stm32_rcc_init(np, base, stm32mp1_match_data)) { base 2103 drivers/clk/clk-stm32mp1.c iounmap(base); base 22 drivers/clk/clk-tango4.c static void __init make_pll(int idx, const char *parent, void __iomem *base) base 28 drivers/clk/clk-tango4.c val = readl(base + idx * 8); base 36 drivers/clk/clk-tango4.c static void __init make_cd(int idx, void __iomem *base) base 42 drivers/clk/clk-tango4.c val = readl(base + idx * 8); base 53 drivers/clk/clk-tango4.c void __iomem *base = of_iomap(np, 0); base 56 drivers/clk/clk-tango4.c if (!base) base 59 drivers/clk/clk-tango4.c if (readl(base + CPUCLK_DIV) & DIV_BYPASS) base 62 drivers/clk/clk-tango4.c if (readl(base + SYSCLK_DIV) & DIV_BYPASS) base 65 drivers/clk/clk-tango4.c writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */ base 67 drivers/clk/clk-tango4.c make_pll(0, parent, base); base 68 drivers/clk/clk-tango4.c make_pll(1, parent, base); base 69 drivers/clk/clk-tango4.c make_pll(2, parent, base); base 70 drivers/clk/clk-tango4.c make_cd(2, base + 0x80); base 71 drivers/clk/clk-tango4.c make_cd(6, base + 0x80); base 74 drivers/clk/clk-tango4.c base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL); base 1179 drivers/clk/clk-u300.c void __init u300_clk_init(void __iomem *base) base 1183 drivers/clk/clk-u300.c syscon_vbase = base; base 40 drivers/clk/davinci/pll-da830.c int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 44 drivers/clk/davinci/pll-da830.c davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip); base 46 drivers/clk/davinci/pll-da830.c clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); base 50 drivers/clk/davinci/pll-da830.c clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); base 53 drivers/clk/davinci/pll-da830.c clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); base 57 drivers/clk/davinci/pll-da830.c clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); base 60 drivers/clk/davinci/pll-da830.c clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); base 63 drivers/clk/davinci/pll-da830.c clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); base 65 drivers/clk/davinci/pll-da830.c clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base); base 89 drivers/clk/davinci/pll-da850.c int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 93 drivers/clk/davinci/pll-da850.c davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip); base 95 drivers/clk/davinci/pll-da850.c clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base); base 98 drivers/clk/davinci/pll-da850.c clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); base 103 drivers/clk/davinci/pll-da850.c clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); base 106 drivers/clk/davinci/pll-da850.c clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); base 110 drivers/clk/davinci/pll-da850.c davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); base 112 drivers/clk/davinci/pll-da850.c clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); base 115 drivers/clk/davinci/pll-da850.c davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); base 117 drivers/clk/davinci/pll-da850.c davinci_pll_auxclk_register(dev, "pll0_auxclk", base); base 126 drivers/clk/davinci/pll-da850.c davinci_pll_obsclk_register(dev, &da850_pll0_obsclk_info, base); base 144 drivers/clk/davinci/pll-da850.c void __iomem *base; base 147 drivers/clk/davinci/pll-da850.c base = of_iomap(node, 0); base 148 drivers/clk/davinci/pll-da850.c if (!base) { base 157 drivers/clk/davinci/pll-da850.c da850_pll0_sysclk_info, 7, base, cfgchip); base 198 drivers/clk/davinci/pll-da850.c int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 202 drivers/clk/davinci/pll-da850.c davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip); base 204 drivers/clk/davinci/pll-da850.c davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); base 206 drivers/clk/davinci/pll-da850.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base); base 209 drivers/clk/davinci/pll-da850.c davinci_pll_sysclk_register(dev, &pll1_sysclk3, base); base 211 drivers/clk/davinci/pll-da850.c davinci_pll_obsclk_register(dev, &da850_pll1_obsclk_info, base); base 223 drivers/clk/davinci/pll-da850.c int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 227 drivers/clk/davinci/pll-da850.c da850_pll1_sysclk_info, 3, base, cfgchip); base 31 drivers/clk/davinci/pll-dm355.c int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 35 drivers/clk/davinci/pll-dm355.c davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base, cfgchip); base 37 drivers/clk/davinci/pll-dm355.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); base 40 drivers/clk/davinci/pll-dm355.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base); base 43 drivers/clk/davinci/pll-dm355.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base); base 46 drivers/clk/davinci/pll-dm355.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base); base 49 drivers/clk/davinci/pll-dm355.c clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base); base 52 drivers/clk/davinci/pll-dm355.c davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base); base 68 drivers/clk/davinci/pll-dm355.c int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 70 drivers/clk/davinci/pll-dm355.c davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base, cfgchip); base 72 drivers/clk/davinci/pll-dm355.c davinci_pll_sysclk_register(dev, &pll2_sysclk1, base); base 74 drivers/clk/davinci/pll-dm355.c davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base); base 60 drivers/clk/davinci/pll-dm365.c int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 64 drivers/clk/davinci/pll-dm365.c davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip); base 66 drivers/clk/davinci/pll-dm365.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); base 69 drivers/clk/davinci/pll-dm365.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base); base 72 drivers/clk/davinci/pll-dm365.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base); base 75 drivers/clk/davinci/pll-dm365.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base); base 78 drivers/clk/davinci/pll-dm365.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base); base 81 drivers/clk/davinci/pll-dm365.c davinci_pll_sysclk_register(dev, &pll1_sysclk6, base); base 83 drivers/clk/davinci/pll-dm365.c davinci_pll_sysclk_register(dev, &pll1_sysclk7, base); base 85 drivers/clk/davinci/pll-dm365.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk8, base); base 88 drivers/clk/davinci/pll-dm365.c davinci_pll_sysclk_register(dev, &pll1_sysclk9, base); base 90 drivers/clk/davinci/pll-dm365.c clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base); base 93 drivers/clk/davinci/pll-dm365.c davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base); base 95 drivers/clk/davinci/pll-dm365.c davinci_pll_obsclk_register(dev, &dm365_pll1_obsclk_info, base); base 123 drivers/clk/davinci/pll-dm365.c int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 127 drivers/clk/davinci/pll-dm365.c davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base, cfgchip); base 129 drivers/clk/davinci/pll-dm365.c davinci_pll_sysclk_register(dev, &pll2_sysclk1, base); base 131 drivers/clk/davinci/pll-dm365.c clk = davinci_pll_sysclk_register(dev, &pll2_sysclk2, base); base 134 drivers/clk/davinci/pll-dm365.c davinci_pll_sysclk_register(dev, &pll2_sysclk3, base); base 136 drivers/clk/davinci/pll-dm365.c clk = davinci_pll_sysclk_register(dev, &pll2_sysclk4, base); base 139 drivers/clk/davinci/pll-dm365.c davinci_pll_sysclk_register(dev, &pll2_sysclk5, base); base 141 drivers/clk/davinci/pll-dm365.c davinci_pll_auxclk_register(dev, "pll2_auxclk", base); base 143 drivers/clk/davinci/pll-dm365.c davinci_pll_obsclk_register(dev, &dm365_pll2_obsclk_info, base); base 31 drivers/clk/davinci/pll-dm644x.c int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 35 drivers/clk/davinci/pll-dm644x.c davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base, cfgchip); base 37 drivers/clk/davinci/pll-dm644x.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); base 40 drivers/clk/davinci/pll-dm644x.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base); base 43 drivers/clk/davinci/pll-dm644x.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base); base 46 drivers/clk/davinci/pll-dm644x.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base); base 49 drivers/clk/davinci/pll-dm644x.c clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base); base 52 drivers/clk/davinci/pll-dm644x.c davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base); base 70 drivers/clk/davinci/pll-dm644x.c int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 72 drivers/clk/davinci/pll-dm644x.c davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base, cfgchip); base 74 drivers/clk/davinci/pll-dm644x.c davinci_pll_sysclk_register(dev, &pll2_sysclk1, base); base 76 drivers/clk/davinci/pll-dm644x.c davinci_pll_sysclk_register(dev, &pll2_sysclk2, base); base 78 drivers/clk/davinci/pll-dm644x.c davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base); base 33 drivers/clk/davinci/pll-dm646x.c int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 37 drivers/clk/davinci/pll-dm646x.c davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base, cfgchip); base 39 drivers/clk/davinci/pll-dm646x.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); base 42 drivers/clk/davinci/pll-dm646x.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base); base 45 drivers/clk/davinci/pll-dm646x.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base); base 49 drivers/clk/davinci/pll-dm646x.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base); base 52 drivers/clk/davinci/pll-dm646x.c clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base); base 55 drivers/clk/davinci/pll-dm646x.c davinci_pll_sysclk_register(dev, &pll1_sysclk6, base); base 57 drivers/clk/davinci/pll-dm646x.c davinci_pll_sysclk_register(dev, &pll1_sysclk8, base); base 59 drivers/clk/davinci/pll-dm646x.c davinci_pll_sysclk_register(dev, &pll1_sysclk9, base); base 61 drivers/clk/davinci/pll-dm646x.c davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base); base 63 drivers/clk/davinci/pll-dm646x.c davinci_pll_auxclk_register(dev, "pll1_auxclk", base); base 78 drivers/clk/davinci/pll-dm646x.c int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) base 80 drivers/clk/davinci/pll-dm646x.c davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base, cfgchip); base 82 drivers/clk/davinci/pll-dm646x.c davinci_pll_sysclk_register(dev, &pll2_sysclk1, base); base 106 drivers/clk/davinci/pll.c void __iomem *base; base 122 drivers/clk/davinci/pll.c mult = readl(pll->base + PLLM) & pll->pllm_mask; base 188 drivers/clk/davinci/pll.c writel(mult - 1, pll->base + PLLM); base 214 drivers/clk/davinci/pll.c mult = readl(pll->base + PLLM) & pll->pllm_mask; base 290 drivers/clk/davinci/pll.c void __iomem *base; base 314 drivers/clk/davinci/pll.c ctrl = readl(pll->base + PLLCTL); base 319 drivers/clk/davinci/pll.c writel(ctrl, pll->base + PLLCTL); base 325 drivers/clk/davinci/pll.c writel(ctrl, pll->base + PLLCTL); base 331 drivers/clk/davinci/pll.c writel(ctrl, pll->base + PLLCTL); base 337 drivers/clk/davinci/pll.c writel(ctrl, pll->base + PLLCTL); base 369 drivers/clk/davinci/pll.c void __iomem *base, base 419 drivers/clk/davinci/pll.c parent_name, base + PREDIV, fixed, flags); base 459 drivers/clk/davinci/pll.c pllout->base = base; base 485 drivers/clk/davinci/pll.c parent_name, base + POSTDIV, fixed, flags); base 509 drivers/clk/davinci/pll.c pllen->base = base; base 545 drivers/clk/davinci/pll.c void __iomem *base) base 547 drivers/clk/davinci/pll.c return clk_register_gate(dev, name, OSCIN_CLK_NAME, 0, base + CKEN, base 559 drivers/clk/davinci/pll.c void __iomem *base) base 561 drivers/clk/davinci/pll.c return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV, base 575 drivers/clk/davinci/pll.c void __iomem *base) base 588 drivers/clk/davinci/pll.c mux->reg = base + OCSEL; base 598 drivers/clk/davinci/pll.c gate->reg = base + CKEN; base 607 drivers/clk/davinci/pll.c divider->reg = base + OSCDIV; base 612 drivers/clk/davinci/pll.c oscdiv = readl(base + OSCDIV); base 614 drivers/clk/davinci/pll.c writel(oscdiv, base + OSCDIV); base 651 drivers/clk/davinci/pll.c pllcmd = readl(pll->base + PLLCMD); base 653 drivers/clk/davinci/pll.c writel(pllcmd, pll->base + PLLCMD); base 658 drivers/clk/davinci/pll.c pllstat = readl(pll->base + PLLSTAT); base 679 drivers/clk/davinci/pll.c void __iomem *base) base 699 drivers/clk/davinci/pll.c gate->reg = base + reg; base 708 drivers/clk/davinci/pll.c divider->reg = base + reg; base 750 drivers/clk/davinci/pll.c void __iomem *base, base 762 drivers/clk/davinci/pll.c clk = davinci_pll_clk_register(dev, info, parent_name, base, cfgchip); base 800 drivers/clk/davinci/pll.c clk = davinci_pll_sysclk_register(dev, *div_info, base); base 817 drivers/clk/davinci/pll.c clk = davinci_pll_auxclk_register(dev, child_name, base); base 829 drivers/clk/davinci/pll.c clk = davinci_pll_obsclk_register(dev, obsclk_info, base); base 904 drivers/clk/davinci/pll.c typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base, base 914 drivers/clk/davinci/pll.c void __iomem *base; base 934 drivers/clk/davinci/pll.c base = devm_ioremap_resource(dev, res); base 935 drivers/clk/davinci/pll.c if (IS_ERR(base)) base 936 drivers/clk/davinci/pll.c return PTR_ERR(base); base 938 drivers/clk/davinci/pll.c return pll_init(dev, base, pdata->cfgchip); base 1006 drivers/clk/davinci/pll.c regset->base = pll->base; base 98 drivers/clk/davinci/pll.h void __iomem *base, base 102 drivers/clk/davinci/pll.h void __iomem *base); base 105 drivers/clk/davinci/pll.h void __iomem *base); base 109 drivers/clk/davinci/pll.h void __iomem *base); base 113 drivers/clk/davinci/pll.h void __iomem *base); base 120 drivers/clk/davinci/pll.h void __iomem *base, base 126 drivers/clk/davinci/pll.h int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 128 drivers/clk/davinci/pll.h int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 131 drivers/clk/davinci/pll.h int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 134 drivers/clk/davinci/pll.h int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 137 drivers/clk/davinci/pll.h int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 41 drivers/clk/davinci/psc-da830.c static int da830_psc0_init(struct device *dev, void __iomem *base) base 43 drivers/clk/davinci/psc-da830.c return davinci_psc_register_clocks(dev, da830_psc0_info, 16, base); base 103 drivers/clk/davinci/psc-da830.c static int da830_psc1_init(struct device *dev, void __iomem *base) base 105 drivers/clk/davinci/psc-da830.c return davinci_psc_register_clocks(dev, da830_psc1_info, 32, base); base 73 drivers/clk/davinci/psc-da850.c static int da850_psc0_init(struct device *dev, void __iomem *base) base 77 drivers/clk/davinci/psc-da850.c return davinci_psc_register_clocks(dev, da850_psc0_info, 16, base); base 80 drivers/clk/davinci/psc-da850.c static int of_da850_psc0_init(struct device *dev, void __iomem *base) base 82 drivers/clk/davinci/psc-da850.c return of_davinci_psc_clk_init(dev, da850_psc0_info, 16, base); base 129 drivers/clk/davinci/psc-da850.c static int da850_psc1_init(struct device *dev, void __iomem *base) base 131 drivers/clk/davinci/psc-da850.c return davinci_psc_register_clocks(dev, da850_psc1_info, 32, base); base 134 drivers/clk/davinci/psc-da850.c static int of_da850_psc1_init(struct device *dev, void __iomem *base) base 136 drivers/clk/davinci/psc-da850.c return of_davinci_psc_clk_init(dev, da850_psc1_info, 32, base); base 72 drivers/clk/davinci/psc-dm355.c int dm355_psc_init(struct device *dev, void __iomem *base) base 74 drivers/clk/davinci/psc-dm355.c return davinci_psc_register_clocks(dev, dm355_psc_info, 42, base); base 91 drivers/clk/davinci/psc-dm365.c int dm365_psc_init(struct device *dev, void __iomem *base) base 93 drivers/clk/davinci/psc-dm365.c return davinci_psc_register_clocks(dev, dm365_psc_info, 52, base); base 68 drivers/clk/davinci/psc-dm644x.c int dm644x_psc_init(struct device *dev, void __iomem *base) base 70 drivers/clk/davinci/psc-dm644x.c return davinci_psc_register_clocks(dev, dm644x_psc_info, 41, base); base 63 drivers/clk/davinci/psc-dm646x.c int dm646x_psc_init(struct device *dev, void __iomem *base) base 65 drivers/clk/davinci/psc-dm646x.c return davinci_psc_register_clocks(dev, dm646x_psc_info, 46, base); base 363 drivers/clk/davinci/psc.c void __iomem *base) base 400 drivers/clk/davinci/psc.c regmap = regmap_init_mmio(dev, base, &davinci_psc_regmap_config); base 456 drivers/clk/davinci/psc.c void __iomem *base) base 460 drivers/clk/davinci/psc.c psc = __davinci_psc_register_clocks(dev, info, num_clks, base); base 481 drivers/clk/davinci/psc.c void __iomem *base) base 486 drivers/clk/davinci/psc.c psc = __davinci_psc_register_clocks(dev, info, num_clks, base); base 535 drivers/clk/davinci/psc.c void __iomem *base; base 550 drivers/clk/davinci/psc.c base = devm_ioremap_resource(dev, res); base 551 drivers/clk/davinci/psc.c if (IS_ERR(base)) base 552 drivers/clk/davinci/psc.c return PTR_ERR(base); base 559 drivers/clk/davinci/psc.c return init_data->psc_init(dev, base); base 82 drivers/clk/davinci/psc.h void __iomem *base); base 87 drivers/clk/davinci/psc.h void __iomem *base); base 94 drivers/clk/davinci/psc.h int (*psc_init)(struct device *dev, void __iomem *base); base 412 drivers/clk/hisilicon/clk-hi3620.c void __iomem *base, struct device_node *np) base 430 drivers/clk/hisilicon/clk-hi3620.c mclk->clken_reg = base + mmc_clk->clken_reg; base 432 drivers/clk/hisilicon/clk-hi3620.c mclk->div_reg = base + mmc_clk->div_reg; base 435 drivers/clk/hisilicon/clk-hi3620.c mclk->drv_reg = base + mmc_clk->drv_reg; base 438 drivers/clk/hisilicon/clk-hi3620.c mclk->sam_reg = base + mmc_clk->sam_reg; base 450 drivers/clk/hisilicon/clk-hi3620.c void __iomem *base; base 459 drivers/clk/hisilicon/clk-hi3620.c base = of_iomap(node, 0); base 460 drivers/clk/hisilicon/clk-hi3620.c if (!base) { base 476 drivers/clk/hisilicon/clk-hi3620.c hisi_register_clk_mmc(mmc_clk, base, node); base 95 drivers/clk/hisilicon/clk-hisi-phase.c void __iomem *base, spinlock_t *lock) base 110 drivers/clk/hisilicon/clk-hisi-phase.c phase->reg = base + clks->offset; base 256 drivers/clk/hisilicon/clk-hix5hd2.c void __iomem *base = data->base; base 279 drivers/clk/hisilicon/clk-hix5hd2.c p_clk->ctrl_reg = base + clks[i].ctrl_reg; base 282 drivers/clk/hisilicon/clk-hix5hd2.c p_clk->phy_reg = base + clks[i].phy_reg; base 40 drivers/clk/hisilicon/clk.c clk_data->base = devm_ioremap(&pdev->dev, base 42 drivers/clk/hisilicon/clk.c if (!clk_data->base) base 63 drivers/clk/hisilicon/clk.c void __iomem *base; base 65 drivers/clk/hisilicon/clk.c base = of_iomap(np, 0); base 66 drivers/clk/hisilicon/clk.c if (!base) { base 75 drivers/clk/hisilicon/clk.c clk_data->base = base; base 154 drivers/clk/hisilicon/clk.c void __iomem *base = data->base; base 163 drivers/clk/hisilicon/clk.c base + clks[i].offset, clks[i].shift, base 192 drivers/clk/hisilicon/clk.c void __iomem *base = data->base; base 197 drivers/clk/hisilicon/clk.c clk = clk_register_hisi_phase(dev, &clks[i], base, base 216 drivers/clk/hisilicon/clk.c void __iomem *base = data->base; base 223 drivers/clk/hisilicon/clk.c base + clks[i].offset, base 254 drivers/clk/hisilicon/clk.c void __iomem *base = data->base; base 261 drivers/clk/hisilicon/clk.c base + clks[i].offset, base 291 drivers/clk/hisilicon/clk.c void __iomem *base = data->base; base 298 drivers/clk/hisilicon/clk.c base + clks[i].offset, base 320 drivers/clk/hisilicon/clk.c void __iomem *base = data->base; base 327 drivers/clk/hisilicon/clk.c base + clks[i].offset, base 23 drivers/clk/hisilicon/clk.h void __iomem *base; base 124 drivers/clk/hisilicon/clk.h void __iomem *base, spinlock_t *lock); base 38 drivers/clk/imx/clk-frac-pll.c void __iomem *base; base 47 drivers/clk/imx/clk-frac-pll.c return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0, base 56 drivers/clk/imx/clk-frac-pll.c if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK)) base 60 drivers/clk/imx/clk-frac-pll.c return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0, base 69 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); base 71 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); base 81 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); base 83 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); base 91 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); base 103 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); base 105 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG1); base 171 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG1); base 174 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG1); base 176 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); base 178 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); base 181 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); base 183 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); base 188 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); base 190 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); base 205 drivers/clk/imx/clk-frac-pll.c void __iomem *base) base 222 drivers/clk/imx/clk-frac-pll.c pll->base = base; base 64 drivers/clk/imx/clk-imx31.c static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref) base 69 drivers/clk/imx/clk-imx31.c clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); base 70 drivers/clk/imx/clk-imx31.c clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); base 71 drivers/clk/imx/clk-imx31.c clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); base 72 drivers/clk/imx/clk-imx31.c clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel)); base 73 drivers/clk/imx/clk-imx31.c clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); base 74 drivers/clk/imx/clk-imx31.c clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); base 75 drivers/clk/imx/clk-imx31.c clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); base 76 drivers/clk/imx/clk-imx31.c clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); base 77 drivers/clk/imx/clk-imx31.c clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5); base 78 drivers/clk/imx/clk-imx31.c clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel)); base 79 drivers/clk/imx/clk-imx31.c clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel)); base 80 drivers/clk/imx/clk-imx31.c clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel)); base 81 drivers/clk/imx/clk-imx31.c clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9); base 82 drivers/clk/imx/clk-imx31.c clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2); base 83 drivers/clk/imx/clk-imx31.c clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3); base 84 drivers/clk/imx/clk-imx31.c clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3); base 85 drivers/clk/imx/clk-imx31.c clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6); base 86 drivers/clk/imx/clk-imx31.c clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0); base 87 drivers/clk/imx/clk-imx31.c clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2); base 88 drivers/clk/imx/clk-imx31.c clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4); base 89 drivers/clk/imx/clk-imx31.c clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6); base 90 drivers/clk/imx/clk-imx31.c clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8); base 91 drivers/clk/imx/clk-imx31.c clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10); base 92 drivers/clk/imx/clk-imx31.c clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12); base 93 drivers/clk/imx/clk-imx31.c clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); base 94 drivers/clk/imx/clk-imx31.c clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16); base 95 drivers/clk/imx/clk-imx31.c clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18); base 96 drivers/clk/imx/clk-imx31.c clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20); base 97 drivers/clk/imx/clk-imx31.c clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22); base 98 drivers/clk/imx/clk-imx31.c clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24); base 99 drivers/clk/imx/clk-imx31.c clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26); base 100 drivers/clk/imx/clk-imx31.c clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28); base 101 drivers/clk/imx/clk-imx31.c clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30); base 102 drivers/clk/imx/clk-imx31.c clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0); base 103 drivers/clk/imx/clk-imx31.c clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2); base 104 drivers/clk/imx/clk-imx31.c clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4); base 105 drivers/clk/imx/clk-imx31.c clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6); base 106 drivers/clk/imx/clk-imx31.c clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8); base 107 drivers/clk/imx/clk-imx31.c clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10); base 108 drivers/clk/imx/clk-imx31.c clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12); base 109 drivers/clk/imx/clk-imx31.c clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14); base 110 drivers/clk/imx/clk-imx31.c clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16); base 111 drivers/clk/imx/clk-imx31.c clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); base 112 drivers/clk/imx/clk-imx31.c clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20); base 113 drivers/clk/imx/clk-imx31.c clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22); base 114 drivers/clk/imx/clk-imx31.c clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24); base 115 drivers/clk/imx/clk-imx31.c clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26); base 116 drivers/clk/imx/clk-imx31.c clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28); base 117 drivers/clk/imx/clk-imx31.c clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30); base 118 drivers/clk/imx/clk-imx31.c clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0); base 119 drivers/clk/imx/clk-imx31.c clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2); base 120 drivers/clk/imx/clk-imx31.c clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4); base 121 drivers/clk/imx/clk-imx31.c clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6); base 122 drivers/clk/imx/clk-imx31.c clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); base 123 drivers/clk/imx/clk-imx31.c clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); base 124 drivers/clk/imx/clk-imx31.c clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); base 137 drivers/clk/imx/clk-imx31.c void __iomem *base; base 139 drivers/clk/imx/clk-imx31.c base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K); base 140 drivers/clk/imx/clk-imx31.c if (!base) base 143 drivers/clk/imx/clk-imx31.c _mx31_clocks_init(base, fref); base 95 drivers/clk/imx/clk-imx35.c void __iomem *base; base 100 drivers/clk/imx/clk-imx35.c base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K); base 101 drivers/clk/imx/clk-imx35.c BUG_ON(!base); base 103 drivers/clk/imx/clk-imx35.c pdr0 = __raw_readl(base + MXC_CCM_PDR0); base 117 drivers/clk/imx/clk-imx35.c clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); base 118 drivers/clk/imx/clk-imx35.c clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); base 143 drivers/clk/imx/clk-imx35.c clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); base 144 drivers/clk/imx/clk-imx35.c clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); base 145 drivers/clk/imx/clk-imx35.c clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel)); base 147 drivers/clk/imx/clk-imx35.c clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); base 148 drivers/clk/imx/clk-imx35.c clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); base 150 drivers/clk/imx/clk-imx35.c clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); base 151 drivers/clk/imx/clk-imx35.c clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6); base 152 drivers/clk/imx/clk-imx35.c clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6); base 153 drivers/clk/imx/clk-imx35.c clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6); base 155 drivers/clk/imx/clk-imx35.c clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel)); base 156 drivers/clk/imx/clk-imx35.c clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ base 157 drivers/clk/imx/clk-imx35.c clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6); base 159 drivers/clk/imx/clk-imx35.c clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel)); base 160 drivers/clk/imx/clk-imx35.c clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3); base 161 drivers/clk/imx/clk-imx35.c clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6); base 162 drivers/clk/imx/clk-imx35.c clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3); base 163 drivers/clk/imx/clk-imx35.c clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6); base 165 drivers/clk/imx/clk-imx35.c clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); base 166 drivers/clk/imx/clk-imx35.c clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6); base 168 drivers/clk/imx/clk-imx35.c clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); base 170 drivers/clk/imx/clk-imx35.c clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); base 171 drivers/clk/imx/clk-imx35.c clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); base 173 drivers/clk/imx/clk-imx35.c clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); base 174 drivers/clk/imx/clk-imx35.c clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); base 175 drivers/clk/imx/clk-imx35.c clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); base 176 drivers/clk/imx/clk-imx35.c clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); base 177 drivers/clk/imx/clk-imx35.c clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); base 178 drivers/clk/imx/clk-imx35.c clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); base 179 drivers/clk/imx/clk-imx35.c clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); base 180 drivers/clk/imx/clk-imx35.c clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); base 181 drivers/clk/imx/clk-imx35.c clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16); base 182 drivers/clk/imx/clk-imx35.c clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18); base 183 drivers/clk/imx/clk-imx35.c clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20); base 184 drivers/clk/imx/clk-imx35.c clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22); base 185 drivers/clk/imx/clk-imx35.c clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24); base 186 drivers/clk/imx/clk-imx35.c clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26); base 187 drivers/clk/imx/clk-imx35.c clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28); base 188 drivers/clk/imx/clk-imx35.c clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30); base 190 drivers/clk/imx/clk-imx35.c clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0); base 191 drivers/clk/imx/clk-imx35.c clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2); base 192 drivers/clk/imx/clk-imx35.c clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4); base 193 drivers/clk/imx/clk-imx35.c clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6); base 194 drivers/clk/imx/clk-imx35.c clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8); base 195 drivers/clk/imx/clk-imx35.c clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10); base 196 drivers/clk/imx/clk-imx35.c clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12); base 197 drivers/clk/imx/clk-imx35.c clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14); base 198 drivers/clk/imx/clk-imx35.c clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16); base 199 drivers/clk/imx/clk-imx35.c clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18); base 200 drivers/clk/imx/clk-imx35.c clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20); base 201 drivers/clk/imx/clk-imx35.c clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22); base 202 drivers/clk/imx/clk-imx35.c clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24); base 203 drivers/clk/imx/clk-imx35.c clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26); base 204 drivers/clk/imx/clk-imx35.c clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28); base 205 drivers/clk/imx/clk-imx35.c clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30); base 207 drivers/clk/imx/clk-imx35.c clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0); base 208 drivers/clk/imx/clk-imx35.c clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2); base 209 drivers/clk/imx/clk-imx35.c clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4); base 210 drivers/clk/imx/clk-imx35.c clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6); base 211 drivers/clk/imx/clk-imx35.c clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8); base 212 drivers/clk/imx/clk-imx35.c clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10); base 213 drivers/clk/imx/clk-imx35.c clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12); base 214 drivers/clk/imx/clk-imx35.c clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14); base 215 drivers/clk/imx/clk-imx35.c clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16); base 216 drivers/clk/imx/clk-imx35.c clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18); base 217 drivers/clk/imx/clk-imx35.c clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); base 218 drivers/clk/imx/clk-imx35.c clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22); base 219 drivers/clk/imx/clk-imx35.c clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24); base 220 drivers/clk/imx/clk-imx35.c clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); base 221 drivers/clk/imx/clk-imx35.c clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); base 223 drivers/clk/imx/clk-imx35.c clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); base 224 drivers/clk/imx/clk-imx35.c clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); base 225 drivers/clk/imx/clk-imx35.c clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); base 440 drivers/clk/imx/clk-imx6q.c void __iomem *anatop_base, *base; base 463 drivers/clk/imx/clk-imx6q.c anatop_base = base = of_iomap(np, 0); base 464 drivers/clk/imx/clk-imx6q.c WARN_ON(!base); base 475 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 476 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 477 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 478 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 479 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 480 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 481 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 484 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); base 485 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); base 486 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); base 487 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); base 488 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); base 489 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); base 490 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); base 492 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); base 493 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); base 494 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); base 495 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); base 496 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); base 497 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); base 498 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); base 509 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); base 510 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); base 511 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); base 512 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); base 513 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); base 514 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); base 515 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); base 523 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); base 524 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); base 530 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6); base 531 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6); base 548 drivers/clk/imx/clk-imx6q.c base + 0xe0, 0, 2, 0, clk_enet_ref_table, base 556 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_hw_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); base 557 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_hw_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); base 559 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); base 560 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_hw_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); base 571 drivers/clk/imx/clk-imx6q.c writel(readl(base + 0x160) & ~0x3c00, base + 0x160); base 572 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_hw_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12)); base 573 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_hw_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13)); base 575 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); base 576 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); base 579 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); base 580 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); base 581 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); base 582 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); base 583 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); base 584 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); base 585 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); base 600 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); base 601 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); base 602 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); base 603 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); base 606 drivers/clk/imx/clk-imx6q.c base = of_iomap(np, 0); base 607 drivers/clk/imx/clk-imx6q.c WARN_ON(!base); base 610 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_STEP] = imx_clk_hw_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); base 611 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); base 612 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); base 613 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); base 614 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); base 615 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); base 616 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_AXI_SEL] = imx_clk_hw_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); base 617 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); base 618 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ASRC_SEL] = imx_clk_hw_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); base 619 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); base 621 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); base 622 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); base 625 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CAN_SEL] = imx_clk_hw_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); base 626 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); base 627 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_hw_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels)); base 628 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); base 629 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2)); base 631 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MLB_SEL] = imx_clk_hw_mux("mlb_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); base 633 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); base 635 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_hw_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); base 637 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); base 639 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_hw_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); base 640 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_SEL] = imx_clk_hw_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); base 641 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_SEL] = imx_clk_hw_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); base 645 drivers/clk/imx/clk-imx6q.c imx_mmdc_mask_handshake(base, 1); base 648 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); base 649 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); base 656 drivers/clk/imx/clk-imx6q.c init_ldb_clks(np, base); base 658 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); base 659 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); base 662 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); base 663 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); base 664 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); base 665 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); base 666 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_hw_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); base 667 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_hw_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); base 670 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels_2, ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT); base 671 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels_2, ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT); base 672 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels_2, ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT); base 673 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels_2, ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT); base 674 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); base 675 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); base 676 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); base 677 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 678 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 679 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 680 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 681 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels_2, ARRAY_SIZE(enfc_sels_2)); base 682 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels)); base 683 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); base 684 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PRE_AXI] = imx_clk_hw_mux("pre_axi", base + 0x18, 1, 1, pre_axi_sels, ARRAY_SIZE(pre_axi_sels)); base 686 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); base 687 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); base 688 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); base 689 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); base 690 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); base 691 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); base 692 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); base 693 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); base 694 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); base 695 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); base 696 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); base 697 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); base 698 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup); base 699 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup); base 702 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_hw_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); base 703 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_hw_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); base 704 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); base 705 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); base 706 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CKO] = imx_clk_hw_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); base 709 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); base 710 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); base 713 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); base 714 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); base 715 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2); base 716 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ESAI_PRED] = imx_clk_hw_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); base 717 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ESAI_PODF] = imx_clk_hw_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); base 718 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ASRC_PRED] = imx_clk_hw_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); base 719 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ASRC_PODF] = imx_clk_hw_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); base 720 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); base 721 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); base 724 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_divider("ipg_per", "ipg_per_sel", base + 0x1c, 0, 6); base 725 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); base 726 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "can_sel", base + 0x20, 2, 6); base 727 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6); base 731 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); base 732 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "pll3_60m", base + 0x20, 2, 6); base 733 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); base 734 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); base 740 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MLB_PODF] = imx_clk_hw_divider("mlb_podf", "mlb_sel", base + 0x18, 23, 3); base 742 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); base 743 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_hw_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); base 745 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 29, 3); base 747 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_hw_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); base 748 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_PODF] = imx_clk_hw_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); base 749 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_PODF] = imx_clk_hw_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); base 750 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_hw_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); base 751 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_hw_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); base 752 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_hw_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); base 753 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_hw_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); base 754 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_hw_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); base 755 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_hw_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); base 756 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_hw_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); base 757 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); base 758 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); base 759 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); base 760 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); base 761 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); base 762 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); base 763 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); base 764 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); base 765 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); base 766 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); base 767 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ENFC_PRED] = imx_clk_hw_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); base 768 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ENFC_PODF] = imx_clk_hw_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); base 770 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3); base 771 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); base 773 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); base 774 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); base 777 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_hw_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); base 778 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CKO1_PODF] = imx_clk_hw_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); base 779 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CKO2_PODF] = imx_clk_hw_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); base 782 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_AXI] = imx_clk_hw_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); base 783 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); base 785 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_hw_gate("mmdc_ch1_axi_cg", "periph2", base + 0x4, 18); base 786 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "mmdc_ch1_axi_cg", base + 0x14, 3, 3, base + 0x48, 2); base 788 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); base 790 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); base 791 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); base 794 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_APBH_DMA] = imx_clk_hw_gate2("apbh_dma", "usdhc3", base + 0x68, 4); base 795 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ASRC] = imx_clk_hw_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc); base 796 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); base 797 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); base 798 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68, 8); base 799 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68, 10); base 800 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg", "ipg", base + 0x68, 12); base 801 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg", "ipg", base + 0x68, 14); base 802 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial", "can_root", base + 0x68, 16); base 803 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg", "ipg", base + 0x68, 18); base 804 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial", "can_root", base + 0x68, 20); base 805 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_DCIC1] = imx_clk_hw_gate2("dcic1", "ipu1_podf", base + 0x68, 24); base 806 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_DCIC2] = imx_clk_hw_gate2("dcic2", "ipu2_podf", base + 0x68, 26); base 807 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); base 808 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); base 809 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); base 810 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); base 812 drivers/clk/imx/clk-imx6q.c hws[IMX6DL_CLK_I2C4] = imx_clk_hw_gate2("i2c4", "ipg_per", base + 0x6c, 8); base 814 drivers/clk/imx/clk-imx6q.c hws[IMX6Q_CLK_ECSPI5] = imx_clk_hw_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); base 815 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x6c, 10); base 816 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "ipg", base + 0x6c, 12); base 817 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "ipg", base + 0x6c, 14); base 818 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); base 819 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); base 820 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); base 821 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPT_IPG] = imx_clk_hw_gate2("gpt_ipg", "ipg", base + 0x6c, 20); base 822 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_hw_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); base 823 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_hw_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); base 824 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_hw_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); base 825 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_hw_gate2("hdmi_iahb", "ahb", base + 0x70, 0); base 826 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_hw_gate2("hdmi_isfr", "mipi_core_cfg", base + 0x70, 4); base 827 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "ipg_per", base + 0x70, 6); base 828 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "ipg_per", base + 0x70, 8); base 829 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "ipg_per", base + 0x70, 10); base 830 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IIM] = imx_clk_hw_gate2("iim", "ipg", base + 0x70, 12); base 831 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ENFC] = imx_clk_hw_gate2("enfc", "enfc_podf", base + 0x70, 14); base 832 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_VDOA] = imx_clk_hw_gate2("vdoa", "vdo_axi", base + 0x70, 26); base 833 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1] = imx_clk_hw_gate2("ipu1", "ipu1_podf", base + 0x74, 0); base 834 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_DI0] = imx_clk_hw_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); base 835 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU1_DI1] = imx_clk_hw_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); base 836 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2] = imx_clk_hw_gate2("ipu2", "ipu2_podf", base + 0x74, 6); base 837 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_DI0] = imx_clk_hw_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); base 839 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_sel", base + 0x74, 12); base 840 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1", "ldb_di1_sel", base + 0x74, 14); base 842 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); base 843 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); base 845 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_IPU2_DI1] = imx_clk_hw_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); base 846 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_HSI_TX] = imx_clk_hw_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg); base 847 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_hw_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg); base 848 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MIPI_IPG] = imx_clk_hw_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg); base 855 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb", "mlb_podf", base + 0x74, 18); base 857 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb", "axi", base + 0x74, 18); base 858 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_hw_gate2_flags("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL); base 859 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_hw_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); base 860 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); base 861 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_OCRAM] = imx_clk_hw_gate2("ocram", "ahb", base + 0x74, 28); base 862 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_hw_gate2("openvg_axi", "axi", base + 0x74, 30); base 863 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PCIE_AXI] = imx_clk_hw_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); base 864 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PER1_BCH] = imx_clk_hw_gate2("per1_bch", "usdhc3", base + 0x78, 12); base 865 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "ipg_per", base + 0x78, 16); base 866 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "ipg_per", base + 0x78, 18); base 867 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "ipg_per", base + 0x78, 20); base 868 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "ipg_per", base + 0x78, 22); base 869 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); base 870 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPMI_BCH] = imx_clk_hw_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); base 871 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io", "enfc", base + 0x78, 28); base 872 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_GPMI_APB] = imx_clk_hw_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); base 873 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); base 874 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SATA] = imx_clk_hw_gate2("sata", "ahb", base + 0x7c, 4); base 875 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ahb", base + 0x7c, 6); base 876 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12); base 877 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif); base 878 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); base 879 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); base 880 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); base 881 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); base 882 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); base 883 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); base 884 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); base 885 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_UART_IPG] = imx_clk_hw_gate2("uart_ipg", "ipg", base + 0x7c, 24); base 886 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); base 887 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0); base 888 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); base 889 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); base 890 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); base 891 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); base 892 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_EIM_SLOW] = imx_clk_hw_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); base 893 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_VDO_AXI] = imx_clk_hw_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); base 894 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_VPU_AXI] = imx_clk_hw_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); base 896 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PRE0] = imx_clk_hw_gate2("pre0", "pre_axi", base + 0x80, 16); base 897 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PRE1] = imx_clk_hw_gate2("pre1", "pre_axi", base + 0x80, 18); base 898 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PRE2] = imx_clk_hw_gate2("pre2", "pre_axi", base + 0x80, 20); base 899 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PRE3] = imx_clk_hw_gate2("pre3", "pre_axi", base + 0x80, 22); base 900 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PRG0_AXI] = imx_clk_hw_gate2_shared("prg0_axi", "ipu1_podf", base + 0x80, 24, &share_count_prg0); base 901 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PRG1_AXI] = imx_clk_hw_gate2_shared("prg1_axi", "ipu2_podf", base + 0x80, 26, &share_count_prg1); base 902 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PRG0_APB] = imx_clk_hw_gate2_shared("prg0_apb", "ipg", base + 0x80, 24, &share_count_prg0); base 903 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_PRG1_APB] = imx_clk_hw_gate2_shared("prg1_apb", "ipg", base + 0x80, 26, &share_count_prg1); base 905 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CKO1] = imx_clk_hw_gate("cko1", "cko1_podf", base + 0x60, 7); base 906 drivers/clk/imx/clk-imx6q.c hws[IMX6QDL_CLK_CKO2] = imx_clk_hw_gate("cko2", "cko2_podf", base + 0x60, 24); base 190 drivers/clk/imx/clk-imx6sl.c void __iomem *base; base 209 drivers/clk/imx/clk-imx6sl.c base = of_iomap(np, 0); base 210 drivers/clk/imx/clk-imx6sl.c WARN_ON(!base); base 211 drivers/clk/imx/clk-imx6sl.c anatop_base = base; base 213 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 214 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 215 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 216 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 217 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 218 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 219 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 222 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); base 223 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); base 224 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); base 225 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); base 226 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); base 227 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); base 228 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); base 230 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); base 231 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); base 232 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); base 233 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); base 234 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); base 235 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); base 236 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); base 247 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); base 248 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); base 249 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); base 250 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); base 251 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); base 252 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); base 253 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); base 255 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); base 256 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LVDS1_OUT] = imx_clk_hw_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12)); base 257 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); base 266 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); base 267 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); base 268 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6); base 269 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6); base 272 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); base 273 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); base 274 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); base 275 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); base 276 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); base 279 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0); base 280 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1); base 281 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2); base 282 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0); base 283 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1); base 284 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2); base 285 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3); base 294 drivers/clk/imx/clk-imx6sl.c base = of_iomap(np, 0); base 295 drivers/clk/imx/clk-imx6sl.c WARN_ON(!base); base 296 drivers/clk/imx/clk-imx6sl.c ccm_base = base; base 299 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_STEP] = imx_clk_hw_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); base 300 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); base 301 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_hw_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels)); base 302 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_OCRAM_SEL] = imx_clk_hw_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels)); base 303 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_hw_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); base 304 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); base 305 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); base 306 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); base 307 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); base 308 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_hw_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels)); base 309 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC1_SEL] = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); base 310 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC2_SEL] = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); base 311 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC3_SEL] = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); base 312 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC4_SEL] = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); base 313 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI1_SEL] = imx_clk_hw_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); base 314 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI2_SEL] = imx_clk_hw_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); base 315 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI3_SEL] = imx_clk_hw_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); base 316 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PERCLK_SEL] = imx_clk_hw_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup); base 317 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_hw_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels)); base 318 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_hw_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels)); base 319 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_hw_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); base 320 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_GPU2D_SEL] = imx_clk_hw_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); base 321 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_hw_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); base 322 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_hw_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels)); base 323 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_hw_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); base 324 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_hw_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); base 325 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_hw_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); base 326 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); base 327 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); base 330 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); base 331 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); base 334 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_OCRAM_PODF] = imx_clk_hw_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0); base 335 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_hw_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3); base 336 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_hw_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3); base 337 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2); base 338 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_CSI_PODF] = imx_clk_hw_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); base 339 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_hw_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3); base 340 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); base 341 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); base 342 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); base 343 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); base 344 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); base 345 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); base 346 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); base 347 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); base 348 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); base 349 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); base 350 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PERCLK] = imx_clk_hw_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup); base 351 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_hw_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); base 352 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_hw_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); base 353 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_hw_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); base 354 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_GPU2D_PODF] = imx_clk_hw_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); base 355 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_hw_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); base 356 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_hw_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); base 357 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_hw_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup); base 358 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_hw_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); base 359 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_hw_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); base 360 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_hw_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); base 361 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_hw_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3); base 362 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_hw_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3); base 363 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_hw_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3); base 364 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_hw_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3); base 365 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); base 366 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_UART_ROOT] = imx_clk_hw_divider("uart_root", "uart_sel", base + 0x24, 0, 6); base 369 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); base 370 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_MMDC_ROOT] = imx_clk_hw_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2); base 371 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); base 374 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); base 375 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); base 376 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); base 377 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); base 378 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x6c, 10); base 379 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "perclk", base + 0x6c, 12); base 380 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "perclk", base + 0x6c, 14); base 381 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_hw_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16); base 382 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_GPT] = imx_clk_hw_gate2("gpt", "perclk", base + 0x6c, 20); base 383 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_GPT_SERIAL] = imx_clk_hw_gate2("gpt_serial", "perclk", base + 0x6c, 22); base 384 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_GPU2D_OVG] = imx_clk_hw_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26); base 385 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "perclk", base + 0x70, 6); base 386 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "perclk", base + 0x70, 8); base 387 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "perclk", base + 0x70, 10); base 388 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_OCOTP] = imx_clk_hw_gate2("ocotp", "ipg", base + 0x70, 12); base 389 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_CSI] = imx_clk_hw_gate2("csi", "csi_podf", base + 0x74, 0); base 390 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PXP_AXI] = imx_clk_hw_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2); base 391 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EPDC_AXI] = imx_clk_hw_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4); base 392 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LCDIF_AXI] = imx_clk_hw_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6); base 393 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8); base 394 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_EPDC_PIX] = imx_clk_hw_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10); base 395 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); base 396 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2("mmdc_p1_ipg", "ipg", base + 0x74, 26); base 397 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_OCRAM] = imx_clk_hw_gate2("ocram", "ocram_podf", base + 0x74, 28); base 398 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "perclk", base + 0x78, 16); base 399 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "perclk", base + 0x78, 18); base 400 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "perclk", base + 0x78, 20); base 401 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "perclk", base + 0x78, 22); base 402 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ipg", base + 0x7c, 6); base 403 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12); base 404 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif); base 405 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); base 406 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); base 407 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); base 408 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); base 409 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); base 410 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); base 411 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); base 412 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_UART] = imx_clk_hw_gate2("uart", "ipg", base + 0x7c, 24); base 413 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_root", base + 0x7c, 26); base 414 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0); base 415 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); base 416 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); base 417 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); base 418 drivers/clk/imx/clk-imx6sl.c hws[IMX6SL_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); base 421 drivers/clk/imx/clk-imx6sl.c imx_mmdc_mask_handshake(base, 0); base 97 drivers/clk/imx/clk-imx6sll.c void __iomem *base; base 118 drivers/clk/imx/clk-imx6sll.c base = of_iomap(np, 0); base 120 drivers/clk/imx/clk-imx6sll.c WARN_ON(!base); base 123 drivers/clk/imx/clk-imx6sll.c writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0)); base 124 drivers/clk/imx/clk-imx6sll.c writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10)); base 125 drivers/clk/imx/clk-imx6sll.c writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20)); base 126 drivers/clk/imx/clk-imx6sll.c writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30)); base 127 drivers/clk/imx/clk-imx6sll.c writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70)); base 128 drivers/clk/imx/clk-imx6sll.c writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0)); base 129 drivers/clk/imx/clk-imx6sll.c writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0)); base 131 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 132 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 133 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 134 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 135 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 136 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 137 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 139 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); base 140 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); base 141 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); base 142 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); base 143 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); base 144 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); base 145 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); base 147 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); base 148 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); base 149 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); base 150 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); base 151 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); base 152 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); base 153 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); base 156 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); base 157 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); base 158 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); base 159 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); base 160 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); base 161 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); base 169 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); base 170 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); base 177 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USBPHY1_GATE] = imx_clk_hw_gate_flags("usbphy1_gate", "dummy", base + 0x10, 6, CLK_IS_CRITICAL); base 178 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USBPHY2_GATE] = imx_clk_hw_gate_flags("usbphy2_gate", "dummy", base + 0x20, 6, CLK_IS_CRITICAL); base 182 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); base 183 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); base 184 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); base 185 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL2_PFD3] = imx_clk_hw_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3); base 186 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); base 187 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); base 188 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); base 189 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); base 192 drivers/clk/imx/clk-imx6sll.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); base 194 drivers/clk/imx/clk-imx6sll.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock); base 196 drivers/clk/imx/clk-imx6sll.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); base 198 drivers/clk/imx/clk-imx6sll.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); base 207 drivers/clk/imx/clk-imx6sll.c base = of_iomap(np, 0); base 208 drivers/clk/imx/clk-imx6sll.c WARN_ON(!base); base 210 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_STEP] = imx_clk_hw_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels)); base 211 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PLL1_SW] = imx_clk_hw_mux_flags("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0); base 212 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_AXI_ALT_SEL] = imx_clk_hw_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); base 213 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_AXI_SEL] = imx_clk_hw_mux_flags("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0); base 214 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); base 215 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); base 216 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); base 217 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); base 218 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 219 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 220 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USDHC3_SEL] = imx_clk_hw_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 221 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI1_SEL] = imx_clk_hw_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); base 222 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI2_SEL] = imx_clk_hw_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); base 223 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI3_SEL] = imx_clk_hw_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); base 224 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PERCLK_SEL] = imx_clk_hw_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); base 225 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); base 226 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); base 227 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_EXTERN_AUDIO_SEL] = imx_clk_hw_mux("extern_audio_sel", base + 0x30, 7, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); base 228 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_EPDC_PRE_SEL] = imx_clk_hw_mux("epdc_pre_sel", base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels)); base 229 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_EPDC_SEL] = imx_clk_hw_mux("epdc_sel", base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels)); base 230 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); base 231 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_LCDIF_PRE_SEL] = imx_clk_hw_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels)); base 232 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); base 234 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); base 235 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); base 237 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); base 238 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); base 239 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2); base 240 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_LCDIF_PODF] = imx_clk_hw_divider("lcdif_podf", "lcdif_pred", base + 0x18, 23, 3); base 241 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PERCLK] = imx_clk_hw_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); base 242 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); base 243 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); base 244 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); base 245 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); base 246 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); base 247 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); base 248 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); base 249 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); base 250 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); base 251 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); base 252 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); base 253 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); base 254 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_EXTERN_AUDIO_PRED] = imx_clk_hw_divider("extern_audio_pred", "extern_audio_sel", base + 0x30, 12, 3); base 255 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_EXTERN_AUDIO_PODF] = imx_clk_hw_divider("extern_audio_podf", "extern_audio_pred", base + 0x30, 9, 3); base 256 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_EPDC_PODF] = imx_clk_hw_divider("epdc_podf", "epdc_pre_sel", base + 0x34, 12, 3); base 257 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_ECSPI_PODF] = imx_clk_hw_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6); base 258 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_LCDIF_PRED] = imx_clk_hw_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3); base 260 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); base 261 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_MMDC_PODF] = imx_clk_hw_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); base 262 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_AXI_PODF] = imx_clk_hw_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); base 263 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); base 270 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels)); base 271 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux("ldb_di1_sel", base + 0x1c, 7, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels)); base 272 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); base 273 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux("ldb_di1_div_sel", base + 0x20, 10, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels)); base 276 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_AIPSTZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL); base 277 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_AIPSTZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL); base 278 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_DCP] = imx_clk_hw_gate2("dcp", "ahb", base + 0x68, 10); base 279 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART2_IPG] = imx_clk_hw_gate2("uart2_ipg", "ipg", base + 0x68, 28); base 280 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART2_SERIAL] = imx_clk_hw_gate2("uart2_serial", "uart_podf", base + 0x68, 28); base 281 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_GPIO2] = imx_clk_hw_gate2("gpio2", "ipg", base + 0x68, 30); base 284 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); base 285 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2); base 286 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4); base 287 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6); base 288 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART3_IPG] = imx_clk_hw_gate2("uart3_ipg", "ipg", base + 0x6c, 10); base 289 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART3_SERIAL] = imx_clk_hw_gate2("uart3_serial", "uart_podf", base + 0x6c, 10); base 290 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "perclk", base + 0x6c, 12); base 291 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "perclk", base + 0x6c, 14); base 292 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_GPT_BUS] = imx_clk_hw_gate2("gpt1_bus", "perclk", base + 0x6c, 20); base 293 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_GPT_SERIAL] = imx_clk_hw_gate2("gpt1_serial", "perclk", base + 0x6c, 22); base 294 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART4_IPG] = imx_clk_hw_gate2("uart4_ipg", "ipg", base + 0x6c, 24); base 295 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_hw_gate2("uart4_serial", "uart_podf", base + 0x6c, 24); base 296 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_GPIO1] = imx_clk_hw_gate2("gpio1", "ipg", base + 0x6c, 26); base 297 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_GPIO5] = imx_clk_hw_gate2("gpio5", "ipg", base + 0x6c, 30); base 300 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_GPIO6] = imx_clk_hw_gate2("gpio6", "ipg", base + 0x70, 0); base 301 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_CSI] = imx_clk_hw_gate2("csi", "axi", base + 0x70, 2); base 302 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "perclk", base + 0x70, 6); base 303 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "perclk", base + 0x70, 8); base 304 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "perclk", base + 0x70, 10); base 305 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_OCOTP] = imx_clk_hw_gate2("ocotp", "ipg", base + 0x70, 12); base 306 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_GPIO3] = imx_clk_hw_gate2("gpio3", "ipg", base + 0x70, 26); base 307 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif_apb", "axi", base + 0x70, 28); base 308 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PXP] = imx_clk_hw_gate2("pxp", "axi", base + 0x70, 30); base 311 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART5_IPG] = imx_clk_hw_gate2("uart5_ipg", "ipg", base + 0x74, 2); base 312 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART5_SERIAL] = imx_clk_hw_gate2("uart5_serial", "uart_podf", base + 0x74, 2); base 313 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_EPDC_AXI] = imx_clk_hw_gate2("epdc_aclk", "axi", base + 0x74, 4); base 314 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_EPDC_PIX] = imx_clk_hw_gate2("epdc_pix", "epdc_podf", base + 0x74, 4); base 315 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10); base 316 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_GPIO4] = imx_clk_hw_gate2("gpio4", "ipg", base + 0x74, 12); base 317 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_WDOG1] = imx_clk_hw_gate2("wdog1", "ipg", base + 0x74, 16); base 318 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_MMDC_P0_FAST] = imx_clk_hw_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL); base 319 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); base 320 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2_flags("mmdc_p1_ipg", "ipg", base + 0x74, 26, CLK_IS_CRITICAL); base 321 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_OCRAM] = imx_clk_hw_gate_flags("ocram", "ahb", base + 0x74, 28, CLK_IS_CRITICAL); base 324 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "perclk", base + 0x78, 16); base 325 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "perclk", base + 0x78, 18); base 326 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "perclk", base + 0x78, 20); base 327 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "perclk", base + 0x78, 22); base 330 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); base 331 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ahb", base + 0x7c, 6); base 332 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_WDOG2] = imx_clk_hw_gate2("wdog2", "ipg", base + 0x7c, 10); base 333 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12); base 334 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_EXTERN_AUDIO] = imx_clk_hw_gate2_shared("extern_audio", "extern_audio_podf", base + 0x7c, 14, &share_count_audio); base 335 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); base 336 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); base 337 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); base 338 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); base 339 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); base 340 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); base 341 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); base 342 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); base 343 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART1_IPG] = imx_clk_hw_gate2("uart1_ipg", "ipg", base + 0x7c, 24); base 344 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_UART1_SERIAL] = imx_clk_hw_gate2("uart1_serial", "uart_podf", base + 0x7c, 24); base 347 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0); base 348 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); base 349 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); base 350 drivers/clk/imx/clk-imx6sll.c hws[IMX6SLL_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); base 353 drivers/clk/imx/clk-imx6sll.c imx_mmdc_mask_handshake(base, 0); base 129 drivers/clk/imx/clk-imx6sx.c void __iomem *base; base 154 drivers/clk/imx/clk-imx6sx.c base = of_iomap(np, 0); base 155 drivers/clk/imx/clk-imx6sx.c WARN_ON(!base); base 158 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 159 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 160 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 161 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 162 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 163 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 164 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 167 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); base 168 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); base 169 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); base 170 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); base 171 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); base 172 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); base 173 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); base 175 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); base 176 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); base 177 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); base 178 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); base 179 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); base 180 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); base 181 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); base 192 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); base 193 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); base 194 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); base 195 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); base 196 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); base 197 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); base 198 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); base 206 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); base 207 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); base 213 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6); base 214 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6); base 218 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_hw_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); base 220 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LVDS1_OUT] = imx_clk_hw_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12)); base 221 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LVDS2_OUT] = imx_clk_hw_gate_exclusive("lvds2_out", "lvds2_sel", base + 0x160, 11, BIT(13)); base 222 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); base 223 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); base 226 drivers/clk/imx/clk-imx6sx.c base + 0xe0, 0, 2, 0, clk_enet_ref_table, base 229 drivers/clk/imx/clk-imx6sx.c base + 0xe0, 2, 2, 0, clk_enet_ref_table, base 231 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20); base 234 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ENET_PTP] = imx_clk_hw_gate("enet_ptp_25m", "enet_ptp_ref", base + 0xe0, 21); base 237 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); base 238 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); base 239 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); base 240 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL2_PFD3] = imx_clk_hw_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3); base 241 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); base 242 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); base 243 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); base 244 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); base 255 drivers/clk/imx/clk-imx6sx.c CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); base 257 drivers/clk/imx/clk-imx6sx.c CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); base 259 drivers/clk/imx/clk-imx6sx.c CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); base 261 drivers/clk/imx/clk-imx6sx.c CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); base 264 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); base 265 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LVDS2_SEL] = imx_clk_hw_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); base 268 drivers/clk/imx/clk-imx6sx.c base = of_iomap(np, 0); base 269 drivers/clk/imx/clk-imx6sx.c WARN_ON(!base); base 272 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_STEP] = imx_clk_hw_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); base 273 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); base 274 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_OCRAM_SEL] = imx_clk_hw_mux("ocram_sel", base + 0x14, 6, 2, ocram_sels, ARRAY_SIZE(ocram_sels)); base 275 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); base 276 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); base 277 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); base 278 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); base 279 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PCIE_AXI_SEL] = imx_clk_hw_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); base 280 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GPU_AXI_SEL] = imx_clk_hw_mux("gpu_axi_sel", base + 0x18, 8, 2, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); base 281 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GPU_CORE_SEL] = imx_clk_hw_mux("gpu_core_sel", base + 0x18, 4, 2, gpu_core_sels, ARRAY_SIZE(gpu_core_sels)); base 282 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_EIM_SLOW_SEL] = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); base 283 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 284 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 285 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC3_SEL] = imx_clk_hw_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 286 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC4_SEL] = imx_clk_hw_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 287 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI3_SEL] = imx_clk_hw_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); base 288 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI2_SEL] = imx_clk_hw_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); base 289 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI1_SEL] = imx_clk_hw_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); base 290 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_QSPI1_SEL] = imx_clk_hw_mux_flags("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels), CLK_SET_RATE_PARENT); base 291 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PERCLK_SEL] = imx_clk_hw_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); base 292 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_VID_SEL] = imx_clk_hw_mux("vid_sel", base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels)); base 293 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); base 294 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CAN_SEL] = imx_clk_hw_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); base 295 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); base 296 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_QSPI2_SEL] = imx_clk_hw_mux_flags("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT); base 297 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); base 298 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_AUDIO_SEL] = imx_clk_hw_mux("audio_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); base 299 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ENET_PRE_SEL] = imx_clk_hw_mux("enet_pre_sel", base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels)); base 300 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ENET_SEL] = imx_clk_hw_mux("enet_sel", base + 0x34, 9, 3, enet_sels, ARRAY_SIZE(enet_sels)); base 301 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_M4_PRE_SEL] = imx_clk_hw_mux("m4_pre_sel", base + 0x34, 6, 3, m4_pre_sels, ARRAY_SIZE(m4_pre_sels)); base 302 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_M4_SEL] = imx_clk_hw_mux("m4_sel", base + 0x34, 0, 3, m4_sels, ARRAY_SIZE(m4_sels)); base 303 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); base 304 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LCDIF2_PRE_SEL] = imx_clk_hw_mux("lcdif2_pre_sel", base + 0x38, 6, 3, lcdif2_pre_sels, ARRAY_SIZE(lcdif2_pre_sels)); base 305 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LCDIF2_SEL] = imx_clk_hw_mux("lcdif2_sel", base + 0x38, 0, 3, lcdif2_sels, ARRAY_SIZE(lcdif2_sels)); base 306 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_DISPLAY_SEL] = imx_clk_hw_mux("display_sel", base + 0x3c, 14, 2, display_sels, ARRAY_SIZE(display_sels)); base 307 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); base 308 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); base 309 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); base 310 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CKO] = imx_clk_hw_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); base 312 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT); base 313 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT); base 314 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels), CLK_SET_RATE_PARENT); base 315 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels), CLK_SET_RATE_PARENT); base 316 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LCDIF1_PRE_SEL] = imx_clk_hw_mux_flags("lcdif1_pre_sel", base + 0x38, 15, 3, lcdif1_pre_sels, ARRAY_SIZE(lcdif1_pre_sels), CLK_SET_RATE_PARENT); base 317 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LCDIF1_SEL] = imx_clk_hw_mux_flags("lcdif1_sel", base + 0x38, 9, 3, lcdif1_sels, ARRAY_SIZE(lcdif1_sels), CLK_SET_RATE_PARENT); base 320 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); base 321 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); base 322 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2); base 323 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GPU_CORE_PODF] = imx_clk_hw_divider("gpu_core_podf", "gpu_core_sel", base + 0x18, 29, 3); base 324 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GPU_AXI_PODF] = imx_clk_hw_divider("gpu_axi_podf", "gpu_axi_sel", base + 0x18, 26, 3); base 325 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LCDIF1_PODF] = imx_clk_hw_divider("lcdif1_podf", "lcdif1_pred", base + 0x18, 23, 3); base 326 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_QSPI1_PODF] = imx_clk_hw_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3); base 327 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_EIM_SLOW_PODF] = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); base 328 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LCDIF2_PODF] = imx_clk_hw_divider("lcdif2_podf", "lcdif2_pred", base + 0x1c, 20, 3); base 329 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PERCLK] = imx_clk_hw_divider_flags("perclk", "perclk_sel", base + 0x1c, 0, 6, CLK_IS_CRITICAL); base 330 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_VID_PODF] = imx_clk_hw_divider("vid_podf", "vid_sel", base + 0x20, 24, 2); base 331 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CAN_PODF] = imx_clk_hw_divider("can_podf", "can_sel", base + 0x20, 2, 6); base 332 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); base 333 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); base 334 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); base 335 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); base 336 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); base 337 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ESAI_PRED] = imx_clk_hw_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); base 338 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ESAI_PODF] = imx_clk_hw_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); base 339 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); base 340 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); base 341 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); base 342 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); base 343 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_QSPI2_PRED] = imx_clk_hw_divider("qspi2_pred", "qspi2_sel", base + 0x2c, 18, 3); base 344 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_QSPI2_PODF] = imx_clk_hw_divider("qspi2_podf", "qspi2_pred", base + 0x2c, 21, 6); base 345 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); base 346 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); base 347 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); base 348 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); base 349 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_AUDIO_PRED] = imx_clk_hw_divider("audio_pred", "audio_sel", base + 0x30, 12, 3); base 350 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_AUDIO_PODF] = imx_clk_hw_divider("audio_podf", "audio_pred", base + 0x30, 9, 3); base 351 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ENET_PODF] = imx_clk_hw_divider("enet_podf", "enet_pre_sel", base + 0x34, 12, 3); base 352 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_M4_PODF] = imx_clk_hw_divider("m4_podf", "m4_sel", base + 0x34, 3, 3); base 353 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ECSPI_PODF] = imx_clk_hw_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6); base 354 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LCDIF1_PRED] = imx_clk_hw_divider("lcdif1_pred", "lcdif1_pre_sel", base + 0x38, 12, 3); base 355 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LCDIF2_PRED] = imx_clk_hw_divider("lcdif2_pred", "lcdif2_pre_sel", base + 0x38, 3, 3); base 356 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_DISPLAY_PODF] = imx_clk_hw_divider("display_podf", "display_sel", base + 0x3c, 16, 3); base 357 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CSI_PODF] = imx_clk_hw_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); base 358 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CKO1_PODF] = imx_clk_hw_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); base 359 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CKO2_PODF] = imx_clk_hw_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); base 367 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); base 368 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); base 370 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_OCRAM_PODF] = imx_clk_hw_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0); base 371 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); base 372 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_MMDC_PODF] = imx_clk_hw_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); base 373 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); base 377 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_AIPS_TZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL); base 378 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_AIPS_TZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL); base 379 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_APBH_DMA] = imx_clk_hw_gate2("apbh_dma", "usdhc3", base + 0x68, 4); base 380 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); base 381 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); base 382 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68, 8); base 383 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68, 10); base 384 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg", "ipg", base + 0x68, 12); base 385 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg", "ipg", base + 0x68, 14); base 386 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial", "can_podf", base + 0x68, 16); base 387 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg", "ipg", base + 0x68, 18); base 388 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial", "can_podf", base + 0x68, 20); base 389 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_DCIC1] = imx_clk_hw_gate2("dcic1", "display_podf", base + 0x68, 24); base 390 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_DCIC2] = imx_clk_hw_gate2("dcic2", "display_podf", base + 0x68, 26); base 391 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_AIPS_TZ3] = imx_clk_hw_gate2_flags("aips_tz3", "ahb", base + 0x68, 30, CLK_IS_CRITICAL); base 394 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); base 395 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2); base 396 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4); base 397 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6); base 398 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ECSPI5] = imx_clk_hw_gate2("ecspi5", "ecspi_podf", base + 0x6c, 8); base 399 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "perclk", base + 0x6c, 12); base 400 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "perclk", base + 0x6c, 14); base 401 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); base 402 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); base 403 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); base 404 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_WAKEUP] = imx_clk_hw_gate2_flags("wakeup", "ipg", base + 0x6c, 18, CLK_IS_CRITICAL); base 405 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GPT_BUS] = imx_clk_hw_gate2("gpt_bus", "perclk", base + 0x6c, 20); base 406 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GPT_SERIAL] = imx_clk_hw_gate2("gpt_serial", "perclk", base + 0x6c, 22); base 407 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GPU] = imx_clk_hw_gate2("gpu", "gpu_core_podf", base + 0x6c, 26); base 408 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_OCRAM_S] = imx_clk_hw_gate2("ocram_s", "ahb", base + 0x6c, 28); base 409 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CANFD] = imx_clk_hw_gate2("canfd", "can_podf", base + 0x6c, 30); base 412 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CSI] = imx_clk_hw_gate2("csi", "csi_podf", base + 0x70, 2); base 413 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "perclk", base + 0x70, 6); base 414 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "perclk", base + 0x70, 8); base 415 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "perclk", base + 0x70, 10); base 416 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_OCOTP] = imx_clk_hw_gate2("ocotp", "ipg", base + 0x70, 12); base 417 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_IOMUXC] = imx_clk_hw_gate2("iomuxc", "lcdif1_podf", base + 0x70, 14); base 418 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_IPMUX1] = imx_clk_hw_gate2_flags("ipmux1", "ahb", base + 0x70, 16, CLK_IS_CRITICAL); base 419 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_IPMUX2] = imx_clk_hw_gate2_flags("ipmux2", "ahb", base + 0x70, 18, CLK_IS_CRITICAL); base 420 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_IPMUX3] = imx_clk_hw_gate2_flags("ipmux3", "ahb", base + 0x70, 20, CLK_IS_CRITICAL); base 421 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_TZASC1] = imx_clk_hw_gate2_flags("tzasc1", "mmdc_podf", base + 0x70, 22, CLK_IS_CRITICAL); base 422 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif_apb", "display_podf", base + 0x70, 28); base 423 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PXP_AXI] = imx_clk_hw_gate2("pxp_axi", "display_podf", base + 0x70, 30); base 426 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_M4] = imx_clk_hw_gate2("m4", "m4_podf", base + 0x74, 2); base 427 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x74, 4); base 428 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ENET_AHB] = imx_clk_hw_gate2("enet_ahb", "enet_sel", base + 0x74, 4); base 429 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_DISPLAY_AXI] = imx_clk_hw_gate2("display_axi", "display_podf", base + 0x74, 6); base 430 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LCDIF2_PIX] = imx_clk_hw_gate2("lcdif2_pix", "lcdif2_sel", base + 0x74, 8); base 431 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LCDIF1_PIX] = imx_clk_hw_gate2("lcdif1_pix", "lcdif1_sel", base + 0x74, 10); base 432 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12); base 433 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_QSPI1] = imx_clk_hw_gate2("qspi1", "qspi1_podf", base + 0x74, 14); base 434 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_MLB] = imx_clk_hw_gate2("mlb", "ahb", base + 0x74, 18); base 435 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_hw_gate2_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL); base 436 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); base 437 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2_flags("mmdc_p1_ipg", "ipg", base + 0x74, 26, CLK_IS_CRITICAL); base 438 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_OCRAM] = imx_clk_hw_gate2_flags("ocram", "ocram_podf", base + 0x74, 28, CLK_IS_CRITICAL); base 441 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PCIE_AXI] = imx_clk_hw_gate2("pcie_axi", "display_podf", base + 0x78, 0); base 442 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_QSPI2] = imx_clk_hw_gate2("qspi2", "qspi2_podf", base + 0x78, 10); base 443 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PER1_BCH] = imx_clk_hw_gate2("per1_bch", "usdhc3", base + 0x78, 12); base 444 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PER2_MAIN] = imx_clk_hw_gate2_flags("per2_main", "ahb", base + 0x78, 14, CLK_IS_CRITICAL); base 445 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "perclk", base + 0x78, 16); base 446 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "perclk", base + 0x78, 18); base 447 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "perclk", base + 0x78, 20); base 448 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "perclk", base + 0x78, 22); base 449 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); base 450 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GPMI_BCH] = imx_clk_hw_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); base 451 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io", "qspi2_podf", base + 0x78, 28); base 452 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GPMI_APB] = imx_clk_hw_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); base 455 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); base 456 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ahb", base + 0x7c, 6); base 457 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12); base 458 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_AUDIO] = imx_clk_hw_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio); base 459 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); base 460 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); base 461 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); base 462 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); base 463 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); base 464 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); base 465 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); base 466 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); base 467 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_UART_IPG] = imx_clk_hw_gate2("uart_ipg", "ipg", base + 0x7c, 24); base 468 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_podf", base + 0x7c, 26); base 469 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SAI1_IPG] = imx_clk_hw_gate2_shared("sai1_ipg", "ipg", base + 0x7c, 28, &share_count_sai1); base 470 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SAI2_IPG] = imx_clk_hw_gate2_shared("sai2_ipg", "ipg", base + 0x7c, 30, &share_count_sai2); base 471 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SAI1] = imx_clk_hw_gate2_shared("sai1", "ssi1_podf", base + 0x7c, 28, &share_count_sai1); base 472 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_SAI2] = imx_clk_hw_gate2_shared("sai2", "ssi2_podf", base + 0x7c, 30, &share_count_sai2); base 475 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0); base 476 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); base 477 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); base 478 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); base 479 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); base 480 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_EIM_SLOW] = imx_clk_hw_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); base 481 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PWM8] = imx_clk_hw_gate2("pwm8", "perclk", base + 0x80, 16); base 482 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_VADC] = imx_clk_hw_gate2("vadc", "vid_podf", base + 0x80, 20); base 483 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_GIS] = imx_clk_hw_gate2("gis", "display_podf", base + 0x80, 22); base 484 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_I2C4] = imx_clk_hw_gate2("i2c4", "perclk", base + 0x80, 24); base 485 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PWM5] = imx_clk_hw_gate2("pwm5", "perclk", base + 0x80, 26); base 486 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PWM6] = imx_clk_hw_gate2("pwm6", "perclk", base + 0x80, 28); base 487 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_PWM7] = imx_clk_hw_gate2("pwm7", "perclk", base + 0x80, 30); base 489 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CKO1] = imx_clk_hw_gate("cko1", "cko1_podf", base + 0x60, 7); base 490 drivers/clk/imx/clk-imx6sx.c hws[IMX6SX_CLK_CKO2] = imx_clk_hw_gate("cko2", "cko2_podf", base + 0x60, 24); base 493 drivers/clk/imx/clk-imx6sx.c imx_mmdc_mask_handshake(base, 0); base 117 drivers/clk/imx/clk-imx6ul.c void __iomem *base; base 137 drivers/clk/imx/clk-imx6ul.c base = of_iomap(np, 0); base 139 drivers/clk/imx/clk-imx6ul.c WARN_ON(!base); base 141 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 142 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 143 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 144 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 145 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 146 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 147 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); base 149 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); base 150 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); base 151 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); base 152 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); base 153 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); base 154 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); base 155 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); base 157 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); base 158 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); base 159 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); base 160 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); base 161 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); base 162 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); base 163 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); base 164 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CSI_SEL] = imx_clk_hw_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT); base 176 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); base 177 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); base 178 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); base 179 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); base 180 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); base 181 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); base 189 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); base 190 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); base 196 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6); base 197 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6); base 200 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); base 201 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); base 202 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); base 203 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL2_PFD3] = imx_clk_hw_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3); base 204 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); base 205 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); base 206 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); base 207 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); base 210 drivers/clk/imx/clk-imx6ul.c base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); base 212 drivers/clk/imx/clk-imx6ul.c base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock); base 214 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20); base 216 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ENET_PTP] = imx_clk_hw_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21); base 219 drivers/clk/imx/clk-imx6ul.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); base 221 drivers/clk/imx/clk-imx6ul.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock); base 223 drivers/clk/imx/clk-imx6ul.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); base 225 drivers/clk/imx/clk-imx6ul.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); base 234 drivers/clk/imx/clk-imx6ul.c base = of_iomap(np, 0); base 235 drivers/clk/imx/clk-imx6ul.c WARN_ON(!base); base 237 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CA7_SECONDARY_SEL] = imx_clk_hw_mux("ca7_secondary_sel", base + 0xc, 3, 1, ca7_secondary_sels, ARRAY_SIZE(ca7_secondary_sels)); base 238 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_STEP] = imx_clk_hw_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels)); base 239 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PLL1_SW] = imx_clk_hw_mux_flags("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0); base 240 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_AXI_ALT_SEL] = imx_clk_hw_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); base 241 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_AXI_SEL] = imx_clk_hw_mux_flags("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0); base 242 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); base 243 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); base 244 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); base 245 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); base 246 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_EIM_SLOW_SEL] = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); base 247 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPMI_SEL] = imx_clk_hw_mux("gpmi_sel", base + 0x1c, 19, 1, gpmi_sels, ARRAY_SIZE(gpmi_sels)); base 248 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_BCH_SEL] = imx_clk_hw_mux("bch_sel", base + 0x1c, 18, 1, bch_sels, ARRAY_SIZE(bch_sels)); base 249 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 250 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); base 251 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI3_SEL] = imx_clk_hw_mux("sai3_sel", base + 0x1c, 14, 2, sai_sels, ARRAY_SIZE(sai_sels)); base 252 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI2_SEL] = imx_clk_hw_mux("sai2_sel", base + 0x1c, 12, 2, sai_sels, ARRAY_SIZE(sai_sels)); base 253 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI1_SEL] = imx_clk_hw_mux("sai1_sel", base + 0x1c, 10, 2, sai_sels, ARRAY_SIZE(sai_sels)); base 254 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_QSPI1_SEL] = imx_clk_hw_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels)); base 255 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PERCLK_SEL] = imx_clk_hw_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); base 256 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CAN_SEL] = imx_clk_hw_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); base 258 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel", base + 0x20, 19, 2, esai_sels, ARRAY_SIZE(esai_sels)); base 259 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); base 260 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels)); base 261 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels)); base 262 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); base 264 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_hw_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels)); base 265 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SIM_SEL] = imx_clk_hw_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels)); base 267 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_EPDC_PRE_SEL] = imx_clk_hw_mux("epdc_pre_sel", base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels)); base 268 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_EPDC_SEL] = imx_clk_hw_mux("epdc_sel", base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels)); base 270 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); base 271 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_hw_mux_flags("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels), CLK_SET_RATE_PARENT); base 272 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); base 274 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); base 275 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels)); base 277 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); base 278 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); base 279 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CKO] = imx_clk_hw_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); base 286 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); base 287 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); base 289 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); base 290 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); base 291 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2); base 292 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_LCDIF_PODF] = imx_clk_hw_divider("lcdif_podf", "lcdif_pred", base + 0x18, 23, 3); base 293 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_QSPI1_PDOF] = imx_clk_hw_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3); base 294 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_EIM_SLOW_PODF] = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); base 295 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PERCLK] = imx_clk_hw_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); base 296 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CAN_PODF] = imx_clk_hw_divider("can_podf", "can_sel", base + 0x20, 2, 6); base 297 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPMI_PODF] = imx_clk_hw_divider("gpmi_podf", "gpmi_sel", base + 0x24, 22, 3); base 298 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_BCH_PODF] = imx_clk_hw_divider("bch_podf", "bch_sel", base + 0x24, 19, 3); base 299 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); base 300 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); base 301 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); base 302 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI3_PRED] = imx_clk_hw_divider("sai3_pred", "sai3_sel", base + 0x28, 22, 3); base 303 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI3_PODF] = imx_clk_hw_divider("sai3_podf", "sai3_pred", base + 0x28, 16, 6); base 304 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI1_PRED] = imx_clk_hw_divider("sai1_pred", "sai1_sel", base + 0x28, 6, 3); base 305 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI1_PODF] = imx_clk_hw_divider("sai1_podf", "sai1_pred", base + 0x28, 0, 6); base 307 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_ESAI_PRED] = imx_clk_hw_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); base 308 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_ESAI_PODF] = imx_clk_hw_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); base 310 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ENFC_PRED] = imx_clk_hw_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); base 311 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ENFC_PODF] = imx_clk_hw_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); base 312 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI2_PRED] = imx_clk_hw_divider("sai2_pred", "sai2_sel", base + 0x2c, 6, 3); base 313 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI2_PODF] = imx_clk_hw_divider("sai2_podf", "sai2_pred", base + 0x2c, 0, 6); base 314 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); base 315 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); base 317 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SIM_PODF] = imx_clk_hw_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3); base 319 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_EPDC_PODF] = imx_clk_hw_divider("epdc_podf", "epdc_pre_sel", base + 0x34, 12, 3); base 320 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ECSPI_PODF] = imx_clk_hw_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6); base 321 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_LCDIF_PRED] = imx_clk_hw_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3); base 322 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CSI_PODF] = imx_clk_hw_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); base 324 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CKO1_PODF] = imx_clk_hw_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); base 325 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CKO2_PODF] = imx_clk_hw_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); base 327 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); base 328 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_MMDC_PODF] = imx_clk_hw_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); base 329 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_AXI_PODF] = imx_clk_hw_busy_divider("axi_podf", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); base 330 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); base 333 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_AIPSTZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL); base 334 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_AIPSTZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL); base 335 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_APBHDMA] = imx_clk_hw_gate2("apbh_dma", "bch_podf", base + 0x68, 4); base 336 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); base 337 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); base 339 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68, 8); base 340 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68, 10); base 341 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg", "ipg", base + 0x68, 12); base 343 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_DCP_CLK] = imx_clk_hw_gate2("dcp", "ahb", base + 0x68, 10); base 344 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x68, 12); base 345 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ENET_AHB] = imx_clk_hw_gate2("enet_ahb", "ahb", base + 0x68, 12); base 347 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg", "ipg", base + 0x68, 14); base 348 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial", "can_podf", base + 0x68, 16); base 349 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg", "ipg", base + 0x68, 18); base 350 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial", "can_podf", base + 0x68, 20); base 351 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPT2_BUS] = imx_clk_hw_gate2("gpt2_bus", "perclk", base + 0x68, 24); base 352 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_hw_gate2("gpt2_serial", "perclk", base + 0x68, 26); base 353 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART2_IPG] = imx_clk_hw_gate2("uart2_ipg", "ipg", base + 0x68, 28); base 354 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART2_SERIAL] = imx_clk_hw_gate2("uart2_serial", "uart_podf", base + 0x68, 28); base 356 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_AIPSTZ3] = imx_clk_hw_gate2("aips_tz3", "ahb", base + 0x80, 18); base 357 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPIO2] = imx_clk_hw_gate2("gpio2", "ipg", base + 0x68, 30); base 360 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); base 361 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2); base 362 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4); base 363 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6); base 364 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ADC2] = imx_clk_hw_gate2("adc2", "ipg", base + 0x6c, 8); base 365 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART3_IPG] = imx_clk_hw_gate2("uart3_ipg", "ipg", base + 0x6c, 10); base 366 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART3_SERIAL] = imx_clk_hw_gate2("uart3_serial", "uart_podf", base + 0x6c, 10); base 367 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "perclk", base + 0x6c, 12); base 368 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "perclk", base + 0x6c, 14); base 369 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ADC1] = imx_clk_hw_gate2("adc1", "ipg", base + 0x6c, 16); base 370 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPT1_BUS] = imx_clk_hw_gate2("gpt1_bus", "perclk", base + 0x6c, 20); base 371 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_hw_gate2("gpt1_serial", "perclk", base + 0x6c, 22); base 372 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART4_IPG] = imx_clk_hw_gate2("uart4_ipg", "ipg", base + 0x6c, 24); base 373 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART4_SERIAL] = imx_clk_hw_gate2("uart4_serial", "uart_podf", base + 0x6c, 24); base 374 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPIO1] = imx_clk_hw_gate2("gpio1", "ipg", base + 0x6c, 26); base 375 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPIO5] = imx_clk_hw_gate2("gpio5", "ipg", base + 0x6c, 30); base 379 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal", "esai_podf", base + 0x70, 0, &share_count_esai); base 380 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x70, 0, &share_count_esai); base 381 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x70, 0, &share_count_esai); base 383 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CSI] = imx_clk_hw_gate2("csi", "csi_podf", base + 0x70, 2); base 384 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "perclk", base + 0x70, 6); base 385 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "perclk", base + 0x70, 8); base 386 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "perclk", base + 0x70, 10); base 387 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_OCOTP] = imx_clk_hw_gate2("ocotp", "ipg", base + 0x70, 12); base 388 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_IOMUXC] = imx_clk_hw_gate2("iomuxc", "lcdif_podf", base + 0x70, 14); base 389 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPIO3] = imx_clk_hw_gate2("gpio3", "ipg", base + 0x70, 26); base 390 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif_apb", "axi", base + 0x70, 28); base 391 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PXP] = imx_clk_hw_gate2("pxp", "axi", base + 0x70, 30); base 394 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART5_IPG] = imx_clk_hw_gate2("uart5_ipg", "ipg", base + 0x74, 2); base 395 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART5_SERIAL] = imx_clk_hw_gate2("uart5_serial", "uart_podf", base + 0x74, 2); base 397 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x74, 4); base 398 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ENET_AHB] = imx_clk_hw_gate2("enet_ahb", "ahb", base + 0x74, 4); base 400 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_EPDC_ACLK] = imx_clk_hw_gate2("epdc_aclk", "axi", base + 0x74, 4); base 401 drivers/clk/imx/clk-imx6ul.c hws[IMX6ULL_CLK_EPDC_PIX] = imx_clk_hw_gate2("epdc_pix", "epdc_podf", base + 0x74, 4); base 403 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART6_IPG] = imx_clk_hw_gate2("uart6_ipg", "ipg", base + 0x74, 6); base 404 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART6_SERIAL] = imx_clk_hw_gate2("uart6_serial", "uart_podf", base + 0x74, 6); base 405 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10); base 406 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPIO4] = imx_clk_hw_gate2("gpio4", "ipg", base + 0x74, 12); base 407 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_QSPI] = imx_clk_hw_gate2("qspi1", "qspi1_podf", base + 0x74, 14); base 408 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_WDOG1] = imx_clk_hw_gate2("wdog1", "ipg", base + 0x74, 16); base 409 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_hw_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL); base 410 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); base 411 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2_flags("mmdc_p1_ipg", "ipg", base + 0x74, 26, CLK_IS_CRITICAL); base 412 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_AXI] = imx_clk_hw_gate_flags("axi", "axi_podf", base + 0x74, 28, CLK_IS_CRITICAL); base 415 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PER_BCH] = imx_clk_hw_gate2("per_bch", "bch_podf", base + 0x78, 12); base 416 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "perclk", base + 0x78, 16); base 417 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "perclk", base + 0x78, 18); base 418 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "perclk", base + 0x78, 20); base 419 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "perclk", base + 0x78, 22); base 420 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb", "bch_podf", base + 0x78, 24); base 421 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPMI_BCH] = imx_clk_hw_gate2("gpmi_bch", "gpmi_podf", base + 0x78, 26); base 422 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io", "enfc_podf", base + 0x78, 28); base 423 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_GPMI_APB] = imx_clk_hw_gate2("gpmi_apb", "bch_podf", base + 0x78, 30); base 426 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); base 427 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ahb", base + 0x7c, 6); base 428 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_KPP] = imx_clk_hw_gate2("kpp", "ipg", base + 0x7c, 8); base 429 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_WDOG2] = imx_clk_hw_gate2("wdog2", "ipg", base + 0x7c, 10); base 430 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12); base 431 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); base 432 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); base 433 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI3] = imx_clk_hw_gate2_shared("sai3", "sai3_podf", base + 0x7c, 22, &share_count_sai3); base 434 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI3_IPG] = imx_clk_hw_gate2_shared("sai3_ipg", "ipg", base + 0x7c, 22, &share_count_sai3); base 435 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART1_IPG] = imx_clk_hw_gate2("uart1_ipg", "ipg", base + 0x7c, 24); base 436 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART1_SERIAL] = imx_clk_hw_gate2("uart1_serial", "uart_podf", base + 0x7c, 24); base 437 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART7_IPG] = imx_clk_hw_gate2("uart7_ipg", "ipg", base + 0x7c, 26); base 438 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART7_SERIAL] = imx_clk_hw_gate2("uart7_serial", "uart_podf", base + 0x7c, 26); base 439 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI1] = imx_clk_hw_gate2_shared("sai1", "sai1_podf", base + 0x7c, 28, &share_count_sai1); base 440 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI1_IPG] = imx_clk_hw_gate2_shared("sai1_ipg", "ipg", base + 0x7c, 28, &share_count_sai1); base 441 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI2] = imx_clk_hw_gate2_shared("sai2", "sai2_podf", base + 0x7c, 30, &share_count_sai2); base 442 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SAI2_IPG] = imx_clk_hw_gate2_shared("sai2_ipg", "ipg", base + 0x7c, 30, &share_count_sai2); base 445 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0); base 446 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); base 447 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); base 449 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SIM1] = imx_clk_hw_gate2("sim1", "sim_sel", base + 0x80, 6); base 450 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_SIM2] = imx_clk_hw_gate2("sim2", "sim_sel", base + 0x80, 8); base 452 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_EIM] = imx_clk_hw_gate2("eim", "eim_slow_podf", base + 0x80, 10); base 453 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PWM8] = imx_clk_hw_gate2("pwm8", "perclk", base + 0x80, 16); base 454 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART8_IPG] = imx_clk_hw_gate2("uart8_ipg", "ipg", base + 0x80, 14); base 455 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_UART8_SERIAL] = imx_clk_hw_gate2("uart8_serial", "uart_podf", base + 0x80, 14); base 456 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_WDOG3] = imx_clk_hw_gate2("wdog3", "ipg", base + 0x80, 20); base 457 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_I2C4] = imx_clk_hw_gate2("i2c4", "perclk", base + 0x80, 24); base 458 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PWM5] = imx_clk_hw_gate2("pwm5", "perclk", base + 0x80, 26); base 459 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PWM6] = imx_clk_hw_gate2("pwm6", "perclk", base + 0x80, 28); base 460 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_PWM7] = imx_clk_hw_gate2("pwm7", "perclk", base + 0x80, 30); base 463 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CKO1] = imx_clk_hw_gate("cko1", "cko1_podf", base + 0x60, 7); base 464 drivers/clk/imx/clk-imx6ul.c hws[IMX6UL_CLK_CKO2] = imx_clk_hw_gate("cko2", "cko2_podf", base + 0x60, 24); base 467 drivers/clk/imx/clk-imx6ul.c imx_mmdc_mask_handshake(base, 0); base 394 drivers/clk/imx/clk-imx7d.c void __iomem *base; base 410 drivers/clk/imx/clk-imx7d.c base = of_iomap(np, 0); base 411 drivers/clk/imx/clk-imx7d.c WARN_ON(!base); base 414 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); base 415 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); base 416 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); base 417 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); base 418 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); base 419 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); base 421 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ARM_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7f); base 422 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_DRAM_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_DDR_IMX7, "pll_dram_main", "osc", base + 0x70, 0x7f); base 423 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1); base 424 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ENET_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0xe0, 0x0); base 425 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_AUDIO_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_AV_IMX7, "pll_audio_main", "osc", base + 0xf0, 0x7f); base 426 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_VIDEO_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_AV_IMX7, "pll_video_main", "osc", base + 0x130, 0x7f); base 428 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ARM_MAIN_BYPASS] = imx_clk_hw_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT); base 429 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_hw_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT); base 430 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_MAIN_BYPASS] = imx_clk_hw_mux_flags("pll_sys_main_bypass", base + 0xb0, 16, 1, pll_sys_bypass_sel, ARRAY_SIZE(pll_sys_bypass_sel), CLK_SET_RATE_PARENT); base 431 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ENET_MAIN_BYPASS] = imx_clk_hw_mux_flags("pll_enet_main_bypass", base + 0xe0, 16, 1, pll_enet_bypass_sel, ARRAY_SIZE(pll_enet_bypass_sel), CLK_SET_RATE_PARENT); base 432 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_hw_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT); base 433 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_hw_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT); base 435 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_hw_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13); base 436 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_hw_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13); base 437 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_hw_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13); base 438 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_hw_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13); base 439 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_hw_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13); base 442 drivers/clk/imx/clk-imx7d.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock); base 444 drivers/clk/imx/clk-imx7d.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock); base 446 drivers/clk/imx/clk-imx7d.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); base 448 drivers/clk/imx/clk-imx7d.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 19, 2, 0, test_div_table, &imx_ccm_lock); base 450 drivers/clk/imx/clk-imx7d.c CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock); base 452 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_hw_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0); base 453 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_hw_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1); base 454 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_hw_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main_clk", base + 0xc0, 2); base 456 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_PFD3_CLK] = imx_clk_hw_pfd("pll_sys_pfd3_clk", "pll_sys_main_clk", base + 0xc0, 3); base 457 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_PFD4_CLK] = imx_clk_hw_pfd("pll_sys_pfd4_clk", "pll_sys_main_clk", base + 0xd0, 0); base 458 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_PFD5_CLK] = imx_clk_hw_pfd("pll_sys_pfd5_clk", "pll_sys_main_clk", base + 0xd0, 1); base 459 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_PFD6_CLK] = imx_clk_hw_pfd("pll_sys_pfd6_clk", "pll_sys_main_clk", base + 0xd0, 2); base 460 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_PFD7_CLK] = imx_clk_hw_pfd("pll_sys_pfd7_clk", "pll_sys_main_clk", base + 0xd0, 3); base 467 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_MAIN_480M_CLK] = imx_clk_hw_gate_dis_flags("pll_sys_main_480m_clk", "pll_sys_main_480m", base + 0xb0, 4, CLK_IS_CRITICAL); base 468 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_MAIN_240M_CLK] = imx_clk_hw_gate_dis("pll_sys_main_240m_clk", "pll_sys_main_240m", base + 0xb0, 5); base 469 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_MAIN_120M_CLK] = imx_clk_hw_gate_dis("pll_sys_main_120m_clk", "pll_sys_main_120m", base + 0xb0, 6); base 470 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_DRAM_MAIN_533M_CLK] = imx_clk_hw_gate("pll_dram_533m_clk", "pll_dram_533m", base + 0x70, 12); base 476 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_PFD0_196M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd0_196m_clk", "pll_sys_pfd0_196m", base + 0xb0, 26); base 477 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_PFD1_166M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd1_166m_clk", "pll_sys_pfd1_166m", base + 0xb0, 27); base 478 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_SYS_PFD2_135M_CLK] = imx_clk_hw_gate_dis("pll_sys_pfd2_135m_clk", "pll_sys_pfd2_135m", base + 0xb0, 28); base 489 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ENET_MAIN_500M_CLK] = imx_clk_hw_gate("pll_enet_500m_clk", "pll_enet_500m", base + 0xe0, 12); base 490 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ENET_MAIN_250M_CLK] = imx_clk_hw_gate("pll_enet_250m_clk", "pll_enet_250m", base + 0xe0, 11); base 491 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ENET_MAIN_125M_CLK] = imx_clk_hw_gate("pll_enet_125m_clk", "pll_enet_125m", base + 0xe0, 10); base 492 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ENET_MAIN_100M_CLK] = imx_clk_hw_gate("pll_enet_100m_clk", "pll_enet_100m", base + 0xe0, 9); base 493 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ENET_MAIN_50M_CLK] = imx_clk_hw_gate("pll_enet_50m_clk", "pll_enet_50m", base + 0xe0, 8); base 494 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ENET_MAIN_40M_CLK] = imx_clk_hw_gate("pll_enet_40m_clk", "pll_enet_40m", base + 0xe0, 7); base 495 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PLL_ENET_MAIN_25M_CLK] = imx_clk_hw_gate("pll_enet_25m_clk", "pll_enet_25m", base + 0xe0, 6); base 497 drivers/clk/imx/clk-imx7d.c hws[IMX7D_LVDS1_OUT_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x170, 0, 5, lvds1_sel, ARRAY_SIZE(lvds1_sel)); base 498 drivers/clk/imx/clk-imx7d.c hws[IMX7D_LVDS1_OUT_CLK] = imx_clk_hw_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x170, 5, BIT(6)); base 501 drivers/clk/imx/clk-imx7d.c base = of_iomap(np, 0); base 502 drivers/clk/imx/clk-imx7d.c WARN_ON(!base); base 504 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_hw_mux2("arm_a7_src", base + 0x8000, 24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel)); base 505 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_hw_mux2("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel)); base 506 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_hw_mux2("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel)); base 507 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_hw_mux2("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel)); base 508 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_hw_mux2("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel)); base 509 drivers/clk/imx/clk-imx7d.c hws[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_hw_mux2("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel)); base 510 drivers/clk/imx/clk-imx7d.c hws[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_hw_mux2("ahb_src", base + 0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel)); base 511 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_hw_mux2("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel)); base 512 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel)); base 513 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_hw_mux2("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel)); base 514 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel)); base 515 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_hw_mux2("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel)); base 516 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel)); base 517 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel)); base 518 drivers/clk/imx/clk-imx7d.c hws[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_hw_mux2("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel)); base 519 drivers/clk/imx/clk-imx7d.c hws[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_hw_mux2("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel)); base 520 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_hw_mux2("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel)); base 521 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_hw_mux2("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel)); base 522 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_hw_mux2("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel)); base 523 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI1_ROOT_SRC] = imx_clk_hw_mux2("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel)); base 524 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI2_ROOT_SRC] = imx_clk_hw_mux2("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel)); base 525 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI3_ROOT_SRC] = imx_clk_hw_mux2("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel)); base 526 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SPDIF_ROOT_SRC] = imx_clk_hw_mux2("spdif_src", base + 0xa680, 24, 3, spdif_sel, ARRAY_SIZE(spdif_sel)); base 527 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_hw_mux2("enet1_ref_src", base + 0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel)); base 528 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_hw_mux2("enet1_time_src", base + 0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel)); base 529 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_hw_mux2("enet2_ref_src", base + 0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel)); base 530 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_hw_mux2("enet2_time_src", base + 0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel)); base 531 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_hw_mux2("enet_phy_ref_src", base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel)); base 532 drivers/clk/imx/clk-imx7d.c hws[IMX7D_EIM_ROOT_SRC] = imx_clk_hw_mux2("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel)); base 533 drivers/clk/imx/clk-imx7d.c hws[IMX7D_NAND_ROOT_SRC] = imx_clk_hw_mux2("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel)); base 534 drivers/clk/imx/clk-imx7d.c hws[IMX7D_QSPI_ROOT_SRC] = imx_clk_hw_mux2("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel)); base 535 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC1_ROOT_SRC] = imx_clk_hw_mux2("usdhc1_src", base + 0xab00, 24, 3, usdhc1_sel, ARRAY_SIZE(usdhc1_sel)); base 536 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC2_ROOT_SRC] = imx_clk_hw_mux2("usdhc2_src", base + 0xab80, 24, 3, usdhc2_sel, ARRAY_SIZE(usdhc2_sel)); base 537 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC3_ROOT_SRC] = imx_clk_hw_mux2("usdhc3_src", base + 0xac00, 24, 3, usdhc3_sel, ARRAY_SIZE(usdhc3_sel)); base 538 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CAN1_ROOT_SRC] = imx_clk_hw_mux2("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel)); base 539 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CAN2_ROOT_SRC] = imx_clk_hw_mux2("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel)); base 540 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C1_ROOT_SRC] = imx_clk_hw_mux2("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel)); base 541 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C2_ROOT_SRC] = imx_clk_hw_mux2("i2c2_src", base + 0xae00, 24, 3, i2c2_sel, ARRAY_SIZE(i2c2_sel)); base 542 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C3_ROOT_SRC] = imx_clk_hw_mux2("i2c3_src", base + 0xae80, 24, 3, i2c3_sel, ARRAY_SIZE(i2c3_sel)); base 543 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C4_ROOT_SRC] = imx_clk_hw_mux2("i2c4_src", base + 0xaf00, 24, 3, i2c4_sel, ARRAY_SIZE(i2c4_sel)); base 544 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART1_ROOT_SRC] = imx_clk_hw_mux2("uart1_src", base + 0xaf80, 24, 3, uart1_sel, ARRAY_SIZE(uart1_sel)); base 545 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART2_ROOT_SRC] = imx_clk_hw_mux2("uart2_src", base + 0xb000, 24, 3, uart2_sel, ARRAY_SIZE(uart2_sel)); base 546 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART3_ROOT_SRC] = imx_clk_hw_mux2("uart3_src", base + 0xb080, 24, 3, uart3_sel, ARRAY_SIZE(uart3_sel)); base 547 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART4_ROOT_SRC] = imx_clk_hw_mux2("uart4_src", base + 0xb100, 24, 3, uart4_sel, ARRAY_SIZE(uart4_sel)); base 548 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART5_ROOT_SRC] = imx_clk_hw_mux2("uart5_src", base + 0xb180, 24, 3, uart5_sel, ARRAY_SIZE(uart5_sel)); base 549 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART6_ROOT_SRC] = imx_clk_hw_mux2("uart6_src", base + 0xb200, 24, 3, uart6_sel, ARRAY_SIZE(uart6_sel)); base 550 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART7_ROOT_SRC] = imx_clk_hw_mux2("uart7_src", base + 0xb280, 24, 3, uart7_sel, ARRAY_SIZE(uart7_sel)); base 551 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI1_ROOT_SRC] = imx_clk_hw_mux2("ecspi1_src", base + 0xb300, 24, 3, ecspi1_sel, ARRAY_SIZE(ecspi1_sel)); base 552 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI2_ROOT_SRC] = imx_clk_hw_mux2("ecspi2_src", base + 0xb380, 24, 3, ecspi2_sel, ARRAY_SIZE(ecspi2_sel)); base 553 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI3_ROOT_SRC] = imx_clk_hw_mux2("ecspi3_src", base + 0xb400, 24, 3, ecspi3_sel, ARRAY_SIZE(ecspi3_sel)); base 554 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI4_ROOT_SRC] = imx_clk_hw_mux2("ecspi4_src", base + 0xb480, 24, 3, ecspi4_sel, ARRAY_SIZE(ecspi4_sel)); base 555 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM1_ROOT_SRC] = imx_clk_hw_mux2("pwm1_src", base + 0xb500, 24, 3, pwm1_sel, ARRAY_SIZE(pwm1_sel)); base 556 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM2_ROOT_SRC] = imx_clk_hw_mux2("pwm2_src", base + 0xb580, 24, 3, pwm2_sel, ARRAY_SIZE(pwm2_sel)); base 557 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM3_ROOT_SRC] = imx_clk_hw_mux2("pwm3_src", base + 0xb600, 24, 3, pwm3_sel, ARRAY_SIZE(pwm3_sel)); base 558 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM4_ROOT_SRC] = imx_clk_hw_mux2("pwm4_src", base + 0xb680, 24, 3, pwm4_sel, ARRAY_SIZE(pwm4_sel)); base 559 drivers/clk/imx/clk-imx7d.c hws[IMX7D_FLEXTIMER1_ROOT_SRC] = imx_clk_hw_mux2("flextimer1_src", base + 0xb700, 24, 3, flextimer1_sel, ARRAY_SIZE(flextimer1_sel)); base 560 drivers/clk/imx/clk-imx7d.c hws[IMX7D_FLEXTIMER2_ROOT_SRC] = imx_clk_hw_mux2("flextimer2_src", base + 0xb780, 24, 3, flextimer2_sel, ARRAY_SIZE(flextimer2_sel)); base 561 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SIM1_ROOT_SRC] = imx_clk_hw_mux2("sim1_src", base + 0xb800, 24, 3, sim1_sel, ARRAY_SIZE(sim1_sel)); base 562 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SIM2_ROOT_SRC] = imx_clk_hw_mux2("sim2_src", base + 0xb880, 24, 3, sim2_sel, ARRAY_SIZE(sim2_sel)); base 563 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT1_ROOT_SRC] = imx_clk_hw_mux2("gpt1_src", base + 0xb900, 24, 3, gpt1_sel, ARRAY_SIZE(gpt1_sel)); base 564 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT2_ROOT_SRC] = imx_clk_hw_mux2("gpt2_src", base + 0xb980, 24, 3, gpt2_sel, ARRAY_SIZE(gpt2_sel)); base 565 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT3_ROOT_SRC] = imx_clk_hw_mux2("gpt3_src", base + 0xba00, 24, 3, gpt3_sel, ARRAY_SIZE(gpt3_sel)); base 566 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT4_ROOT_SRC] = imx_clk_hw_mux2("gpt4_src", base + 0xba80, 24, 3, gpt4_sel, ARRAY_SIZE(gpt4_sel)); base 567 drivers/clk/imx/clk-imx7d.c hws[IMX7D_TRACE_ROOT_SRC] = imx_clk_hw_mux2("trace_src", base + 0xbb00, 24, 3, trace_sel, ARRAY_SIZE(trace_sel)); base 568 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WDOG_ROOT_SRC] = imx_clk_hw_mux2("wdog_src", base + 0xbb80, 24, 3, wdog_sel, ARRAY_SIZE(wdog_sel)); base 569 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CSI_MCLK_ROOT_SRC] = imx_clk_hw_mux2("csi_mclk_src", base + 0xbc00, 24, 3, csi_mclk_sel, ARRAY_SIZE(csi_mclk_sel)); base 570 drivers/clk/imx/clk-imx7d.c hws[IMX7D_AUDIO_MCLK_ROOT_SRC] = imx_clk_hw_mux2("audio_mclk_src", base + 0xbc80, 24, 3, audio_mclk_sel, ARRAY_SIZE(audio_mclk_sel)); base 571 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WRCLK_ROOT_SRC] = imx_clk_hw_mux2("wrclk_src", base + 0xbd00, 24, 3, wrclk_sel, ARRAY_SIZE(wrclk_sel)); base 572 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CLKO1_ROOT_SRC] = imx_clk_hw_mux2("clko1_src", base + 0xbd80, 24, 3, clko1_sel, ARRAY_SIZE(clko1_sel)); base 573 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CLKO2_ROOT_SRC] = imx_clk_hw_mux2("clko2_src", base + 0xbe00, 24, 3, clko2_sel, ARRAY_SIZE(clko2_sel)); base 575 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ARM_A7_ROOT_CG] = imx_clk_hw_gate3("arm_a7_cg", "arm_a7_src", base + 0x8000, 28); base 576 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ARM_M4_ROOT_CG] = imx_clk_hw_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); base 577 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MAIN_AXI_ROOT_CG] = imx_clk_hw_gate3("axi_cg", "axi_src", base + 0x8800, 28); base 578 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DISP_AXI_ROOT_CG] = imx_clk_hw_gate3("disp_axi_cg", "disp_axi_src", base + 0x8880, 28); base 579 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET_AXI_ROOT_CG] = imx_clk_hw_gate3("enet_axi_cg", "enet_axi_src", base + 0x8900, 28); base 580 drivers/clk/imx/clk-imx7d.c hws[IMX7D_NAND_USDHC_BUS_ROOT_CG] = imx_clk_hw_gate3("nand_usdhc_cg", "nand_usdhc_src", base + 0x8980, 28); base 581 drivers/clk/imx/clk-imx7d.c hws[IMX7D_AHB_CHANNEL_ROOT_CG] = imx_clk_hw_gate3("ahb_cg", "ahb_src", base + 0x9000, 28); base 582 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_PHYM_ROOT_CG] = imx_clk_hw_gate3("dram_phym_cg", "dram_phym_src", base + 0x9800, 28); base 583 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_ROOT_CG] = imx_clk_hw_gate3("dram_cg", "dram_src", base + 0x9880, 28); base 584 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_PHYM_ALT_ROOT_CG] = imx_clk_hw_gate3("dram_phym_alt_cg", "dram_phym_alt_src", base + 0xa000, 28); base 585 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_ALT_ROOT_CG] = imx_clk_hw_gate3("dram_alt_cg", "dram_alt_src", base + 0xa080, 28); base 586 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USB_HSIC_ROOT_CG] = imx_clk_hw_gate3("usb_hsic_cg", "usb_hsic_src", base + 0xa100, 28); base 587 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PCIE_CTRL_ROOT_CG] = imx_clk_hw_gate3("pcie_ctrl_cg", "pcie_ctrl_src", base + 0xa180, 28); base 588 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PCIE_PHY_ROOT_CG] = imx_clk_hw_gate3("pcie_phy_cg", "pcie_phy_src", base + 0xa200, 28); base 589 drivers/clk/imx/clk-imx7d.c hws[IMX7D_EPDC_PIXEL_ROOT_CG] = imx_clk_hw_gate3("epdc_pixel_cg", "epdc_pixel_src", base + 0xa280, 28); base 590 drivers/clk/imx/clk-imx7d.c hws[IMX7D_LCDIF_PIXEL_ROOT_CG] = imx_clk_hw_gate3("lcdif_pixel_cg", "lcdif_pixel_src", base + 0xa300, 28); base 591 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_DSI_ROOT_CG] = imx_clk_hw_gate3("mipi_dsi_cg", "mipi_dsi_src", base + 0xa380, 28); base 592 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_CSI_ROOT_CG] = imx_clk_hw_gate3("mipi_csi_cg", "mipi_csi_src", base + 0xa400, 28); base 593 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_DPHY_ROOT_CG] = imx_clk_hw_gate3("mipi_dphy_cg", "mipi_dphy_src", base + 0xa480, 28); base 594 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI1_ROOT_CG] = imx_clk_hw_gate3("sai1_cg", "sai1_src", base + 0xa500, 28); base 595 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI2_ROOT_CG] = imx_clk_hw_gate3("sai2_cg", "sai2_src", base + 0xa580, 28); base 596 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI3_ROOT_CG] = imx_clk_hw_gate3("sai3_cg", "sai3_src", base + 0xa600, 28); base 597 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SPDIF_ROOT_CG] = imx_clk_hw_gate3("spdif_cg", "spdif_src", base + 0xa680, 28); base 598 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET1_REF_ROOT_CG] = imx_clk_hw_gate3("enet1_ref_cg", "enet1_ref_src", base + 0xa700, 28); base 599 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET1_TIME_ROOT_CG] = imx_clk_hw_gate3("enet1_time_cg", "enet1_time_src", base + 0xa780, 28); base 600 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET2_REF_ROOT_CG] = imx_clk_hw_gate3("enet2_ref_cg", "enet2_ref_src", base + 0xa800, 28); base 601 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET2_TIME_ROOT_CG] = imx_clk_hw_gate3("enet2_time_cg", "enet2_time_src", base + 0xa880, 28); base 602 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET_PHY_REF_ROOT_CG] = imx_clk_hw_gate3("enet_phy_ref_cg", "enet_phy_ref_src", base + 0xa900, 28); base 603 drivers/clk/imx/clk-imx7d.c hws[IMX7D_EIM_ROOT_CG] = imx_clk_hw_gate3("eim_cg", "eim_src", base + 0xa980, 28); base 604 drivers/clk/imx/clk-imx7d.c hws[IMX7D_NAND_ROOT_CG] = imx_clk_hw_gate3("nand_cg", "nand_src", base + 0xaa00, 28); base 605 drivers/clk/imx/clk-imx7d.c hws[IMX7D_QSPI_ROOT_CG] = imx_clk_hw_gate3("qspi_cg", "qspi_src", base + 0xaa80, 28); base 606 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC1_ROOT_CG] = imx_clk_hw_gate3("usdhc1_cg", "usdhc1_src", base + 0xab00, 28); base 607 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC2_ROOT_CG] = imx_clk_hw_gate3("usdhc2_cg", "usdhc2_src", base + 0xab80, 28); base 608 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC3_ROOT_CG] = imx_clk_hw_gate3("usdhc3_cg", "usdhc3_src", base + 0xac00, 28); base 609 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CAN1_ROOT_CG] = imx_clk_hw_gate3("can1_cg", "can1_src", base + 0xac80, 28); base 610 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CAN2_ROOT_CG] = imx_clk_hw_gate3("can2_cg", "can2_src", base + 0xad00, 28); base 611 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C1_ROOT_CG] = imx_clk_hw_gate3("i2c1_cg", "i2c1_src", base + 0xad80, 28); base 612 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C2_ROOT_CG] = imx_clk_hw_gate3("i2c2_cg", "i2c2_src", base + 0xae00, 28); base 613 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C3_ROOT_CG] = imx_clk_hw_gate3("i2c3_cg", "i2c3_src", base + 0xae80, 28); base 614 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C4_ROOT_CG] = imx_clk_hw_gate3("i2c4_cg", "i2c4_src", base + 0xaf00, 28); base 615 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART1_ROOT_CG] = imx_clk_hw_gate3("uart1_cg", "uart1_src", base + 0xaf80, 28); base 616 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART2_ROOT_CG] = imx_clk_hw_gate3("uart2_cg", "uart2_src", base + 0xb000, 28); base 617 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART3_ROOT_CG] = imx_clk_hw_gate3("uart3_cg", "uart3_src", base + 0xb080, 28); base 618 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART4_ROOT_CG] = imx_clk_hw_gate3("uart4_cg", "uart4_src", base + 0xb100, 28); base 619 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART5_ROOT_CG] = imx_clk_hw_gate3("uart5_cg", "uart5_src", base + 0xb180, 28); base 620 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART6_ROOT_CG] = imx_clk_hw_gate3("uart6_cg", "uart6_src", base + 0xb200, 28); base 621 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART7_ROOT_CG] = imx_clk_hw_gate3("uart7_cg", "uart7_src", base + 0xb280, 28); base 622 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI1_ROOT_CG] = imx_clk_hw_gate3("ecspi1_cg", "ecspi1_src", base + 0xb300, 28); base 623 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI2_ROOT_CG] = imx_clk_hw_gate3("ecspi2_cg", "ecspi2_src", base + 0xb380, 28); base 624 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI3_ROOT_CG] = imx_clk_hw_gate3("ecspi3_cg", "ecspi3_src", base + 0xb400, 28); base 625 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI4_ROOT_CG] = imx_clk_hw_gate3("ecspi4_cg", "ecspi4_src", base + 0xb480, 28); base 626 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM1_ROOT_CG] = imx_clk_hw_gate3("pwm1_cg", "pwm1_src", base + 0xb500, 28); base 627 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM2_ROOT_CG] = imx_clk_hw_gate3("pwm2_cg", "pwm2_src", base + 0xb580, 28); base 628 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM3_ROOT_CG] = imx_clk_hw_gate3("pwm3_cg", "pwm3_src", base + 0xb600, 28); base 629 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM4_ROOT_CG] = imx_clk_hw_gate3("pwm4_cg", "pwm4_src", base + 0xb680, 28); base 630 drivers/clk/imx/clk-imx7d.c hws[IMX7D_FLEXTIMER1_ROOT_CG] = imx_clk_hw_gate3("flextimer1_cg", "flextimer1_src", base + 0xb700, 28); base 631 drivers/clk/imx/clk-imx7d.c hws[IMX7D_FLEXTIMER2_ROOT_CG] = imx_clk_hw_gate3("flextimer2_cg", "flextimer2_src", base + 0xb780, 28); base 632 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SIM1_ROOT_CG] = imx_clk_hw_gate3("sim1_cg", "sim1_src", base + 0xb800, 28); base 633 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SIM2_ROOT_CG] = imx_clk_hw_gate3("sim2_cg", "sim2_src", base + 0xb880, 28); base 634 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT1_ROOT_CG] = imx_clk_hw_gate3("gpt1_cg", "gpt1_src", base + 0xb900, 28); base 635 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT2_ROOT_CG] = imx_clk_hw_gate3("gpt2_cg", "gpt2_src", base + 0xb980, 28); base 636 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT3_ROOT_CG] = imx_clk_hw_gate3("gpt3_cg", "gpt3_src", base + 0xbA00, 28); base 637 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT4_ROOT_CG] = imx_clk_hw_gate3("gpt4_cg", "gpt4_src", base + 0xbA80, 28); base 638 drivers/clk/imx/clk-imx7d.c hws[IMX7D_TRACE_ROOT_CG] = imx_clk_hw_gate3("trace_cg", "trace_src", base + 0xbb00, 28); base 639 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WDOG_ROOT_CG] = imx_clk_hw_gate3("wdog_cg", "wdog_src", base + 0xbb80, 28); base 640 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CSI_MCLK_ROOT_CG] = imx_clk_hw_gate3("csi_mclk_cg", "csi_mclk_src", base + 0xbc00, 28); base 641 drivers/clk/imx/clk-imx7d.c hws[IMX7D_AUDIO_MCLK_ROOT_CG] = imx_clk_hw_gate3("audio_mclk_cg", "audio_mclk_src", base + 0xbc80, 28); base 642 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WRCLK_ROOT_CG] = imx_clk_hw_gate3("wrclk_cg", "wrclk_src", base + 0xbd00, 28); base 643 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CLKO1_ROOT_CG] = imx_clk_hw_gate3("clko1_cg", "clko1_src", base + 0xbd80, 28); base 644 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CLKO2_ROOT_CG] = imx_clk_hw_gate3("clko2_cg", "clko2_src", base + 0xbe00, 28); base 646 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MAIN_AXI_ROOT_PRE_DIV] = imx_clk_hw_divider2("axi_pre_div", "axi_cg", base + 0x8800, 16, 3); base 647 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DISP_AXI_ROOT_PRE_DIV] = imx_clk_hw_divider2("disp_axi_pre_div", "disp_axi_cg", base + 0x8880, 16, 3); base 648 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET_AXI_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet_axi_pre_div", "enet_axi_cg", base + 0x8900, 16, 3); base 649 drivers/clk/imx/clk-imx7d.c hws[IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV] = imx_clk_hw_divider2("nand_usdhc_pre_div", "nand_usdhc_cg", base + 0x8980, 16, 3); base 650 drivers/clk/imx/clk-imx7d.c hws[IMX7D_AHB_CHANNEL_ROOT_PRE_DIV] = imx_clk_hw_divider2("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3); base 651 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV] = imx_clk_hw_divider2("dram_phym_alt_pre_div", "dram_phym_alt_cg", base + 0xa000, 16, 3); base 652 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_ALT_ROOT_PRE_DIV] = imx_clk_hw_divider2("dram_alt_pre_div", "dram_alt_cg", base + 0xa080, 16, 3); base 653 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USB_HSIC_ROOT_PRE_DIV] = imx_clk_hw_divider2("usb_hsic_pre_div", "usb_hsic_cg", base + 0xa100, 16, 3); base 654 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PCIE_CTRL_ROOT_PRE_DIV] = imx_clk_hw_divider2("pcie_ctrl_pre_div", "pcie_ctrl_cg", base + 0xa180, 16, 3); base 655 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PCIE_PHY_ROOT_PRE_DIV] = imx_clk_hw_divider2("pcie_phy_pre_div", "pcie_phy_cg", base + 0xa200, 16, 3); base 656 drivers/clk/imx/clk-imx7d.c hws[IMX7D_EPDC_PIXEL_ROOT_PRE_DIV] = imx_clk_hw_divider2("epdc_pixel_pre_div", "epdc_pixel_cg", base + 0xa280, 16, 3); base 657 drivers/clk/imx/clk-imx7d.c hws[IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV] = imx_clk_hw_divider2("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa300, 16, 3); base 658 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_DSI_ROOT_PRE_DIV] = imx_clk_hw_divider2("mipi_dsi_pre_div", "mipi_dsi_cg", base + 0xa380, 16, 3); base 659 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_CSI_ROOT_PRE_DIV] = imx_clk_hw_divider2("mipi_csi_pre_div", "mipi_csi_cg", base + 0xa400, 16, 3); base 660 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_DPHY_ROOT_PRE_DIV] = imx_clk_hw_divider2("mipi_dphy_pre_div", "mipi_dphy_cg", base + 0xa480, 16, 3); base 661 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI1_ROOT_PRE_DIV] = imx_clk_hw_divider2("sai1_pre_div", "sai1_cg", base + 0xa500, 16, 3); base 662 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI2_ROOT_PRE_DIV] = imx_clk_hw_divider2("sai2_pre_div", "sai2_cg", base + 0xa580, 16, 3); base 663 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI3_ROOT_PRE_DIV] = imx_clk_hw_divider2("sai3_pre_div", "sai3_cg", base + 0xa600, 16, 3); base 664 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SPDIF_ROOT_PRE_DIV] = imx_clk_hw_divider2("spdif_pre_div", "spdif_cg", base + 0xa680, 16, 3); base 665 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET1_REF_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet1_ref_pre_div", "enet1_ref_cg", base + 0xa700, 16, 3); base 666 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET1_TIME_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet1_time_pre_div", "enet1_time_cg", base + 0xa780, 16, 3); base 667 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET2_REF_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet2_ref_pre_div", "enet2_ref_cg", base + 0xa800, 16, 3); base 668 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET2_TIME_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet2_time_pre_div", "enet2_time_cg", base + 0xa880, 16, 3); base 669 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = imx_clk_hw_divider2("enet_phy_ref_pre_div", "enet_phy_ref_cg", base + 0xa900, 16, 3); base 670 drivers/clk/imx/clk-imx7d.c hws[IMX7D_EIM_ROOT_PRE_DIV] = imx_clk_hw_divider2("eim_pre_div", "eim_cg", base + 0xa980, 16, 3); base 671 drivers/clk/imx/clk-imx7d.c hws[IMX7D_NAND_ROOT_PRE_DIV] = imx_clk_hw_divider2("nand_pre_div", "nand_cg", base + 0xaa00, 16, 3); base 672 drivers/clk/imx/clk-imx7d.c hws[IMX7D_QSPI_ROOT_PRE_DIV] = imx_clk_hw_divider2("qspi_pre_div", "qspi_cg", base + 0xaa80, 16, 3); base 673 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC1_ROOT_PRE_DIV] = imx_clk_hw_divider2("usdhc1_pre_div", "usdhc1_cg", base + 0xab00, 16, 3); base 674 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC2_ROOT_PRE_DIV] = imx_clk_hw_divider2("usdhc2_pre_div", "usdhc2_cg", base + 0xab80, 16, 3); base 675 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC3_ROOT_PRE_DIV] = imx_clk_hw_divider2("usdhc3_pre_div", "usdhc3_cg", base + 0xac00, 16, 3); base 676 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CAN1_ROOT_PRE_DIV] = imx_clk_hw_divider2("can1_pre_div", "can1_cg", base + 0xac80, 16, 3); base 677 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CAN2_ROOT_PRE_DIV] = imx_clk_hw_divider2("can2_pre_div", "can2_cg", base + 0xad00, 16, 3); base 678 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C1_ROOT_PRE_DIV] = imx_clk_hw_divider2("i2c1_pre_div", "i2c1_cg", base + 0xad80, 16, 3); base 679 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C2_ROOT_PRE_DIV] = imx_clk_hw_divider2("i2c2_pre_div", "i2c2_cg", base + 0xae00, 16, 3); base 680 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C3_ROOT_PRE_DIV] = imx_clk_hw_divider2("i2c3_pre_div", "i2c3_cg", base + 0xae80, 16, 3); base 681 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C4_ROOT_PRE_DIV] = imx_clk_hw_divider2("i2c4_pre_div", "i2c4_cg", base + 0xaf00, 16, 3); base 682 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART1_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart1_pre_div", "uart1_cg", base + 0xaf80, 16, 3); base 683 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART2_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart2_pre_div", "uart2_cg", base + 0xb000, 16, 3); base 684 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART3_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart3_pre_div", "uart3_cg", base + 0xb080, 16, 3); base 685 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART4_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart4_pre_div", "uart4_cg", base + 0xb100, 16, 3); base 686 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART5_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart5_pre_div", "uart5_cg", base + 0xb180, 16, 3); base 687 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART6_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart6_pre_div", "uart6_cg", base + 0xb200, 16, 3); base 688 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART7_ROOT_PRE_DIV] = imx_clk_hw_divider2("uart7_pre_div", "uart7_cg", base + 0xb280, 16, 3); base 689 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI1_ROOT_PRE_DIV] = imx_clk_hw_divider2("ecspi1_pre_div", "ecspi1_cg", base + 0xb300, 16, 3); base 690 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI2_ROOT_PRE_DIV] = imx_clk_hw_divider2("ecspi2_pre_div", "ecspi2_cg", base + 0xb380, 16, 3); base 691 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI3_ROOT_PRE_DIV] = imx_clk_hw_divider2("ecspi3_pre_div", "ecspi3_cg", base + 0xb400, 16, 3); base 692 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI4_ROOT_PRE_DIV] = imx_clk_hw_divider2("ecspi4_pre_div", "ecspi4_cg", base + 0xb480, 16, 3); base 693 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM1_ROOT_PRE_DIV] = imx_clk_hw_divider2("pwm1_pre_div", "pwm1_cg", base + 0xb500, 16, 3); base 694 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM2_ROOT_PRE_DIV] = imx_clk_hw_divider2("pwm2_pre_div", "pwm2_cg", base + 0xb580, 16, 3); base 695 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM3_ROOT_PRE_DIV] = imx_clk_hw_divider2("pwm3_pre_div", "pwm3_cg", base + 0xb600, 16, 3); base 696 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM4_ROOT_PRE_DIV] = imx_clk_hw_divider2("pwm4_pre_div", "pwm4_cg", base + 0xb680, 16, 3); base 697 drivers/clk/imx/clk-imx7d.c hws[IMX7D_FLEXTIMER1_ROOT_PRE_DIV] = imx_clk_hw_divider2("flextimer1_pre_div", "flextimer1_cg", base + 0xb700, 16, 3); base 698 drivers/clk/imx/clk-imx7d.c hws[IMX7D_FLEXTIMER2_ROOT_PRE_DIV] = imx_clk_hw_divider2("flextimer2_pre_div", "flextimer2_cg", base + 0xb780, 16, 3); base 699 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SIM1_ROOT_PRE_DIV] = imx_clk_hw_divider2("sim1_pre_div", "sim1_cg", base + 0xb800, 16, 3); base 700 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SIM2_ROOT_PRE_DIV] = imx_clk_hw_divider2("sim2_pre_div", "sim2_cg", base + 0xb880, 16, 3); base 701 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT1_ROOT_PRE_DIV] = imx_clk_hw_divider2("gpt1_pre_div", "gpt1_cg", base + 0xb900, 16, 3); base 702 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT2_ROOT_PRE_DIV] = imx_clk_hw_divider2("gpt2_pre_div", "gpt2_cg", base + 0xb980, 16, 3); base 703 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT3_ROOT_PRE_DIV] = imx_clk_hw_divider2("gpt3_pre_div", "gpt3_cg", base + 0xba00, 16, 3); base 704 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT4_ROOT_PRE_DIV] = imx_clk_hw_divider2("gpt4_pre_div", "gpt4_cg", base + 0xba80, 16, 3); base 705 drivers/clk/imx/clk-imx7d.c hws[IMX7D_TRACE_ROOT_PRE_DIV] = imx_clk_hw_divider2("trace_pre_div", "trace_cg", base + 0xbb00, 16, 3); base 706 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WDOG_ROOT_PRE_DIV] = imx_clk_hw_divider2("wdog_pre_div", "wdog_cg", base + 0xbb80, 16, 3); base 707 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CSI_MCLK_ROOT_PRE_DIV] = imx_clk_hw_divider2("csi_mclk_pre_div", "csi_mclk_cg", base + 0xbc00, 16, 3); base 708 drivers/clk/imx/clk-imx7d.c hws[IMX7D_AUDIO_MCLK_ROOT_PRE_DIV] = imx_clk_hw_divider2("audio_mclk_pre_div", "audio_mclk_cg", base + 0xbc80, 16, 3); base 709 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WRCLK_ROOT_PRE_DIV] = imx_clk_hw_divider2("wrclk_pre_div", "wrclk_cg", base + 0xbd00, 16, 3); base 710 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CLKO1_ROOT_PRE_DIV] = imx_clk_hw_divider2("clko1_pre_div", "clko1_cg", base + 0xbd80, 16, 3); base 711 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CLKO2_ROOT_PRE_DIV] = imx_clk_hw_divider2("clko2_pre_div", "clko2_cg", base + 0xbe00, 16, 3); base 713 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_hw_divider2("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3); base 714 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_hw_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); base 715 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_hw_divider2("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6); base 716 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_hw_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6); base 717 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_hw_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6); base 718 drivers/clk/imx/clk-imx7d.c hws[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_hw_divider2("nand_usdhc_root_clk", "nand_usdhc_pre_div", base + 0x8980, 0, 6); base 719 drivers/clk/imx/clk-imx7d.c hws[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_hw_divider2("ahb_root_clk", "ahb_pre_div", base + 0x9000, 0, 6); base 720 drivers/clk/imx/clk-imx7d.c hws[IMX7D_IPG_ROOT_CLK] = imx_clk_hw_divider_flags("ipg_root_clk", "ahb_root_clk", base + 0x9080, 0, 2, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT); base 721 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_ROOT_DIV] = imx_clk_hw_divider2("dram_post_div", "dram_cg", base + 0x9880, 0, 3); base 722 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_hw_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3); base 723 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_hw_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3); base 724 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USB_HSIC_ROOT_DIV] = imx_clk_hw_divider2("usb_hsic_post_div", "usb_hsic_pre_div", base + 0xa100, 0, 6); base 725 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PCIE_CTRL_ROOT_DIV] = imx_clk_hw_divider2("pcie_ctrl_post_div", "pcie_ctrl_pre_div", base + 0xa180, 0, 6); base 726 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PCIE_PHY_ROOT_DIV] = imx_clk_hw_divider2("pcie_phy_post_div", "pcie_phy_pre_div", base + 0xa200, 0, 6); base 727 drivers/clk/imx/clk-imx7d.c hws[IMX7D_EPDC_PIXEL_ROOT_DIV] = imx_clk_hw_divider2("epdc_pixel_post_div", "epdc_pixel_pre_div", base + 0xa280, 0, 6); base 728 drivers/clk/imx/clk-imx7d.c hws[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_hw_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6); base 729 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_hw_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6); base 730 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_hw_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6); base 731 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_hw_divider2("mipi_dphy_post_div", "mipi_dphy_pre_div", base + 0xa480, 0, 6); base 732 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI1_ROOT_DIV] = imx_clk_hw_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6); base 733 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI2_ROOT_DIV] = imx_clk_hw_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6); base 734 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI3_ROOT_DIV] = imx_clk_hw_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6); base 735 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SPDIF_ROOT_DIV] = imx_clk_hw_divider2("spdif_post_div", "spdif_pre_div", base + 0xa680, 0, 6); base 736 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET1_REF_ROOT_DIV] = imx_clk_hw_divider2("enet1_ref_post_div", "enet1_ref_pre_div", base + 0xa700, 0, 6); base 737 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_hw_divider2("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6); base 738 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_hw_divider2("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6); base 739 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_hw_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6); base 740 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_hw_divider2("enet_phy_ref_root_clk", "enet_phy_ref_pre_div", base + 0xa900, 0, 6); base 741 drivers/clk/imx/clk-imx7d.c hws[IMX7D_EIM_ROOT_DIV] = imx_clk_hw_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6); base 742 drivers/clk/imx/clk-imx7d.c hws[IMX7D_NAND_ROOT_CLK] = imx_clk_hw_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6); base 743 drivers/clk/imx/clk-imx7d.c hws[IMX7D_QSPI_ROOT_DIV] = imx_clk_hw_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6); base 744 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC1_ROOT_DIV] = imx_clk_hw_divider2("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6); base 745 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC2_ROOT_DIV] = imx_clk_hw_divider2("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6); base 746 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC3_ROOT_DIV] = imx_clk_hw_divider2("usdhc3_post_div", "usdhc3_pre_div", base + 0xac00, 0, 6); base 747 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CAN1_ROOT_DIV] = imx_clk_hw_divider2("can1_post_div", "can1_pre_div", base + 0xac80, 0, 6); base 748 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CAN2_ROOT_DIV] = imx_clk_hw_divider2("can2_post_div", "can2_pre_div", base + 0xad00, 0, 6); base 749 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C1_ROOT_DIV] = imx_clk_hw_divider2("i2c1_post_div", "i2c1_pre_div", base + 0xad80, 0, 6); base 750 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C2_ROOT_DIV] = imx_clk_hw_divider2("i2c2_post_div", "i2c2_pre_div", base + 0xae00, 0, 6); base 751 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C3_ROOT_DIV] = imx_clk_hw_divider2("i2c3_post_div", "i2c3_pre_div", base + 0xae80, 0, 6); base 752 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C4_ROOT_DIV] = imx_clk_hw_divider2("i2c4_post_div", "i2c4_pre_div", base + 0xaf00, 0, 6); base 753 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART1_ROOT_DIV] = imx_clk_hw_divider2("uart1_post_div", "uart1_pre_div", base + 0xaf80, 0, 6); base 754 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART2_ROOT_DIV] = imx_clk_hw_divider2("uart2_post_div", "uart2_pre_div", base + 0xb000, 0, 6); base 755 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART3_ROOT_DIV] = imx_clk_hw_divider2("uart3_post_div", "uart3_pre_div", base + 0xb080, 0, 6); base 756 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART4_ROOT_DIV] = imx_clk_hw_divider2("uart4_post_div", "uart4_pre_div", base + 0xb100, 0, 6); base 757 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART5_ROOT_DIV] = imx_clk_hw_divider2("uart5_post_div", "uart5_pre_div", base + 0xb180, 0, 6); base 758 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART6_ROOT_DIV] = imx_clk_hw_divider2("uart6_post_div", "uart6_pre_div", base + 0xb200, 0, 6); base 759 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART7_ROOT_DIV] = imx_clk_hw_divider2("uart7_post_div", "uart7_pre_div", base + 0xb280, 0, 6); base 760 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI1_ROOT_DIV] = imx_clk_hw_divider2("ecspi1_post_div", "ecspi1_pre_div", base + 0xb300, 0, 6); base 761 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI2_ROOT_DIV] = imx_clk_hw_divider2("ecspi2_post_div", "ecspi2_pre_div", base + 0xb380, 0, 6); base 762 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI3_ROOT_DIV] = imx_clk_hw_divider2("ecspi3_post_div", "ecspi3_pre_div", base + 0xb400, 0, 6); base 763 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI4_ROOT_DIV] = imx_clk_hw_divider2("ecspi4_post_div", "ecspi4_pre_div", base + 0xb480, 0, 6); base 764 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM1_ROOT_DIV] = imx_clk_hw_divider2("pwm1_post_div", "pwm1_pre_div", base + 0xb500, 0, 6); base 765 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM2_ROOT_DIV] = imx_clk_hw_divider2("pwm2_post_div", "pwm2_pre_div", base + 0xb580, 0, 6); base 766 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM3_ROOT_DIV] = imx_clk_hw_divider2("pwm3_post_div", "pwm3_pre_div", base + 0xb600, 0, 6); base 767 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM4_ROOT_DIV] = imx_clk_hw_divider2("pwm4_post_div", "pwm4_pre_div", base + 0xb680, 0, 6); base 768 drivers/clk/imx/clk-imx7d.c hws[IMX7D_FLEXTIMER1_ROOT_DIV] = imx_clk_hw_divider2("flextimer1_post_div", "flextimer1_pre_div", base + 0xb700, 0, 6); base 769 drivers/clk/imx/clk-imx7d.c hws[IMX7D_FLEXTIMER2_ROOT_DIV] = imx_clk_hw_divider2("flextimer2_post_div", "flextimer2_pre_div", base + 0xb780, 0, 6); base 770 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SIM1_ROOT_DIV] = imx_clk_hw_divider2("sim1_post_div", "sim1_pre_div", base + 0xb800, 0, 6); base 771 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SIM2_ROOT_DIV] = imx_clk_hw_divider2("sim2_post_div", "sim2_pre_div", base + 0xb880, 0, 6); base 772 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT1_ROOT_DIV] = imx_clk_hw_divider2("gpt1_post_div", "gpt1_pre_div", base + 0xb900, 0, 6); base 773 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT2_ROOT_DIV] = imx_clk_hw_divider2("gpt2_post_div", "gpt2_pre_div", base + 0xb980, 0, 6); base 774 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT3_ROOT_DIV] = imx_clk_hw_divider2("gpt3_post_div", "gpt3_pre_div", base + 0xba00, 0, 6); base 775 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT4_ROOT_DIV] = imx_clk_hw_divider2("gpt4_post_div", "gpt4_pre_div", base + 0xba80, 0, 6); base 776 drivers/clk/imx/clk-imx7d.c hws[IMX7D_TRACE_ROOT_DIV] = imx_clk_hw_divider2("trace_post_div", "trace_pre_div", base + 0xbb00, 0, 6); base 777 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WDOG_ROOT_DIV] = imx_clk_hw_divider2("wdog_post_div", "wdog_pre_div", base + 0xbb80, 0, 6); base 778 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CSI_MCLK_ROOT_DIV] = imx_clk_hw_divider2("csi_mclk_post_div", "csi_mclk_pre_div", base + 0xbc00, 0, 6); base 779 drivers/clk/imx/clk-imx7d.c hws[IMX7D_AUDIO_MCLK_ROOT_DIV] = imx_clk_hw_divider2("audio_mclk_post_div", "audio_mclk_pre_div", base + 0xbc80, 0, 6); base 780 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WRCLK_ROOT_DIV] = imx_clk_hw_divider2("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, 6); base 781 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CLKO1_ROOT_DIV] = imx_clk_hw_divider2("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, 6); base 782 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CLKO2_ROOT_DIV] = imx_clk_hw_divider2("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, 6); base 784 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_hw_gate2_flags("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0, CLK_OPS_PARENT_ENABLE); base 785 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_hw_gate4("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0); base 786 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_hw_gate2_flags("main_axi_root_clk", "axi_post_div", base + 0x4040, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); base 787 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_hw_gate4("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0); base 788 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_hw_gate4("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0); base 789 drivers/clk/imx/clk-imx7d.c hws[IMX7D_OCRAM_CLK] = imx_clk_hw_gate4("ocram_clk", "main_axi_root_clk", base + 0x4110, 0); base 790 drivers/clk/imx/clk-imx7d.c hws[IMX7D_OCRAM_S_CLK] = imx_clk_hw_gate4("ocram_s_clk", "ahb_root_clk", base + 0x4120, 0); base 791 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_root_clk", "dram_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); base 792 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); base 793 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); base 794 drivers/clk/imx/clk-imx7d.c hws[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); base 795 drivers/clk/imx/clk-imx7d.c hws[IMX7D_OCOTP_CLK] = imx_clk_hw_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0); base 796 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SNVS_CLK] = imx_clk_hw_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0); base 797 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MU_ROOT_CLK] = imx_clk_hw_gate4("mu_root_clk", "ipg_root_clk", base + 0x4270, 0); base 798 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CAAM_CLK] = imx_clk_hw_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0); base 799 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_hw_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0); base 800 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SDMA_CORE_CLK] = imx_clk_hw_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0); base 801 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_hw_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0); base 802 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_hw_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0); base 803 drivers/clk/imx/clk-imx7d.c hws[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_hw_gate4("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0); base 804 drivers/clk/imx/clk-imx7d.c hws[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_hw_gate4("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0); base 805 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_hw_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0); base 806 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_hw_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0); base 807 drivers/clk/imx/clk-imx7d.c hws[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_hw_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0); base 808 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET1_IPG_ROOT_CLK] = imx_clk_hw_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base + 0x4700, 0, &share_count_enet1); base 809 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_hw_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div", base + 0x4700, 0, &share_count_enet1); base 810 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET2_IPG_ROOT_CLK] = imx_clk_hw_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base + 0x4710, 0, &share_count_enet2); base 811 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_hw_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4710, 0, &share_count_enet2); base 812 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI1_ROOT_CLK] = imx_clk_hw_gate2_shared2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0, &share_count_sai1); base 813 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI1_IPG_CLK] = imx_clk_hw_gate2_shared2("sai1_ipg_clk", "ipg_root_clk", base + 0x48c0, 0, &share_count_sai1); base 814 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI2_ROOT_CLK] = imx_clk_hw_gate2_shared2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0, &share_count_sai2); base 815 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI2_IPG_CLK] = imx_clk_hw_gate2_shared2("sai2_ipg_clk", "ipg_root_clk", base + 0x48d0, 0, &share_count_sai2); base 816 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI3_ROOT_CLK] = imx_clk_hw_gate2_shared2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0, &share_count_sai3); base 817 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SAI3_IPG_CLK] = imx_clk_hw_gate2_shared2("sai3_ipg_clk", "ipg_root_clk", base + 0x48e0, 0, &share_count_sai3); base 818 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SPDIF_ROOT_CLK] = imx_clk_hw_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0); base 819 drivers/clk/imx/clk-imx7d.c hws[IMX7D_EIM_ROOT_CLK] = imx_clk_hw_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0); base 820 drivers/clk/imx/clk-imx7d.c hws[IMX7D_NAND_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand); base 821 drivers/clk/imx/clk-imx7d.c hws[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand); base 822 drivers/clk/imx/clk-imx7d.c hws[IMX7D_QSPI_ROOT_CLK] = imx_clk_hw_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0); base 823 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC1_ROOT_CLK] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0); base 824 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC2_ROOT_CLK] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0); base 825 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USDHC3_ROOT_CLK] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3_post_div", base + 0x46e0, 0); base 826 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CAN1_ROOT_CLK] = imx_clk_hw_gate4("can1_root_clk", "can1_post_div", base + 0x4740, 0); base 827 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CAN2_ROOT_CLK] = imx_clk_hw_gate4("can2_root_clk", "can2_post_div", base + 0x4750, 0); base 828 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C1_ROOT_CLK] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1_post_div", base + 0x4880, 0); base 829 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C2_ROOT_CLK] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2_post_div", base + 0x4890, 0); base 830 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C3_ROOT_CLK] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3_post_div", base + 0x48a0, 0); base 831 drivers/clk/imx/clk-imx7d.c hws[IMX7D_I2C4_ROOT_CLK] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4_post_div", base + 0x48b0, 0); base 832 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART1_ROOT_CLK] = imx_clk_hw_gate4("uart1_root_clk", "uart1_post_div", base + 0x4940, 0); base 833 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART2_ROOT_CLK] = imx_clk_hw_gate4("uart2_root_clk", "uart2_post_div", base + 0x4950, 0); base 834 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART3_ROOT_CLK] = imx_clk_hw_gate4("uart3_root_clk", "uart3_post_div", base + 0x4960, 0); base 835 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART4_ROOT_CLK] = imx_clk_hw_gate4("uart4_root_clk", "uart4_post_div", base + 0x4970, 0); base 836 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART5_ROOT_CLK] = imx_clk_hw_gate4("uart5_root_clk", "uart5_post_div", base + 0x4980, 0); base 837 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART6_ROOT_CLK] = imx_clk_hw_gate4("uart6_root_clk", "uart6_post_div", base + 0x4990, 0); base 838 drivers/clk/imx/clk-imx7d.c hws[IMX7D_UART7_ROOT_CLK] = imx_clk_hw_gate4("uart7_root_clk", "uart7_post_div", base + 0x49a0, 0); base 839 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI1_ROOT_CLK] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1_post_div", base + 0x4780, 0); base 840 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI2_ROOT_CLK] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2_post_div", base + 0x4790, 0); base 841 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI3_ROOT_CLK] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3_post_div", base + 0x47a0, 0); base 842 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ECSPI4_ROOT_CLK] = imx_clk_hw_gate4("ecspi4_root_clk", "ecspi4_post_div", base + 0x47b0, 0); base 843 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM1_ROOT_CLK] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1_post_div", base + 0x4840, 0); base 844 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM2_ROOT_CLK] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2_post_div", base + 0x4850, 0); base 845 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM3_ROOT_CLK] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3_post_div", base + 0x4860, 0); base 846 drivers/clk/imx/clk-imx7d.c hws[IMX7D_PWM4_ROOT_CLK] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4_post_div", base + 0x4870, 0); base 847 drivers/clk/imx/clk-imx7d.c hws[IMX7D_FLEXTIMER1_ROOT_CLK] = imx_clk_hw_gate4("flextimer1_root_clk", "flextimer1_post_div", base + 0x4800, 0); base 848 drivers/clk/imx/clk-imx7d.c hws[IMX7D_FLEXTIMER2_ROOT_CLK] = imx_clk_hw_gate4("flextimer2_root_clk", "flextimer2_post_div", base + 0x4810, 0); base 849 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SIM1_ROOT_CLK] = imx_clk_hw_gate4("sim1_root_clk", "sim1_post_div", base + 0x4900, 0); base 850 drivers/clk/imx/clk-imx7d.c hws[IMX7D_SIM2_ROOT_CLK] = imx_clk_hw_gate4("sim2_root_clk", "sim2_post_div", base + 0x4910, 0); base 851 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT1_ROOT_CLK] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1_post_div", base + 0x47c0, 0); base 852 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT2_ROOT_CLK] = imx_clk_hw_gate4("gpt2_root_clk", "gpt2_post_div", base + 0x47d0, 0); base 853 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT3_ROOT_CLK] = imx_clk_hw_gate4("gpt3_root_clk", "gpt3_post_div", base + 0x47e0, 0); base 854 drivers/clk/imx/clk-imx7d.c hws[IMX7D_GPT4_ROOT_CLK] = imx_clk_hw_gate4("gpt4_root_clk", "gpt4_post_div", base + 0x47f0, 0); base 855 drivers/clk/imx/clk-imx7d.c hws[IMX7D_TRACE_ROOT_CLK] = imx_clk_hw_gate4("trace_root_clk", "trace_post_div", base + 0x4300, 0); base 856 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WDOG1_ROOT_CLK] = imx_clk_hw_gate4("wdog1_root_clk", "wdog_post_div", base + 0x49c0, 0); base 857 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WDOG2_ROOT_CLK] = imx_clk_hw_gate4("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0); base 858 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WDOG3_ROOT_CLK] = imx_clk_hw_gate4("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0); base 859 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WDOG4_ROOT_CLK] = imx_clk_hw_gate4("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0); base 860 drivers/clk/imx/clk-imx7d.c hws[IMX7D_KPP_ROOT_CLK] = imx_clk_hw_gate4("kpp_root_clk", "ipg_root_clk", base + 0x4aa0, 0); base 861 drivers/clk/imx/clk-imx7d.c hws[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_hw_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0); base 862 drivers/clk/imx/clk-imx7d.c hws[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_hw_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0); base 863 drivers/clk/imx/clk-imx7d.c hws[IMX7D_WRCLK_ROOT_CLK] = imx_clk_hw_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0); base 864 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USB_CTRL_CLK] = imx_clk_hw_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0); base 865 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USB_PHY1_CLK] = imx_clk_hw_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0); base 866 drivers/clk/imx/clk-imx7d.c hws[IMX7D_USB_PHY2_CLK] = imx_clk_hw_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0); base 867 drivers/clk/imx/clk-imx7d.c hws[IMX7D_ADC_ROOT_CLK] = imx_clk_hw_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); base 63 drivers/clk/imx/clk-imx7ulp.c void __iomem *base; base 83 drivers/clk/imx/clk-imx7ulp.c base = of_iomap(np, 0); base 84 drivers/clk/imx/clk-imx7ulp.c WARN_ON(!base); base 87 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); base 88 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); base 91 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x508, 8, 3, CLK_SET_RATE_GATE); base 92 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE); base 95 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_APLL] = imx_clk_pllv4("apll", "apll_pre_div", base + 0x500); base 96 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SPLL] = imx_clk_pllv4("spll", "spll_pre_div", base + 0x600); base 99 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_APLL_PFD0] = imx_clk_pfdv2("apll_pfd0", "apll", base + 0x50c, 0); base 100 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_APLL_PFD1] = imx_clk_pfdv2("apll_pfd1", "apll", base + 0x50c, 1); base 101 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_APLL_PFD2] = imx_clk_pfdv2("apll_pfd2", "apll", base + 0x50c, 2); base 102 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_APLL_PFD3] = imx_clk_pfdv2("apll_pfd3", "apll", base + 0x50c, 3); base 105 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_pfdv2("spll_pfd0", "spll", base + 0x60C, 0); base 106 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_pfdv2("spll_pfd1", "spll", base + 0x60C, 1); base 107 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_pfdv2("spll_pfd2", "spll", base + 0x60C, 2); base 108 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_pfdv2("spll_pfd3", "spll", base + 0x60C, 3); base 111 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_APLL_PFD_SEL] = imx_clk_hw_mux_flags("apll_pfd_sel", base + 0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); base 112 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SPLL_PFD_SEL] = imx_clk_hw_mux_flags("spll_pfd_sel", base + 0x608, 14, 2, spll_pfd_sels, ARRAY_SIZE(spll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); base 113 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_APLL_SEL] = imx_clk_hw_mux_flags("apll_sel", base + 0x508, 1, 1, apll_sels, ARRAY_SIZE(apll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); base 114 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SPLL_SEL] = imx_clk_hw_mux_flags("spll_sel", base + 0x608, 1, 1, spll_sels, ARRAY_SIZE(spll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); base 116 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SPLL_BUS_CLK] = imx_clk_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, ulp_div_table, &imx_ccm_lock); base 119 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels)); base 120 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_hw_mux2("hsrun_scs_sel", base + 0x1c, 24, 4, scs_sels, ARRAY_SIZE(scs_sels)); base 121 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_NIC_SEL] = imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels)); base 122 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); base 124 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT); base 125 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT); base 127 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_DDR_DIV] = imx_clk_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3, base 130 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_NIC0_DIV] = imx_clk_hw_divider_flags("nic0_clk", "nic_sel", base + 0x40, 24, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); base 131 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_NIC1_DIV] = imx_clk_hw_divider_flags("nic1_clk", "nic0_clk", base + 0x40, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); base 132 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_NIC1_BUS_DIV] = imx_clk_hw_divider_flags("nic1_bus_clk", "nic0_clk", base + 0x40, 4, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); base 134 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_GPU_DIV] = imx_clk_hw_divider("gpu_clk", "nic0_clk", base + 0x40, 20, 4); base 136 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_SOSC_BUS_CLK] = imx_clk_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3, base 138 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_FIRC_BUS_CLK] = imx_clk_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8, 3, base 151 drivers/clk/imx/clk-imx7ulp.c void __iomem *base; base 163 drivers/clk/imx/clk-imx7ulp.c base = of_iomap(np, 0); base 164 drivers/clk/imx/clk-imx7ulp.c WARN_ON(!base); base 166 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_DMA1] = imx_clk_hw_gate("dma1", "nic1_clk", base + 0x20, 30); base 167 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_RGPIO2P1] = imx_clk_hw_gate("rgpio2p1", "nic1_bus_clk", base + 0x3c, 30); base 168 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_DMA_MUX1] = imx_clk_hw_gate("dma_mux1", "nic1_bus_clk", base + 0x84, 30); base 169 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_CAAM] = imx_clk_hw_gate("caam", "nic1_clk", base + 0x90, 30); base 170 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPTPM4] = imx7ulp_clk_composite("lptpm4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94); base 171 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPTPM5] = imx7ulp_clk_composite("lptpm5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98); base 172 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPIT1] = imx7ulp_clk_composite("lpit1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c); base 173 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPSPI2] = imx7ulp_clk_composite("lpspi2", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa4); base 174 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPSPI3] = imx7ulp_clk_composite("lpspi3", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa8); base 175 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPI2C4] = imx7ulp_clk_composite("lpi2c4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xac); base 176 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPI2C5] = imx7ulp_clk_composite("lpi2c5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb0); base 177 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPUART4] = imx7ulp_clk_composite("lpuart4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb4); base 178 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPUART5] = imx7ulp_clk_composite("lpuart5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb8); base 179 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_FLEXIO1] = imx7ulp_clk_composite("flexio1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xc4); base 180 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_USB0] = imx7ulp_clk_composite("usb0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xcc); base 181 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_USB1] = imx7ulp_clk_composite("usb1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xd0); base 182 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_USB_PHY] = imx_clk_hw_gate("usb_phy", "nic1_bus_clk", base + 0xd4, 30); base 183 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_USDHC0] = imx7ulp_clk_composite("usdhc0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xdc); base 184 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_USDHC1] = imx7ulp_clk_composite("usdhc1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xe0); base 185 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_WDG1] = imx7ulp_clk_composite("wdg1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0xf4); base 186 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_WDG2] = imx7ulp_clk_composite("sdg2", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0x10c); base 206 drivers/clk/imx/clk-imx7ulp.c void __iomem *base; base 218 drivers/clk/imx/clk-imx7ulp.c base = of_iomap(np, 0); base 219 drivers/clk/imx/clk-imx7ulp.c WARN_ON(!base); base 221 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPTPM6] = imx7ulp_clk_composite("lptpm6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x84); base 222 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPTPM7] = imx7ulp_clk_composite("lptpm7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x88); base 225 drivers/clk/imx/clk-imx7ulp.c base + 0xac, 30, 0, &imx_ccm_lock); base 226 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPI2C6] = imx7ulp_clk_composite("lpi2c6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x90); base 227 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPI2C7] = imx7ulp_clk_composite("lpi2c7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94); base 228 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPUART6] = imx7ulp_clk_composite("lpuart6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98); base 229 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LPUART7] = imx7ulp_clk_composite("lpuart7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c); base 230 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_DSI] = imx7ulp_clk_composite("dsi", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0xa4); base 231 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_LCDIF] = imx7ulp_clk_composite("lcdif", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xa8); base 233 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_VIU] = imx_clk_hw_gate("viu", "nic1_clk", base + 0xa0, 30); base 234 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_PCTLC] = imx_clk_hw_gate("pctlc", "nic1_bus_clk", base + 0xb8, 30); base 235 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_PCTLD] = imx_clk_hw_gate("pctld", "nic1_bus_clk", base + 0xbc, 30); base 236 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_PCTLE] = imx_clk_hw_gate("pctle", "nic1_bus_clk", base + 0xc0, 30); base 237 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_PCTLF] = imx_clk_hw_gate("pctlf", "nic1_bus_clk", base + 0xc4, 30); base 239 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_GPU3D] = imx7ulp_clk_composite("gpu3d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140); base 240 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_GPU2D] = imx7ulp_clk_composite("gpu2d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144); base 260 drivers/clk/imx/clk-imx7ulp.c void __iomem *base; base 271 drivers/clk/imx/clk-imx7ulp.c base = of_iomap(np, 0); base 272 drivers/clk/imx/clk-imx7ulp.c WARN_ON(!base); base 274 drivers/clk/imx/clk-imx7ulp.c clks[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_IS_CRITICAL); base 372 drivers/clk/imx/clk-imx8mm.c void __iomem *base; base 384 drivers/clk/imx/clk-imx8mm.c base = of_iomap(np, 0); base 385 drivers/clk/imx/clk-imx8mm.c if (WARN_ON(!base)) base 388 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 389 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 390 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 391 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 392 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 393 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 394 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 395 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 396 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 397 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 399 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mm_audio_pll); base 400 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mm_audio_pll); base 401 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mm_video_pll); base 402 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mm_dram_pll); base 403 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mm_gpu_pll); base 404 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mm_vpu_pll); base 405 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mm_arm_pll); base 406 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mm_sys_pll); base 407 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mm_sys_pll); base 408 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mm_sys_pll); base 411 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); base 412 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); base 413 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); base 414 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); base 415 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); base 416 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); base 417 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); base 418 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT); base 419 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT); base 420 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); base 423 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); base 424 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); base 425 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13); base 426 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); base 427 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); base 428 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11); base 429 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); base 430 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11); base 431 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11); base 432 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); base 456 drivers/clk/imx/clk-imx8mm.c base = devm_platform_ioremap_resource(pdev, 0); base 457 drivers/clk/imx/clk-imx8mm.c if (WARN_ON(IS_ERR(base))) base 458 drivers/clk/imx/clk-imx8mm.c return PTR_ERR(base); base 461 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)); base 462 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_M4_SRC] = imx_clk_mux2("arm_m4_src", base + 0x8080, 24, 3, imx8mm_m4_sels, ARRAY_SIZE(imx8mm_m4_sels)); base 463 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_VPU_SRC] = imx_clk_mux2("vpu_src", base + 0x8100, 24, 3, imx8mm_vpu_sels, ARRAY_SIZE(imx8mm_vpu_sels)); base 464 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPU3D_SRC] = imx_clk_mux2("gpu3d_src", base + 0x8180, 24, 3, imx8mm_gpu3d_sels, ARRAY_SIZE(imx8mm_gpu3d_sels)); base 465 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPU2D_SRC] = imx_clk_mux2("gpu2d_src", base + 0x8200, 24, 3, imx8mm_gpu2d_sels, ARRAY_SIZE(imx8mm_gpu2d_sels)); base 466 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28); base 467 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_M4_CG] = imx_clk_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); base 468 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_VPU_CG] = imx_clk_gate3("vpu_cg", "vpu_src", base + 0x8100, 28); base 469 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPU3D_CG] = imx_clk_gate3("gpu3d_cg", "gpu3d_src", base + 0x8180, 28); base 470 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPU2D_CG] = imx_clk_gate3("gpu2d_cg", "gpu2d_src", base + 0x8200, 28); base 471 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3); base 472 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_M4_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); base 473 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_VPU_DIV] = imx_clk_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3); base 474 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPU3D_DIV] = imx_clk_divider2("gpu3d_div", "gpu3d_cg", base + 0x8180, 0, 3); base 475 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPU2D_DIV] = imx_clk_divider2("gpu2d_div", "gpu2d_cg", base + 0x8200, 0, 3); base 478 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800); base 479 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels, base + 0x8880); base 480 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_composite_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900); base 481 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_VPU_BUS] = imx8m_clk_composite("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980); base 482 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00); base 483 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80); base 484 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DISP_RTRM] = imx8m_clk_composite("disp_rtrm", imx8mm_disp_rtrm_sels, base + 0x8b00); base 485 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_USB_BUS] = imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80); base 486 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mm_gpu_axi_sels, base + 0x8c00); base 487 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mm_gpu_ahb_sels, base + 0x8c80); base 488 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mm_noc_sels, base + 0x8d00); base 489 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_NOC_APB] = imx8m_clk_composite_critical("noc_apb", imx8mm_noc_apb_sels, base + 0x8d80); base 492 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels, base + 0x9000); base 493 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mm_audio_ahb_sels, base + 0x9100); base 496 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); base 497 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1); base 500 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mm_dram_alt_sels, base + 0xa000); base 501 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mm_dram_apb_sels, base + 0xa080); base 502 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_VPU_G1] = imx8m_clk_composite("vpu_g1", imx8mm_vpu_g1_sels, base + 0xa100); base 503 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_VPU_G2] = imx8m_clk_composite("vpu_g2", imx8mm_vpu_g2_sels, base + 0xa180); base 504 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DISP_DTRC] = imx8m_clk_composite("disp_dtrc", imx8mm_disp_dtrc_sels, base + 0xa200); base 505 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DISP_DC8000] = imx8m_clk_composite("disp_dc8000", imx8mm_disp_dc8000_sels, base + 0xa280); base 506 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PCIE1_CTRL] = imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels, base + 0xa300); base 507 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PCIE1_PHY] = imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels, base + 0xa380); base 508 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PCIE1_AUX] = imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels, base + 0xa400); base 509 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DC_PIXEL] = imx8m_clk_composite("dc_pixel", imx8mm_dc_pixel_sels, base + 0xa480); base 510 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_composite("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500); base 511 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI1] = imx8m_clk_composite("sai1", imx8mm_sai1_sels, base + 0xa580); base 512 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mm_sai2_sels, base + 0xa600); base 513 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mm_sai3_sels, base + 0xa680); base 514 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI4] = imx8m_clk_composite("sai4", imx8mm_sai4_sels, base + 0xa700); base 515 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mm_sai5_sels, base + 0xa780); base 516 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mm_sai6_sels, base + 0xa800); base 517 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SPDIF1] = imx8m_clk_composite("spdif1", imx8mm_spdif1_sels, base + 0xa880); base 518 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SPDIF2] = imx8m_clk_composite("spdif2", imx8mm_spdif2_sels, base + 0xa900); base 519 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels, base + 0xa980); base 520 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels, base + 0xaa00); base 521 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels, base + 0xaa80); base 522 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_NAND] = imx8m_clk_composite("nand", imx8mm_nand_sels, base + 0xab00); base 523 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80); base 524 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels, base + 0xac00); base 525 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels, base + 0xac80); base 526 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00); base 527 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80); base 528 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00); base 529 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80); base 530 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_UART1] = imx8m_clk_composite("uart1", imx8mm_uart1_sels, base + 0xaf00); base 531 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_UART2] = imx8m_clk_composite("uart2", imx8mm_uart2_sels, base + 0xaf80); base 532 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_UART3] = imx8m_clk_composite("uart3", imx8mm_uart3_sels, base + 0xb000); base 533 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_UART4] = imx8m_clk_composite("uart4", imx8mm_uart4_sels, base + 0xb080); base 534 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100); base 535 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180); base 536 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mm_gic_sels, base + 0xb200); base 537 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280); base 538 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300); base 539 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380); base 540 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400); base 541 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480); base 542 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500); base 543 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPT1] = imx8m_clk_composite("gpt1", imx8mm_gpt1_sels, base + 0xb580); base 544 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900); base 545 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mm_wrclk_sels, base + 0xb980); base 546 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_CLKO1] = imx8m_clk_composite("clko1", imx8mm_clko1_sels, base + 0xba00); base 547 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DSI_CORE] = imx8m_clk_composite("dsi_core", imx8mm_dsi_core_sels, base + 0xbb00); base 548 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DSI_PHY_REF] = imx8m_clk_composite("dsi_phy_ref", imx8mm_dsi_phy_sels, base + 0xbb80); base 549 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mm_dsi_dbi_sels, base + 0xbc00); base 550 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_USDHC3] = imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels, base + 0xbc80); base 551 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_CSI1_CORE] = imx8m_clk_composite("csi1_core", imx8mm_csi1_core_sels, base + 0xbd00); base 552 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mm_csi1_phy_sels, base + 0xbd80); base 553 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_CSI1_ESC] = imx8m_clk_composite("csi1_esc", imx8mm_csi1_esc_sels, base + 0xbe00); base 554 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_CSI2_CORE] = imx8m_clk_composite("csi2_core", imx8mm_csi2_core_sels, base + 0xbe80); base 555 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_CSI2_PHY_REF] = imx8m_clk_composite("csi2_phy_ref", imx8mm_csi2_phy_sels, base + 0xbf00); base 556 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_CSI2_ESC] = imx8m_clk_composite("csi2_esc", imx8mm_csi2_esc_sels, base + 0xbf80); base 557 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PCIE2_CTRL] = imx8m_clk_composite("pcie2_ctrl", imx8mm_pcie2_ctrl_sels, base + 0xc000); base 558 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PCIE2_PHY] = imx8m_clk_composite("pcie2_phy", imx8mm_pcie2_phy_sels, base + 0xc080); base 559 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PCIE2_AUX] = imx8m_clk_composite("pcie2_aux", imx8mm_pcie2_aux_sels, base + 0xc100); base 560 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180); base 561 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PDM] = imx8m_clk_composite("pdm", imx8mm_pdm_sels, base + 0xc200); base 562 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_VPU_H1] = imx8m_clk_composite("vpu_h1", imx8mm_vpu_h1_sels, base + 0xc280); base 565 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0); base 566 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0); base 567 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0); base 568 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0); base 569 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0); base 570 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0); base 571 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0); base 572 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0); base 573 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0); base 574 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0); base 575 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0); base 576 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0); base 577 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0); base 578 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0); base 579 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0); base 580 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0); base 581 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PCIE1_ROOT] = imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0); base 582 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0); base 583 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0); base 584 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0); base 585 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0); base 586 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0); base 587 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_NAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand); base 588 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand); base 589 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI1_ROOT] = imx_clk_gate2_shared2("sai1_root_clk", "sai1", base + 0x4330, 0, &share_count_sai1); base 590 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI1_IPG] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_audio_root", base + 0x4330, 0, &share_count_sai1); base 591 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2); base 592 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2); base 593 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3); base 594 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3); base 595 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI4_ROOT] = imx_clk_gate2_shared2("sai4_root_clk", "sai4", base + 0x4360, 0, &share_count_sai4); base 596 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI4_IPG] = imx_clk_gate2_shared2("sai4_ipg_clk", "ipg_audio_root", base + 0x4360, 0, &share_count_sai4); base 597 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5); base 598 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); base 599 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); base 600 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); base 601 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SNVS_ROOT] = imx_clk_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0); base 602 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); base 603 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); base 604 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); base 605 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0); base 606 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0); base 607 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_gate4("gpu3d_root_clk", "gpu3d_div", base + 0x44f0, 0); base 608 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0); base 609 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0); base 610 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0); base 611 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0); base 612 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0); base 613 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_VPU_G1_ROOT] = imx_clk_gate4("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0); base 614 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPU_BUS_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0); base 615 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_VPU_H1_ROOT] = imx_clk_gate4("vpu_h1_root_clk", "vpu_h1", base + 0x4590, 0); base 616 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0); base 617 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm); base 618 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm); base 619 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_disp); base 620 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp); base 621 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp); base 622 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_disp); base 623 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0); base 624 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0); base 625 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_VPU_DEC_ROOT] = imx_clk_gate4("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0); base 626 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0); base 627 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0); base 628 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_SDMA3_ROOT] = imx_clk_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0); base 629 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_GPU2D_ROOT] = imx_clk_gate4("gpu2d_root_clk", "gpu2d_div", base + 0x4660, 0); base 630 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0); base 635 drivers/clk/imx/clk-imx8mm.c clks[IMX8MM_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mm_dram_core_sels, ARRAY_SIZE(imx8mm_dram_core_sels), CLK_IS_CRITICAL); base 383 drivers/clk/imx/clk-imx8mn.c void __iomem *base; base 395 drivers/clk/imx/clk-imx8mn.c base = of_iomap(np, 0); base 396 drivers/clk/imx/clk-imx8mn.c if (WARN_ON(!base)) { base 401 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 402 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 403 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 404 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 405 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 406 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 407 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 408 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 409 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 410 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 412 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mn_audio_pll); base 413 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mn_audio_pll); base 414 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mn_video_pll); base 415 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mn_dram_pll); base 416 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mn_gpu_pll); base 417 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mn_vpu_pll); base 418 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mn_arm_pll); base 419 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mn_sys_pll); base 420 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mn_sys_pll); base 421 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mn_sys_pll); base 424 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); base 425 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); base 426 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); base 427 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); base 428 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); base 429 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); base 430 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); base 431 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT); base 432 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT); base 433 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); base 436 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); base 437 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); base 438 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13); base 439 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); base 440 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); base 441 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11); base 442 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); base 443 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11); base 444 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11); base 445 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); base 469 drivers/clk/imx/clk-imx8mn.c base = devm_platform_ioremap_resource(pdev, 0); base 470 drivers/clk/imx/clk-imx8mn.c if (WARN_ON(IS_ERR(base))) { base 471 drivers/clk/imx/clk-imx8mn.c ret = PTR_ERR(base); base 476 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)); base 477 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mn_gpu_core_sels, ARRAY_SIZE(imx8mn_gpu_core_sels)); base 478 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mn_gpu_shader_sels, ARRAY_SIZE(imx8mn_gpu_shader_sels)); base 479 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28); base 480 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28); base 481 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28); base 483 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3); base 484 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3); base 485 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3); base 488 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800); base 489 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880); base 490 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_composite("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900); base 491 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00); base 492 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80); base 493 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_USB_BUS] = imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80); base 494 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00); base 495 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80); base 496 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00); base 498 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000); base 499 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100); base 500 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); base 501 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1); base 502 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL); base 503 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000); base 504 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080); base 505 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500); base 506 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mn_sai2_sels, base + 0xa600); base 507 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mn_sai3_sels, base + 0xa680); base 508 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mn_sai5_sels, base + 0xa780); base 509 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mn_sai6_sels, base + 0xa800); base 510 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SPDIF1] = imx8m_clk_composite("spdif1", imx8mn_spdif1_sels, base + 0xa880); base 511 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980); base 512 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base + 0xaa00); base 513 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80); base 514 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_NAND] = imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00); base 515 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80); base 516 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels, base + 0xac00); base 517 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80); base 518 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00); base 519 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80); base 520 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00); base 521 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80); base 522 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_UART1] = imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00); base 523 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_UART2] = imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80); base 524 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_UART3] = imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000); base 525 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_UART4] = imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080); base 526 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100); base 527 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180); base 528 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mn_gic_sels, base + 0xb200); base 529 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280); base 530 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300); base 531 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380); base 532 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400); base 533 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480); base 534 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500); base 535 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900); base 536 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980); base 537 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_CLKO1] = imx8m_clk_composite("clko1", imx8mn_clko1_sels, base + 0xba00); base 538 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_CLKO2] = imx8m_clk_composite("clko2", imx8mn_clko2_sels, base + 0xba80); base 539 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DSI_CORE] = imx8m_clk_composite("dsi_core", imx8mn_dsi_core_sels, base + 0xbb00); base 540 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DSI_PHY_REF] = imx8m_clk_composite("dsi_phy_ref", imx8mn_dsi_phy_sels, base + 0xbb80); base 541 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mn_dsi_dbi_sels, base + 0xbc00); base 542 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_USDHC3] = imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels, base + 0xbc80); base 543 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_CAMERA_PIXEL] = imx8m_clk_composite("camera_pixel", imx8mn_camera_pixel_sels, base + 0xbd00); base 544 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mn_csi1_phy_sels, base + 0xbd80); base 545 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_CSI2_PHY_REF] = imx8m_clk_composite("csi2_phy_ref", imx8mn_csi2_phy_sels, base + 0xbf00); base 546 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_CSI2_ESC] = imx8m_clk_composite("csi2_esc", imx8mn_csi2_esc_sels, base + 0xbf80); base 547 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180); base 548 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_PDM] = imx8m_clk_composite("pdm", imx8mn_pdm_sels, base + 0xc200); base 549 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI7] = imx8m_clk_composite("sai7", imx8mn_sai7_sels, base + 0xc300); base 551 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0); base 552 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0); base 553 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0); base 554 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0); base 555 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0); base 556 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0); base 557 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0); base 558 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0); base 559 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0); base 560 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0); base 561 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0); base 562 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0); base 563 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0); base 564 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0); base 565 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0); base 566 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0); base 567 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0); base 568 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0); base 569 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0); base 570 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0); base 571 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_NAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand); base 572 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand); base 573 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2); base 574 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2); base 575 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3); base 576 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3); base 577 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5); base 578 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); base 579 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); base 580 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); base 581 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); base 582 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); base 583 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); base 584 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0); base 585 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0); base 586 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_gate4("gpu_core_root_clk", "gpu_core_div", base + 0x44f0, 0); base 587 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0); base 588 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0); base 589 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0); base 590 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0); base 591 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0); base 592 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_GPU_BUS_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0); base 593 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_ASRC_ROOT] = imx_clk_gate4("asrc_root_clk", "audio_ahb", base + 0x4580, 0); base 594 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm); base 595 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm); base 596 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp); base 597 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp); base 598 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_CAMERA_PIXEL_ROOT] = imx_clk_gate2_shared2("camera_pixel_clk", "camera_pixel", base + 0x45d0, 0, &share_count_disp); base 599 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_DISP_PIXEL_ROOT] = imx_clk_gate2_shared2("disp_pixel_clk", "disp_pixel", base + 0x45d0, 0, &share_count_disp); base 600 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0); base 601 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0); base 602 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0); base 603 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0); base 604 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0); base 605 drivers/clk/imx/clk-imx8mn.c clks[IMX8MN_CLK_SAI7_ROOT] = imx_clk_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7); base 287 drivers/clk/imx/clk-imx8mq.c void __iomem *base; base 300 drivers/clk/imx/clk-imx8mq.c base = of_iomap(np, 0); base 301 drivers/clk/imx/clk-imx8mq.c if (WARN_ON(!base)) base 304 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 305 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 306 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 307 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 308 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 309 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 310 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_SYS1_PLL1_REF_SEL] = imx_clk_mux("sys1_pll1_ref_sel", base + 0x30, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 311 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_SYS2_PLL1_REF_SEL] = imx_clk_mux("sys2_pll1_ref_sel", base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 312 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 313 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); base 315 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_ARM_PLL_REF_DIV] = imx_clk_divider("arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6); base 316 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_GPU_PLL_REF_DIV] = imx_clk_divider("gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6); base 317 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_VPU_PLL_REF_DIV] = imx_clk_divider("vpu_pll_ref_div", "vpu_pll_ref_sel", base + 0x20, 5, 6); base 318 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_AUDIO_PLL1_REF_DIV] = imx_clk_divider("audio_pll1_ref_div", "audio_pll1_ref_sel", base + 0x0, 5, 6); base 319 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_AUDIO_PLL2_REF_DIV] = imx_clk_divider("audio_pll2_ref_div", "audio_pll2_ref_sel", base + 0x8, 5, 6); base 320 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_VIDEO_PLL1_REF_DIV] = imx_clk_divider("video_pll1_ref_div", "video_pll1_ref_sel", base + 0x10, 5, 6); base 322 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_ARM_PLL] = imx_clk_frac_pll("arm_pll", "arm_pll_ref_div", base + 0x28); base 323 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_GPU_PLL] = imx_clk_frac_pll("gpu_pll", "gpu_pll_ref_div", base + 0x18); base 324 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_VPU_PLL] = imx_clk_frac_pll("vpu_pll", "vpu_pll_ref_div", base + 0x20); base 325 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_AUDIO_PLL1] = imx_clk_frac_pll("audio_pll1", "audio_pll1_ref_div", base + 0x0); base 326 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_AUDIO_PLL2] = imx_clk_frac_pll("audio_pll2", "audio_pll2_ref_div", base + 0x8); base 327 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_VIDEO_PLL1] = imx_clk_frac_pll("video_pll1", "video_pll1_ref_div", base + 0x10); base 330 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); base 331 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_GPU_PLL_BYPASS] = imx_clk_mux("gpu_pll_bypass", base + 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels)); base 332 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_VPU_PLL_BYPASS] = imx_clk_mux("vpu_pll_bypass", base + 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels)); base 333 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_AUDIO_PLL1_BYPASS] = imx_clk_mux("audio_pll1_bypass", base + 0x0, 14, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels)); base 334 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_AUDIO_PLL2_BYPASS] = imx_clk_mux("audio_pll2_bypass", base + 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels)); base 335 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_VIDEO_PLL1_BYPASS] = imx_clk_mux("video_pll1_bypass", base + 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels)); base 338 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x28, 21); base 339 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x18, 21); base 340 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x20, 21); base 341 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base + 0x0, 21); base 342 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x8, 21); base 343 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21); base 345 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, CLK_IS_CRITICAL); base 346 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, CLK_IS_CRITICAL); base 347 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL); base 348 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL); base 371 drivers/clk/imx/clk-imx8mq.c base = devm_platform_ioremap_resource(pdev, 0); base 372 drivers/clk/imx/clk-imx8mq.c if (WARN_ON(IS_ERR(base))) base 373 drivers/clk/imx/clk-imx8mq.c return PTR_ERR(base); base 376 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels)); base 377 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_M4_SRC] = imx_clk_mux2("arm_m4_src", base + 0x8080, 24, 3, imx8mq_arm_m4_sels, ARRAY_SIZE(imx8mq_arm_m4_sels)); base 378 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_VPU_SRC] = imx_clk_mux2("vpu_src", base + 0x8100, 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels)); base 379 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels)); base 380 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mq_gpu_shader_sels, ARRAY_SIZE(imx8mq_gpu_shader_sels)); base 382 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_A53_CG] = imx_clk_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL); base 383 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_M4_CG] = imx_clk_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); base 384 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_VPU_CG] = imx_clk_gate3("vpu_cg", "vpu_src", base + 0x8100, 28); base 385 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28); base 386 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28); base 388 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3); base 389 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_M4_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); base 390 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_VPU_DIV] = imx_clk_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3); base 391 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3); base 392 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3); base 395 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800); base 396 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mq_enet_axi_sels, base + 0x8880); base 397 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_NAND_USDHC_BUS] = imx8m_clk_composite("nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900); base 398 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_VPU_BUS] = imx8m_clk_composite("vpu_bus", imx8mq_vpu_bus_sels, base + 0x8980); base 399 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mq_disp_axi_sels, base + 0x8a00); base 400 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mq_disp_apb_sels, base + 0x8a80); base 401 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DISP_RTRM] = imx8m_clk_composite("disp_rtrm", imx8mq_disp_rtrm_sels, base + 0x8b00); base 402 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_USB_BUS] = imx8m_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80); base 403 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mq_gpu_axi_sels, base + 0x8c00); base 404 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mq_gpu_ahb_sels, base + 0x8c80); base 405 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mq_noc_sels, base + 0x8d00); base 406 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_NOC_APB] = imx8m_clk_composite_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80); base 410 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels, base + 0x9000); base 411 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100); base 414 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); base 415 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1); base 418 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL); base 420 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000); base 421 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080); base 422 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_VPU_G1] = imx8m_clk_composite("vpu_g1", imx8mq_vpu_g1_sels, base + 0xa100); base 423 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_VPU_G2] = imx8m_clk_composite("vpu_g2", imx8mq_vpu_g2_sels, base + 0xa180); base 424 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DISP_DTRC] = imx8m_clk_composite("disp_dtrc", imx8mq_disp_dtrc_sels, base + 0xa200); base 425 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DISP_DC8000] = imx8m_clk_composite("disp_dc8000", imx8mq_disp_dc8000_sels, base + 0xa280); base 426 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PCIE1_CTRL] = imx8m_clk_composite("pcie1_ctrl", imx8mq_pcie1_ctrl_sels, base + 0xa300); base 427 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PCIE1_PHY] = imx8m_clk_composite("pcie1_phy", imx8mq_pcie1_phy_sels, base + 0xa380); base 428 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PCIE1_AUX] = imx8m_clk_composite("pcie1_aux", imx8mq_pcie1_aux_sels, base + 0xa400); base 429 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DC_PIXEL] = imx8m_clk_composite("dc_pixel", imx8mq_dc_pixel_sels, base + 0xa480); base 430 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_LCDIF_PIXEL] = imx8m_clk_composite("lcdif_pixel", imx8mq_lcdif_pixel_sels, base + 0xa500); base 431 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI1] = imx8m_clk_composite("sai1", imx8mq_sai1_sels, base + 0xa580); base 432 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mq_sai2_sels, base + 0xa600); base 433 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mq_sai3_sels, base + 0xa680); base 434 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI4] = imx8m_clk_composite("sai4", imx8mq_sai4_sels, base + 0xa700); base 435 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mq_sai5_sels, base + 0xa780); base 436 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mq_sai6_sels, base + 0xa800); base 437 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SPDIF1] = imx8m_clk_composite("spdif1", imx8mq_spdif1_sels, base + 0xa880); base 438 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SPDIF2] = imx8m_clk_composite("spdif2", imx8mq_spdif2_sels, base + 0xa900); base 439 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mq_enet_ref_sels, base + 0xa980); base 440 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mq_enet_timer_sels, base + 0xaa00); base 441 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy", imx8mq_enet_phy_sels, base + 0xaa80); base 442 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_NAND] = imx8m_clk_composite("nand", imx8mq_nand_sels, base + 0xab00); base 443 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80); base 444 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mq_usdhc1_sels, base + 0xac00); base 445 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mq_usdhc2_sels, base + 0xac80); base 446 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00); base 447 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80); base 448 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00); base 449 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80); base 450 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_UART1] = imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00); base 451 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_UART2] = imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80); base 452 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_UART3] = imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000); base 453 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_UART4] = imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080); base 454 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100); base 455 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180); base 456 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mq_gic_sels, base + 0xb200); base 457 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280); base 458 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300); base 459 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mq_pwm1_sels, base + 0xb380); base 460 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mq_pwm2_sels, base + 0xb400); base 461 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mq_pwm3_sels, base + 0xb480); base 462 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mq_pwm4_sels, base + 0xb500); base 463 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPT1] = imx8m_clk_composite("gpt1", imx8mq_gpt1_sels, base + 0xb580); base 464 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900); base 465 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mq_wrclk_sels, base + 0xb980); base 466 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_CLKO1] = imx8m_clk_composite("clko1", imx8mq_clko1_sels, base + 0xba00); base 467 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_CLKO2] = imx8m_clk_composite("clko2", imx8mq_clko2_sels, base + 0xba80); base 468 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DSI_CORE] = imx8m_clk_composite("dsi_core", imx8mq_dsi_core_sels, base + 0xbb00); base 469 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DSI_PHY_REF] = imx8m_clk_composite("dsi_phy_ref", imx8mq_dsi_phy_sels, base + 0xbb80); base 470 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mq_dsi_dbi_sels, base + 0xbc00); base 471 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DSI_ESC] = imx8m_clk_composite("dsi_esc", imx8mq_dsi_esc_sels, base + 0xbc80); base 472 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DSI_AHB] = imx8m_clk_composite("dsi_ahb", imx8mq_dsi_ahb_sels, base + 0x9200); base 473 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DSI_IPG_DIV] = imx_clk_divider2("dsi_ipg_div", "dsi_ahb", base + 0x9280, 0, 6); base 474 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_CSI1_CORE] = imx8m_clk_composite("csi1_core", imx8mq_csi1_core_sels, base + 0xbd00); base 475 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mq_csi1_phy_sels, base + 0xbd80); base 476 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_CSI1_ESC] = imx8m_clk_composite("csi1_esc", imx8mq_csi1_esc_sels, base + 0xbe00); base 477 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_CSI2_CORE] = imx8m_clk_composite("csi2_core", imx8mq_csi2_core_sels, base + 0xbe80); base 478 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_CSI2_PHY_REF] = imx8m_clk_composite("csi2_phy_ref", imx8mq_csi2_phy_sels, base + 0xbf00); base 479 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_CSI2_ESC] = imx8m_clk_composite("csi2_esc", imx8mq_csi2_esc_sels, base + 0xbf80); base 480 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PCIE2_CTRL] = imx8m_clk_composite("pcie2_ctrl", imx8mq_pcie2_ctrl_sels, base + 0xc000); base 481 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PCIE2_PHY] = imx8m_clk_composite("pcie2_phy", imx8mq_pcie2_phy_sels, base + 0xc080); base 482 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PCIE2_AUX] = imx8m_clk_composite("pcie2_aux", imx8mq_pcie2_aux_sels, base + 0xc100); base 483 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180); base 485 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0); base 486 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0); base 487 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0); base 488 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0); base 489 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0); base 490 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0); base 491 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0); base 492 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0); base 493 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0); base 494 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0); base 495 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0); base 496 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0); base 497 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0); base 498 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0); base 499 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0); base 500 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0); base 501 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PCIE1_ROOT] = imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0); base 502 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PCIE2_ROOT] = imx_clk_gate4("pcie2_root_clk", "pcie2_ctrl", base + 0x4640, 0); base 503 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0); base 504 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0); base 505 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0); base 506 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0); base 507 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0); base 508 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand); base 509 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand); base 510 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI1_ROOT] = imx_clk_gate2_shared2("sai1_root_clk", "sai1", base + 0x4330, 0, &share_count_sai1); base 511 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI1_IPG] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_audio_root", base + 0x4330, 0, &share_count_sai1); base 512 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2); base 513 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_root", base + 0x4340, 0, &share_count_sai2); base 514 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3); base 515 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_root", base + 0x4350, 0, &share_count_sai3); base 516 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI4_ROOT] = imx_clk_gate2_shared2("sai4_root_clk", "sai4", base + 0x4360, 0, &share_count_sai4); base 517 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI4_IPG] = imx_clk_gate2_shared2("sai4_ipg_clk", "ipg_audio_root", base + 0x4360, 0, &share_count_sai4); base 518 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5); base 519 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); base 520 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); base 521 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); base 522 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SNVS_ROOT] = imx_clk_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0); base 523 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); base 524 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); base 525 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); base 526 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0); base 527 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0); base 528 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0); base 529 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0); base 530 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0); base 531 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0); base 532 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0); base 533 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0); base 534 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0); base 535 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0); base 536 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_gate2_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); base 537 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_GPU_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_core_div", base + 0x4570, 0); base 538 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_gate2_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); base 539 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss); base 540 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss); base 541 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss); base 542 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss); base 543 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0); base 544 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); base 545 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0); base 546 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_gate4("csi2_root_clk", "csi2_core", base + 0x4660, 0); base 547 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0); base 548 drivers/clk/imx/clk-imx8mq.c clks[IMX8MQ_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0); base 169 drivers/clk/imx/clk-imx8qxp-lpcg.c void __iomem *base; base 179 drivers/clk/imx/clk-imx8qxp-lpcg.c base = devm_ioremap(dev, res->start, resource_size(res)); base 180 drivers/clk/imx/clk-imx8qxp-lpcg.c if (!base) base 194 drivers/clk/imx/clk-imx8qxp-lpcg.c lpcg->flags, base + lpcg->offset, base 36 drivers/clk/imx/clk-pll14xx.c void __iomem *base; base 80 drivers/clk/imx/clk-pll14xx.c pll_div = readl_relaxed(pll->base + 4); base 99 drivers/clk/imx/clk-pll14xx.c pll_div_ctl0 = readl_relaxed(pll->base + 4); base 100 drivers/clk/imx/clk-pll14xx.c pll_div_ctl1 = readl_relaxed(pll->base + 8); base 130 drivers/clk/imx/clk-pll14xx.c return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0, base 149 drivers/clk/imx/clk-pll14xx.c tmp = readl_relaxed(pll->base + 4); base 154 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base + 4); base 160 drivers/clk/imx/clk-pll14xx.c tmp = readl_relaxed(pll->base); base 162 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); base 166 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); base 170 drivers/clk/imx/clk-pll14xx.c writel(tmp, pll->base); base 174 drivers/clk/imx/clk-pll14xx.c writel_relaxed(div_val, pll->base + 0x4); base 186 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); base 195 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); base 215 drivers/clk/imx/clk-pll14xx.c tmp = readl_relaxed(pll->base + 4); base 220 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base + 4); base 223 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base + 8); base 229 drivers/clk/imx/clk-pll14xx.c tmp = readl_relaxed(pll->base); base 231 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); base 235 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); base 239 drivers/clk/imx/clk-pll14xx.c writel_relaxed(div_val, pll->base + 0x4); base 240 drivers/clk/imx/clk-pll14xx.c writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8); base 252 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); base 261 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); base 276 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); base 280 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); base 282 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); base 289 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); base 299 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); base 313 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); base 315 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); base 341 drivers/clk/imx/clk-pll14xx.c void __iomem *base, base 373 drivers/clk/imx/clk-pll14xx.c pll->base = base; base 379 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); base 381 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); base 26 drivers/clk/imx/clk-pllv1.c void __iomem *base; base 62 drivers/clk/imx/clk-pllv1.c reg = readl(pll->base); base 115 drivers/clk/imx/clk-pllv1.c const char *parent, void __iomem *base) base 125 drivers/clk/imx/clk-pllv1.c pll->base = base; base 75 drivers/clk/imx/clk-pllv2.c void __iomem *base; base 116 drivers/clk/imx/clk-pllv2.c pllbase = pll->base; base 163 drivers/clk/imx/clk-pllv2.c pllbase = pll->base; base 202 drivers/clk/imx/clk-pllv2.c pllbase = pll->base; base 229 drivers/clk/imx/clk-pllv2.c pllbase = pll->base; base 243 drivers/clk/imx/clk-pllv2.c void __iomem *base) base 253 drivers/clk/imx/clk-pllv2.c pll->base = base; base 42 drivers/clk/imx/clk-pllv3.c void __iomem *base; base 57 drivers/clk/imx/clk-pllv3.c u32 val = readl_relaxed(pll->base) & pll->power_bit; base 65 drivers/clk/imx/clk-pllv3.c if (readl_relaxed(pll->base) & BM_PLL_LOCK) base 72 drivers/clk/imx/clk-pllv3.c return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; base 80 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); base 85 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); base 95 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); base 100 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); base 107 drivers/clk/imx/clk-pllv3.c if (readl_relaxed(pll->base) & BM_PLL_LOCK) base 117 drivers/clk/imx/clk-pllv3.c u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; base 144 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); base 147 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); base 165 drivers/clk/imx/clk-pllv3.c u32 div = readl_relaxed(pll->base) & pll->div_mask; base 199 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); base 202 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); base 220 drivers/clk/imx/clk-pllv3.c u32 mfn = readl_relaxed(pll->base + pll->num_offset); base 221 drivers/clk/imx/clk-pllv3.c u32 mfd = readl_relaxed(pll->base + pll->denom_offset); base 222 drivers/clk/imx/clk-pllv3.c u32 div = readl_relaxed(pll->base) & pll->div_mask; base 286 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); base 289 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); base 290 drivers/clk/imx/clk-pllv3.c writel_relaxed(mfn, pll->base + pll->num_offset); base 291 drivers/clk/imx/clk-pllv3.c writel_relaxed(mfd, pll->base + pll->denom_offset); base 353 drivers/clk/imx/clk-pllv3.c mf.mfn = readl_relaxed(pll->base + pll->num_offset); base 354 drivers/clk/imx/clk-pllv3.c mf.mfd = readl_relaxed(pll->base + pll->denom_offset); base 355 drivers/clk/imx/clk-pllv3.c mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; base 376 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); base 381 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); base 383 drivers/clk/imx/clk-pllv3.c writel_relaxed(mf.mfn, pll->base + pll->num_offset); base 384 drivers/clk/imx/clk-pllv3.c writel_relaxed(mf.mfd, pll->base + pll->denom_offset); base 414 drivers/clk/imx/clk-pllv3.c const char *parent_name, void __iomem *base, base 472 drivers/clk/imx/clk-pllv3.c pll->base = base; base 39 drivers/clk/imx/clk-pllv4.c void __iomem *base; base 53 drivers/clk/imx/clk-pllv4.c return readl_poll_timeout(pll->base + PLL_CSR_OFFSET, base 61 drivers/clk/imx/clk-pllv4.c if (readl_relaxed(pll->base) & PLL_EN) base 74 drivers/clk/imx/clk-pllv4.c mult = readl_relaxed(pll->base + PLL_CFG_OFFSET); base 78 drivers/clk/imx/clk-pllv4.c mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); base 79 drivers/clk/imx/clk-pllv4.c mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); base 167 drivers/clk/imx/clk-pllv4.c val = readl_relaxed(pll->base + PLL_CFG_OFFSET); base 170 drivers/clk/imx/clk-pllv4.c writel_relaxed(val, pll->base + PLL_CFG_OFFSET); base 172 drivers/clk/imx/clk-pllv4.c writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); base 173 drivers/clk/imx/clk-pllv4.c writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); base 183 drivers/clk/imx/clk-pllv4.c val = readl_relaxed(pll->base); base 185 drivers/clk/imx/clk-pllv4.c writel_relaxed(val, pll->base); base 195 drivers/clk/imx/clk-pllv4.c val = readl_relaxed(pll->base); base 197 drivers/clk/imx/clk-pllv4.c writel_relaxed(val, pll->base); base 210 drivers/clk/imx/clk-pllv4.c void __iomem *base) base 221 drivers/clk/imx/clk-pllv4.c pll->base = base; base 90 drivers/clk/imx/clk-sccg-pll.c void __iomem *base; base 105 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG0); base 109 drivers/clk/imx/clk-sccg-pll.c return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, base 309 drivers/clk/imx/clk-sccg-pll.c u32 val = readl_relaxed(pll->base + PLL_CFG0); base 319 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG0); base 321 drivers/clk/imx/clk-sccg-pll.c writel_relaxed(val, pll->base + PLL_CFG0); base 331 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG0); base 333 drivers/clk/imx/clk-sccg-pll.c writel_relaxed(val, pll->base + PLL_CFG0); base 343 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG2); base 352 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); base 375 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); base 378 drivers/clk/imx/clk-sccg-pll.c writel(val, pll->base + PLL_CFG0); base 380 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG2); base 388 drivers/clk/imx/clk-sccg-pll.c writel_relaxed(val, pll->base + PLL_CFG2); base 399 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); base 412 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); base 415 drivers/clk/imx/clk-sccg-pll.c writel(val, pll->base + PLL_CFG0); base 513 drivers/clk/imx/clk-sccg-pll.c void __iomem *base, base 529 drivers/clk/imx/clk-sccg-pll.c pll->base = base; base 537 drivers/clk/imx/clk-sccg-pll.c pll->base = base; base 61 drivers/clk/imx/clk.h #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ base 62 drivers/clk/imx/clk.h to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask)) base 98 drivers/clk/imx/clk.h void __iomem *base, const struct imx_pll14xx_clk *pll_clk); base 101 drivers/clk/imx/clk.h const char *parent, void __iomem *base); base 104 drivers/clk/imx/clk.h void __iomem *base); base 107 drivers/clk/imx/clk.h void __iomem *base); base 113 drivers/clk/imx/clk.h void __iomem *base, base 130 drivers/clk/imx/clk.h const char *parent_name, void __iomem *base, u32 div_mask); base 150 drivers/clk/imx/clk.h void __iomem *base); base 38 drivers/clk/ingenic/cgu.c return !!(readl(cgu->base + info->reg) & BIT(info->bit)) base 56 drivers/clk/ingenic/cgu.c u32 clkgr = readl(cgu->base + info->reg); base 63 drivers/clk/ingenic/cgu.c writel(clkgr, cgu->base + info->reg); base 87 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); base 186 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); base 197 drivers/clk/ingenic/cgu.c writel(ctl, cgu->base + pll_info->reg); base 215 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); base 220 drivers/clk/ingenic/cgu.c writel(ctl, cgu->base + pll_info->reg); base 224 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); base 248 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); base 252 drivers/clk/ingenic/cgu.c writel(ctl, cgu->base + pll_info->reg); base 266 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); base 297 drivers/clk/ingenic/cgu.c reg = readl(cgu->base + clk_info->mux.reg); base 351 drivers/clk/ingenic/cgu.c reg = readl(cgu->base + clk_info->mux.reg); base 354 drivers/clk/ingenic/cgu.c writel(reg, cgu->base + clk_info->mux.reg); base 375 drivers/clk/ingenic/cgu.c div_reg = readl(cgu->base + clk_info->div.reg); base 484 drivers/clk/ingenic/cgu.c reg = readl(cgu->base + clk_info->div.reg); base 500 drivers/clk/ingenic/cgu.c writel(reg, cgu->base + clk_info->div.reg); base 505 drivers/clk/ingenic/cgu.c reg = readl(cgu->base + clk_info->div.reg); base 750 drivers/clk/ingenic/cgu.c cgu->base = of_iomap(np, 0); base 751 drivers/clk/ingenic/cgu.c if (!cgu->base) { base 182 drivers/clk/ingenic/cgu.h void __iomem *base; base 51 drivers/clk/ingenic/jz4770-cgu.c void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; base 52 drivers/clk/ingenic/jz4770-cgu.c void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; base 61 drivers/clk/ingenic/jz4770-cgu.c void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; base 62 drivers/clk/ingenic/jz4770-cgu.c void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; base 70 drivers/clk/ingenic/jz4770-cgu.c void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; base 71 drivers/clk/ingenic/jz4770-cgu.c void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; base 109 drivers/clk/ingenic/jz4780-cgu.c usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); base 113 drivers/clk/ingenic/jz4780-cgu.c writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); base 125 drivers/clk/ingenic/jz4780-cgu.c usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); base 190 drivers/clk/ingenic/jz4780-cgu.c usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); base 193 drivers/clk/ingenic/jz4780-cgu.c writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); base 42 drivers/clk/ingenic/pm.c ingenic_cgu_base = cgu->base; base 669 drivers/clk/mediatek/clk-mt2701.c void __iomem *base; base 673 drivers/clk/mediatek/clk-mt2701.c base = devm_ioremap_resource(&pdev->dev, res); base 674 drivers/clk/mediatek/clk-mt2701.c if (IS_ERR(base)) base 675 drivers/clk/mediatek/clk-mt2701.c return PTR_ERR(base); base 686 drivers/clk/mediatek/clk-mt2701.c base, &mt2701_clk_lock, clk_data); base 689 drivers/clk/mediatek/clk-mt2701.c base, &mt2701_clk_lock, clk_data); base 889 drivers/clk/mediatek/clk-mt2701.c void __iomem *base; base 894 drivers/clk/mediatek/clk-mt2701.c base = devm_ioremap_resource(&pdev->dev, res); base 895 drivers/clk/mediatek/clk-mt2701.c if (IS_ERR(base)) base 896 drivers/clk/mediatek/clk-mt2701.c return PTR_ERR(base); base 903 drivers/clk/mediatek/clk-mt2701.c mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, base 1308 drivers/clk/mediatek/clk-mt2712.c void __iomem *base; base 1311 drivers/clk/mediatek/clk-mt2712.c base = devm_ioremap_resource(&pdev->dev, res); base 1312 drivers/clk/mediatek/clk-mt2712.c if (IS_ERR(base)) { base 1314 drivers/clk/mediatek/clk-mt2712.c return PTR_ERR(base); base 1331 drivers/clk/mediatek/clk-mt2712.c mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, base 1333 drivers/clk/mediatek/clk-mt2712.c mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, base 1396 drivers/clk/mediatek/clk-mt2712.c void __iomem *base; base 1399 drivers/clk/mediatek/clk-mt2712.c base = devm_ioremap_resource(&pdev->dev, res); base 1400 drivers/clk/mediatek/clk-mt2712.c if (IS_ERR(base)) { base 1402 drivers/clk/mediatek/clk-mt2712.c return PTR_ERR(base); base 1407 drivers/clk/mediatek/clk-mt2712.c mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, base 1229 drivers/clk/mediatek/clk-mt6779.c void __iomem *base; base 1233 drivers/clk/mediatek/clk-mt6779.c base = devm_ioremap_resource(&pdev->dev, res); base 1234 drivers/clk/mediatek/clk-mt6779.c if (IS_ERR(base)) base 1235 drivers/clk/mediatek/clk-mt6779.c return PTR_ERR(base); base 1248 drivers/clk/mediatek/clk-mt6779.c base, &mt6779_clk_lock, clk_data); base 1251 drivers/clk/mediatek/clk-mt6779.c base, &mt6779_clk_lock, clk_data); base 386 drivers/clk/mediatek/clk-mt6797.c void __iomem *base; base 390 drivers/clk/mediatek/clk-mt6797.c base = devm_ioremap_resource(&pdev->dev, res); base 391 drivers/clk/mediatek/clk-mt6797.c if (IS_ERR(base)) base 392 drivers/clk/mediatek/clk-mt6797.c return PTR_ERR(base); base 399 drivers/clk/mediatek/clk-mt6797.c mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, base 615 drivers/clk/mediatek/clk-mt7622.c void __iomem *base; base 619 drivers/clk/mediatek/clk-mt7622.c base = devm_ioremap_resource(&pdev->dev, res); base 620 drivers/clk/mediatek/clk-mt7622.c if (IS_ERR(base)) base 621 drivers/clk/mediatek/clk-mt7622.c return PTR_ERR(base); base 632 drivers/clk/mediatek/clk-mt7622.c base, &mt7622_clk_lock, clk_data); base 635 drivers/clk/mediatek/clk-mt7622.c base, &mt7622_clk_lock, clk_data); base 695 drivers/clk/mediatek/clk-mt7622.c void __iomem *base; base 700 drivers/clk/mediatek/clk-mt7622.c base = devm_ioremap_resource(&pdev->dev, res); base 701 drivers/clk/mediatek/clk-mt7622.c if (IS_ERR(base)) base 702 drivers/clk/mediatek/clk-mt7622.c return PTR_ERR(base); base 709 drivers/clk/mediatek/clk-mt7622.c mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, base 575 drivers/clk/mediatek/clk-mt7629.c void __iomem *base; base 579 drivers/clk/mediatek/clk-mt7629.c base = devm_ioremap_resource(&pdev->dev, res); base 580 drivers/clk/mediatek/clk-mt7629.c if (IS_ERR(base)) base 581 drivers/clk/mediatek/clk-mt7629.c return PTR_ERR(base); base 592 drivers/clk/mediatek/clk-mt7629.c base, &mt7629_clk_lock, clk_data); base 626 drivers/clk/mediatek/clk-mt7629.c void __iomem *base; base 631 drivers/clk/mediatek/clk-mt7629.c base = devm_ioremap_resource(&pdev->dev, res); base 632 drivers/clk/mediatek/clk-mt7629.c if (IS_ERR(base)) base 633 drivers/clk/mediatek/clk-mt7629.c return PTR_ERR(base); base 640 drivers/clk/mediatek/clk-mt7629.c mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, base 519 drivers/clk/mediatek/clk-mt8135.c void __iomem *base; base 522 drivers/clk/mediatek/clk-mt8135.c base = of_iomap(node, 0); base 523 drivers/clk/mediatek/clk-mt8135.c if (!base) { base 532 drivers/clk/mediatek/clk-mt8135.c mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, base 569 drivers/clk/mediatek/clk-mt8135.c void __iomem *base; base 571 drivers/clk/mediatek/clk-mt8135.c base = of_iomap(node, 0); base 572 drivers/clk/mediatek/clk-mt8135.c if (!base) { base 581 drivers/clk/mediatek/clk-mt8135.c mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, base 927 drivers/clk/mediatek/clk-mt8173.c void __iomem *base; base 930 drivers/clk/mediatek/clk-mt8173.c base = of_iomap(node, 0); base 931 drivers/clk/mediatek/clk-mt8173.c if (!base) { base 940 drivers/clk/mediatek/clk-mt8173.c mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, base 979 drivers/clk/mediatek/clk-mt8173.c void __iomem *base; base 981 drivers/clk/mediatek/clk-mt8173.c base = of_iomap(node, 0); base 982 drivers/clk/mediatek/clk-mt8173.c if (!base) { base 991 drivers/clk/mediatek/clk-mt8173.c mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, base 1081 drivers/clk/mediatek/clk-mt8173.c void __iomem *base; base 1085 drivers/clk/mediatek/clk-mt8173.c base = of_iomap(node, 0); base 1086 drivers/clk/mediatek/clk-mt8173.c if (!base) { base 1093 drivers/clk/mediatek/clk-mt8173.c iounmap(base); base 1103 drivers/clk/mediatek/clk-mt8173.c base + cku->reg_ofs); base 1115 drivers/clk/mediatek/clk-mt8173.c base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO, base 1193 drivers/clk/mediatek/clk-mt8183.c void __iomem *base; base 1196 drivers/clk/mediatek/clk-mt8183.c base = devm_ioremap_resource(&pdev->dev, res); base 1197 drivers/clk/mediatek/clk-mt8183.c if (IS_ERR(base)) base 1198 drivers/clk/mediatek/clk-mt8183.c return PTR_ERR(base); base 1212 drivers/clk/mediatek/clk-mt8183.c base, &mt8183_clk_lock, top_clk_data); base 1215 drivers/clk/mediatek/clk-mt8183.c base, &mt8183_clk_lock, top_clk_data); base 1264 drivers/clk/mediatek/clk-mt8183.c void __iomem *base; base 1267 drivers/clk/mediatek/clk-mt8183.c base = devm_ioremap_resource(&pdev->dev, res); base 1268 drivers/clk/mediatek/clk-mt8183.c if (IS_ERR(base)) base 1269 drivers/clk/mediatek/clk-mt8183.c return PTR_ERR(base); base 1273 drivers/clk/mediatek/clk-mt8183.c mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, base 681 drivers/clk/mediatek/clk-mt8516.c void __iomem *base; base 683 drivers/clk/mediatek/clk-mt8516.c base = of_iomap(node, 0); base 684 drivers/clk/mediatek/clk-mt8516.c if (!base) { base 696 drivers/clk/mediatek/clk-mt8516.c mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, base 699 drivers/clk/mediatek/clk-mt8516.c base, &mt8516_clk_lock, clk_data); base 712 drivers/clk/mediatek/clk-mt8516.c void __iomem *base; base 714 drivers/clk/mediatek/clk-mt8516.c base = of_iomap(node, 0); base 715 drivers/clk/mediatek/clk-mt8516.c if (!base) { base 722 drivers/clk/mediatek/clk-mt8516.c mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base, base 790 drivers/clk/mediatek/clk-mt8516.c void __iomem *base; base 793 drivers/clk/mediatek/clk-mt8516.c base = of_iomap(node, 0); base 794 drivers/clk/mediatek/clk-mt8516.c if (!base) { base 150 drivers/clk/mediatek/clk-mtk.c void __iomem *base, spinlock_t *lock) base 168 drivers/clk/mediatek/clk-mtk.c mux->reg = base + mc->mux_reg; base 191 drivers/clk/mediatek/clk-mtk.c gate->reg = base + mc->gate_reg; base 207 drivers/clk/mediatek/clk-mtk.c div->reg = base + mc->divider_reg; base 237 drivers/clk/mediatek/clk-mtk.c int num, void __iomem *base, spinlock_t *lock, base 249 drivers/clk/mediatek/clk-mtk.c clk = mtk_clk_register_composite(mc, base, lock); base 263 drivers/clk/mediatek/clk-mtk.c int num, void __iomem *base, spinlock_t *lock, base 276 drivers/clk/mediatek/clk-mtk.c mcd->flags, base + mcd->div_reg, mcd->div_shift, base 146 drivers/clk/mediatek/clk-mtk.h void __iomem *base, spinlock_t *lock); base 149 drivers/clk/mediatek/clk-mtk.h int num, void __iomem *base, spinlock_t *lock, base 200 drivers/clk/mediatek/clk-mtk.h int num, void __iomem *base, spinlock_t *lock, base 301 drivers/clk/mediatek/clk-pll.c void __iomem *base) base 312 drivers/clk/mediatek/clk-pll.c pll->base_addr = base + data->reg; base 313 drivers/clk/mediatek/clk-pll.c pll->pwr_addr = base + data->pwr_reg; base 314 drivers/clk/mediatek/clk-pll.c pll->pd_addr = base + data->pd_reg; base 315 drivers/clk/mediatek/clk-pll.c pll->pcw_addr = base + data->pcw_reg; base 317 drivers/clk/mediatek/clk-pll.c pll->pcw_chg_addr = base + data->pcw_chg_reg; base 321 drivers/clk/mediatek/clk-pll.c pll->tuner_addr = base + data->tuner_reg; base 323 drivers/clk/mediatek/clk-pll.c pll->tuner_en_addr = base + data->tuner_en_reg; base 347 drivers/clk/mediatek/clk-pll.c void __iomem *base; base 351 drivers/clk/mediatek/clk-pll.c base = of_iomap(node, 0); base 352 drivers/clk/mediatek/clk-pll.c if (!base) { base 360 drivers/clk/mediatek/clk-pll.c clk = mtk_clk_register_pll(pll, base); base 29 drivers/clk/mmp/clk-apbc.c void __iomem *base; base 48 drivers/clk/mmp/clk-apbc.c data = readl_relaxed(apbc->base); base 52 drivers/clk/mmp/clk-apbc.c writel_relaxed(data, apbc->base); base 62 drivers/clk/mmp/clk-apbc.c data = readl_relaxed(apbc->base); base 64 drivers/clk/mmp/clk-apbc.c writel_relaxed(data, apbc->base); base 75 drivers/clk/mmp/clk-apbc.c data = readl_relaxed(apbc->base); base 77 drivers/clk/mmp/clk-apbc.c writel_relaxed(data, apbc->base); base 95 drivers/clk/mmp/clk-apbc.c data = readl_relaxed(apbc->base); base 99 drivers/clk/mmp/clk-apbc.c writel_relaxed(data, apbc->base); base 109 drivers/clk/mmp/clk-apbc.c data = readl_relaxed(apbc->base); base 111 drivers/clk/mmp/clk-apbc.c writel_relaxed(data, apbc->base); base 123 drivers/clk/mmp/clk-apbc.c void __iomem *base, unsigned int delay, base 140 drivers/clk/mmp/clk-apbc.c apbc->base = base; base 23 drivers/clk/mmp/clk-apmu.c void __iomem *base; base 38 drivers/clk/mmp/clk-apmu.c data = readl_relaxed(apmu->base) | apmu->enable_mask; base 39 drivers/clk/mmp/clk-apmu.c writel_relaxed(data, apmu->base); base 56 drivers/clk/mmp/clk-apmu.c data = readl_relaxed(apmu->base) & ~apmu->enable_mask; base 57 drivers/clk/mmp/clk-apmu.c writel_relaxed(data, apmu->base); base 69 drivers/clk/mmp/clk-apmu.c void __iomem *base, u32 enable_mask, spinlock_t *lock) base 85 drivers/clk/mmp/clk-apmu.c apmu->base = base; base 58 drivers/clk/mmp/clk-frac.c val = readl_relaxed(factor->base); base 96 drivers/clk/mmp/clk-frac.c val = readl_relaxed(factor->base); base 104 drivers/clk/mmp/clk-frac.c writel_relaxed(val, factor->base); base 123 drivers/clk/mmp/clk-frac.c val = readl(factor->base); base 144 drivers/clk/mmp/clk-frac.c writel(val, factor->base); base 159 drivers/clk/mmp/clk-frac.c unsigned long flags, void __iomem *base, base 178 drivers/clk/mmp/clk-frac.c factor->base = base; base 188 drivers/clk/mmp/clk-of-pxa1928.c int i, base, nr_resets; base 195 drivers/clk/mmp/clk-of-pxa1928.c base = 0; base 197 drivers/clk/mmp/clk-of-pxa1928.c cells[base + i].clk_id = apbc_gate_clks[i].id; base 198 drivers/clk/mmp/clk-of-pxa1928.c cells[base + i].reg = base 200 drivers/clk/mmp/clk-of-pxa1928.c cells[base + i].flags = 0; base 201 drivers/clk/mmp/clk-of-pxa1928.c cells[base + i].lock = apbc_gate_clks[i].lock; base 202 drivers/clk/mmp/clk-of-pxa1928.c cells[base + i].bits = 0x4; base 238 drivers/clk/mmp/clk-of-pxa910.c int i, base, nr_resets_apbc, nr_resets_apbcp, nr_resets; base 247 drivers/clk/mmp/clk-of-pxa910.c base = 0; base 249 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].clk_id = apbc_gate_clks[i].id; base 250 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].reg = base 252 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].flags = 0; base 253 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].lock = apbc_gate_clks[i].lock; base 254 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].bits = 0x4; base 257 drivers/clk/mmp/clk-of-pxa910.c base = nr_resets_apbc; base 259 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].clk_id = apbcp_gate_clks[i].id; base 260 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].reg = base 262 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].flags = 0; base 263 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].lock = apbc_gate_clks[i].lock; base 264 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].bits = 0x4; base 72 drivers/clk/mmp/clk.c void __iomem *base, int size) base 81 drivers/clk/mmp/clk.c base + clks[i].offset, base 98 drivers/clk/mmp/clk.c void __iomem *base, int size) base 107 drivers/clk/mmp/clk.c base + clks[i].offset, base 126 drivers/clk/mmp/clk.c void __iomem *base, int size) base 136 drivers/clk/mmp/clk.c base + clks[i].offset, base 154 drivers/clk/mmp/clk.c void __iomem *base, int size) base 163 drivers/clk/mmp/clk.c base + clks[i].offset, base 28 drivers/clk/mmp/clk.h void __iomem *base; base 37 drivers/clk/mmp/clk.h void __iomem *base, struct mmp_clk_factor_masks *masks, base 131 drivers/clk/mmp/clk.h const char *parent_name, void __iomem *base, base 134 drivers/clk/mmp/clk.h const char *parent_name, void __iomem *base, u32 enable_mask, base 178 drivers/clk/mmp/clk.h void __iomem *base, int size); base 194 drivers/clk/mmp/clk.h void __iomem *base, int size); base 210 drivers/clk/mmp/clk.h void __iomem *base, int size); base 225 drivers/clk/mmp/clk.h void __iomem *base, int size); base 364 drivers/clk/mvebu/armada-37xx-periph.c static bool armada_3700_pm_dvfs_is_enabled(struct regmap *base) base 368 drivers/clk/mvebu/armada-37xx-periph.c if (IS_ERR(base)) base 371 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &val); base 376 drivers/clk/mvebu/armada-37xx-periph.c static unsigned int armada_3700_pm_dvfs_get_cpu_div(struct regmap *base) base 387 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &load_level); base 396 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &div); base 401 drivers/clk/mvebu/armada-37xx-periph.c static unsigned int armada_3700_pm_dvfs_get_cpu_parent(struct regmap *base) base 412 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &load_level); base 421 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &sel); base 444 drivers/clk/mvebu/armada-37xx-periph.c struct regmap *base = pm_cpu->nb_pm_base; base 451 drivers/clk/mvebu/armada-37xx-periph.c if (IS_ERR(base) || armada_3700_pm_dvfs_is_enabled(base)) base 463 drivers/clk/mvebu/armada-37xx-periph.c regmap_update_bits(base, reg, mask, val); base 485 drivers/clk/mvebu/armada-37xx-periph.c struct regmap *base = pm_cpu->nb_pm_base; base 489 drivers/clk/mvebu/armada-37xx-periph.c if (!armada_3700_pm_dvfs_is_enabled(base)) base 497 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &val); base 530 drivers/clk/mvebu/armada-37xx-periph.c static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base) base 537 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level); base 542 drivers/clk/mvebu/armada-37xx-periph.c regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD, base 552 drivers/clk/mvebu/armada-37xx-periph.c struct regmap *base = pm_cpu->nb_pm_base; base 557 drivers/clk/mvebu/armada-37xx-periph.c if (!armada_3700_pm_dvfs_is_enabled(base)) base 566 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &val); base 579 drivers/clk/mvebu/armada-37xx-periph.c clk_pm_cpu_set_rate_wa(rate, base); base 581 drivers/clk/mvebu/armada-37xx-periph.c regmap_update_bits(base, reg, mask, load_level); base 257 drivers/clk/mvebu/clk-corediv.c void __iomem *base; base 262 drivers/clk/mvebu/clk-corediv.c base = of_iomap(node, 0); base 263 drivers/clk/mvebu/clk-corediv.c if (WARN_ON(!base)) base 294 drivers/clk/mvebu/clk-corediv.c corediv[i].reg = base; base 308 drivers/clk/mvebu/clk-corediv.c iounmap(base); base 112 drivers/clk/mvebu/common.c void __iomem *base; base 116 drivers/clk/mvebu/common.c base = of_iomap(np, 0); base 117 drivers/clk/mvebu/common.c if (WARN_ON(!base)) base 130 drivers/clk/mvebu/common.c iounmap(base); base 137 drivers/clk/mvebu/common.c rate = desc->get_tclk_freq(base); base 145 drivers/clk/mvebu/common.c rate = desc->get_cpu_freq(base); base 148 drivers/clk/mvebu/common.c && desc->is_sscg_enabled(base)) base 162 drivers/clk/mvebu/common.c desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div); base 173 drivers/clk/mvebu/common.c rate = desc->get_refclk_freq(base); base 180 drivers/clk/mvebu/common.c iounmap(base); base 195 drivers/clk/mvebu/common.c void __iomem *base; base 220 drivers/clk/mvebu/common.c ctrl->saved_reg = readl(ctrl->base); base 226 drivers/clk/mvebu/common.c writel(ctrl->saved_reg, ctrl->base); base 238 drivers/clk/mvebu/common.c void __iomem *base; base 247 drivers/clk/mvebu/common.c base = of_iomap(np, 0); base 248 drivers/clk/mvebu/common.c if (WARN_ON(!base)) base 264 drivers/clk/mvebu/common.c ctrl->base = base; base 280 drivers/clk/mvebu/common.c desc[n].flags, base, desc[n].bit_idx, base 293 drivers/clk/mvebu/common.c iounmap(base); base 20 drivers/clk/mvebu/dove-divider.c void __iomem *base; base 37 drivers/clk/mvebu/dove-divider.c static void dove_load_divider(void __iomem *base, u32 val, u32 mask, u32 load) base 41 drivers/clk/mvebu/dove-divider.c v = readl_relaxed(base + DIV_CTRL1) | DIV_CTRL1_N_RESET_MASK; base 42 drivers/clk/mvebu/dove-divider.c writel_relaxed(v, base + DIV_CTRL1); base 44 drivers/clk/mvebu/dove-divider.c v = (readl_relaxed(base + DIV_CTRL0) & ~(mask | load)) | val; base 45 drivers/clk/mvebu/dove-divider.c writel_relaxed(v, base + DIV_CTRL0); base 46 drivers/clk/mvebu/dove-divider.c writel_relaxed(v | load, base + DIV_CTRL0); base 48 drivers/clk/mvebu/dove-divider.c writel_relaxed(v, base + DIV_CTRL0); base 56 drivers/clk/mvebu/dove-divider.c val = readl_relaxed(dc->base + DIV_CTRL0); base 149 drivers/clk/mvebu/dove-divider.c dove_load_divider(dc->base, div, mask, load); base 163 drivers/clk/mvebu/dove-divider.c void __iomem *base) base 176 drivers/clk/mvebu/dove-divider.c dc->base = base; base 219 drivers/clk/mvebu/dove-divider.c static int dove_divider_init(struct device *dev, void __iomem *base, base 236 drivers/clk/mvebu/dove-divider.c ARRAY_SIZE(core_pll), base); base 250 drivers/clk/mvebu/dove-divider.c void __iomem *base; base 252 drivers/clk/mvebu/dove-divider.c base = of_iomap(np, 0); base 253 drivers/clk/mvebu/dove-divider.c if (WARN_ON(!base)) base 256 drivers/clk/mvebu/dove-divider.c if (WARN_ON(dove_divider_init(NULL, base, dove_divider_clocks))) { base 257 drivers/clk/mvebu/dove-divider.c iounmap(base); base 292 drivers/clk/mvebu/kirkwood.c void __iomem *base; base 295 drivers/clk/mvebu/kirkwood.c base = of_iomap(np, 0); base 296 drivers/clk/mvebu/kirkwood.c if (WARN_ON(!base)) base 319 drivers/clk/mvebu/kirkwood.c desc[n].flags, base, desc[n].shift, base 330 drivers/clk/mvebu/kirkwood.c iounmap(base); base 25 drivers/clk/mxs/clk-pll.c void __iomem *base; base 36 drivers/clk/mxs/clk-pll.c writel_relaxed(1 << pll->power, pll->base + SET); base 47 drivers/clk/mxs/clk-pll.c writel_relaxed(1 << pll->power, pll->base + CLR); base 54 drivers/clk/mxs/clk-pll.c writel_relaxed(1 << 31, pll->base + CLR); base 63 drivers/clk/mxs/clk-pll.c writel_relaxed(1 << 31, pll->base + SET); base 83 drivers/clk/mxs/clk-pll.c void __iomem *base, u8 power, unsigned long rate) base 99 drivers/clk/mxs/clk-pll.c pll->base = base; base 44 drivers/clk/mxs/clk-ssp.c val = readl(ssp->base + HW_SSP_TIMING(ssp)); base 48 drivers/clk/mxs/clk-ssp.c writel(val, ssp->base + HW_SSP_TIMING(ssp)); base 22 drivers/clk/mxs/clk.h void __iomem *base, u8 power, unsigned long rate); base 535 drivers/clk/nxp/clk-lpc18xx-cgu.c void __iomem *base, int n) base 537 drivers/clk/nxp/clk-lpc18xx-cgu.c void __iomem *reg = base + LPC18XX_CGU_IDIV_CTRL(n); base 583 drivers/clk/nxp/clk-lpc18xx-cgu.c void __iomem *base) base 588 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->pll.reg = base; base 589 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->mux.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET; base 590 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->gate.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET; base 601 drivers/clk/nxp/clk-lpc18xx-cgu.c void __iomem *base) base 616 drivers/clk/nxp/clk-lpc18xx-cgu.c 0, base + LPC18XX_CGU_XTAL_OSC_CTRL, base 624 drivers/clk/nxp/clk-lpc18xx-cgu.c base); base 632 drivers/clk/nxp/clk-lpc18xx-cgu.c base, i); base 1493 drivers/clk/nxp/clk-lpc32xx.c void __iomem *base = NULL; base 1514 drivers/clk/nxp/clk-lpc32xx.c base = of_iomap(np, 0); base 1515 drivers/clk/nxp/clk-lpc32xx.c if (!base) { base 1520 drivers/clk/nxp/clk-lpc32xx.c clk_regmap = regmap_init_mmio(NULL, base, &lpc32xx_scb_regmap_config); base 1524 drivers/clk/nxp/clk-lpc32xx.c iounmap(base); base 193 drivers/clk/pistachio/clk-pistachio.c p->base + 0x200, 18, 0x1f, 0, base 73 drivers/clk/pistachio/clk-pll.c void __iomem *base; base 80 drivers/clk/pistachio/clk-pll.c return readl(pll->base + reg); base 85 drivers/clk/pistachio/clk-pll.c writel(val, pll->base + reg); base 447 drivers/clk/pistachio/clk-pll.c unsigned long flags, void __iomem *base, base 485 drivers/clk/pistachio/clk-pll.c pll->base = base; base 505 drivers/clk/pistachio/clk-pll.c 0, p->base + pll[i].reg_base, base 29 drivers/clk/pistachio/clk.c p->base = of_iomap(node, 0); base 30 drivers/clk/pistachio/clk.c if (!p->base) { base 67 drivers/clk/pistachio/clk.c p->base + gate[i].reg, gate[i].shift, base 84 drivers/clk/pistachio/clk.c p->base + mux[i].reg, mux[i].shift, base 100 drivers/clk/pistachio/clk.c 0, p->base + div[i].reg, 0, base 143 drivers/clk/pistachio/clk.h void __iomem *base; base 43 drivers/clk/qcom/a53-pll.c void __iomem *base; base 52 drivers/clk/qcom/a53-pll.c base = devm_ioremap_resource(dev, res); base 53 drivers/clk/qcom/a53-pll.c if (IS_ERR(base)) base 54 drivers/clk/qcom/a53-pll.c return PTR_ERR(base); base 56 drivers/clk/qcom/a53-pll.c regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config); base 26 drivers/clk/qcom/clk-spmi-pmic-div.c u16 base; base 55 drivers/clk/qcom/clk-spmi-pmic-div.c regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); base 68 drivers/clk/qcom/clk-spmi-pmic-div.c ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL, base 85 drivers/clk/qcom/clk-spmi-pmic-div.c regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); base 132 drivers/clk/qcom/clk-spmi-pmic-div.c regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); base 155 drivers/clk/qcom/clk-spmi-pmic-div.c ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, base 264 drivers/clk/qcom/clk-spmi-pmic-div.c clkdiv[i].base = start + i * 0x100; base 75 drivers/clk/qcom/common.c void __iomem *base; base 80 drivers/clk/qcom/common.c base = devm_ioremap_resource(dev, res); base 81 drivers/clk/qcom/common.c if (IS_ERR(base)) base 82 drivers/clk/qcom/common.c return ERR_CAST(base); base 84 drivers/clk/qcom/common.c return devm_regmap_init_mmio(dev, base, desc->config); base 317 drivers/clk/qcom/common.c void __iomem *base; base 320 drivers/clk/qcom/common.c base = devm_ioremap_resource(&pdev->dev, res); base 321 drivers/clk/qcom/common.c if (IS_ERR(base)) base 324 drivers/clk/qcom/common.c regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config); base 52 drivers/clk/qcom/hfpll.c void __iomem *base; base 66 drivers/clk/qcom/hfpll.c base = devm_ioremap_resource(dev, res); base 67 drivers/clk/qcom/hfpll.c if (IS_ERR(base)) base 68 drivers/clk/qcom/hfpll.c return PTR_ERR(base); base 70 drivers/clk/qcom/hfpll.c regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config); base 37 drivers/clk/qcom/kpss-xcc.c void __iomem *base; base 45 drivers/clk/qcom/kpss-xcc.c base = devm_ioremap_resource(&pdev->dev, res); base 46 drivers/clk/qcom/kpss-xcc.c if (IS_ERR(base)) base 47 drivers/clk/qcom/kpss-xcc.c return PTR_ERR(base); base 54 drivers/clk/qcom/kpss-xcc.c base += 0x14; base 57 drivers/clk/qcom/kpss-xcc.c base += 0x28; base 61 drivers/clk/qcom/kpss-xcc.c ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, base 113 drivers/clk/renesas/r7s9210-cpg-mssr.c void __iomem *base) base 123 drivers/clk/renesas/r7s9210-cpg-mssr.c frqcr = readl(base + CPG_FRQCR) & 0xFFF; base 161 drivers/clk/renesas/r7s9210-cpg-mssr.c struct clk **clks, void __iomem *base, base 188 drivers/clk/renesas/r7s9210-cpg-mssr.c r7s9210_update_clk_table(parent, base); base 224 drivers/clk/renesas/r8a77970-cpg-mssr.c struct clk **clks, void __iomem *base, base 241 drivers/clk/renesas/r8a77970-cpg-mssr.c return rcar_gen3_cpg_clk_register(dev, core, info, clks, base, base 251 drivers/clk/renesas/r8a77970-cpg-mssr.c base + CPG_SD0CKCR, base 135 drivers/clk/renesas/rcar-gen2-cpg.c void __iomem *base) base 151 drivers/clk/renesas/rcar-gen2-cpg.c zclk->reg = base + CPG_FRQCRC; base 152 drivers/clk/renesas/rcar-gen2-cpg.c zclk->kick_reg = base + CPG_FRQCRB; base 164 drivers/clk/renesas/rcar-gen2-cpg.c void __iomem *base) base 183 drivers/clk/renesas/rcar-gen2-cpg.c gate->reg = base + CPG_RCANCKCR; base 208 drivers/clk/renesas/rcar-gen2-cpg.c void __iomem *base) base 218 drivers/clk/renesas/rcar-gen2-cpg.c div->reg = base + CPG_ADSPCKCR; base 229 drivers/clk/renesas/rcar-gen2-cpg.c gate->reg = base + CPG_ADSPCKCR; base 275 drivers/clk/renesas/rcar-gen2-cpg.c struct clk **clks, void __iomem *base, base 307 drivers/clk/renesas/rcar-gen2-cpg.c u32 pll0cr = readl(base + CPG_PLL0CR); base 323 drivers/clk/renesas/rcar-gen2-cpg.c return cpg_z_clk_register(core->name, parent_name, base); base 330 drivers/clk/renesas/rcar-gen2-cpg.c return cpg_adsp_clk_register(core->name, parent_name, base); base 359 drivers/clk/renesas/rcar-gen2-cpg.c return cpg_rcan_clk_register(core->name, parent_name, base); base 371 drivers/clk/renesas/rcar-gen2-cpg.c base + CPG_SDCKCR, shift, 4, base 35 drivers/clk/renesas/rcar-gen2-cpg.h struct clk **clks, void __iomem *base, base 380 drivers/clk/renesas/rcar-gen3-cpg.c void __iomem *base, unsigned int offset, const char *parent_name, base 398 drivers/clk/renesas/rcar-gen3-cpg.c clock->csn.reg = base + offset; base 443 drivers/clk/renesas/rcar-gen3-cpg.c void __iomem *base, const char *parent_name, base 453 drivers/clk/renesas/rcar-gen3-cpg.c rpc->div.reg = base + CPG_RPCCKCR; base 458 drivers/clk/renesas/rcar-gen3-cpg.c rpc->gate.reg = base + CPG_RPCCKCR; base 463 drivers/clk/renesas/rcar-gen3-cpg.c rpc->csn.reg = base + CPG_RPCCKCR; base 484 drivers/clk/renesas/rcar-gen3-cpg.c void __iomem *base, base 497 drivers/clk/renesas/rcar-gen3-cpg.c rpcd2->gate.reg = base + CPG_RPCCKCR; base 543 drivers/clk/renesas/rcar-gen3-cpg.c struct clk **clks, void __iomem *base, base 567 drivers/clk/renesas/rcar-gen3-cpg.c value = readl(base + CPG_PLL0CR); base 585 drivers/clk/renesas/rcar-gen3-cpg.c value = readl(base + CPG_PLL2CR); base 603 drivers/clk/renesas/rcar-gen3-cpg.c value = readl(base + CPG_PLL4CR); base 610 drivers/clk/renesas/rcar-gen3-cpg.c return cpg_sd_clk_register(core->name, base, core->offset, base 621 drivers/clk/renesas/rcar-gen3-cpg.c csn->reg = base + CPG_RCKCR; base 662 drivers/clk/renesas/rcar-gen3-cpg.c base, core->div, core->offset); base 676 drivers/clk/renesas/rcar-gen3-cpg.c if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) { base 689 drivers/clk/renesas/rcar-gen3-cpg.c base + CPG_RPCCKCR, 3, 2, 0, base 694 drivers/clk/renesas/rcar-gen3-cpg.c return cpg_rpc_clk_register(core->name, base, base 698 drivers/clk/renesas/rcar-gen3-cpg.c return cpg_rpcd2_clk_register(core->name, base, base 71 drivers/clk/renesas/rcar-gen3-cpg.h struct clk **clks, void __iomem *base, base 30 drivers/clk/renesas/rcar-usb2-clock-sel.c void __iomem *base; base 39 drivers/clk/renesas/rcar-usb2-clock-sel.c u16 val = readw(priv->base + USB20_CLKSET0); base 45 drivers/clk/renesas/rcar-usb2-clock-sel.c writew(CLKSET0_EXTAL_ONLY, priv->base + USB20_CLKSET0); base 51 drivers/clk/renesas/rcar-usb2-clock-sel.c writew(CLKSET0_PRIVATE, priv->base + USB20_CLKSET0); base 127 drivers/clk/renesas/rcar-usb2-clock-sel.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 128 drivers/clk/renesas/rcar-usb2-clock-sel.c if (IS_ERR(priv->base)) base 129 drivers/clk/renesas/rcar-usb2-clock-sel.c return PTR_ERR(priv->base); base 130 drivers/clk/renesas/renesas-cpg-mssr.c void __iomem *base; base 181 drivers/clk/renesas/renesas-cpg-mssr.c value = readb(priv->base + STBCR(reg)); base 186 drivers/clk/renesas/renesas-cpg-mssr.c writeb(value, priv->base + STBCR(reg)); base 189 drivers/clk/renesas/renesas-cpg-mssr.c readb(priv->base + STBCR(reg)); base 190 drivers/clk/renesas/renesas-cpg-mssr.c barrier_data(priv->base + STBCR(reg)); base 192 drivers/clk/renesas/renesas-cpg-mssr.c value = readl(priv->base + SMSTPCR(reg)); base 197 drivers/clk/renesas/renesas-cpg-mssr.c writel(value, priv->base + SMSTPCR(reg)); base 206 drivers/clk/renesas/renesas-cpg-mssr.c if (!(readl(priv->base + MSTPSR(reg)) & bitmask)) base 213 drivers/clk/renesas/renesas-cpg-mssr.c priv->base + SMSTPCR(reg), bit); base 237 drivers/clk/renesas/renesas-cpg-mssr.c value = readb(priv->base + STBCR(clock->index / 32)); base 239 drivers/clk/renesas/renesas-cpg-mssr.c value = readl(priv->base + MSTPSR(clock->index / 32)); base 341 drivers/clk/renesas/renesas-cpg-mssr.c div *= (readl(priv->base + core->offset) & 0x3f) + 1; base 345 drivers/clk/renesas/renesas-cpg-mssr.c priv->base + core->offset, base 362 drivers/clk/renesas/renesas-cpg-mssr.c priv->clks, priv->base, base 580 drivers/clk/renesas/renesas-cpg-mssr.c writel(bitmask, priv->base + SRCR(reg)); base 586 drivers/clk/renesas/renesas-cpg-mssr.c writel(bitmask, priv->base + SRSTCLR(reg)); base 600 drivers/clk/renesas/renesas-cpg-mssr.c writel(bitmask, priv->base + SRCR(reg)); base 614 drivers/clk/renesas/renesas-cpg-mssr.c writel(bitmask, priv->base + SRSTCLR(reg)); base 626 drivers/clk/renesas/renesas-cpg-mssr.c return !!(readl(priv->base + SRCR(reg)) & bitmask); base 804 drivers/clk/renesas/renesas-cpg-mssr.c readl(priv->base + SMSTPCR(reg)); base 833 drivers/clk/renesas/renesas-cpg-mssr.c oldval = readb(priv->base + STBCR(reg)); base 835 drivers/clk/renesas/renesas-cpg-mssr.c oldval = readl(priv->base + SMSTPCR(reg)); base 842 drivers/clk/renesas/renesas-cpg-mssr.c writeb(newval, priv->base + STBCR(reg)); base 844 drivers/clk/renesas/renesas-cpg-mssr.c readb(priv->base + STBCR(reg)); base 845 drivers/clk/renesas/renesas-cpg-mssr.c barrier_data(priv->base + STBCR(reg)); base 848 drivers/clk/renesas/renesas-cpg-mssr.c writel(newval, priv->base + SMSTPCR(reg)); base 856 drivers/clk/renesas/renesas-cpg-mssr.c oldval = readl(priv->base + MSTPSR(reg)); base 864 drivers/clk/renesas/renesas-cpg-mssr.c priv->base + SMSTPCR(reg), oldval & mask); base 902 drivers/clk/renesas/renesas-cpg-mssr.c priv->base = of_iomap(np, 0); base 903 drivers/clk/renesas/renesas-cpg-mssr.c if (!priv->base) { base 925 drivers/clk/renesas/renesas-cpg-mssr.c if (priv->base) base 926 drivers/clk/renesas/renesas-cpg-mssr.c iounmap(priv->base); base 153 drivers/clk/renesas/renesas-cpg-mssr.h struct clk **clks, void __iomem *base, base 161 drivers/clk/rockchip/clk-half-divider.c u8 num_parents, void __iomem *base, base 182 drivers/clk/rockchip/clk-half-divider.c mux->reg = base + muxdiv_offset; base 197 drivers/clk/rockchip/clk-half-divider.c gate->reg = base + gate_offset; base 209 drivers/clk/rockchip/clk-half-divider.c div->reg = base + muxdiv_offset; base 39 drivers/clk/rockchip/clk.c void __iomem *base, base 59 drivers/clk/rockchip/clk.c mux->reg = base + muxdiv_offset; base 76 drivers/clk/rockchip/clk.c gate->reg = base + gate_offset; base 91 drivers/clk/rockchip/clk.c div->reg = base + div_offset; base 93 drivers/clk/rockchip/clk.c div->reg = base + muxdiv_offset; base 212 drivers/clk/rockchip/clk.c void __iomem *base, int muxdiv_offset, u8 div_flags, base 239 drivers/clk/rockchip/clk.c gate->reg = base + gate_offset; base 247 drivers/clk/rockchip/clk.c div->reg = base + muxdiv_offset; base 279 drivers/clk/rockchip/clk.c frac_mux->reg = base + child->muxdiv_offset; base 319 drivers/clk/rockchip/clk.c void __iomem *base, unsigned int mult, unsigned int div, base 339 drivers/clk/rockchip/clk.c gate->reg = base + gate_offset; base 365 drivers/clk/rockchip/clk.c void __iomem *base, unsigned long nr_clks) base 382 drivers/clk/rockchip/clk.c ctx->reg_base = base; base 832 drivers/clk/rockchip/clk.h void __iomem *base, unsigned long nr_clks); base 857 drivers/clk/rockchip/clk.h u8 num_parents, void __iomem *base, base 869 drivers/clk/rockchip/clk.h void __iomem *base, u8 flags); base 873 drivers/clk/rockchip/clk.h void __iomem *base, u8 flags) base 82 drivers/clk/rockchip/softrst.c void __iomem *base, u8 flags) base 93 drivers/clk/rockchip/softrst.c softrst->reg_base = base; base 137 drivers/clk/samsung/clk-cpu.c static void exynos_set_safe_div(void __iomem *base, unsigned long div, base 142 drivers/clk/samsung/clk-cpu.c div0 = readl(base + E4210_DIV_CPU0); base 144 drivers/clk/samsung/clk-cpu.c writel(div0, base + E4210_DIV_CPU0); base 145 drivers/clk/samsung/clk-cpu.c wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask); base 150 drivers/clk/samsung/clk-cpu.c struct exynos_cpuclk *cpuclk, void __iomem *base) base 175 drivers/clk/samsung/clk-cpu.c if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK) base 176 drivers/clk/samsung/clk-cpu.c div1 = readl(base + E4210_DIV_CPU1) & base 202 drivers/clk/samsung/clk-cpu.c exynos_set_safe_div(base, alt_div, alt_div_mask); base 207 drivers/clk/samsung/clk-cpu.c mux_reg = readl(base + E4210_SRC_CPU); base 208 drivers/clk/samsung/clk-cpu.c writel(mux_reg | (1 << 16), base + E4210_SRC_CPU); base 209 drivers/clk/samsung/clk-cpu.c wait_until_mux_stable(base + E4210_STAT_CPU, 16, 2); base 212 drivers/clk/samsung/clk-cpu.c writel(div0, base + E4210_DIV_CPU0); base 213 drivers/clk/samsung/clk-cpu.c wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL); base 216 drivers/clk/samsung/clk-cpu.c writel(div1, base + E4210_DIV_CPU1); base 217 drivers/clk/samsung/clk-cpu.c wait_until_divider_stable(base + E4210_DIV_STAT_CPU1, base 227 drivers/clk/samsung/clk-cpu.c struct exynos_cpuclk *cpuclk, void __iomem *base) base 246 drivers/clk/samsung/clk-cpu.c mux_reg = readl(base + E4210_SRC_CPU); base 247 drivers/clk/samsung/clk-cpu.c writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU); base 248 drivers/clk/samsung/clk-cpu.c wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1); base 255 drivers/clk/samsung/clk-cpu.c exynos_set_safe_div(base, div, div_mask); base 265 drivers/clk/samsung/clk-cpu.c static void exynos5433_set_safe_div(void __iomem *base, unsigned long div, base 270 drivers/clk/samsung/clk-cpu.c div0 = readl(base + E5433_DIV_CPU0); base 272 drivers/clk/samsung/clk-cpu.c writel(div0, base + E5433_DIV_CPU0); base 273 drivers/clk/samsung/clk-cpu.c wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask); base 278 drivers/clk/samsung/clk-cpu.c struct exynos_cpuclk *cpuclk, void __iomem *base) base 316 drivers/clk/samsung/clk-cpu.c exynos5433_set_safe_div(base, alt_div, alt_div_mask); base 321 drivers/clk/samsung/clk-cpu.c mux_reg = readl(base + E5433_MUX_SEL2); base 322 drivers/clk/samsung/clk-cpu.c writel(mux_reg | 1, base + E5433_MUX_SEL2); base 323 drivers/clk/samsung/clk-cpu.c wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2); base 326 drivers/clk/samsung/clk-cpu.c writel(div0, base + E5433_DIV_CPU0); base 327 drivers/clk/samsung/clk-cpu.c wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, DIV_MASK_ALL); base 329 drivers/clk/samsung/clk-cpu.c writel(div1, base + E5433_DIV_CPU1); base 330 drivers/clk/samsung/clk-cpu.c wait_until_divider_stable(base + E5433_DIV_STAT_CPU1, DIV_MASK_ALL); base 338 drivers/clk/samsung/clk-cpu.c struct exynos_cpuclk *cpuclk, void __iomem *base) base 347 drivers/clk/samsung/clk-cpu.c mux_reg = readl(base + E5433_MUX_SEL2); base 348 drivers/clk/samsung/clk-cpu.c writel(mux_reg & ~1, base + E5433_MUX_SEL2); base 349 drivers/clk/samsung/clk-cpu.c wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1); base 351 drivers/clk/samsung/clk-cpu.c exynos5433_set_safe_div(base, div, div_mask); base 365 drivers/clk/samsung/clk-cpu.c void __iomem *base; base 369 drivers/clk/samsung/clk-cpu.c base = cpuclk->ctrl_base; base 372 drivers/clk/samsung/clk-cpu.c err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base); base 374 drivers/clk/samsung/clk-cpu.c err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base); base 388 drivers/clk/samsung/clk-cpu.c void __iomem *base; base 392 drivers/clk/samsung/clk-cpu.c base = cpuclk->ctrl_base; base 395 drivers/clk/samsung/clk-cpu.c err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base); base 397 drivers/clk/samsung/clk-cpu.c err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base); base 20 drivers/clk/samsung/clk-exynos5-subcmu.c static void exynos5_subcmu_clk_save(void __iomem *base, base 25 drivers/clk/samsung/clk-exynos5-subcmu.c rd->save = readl(base + rd->offset); base 26 drivers/clk/samsung/clk-exynos5-subcmu.c writel((rd->save & ~rd->mask) | rd->value, base + rd->offset); base 31 drivers/clk/samsung/clk-exynos5-subcmu.c static void exynos5_subcmu_clk_restore(void __iomem *base, base 36 drivers/clk/samsung/clk-exynos5-subcmu.c writel((readl(base + rd->offset) & ~rd->mask) | rd->save, base 37 drivers/clk/samsung/clk-exynos5-subcmu.c base + rd->offset); base 1251 drivers/clk/samsung/clk-pll.c void __iomem *base) base 1386 drivers/clk/samsung/clk-pll.c pll->lock_reg = base + pll_clk->lock_offset; base 1387 drivers/clk/samsung/clk-pll.c pll->con_reg = base + pll_clk->con_offset; base 1402 drivers/clk/samsung/clk-pll.c unsigned int nr_pll, void __iomem *base) base 1407 drivers/clk/samsung/clk-pll.c _samsung_clk_register_pll(ctx, &pll_list[cnt], base); base 127 drivers/clk/samsung/clk-s3c2410-dclk.c void __iomem *base; base 178 drivers/clk/samsung/clk-s3c2410-dclk.c dclk_con = readl_relaxed(s3c24xx_dclk->base); base 186 drivers/clk/samsung/clk-s3c2410-dclk.c writel_relaxed(dclk_con, s3c24xx_dclk->base); base 222 drivers/clk/samsung/clk-s3c2410-dclk.c s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base); base 230 drivers/clk/samsung/clk-s3c2410-dclk.c writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base); base 261 drivers/clk/samsung/clk-s3c2410-dclk.c s3c24xx_dclk->base = devm_ioremap_resource(&pdev->dev, mem); base 262 drivers/clk/samsung/clk-s3c2410-dclk.c if (IS_ERR(s3c24xx_dclk->base)) base 263 drivers/clk/samsung/clk-s3c2410-dclk.c return PTR_ERR(s3c24xx_dclk->base); base 272 drivers/clk/samsung/clk-s3c2410-dclk.c s3c24xx_dclk->base, 1, 1, 0, base 277 drivers/clk/samsung/clk-s3c2410-dclk.c s3c24xx_dclk->base, 17, 1, 0, base 281 drivers/clk/samsung/clk-s3c2410-dclk.c "mux_dclk0", 0, s3c24xx_dclk->base, base 284 drivers/clk/samsung/clk-s3c2410-dclk.c "mux_dclk1", 0, s3c24xx_dclk->base, base 289 drivers/clk/samsung/clk-s3c2410-dclk.c s3c24xx_dclk->base, 0, 0, base 293 drivers/clk/samsung/clk-s3c2410-dclk.c s3c24xx_dclk->base, 16, 0, base 322 drivers/clk/samsung/clk-s3c2410.c void __iomem *base) base 325 drivers/clk/samsung/clk-s3c2410.c reg_base = base; base 206 drivers/clk/samsung/clk-s3c2412.c unsigned long ext_f, void __iomem *base) base 210 drivers/clk/samsung/clk-s3c2412.c reg_base = base; base 343 drivers/clk/samsung/clk-s3c2443.c void __iomem *base) base 347 drivers/clk/samsung/clk-s3c2443.c reg_base = base; base 393 drivers/clk/samsung/clk-s3c64xx.c void __iomem *base) base 397 drivers/clk/samsung/clk-s3c64xx.c reg_base = base; base 23 drivers/clk/samsung/clk.c void samsung_clk_save(void __iomem *base, base 28 drivers/clk/samsung/clk.c rd->value = readl(base + rd->offset); base 31 drivers/clk/samsung/clk.c void samsung_clk_restore(void __iomem *base, base 36 drivers/clk/samsung/clk.c writel(rd->value, base + rd->offset); base 58 drivers/clk/samsung/clk.c void __iomem *base, unsigned long nr_clks) base 71 drivers/clk/samsung/clk.c ctx->reg_base = base; base 317 drivers/clk/samsung/clk.h struct device_node *np, void __iomem *base, base 352 drivers/clk/samsung/clk.h unsigned int nr_clk, void __iomem *base); base 376 drivers/clk/samsung/clk.h extern void samsung_clk_save(void __iomem *base, base 379 drivers/clk/samsung/clk.h extern void samsung_clk_restore(void __iomem *base, base 176 drivers/clk/socfpga/clk-s10.c void __iomem *base = data->base; base 182 drivers/clk/socfpga/clk-s10.c clks[i].flags, base, clks[i].offset); base 197 drivers/clk/socfpga/clk-s10.c void __iomem *base = data->base; base 204 drivers/clk/socfpga/clk-s10.c clks[i].flags, base, base 224 drivers/clk/socfpga/clk-s10.c void __iomem *base = data->base; base 231 drivers/clk/socfpga/clk-s10.c clks[i].flags, base, base 253 drivers/clk/socfpga/clk-s10.c void __iomem *base = data->base; base 259 drivers/clk/socfpga/clk-s10.c clks[i].flags, base, base 280 drivers/clk/socfpga/clk-s10.c void __iomem *base; base 283 drivers/clk/socfpga/clk-s10.c base = devm_ioremap_resource(dev, res); base 284 drivers/clk/socfpga/clk-s10.c if (IS_ERR(base)) { base 286 drivers/clk/socfpga/clk-s10.c return ERR_CAST(base); base 293 drivers/clk/socfpga/clk-s10.c clk_data->base = base; base 11 drivers/clk/socfpga/stratix10-clk.h void __iomem *base; base 42 drivers/clk/sprd/common.c void __iomem *base; base 55 drivers/clk/sprd/common.c base = devm_ioremap_resource(&pdev->dev, res); base 56 drivers/clk/sprd/common.c if (IS_ERR(base)) base 57 drivers/clk/sprd/common.c return PTR_ERR(base); base 59 drivers/clk/sprd/common.c regmap = devm_regmap_init_mmio(&pdev->dev, base, base 184 drivers/clk/st/clkgen-pll.c void __iomem *base = pll->regs_base; base 194 drivers/clk/st/clkgen-pll.c ret = readl_relaxed_poll_timeout(base + field->offset, reg, base 21 drivers/clk/st/clkgen.h static inline unsigned long clkgen_read(void __iomem *base, base 24 drivers/clk/st/clkgen.h return (readl(base + field->offset) >> field->shift) & field->mask; base 28 drivers/clk/st/clkgen.h static inline void clkgen_write(void __iomem *base, struct clkgen_field *field, base 31 drivers/clk/st/clkgen.h writel((readl(base + field->offset) & base 33 drivers/clk/st/clkgen.h base + field->offset); base 28 drivers/clk/sunxi-ng/ccu_common.c addr = common->base + common->lock_reg; base 30 drivers/clk/sunxi-ng/ccu_common.c addr = common->base + common->reg; base 94 drivers/clk/sunxi-ng/ccu_common.c cclk->base = reg; base 128 drivers/clk/sunxi-ng/ccu_common.c reset->base = reg; base 27 drivers/clk/sunxi-ng/ccu_common.h void __iomem *base; base 63 drivers/clk/sunxi-ng/ccu_div.c reg = readl(cd->common.base + cd->common.reg); base 107 drivers/clk/sunxi-ng/ccu_div.c reg = readl(cd->common.base + cd->common.reg); base 111 drivers/clk/sunxi-ng/ccu_div.c cd->common.base + cd->common.reg); base 19 drivers/clk/sunxi-ng/ccu_frac.c return !(readl(common->base + common->reg) & cf->enable); base 32 drivers/clk/sunxi-ng/ccu_frac.c reg = readl(common->base + common->reg); base 33 drivers/clk/sunxi-ng/ccu_frac.c writel(reg & ~cf->enable, common->base + common->reg); base 47 drivers/clk/sunxi-ng/ccu_frac.c reg = readl(common->base + common->reg); base 48 drivers/clk/sunxi-ng/ccu_frac.c writel(reg | cf->enable, common->base + common->reg); base 75 drivers/clk/sunxi-ng/ccu_frac.c reg = readl(common->base + common->reg); base 101 drivers/clk/sunxi-ng/ccu_frac.c reg = readl(common->base + common->reg); base 103 drivers/clk/sunxi-ng/ccu_frac.c writel(reg | sel, common->base + common->reg); base 22 drivers/clk/sunxi-ng/ccu_gate.c reg = readl(common->base + common->reg); base 23 drivers/clk/sunxi-ng/ccu_gate.c writel(reg & ~gate, common->base + common->reg); base 45 drivers/clk/sunxi-ng/ccu_gate.c reg = readl(common->base + common->reg); base 46 drivers/clk/sunxi-ng/ccu_gate.c writel(reg | gate, common->base + common->reg); base 65 drivers/clk/sunxi-ng/ccu_gate.c return readl(common->base + common->reg) & gate; base 32 drivers/clk/sunxi-ng/ccu_mmc_timing.c val = readl(cm->base + cm->reg); base 37 drivers/clk/sunxi-ng/ccu_mmc_timing.c writel(val, cm->base + cm->reg); base 61 drivers/clk/sunxi-ng/ccu_mmc_timing.c return !!(readl(cm->base + cm->reg) & CCU_MMC_NEW_TIMING_MODE); base 158 drivers/clk/sunxi-ng/ccu_mp.c reg = readl(cmp->common.base + cmp->common.reg); base 209 drivers/clk/sunxi-ng/ccu_mp.c reg = readl(cmp->common.base + cmp->common.reg); base 215 drivers/clk/sunxi-ng/ccu_mp.c writel(reg, cmp->common.base + cmp->common.reg); base 271 drivers/clk/sunxi-ng/ccu_mp.c u32 val = readl(cm->base + cm->reg); base 282 drivers/clk/sunxi-ng/ccu_mp.c u32 val = readl(cm->base + cm->reg); base 308 drivers/clk/sunxi-ng/ccu_mp.c u32 val = readl(cm->base + cm->reg); base 84 drivers/clk/sunxi-ng/ccu_mult.c reg = readl(cm->common.base + cm->common.reg); base 134 drivers/clk/sunxi-ng/ccu_mult.c reg = readl(cm->common.base + cm->common.reg); base 138 drivers/clk/sunxi-ng/ccu_mult.c writel(reg, cm->common.base + cm->common.reg); base 30 drivers/clk/sunxi-ng/ccu_mux.c reg = readl(common->base + common->reg); base 162 drivers/clk/sunxi-ng/ccu_mux.c reg = readl(common->base + common->reg); base 190 drivers/clk/sunxi-ng/ccu_mux.c reg = readl(common->base + common->reg); base 192 drivers/clk/sunxi-ng/ccu_mux.c writel(reg | (index << cm->shift), common->base + common->reg); base 72 drivers/clk/sunxi-ng/ccu_nk.c reg = readl(nk->common.base + nk->common.reg); base 136 drivers/clk/sunxi-ng/ccu_nk.c reg = readl(nk->common.base + nk->common.reg); base 142 drivers/clk/sunxi-ng/ccu_nk.c writel(reg, nk->common.base + nk->common.reg); base 78 drivers/clk/sunxi-ng/ccu_nkm.c reg = readl(nkm->common.base + nkm->common.reg); base 166 drivers/clk/sunxi-ng/ccu_nkm.c reg = readl(nkm->common.base + nkm->common.reg); base 174 drivers/clk/sunxi-ng/ccu_nkm.c writel(reg, nkm->common.base + nkm->common.reg); base 98 drivers/clk/sunxi-ng/ccu_nkmp.c reg = readl(nkmp->common.base + nkmp->common.reg); base 207 drivers/clk/sunxi-ng/ccu_nkmp.c reg = readl(nkmp->common.base + nkmp->common.reg); base 215 drivers/clk/sunxi-ng/ccu_nkmp.c writel(reg, nkmp->common.base + nkmp->common.reg); base 95 drivers/clk/sunxi-ng/ccu_nm.c reg = readl(nm->common.base + nm->common.reg); base 185 drivers/clk/sunxi-ng/ccu_nm.c reg = readl(nm->common.base + nm->common.reg); base 187 drivers/clk/sunxi-ng/ccu_nm.c writel(reg, nm->common.base + nm->common.reg); base 217 drivers/clk/sunxi-ng/ccu_nm.c reg = readl(nm->common.base + nm->common.reg); base 223 drivers/clk/sunxi-ng/ccu_nm.c writel(reg, nm->common.base + nm->common.reg); base 22 drivers/clk/sunxi-ng/ccu_phase.c reg = readl(phase->common.base + phase->common.reg); base 111 drivers/clk/sunxi-ng/ccu_phase.c reg = readl(phase->common.base + phase->common.reg); base 114 drivers/clk/sunxi-ng/ccu_phase.c phase->common.base + phase->common.reg); base 23 drivers/clk/sunxi-ng/ccu_reset.c reg = readl(ccu->base + map->reg); base 24 drivers/clk/sunxi-ng/ccu_reset.c writel(reg & ~map->bit, ccu->base + map->reg); base 41 drivers/clk/sunxi-ng/ccu_reset.c reg = readl(ccu->base + map->reg); base 42 drivers/clk/sunxi-ng/ccu_reset.c writel(reg | map->bit, ccu->base + map->reg); base 69 drivers/clk/sunxi-ng/ccu_reset.c return !(map->bit & readl(ccu->base + map->reg)); base 19 drivers/clk/sunxi-ng/ccu_reset.h void __iomem *base; base 18 drivers/clk/sunxi-ng/ccu_sdm.c if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable)) base 21 drivers/clk/sunxi-ng/ccu_sdm.c return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable); base 39 drivers/clk/sunxi-ng/ccu_sdm.c common->base + sdm->tuning_reg); base 43 drivers/clk/sunxi-ng/ccu_sdm.c reg = readl(common->base + sdm->tuning_reg); base 44 drivers/clk/sunxi-ng/ccu_sdm.c writel(reg | sdm->tuning_enable, common->base + sdm->tuning_reg); base 48 drivers/clk/sunxi-ng/ccu_sdm.c reg = readl(common->base + common->reg); base 49 drivers/clk/sunxi-ng/ccu_sdm.c writel(reg | sdm->enable, common->base + common->reg); base 63 drivers/clk/sunxi-ng/ccu_sdm.c reg = readl(common->base + common->reg); base 64 drivers/clk/sunxi-ng/ccu_sdm.c writel(reg & ~sdm->enable, common->base + common->reg); base 68 drivers/clk/sunxi-ng/ccu_sdm.c reg = readl(common->base + sdm->tuning_reg); base 69 drivers/clk/sunxi-ng/ccu_sdm.c writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg); base 122 drivers/clk/sunxi-ng/ccu_sdm.c reg = readl(common->base + sdm->tuning_reg); base 264 drivers/clk/tegra/clk-dfll.c void __iomem *base; base 332 drivers/clk/tegra/clk-dfll.c return __raw_readl(td->base + offs); base 338 drivers/clk/tegra/clk-dfll.c __raw_writel(val, td->base + offs); base 1938 drivers/clk/tegra/clk-dfll.c td->base = devm_ioremap(td->dev, mem->start, resource_size(mem)); base 1939 drivers/clk/tegra/clk-dfll.c if (!td->base) { base 480 drivers/clk/tegra/clk-emc.c struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, base 494 drivers/clk/tegra/clk-emc.c tegra->clk_regs = base; base 22 drivers/clk/tegra/clk-periph-fixed.c value = readl(fixed->base + fixed->regs->enb_reg); base 24 drivers/clk/tegra/clk-periph-fixed.c value = readl(fixed->base + fixed->regs->rst_reg); base 37 drivers/clk/tegra/clk-periph-fixed.c writel(mask, fixed->base + fixed->regs->enb_set_reg); base 47 drivers/clk/tegra/clk-periph-fixed.c writel(mask, fixed->base + fixed->regs->enb_clr_reg); base 73 drivers/clk/tegra/clk-periph-fixed.c void __iomem *base, base 97 drivers/clk/tegra/clk-periph-fixed.c fixed->base = base; base 661 drivers/clk/tegra/clk-tegra210.c static inline void _pll_misc_chk_default(void __iomem *base, base 665 drivers/clk/tegra/clk-tegra210.c u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]); base 1356 drivers/clk/tegra/clk-tegra210.c u32 val, base, ndiv_new_mask; base 1375 drivers/clk/tegra/clk-tegra210.c base = readl_relaxed(clk_base + pllx->params->base_reg) & base 1377 drivers/clk/tegra/clk-tegra210.c base |= cfg->n << pllx->params->div_nmp->divn_shift; base 1378 drivers/clk/tegra/clk-tegra210.c writel_relaxed(base, clk_base + pllx->params->base_reg); base 528 drivers/clk/tegra/clk.h void __iomem *base; base 538 drivers/clk/tegra/clk.h void __iomem *base, base 808 drivers/clk/tegra/clk.h struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, base 811 drivers/clk/tegra/clk.h static inline struct clk *tegra_clk_register_emc(void __iomem *base, base 48 drivers/clk/ti/clkctrl.c void __iomem *base; base 535 drivers/clk/ti/clkctrl.c provider->base = of_iomap(node, 0); base 590 drivers/clk/ti/clkctrl.c hw->enable_reg.ptr = provider->base + reg_data->offset; base 68 drivers/clk/ti/fapll.c void __iomem *base; base 88 drivers/clk/ti/fapll.c u32 v = readl_relaxed(fd->base); base 98 drivers/clk/ti/fapll.c u32 v = readl_relaxed(fd->base); base 104 drivers/clk/ti/fapll.c writel_relaxed(v, fd->base); base 109 drivers/clk/ti/fapll.c u32 v = readl_relaxed(fd->base); base 115 drivers/clk/ti/fapll.c writel_relaxed(v, fd->base); base 123 drivers/clk/ti/fapll.c while ((v = readl_relaxed(fd->base))) { base 141 drivers/clk/ti/fapll.c u32 v = readl_relaxed(fd->base); base 144 drivers/clk/ti/fapll.c writel_relaxed(v, fd->base); base 153 drivers/clk/ti/fapll.c u32 v = readl_relaxed(fd->base); base 156 drivers/clk/ti/fapll.c writel_relaxed(v, fd->base); base 162 drivers/clk/ti/fapll.c u32 v = readl_relaxed(fd->base); base 180 drivers/clk/ti/fapll.c v = readl_relaxed(fd->base); base 260 drivers/clk/ti/fapll.c v = readl_relaxed(fd->base); base 264 drivers/clk/ti/fapll.c writel_relaxed(v, fd->base); base 285 drivers/clk/ti/fapll.c u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); base 288 drivers/clk/ti/fapll.c writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); base 296 drivers/clk/ti/fapll.c u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); base 299 drivers/clk/ti/fapll.c writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); base 305 drivers/clk/ti/fapll.c u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); base 578 drivers/clk/ti/fapll.c fd->base = of_iomap(node, 0); base 579 drivers/clk/ti/fapll.c if (!fd->base) { base 584 drivers/clk/ti/fapll.c if (fapll_is_ddr_pll(fd->base)) base 620 drivers/clk/ti/fapll.c freq = fd->base + (output_instance * 8); base 654 drivers/clk/ti/fapll.c iounmap(fd->base); base 28 drivers/clk/ux500/clk-prcc.c void __iomem *base; base 39 drivers/clk/ux500/clk-prcc.c writel(clk->cg_sel, (clk->base + PRCC_PCKEN)); base 40 drivers/clk/ux500/clk-prcc.c while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel)) base 51 drivers/clk/ux500/clk-prcc.c writel(clk->cg_sel, (clk->base + PRCC_PCKDIS)); base 59 drivers/clk/ux500/clk-prcc.c writel(clk->cg_sel, (clk->base + PRCC_KCKEN)); base 60 drivers/clk/ux500/clk-prcc.c while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel)) base 71 drivers/clk/ux500/clk-prcc.c writel(clk->cg_sel, (clk->base + PRCC_KCKDIS)); base 113 drivers/clk/ux500/clk-prcc.c clk->base = ioremap(phy_base, SZ_4K); base 114 drivers/clk/ux500/clk-prcc.c if (!clk->base) base 134 drivers/clk/ux500/clk-prcc.c iounmap(clk->base); base 22 drivers/clk/ux500/u8500_of_clk.c #define PRCC_SHOW(clk, base, bit) \ base 23 drivers/clk/ux500/u8500_of_clk.c clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] base 24 drivers/clk/ux500/u8500_of_clk.c #define PRCC_PCLK_STORE(clk, base, bit) \ base 25 drivers/clk/ux500/u8500_of_clk.c prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk base 26 drivers/clk/ux500/u8500_of_clk.c #define PRCC_KCLK_STORE(clk, base, bit) \ base 27 drivers/clk/ux500/u8500_of_clk.c prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk base 33 drivers/clk/ux500/u8500_of_clk.c unsigned int base, bit; base 38 drivers/clk/ux500/u8500_of_clk.c base = clkspec->args[0]; base 41 drivers/clk/ux500/u8500_of_clk.c if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) { base 42 drivers/clk/ux500/u8500_of_clk.c pr_err("%s: invalid PRCC base %d\n", __func__, base); base 46 drivers/clk/ux500/u8500_of_clk.c return PRCC_SHOW(clk_data, base, bit); base 394 drivers/clk/versatile/clk-icst.c void __iomem *base) base 403 drivers/clk/versatile/clk-icst.c map = regmap_init_mmio(dev, base, &icst_regmap_conf); base 19 drivers/clk/versatile/clk-icst.h void __iomem *base); base 84 drivers/clk/versatile/clk-impd1.c void integrator_impd1_clk_init(void __iomem *base, unsigned int id) base 104 drivers/clk/versatile/clk-impd1.c base); base 112 drivers/clk/versatile/clk-impd1.c base); base 30 drivers/clk/versatile/clk-sp810.c void __iomem *base; base 38 drivers/clk/versatile/clk-sp810.c u32 val = readl(timerclken->sp810->base + SCCTRL); base 55 drivers/clk/versatile/clk-sp810.c val = readl(sp810->base + SCCTRL); base 58 drivers/clk/versatile/clk-sp810.c writel(val, sp810->base + SCCTRL); base 103 drivers/clk/versatile/clk-sp810.c sp810->base = of_iomap(node, 0); base 180 drivers/clk/x86/clk-pmc-atom.c pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE; base 37 drivers/clk/x86/clk-st.c if (!st_data || !st_data->base) base 47 drivers/clk/x86/clk-st.c 0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL); base 52 drivers/clk/x86/clk-st.c 0, st_data->base + MISCCLKCNTL1, OSCCLKENB, base 228 drivers/clocksource/acpi_pm.c unsigned int base; base 231 drivers/clocksource/acpi_pm.c ret = kstrtouint(arg, 16, &base); base 236 drivers/clocksource/acpi_pm.c base); base 237 drivers/clocksource/acpi_pm.c pmtmr_ioport = base; base 57 drivers/clocksource/arm_arch_timer.c void __iomem *base; base 95 drivers/clocksource/arm_arch_timer.c writel_relaxed(val, timer->base + CNTP_CTL); base 98 drivers/clocksource/arm_arch_timer.c writel_relaxed(val, timer->base + CNTP_TVAL); base 105 drivers/clocksource/arm_arch_timer.c writel_relaxed(val, timer->base + CNTV_CTL); base 108 drivers/clocksource/arm_arch_timer.c writel_relaxed(val, timer->base + CNTV_TVAL); base 126 drivers/clocksource/arm_arch_timer.c val = readl_relaxed(timer->base + CNTP_CTL); base 129 drivers/clocksource/arm_arch_timer.c val = readl_relaxed(timer->base + CNTP_TVAL); base 136 drivers/clocksource/arm_arch_timer.c val = readl_relaxed(timer->base + CNTV_CTL); base 139 drivers/clocksource/arm_arch_timer.c val = readl_relaxed(timer->base + CNTV_TVAL); base 1134 drivers/clocksource/arm_arch_timer.c static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) base 1144 drivers/clocksource/arm_arch_timer.c t->base = base; base 1304 drivers/clocksource/arm_arch_timer.c void __iomem *base; base 1307 drivers/clocksource/arm_arch_timer.c base = ioremap(frame->cntbase, frame->size); base 1308 drivers/clocksource/arm_arch_timer.c if (!base) { base 1313 drivers/clocksource/arm_arch_timer.c rate = readl_relaxed(base + CNTFRQ); base 1315 drivers/clocksource/arm_arch_timer.c iounmap(base); base 1374 drivers/clocksource/arm_arch_timer.c void __iomem *base; base 1392 drivers/clocksource/arm_arch_timer.c base = ioremap(frame->cntbase, frame->size); base 1393 drivers/clocksource/arm_arch_timer.c if (!base) { base 1398 drivers/clocksource/arm_arch_timer.c ret = arch_timer_mem_register(base, irq); base 1400 drivers/clocksource/arm_arch_timer.c iounmap(base); base 1404 drivers/clocksource/arm_arch_timer.c arch_counter_base = base; base 28 drivers/clocksource/armv7m_systick.c void __iomem *base; base 32 drivers/clocksource/armv7m_systick.c base = of_iomap(np, 0); base 33 drivers/clocksource/armv7m_systick.c if (!base) { base 57 drivers/clocksource/armv7m_systick.c writel_relaxed(SYSTICK_LOAD_RELOAD_MASK, base + SYST_RVR); base 58 drivers/clocksource/armv7m_systick.c writel_relaxed(SYST_CSR_ENABLE, base + SYST_CSR); base 60 drivers/clocksource/armv7m_systick.c ret = clocksource_mmio_init(base + SYST_CVR, "arm_system_timer", rate, base 79 drivers/clocksource/armv7m_systick.c iounmap(base); base 105 drivers/clocksource/asm9260_timer.c void __iomem *base; base 113 drivers/clocksource/asm9260_timer.c writel_relaxed(delta, priv.base + HW_MR0); base 115 drivers/clocksource/asm9260_timer.c writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); base 122 drivers/clocksource/asm9260_timer.c writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG); base 137 drivers/clocksource/asm9260_timer.c priv.base + HW_MCR + SET_REG); base 147 drivers/clocksource/asm9260_timer.c priv.base + HW_MCR + CLR_REG); base 149 drivers/clocksource/asm9260_timer.c writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0); base 151 drivers/clocksource/asm9260_timer.c writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); base 173 drivers/clocksource/asm9260_timer.c writel_relaxed(BM_IR_MR0, priv.base + HW_IR); base 190 drivers/clocksource/asm9260_timer.c priv.base = of_io_request_and_map(np, 0, np->name); base 191 drivers/clocksource/asm9260_timer.c if (IS_ERR(priv.base)) { base 193 drivers/clocksource/asm9260_timer.c return PTR_ERR(priv.base); base 217 drivers/clocksource/asm9260_timer.c writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR); base 219 drivers/clocksource/asm9260_timer.c writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR); base 221 drivers/clocksource/asm9260_timer.c writel_relaxed(BM_CTCR_DEFAULT, priv.base + HW_CTCR); base 223 drivers/clocksource/asm9260_timer.c writel_relaxed(BM_MCR_INT_EN(0) , priv.base + HW_MCR); base 226 drivers/clocksource/asm9260_timer.c clocksource_mmio_init(priv.base + HW_TC1, DRIVER_NAME, rate, base 231 drivers/clocksource/asm9260_timer.c writel_relaxed(0xffffffff, priv.base + HW_MR1); base 233 drivers/clocksource/asm9260_timer.c writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG); base 72 drivers/clocksource/bcm2835_timer.c void __iomem *base; base 77 drivers/clocksource/bcm2835_timer.c base = of_iomap(node, 0); base 78 drivers/clocksource/bcm2835_timer.c if (!base) { base 89 drivers/clocksource/bcm2835_timer.c system_clock = base + REG_COUNTER_LO; base 92 drivers/clocksource/bcm2835_timer.c clocksource_mmio_init(base + REG_COUNTER_LO, node->name, base 108 drivers/clocksource/bcm2835_timer.c timer->control = base + REG_CONTROL; base 109 drivers/clocksource/bcm2835_timer.c timer->compare = base + REG_COMPARE(DEFAULT_TIMER); base 137 drivers/clocksource/bcm2835_timer.c iounmap(base); base 50 drivers/clocksource/bcm_kona_timer.c static void kona_timer_disable_and_clear(void __iomem *base) base 58 drivers/clocksource/bcm_kona_timer.c reg = readl(base + KONA_GPTIMER_STCS_OFFSET); base 65 drivers/clocksource/bcm_kona_timer.c writel(reg, base + KONA_GPTIMER_STCS_OFFSET); base 32 drivers/clocksource/clksrc-dbx500-prcmu.c void __iomem *base = clksrc_dbx500_timer_base; base 36 drivers/clocksource/clksrc-dbx500-prcmu.c count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); base 37 drivers/clocksource/clksrc-dbx500-prcmu.c count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); base 27 drivers/clocksource/clksrc_st_lpc.c void __iomem *base; base 32 drivers/clocksource/clksrc_st_lpc.c writel_relaxed(0, ddata.base + LPC_LPT_START_OFF); base 33 drivers/clocksource/clksrc_st_lpc.c writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF); base 34 drivers/clocksource/clksrc_st_lpc.c writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF); base 35 drivers/clocksource/clksrc_st_lpc.c writel_relaxed(1, ddata.base + LPC_LPT_START_OFF); base 40 drivers/clocksource/clksrc_st_lpc.c return (u64)readl_relaxed(ddata.base + LPC_LPT_LSB_OFF); base 54 drivers/clocksource/clksrc_st_lpc.c ret = clocksource_mmio_init(ddata.base + LPC_LPT_LSB_OFF, base 106 drivers/clocksource/clksrc_st_lpc.c ddata.base = of_iomap(np, 0); base 107 drivers/clocksource/clksrc_st_lpc.c if (!ddata.base) { base 114 drivers/clocksource/clksrc_st_lpc.c iounmap(ddata.base); base 122 drivers/clocksource/clksrc_st_lpc.c iounmap(ddata.base); base 30 drivers/clocksource/clps711x-timer.c static void __init clps711x_clksrc_init(struct clk *clock, void __iomem *base) base 34 drivers/clocksource/clps711x-timer.c tcd = base; base 51 drivers/clocksource/clps711x-timer.c static int __init _clps711x_clkevt_init(struct clk *clock, void __iomem *base, base 64 drivers/clocksource/clps711x-timer.c writew(DIV_ROUND_CLOSEST(rate, HZ), base); base 80 drivers/clocksource/clps711x-timer.c void __iomem *base = of_iomap(np, 0); base 82 drivers/clocksource/clps711x-timer.c if (!base) base 91 drivers/clocksource/clps711x-timer.c clps711x_clksrc_init(clock, base); base 94 drivers/clocksource/clps711x-timer.c return _clps711x_clkevt_init(clock, base, irq); base 51 drivers/clocksource/dw_apb_timer.c return readl(timer->base + offs); base 57 drivers/clocksource/dw_apb_timer.c writel(val, timer->base + offs); base 62 drivers/clocksource/dw_apb_timer.c return readl_relaxed(timer->base + offs); base 68 drivers/clocksource/dw_apb_timer.c writel_relaxed(val, timer->base + offs); base 241 drivers/clocksource/dw_apb_timer.c void __iomem *base, int irq, unsigned long freq) base 250 drivers/clocksource/dw_apb_timer.c dw_ced->timer.base = base; base 383 drivers/clocksource/dw_apb_timer.c dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base, base 391 drivers/clocksource/dw_apb_timer.c dw_cs->timer.base = base; base 18 drivers/clocksource/dw_apb_timer_of.c void __iomem **base, u32 *rate) base 24 drivers/clocksource/dw_apb_timer_of.c *base = of_iomap(np, 0); base 26 drivers/clocksource/dw_apb_timer_of.c if (!*base) base 26 drivers/clocksource/em_sti.c void __iomem *base; base 55 drivers/clocksource/em_sti.c return ioread32(p->base + offs); base 61 drivers/clocksource/em_sti.c iowrite32(value, p->base + offs); base 299 drivers/clocksource/em_sti.c p->base = devm_ioremap_resource(&pdev->dev, res); base 300 drivers/clocksource/em_sti.c if (IS_ERR(p->base)) base 301 drivers/clocksource/em_sti.c return PTR_ERR(p->base); base 82 drivers/clocksource/exynos_mct.c unsigned long base; base 356 drivers/clocksource/exynos_mct.c unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; base 375 drivers/clocksource/exynos_mct.c exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); base 378 drivers/clocksource/exynos_mct.c exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); base 380 drivers/clocksource/exynos_mct.c tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET); base 383 drivers/clocksource/exynos_mct.c exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); base 389 drivers/clocksource/exynos_mct.c if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) base 390 drivers/clocksource/exynos_mct.c exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); base 452 drivers/clocksource/exynos_mct.c mevt->base = EXYNOS4_MCT_L_BASE(cpu); base 466 drivers/clocksource/exynos_mct.c exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); base 494 drivers/clocksource/exynos_mct.c exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); base 501 drivers/clocksource/exynos_mct.c static int __init exynos4_timer_resources(struct device_node *np, void __iomem *base) base 516 drivers/clocksource/exynos_mct.c reg_base = base; base 132 drivers/clocksource/h8300_timer16.c void __iomem *base[2]; base 144 drivers/clocksource/h8300_timer16.c base[REG_CH] = of_iomap(node, 0); base 145 drivers/clocksource/h8300_timer16.c if (!base[REG_CH]) { base 150 drivers/clocksource/h8300_timer16.c base[REG_COMM] = of_iomap(node, 1); base 151 drivers/clocksource/h8300_timer16.c if (!base[REG_COMM]) { base 165 drivers/clocksource/h8300_timer16.c timer16_priv.mapbase = base[REG_CH]; base 166 drivers/clocksource/h8300_timer16.c timer16_priv.mapcommon = base[REG_COMM]; base 183 drivers/clocksource/h8300_timer16.c iounmap(base[REG_COMM]); base 185 drivers/clocksource/h8300_timer16.c iounmap(base[REG_CH]); base 162 drivers/clocksource/h8300_timer8.c void __iomem *base; base 173 drivers/clocksource/h8300_timer8.c base = of_iomap(node, 0); base 174 drivers/clocksource/h8300_timer8.c if (!base) { base 186 drivers/clocksource/h8300_timer8.c timer8_priv.mapbase = base; base 205 drivers/clocksource/h8300_timer8.c iounmap(base); base 125 drivers/clocksource/h8300_tpu.c void __iomem *base[2]; base 135 drivers/clocksource/h8300_tpu.c base[CH_L] = of_iomap(node, CH_L); base 136 drivers/clocksource/h8300_tpu.c if (!base[CH_L]) { base 140 drivers/clocksource/h8300_tpu.c base[CH_H] = of_iomap(node, CH_H); base 141 drivers/clocksource/h8300_tpu.c if (!base[CH_H]) { base 146 drivers/clocksource/h8300_tpu.c tpu_priv.mapbase1 = base[CH_L]; base 147 drivers/clocksource/h8300_tpu.c tpu_priv.mapbase2 = base[CH_H]; base 152 drivers/clocksource/h8300_tpu.c iounmap(base[CH_H]); base 37 drivers/clocksource/jcore-pit.c void __iomem *base; base 48 drivers/clocksource/jcore-pit.c __iomem void *base = jcore_pit_base; base 50 drivers/clocksource/jcore-pit.c seclo = readl(base + REG_SECLO); base 53 drivers/clocksource/jcore-pit.c nsec = readl(base + REG_NSEC); base 54 drivers/clocksource/jcore-pit.c seclo = readl(base + REG_SECLO); base 67 drivers/clocksource/jcore-pit.c writel(0, pit->base + REG_PITEN); base 74 drivers/clocksource/jcore-pit.c writel(delta, pit->base + REG_THROT); base 75 drivers/clocksource/jcore-pit.c writel(pit->enable_val, pit->base + REG_PITEN); base 115 drivers/clocksource/jcore-pit.c buspd = readl(pit->base + REG_BUSPD); base 221 drivers/clocksource/jcore-pit.c pit->base = of_iomap(node, cpu); base 222 drivers/clocksource/jcore-pit.c if (!pit->base) { base 49 drivers/clocksource/mmio.c int __init clocksource_mmio_init(void __iomem *base, const char *name, base 62 drivers/clocksource/mmio.c cs->reg = base; base 100 drivers/clocksource/mps2-timer.c void __iomem *base; base 125 drivers/clocksource/mps2-timer.c base = of_iomap(np, 0); base 126 drivers/clocksource/mps2-timer.c if (!base) { base 145 drivers/clocksource/mps2-timer.c ce->reg = base; base 158 drivers/clocksource/mps2-timer.c writel_relaxed(0, base + TIMER_CTRL); base 173 drivers/clocksource/mps2-timer.c iounmap(base); base 185 drivers/clocksource/mps2-timer.c void __iomem *base; base 209 drivers/clocksource/mps2-timer.c base = of_iomap(np, 0); base 210 drivers/clocksource/mps2-timer.c if (!base) { base 217 drivers/clocksource/mps2-timer.c writel_relaxed(0, base + TIMER_CTRL); base 220 drivers/clocksource/mps2-timer.c writel_relaxed(0xffffffff, base + TIMER_VALUE); base 221 drivers/clocksource/mps2-timer.c writel_relaxed(0xffffffff, base + TIMER_RELOAD); base 223 drivers/clocksource/mps2-timer.c writel_relaxed(TIMER_CTRL_ENABLE, base + TIMER_CTRL); base 225 drivers/clocksource/mps2-timer.c ret = clocksource_mmio_init(base + TIMER_VALUE, name, base 233 drivers/clocksource/mps2-timer.c sched_clock_base = base; base 239 drivers/clocksource/mps2-timer.c iounmap(base); base 191 drivers/clocksource/nomadik-mtu.c static int __init nmdk_timer_init(void __iomem *base, int irq, base 197 drivers/clocksource/nomadik-mtu.c mtu_base = base; base 251 drivers/clocksource/nomadik-mtu.c void __iomem *base; base 254 drivers/clocksource/nomadik-mtu.c base = of_iomap(node, 0); base 255 drivers/clocksource/nomadik-mtu.c if (!base) { base 278 drivers/clocksource/nomadik-mtu.c return nmdk_timer_init(base, irq, pclk, clk); base 28 drivers/clocksource/renesas-ostm.c void __iomem *base; base 57 drivers/clocksource/renesas-ostm.c if (readb(ostm->base + OSTM_TE) & TE) { base 58 drivers/clocksource/renesas-ostm.c writeb(TT, ostm->base + OSTM_TT); base 65 drivers/clocksource/renesas-ostm.c while (readb(ostm->base + OSTM_TE) & TE) base 78 drivers/clocksource/renesas-ostm.c writel(0, ostm->base + OSTM_CMP); base 79 drivers/clocksource/renesas-ostm.c writeb(CTL_FREERUN, ostm->base + OSTM_CTL); base 80 drivers/clocksource/renesas-ostm.c writeb(TS, ostm->base + OSTM_TS); base 82 drivers/clocksource/renesas-ostm.c return clocksource_mmio_init(ostm->base + OSTM_CNT, base 95 drivers/clocksource/renesas-ostm.c system_clock = ostm->base + OSTM_CNT; base 106 drivers/clocksource/renesas-ostm.c writel(delta, ostm->base + OSTM_CMP); base 107 drivers/clocksource/renesas-ostm.c writeb(CTL_ONESHOT, ostm->base + OSTM_CTL); base 108 drivers/clocksource/renesas-ostm.c writeb(TS, ostm->base + OSTM_TS); base 128 drivers/clocksource/renesas-ostm.c writel(ostm->ticks_per_jiffy - 1, ostm->base + OSTM_CMP); base 129 drivers/clocksource/renesas-ostm.c writeb(CTL_PERIODIC, ostm->base + OSTM_CTL); base 130 drivers/clocksource/renesas-ostm.c writeb(TS, ostm->base + OSTM_TS); base 198 drivers/clocksource/renesas-ostm.c ostm->base = of_iomap(np, 0); base 199 drivers/clocksource/renesas-ostm.c if (!ostm->base) { base 248 drivers/clocksource/renesas-ostm.c iounmap(ostm->base); base 64 drivers/clocksource/samsung_pwm_timer.c void __iomem *base; base 93 drivers/clocksource/samsung_pwm_timer.c reg = readl(pwm.base + REG_TCFG0); base 96 drivers/clocksource/samsung_pwm_timer.c writel(reg, pwm.base + REG_TCFG0); base 112 drivers/clocksource/samsung_pwm_timer.c reg = readl(pwm.base + REG_TCFG1); base 115 drivers/clocksource/samsung_pwm_timer.c writel(reg, pwm.base + REG_TCFG1); base 130 drivers/clocksource/samsung_pwm_timer.c tcon = readl_relaxed(pwm.base + REG_TCON); base 132 drivers/clocksource/samsung_pwm_timer.c writel_relaxed(tcon, pwm.base + REG_TCON); base 148 drivers/clocksource/samsung_pwm_timer.c tcon = readl_relaxed(pwm.base + REG_TCON); base 153 drivers/clocksource/samsung_pwm_timer.c writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel)); base 154 drivers/clocksource/samsung_pwm_timer.c writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel)); base 155 drivers/clocksource/samsung_pwm_timer.c writel_relaxed(tcon, pwm.base + REG_TCON); base 170 drivers/clocksource/samsung_pwm_timer.c tcon = readl_relaxed(pwm.base + REG_TCON); base 180 drivers/clocksource/samsung_pwm_timer.c writel_relaxed(tcon, pwm.base + REG_TCON); base 228 drivers/clocksource/samsung_pwm_timer.c writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); base 251 drivers/clocksource/samsung_pwm_timer.c writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); base 289 drivers/clocksource/samsung_pwm_timer.c writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); base 349 drivers/clocksource/samsung_pwm_timer.c pwm.source_reg = pwm.base + 0x40; base 351 drivers/clocksource/samsung_pwm_timer.c pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14; base 404 drivers/clocksource/samsung_pwm_timer.c void __init samsung_pwm_clocksource_init(void __iomem *base, base 407 drivers/clocksource/samsung_pwm_timer.c pwm.base = base; base 440 drivers/clocksource/samsung_pwm_timer.c pwm.base = of_iomap(np, 0); base 441 drivers/clocksource/samsung_pwm_timer.c if (!pwm.base) { base 77 drivers/clocksource/sh_cmt.c u32 (*read_control)(void __iomem *base, unsigned long offs); base 78 drivers/clocksource/sh_cmt.c void (*write_control)(void __iomem *base, unsigned long offs, base 82 drivers/clocksource/sh_cmt.c u32 (*read_count)(void __iomem *base, unsigned long offs); base 83 drivers/clocksource/sh_cmt.c void (*write_count)(void __iomem *base, unsigned long offs, u32 value); base 154 drivers/clocksource/sh_cmt.c static u32 sh_cmt_read16(void __iomem *base, unsigned long offs) base 156 drivers/clocksource/sh_cmt.c return ioread16(base + (offs << 1)); base 159 drivers/clocksource/sh_cmt.c static u32 sh_cmt_read32(void __iomem *base, unsigned long offs) base 161 drivers/clocksource/sh_cmt.c return ioread32(base + (offs << 2)); base 164 drivers/clocksource/sh_cmt.c static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value) base 166 drivers/clocksource/sh_cmt.c iowrite16(value, base + (offs << 1)); base 169 drivers/clocksource/sh_cmt.c static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value) base 171 drivers/clocksource/sh_cmt.c iowrite32(value, base + (offs << 2)); base 32 drivers/clocksource/sh_mtu2.c void __iomem *base; base 162 drivers/clocksource/sh_mtu2.c return ioread16(ch->base + offs); base 164 drivers/clocksource/sh_mtu2.c return ioread8(ch->base + offs); base 178 drivers/clocksource/sh_mtu2.c iowrite16(value, ch->base + offs); base 180 drivers/clocksource/sh_mtu2.c iowrite8(value, ch->base + offs); base 360 drivers/clocksource/sh_mtu2.c ch->base = mtu->mapbase + sh_mtu2_channel_offsets[index]; base 38 drivers/clocksource/sh_tmu.c void __iomem *base; base 96 drivers/clocksource/sh_tmu.c return ioread16(ch->base + offs); base 98 drivers/clocksource/sh_tmu.c return ioread32(ch->base + offs); base 118 drivers/clocksource/sh_tmu.c iowrite16(value, ch->base + offs); base 120 drivers/clocksource/sh_tmu.c iowrite32(value, ch->base + offs); base 460 drivers/clocksource/sh_tmu.c ch->base = tmu->mapbase + 4 + ch->index * 12; base 462 drivers/clocksource/sh_tmu.c ch->base = tmu->mapbase + 8 + ch->index * 12; base 71 drivers/clocksource/timer-atcpit100.c static void atcpit100_ch1_tmr0_en(void __iomem *base) base 73 drivers/clocksource/timer-atcpit100.c writel(~0, base + CH1_REL); base 74 drivers/clocksource/timer-atcpit100.c writel(APB_CLK|TMR_32, base + CH1_CTL); base 77 drivers/clocksource/timer-atcpit100.c static void atcpit100_ch0_tmr0_en(void __iomem *base) base 79 drivers/clocksource/timer-atcpit100.c writel(APB_CLK|TMR_32, base + CH0_CTL); base 82 drivers/clocksource/timer-atcpit100.c static void atcpit100_clkevt_time_setup(void __iomem *base, unsigned long delay) base 84 drivers/clocksource/timer-atcpit100.c writel(delay, base + CH0_CNT); base 85 drivers/clocksource/timer-atcpit100.c writel(delay, base + CH0_REL); base 88 drivers/clocksource/timer-atcpit100.c static void atcpit100_timer_clear_interrupt(void __iomem *base) base 92 drivers/clocksource/timer-atcpit100.c val = readl(base + INT_STA); base 93 drivers/clocksource/timer-atcpit100.c writel(val | CH0INT0, base + INT_STA); base 96 drivers/clocksource/timer-atcpit100.c static void atcpit100_clocksource_start(void __iomem *base) base 100 drivers/clocksource/timer-atcpit100.c val = readl(base + CH_EN); base 101 drivers/clocksource/timer-atcpit100.c writel(val | CH1TMR0EN, base + CH_EN); base 104 drivers/clocksource/timer-atcpit100.c static void atcpit100_clkevt_time_start(void __iomem *base) base 108 drivers/clocksource/timer-atcpit100.c val = readl(base + CH_EN); base 109 drivers/clocksource/timer-atcpit100.c writel(val | CH0TMR0EN, base + CH_EN); base 112 drivers/clocksource/timer-atcpit100.c static void atcpit100_clkevt_time_stop(void __iomem *base) base 116 drivers/clocksource/timer-atcpit100.c atcpit100_timer_clear_interrupt(base); base 117 drivers/clocksource/timer-atcpit100.c val = readl(base + CH_EN); base 118 drivers/clocksource/timer-atcpit100.c writel(val & ~CH0TMR0EN, base + CH_EN); base 225 drivers/clocksource/timer-atcpit100.c void __iomem *base; base 231 drivers/clocksource/timer-atcpit100.c base = timer_of_base(&to); base 236 drivers/clocksource/timer-atcpit100.c ret = clocksource_mmio_init(base + CH1_CNT, base 246 drivers/clocksource/timer-atcpit100.c atcpit100_timer_clear_interrupt(base); base 250 drivers/clocksource/timer-atcpit100.c atcpit100_ch0_tmr0_en(base); base 251 drivers/clocksource/timer-atcpit100.c atcpit100_ch1_tmr0_en(base); base 252 drivers/clocksource/timer-atcpit100.c atcpit100_clocksource_start(base); base 253 drivers/clocksource/timer-atcpit100.c atcpit100_clkevt_time_start(base); base 256 drivers/clocksource/timer-atcpit100.c val = readl(base + INT_EN); base 257 drivers/clocksource/timer-atcpit100.c writel(val | CH0INT0EN, base + INT_EN); base 42 drivers/clocksource/timer-atmel-pit.c void __iomem *base; base 59 drivers/clocksource/timer-atmel-pit.c static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset) base 61 drivers/clocksource/timer-atmel-pit.c return readl_relaxed(base + reg_offset); base 64 drivers/clocksource/timer-atmel-pit.c static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value) base 66 drivers/clocksource/timer-atmel-pit.c writel_relaxed(value, base + reg_offset); base 82 drivers/clocksource/timer-atmel-pit.c t = pit_read(data->base, AT91_PIT_PIIR); base 95 drivers/clocksource/timer-atmel-pit.c pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN); base 107 drivers/clocksource/timer-atmel-pit.c data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR)); base 108 drivers/clocksource/timer-atmel-pit.c pit_write(data->base, AT91_PIT_MR, base 118 drivers/clocksource/timer-atmel-pit.c pit_write(data->base, AT91_PIT_MR, 0); base 124 drivers/clocksource/timer-atmel-pit.c pit_write(data->base, AT91_PIT_MR, 0); base 127 drivers/clocksource/timer-atmel-pit.c while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0) base 131 drivers/clocksource/timer-atmel-pit.c pit_write(data->base, AT91_PIT_MR, base 151 drivers/clocksource/timer-atmel-pit.c (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) { base 153 drivers/clocksource/timer-atmel-pit.c data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, base 177 drivers/clocksource/timer-atmel-pit.c data->base = of_iomap(node, 0); base 178 drivers/clocksource/timer-atmel-pit.c if (!data->base) { base 318 drivers/clocksource/timer-cadence-ttc.c static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base, base 347 drivers/clocksource/timer-cadence-ttc.c ttccs->ttc.base_addr = base; base 371 drivers/clocksource/timer-cadence-ttc.c ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; base 402 drivers/clocksource/timer-cadence-ttc.c void __iomem *base, u32 irq) base 432 drivers/clocksource/timer-cadence-ttc.c ttcce->ttc.base_addr = base; base 53 drivers/clocksource/timer-davinci.c void __iomem *base; base 63 drivers/clocksource/timer-davinci.c void __iomem *base; base 77 drivers/clocksource/timer-davinci.c return readl_relaxed(clockevent->base + reg); base 83 drivers/clocksource/timer-davinci.c writel_relaxed(val, clockevent->base + reg); base 86 drivers/clocksource/timer-davinci.c static void davinci_tim12_shutdown(void __iomem *base) base 100 drivers/clocksource/timer-davinci.c writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); base 103 drivers/clocksource/timer-davinci.c static void davinci_tim12_set_oneshot(void __iomem *base) base 113 drivers/clocksource/timer-davinci.c writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); base 122 drivers/clocksource/timer-davinci.c davinci_tim12_shutdown(clockevent->base); base 133 drivers/clocksource/timer-davinci.c davinci_tim12_set_oneshot(clockevent->base); base 174 drivers/clocksource/timer-davinci.c davinci_tim12_shutdown(clockevent->base); base 183 drivers/clocksource/timer-davinci.c return readl_relaxed(davinci_clocksource.base + base 197 drivers/clocksource/timer-davinci.c static void davinci_clocksource_init_tim34(void __iomem *base) base 206 drivers/clocksource/timer-davinci.c writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34); base 207 drivers/clocksource/timer-davinci.c writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34); base 208 drivers/clocksource/timer-davinci.c writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); base 216 drivers/clocksource/timer-davinci.c static void davinci_clocksource_init_tim12(void __iomem *base) base 223 drivers/clocksource/timer-davinci.c writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12); base 224 drivers/clocksource/timer-davinci.c writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12); base 225 drivers/clocksource/timer-davinci.c writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); base 228 drivers/clocksource/timer-davinci.c static void davinci_timer_init(void __iomem *base) base 231 drivers/clocksource/timer-davinci.c writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR); base 237 drivers/clocksource/timer-davinci.c base + DAVINCI_TIMER_REG_TGCR); base 239 drivers/clocksource/timer-davinci.c writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12); base 240 drivers/clocksource/timer-davinci.c writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34); base 248 drivers/clocksource/timer-davinci.c void __iomem *base; base 264 drivers/clocksource/timer-davinci.c base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg)); base 265 drivers/clocksource/timer-davinci.c if (!base) { base 270 drivers/clocksource/timer-davinci.c davinci_timer_init(base); base 282 drivers/clocksource/timer-davinci.c clockevent->base = base; base 310 drivers/clocksource/timer-davinci.c davinci_clocksource.base = base; base 315 drivers/clocksource/timer-davinci.c davinci_clocksource_init_tim12(base); base 319 drivers/clocksource/timer-davinci.c davinci_clocksource_init_tim34(base); base 62 drivers/clocksource/timer-digicolor.c void __iomem *base; base 75 drivers/clocksource/timer-digicolor.c writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id)); base 81 drivers/clocksource/timer-digicolor.c writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id)); base 88 drivers/clocksource/timer-digicolor.c writel(count, dt->base + COUNT(dt->timer_id)); base 149 drivers/clocksource/timer-digicolor.c return ~readl(dc_timer_dev.base + COUNT(TIMER_B)); base 162 drivers/clocksource/timer-digicolor.c dc_timer_dev.base = of_iomap(node, 0); base 163 drivers/clocksource/timer-digicolor.c if (!dc_timer_dev.base) { base 183 drivers/clocksource/timer-digicolor.c writeb(CONTROL_DISABLE, dc_timer_dev.base + CONTROL(TIMER_B)); base 184 drivers/clocksource/timer-digicolor.c writel(UINT_MAX, dc_timer_dev.base + COUNT(TIMER_B)); base 185 drivers/clocksource/timer-digicolor.c writeb(CONTROL_ENABLE, dc_timer_dev.base + CONTROL(TIMER_B)); base 188 drivers/clocksource/timer-digicolor.c clocksource_mmio_init(dc_timer_dev.base + COUNT(TIMER_B), node->name, base 44 drivers/clocksource/timer-efm32.c void __iomem *base; base 53 drivers/clocksource/timer-efm32.c writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); base 62 drivers/clocksource/timer-efm32.c writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); base 67 drivers/clocksource/timer-efm32.c ddata->base + TIMERn_CTRL); base 76 drivers/clocksource/timer-efm32.c writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); base 77 drivers/clocksource/timer-efm32.c writel_relaxed(ddata->periodic_top, ddata->base + TIMERn_TOP); base 81 drivers/clocksource/timer-efm32.c ddata->base + TIMERn_CTRL); base 82 drivers/clocksource/timer-efm32.c writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); base 92 drivers/clocksource/timer-efm32.c writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); base 93 drivers/clocksource/timer-efm32.c writel_relaxed(evt, ddata->base + TIMERn_CNT); base 94 drivers/clocksource/timer-efm32.c writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); base 103 drivers/clocksource/timer-efm32.c writel_relaxed(TIMERn_IRQ_UF, ddata->base + TIMERn_IFC); base 132 drivers/clocksource/timer-efm32.c void __iomem *base; base 151 drivers/clocksource/timer-efm32.c base = of_iomap(np, 0); base 152 drivers/clocksource/timer-efm32.c if (!base) { base 160 drivers/clocksource/timer-efm32.c TIMERn_CTRL_MODE_UP, base + TIMERn_CTRL); base 161 drivers/clocksource/timer-efm32.c writel_relaxed(TIMERn_CMD_START, base + TIMERn_CMD); base 163 drivers/clocksource/timer-efm32.c ret = clocksource_mmio_init(base + TIMERn_CNT, "efm32 timer", base 175 drivers/clocksource/timer-efm32.c iounmap(base); base 190 drivers/clocksource/timer-efm32.c void __iomem *base; base 210 drivers/clocksource/timer-efm32.c base = of_iomap(np, 0); base 211 drivers/clocksource/timer-efm32.c if (!base) { base 224 drivers/clocksource/timer-efm32.c writel_relaxed(TIMERn_IRQ_UF, base + TIMERn_IEN); base 226 drivers/clocksource/timer-efm32.c clock_event_ddata.base = base; base 244 drivers/clocksource/timer-efm32.c iounmap(base); base 48 drivers/clocksource/timer-fsl-ftm.c static inline void ftm_counter_enable(void __iomem *base) base 53 drivers/clocksource/timer-fsl-ftm.c val = ftm_readl(base + FTM_SC); base 56 drivers/clocksource/timer-fsl-ftm.c ftm_writel(val, base + FTM_SC); base 59 drivers/clocksource/timer-fsl-ftm.c static inline void ftm_counter_disable(void __iomem *base) base 64 drivers/clocksource/timer-fsl-ftm.c val = ftm_readl(base + FTM_SC); base 66 drivers/clocksource/timer-fsl-ftm.c ftm_writel(val, base + FTM_SC); base 69 drivers/clocksource/timer-fsl-ftm.c static inline void ftm_irq_acknowledge(void __iomem *base) base 73 drivers/clocksource/timer-fsl-ftm.c val = ftm_readl(base + FTM_SC); base 75 drivers/clocksource/timer-fsl-ftm.c ftm_writel(val, base + FTM_SC); base 78 drivers/clocksource/timer-fsl-ftm.c static inline void ftm_irq_enable(void __iomem *base) base 82 drivers/clocksource/timer-fsl-ftm.c val = ftm_readl(base + FTM_SC); base 84 drivers/clocksource/timer-fsl-ftm.c ftm_writel(val, base + FTM_SC); base 87 drivers/clocksource/timer-fsl-ftm.c static inline void ftm_irq_disable(void __iomem *base) base 91 drivers/clocksource/timer-fsl-ftm.c val = ftm_readl(base + FTM_SC); base 93 drivers/clocksource/timer-fsl-ftm.c ftm_writel(val, base + FTM_SC); base 96 drivers/clocksource/timer-fsl-ftm.c static inline void ftm_reset_counter(void __iomem *base) base 103 drivers/clocksource/timer-fsl-ftm.c ftm_writel(0x00, base + FTM_CNT); base 95 drivers/clocksource/timer-fttmr010.c void __iomem *base; base 118 drivers/clocksource/timer-fttmr010.c return readl(local_fttmr->base + TIMER2_COUNT); base 123 drivers/clocksource/timer-fttmr010.c return ~readl(local_fttmr->base + TIMER2_COUNT); base 143 drivers/clocksource/timer-fttmr010.c cr = readl(fttmr010->base + TIMER_CR); base 145 drivers/clocksource/timer-fttmr010.c writel(cr, fttmr010->base + TIMER_CR); base 152 drivers/clocksource/timer-fttmr010.c writel(cycles, fttmr010->base + TIMER1_LOAD); base 155 drivers/clocksource/timer-fttmr010.c cr = readl(fttmr010->base + TIMER1_COUNT); base 156 drivers/clocksource/timer-fttmr010.c writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); base 160 drivers/clocksource/timer-fttmr010.c cr = readl(fttmr010->base + TIMER_CR); base 162 drivers/clocksource/timer-fttmr010.c writel(cr, fttmr010->base + TIMER_CR); base 173 drivers/clocksource/timer-fttmr010.c cr = readl(fttmr010->base + TIMER_CR); base 175 drivers/clocksource/timer-fttmr010.c writel(cr, fttmr010->base + TIMER_CR); base 186 drivers/clocksource/timer-fttmr010.c cr = readl(fttmr010->base + TIMER_CR); base 188 drivers/clocksource/timer-fttmr010.c writel(cr, fttmr010->base + TIMER_CR); base 191 drivers/clocksource/timer-fttmr010.c writel(0, fttmr010->base + TIMER1_COUNT); base 193 drivers/clocksource/timer-fttmr010.c writel(~0, fttmr010->base + TIMER1_LOAD); base 195 drivers/clocksource/timer-fttmr010.c writel(0, fttmr010->base + TIMER1_LOAD); base 198 drivers/clocksource/timer-fttmr010.c cr = readl(fttmr010->base + TIMER_INTR_MASK); base 201 drivers/clocksource/timer-fttmr010.c writel(cr, fttmr010->base + TIMER_INTR_MASK); base 214 drivers/clocksource/timer-fttmr010.c cr = readl(fttmr010->base + TIMER_CR); base 216 drivers/clocksource/timer-fttmr010.c writel(cr, fttmr010->base + TIMER_CR); base 220 drivers/clocksource/timer-fttmr010.c writel(period, fttmr010->base + TIMER1_LOAD); base 223 drivers/clocksource/timer-fttmr010.c writel(cr, fttmr010->base + TIMER1_COUNT); base 224 drivers/clocksource/timer-fttmr010.c writel(cr, fttmr010->base + TIMER1_LOAD); base 227 drivers/clocksource/timer-fttmr010.c cr = readl(fttmr010->base + TIMER_INTR_MASK); base 230 drivers/clocksource/timer-fttmr010.c writel(cr, fttmr010->base + TIMER_INTR_MASK); base 234 drivers/clocksource/timer-fttmr010.c cr = readl(fttmr010->base + TIMER_CR); base 236 drivers/clocksource/timer-fttmr010.c writel(cr, fttmr010->base + TIMER_CR); base 283 drivers/clocksource/timer-fttmr010.c fttmr010->base = of_iomap(np, 0); base 284 drivers/clocksource/timer-fttmr010.c if (!fttmr010->base) { base 310 drivers/clocksource/timer-fttmr010.c writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); base 311 drivers/clocksource/timer-fttmr010.c writel(0, fttmr010->base + TIMER_INTR_STATE); base 324 drivers/clocksource/timer-fttmr010.c writel(val, fttmr010->base + TIMER_CR); base 331 drivers/clocksource/timer-fttmr010.c writel(0, fttmr010->base + TIMER2_COUNT); base 332 drivers/clocksource/timer-fttmr010.c writel(0, fttmr010->base + TIMER2_MATCH1); base 333 drivers/clocksource/timer-fttmr010.c writel(0, fttmr010->base + TIMER2_MATCH2); base 336 drivers/clocksource/timer-fttmr010.c writel(~0, fttmr010->base + TIMER2_LOAD); base 337 drivers/clocksource/timer-fttmr010.c clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, base 344 drivers/clocksource/timer-fttmr010.c writel(0, fttmr010->base + TIMER2_LOAD); base 345 drivers/clocksource/timer-fttmr010.c clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, base 356 drivers/clocksource/timer-fttmr010.c writel(0, fttmr010->base + TIMER1_COUNT); base 357 drivers/clocksource/timer-fttmr010.c writel(0, fttmr010->base + TIMER1_LOAD); base 358 drivers/clocksource/timer-fttmr010.c writel(0, fttmr010->base + TIMER1_MATCH1); base 359 drivers/clocksource/timer-fttmr010.c writel(0, fttmr010->base + TIMER1_MATCH2); base 398 drivers/clocksource/timer-fttmr010.c iounmap(fttmr010->base); base 28 drivers/clocksource/timer-gx6605s.c void __iomem *base = timer_of_base(to_timer_of(ce)); base 30 drivers/clocksource/timer-gx6605s.c writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS); base 39 drivers/clocksource/timer-gx6605s.c void __iomem *base = timer_of_base(to_timer_of(ce)); base 42 drivers/clocksource/timer-gx6605s.c writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); base 46 drivers/clocksource/timer-gx6605s.c base + TIMER_CONFIG); base 54 drivers/clocksource/timer-gx6605s.c void __iomem *base = timer_of_base(to_timer_of(ce)); base 57 drivers/clocksource/timer-gx6605s.c writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); base 60 drivers/clocksource/timer-gx6605s.c writel_relaxed(ULONG_MAX - delta, base + TIMER_INI); base 61 drivers/clocksource/timer-gx6605s.c writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL); base 68 drivers/clocksource/timer-gx6605s.c void __iomem *base = timer_of_base(to_timer_of(ce)); base 70 drivers/clocksource/timer-gx6605s.c writel_relaxed(0, base + TIMER_CONTRL); base 71 drivers/clocksource/timer-gx6605s.c writel_relaxed(0, base + TIMER_CONFIG); base 95 drivers/clocksource/timer-gx6605s.c void __iomem *base; base 97 drivers/clocksource/timer-gx6605s.c base = timer_of_base(&to) + CLKSRC_OFFSET; base 99 drivers/clocksource/timer-gx6605s.c return (u64)readl_relaxed(base + TIMER_VALUE); base 102 drivers/clocksource/timer-gx6605s.c static void gx6605s_clkevt_init(void __iomem *base) base 104 drivers/clocksource/timer-gx6605s.c writel_relaxed(0, base + TIMER_DIV); base 105 drivers/clocksource/timer-gx6605s.c writel_relaxed(0, base + TIMER_CONFIG); base 111 drivers/clocksource/timer-gx6605s.c static int gx6605s_clksrc_init(void __iomem *base) base 113 drivers/clocksource/timer-gx6605s.c writel_relaxed(0, base + TIMER_DIV); base 114 drivers/clocksource/timer-gx6605s.c writel_relaxed(0, base + TIMER_INI); base 116 drivers/clocksource/timer-gx6605s.c writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); base 118 drivers/clocksource/timer-gx6605s.c writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG); base 120 drivers/clocksource/timer-gx6605s.c writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL); base 124 drivers/clocksource/timer-gx6605s.c return clocksource_mmio_init(base + TIMER_VALUE, "gx6605s", base 64 drivers/clocksource/timer-imx-gpt.c void __iomem *base; base 94 drivers/clocksource/timer-imx-gpt.c tmp = readl_relaxed(imxtm->base + MXC_TCTL); base 95 drivers/clocksource/timer-imx-gpt.c writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); base 101 drivers/clocksource/timer-imx-gpt.c writel_relaxed(0, imxtm->base + V2_IR); base 109 drivers/clocksource/timer-imx-gpt.c tmp = readl_relaxed(imxtm->base + MXC_TCTL); base 110 drivers/clocksource/timer-imx-gpt.c writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); base 116 drivers/clocksource/timer-imx-gpt.c writel_relaxed(1<<0, imxtm->base + V2_IR); base 122 drivers/clocksource/timer-imx-gpt.c writel_relaxed(0, imxtm->base + MX1_2_TSTAT); base 128 drivers/clocksource/timer-imx-gpt.c imxtm->base + MX1_2_TSTAT); base 133 drivers/clocksource/timer-imx-gpt.c writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); base 156 drivers/clocksource/timer-imx-gpt.c void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; base 179 drivers/clocksource/timer-imx-gpt.c tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt; base 181 drivers/clocksource/timer-imx-gpt.c writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP); base 183 drivers/clocksource/timer-imx-gpt.c return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ? base 193 drivers/clocksource/timer-imx-gpt.c tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt; base 195 drivers/clocksource/timer-imx-gpt.c writel_relaxed(tcmp, imxtm->base + V2_TCMP); base 198 drivers/clocksource/timer-imx-gpt.c (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ? base 210 drivers/clocksource/timer-imx-gpt.c tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); base 212 drivers/clocksource/timer-imx-gpt.c writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); base 232 drivers/clocksource/timer-imx-gpt.c u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); base 234 drivers/clocksource/timer-imx-gpt.c writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); base 264 drivers/clocksource/timer-imx-gpt.c tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat); base 303 drivers/clocksource/timer-imx-gpt.c writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); base 317 drivers/clocksource/timer-imx-gpt.c writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); base 328 drivers/clocksource/timer-imx-gpt.c writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER); base 334 drivers/clocksource/timer-imx-gpt.c writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); base 416 drivers/clocksource/timer-imx-gpt.c writel_relaxed(0, imxtm->base + MXC_TCTL); base 417 drivers/clocksource/timer-imx-gpt.c writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */ base 439 drivers/clocksource/timer-imx-gpt.c imxtm->base = ioremap(pbase, SZ_4K); base 440 drivers/clocksource/timer-imx-gpt.c BUG_ON(!imxtm->base); base 462 drivers/clocksource/timer-imx-gpt.c imxtm->base = of_iomap(np, 0); base 463 drivers/clocksource/timer-imx-gpt.c if (!imxtm->base) base 27 drivers/clocksource/timer-integrator-ap.c void __iomem *base) base 38 drivers/clocksource/timer-integrator-ap.c writel(0xffff, base + TIMER_LOAD); base 39 drivers/clocksource/timer-integrator-ap.c writel(ctrl, base + TIMER_CTRL); base 41 drivers/clocksource/timer-integrator-ap.c ret = clocksource_mmio_init(base + TIMER_VALUE, "timer2", base 46 drivers/clocksource/timer-integrator-ap.c sched_clk_base = base; base 134 drivers/clocksource/timer-integrator-ap.c void __iomem *base, int irq) base 140 drivers/clocksource/timer-integrator-ap.c clkevt_base = base; base 166 drivers/clocksource/timer-integrator-ap.c void __iomem *base; base 173 drivers/clocksource/timer-integrator-ap.c base = of_io_request_and_map(node, 0, "integrator-timer"); base 174 drivers/clocksource/timer-integrator-ap.c if (IS_ERR(base)) base 175 drivers/clocksource/timer-integrator-ap.c return PTR_ERR(base); base 184 drivers/clocksource/timer-integrator-ap.c writel(0, base + TIMER_CTRL); base 204 drivers/clocksource/timer-integrator-ap.c return integrator_clocksource_init(rate, base); base 220 drivers/clocksource/timer-integrator-ap.c return integrator_clockevent_init(rate, base, irq); base 223 drivers/clocksource/timer-integrator-ap.c pr_info("Timer @%p unused\n", base); base 57 drivers/clocksource/timer-ixp4xx.c void __iomem *base; base 80 drivers/clocksource/timer-ixp4xx.c return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET); base 100 drivers/clocksource/timer-ixp4xx.c tmr->base + IXP4XX_OSST_OFFSET); base 113 drivers/clocksource/timer-ixp4xx.c val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); base 117 drivers/clocksource/timer-ixp4xx.c tmr->base + IXP4XX_OSRT1_OFFSET); base 127 drivers/clocksource/timer-ixp4xx.c val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); base 129 drivers/clocksource/timer-ixp4xx.c __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); base 139 drivers/clocksource/timer-ixp4xx.c tmr->base + IXP4XX_OSRT1_OFFSET); base 151 drivers/clocksource/timer-ixp4xx.c __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); base 161 drivers/clocksource/timer-ixp4xx.c val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); base 163 drivers/clocksource/timer-ixp4xx.c __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); base 173 drivers/clocksource/timer-ixp4xx.c static __init int ixp4xx_timer_register(void __iomem *base, base 183 drivers/clocksource/timer-ixp4xx.c tmr->base = base; base 199 drivers/clocksource/timer-ixp4xx.c __raw_writel(0, tmr->base + IXP4XX_OSRT1_OFFSET); base 203 drivers/clocksource/timer-ixp4xx.c tmr->base + IXP4XX_OSST_OFFSET); base 206 drivers/clocksource/timer-ixp4xx.c __raw_writel(0, tmr->base + IXP4XX_OSTS_OFFSET); base 252 drivers/clocksource/timer-ixp4xx.c void __iomem *base; base 254 drivers/clocksource/timer-ixp4xx.c base = ioremap(timerbase, 0x100); base 255 drivers/clocksource/timer-ixp4xx.c if (!base) { base 259 drivers/clocksource/timer-ixp4xx.c ixp4xx_timer_register(base, timer_irq, timer_freq); base 266 drivers/clocksource/timer-ixp4xx.c void __iomem *base; base 270 drivers/clocksource/timer-ixp4xx.c base = of_iomap(np, 0); base 271 drivers/clocksource/timer-ixp4xx.c if (!base) { base 284 drivers/clocksource/timer-ixp4xx.c ret = ixp4xx_timer_register(base, irq, 66666000); base 290 drivers/clocksource/timer-ixp4xx.c iounmap(base); base 43 drivers/clocksource/timer-keystone.c void __iomem *base; base 50 drivers/clocksource/timer-keystone.c return readl_relaxed(timer.base + rg); base 55 drivers/clocksource/timer-keystone.c writel_relaxed(val, timer.base + rg); base 156 drivers/clocksource/timer-keystone.c timer.base = of_iomap(np, 0); base 157 drivers/clocksource/timer-keystone.c if (!timer.base) { base 165 drivers/clocksource/timer-keystone.c iounmap(timer.base); base 221 drivers/clocksource/timer-keystone.c iounmap(timer.base); base 46 drivers/clocksource/timer-lpc32xx.c void __iomem *base; base 79 drivers/clocksource/timer-lpc32xx.c writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); base 80 drivers/clocksource/timer-lpc32xx.c writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0); base 81 drivers/clocksource/timer-lpc32xx.c writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); base 92 drivers/clocksource/timer-lpc32xx.c writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); base 106 drivers/clocksource/timer-lpc32xx.c writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); base 110 drivers/clocksource/timer-lpc32xx.c LPC32XX_TIMER_MCR_MR0S, ddata->base + LPC32XX_TIMER_MCR); base 121 drivers/clocksource/timer-lpc32xx.c ddata->base + LPC32XX_TIMER_MCR); base 127 drivers/clocksource/timer-lpc32xx.c writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); base 128 drivers/clocksource/timer-lpc32xx.c writel_relaxed(ddata->ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0); base 129 drivers/clocksource/timer-lpc32xx.c writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); base 139 drivers/clocksource/timer-lpc32xx.c writel_relaxed(LPC32XX_TIMER_IR_MR0INT, ddata->base + LPC32XX_TIMER_IR); base 161 drivers/clocksource/timer-lpc32xx.c void __iomem *base; base 178 drivers/clocksource/timer-lpc32xx.c base = of_iomap(np, 0); base 179 drivers/clocksource/timer-lpc32xx.c if (!base) { base 190 drivers/clocksource/timer-lpc32xx.c writel_relaxed(LPC32XX_TIMER_TCR_CRST, base + LPC32XX_TIMER_TCR); base 191 drivers/clocksource/timer-lpc32xx.c writel_relaxed(0, base + LPC32XX_TIMER_PR); base 192 drivers/clocksource/timer-lpc32xx.c writel_relaxed(0, base + LPC32XX_TIMER_MCR); base 193 drivers/clocksource/timer-lpc32xx.c writel_relaxed(0, base + LPC32XX_TIMER_CTCR); base 194 drivers/clocksource/timer-lpc32xx.c writel_relaxed(LPC32XX_TIMER_TCR_CEN, base + LPC32XX_TIMER_TCR); base 197 drivers/clocksource/timer-lpc32xx.c ret = clocksource_mmio_init(base + LPC32XX_TIMER_TC, "lpc3220 timer", base 204 drivers/clocksource/timer-lpc32xx.c clocksource_timer_counter = base + LPC32XX_TIMER_TC; base 212 drivers/clocksource/timer-lpc32xx.c iounmap(base); base 222 drivers/clocksource/timer-lpc32xx.c void __iomem *base; base 239 drivers/clocksource/timer-lpc32xx.c base = of_iomap(np, 0); base 240 drivers/clocksource/timer-lpc32xx.c if (!base) { base 257 drivers/clocksource/timer-lpc32xx.c writel_relaxed(0, base + LPC32XX_TIMER_TCR); base 258 drivers/clocksource/timer-lpc32xx.c writel_relaxed(0, base + LPC32XX_TIMER_PR); base 259 drivers/clocksource/timer-lpc32xx.c writel_relaxed(0, base + LPC32XX_TIMER_CTCR); base 260 drivers/clocksource/timer-lpc32xx.c writel_relaxed(LPC32XX_TIMER_IR_MR0INT, base + LPC32XX_TIMER_IR); base 263 drivers/clocksource/timer-lpc32xx.c lpc32xx_clk_event_ddata.base = base; base 279 drivers/clocksource/timer-lpc32xx.c iounmap(base); base 151 drivers/clocksource/timer-of.c iounmap(of_base->base); base 157 drivers/clocksource/timer-of.c of_base->base = of_base->name ? base 160 drivers/clocksource/timer-of.c if (IS_ERR(of_base->base)) { base 162 drivers/clocksource/timer-of.c return PTR_ERR(of_base->base); base 21 drivers/clocksource/timer-of.h void __iomem *base; base 51 drivers/clocksource/timer-of.h return to->of_base.base; base 34 drivers/clocksource/timer-owl.c static inline void owl_timer_reset(void __iomem *base) base 36 drivers/clocksource/timer-owl.c writel(0, base + OWL_Tx_CTL); base 37 drivers/clocksource/timer-owl.c writel(0, base + OWL_Tx_VAL); base 38 drivers/clocksource/timer-owl.c writel(0, base + OWL_Tx_CMP); base 41 drivers/clocksource/timer-owl.c static inline void owl_timer_set_enabled(void __iomem *base, bool enabled) base 43 drivers/clocksource/timer-owl.c u32 ctl = readl(base + OWL_Tx_CTL); base 53 drivers/clocksource/timer-owl.c writel(ctl, base + OWL_Tx_CTL); base 83 drivers/clocksource/timer-owl.c void __iomem *base = owl_clkevt_base; base 85 drivers/clocksource/timer-owl.c owl_timer_set_enabled(base, false); base 86 drivers/clocksource/timer-owl.c writel(OWL_Tx_CTL_INTEN, base + OWL_Tx_CTL); base 87 drivers/clocksource/timer-owl.c writel(0, base + OWL_Tx_VAL); base 88 drivers/clocksource/timer-owl.c writel(evt, base + OWL_Tx_CMP); base 89 drivers/clocksource/timer-owl.c owl_timer_set_enabled(base, true); base 215 drivers/clocksource/timer-oxnas-rps.c void __iomem *base; base 232 drivers/clocksource/timer-oxnas-rps.c base = of_iomap(np, 0); base 233 drivers/clocksource/timer-oxnas-rps.c if (!base) { base 244 drivers/clocksource/timer-oxnas-rps.c rps->clkevt_base = base + TIMER1_REG_OFFSET; base 245 drivers/clocksource/timer-oxnas-rps.c rps->clksrc_base = base + TIMER2_REG_OFFSET; base 274 drivers/clocksource/timer-oxnas-rps.c iounmap(base); base 49 drivers/clocksource/timer-pistachio.c void __iomem *base; base 59 drivers/clocksource/timer-pistachio.c static inline u32 gpt_readl(void __iomem *base, u32 offset, u32 gpt_id) base 61 drivers/clocksource/timer-pistachio.c return readl(base + 0x20 * gpt_id + offset); base 64 drivers/clocksource/timer-pistachio.c static inline void gpt_writel(void __iomem *base, u32 value, u32 offset, base 67 drivers/clocksource/timer-pistachio.c writel(value, base + 0x20 * gpt_id + offset); base 83 drivers/clocksource/timer-pistachio.c overflw = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); base 84 drivers/clocksource/timer-pistachio.c counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); base 101 drivers/clocksource/timer-pistachio.c val = gpt_readl(pcs->base, TIMER_CFG, timeridx); base 107 drivers/clocksource/timer-pistachio.c gpt_writel(pcs->base, val, TIMER_CFG, timeridx); base 116 drivers/clocksource/timer-pistachio.c gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx); base 158 drivers/clocksource/timer-pistachio.c pcs_gpt.base = of_iomap(node, 0); base 159 drivers/clocksource/timer-pistachio.c if (!pcs_gpt.base) { base 205 drivers/clocksource/timer-pistachio.c gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 0); base 206 drivers/clocksource/timer-pistachio.c gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 1); base 207 drivers/clocksource/timer-pistachio.c gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 2); base 208 drivers/clocksource/timer-pistachio.c gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 3); base 211 drivers/clocksource/timer-pistachio.c writel(TIMER_ME_GLOBAL, pcs_gpt.base); base 221 drivers/clocksource/timer-pxa.c void __init pxa_timer_nodt_init(int irq, void __iomem *base) base 225 drivers/clocksource/timer-pxa.c timer_base = base; base 203 drivers/clocksource/timer-qcom.c void __iomem *base; base 206 drivers/clocksource/timer-qcom.c base = of_iomap(np, 0); base 207 drivers/clocksource/timer-qcom.c if (!base) { base 240 drivers/clocksource/timer-qcom.c event_base = base + 0x4; base 241 drivers/clocksource/timer-qcom.c sts_base = base + 0x88; base 35 drivers/clocksource/timer-rda.c static int rda_ostimer_start(void __iomem *base, bool periodic, u64 cycles) base 47 drivers/clocksource/timer-rda.c base + RDA_TIMER_IRQ_MASK_SET); base 50 drivers/clocksource/timer-rda.c writel_relaxed(load_l, base + RDA_OSTIMER_LOADVAL_L); base 51 drivers/clocksource/timer-rda.c writel_relaxed(ctrl, base + RDA_OSTIMER_CTRL); base 56 drivers/clocksource/timer-rda.c static int rda_ostimer_stop(void __iomem *base) base 60 drivers/clocksource/timer-rda.c base + RDA_TIMER_IRQ_MASK_CLR); base 62 drivers/clocksource/timer-rda.c writel_relaxed(0, base + RDA_OSTIMER_CTRL); base 158 drivers/clocksource/timer-rda.c void __iomem *base = timer_of_base(&rda_ostimer_of); base 163 drivers/clocksource/timer-rda.c lo = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_L); base 164 drivers/clocksource/timer-rda.c hi = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H); base 165 drivers/clocksource/timer-rda.c } while (hi != readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H)); base 34 drivers/clocksource/timer-rockchip.c void __iomem *base; base 68 drivers/clocksource/timer-rockchip.c writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0); base 69 drivers/clocksource/timer-rockchip.c writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1); base 74 drivers/clocksource/timer-rockchip.c writel_relaxed(1, timer->base + TIMER_INT_STATUS); base 124 drivers/clocksource/timer-rockchip.c return ~readl_relaxed(rk_clksrc->base + TIMER_CURRENT_VALUE0); base 135 drivers/clocksource/timer-rockchip.c timer->base = of_iomap(np, 0); base 136 drivers/clocksource/timer-rockchip.c if (!timer->base) { base 144 drivers/clocksource/timer-rockchip.c timer->ctrl = timer->base + ctrl_reg; base 193 drivers/clocksource/timer-rockchip.c iounmap(timer->base); base 202 drivers/clocksource/timer-rockchip.c iounmap(timer->base); base 270 drivers/clocksource/timer-rockchip.c ret = clocksource_mmio_init(rk_clksrc->base + TIMER_CURRENT_VALUE0, base 63 drivers/clocksource/timer-sp804.c void __init sp804_timer_disable(void __iomem *base) base 65 drivers/clocksource/timer-sp804.c writel(0, base + TIMER_CTRL); base 68 drivers/clocksource/timer-sp804.c int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, base 89 drivers/clocksource/timer-sp804.c writel(0, base + TIMER_CTRL); base 90 drivers/clocksource/timer-sp804.c writel(0xffffffff, base + TIMER_LOAD); base 91 drivers/clocksource/timer-sp804.c writel(0xffffffff, base + TIMER_VALUE); base 93 drivers/clocksource/timer-sp804.c base + TIMER_CTRL); base 95 drivers/clocksource/timer-sp804.c clocksource_mmio_init(base + TIMER_VALUE, name, base 99 drivers/clocksource/timer-sp804.c sched_clock_base = base; base 178 drivers/clocksource/timer-sp804.c int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) base 195 drivers/clocksource/timer-sp804.c clkevt_base = base; base 201 drivers/clocksource/timer-sp804.c writel(0, base + TIMER_CTRL); base 212 drivers/clocksource/timer-sp804.c void __iomem *base; base 218 drivers/clocksource/timer-sp804.c base = of_iomap(np, 0); base 219 drivers/clocksource/timer-sp804.c if (!base) base 223 drivers/clocksource/timer-sp804.c writel(0, base + TIMER_CTRL); base 224 drivers/clocksource/timer-sp804.c writel(0, base + TIMER_2_BASE + TIMER_CTRL); base 253 drivers/clocksource/timer-sp804.c ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); base 257 drivers/clocksource/timer-sp804.c ret = __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1); base 262 drivers/clocksource/timer-sp804.c ret = __sp804_clockevents_init(base, irq, clk1 , name); base 266 drivers/clocksource/timer-sp804.c ret =__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, base 275 drivers/clocksource/timer-sp804.c iounmap(base); base 283 drivers/clocksource/timer-sp804.c void __iomem *base; base 288 drivers/clocksource/timer-sp804.c base = of_iomap(np, 0); base 289 drivers/clocksource/timer-sp804.c if (!base) { base 301 drivers/clocksource/timer-sp804.c writel(0, base + TIMER_CTRL); base 307 drivers/clocksource/timer-sp804.c ret = __sp804_clocksource_and_sched_clock_init(base, name, clk, 0); base 315 drivers/clocksource/timer-sp804.c ret = __sp804_clockevents_init(base, irq, clk, name); base 323 drivers/clocksource/timer-sp804.c iounmap(base); base 34 drivers/clocksource/timer-sprd.c static void sprd_timer_enable(void __iomem *base, u32 flag) base 36 drivers/clocksource/timer-sprd.c u32 val = readl_relaxed(base + TIMER_CTL); base 49 drivers/clocksource/timer-sprd.c writel_relaxed(val, base + TIMER_CTL); base 52 drivers/clocksource/timer-sprd.c static void sprd_timer_disable(void __iomem *base) base 54 drivers/clocksource/timer-sprd.c u32 val = readl_relaxed(base + TIMER_CTL); base 57 drivers/clocksource/timer-sprd.c writel_relaxed(val, base + TIMER_CTL); base 60 drivers/clocksource/timer-sprd.c static void sprd_timer_update_counter(void __iomem *base, unsigned long cycles) base 62 drivers/clocksource/timer-sprd.c writel_relaxed(cycles & TIMER_VALUE_LO_MASK, base + TIMER_LOAD_LO); base 63 drivers/clocksource/timer-sprd.c writel_relaxed(0, base + TIMER_LOAD_HI); base 66 drivers/clocksource/timer-sprd.c static void sprd_timer_enable_interrupt(void __iomem *base) base 68 drivers/clocksource/timer-sprd.c writel_relaxed(TIMER_INT_EN, base + TIMER_INT); base 71 drivers/clocksource/timer-sprd.c static void sprd_timer_clear_interrupt(void __iomem *base) base 73 drivers/clocksource/timer-sprd.c u32 val = readl_relaxed(base + TIMER_INT); base 76 drivers/clocksource/timer-sprd.c writel_relaxed(val, base + TIMER_INT); base 50 drivers/clocksource/timer-sun4i.c static void sun4i_clkevt_sync(void __iomem *base) base 52 drivers/clocksource/timer-sun4i.c u32 old = readl(base + TIMER_CNTVAL_REG(1)); base 54 drivers/clocksource/timer-sun4i.c while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS) base 58 drivers/clocksource/timer-sun4i.c static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer) base 60 drivers/clocksource/timer-sun4i.c u32 val = readl(base + TIMER_CTL_REG(timer)); base 61 drivers/clocksource/timer-sun4i.c writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer)); base 62 drivers/clocksource/timer-sun4i.c sun4i_clkevt_sync(base); base 65 drivers/clocksource/timer-sun4i.c static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer, base 68 drivers/clocksource/timer-sun4i.c writel(delay, base + TIMER_INTVAL_REG(timer)); base 71 drivers/clocksource/timer-sun4i.c static void sun4i_clkevt_time_start(void __iomem *base, u8 timer, base 74 drivers/clocksource/timer-sun4i.c u32 val = readl(base + TIMER_CTL_REG(timer)); base 82 drivers/clocksource/timer-sun4i.c base + TIMER_CTL_REG(timer)); base 127 drivers/clocksource/timer-sun4i.c static void sun4i_timer_clear_interrupt(void __iomem *base) base 129 drivers/clocksource/timer-sun4i.c writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG); base 42 drivers/clocksource/timer-sun5i.c void __iomem *base; base 75 drivers/clocksource/timer-sun5i.c u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1)); base 77 drivers/clocksource/timer-sun5i.c while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) base 83 drivers/clocksource/timer-sun5i.c u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); base 84 drivers/clocksource/timer-sun5i.c writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer)); base 91 drivers/clocksource/timer-sun5i.c writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer)); base 96 drivers/clocksource/timer-sun5i.c u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); base 104 drivers/clocksource/timer-sun5i.c ce->timer.base + TIMER_CTL_REG(timer)); base 150 drivers/clocksource/timer-sun5i.c writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG); base 160 drivers/clocksource/timer-sun5i.c return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1)); base 187 drivers/clocksource/timer-sun5i.c void __iomem *base, base 211 drivers/clocksource/timer-sun5i.c cs->timer.base = base; base 222 drivers/clocksource/timer-sun5i.c writel(~0, base + TIMER_INTVAL_LO_REG(1)); base 224 drivers/clocksource/timer-sun5i.c base + TIMER_CTL_REG(1)); base 264 drivers/clocksource/timer-sun5i.c static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base, base 289 drivers/clocksource/timer-sun5i.c ce->timer.base = base; base 313 drivers/clocksource/timer-sun5i.c val = readl(base + TIMER_IRQ_EN_REG); base 314 drivers/clocksource/timer-sun5i.c writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG); base 305 drivers/clocksource/timer-tegra.c unsigned int base = tegra_base_for_cpu(cpu, tegra20); base 318 drivers/clocksource/timer-tegra.c cpu_to->of_base.base = timer_reg_base + base; base 366 drivers/clocksource/timer-tegra.c to->of_base.base = timer_reg_base; base 47 drivers/clocksource/timer-ti-32k.c void __iomem *base; base 83 drivers/clocksource/timer-ti-32k.c ti_32k_timer.base = of_iomap(np, 0); base 84 drivers/clocksource/timer-ti-32k.c if (!ti_32k_timer.base) { base 92 drivers/clocksource/timer-ti-32k.c ti_32k_timer.counter = ti_32k_timer.base; base 101 drivers/clocksource/timer-ti-32k.c if (readl_relaxed(ti_32k_timer.base + OMAP2_32KSYNCNT_REV_OFF) & base 23 drivers/clocksource/timer-versatile.c void __iomem *base = of_iomap(node, 0); base 25 drivers/clocksource/timer-versatile.c if (!base) base 28 drivers/clocksource/timer-versatile.c versatile_sys_24mhz = base + SYS_24MHZ; base 50 drivers/clocksource/timer-zevio.c void __iomem *base; base 127 drivers/clocksource/timer-zevio.c timer->base = of_iomap(node, 0); base 128 drivers/clocksource/timer-zevio.c if (!timer->base) { base 132 drivers/clocksource/timer-zevio.c timer->timer1 = timer->base + IO_TIMER1; base 133 drivers/clocksource/timer-zevio.c timer->timer2 = timer->base + IO_TIMER2; base 173 drivers/clocksource/timer-zevio.c writel(0, timer->base + IO_MATCH(TIMER_MATCH)); base 203 drivers/clocksource/timer-zevio.c iounmap(timer->base); base 24 drivers/counter/104-quad-8.c static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)]; base 26 drivers/counter/104-quad-8.c module_param_array(base, uint, &num_quad8, 0); base 27 drivers/counter/104-quad-8.c MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses"); base 55 drivers/counter/104-quad-8.c unsigned int base; base 99 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel; base 108 drivers/counter/104-quad-8.c *val = !!(inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) base 148 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel; base 260 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel; base 303 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base 339 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base 359 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base 382 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base 424 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base 471 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base 523 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * chan->channel + 1; base 627 drivers/counter/104-quad-8.c state = inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) base 641 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id; base 675 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id; base 769 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * id + 1; base 822 drivers/counter/104-quad-8.c const unsigned int flag_addr = priv->base + 2 * count->id + 1; base 930 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * channel_id + 1; base 970 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * channel_id + 1; base 1036 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id + 1; base 1102 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id; base 1129 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id + 1; base 1153 drivers/counter/104-quad-8.c const unsigned int base_offset = quad8iio->base + 2 * id; base 1253 drivers/counter/104-quad-8.c const int base_offset = priv->base + 2 * count->id + 1; base 1415 drivers/counter/104-quad-8.c if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) { base 1417 drivers/counter/104-quad-8.c base[id], base[id] + QUAD8_EXTENT); base 1444 drivers/counter/104-quad-8.c quad8iio->base = base[id]; base 1450 drivers/counter/104-quad-8.c outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP); base 1453 drivers/counter/104-quad-8.c base_offset = base[id] + 2 * i; base 1471 drivers/counter/104-quad-8.c outb(QUAD8_CHAN_OP_ENABLE_COUNTERS, base[id] + QUAD8_REG_CHAN_OP); base 122 drivers/cpufreq/armada-37xx-cpufreq.c static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, base 161 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, val); base 206 drivers/cpufreq/armada-37xx-cpufreq.c static void __init armada37xx_cpufreq_avs_configure(struct regmap *base, base 213 drivers/cpufreq/armada-37xx-cpufreq.c if (base == NULL) base 217 drivers/cpufreq/armada-37xx-cpufreq.c regmap_read(base, ARMADA_37XX_AVS_CTL0, &l0_vdd_min); base 257 drivers/cpufreq/armada-37xx-cpufreq.c static void __init armada37xx_cpufreq_avs_setup(struct regmap *base, base 263 drivers/cpufreq/armada-37xx-cpufreq.c if (base == NULL) base 267 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, ARMADA_37XX_AVS_CTL0, base 272 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, ARMADA_37XX_AVS_CTL2, base 279 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1), base 287 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, ARMADA_37XX_AVS_CTL0, base 293 drivers/cpufreq/armada-37xx-cpufreq.c static void armada37xx_cpufreq_disable_dvfs(struct regmap *base) base 298 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, 0); base 301 drivers/cpufreq/armada-37xx-cpufreq.c static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base) base 308 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, val); base 316 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, mask); base 175 drivers/cpufreq/brcmstb-avs-cpufreq.c void __iomem *base; base 202 drivers/cpufreq/brcmstb-avs-cpufreq.c void __iomem *base = priv->base; base 217 drivers/cpufreq/brcmstb-avs-cpufreq.c val = readl(base + AVS_MBOX_COMMAND); base 226 drivers/cpufreq/brcmstb-avs-cpufreq.c writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS); base 231 drivers/cpufreq/brcmstb-avs-cpufreq.c writel(args[i], base + AVS_MBOX_PARAM(i)); base 238 drivers/cpufreq/brcmstb-avs-cpufreq.c writel(cmd, base + AVS_MBOX_COMMAND); base 249 drivers/cpufreq/brcmstb-avs-cpufreq.c val = readl(base + AVS_MBOX_STATUS); base 262 drivers/cpufreq/brcmstb-avs-cpufreq.c args[i] = readl(base + AVS_MBOX_PARAM(i)); base 266 drivers/cpufreq/brcmstb-avs-cpufreq.c writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS); base 387 drivers/cpufreq/brcmstb-avs-cpufreq.c static u32 brcm_avs_get_voltage(void __iomem *base) base 389 drivers/cpufreq/brcmstb-avs-cpufreq.c return readl(base + AVS_MBOX_VOLTAGE1); base 392 drivers/cpufreq/brcmstb-avs-cpufreq.c static u32 brcm_avs_get_frequency(void __iomem *base) base 394 drivers/cpufreq/brcmstb-avs-cpufreq.c return readl(base + AVS_MBOX_FREQUENCY) * 1000; /* in kHz */ base 422 drivers/cpufreq/brcmstb-avs-cpufreq.c table[i].frequency = brcm_avs_get_frequency(priv->base); base 447 drivers/cpufreq/brcmstb-avs-cpufreq.c magic = readl(priv->base + AVS_MBOX_MAGIC); base 458 drivers/cpufreq/brcmstb-avs-cpufreq.c return brcm_avs_get_frequency(priv->base); base 524 drivers/cpufreq/brcmstb-avs-cpufreq.c priv->base = __map_region(BRCM_AVS_CPU_DATA); base 525 drivers/cpufreq/brcmstb-avs-cpufreq.c if (!priv->base) { base 564 drivers/cpufreq/brcmstb-avs-cpufreq.c iounmap(priv->base); base 656 drivers/cpufreq/brcmstb-avs-cpufreq.c return sprintf(buf, "0x%08x\n", brcm_avs_get_voltage(priv->base)); base 663 drivers/cpufreq/brcmstb-avs-cpufreq.c return sprintf(buf, "0x%08x\n", brcm_avs_get_frequency(priv->base)); base 717 drivers/cpufreq/brcmstb-avs-cpufreq.c iounmap(priv->base); base 222 drivers/cpufreq/imx6q-cpufreq.c void __iomem *base; base 229 drivers/cpufreq/imx6q-cpufreq.c base = of_iomap(np, 0); base 230 drivers/cpufreq/imx6q-cpufreq.c if (!base) { base 243 drivers/cpufreq/imx6q-cpufreq.c val = readl_relaxed(base + OCOTP_CFG3); base 260 drivers/cpufreq/imx6q-cpufreq.c iounmap(base); base 280 drivers/cpufreq/imx6q-cpufreq.c void __iomem *base; base 289 drivers/cpufreq/imx6q-cpufreq.c base = of_iomap(np, 0); base 291 drivers/cpufreq/imx6q-cpufreq.c if (!base) { base 296 drivers/cpufreq/imx6q-cpufreq.c val = readl_relaxed(base + OCOTP_CFG3); base 297 drivers/cpufreq/imx6q-cpufreq.c iounmap(base); base 25 drivers/cpufreq/kirkwood-cpufreq.c void __iomem *base; base 59 drivers/cpufreq/kirkwood-cpufreq.c reg = readl_relaxed(priv.base); base 61 drivers/cpufreq/kirkwood-cpufreq.c writel_relaxed(reg, priv.base); base 76 drivers/cpufreq/kirkwood-cpufreq.c reg = readl_relaxed(priv.base); base 78 drivers/cpufreq/kirkwood-cpufreq.c writel_relaxed(reg, priv.base); base 111 drivers/cpufreq/kirkwood-cpufreq.c priv.base = devm_ioremap_resource(&pdev->dev, res); base 112 drivers/cpufreq/kirkwood-cpufreq.c if (IS_ERR(priv.base)) base 113 drivers/cpufreq/kirkwood-cpufreq.c return PTR_ERR(priv.base); base 828 drivers/cpufreq/powernv-cpufreq.c int base, i; base 832 drivers/cpufreq/powernv-cpufreq.c base = cpu_first_thread_sibling(policy->cpu); base 835 drivers/cpufreq/powernv-cpufreq.c cpumask_set_cpu(base + i, policy->cpus); base 87 drivers/cpufreq/qcom-cpufreq-hw.c void __iomem *base) base 98 drivers/cpufreq/qcom-cpufreq-hw.c data = readl_relaxed(base + REG_FREQ_LUT + base 104 drivers/cpufreq/qcom-cpufreq-hw.c data = readl_relaxed(base + REG_VOLT_LUT + base 182 drivers/cpufreq/qcom-cpufreq-hw.c void __iomem *base; base 208 drivers/cpufreq/qcom-cpufreq-hw.c base = devm_ioremap(dev, res->start, resource_size(res)); base 209 drivers/cpufreq/qcom-cpufreq-hw.c if (!base) base 213 drivers/cpufreq/qcom-cpufreq-hw.c if (!(readl_relaxed(base + REG_ENABLE) & 0x1)) { base 226 drivers/cpufreq/qcom-cpufreq-hw.c policy->driver_data = base + REG_PERF_STATE; base 228 drivers/cpufreq/qcom-cpufreq-hw.c ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, base); base 247 drivers/cpufreq/qcom-cpufreq-hw.c devm_iounmap(dev, base); base 254 drivers/cpufreq/qcom-cpufreq-hw.c void __iomem *base = policy->driver_data - REG_PERF_STATE; base 258 drivers/cpufreq/qcom-cpufreq-hw.c devm_iounmap(&global_pdev->dev, base); base 83 drivers/crypto/amcc/crypto4xx_alg.c return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst, base 235 drivers/crypto/amcc/crypto4xx_alg.c return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst, base 250 drivers/crypto/amcc/crypto4xx_alg.c return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst, base 276 drivers/crypto/amcc/crypto4xx_alg.c skcipher_request_set_callback(subreq, req->base.flags, base 368 drivers/crypto/amcc/crypto4xx_alg.c aead_request_set_callback(subreq, req->base.flags, base 369 drivers/crypto/amcc/crypto4xx_alg.c req->base.complete, req->base.data); base 462 drivers/crypto/amcc/crypto4xx_alg.c struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 487 drivers/crypto/amcc/crypto4xx_alg.c return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst, base 611 drivers/crypto/amcc/crypto4xx_alg.c struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 625 drivers/crypto/amcc/crypto4xx_alg.c return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst, base 689 drivers/crypto/amcc/crypto4xx_alg.c struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 695 drivers/crypto/amcc/crypto4xx_alg.c __crypto_ahash_cast(req->base.tfm)); base 705 drivers/crypto/amcc/crypto4xx_alg.c struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 711 drivers/crypto/amcc/crypto4xx_alg.c return crypto4xx_build_pd(&req->base, ctx, req->src, &dst, base 724 drivers/crypto/amcc/crypto4xx_alg.c struct crypto4xx_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 730 drivers/crypto/amcc/crypto4xx_alg.c return crypto4xx_build_pd(&req->base, ctx, req->src, &dst, base 559 drivers/crypto/amcc/crypto4xx_core.c ctx = crypto_tfm_ctx(ahash_req->base.tfm); base 562 drivers/crypto/amcc/crypto4xx_core.c crypto_tfm_ctx(ahash_req->base.tfm)); base 575 drivers/crypto/amcc/crypto4xx_core.c struct aead_request, base); base 950 drivers/crypto/amcc/crypto4xx_core.c if (alg->base.cra_flags & CRYPTO_ALG_NEED_FALLBACK) { base 952 drivers/crypto/amcc/crypto4xx_core.c crypto_alloc_sync_skcipher(alg->base.cra_name, 0, base 983 drivers/crypto/amcc/crypto4xx_core.c ctx->sw_cipher.aead = crypto_alloc_aead(alg->base.cra_name, 0, base 1194 drivers/crypto/amcc/crypto4xx_core.c .base = { base 1214 drivers/crypto/amcc/crypto4xx_core.c .base = { base 1234 drivers/crypto/amcc/crypto4xx_core.c .base = { base 1255 drivers/crypto/amcc/crypto4xx_core.c .base = { base 1275 drivers/crypto/amcc/crypto4xx_core.c .base = { base 1294 drivers/crypto/amcc/crypto4xx_core.c .base = { base 1324 drivers/crypto/amcc/crypto4xx_core.c .base = { base 1345 drivers/crypto/amcc/crypto4xx_core.c .base = { base 1358 drivers/crypto/amcc/crypto4xx_core.c .base = { base 113 drivers/crypto/atmel-aes.c struct atmel_aes_base_ctx base; base 117 drivers/crypto/atmel-aes.c struct atmel_aes_base_ctx base; base 126 drivers/crypto/atmel-aes.c struct atmel_aes_base_ctx base; base 142 drivers/crypto/atmel-aes.c struct atmel_aes_base_ctx base; base 149 drivers/crypto/atmel-aes.c struct atmel_aes_base_ctx base; base 161 drivers/crypto/atmel-aes.c struct atmel_aes_reqctx base; base 1007 drivers/crypto/atmel-aes.c return container_of(ctx, struct atmel_aes_ctr_ctx, base); base 1131 drivers/crypto/atmel-aes.c return atmel_aes_handle_queue(dd, &req->base); base 1247 drivers/crypto/atmel-aes.c ctx->base.start = atmel_aes_start; base 1257 drivers/crypto/atmel-aes.c ctx->base.start = atmel_aes_ctr_start; base 1466 drivers/crypto/atmel-aes.c return container_of(ctx, struct atmel_aes_gcm_ctx, base); base 1761 drivers/crypto/atmel-aes.c return atmel_aes_handle_queue(dd, &req->base); base 1817 drivers/crypto/atmel-aes.c ctx->base.start = atmel_aes_gcm_start; base 1831 drivers/crypto/atmel-aes.c .base = { base 1849 drivers/crypto/atmel-aes.c return container_of(ctx, struct atmel_aes_xts_ctx, base); base 1873 drivers/crypto/atmel-aes.c ctx->key2, ctx->base.keylen); base 1925 drivers/crypto/atmel-aes.c memcpy(ctx->base.key, key, keylen/2); base 1927 drivers/crypto/atmel-aes.c ctx->base.keylen = keylen/2; base 1947 drivers/crypto/atmel-aes.c ctx->base.start = atmel_aes_xts_start; base 2003 drivers/crypto/atmel-aes.c atmel_aes_set_mode(dd, &rctx->base); base 2129 drivers/crypto/atmel-aes.c if (keys.enckeylen > sizeof(ctx->base.key)) base 2144 drivers/crypto/atmel-aes.c ctx->base.keylen = keys.enckeylen; base 2145 drivers/crypto/atmel-aes.c memcpy(ctx->base.key, keys.enckey, keys.enckeylen); base 2168 drivers/crypto/atmel-aes.c ctx->base.start = atmel_aes_authenc_start; base 2228 drivers/crypto/atmel-aes.c rctx->base.mode = mode; base 2236 drivers/crypto/atmel-aes.c return atmel_aes_handle_queue(dd, &req->base); base 2259 drivers/crypto/atmel-aes.c .base = { base 2279 drivers/crypto/atmel-aes.c .base = { base 2299 drivers/crypto/atmel-aes.c .base = { base 2319 drivers/crypto/atmel-aes.c .base = { base 2339 drivers/crypto/atmel-aes.c .base = { base 195 drivers/crypto/atmel-ecc.c gfp = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? GFP_KERNEL : base 316 drivers/crypto/atmel-ecc.c .base = { base 350 drivers/crypto/atmel-ecc.c atmel_ecdh.base.cra_driver_name); base 293 drivers/crypto/atmel-sha.c if ((dd->is_async || dd->force_complete) && req->base.complete) base 294 drivers/crypto/atmel-sha.c req->base.complete(&req->base, err); base 1150 drivers/crypto/atmel-sha.c struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm); base 1263 drivers/crypto/atmel-sha.c .base = { base 1287 drivers/crypto/atmel-sha.c .base = { base 1313 drivers/crypto/atmel-sha.c .base = { base 1339 drivers/crypto/atmel-sha.c .base = { base 1363 drivers/crypto/atmel-sha.c .base = { base 1728 drivers/crypto/atmel-sha.c struct atmel_sha_ctx base; base 2069 drivers/crypto/atmel-sha.c hmac->base.start = atmel_sha_hmac_start; base 2094 drivers/crypto/atmel-sha.c .base = { base 2119 drivers/crypto/atmel-sha.c .base = { base 2144 drivers/crypto/atmel-sha.c .base = { base 2169 drivers/crypto/atmel-sha.c .base = { base 2194 drivers/crypto/atmel-sha.c .base = { base 2223 drivers/crypto/atmel-sha.c struct atmel_sha_reqctx base; base 2244 drivers/crypto/atmel-sha.c authctx->cb(authctx->aes_dev, err, authctx->base.dd->is_async); base 2366 drivers/crypto/atmel-sha.c struct atmel_sha_reqctx *ctx = &authctx->base; base 2398 drivers/crypto/atmel-sha.c struct atmel_sha_reqctx *ctx = &authctx->base; base 2412 drivers/crypto/atmel-sha.c ctx->flags = hmac->base.flags; base 2421 drivers/crypto/atmel-sha.c struct atmel_sha_reqctx *ctx = &authctx->base; base 2468 drivers/crypto/atmel-sha.c struct atmel_sha_reqctx *ctx = &authctx->base; base 2521 drivers/crypto/atmel-sha.c struct atmel_sha_reqctx *ctx = &authctx->base; base 582 drivers/crypto/atmel-tdes.c req->base.complete(&req->base, err); base 259 drivers/crypto/axis/artpec6_crypto.c void __iomem *base; base 482 drivers/crypto/axis/artpec6_crypto.c void __iomem *base = ac->base; base 499 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(ind, base + A6_PDMA_IN_DESCRQ_PUSH); base 500 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(statd, base + A6_PDMA_IN_STATQ_PUSH); base 501 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(PDMA_IN_CMD_START, base + A6_PDMA_IN_CMD); base 503 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(ind, base + A7_PDMA_IN_DESCRQ_PUSH); base 504 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(statd, base + A7_PDMA_IN_STATQ_PUSH); base 505 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(PDMA_IN_CMD_START, base + A7_PDMA_IN_CMD); base 508 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(outd, base + PDMA_OUT_DESCRQ_PUSH); base 509 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(PDMA_OUT_CMD_START, base + PDMA_OUT_CMD); base 783 drivers/crypto/axis/artpec6_crypto.c void *base; base 791 drivers/crypto/axis/artpec6_crypto.c base = bbuf + 1; base 792 drivers/crypto/axis/artpec6_crypto.c bbuf->buf = PTR_ALIGN(base, ARTPEC_CACHE_LINE_MAX); base 1115 drivers/crypto/axis/artpec6_crypto.c &req->base, base 1160 drivers/crypto/axis/artpec6_crypto.c ret = artpec6_crypto_common_init(&req_ctx->common, &req->base, base 1207 drivers/crypto/axis/artpec6_crypto.c skcipher_request_set_callback(subreq, req->base.flags, base 1250 drivers/crypto/axis/artpec6_crypto.c struct artpec6_cryptotfm_context *ctx = crypto_tfm_ctx(&tfm->base); base 1269 drivers/crypto/axis/artpec6_crypto.c ret = artpec6_crypto_common_init(&req_ctx->common, &req->base, base 1294 drivers/crypto/axis/artpec6_crypto.c &req->base, base 1311 drivers/crypto/axis/artpec6_crypto.c struct artpec6_hashalg_context *ctx = crypto_tfm_ctx(areq->base.tfm); base 1550 drivers/crypto/axis/artpec6_crypto.c crypto_alloc_sync_skcipher(crypto_tfm_alg_name(&tfm->base), base 1627 drivers/crypto/axis/artpec6_crypto.c ret = xts_check_key(&cipher->base, key, keylen); base 1837 drivers/crypto/axis/artpec6_crypto.c struct artpec6_cryptotfm_context *ctx = crypto_tfm_ctx(areq->base.tfm); base 2164 drivers/crypto/axis/artpec6_crypto.c struct skcipher_request, base); base 2176 drivers/crypto/axis/artpec6_crypto.c struct skcipher_request, base); base 2190 drivers/crypto/axis/artpec6_crypto.c struct aead_request, base); base 2233 drivers/crypto/axis/artpec6_crypto.c struct artpec6_hashalg_context *tfm_ctx = crypto_tfm_ctx(&tfm->base); base 2307 drivers/crypto/axis/artpec6_crypto.c &req->base, base 2499 drivers/crypto/axis/artpec6_crypto.c void __iomem *base = ac->base; base 2536 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(out, base + PDMA_OUT_BUF_CFG); base 2537 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(PDMA_OUT_CFG_EN, base + PDMA_OUT_CFG); base 2540 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(in, base + A6_PDMA_IN_BUF_CFG); base 2541 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(PDMA_IN_CFG_EN, base + A6_PDMA_IN_CFG); base 2544 drivers/crypto/axis/artpec6_crypto.c base + A6_PDMA_INTR_MASK); base 2546 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(in, base + A7_PDMA_IN_BUF_CFG); base 2547 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(PDMA_IN_CFG_EN, base + A7_PDMA_IN_CFG); base 2550 drivers/crypto/axis/artpec6_crypto.c base + A7_PDMA_INTR_MASK); base 2559 drivers/crypto/axis/artpec6_crypto.c void __iomem *base = ac->base; base 2562 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(A6_PDMA_IN_CMD_STOP, base + A6_PDMA_IN_CMD); base 2563 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(0, base + A6_PDMA_IN_CFG); base 2564 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(A6_PDMA_OUT_CMD_STOP, base + PDMA_OUT_CMD); base 2566 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(A7_PDMA_IN_CMD_STOP, base + A7_PDMA_IN_CMD); base 2567 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(0, base + A7_PDMA_IN_CFG); base 2568 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(A7_PDMA_OUT_CMD_STOP, base + PDMA_OUT_CMD); base 2571 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(0, base + PDMA_OUT_CFG); base 2579 drivers/crypto/axis/artpec6_crypto.c void __iomem *base = ac->base; base 2587 drivers/crypto/axis/artpec6_crypto.c intr = readl_relaxed(base + A6_PDMA_MASKED_INTR); base 2594 drivers/crypto/axis/artpec6_crypto.c intr = readl_relaxed(base + A7_PDMA_MASKED_INTR); base 2615 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(in_cmd_flush_stat, base + in_cmd_reg); base 2617 drivers/crypto/axis/artpec6_crypto.c writel_relaxed(ack, base + ack_intr_reg); base 2639 drivers/crypto/axis/artpec6_crypto.c .halg.base = { base 2662 drivers/crypto/axis/artpec6_crypto.c .halg.base = { base 2686 drivers/crypto/axis/artpec6_crypto.c .halg.base = { base 2705 drivers/crypto/axis/artpec6_crypto.c .base = { base 2725 drivers/crypto/axis/artpec6_crypto.c .base = { base 2747 drivers/crypto/axis/artpec6_crypto.c .base = { base 2768 drivers/crypto/axis/artpec6_crypto.c .base = { base 2798 drivers/crypto/axis/artpec6_crypto.c .base = { base 2856 drivers/crypto/axis/artpec6_crypto.c void __iomem *base; base 2869 drivers/crypto/axis/artpec6_crypto.c base = devm_platform_ioremap_resource(pdev, 0); base 2870 drivers/crypto/axis/artpec6_crypto.c if (IS_ERR(base)) base 2871 drivers/crypto/axis/artpec6_crypto.c return PTR_ERR(base); base 2890 drivers/crypto/axis/artpec6_crypto.c ac->base = base; base 308 drivers/crypto/bcm/cipher.c container_of(areq, struct ablkcipher_request, base); base 490 drivers/crypto/bcm/cipher.c err = mailbox_send_message(mssg, req->base.flags, rctx->chan_idx); base 916 drivers/crypto/bcm/cipher.c err = mailbox_send_message(mssg, req->base.flags, rctx->chan_idx); base 1301 drivers/crypto/bcm/cipher.c struct aead_request, base); base 1555 drivers/crypto/bcm/cipher.c err = mailbox_send_message(mssg, req->base.flags, rctx->chan_idx); base 1571 drivers/crypto/bcm/cipher.c struct aead_request, base); base 1759 drivers/crypto/bcm/cipher.c rctx->gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG | base 1761 drivers/crypto/bcm/cipher.c rctx->parent = &req->base; base 1976 drivers/crypto/bcm/cipher.c rctx->gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG | base 1978 drivers/crypto/bcm/cipher.c rctx->parent = &req->base; base 2102 drivers/crypto/bcm/cipher.c gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG | base 2174 drivers/crypto/bcm/cipher.c gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG | base 2270 drivers/crypto/bcm/cipher.c gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG | base 2639 drivers/crypto/bcm/cipher.c container_of(areq, struct aead_request, base); base 2672 drivers/crypto/bcm/cipher.c rctx->old_complete = req->base.complete; base 2673 drivers/crypto/bcm/cipher.c rctx->old_data = req->base.data; base 2686 drivers/crypto/bcm/cipher.c req->base.data = rctx->old_data; base 2714 drivers/crypto/bcm/cipher.c rctx->gfp = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG | base 2716 drivers/crypto/bcm/cipher.c rctx->parent = &req->base; base 2893 drivers/crypto/bcm/cipher.c ctx->fallback_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; base 2894 drivers/crypto/bcm/cipher.c ctx->fallback_cipher->base.crt_flags |= base 2901 drivers/crypto/bcm/cipher.c (ctx->fallback_cipher->base.crt_flags & base 2965 drivers/crypto/bcm/cipher.c ctx->fallback_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; base 2966 drivers/crypto/bcm/cipher.c ctx->fallback_cipher->base.crt_flags |= base 2974 drivers/crypto/bcm/cipher.c (ctx->fallback_cipher->base.crt_flags & base 3130 drivers/crypto/bcm/cipher.c .base = { base 3153 drivers/crypto/bcm/cipher.c .base = { base 3176 drivers/crypto/bcm/cipher.c .base = { base 3199 drivers/crypto/bcm/cipher.c .base = { base 3222 drivers/crypto/bcm/cipher.c .base = { base 3245 drivers/crypto/bcm/cipher.c .base = { base 3268 drivers/crypto/bcm/cipher.c .base = { base 3291 drivers/crypto/bcm/cipher.c .base = { base 3314 drivers/crypto/bcm/cipher.c .base = { base 3337 drivers/crypto/bcm/cipher.c .base = { base 3360 drivers/crypto/bcm/cipher.c .base = { base 3383 drivers/crypto/bcm/cipher.c .base = { base 3406 drivers/crypto/bcm/cipher.c .base = { base 3429 drivers/crypto/bcm/cipher.c .base = { base 3452 drivers/crypto/bcm/cipher.c .base = { base 3475 drivers/crypto/bcm/cipher.c .base = { base 3498 drivers/crypto/bcm/cipher.c .base = { base 3521 drivers/crypto/bcm/cipher.c .base = { base 3544 drivers/crypto/bcm/cipher.c .base = { base 3567 drivers/crypto/bcm/cipher.c .base = { base 3847 drivers/crypto/bcm/cipher.c .halg.base = { base 3867 drivers/crypto/bcm/cipher.c .halg.base = { base 3885 drivers/crypto/bcm/cipher.c .halg.base = { base 3903 drivers/crypto/bcm/cipher.c .halg.base = { base 3921 drivers/crypto/bcm/cipher.c .halg.base = { base 3939 drivers/crypto/bcm/cipher.c .halg.base = { base 3957 drivers/crypto/bcm/cipher.c .halg.base = { base 3975 drivers/crypto/bcm/cipher.c .halg.base = { base 3994 drivers/crypto/bcm/cipher.c .halg.base = { base 4013 drivers/crypto/bcm/cipher.c .halg.base = { base 4032 drivers/crypto/bcm/cipher.c .halg.base = { base 4051 drivers/crypto/bcm/cipher.c .halg.base = { base 4070 drivers/crypto/bcm/cipher.c .halg.base = { base 4089 drivers/crypto/bcm/cipher.c .halg.base = { base 4108 drivers/crypto/bcm/cipher.c .halg.base = { base 4127 drivers/crypto/bcm/cipher.c .halg.base = { base 4146 drivers/crypto/bcm/cipher.c .halg.base = { base 4165 drivers/crypto/bcm/cipher.c .halg.base = { base 4184 drivers/crypto/bcm/cipher.c .halg.base = { base 4203 drivers/crypto/bcm/cipher.c .halg.base = { base 4222 drivers/crypto/bcm/cipher.c .halg.base = { base 4241 drivers/crypto/bcm/cipher.c .halg.base = { base 4325 drivers/crypto/bcm/cipher.c struct aead_alg *aalg = container_of(alg, struct aead_alg, base); base 4578 drivers/crypto/bcm/cipher.c hash->halg.base.cra_module = THIS_MODULE; base 4579 drivers/crypto/bcm/cipher.c hash->halg.base.cra_priority = hash_pri; base 4580 drivers/crypto/bcm/cipher.c hash->halg.base.cra_alignmask = 0; base 4581 drivers/crypto/bcm/cipher.c hash->halg.base.cra_ctxsize = sizeof(struct iproc_ctx_s); base 4582 drivers/crypto/bcm/cipher.c hash->halg.base.cra_init = ahash_cra_init; base 4583 drivers/crypto/bcm/cipher.c hash->halg.base.cra_exit = generic_cra_exit; base 4584 drivers/crypto/bcm/cipher.c hash->halg.base.cra_flags = CRYPTO_ALG_ASYNC; base 4614 drivers/crypto/bcm/cipher.c hash->halg.base.cra_driver_name); base 4623 drivers/crypto/bcm/cipher.c aead->base.cra_module = THIS_MODULE; base 4624 drivers/crypto/bcm/cipher.c aead->base.cra_priority = aead_pri; base 4625 drivers/crypto/bcm/cipher.c aead->base.cra_alignmask = 0; base 4626 drivers/crypto/bcm/cipher.c aead->base.cra_ctxsize = sizeof(struct iproc_ctx_s); base 4628 drivers/crypto/bcm/cipher.c aead->base.cra_flags |= CRYPTO_ALG_ASYNC; base 4640 drivers/crypto/bcm/cipher.c pr_debug(" registered aead %s\n", aead->base.cra_driver_name); base 4848 drivers/crypto/bcm/cipher.c cdn = driver_algs[i].alg.hash.halg.base.cra_driver_name; base 4855 drivers/crypto/bcm/cipher.c driver_algs[i].alg.aead.base.cra_driver_name); base 1328 drivers/crypto/caam/caamalg.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1685 drivers/crypto/caam/caamalg.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1913 drivers/crypto/caam/caamalg.c .base = { base 1929 drivers/crypto/caam/caamalg.c .base = { base 1945 drivers/crypto/caam/caamalg.c .base = { base 1961 drivers/crypto/caam/caamalg.c .base = { base 1979 drivers/crypto/caam/caamalg.c .base = { base 2002 drivers/crypto/caam/caamalg.c .base = { base 2018 drivers/crypto/caam/caamalg.c .base = { base 2033 drivers/crypto/caam/caamalg.c .base = { base 2048 drivers/crypto/caam/caamalg.c .base = { base 2063 drivers/crypto/caam/caamalg.c .base = { base 2081 drivers/crypto/caam/caamalg.c .base = { base 2100 drivers/crypto/caam/caamalg.c .base = { base 2120 drivers/crypto/caam/caamalg.c .base = { base 2140 drivers/crypto/caam/caamalg.c .base = { base 2161 drivers/crypto/caam/caamalg.c .base = { base 2182 drivers/crypto/caam/caamalg.c .base = { base 2203 drivers/crypto/caam/caamalg.c .base = { base 2224 drivers/crypto/caam/caamalg.c .base = { base 2245 drivers/crypto/caam/caamalg.c .base = { base 2266 drivers/crypto/caam/caamalg.c .base = { base 2287 drivers/crypto/caam/caamalg.c .base = { base 2310 drivers/crypto/caam/caamalg.c .base = { base 2331 drivers/crypto/caam/caamalg.c .base = { base 2354 drivers/crypto/caam/caamalg.c .base = { base 2375 drivers/crypto/caam/caamalg.c .base = { base 2398 drivers/crypto/caam/caamalg.c .base = { base 2419 drivers/crypto/caam/caamalg.c .base = { base 2442 drivers/crypto/caam/caamalg.c .base = { base 2463 drivers/crypto/caam/caamalg.c .base = { base 2486 drivers/crypto/caam/caamalg.c .base = { base 2507 drivers/crypto/caam/caamalg.c .base = { base 2530 drivers/crypto/caam/caamalg.c .base = { base 2551 drivers/crypto/caam/caamalg.c .base = { base 2574 drivers/crypto/caam/caamalg.c .base = { base 2596 drivers/crypto/caam/caamalg.c .base = { base 2620 drivers/crypto/caam/caamalg.c .base = { base 2642 drivers/crypto/caam/caamalg.c .base = { base 2666 drivers/crypto/caam/caamalg.c .base = { base 2688 drivers/crypto/caam/caamalg.c .base = { base 2712 drivers/crypto/caam/caamalg.c .base = { base 2734 drivers/crypto/caam/caamalg.c .base = { base 2758 drivers/crypto/caam/caamalg.c .base = { base 2780 drivers/crypto/caam/caamalg.c .base = { base 2804 drivers/crypto/caam/caamalg.c .base = { base 2825 drivers/crypto/caam/caamalg.c .base = { base 2848 drivers/crypto/caam/caamalg.c .base = { base 2869 drivers/crypto/caam/caamalg.c .base = { base 2892 drivers/crypto/caam/caamalg.c .base = { base 2913 drivers/crypto/caam/caamalg.c .base = { base 2936 drivers/crypto/caam/caamalg.c .base = { base 2957 drivers/crypto/caam/caamalg.c .base = { base 2980 drivers/crypto/caam/caamalg.c .base = { base 3001 drivers/crypto/caam/caamalg.c .base = { base 3024 drivers/crypto/caam/caamalg.c .base = { base 3045 drivers/crypto/caam/caamalg.c .base = { base 3068 drivers/crypto/caam/caamalg.c .base = { base 3092 drivers/crypto/caam/caamalg.c .base = { base 3117 drivers/crypto/caam/caamalg.c .base = { base 3141 drivers/crypto/caam/caamalg.c .base = { base 3166 drivers/crypto/caam/caamalg.c .base = { base 3190 drivers/crypto/caam/caamalg.c .base = { base 3215 drivers/crypto/caam/caamalg.c .base = { base 3239 drivers/crypto/caam/caamalg.c .base = { base 3264 drivers/crypto/caam/caamalg.c .base = { base 3288 drivers/crypto/caam/caamalg.c .base = { base 3313 drivers/crypto/caam/caamalg.c .base = { base 3337 drivers/crypto/caam/caamalg.c .base = { base 3362 drivers/crypto/caam/caamalg.c .base = { base 3385 drivers/crypto/caam/caamalg.c .base = { base 3509 drivers/crypto/caam/caamalg.c alg->base.cra_module = THIS_MODULE; base 3510 drivers/crypto/caam/caamalg.c alg->base.cra_priority = CAAM_CRA_PRIORITY; base 3511 drivers/crypto/caam/caamalg.c alg->base.cra_ctxsize = sizeof(struct caam_ctx); base 3512 drivers/crypto/caam/caamalg.c alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; base 3522 drivers/crypto/caam/caamalg.c alg->base.cra_module = THIS_MODULE; base 3523 drivers/crypto/caam/caamalg.c alg->base.cra_priority = CAAM_CRA_PRIORITY; base 3524 drivers/crypto/caam/caamalg.c alg->base.cra_ctxsize = sizeof(struct caam_ctx); base 3525 drivers/crypto/caam/caamalg.c alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; base 3619 drivers/crypto/caam/caamalg.c t_alg->skcipher.base.cra_driver_name); base 3671 drivers/crypto/caam/caamalg.c t_alg->aead.base.cra_driver_name); base 946 drivers/crypto/caam/caamalg_qi.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1252 drivers/crypto/caam/caamalg_qi.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1440 drivers/crypto/caam/caamalg_qi.c .base = { base 1456 drivers/crypto/caam/caamalg_qi.c .base = { base 1472 drivers/crypto/caam/caamalg_qi.c .base = { base 1488 drivers/crypto/caam/caamalg_qi.c .base = { base 1506 drivers/crypto/caam/caamalg_qi.c .base = { base 1529 drivers/crypto/caam/caamalg_qi.c .base = { base 1548 drivers/crypto/caam/caamalg_qi.c .base = { base 1567 drivers/crypto/caam/caamalg_qi.c .base = { base 1587 drivers/crypto/caam/caamalg_qi.c .base = { base 1607 drivers/crypto/caam/caamalg_qi.c .base = { base 1628 drivers/crypto/caam/caamalg_qi.c .base = { base 1651 drivers/crypto/caam/caamalg_qi.c .base = { base 1672 drivers/crypto/caam/caamalg_qi.c .base = { base 1695 drivers/crypto/caam/caamalg_qi.c .base = { base 1716 drivers/crypto/caam/caamalg_qi.c .base = { base 1739 drivers/crypto/caam/caamalg_qi.c .base = { base 1760 drivers/crypto/caam/caamalg_qi.c .base = { base 1784 drivers/crypto/caam/caamalg_qi.c .base = { base 1805 drivers/crypto/caam/caamalg_qi.c .base = { base 1829 drivers/crypto/caam/caamalg_qi.c .base = { base 1850 drivers/crypto/caam/caamalg_qi.c .base = { base 1874 drivers/crypto/caam/caamalg_qi.c .base = { base 1895 drivers/crypto/caam/caamalg_qi.c .base = { base 1918 drivers/crypto/caam/caamalg_qi.c .base = { base 1940 drivers/crypto/caam/caamalg_qi.c .base = { base 1964 drivers/crypto/caam/caamalg_qi.c .base = { base 1986 drivers/crypto/caam/caamalg_qi.c .base = { base 2010 drivers/crypto/caam/caamalg_qi.c .base = { base 2032 drivers/crypto/caam/caamalg_qi.c .base = { base 2056 drivers/crypto/caam/caamalg_qi.c .base = { base 2078 drivers/crypto/caam/caamalg_qi.c .base = { base 2102 drivers/crypto/caam/caamalg_qi.c .base = { base 2124 drivers/crypto/caam/caamalg_qi.c .base = { base 2148 drivers/crypto/caam/caamalg_qi.c .base = { base 2169 drivers/crypto/caam/caamalg_qi.c .base = { base 2192 drivers/crypto/caam/caamalg_qi.c .base = { base 2213 drivers/crypto/caam/caamalg_qi.c .base = { base 2236 drivers/crypto/caam/caamalg_qi.c .base = { base 2257 drivers/crypto/caam/caamalg_qi.c .base = { base 2281 drivers/crypto/caam/caamalg_qi.c .base = { base 2302 drivers/crypto/caam/caamalg_qi.c .base = { base 2326 drivers/crypto/caam/caamalg_qi.c .base = { base 2347 drivers/crypto/caam/caamalg_qi.c .base = { base 2371 drivers/crypto/caam/caamalg_qi.c .base = { base 2392 drivers/crypto/caam/caamalg_qi.c .base = { base 2524 drivers/crypto/caam/caamalg_qi.c alg->base.cra_module = THIS_MODULE; base 2525 drivers/crypto/caam/caamalg_qi.c alg->base.cra_priority = CAAM_CRA_PRIORITY; base 2526 drivers/crypto/caam/caamalg_qi.c alg->base.cra_ctxsize = sizeof(struct caam_ctx); base 2527 drivers/crypto/caam/caamalg_qi.c alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; base 2537 drivers/crypto/caam/caamalg_qi.c alg->base.cra_module = THIS_MODULE; base 2538 drivers/crypto/caam/caamalg_qi.c alg->base.cra_priority = CAAM_CRA_PRIORITY; base 2539 drivers/crypto/caam/caamalg_qi.c alg->base.cra_ctxsize = sizeof(struct caam_ctx); base 2540 drivers/crypto/caam/caamalg_qi.c alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; base 2611 drivers/crypto/caam/caamalg_qi.c t_alg->skcipher.base.cra_driver_name); base 2657 drivers/crypto/caam/caamalg_qi.c t_alg->aead.base.cra_driver_name); base 133 drivers/crypto/caam/caamalg_qi2.c base)); base 358 drivers/crypto/caam/caamalg_qi2.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1124 drivers/crypto/caam/caamalg_qi2.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1292 drivers/crypto/caam/caamalg_qi2.c base); base 1313 drivers/crypto/caam/caamalg_qi2.c base); base 1346 drivers/crypto/caam/caamalg_qi2.c caam_req->ctx = &req->base; base 1350 drivers/crypto/caam/caamalg_qi2.c !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 1374 drivers/crypto/caam/caamalg_qi2.c caam_req->ctx = &req->base; base 1378 drivers/crypto/caam/caamalg_qi2.c !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 1491 drivers/crypto/caam/caamalg_qi2.c caam_req->ctx = &req->base; base 1495 drivers/crypto/caam/caamalg_qi2.c !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 1521 drivers/crypto/caam/caamalg_qi2.c caam_req->ctx = &req->base; base 1525 drivers/crypto/caam/caamalg_qi2.c !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 1602 drivers/crypto/caam/caamalg_qi2.c .base = { base 1618 drivers/crypto/caam/caamalg_qi2.c .base = { base 1634 drivers/crypto/caam/caamalg_qi2.c .base = { base 1650 drivers/crypto/caam/caamalg_qi2.c .base = { base 1668 drivers/crypto/caam/caamalg_qi2.c .base = { base 1691 drivers/crypto/caam/caamalg_qi2.c .base = { base 1707 drivers/crypto/caam/caamalg_qi2.c .base = { base 1726 drivers/crypto/caam/caamalg_qi2.c .base = { base 1745 drivers/crypto/caam/caamalg_qi2.c .base = { base 1765 drivers/crypto/caam/caamalg_qi2.c .base = { base 1785 drivers/crypto/caam/caamalg_qi2.c .base = { base 1806 drivers/crypto/caam/caamalg_qi2.c .base = { base 1829 drivers/crypto/caam/caamalg_qi2.c .base = { base 1850 drivers/crypto/caam/caamalg_qi2.c .base = { base 1873 drivers/crypto/caam/caamalg_qi2.c .base = { base 1894 drivers/crypto/caam/caamalg_qi2.c .base = { base 1917 drivers/crypto/caam/caamalg_qi2.c .base = { base 1938 drivers/crypto/caam/caamalg_qi2.c .base = { base 1962 drivers/crypto/caam/caamalg_qi2.c .base = { base 1983 drivers/crypto/caam/caamalg_qi2.c .base = { base 2007 drivers/crypto/caam/caamalg_qi2.c .base = { base 2028 drivers/crypto/caam/caamalg_qi2.c .base = { base 2052 drivers/crypto/caam/caamalg_qi2.c .base = { base 2073 drivers/crypto/caam/caamalg_qi2.c .base = { base 2096 drivers/crypto/caam/caamalg_qi2.c .base = { base 2118 drivers/crypto/caam/caamalg_qi2.c .base = { base 2142 drivers/crypto/caam/caamalg_qi2.c .base = { base 2164 drivers/crypto/caam/caamalg_qi2.c .base = { base 2188 drivers/crypto/caam/caamalg_qi2.c .base = { base 2210 drivers/crypto/caam/caamalg_qi2.c .base = { base 2234 drivers/crypto/caam/caamalg_qi2.c .base = { base 2256 drivers/crypto/caam/caamalg_qi2.c .base = { base 2280 drivers/crypto/caam/caamalg_qi2.c .base = { base 2302 drivers/crypto/caam/caamalg_qi2.c .base = { base 2326 drivers/crypto/caam/caamalg_qi2.c .base = { base 2347 drivers/crypto/caam/caamalg_qi2.c .base = { base 2370 drivers/crypto/caam/caamalg_qi2.c .base = { base 2391 drivers/crypto/caam/caamalg_qi2.c .base = { base 2414 drivers/crypto/caam/caamalg_qi2.c .base = { base 2435 drivers/crypto/caam/caamalg_qi2.c .base = { base 2459 drivers/crypto/caam/caamalg_qi2.c .base = { base 2480 drivers/crypto/caam/caamalg_qi2.c .base = { base 2504 drivers/crypto/caam/caamalg_qi2.c .base = { base 2525 drivers/crypto/caam/caamalg_qi2.c .base = { base 2549 drivers/crypto/caam/caamalg_qi2.c .base = { base 2570 drivers/crypto/caam/caamalg_qi2.c .base = { base 2594 drivers/crypto/caam/caamalg_qi2.c .base = { base 2618 drivers/crypto/caam/caamalg_qi2.c .base = { base 2643 drivers/crypto/caam/caamalg_qi2.c .base = { base 2667 drivers/crypto/caam/caamalg_qi2.c .base = { base 2692 drivers/crypto/caam/caamalg_qi2.c .base = { base 2716 drivers/crypto/caam/caamalg_qi2.c .base = { base 2741 drivers/crypto/caam/caamalg_qi2.c .base = { base 2765 drivers/crypto/caam/caamalg_qi2.c .base = { base 2790 drivers/crypto/caam/caamalg_qi2.c .base = { base 2814 drivers/crypto/caam/caamalg_qi2.c .base = { base 2839 drivers/crypto/caam/caamalg_qi2.c .base = { base 2862 drivers/crypto/caam/caamalg_qi2.c .base = { base 2885 drivers/crypto/caam/caamalg_qi2.c .base = { base 2909 drivers/crypto/caam/caamalg_qi2.c .base = { base 2938 drivers/crypto/caam/caamalg_qi2.c alg->base.cra_module = THIS_MODULE; base 2939 drivers/crypto/caam/caamalg_qi2.c alg->base.cra_priority = CAAM_CRA_PRIORITY; base 2940 drivers/crypto/caam/caamalg_qi2.c alg->base.cra_ctxsize = sizeof(struct caam_ctx); base 2941 drivers/crypto/caam/caamalg_qi2.c alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; base 2951 drivers/crypto/caam/caamalg_qi2.c alg->base.cra_module = THIS_MODULE; base 2952 drivers/crypto/caam/caamalg_qi2.c alg->base.cra_priority = CAAM_CRA_PRIORITY; base 2953 drivers/crypto/caam/caamalg_qi2.c alg->base.cra_ctxsize = sizeof(struct caam_ctx); base 2954 drivers/crypto/caam/caamalg_qi2.c alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; base 3263 drivers/crypto/caam/caamalg_qi2.c unsigned int blocksize = crypto_tfm_alg_blocksize(&ahash->base); base 3367 drivers/crypto/caam/caamalg_qi2.c req->base.complete(&req->base, ecode); base 3397 drivers/crypto/caam/caamalg_qi2.c req->base.complete(&req->base, ecode); base 3424 drivers/crypto/caam/caamalg_qi2.c req->base.complete(&req->base, ecode); base 3454 drivers/crypto/caam/caamalg_qi2.c req->base.complete(&req->base, ecode); base 3465 drivers/crypto/caam/caamalg_qi2.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 3477 drivers/crypto/caam/caamalg_qi2.c *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1); base 3557 drivers/crypto/caam/caamalg_qi2.c req_ctx->ctx = &req->base; base 3563 drivers/crypto/caam/caamalg_qi2.c req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) base 3593 drivers/crypto/caam/caamalg_qi2.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 3642 drivers/crypto/caam/caamalg_qi2.c req_ctx->ctx = &req->base; base 3647 drivers/crypto/caam/caamalg_qi2.c (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) base 3664 drivers/crypto/caam/caamalg_qi2.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 3736 drivers/crypto/caam/caamalg_qi2.c req_ctx->ctx = &req->base; base 3741 drivers/crypto/caam/caamalg_qi2.c (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) base 3758 drivers/crypto/caam/caamalg_qi2.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 3832 drivers/crypto/caam/caamalg_qi2.c req_ctx->ctx = &req->base; base 3836 drivers/crypto/caam/caamalg_qi2.c (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) base 3853 drivers/crypto/caam/caamalg_qi2.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 3904 drivers/crypto/caam/caamalg_qi2.c req_ctx->ctx = &req->base; base 3909 drivers/crypto/caam/caamalg_qi2.c (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) base 3926 drivers/crypto/caam/caamalg_qi2.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 3937 drivers/crypto/caam/caamalg_qi2.c *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1); base 4016 drivers/crypto/caam/caamalg_qi2.c req_ctx->ctx = &req->base; base 4022 drivers/crypto/caam/caamalg_qi2.c req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) base 4056 drivers/crypto/caam/caamalg_qi2.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 4130 drivers/crypto/caam/caamalg_qi2.c req_ctx->ctx = &req->base; base 4134 drivers/crypto/caam/caamalg_qi2.c !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) base 4152 drivers/crypto/caam/caamalg_qi2.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 4161 drivers/crypto/caam/caamalg_qi2.c *next_buflen = req->nbytes & (crypto_tfm_alg_blocksize(&ahash->base) - base 4244 drivers/crypto/caam/caamalg_qi2.c req_ctx->ctx = &req->base; base 4249 drivers/crypto/caam/caamalg_qi2.c !(ret == -EBUSY && req->base.flags & base 4512 drivers/crypto/caam/caamalg_qi2.c struct crypto_alg *base = tfm->__crt_alg; base 4514 drivers/crypto/caam/caamalg_qi2.c container_of(base, struct hash_alg_common, base); base 4597 drivers/crypto/caam/caamalg_qi2.c alg = &halg->halg.base; base 5213 drivers/crypto/caam/caamalg_qi2.c t_alg->skcipher.base.cra_driver_name, err); base 5263 drivers/crypto/caam/caamalg_qi2.c t_alg->aead.base.cra_driver_name, err); base 5299 drivers/crypto/caam/caamalg_qi2.c t_alg->ahash_alg.halg.base.cra_driver_name, base 5318 drivers/crypto/caam/caamalg_qi2.c t_alg->ahash_alg.halg.base.cra_driver_name, base 448 drivers/crypto/caam/caamhash.c int blocksize = crypto_tfm_alg_blocksize(&ahash->base); base 625 drivers/crypto/caam/caamhash.c req->base.complete(&req->base, ecode); base 657 drivers/crypto/caam/caamhash.c req->base.complete(&req->base, ecode); base 685 drivers/crypto/caam/caamhash.c req->base.complete(&req->base, ecode); base 717 drivers/crypto/caam/caamhash.c req->base.complete(&req->base, ecode); base 787 drivers/crypto/caam/caamhash.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 926 drivers/crypto/caam/caamhash.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 992 drivers/crypto/caam/caamhash.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1072 drivers/crypto/caam/caamhash.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1149 drivers/crypto/caam/caamhash.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1208 drivers/crypto/caam/caamhash.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1343 drivers/crypto/caam/caamhash.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1429 drivers/crypto/caam/caamhash.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1809 drivers/crypto/caam/caamhash.c struct crypto_alg *base = tfm->__crt_alg; base 1811 drivers/crypto/caam/caamhash.c container_of(base, struct hash_alg_common, base); base 1954 drivers/crypto/caam/caamhash.c alg = &halg->halg.base; base 2040 drivers/crypto/caam/caamhash.c t_alg->ahash_alg.halg.base.cra_driver_name, base 2060 drivers/crypto/caam/caamhash.c t_alg->ahash_alg.halg.base.cra_driver_name, base 252 drivers/crypto/caam/caampkc.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 1076 drivers/crypto/caam/caampkc.c .base = { base 1116 drivers/crypto/caam/caampkc.c caam_rsa.akcipher.base.cra_driver_name); base 169 drivers/crypto/cavium/cpt/cptvf_algs.c req_info->callback_arg = (void *)&req->base; base 186 drivers/crypto/cavium/nitrox/nitrox_aead.c areq->base.complete(&areq->base, err); base 206 drivers/crypto/cavium/nitrox/nitrox_aead.c rctx->flags = areq->base.flags; base 237 drivers/crypto/cavium/nitrox/nitrox_aead.c rctx->flags = areq->base.flags; base 366 drivers/crypto/cavium/nitrox/nitrox_aead.c struct nitrox_aead_rctx *aead_rctx = &rctx->base; base 398 drivers/crypto/cavium/nitrox/nitrox_aead.c struct nitrox_kcrypt_request *nkreq = &rctx->base.nkreq; base 407 drivers/crypto/cavium/nitrox/nitrox_aead.c areq->base.complete(&areq->base, err); base 415 drivers/crypto/cavium/nitrox/nitrox_aead.c struct nitrox_aead_rctx *aead_rctx = &rctx->base; base 425 drivers/crypto/cavium/nitrox/nitrox_aead.c aead_rctx->flags = areq->base.flags; base 447 drivers/crypto/cavium/nitrox/nitrox_aead.c struct nitrox_aead_rctx *aead_rctx = &rctx->base; base 458 drivers/crypto/cavium/nitrox/nitrox_aead.c aead_rctx->flags = areq->base.flags; base 490 drivers/crypto/cavium/nitrox/nitrox_aead.c .base = { base 509 drivers/crypto/cavium/nitrox/nitrox_aead.c .base = { base 50 drivers/crypto/cavium/nitrox/nitrox_dev.h u8 *base; base 37 drivers/crypto/cavium/nitrox/nitrox_lib.c cmdq->base = cmdq->unalign_base + (cmdq->dma - cmdq->unalign_dma); base 80 drivers/crypto/cavium/nitrox/nitrox_lib.c cmdq->base = NULL; base 252 drivers/crypto/cavium/nitrox/nitrox_req.h struct nitrox_aead_rctx base; base 295 drivers/crypto/cavium/nitrox/nitrox_reqmgr.c ent = cmdq->base + (idx * cmdq->instr_size); base 214 drivers/crypto/cavium/nitrox/nitrox_skcipher.c creq->flags = skreq->base.flags; base 215 drivers/crypto/cavium/nitrox/nitrox_skcipher.c creq->gfp = (skreq->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 328 drivers/crypto/cavium/nitrox/nitrox_skcipher.c .base = { base 347 drivers/crypto/cavium/nitrox/nitrox_skcipher.c .base = { base 366 drivers/crypto/cavium/nitrox/nitrox_skcipher.c .base = { base 385 drivers/crypto/cavium/nitrox/nitrox_skcipher.c .base = { base 404 drivers/crypto/cavium/nitrox/nitrox_skcipher.c .base = { base 423 drivers/crypto/cavium/nitrox/nitrox_skcipher.c .base = { base 443 drivers/crypto/cavium/nitrox/nitrox_skcipher.c .base = { base 462 drivers/crypto/cavium/nitrox/nitrox_skcipher.c .base = { base 387 drivers/crypto/cavium/zip/zip_main.c .base = { base 400 drivers/crypto/cavium/zip/zip_main.c .base = { base 108 drivers/crypto/ccp/ccp-crypto-aes-cmac.c gfp = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? base 173 drivers/crypto/ccp/ccp-crypto-aes-cmac.c ret = ccp_crypto_enqueue_request(&req->base, &rctx->cmd); base 354 drivers/crypto/ccp/ccp-crypto-aes-cmac.c struct crypto_alg *base; base 378 drivers/crypto/ccp/ccp-crypto-aes-cmac.c base = &halg->base; base 379 drivers/crypto/ccp/ccp-crypto-aes-cmac.c snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "cmac(aes)"); base 380 drivers/crypto/ccp/ccp-crypto-aes-cmac.c snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "cmac-aes-ccp"); base 381 drivers/crypto/ccp/ccp-crypto-aes-cmac.c base->cra_flags = CRYPTO_ALG_ASYNC | base 384 drivers/crypto/ccp/ccp-crypto-aes-cmac.c base->cra_blocksize = AES_BLOCK_SIZE; base 385 drivers/crypto/ccp/ccp-crypto-aes-cmac.c base->cra_ctxsize = sizeof(struct ccp_ctx); base 386 drivers/crypto/ccp/ccp-crypto-aes-cmac.c base->cra_priority = CCP_CRA_PRIORITY; base 387 drivers/crypto/ccp/ccp-crypto-aes-cmac.c base->cra_init = ccp_aes_cmac_cra_init; base 388 drivers/crypto/ccp/ccp-crypto-aes-cmac.c base->cra_module = THIS_MODULE; base 393 drivers/crypto/ccp/ccp-crypto-aes-cmac.c base->cra_name, ret); base 135 drivers/crypto/ccp/ccp-crypto-aes-galois.c ret = ccp_crypto_enqueue_request(&req->base, &rctx->cmd); base 174 drivers/crypto/ccp/ccp-crypto-aes-galois.c .base = { base 228 drivers/crypto/ccp/ccp-crypto-aes-galois.c snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name); base 229 drivers/crypto/ccp/ccp-crypto-aes-galois.c snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", base 231 drivers/crypto/ccp/ccp-crypto-aes-galois.c alg->base.cra_blocksize = def->blocksize; base 232 drivers/crypto/ccp/ccp-crypto-aes-galois.c alg->base.cra_ablkcipher.ivsize = def->ivsize; base 237 drivers/crypto/ccp/ccp-crypto-aes-galois.c alg->base.cra_name, ret); base 108 drivers/crypto/ccp/ccp-crypto-aes-xts.c struct ccp_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 155 drivers/crypto/ccp/ccp-crypto-aes-xts.c skcipher_request_set_callback(subreq, req->base.flags, base 183 drivers/crypto/ccp/ccp-crypto-aes-xts.c ret = ccp_crypto_enqueue_request(&req->base, &rctx->cmd); base 25 drivers/crypto/ccp/ccp-crypto-aes.c struct ccp_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 69 drivers/crypto/ccp/ccp-crypto-aes.c struct ccp_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 108 drivers/crypto/ccp/ccp-crypto-aes.c ret = ccp_crypto_enqueue_request(&req->base, &rctx->cmd); base 167 drivers/crypto/ccp/ccp-crypto-aes.c struct ccp_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 24 drivers/crypto/ccp/ccp-crypto-des3.c struct ccp_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 63 drivers/crypto/ccp/ccp-crypto-des3.c struct ccp_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 103 drivers/crypto/ccp/ccp-crypto-des3.c ret = ccp_crypto_enqueue_request(&req->base, &rctx->cmd); base 25 drivers/crypto/ccp/ccp-crypto-rsa.c return container_of(req, struct akcipher_request, base); base 89 drivers/crypto/ccp/ccp-crypto-rsa.c ret = ccp_crypto_enqueue_request(&req->base, &rctx->cmd); base 205 drivers/crypto/ccp/ccp-crypto-rsa.c struct ccp_ctx *ctx = crypto_tfm_ctx(&tfm->base); base 218 drivers/crypto/ccp/ccp-crypto-rsa.c .base = { base 260 drivers/crypto/ccp/ccp-crypto-rsa.c snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name); base 261 drivers/crypto/ccp/ccp-crypto-rsa.c snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", base 266 drivers/crypto/ccp/ccp-crypto-rsa.c alg->base.cra_name, ret); base 100 drivers/crypto/ccp/ccp-crypto-sha.c gfp = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? base 170 drivers/crypto/ccp/ccp-crypto-sha.c ret = ccp_crypto_enqueue_request(&req->base, &rctx->cmd); base 423 drivers/crypto/ccp/ccp-crypto-sha.c struct crypto_alg *base; base 441 drivers/crypto/ccp/ccp-crypto-sha.c base = &halg->base; base 442 drivers/crypto/ccp/ccp-crypto-sha.c snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "hmac(%s)", def->name); base 443 drivers/crypto/ccp/ccp-crypto-sha.c snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "hmac-%s", base 445 drivers/crypto/ccp/ccp-crypto-sha.c base->cra_init = ccp_hmac_sha_cra_init; base 446 drivers/crypto/ccp/ccp-crypto-sha.c base->cra_exit = ccp_hmac_sha_cra_exit; base 451 drivers/crypto/ccp/ccp-crypto-sha.c base->cra_name, ret); base 467 drivers/crypto/ccp/ccp-crypto-sha.c struct crypto_alg *base; base 491 drivers/crypto/ccp/ccp-crypto-sha.c base = &halg->base; base 492 drivers/crypto/ccp/ccp-crypto-sha.c snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name); base 493 drivers/crypto/ccp/ccp-crypto-sha.c snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", base 495 drivers/crypto/ccp/ccp-crypto-sha.c base->cra_flags = CRYPTO_ALG_ASYNC | base 498 drivers/crypto/ccp/ccp-crypto-sha.c base->cra_blocksize = def->block_size; base 499 drivers/crypto/ccp/ccp-crypto-sha.c base->cra_ctxsize = sizeof(struct ccp_ctx); base 500 drivers/crypto/ccp/ccp-crypto-sha.c base->cra_priority = CCP_CRA_PRIORITY; base 501 drivers/crypto/ccp/ccp-crypto-sha.c base->cra_init = ccp_sha_cra_init; base 502 drivers/crypto/ccp/ccp-crypto-sha.c base->cra_exit = ccp_sha_cra_exit; base 503 drivers/crypto/ccp/ccp-crypto-sha.c base->cra_module = THIS_MODULE; base 508 drivers/crypto/ccp/ccp-crypto-sha.c base->cra_name, ret); base 83 drivers/crypto/ccp/ccp-crypto.h ahash_alg = container_of(alg, struct ahash_alg, halg.base); base 74 drivers/crypto/ccree/cc_aead.c crypto_tfm_alg_name(&tfm->base)); base 138 drivers/crypto/ccree/cc_aead.c crypto_tfm_alg_name(&tfm->base)); base 2024 drivers/crypto/ccree/cc_aead.c rc = cc_send_request(ctx->drvdata, &cc_req, desc, seq_len, &req->base); base 2631 drivers/crypto/ccree/cc_aead.c snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name); base 2632 drivers/crypto/ccree/cc_aead.c snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", base 2634 drivers/crypto/ccree/cc_aead.c alg->base.cra_module = THIS_MODULE; base 2635 drivers/crypto/ccree/cc_aead.c alg->base.cra_priority = CC_CRA_PRIO; base 2637 drivers/crypto/ccree/cc_aead.c alg->base.cra_ctxsize = sizeof(struct cc_aead_ctx); base 2638 drivers/crypto/ccree/cc_aead.c alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; base 2715 drivers/crypto/ccree/cc_aead.c t_alg->aead_alg.base.cra_driver_name); base 2720 drivers/crypto/ccree/cc_aead.c t_alg->aead_alg.base.cra_driver_name); base 582 drivers/crypto/ccree/cc_buffer_mgr.c gfp_t flags = cc_gfp_flags(&req->base); base 1019 drivers/crypto/ccree/cc_buffer_mgr.c gfp_t flags = cc_gfp_flags(&req->base); base 163 drivers/crypto/ccree/cc_cipher.c skcipher_alg.base); base 215 drivers/crypto/ccree/cc_cipher.c skcipher_alg.base); base 387 drivers/crypto/ccree/cc_cipher.c skcipher_alg.base); base 543 drivers/crypto/ccree/cc_cipher.c skcipher_alg.base); base 598 drivers/crypto/ccree/cc_cipher.c skcipher_alg.base); base 869 drivers/crypto/ccree/cc_cipher.c gfp_t flags = cc_gfp_flags(&req->base); base 940 drivers/crypto/ccree/cc_cipher.c &req->base); base 1649 drivers/crypto/ccree/cc_cipher.c snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name); base 1650 drivers/crypto/ccree/cc_cipher.c snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", base 1652 drivers/crypto/ccree/cc_cipher.c alg->base.cra_module = THIS_MODULE; base 1653 drivers/crypto/ccree/cc_cipher.c alg->base.cra_priority = CC_CRA_PRIO; base 1654 drivers/crypto/ccree/cc_cipher.c alg->base.cra_blocksize = tmpl->blocksize; base 1655 drivers/crypto/ccree/cc_cipher.c alg->base.cra_alignmask = 0; base 1656 drivers/crypto/ccree/cc_cipher.c alg->base.cra_ctxsize = sizeof(struct cc_cipher_ctx); base 1658 drivers/crypto/ccree/cc_cipher.c alg->base.cra_init = cc_cipher_init; base 1659 drivers/crypto/ccree/cc_cipher.c alg->base.cra_exit = cc_cipher_exit; base 1660 drivers/crypto/ccree/cc_cipher.c alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; base 1726 drivers/crypto/ccree/cc_cipher.c t_alg->skcipher_alg.base.cra_driver_name, rc); base 1729 drivers/crypto/ccree/cc_cipher.c t_alg->skcipher_alg.base.cra_driver_name); base 1736 drivers/crypto/ccree/cc_cipher.c t_alg->skcipher_alg.base.cra_driver_name); base 83 drivers/crypto/ccree/cc_debugfs.c regset->base = drvdata->cc_base; base 104 drivers/crypto/ccree/cc_debugfs.c verset->base = drvdata->cc_base; base 429 drivers/crypto/ccree/cc_hash.c gfp_t flags = cc_gfp_flags(&req->base); base 512 drivers/crypto/ccree/cc_hash.c rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); base 554 drivers/crypto/ccree/cc_hash.c unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base); base 562 drivers/crypto/ccree/cc_hash.c gfp_t flags = cc_gfp_flags(&req->base); base 616 drivers/crypto/ccree/cc_hash.c rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); base 640 drivers/crypto/ccree/cc_hash.c gfp_t flags = cc_gfp_flags(&req->base); base 684 drivers/crypto/ccree/cc_hash.c rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); base 736 drivers/crypto/ccree/cc_hash.c blocksize = crypto_tfm_alg_blocksize(&ahash->base); base 1123 drivers/crypto/ccree/cc_hash.c container_of(tfm->__crt_alg, struct hash_alg_common, base); base 1155 drivers/crypto/ccree/cc_hash.c unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base); base 1160 drivers/crypto/ccree/cc_hash.c gfp_t flags = cc_gfp_flags(&req->base); base 1208 drivers/crypto/ccree/cc_hash.c rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); base 1229 drivers/crypto/ccree/cc_hash.c gfp_t flags = cc_gfp_flags(&req->base); base 1329 drivers/crypto/ccree/cc_hash.c rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); base 1351 drivers/crypto/ccree/cc_hash.c gfp_t flags = cc_gfp_flags(&req->base); base 1411 drivers/crypto/ccree/cc_hash.c rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); base 1433 drivers/crypto/ccree/cc_hash.c gfp_t flags = cc_gfp_flags(&req->base); base 1490 drivers/crypto/ccree/cc_hash.c rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); base 1835 drivers/crypto/ccree/cc_hash.c alg = &halg->halg.base; base 228 drivers/crypto/chelsio/chcr_algo.c req->base.complete(&req->base, err); base 772 drivers/crypto/chelsio/chcr_algo.c gfp_t flags = wrparam->req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? base 838 drivers/crypto/chelsio/chcr_algo.c create_wreq(c_ctx(tfm), chcr_req, &(wrparam->req->base), reqctx->imm, 0, base 880 drivers/crypto/chelsio/chcr_algo.c cipher->base.crt_flags & CRYPTO_TFM_REQ_MASK); base 1153 drivers/crypto/chelsio/chcr_algo.c req->base.flags, base 1184 drivers/crypto/chelsio/chcr_algo.c req->base.complete(&req->base, err); base 1268 drivers/crypto/chelsio/chcr_algo.c req->base.flags, base 1313 drivers/crypto/chelsio/chcr_algo.c if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 1347 drivers/crypto/chelsio/chcr_algo.c if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) base 1503 drivers/crypto/chelsio/chcr_algo.c gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : base 1573 drivers/crypto/chelsio/chcr_algo.c create_wreq(h_ctx(tfm), chcr_req, &req->base, req_ctx->hctx_wr.imm, base 1616 drivers/crypto/chelsio/chcr_algo.c if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 1766 drivers/crypto/chelsio/chcr_algo.c if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 1859 drivers/crypto/chelsio/chcr_algo.c if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 2040 drivers/crypto/chelsio/chcr_algo.c req->base.complete(&req->base, err); base 2313 drivers/crypto/chelsio/chcr_algo.c aead_request_set_callback(subreq, req->base.flags, base 2314 drivers/crypto/chelsio/chcr_algo.c req->base.complete, req->base.data); base 2341 drivers/crypto/chelsio/chcr_algo.c gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : base 2449 drivers/crypto/chelsio/chcr_algo.c create_wreq(a_ctx(tfm), chcr_req, &req->base, reqctx->imm, size, base 2900 drivers/crypto/chelsio/chcr_algo.c gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : base 2968 drivers/crypto/chelsio/chcr_algo.c create_wreq(a_ctx(tfm), chcr_req, &req->base, reqctx->imm, 0, base 2996 drivers/crypto/chelsio/chcr_algo.c gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : base 3083 drivers/crypto/chelsio/chcr_algo.c create_wreq(a_ctx(tfm), chcr_req, &req->base, reqctx->imm, size, base 3100 drivers/crypto/chelsio/chcr_algo.c aeadctx->sw_cipher = crypto_alloc_aead(alg->base.cra_name, 0, base 3631 drivers/crypto/chelsio/chcr_algo.c if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 3789 drivers/crypto/chelsio/chcr_algo.c .halg.base = { base 3801 drivers/crypto/chelsio/chcr_algo.c .halg.base = { base 3813 drivers/crypto/chelsio/chcr_algo.c .halg.base = { base 3825 drivers/crypto/chelsio/chcr_algo.c .halg.base = { base 3837 drivers/crypto/chelsio/chcr_algo.c .halg.base = { base 3850 drivers/crypto/chelsio/chcr_algo.c .halg.base = { base 3862 drivers/crypto/chelsio/chcr_algo.c .halg.base = { base 3874 drivers/crypto/chelsio/chcr_algo.c .halg.base = { base 3886 drivers/crypto/chelsio/chcr_algo.c .halg.base = { base 3898 drivers/crypto/chelsio/chcr_algo.c .halg.base = { base 3910 drivers/crypto/chelsio/chcr_algo.c .base = { base 3929 drivers/crypto/chelsio/chcr_algo.c .base = { base 3949 drivers/crypto/chelsio/chcr_algo.c .base = { base 3968 drivers/crypto/chelsio/chcr_algo.c .base = { base 3987 drivers/crypto/chelsio/chcr_algo.c .base = { base 4008 drivers/crypto/chelsio/chcr_algo.c .base = { base 4030 drivers/crypto/chelsio/chcr_algo.c .base = { base 4050 drivers/crypto/chelsio/chcr_algo.c .base = { base 4071 drivers/crypto/chelsio/chcr_algo.c .base = { base 4092 drivers/crypto/chelsio/chcr_algo.c .base = { base 4113 drivers/crypto/chelsio/chcr_algo.c .base = { base 4134 drivers/crypto/chelsio/chcr_algo.c .base = { base 4156 drivers/crypto/chelsio/chcr_algo.c .base = { base 4176 drivers/crypto/chelsio/chcr_algo.c .base = { base 4197 drivers/crypto/chelsio/chcr_algo.c .base = { base 4218 drivers/crypto/chelsio/chcr_algo.c .base = { base 4303 drivers/crypto/chelsio/chcr_algo.c driver_algs[i].alg.aead.base.cra_flags = base 4309 drivers/crypto/chelsio/chcr_algo.c driver_algs[i].alg.aead.base.cra_module = THIS_MODULE; base 4311 drivers/crypto/chelsio/chcr_algo.c name = driver_algs[i].alg.aead.base.cra_driver_name; base 4322 drivers/crypto/chelsio/chcr_algo.c a_hash->halg.base.cra_priority = CHCR_CRA_PRIORITY; base 4323 drivers/crypto/chelsio/chcr_algo.c a_hash->halg.base.cra_module = THIS_MODULE; base 4324 drivers/crypto/chelsio/chcr_algo.c a_hash->halg.base.cra_flags = CRYPTO_ALG_ASYNC; base 4325 drivers/crypto/chelsio/chcr_algo.c a_hash->halg.base.cra_alignmask = 0; base 4326 drivers/crypto/chelsio/chcr_algo.c a_hash->halg.base.cra_exit = NULL; base 4329 drivers/crypto/chelsio/chcr_algo.c a_hash->halg.base.cra_init = chcr_hmac_cra_init; base 4330 drivers/crypto/chelsio/chcr_algo.c a_hash->halg.base.cra_exit = chcr_hmac_cra_exit; base 4333 drivers/crypto/chelsio/chcr_algo.c a_hash->halg.base.cra_ctxsize = SZ_AHASH_H_CTX; base 4336 drivers/crypto/chelsio/chcr_algo.c a_hash->halg.base.cra_ctxsize = SZ_AHASH_CTX; base 4337 drivers/crypto/chelsio/chcr_algo.c a_hash->halg.base.cra_init = chcr_sha_cra_init; base 4340 drivers/crypto/chelsio/chcr_algo.c ai = driver_algs[i].alg.hash.halg.base; base 258 drivers/crypto/exynos-rng.c .base = { base 131 drivers/crypto/geode-aes.c tctx->fallback.cip->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; base 132 drivers/crypto/geode-aes.c tctx->fallback.cip->base.crt_flags |= base 138 drivers/crypto/geode-aes.c tfm->crt_flags |= (tctx->fallback.cip->base.crt_flags & base 255 drivers/crypto/geode-aes.c const char *name = crypto_tfm_alg_name(&tfm->base); base 331 drivers/crypto/geode-aes.c .base.cra_name = "cbc(aes)", base 332 drivers/crypto/geode-aes.c .base.cra_driver_name = "cbc-aes-geode", base 333 drivers/crypto/geode-aes.c .base.cra_priority = 400, base 334 drivers/crypto/geode-aes.c .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | base 336 drivers/crypto/geode-aes.c .base.cra_blocksize = AES_BLOCK_SIZE, base 337 drivers/crypto/geode-aes.c .base.cra_ctxsize = sizeof(struct geode_aes_tfm_ctx), base 338 drivers/crypto/geode-aes.c .base.cra_alignmask = 15, base 339 drivers/crypto/geode-aes.c .base.cra_module = THIS_MODULE, base 349 drivers/crypto/geode-aes.c .base.cra_name = "ecb(aes)", base 350 drivers/crypto/geode-aes.c .base.cra_driver_name = "ecb-aes-geode", base 351 drivers/crypto/geode-aes.c .base.cra_priority = 400, base 352 drivers/crypto/geode-aes.c .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | base 354 drivers/crypto/geode-aes.c .base.cra_blocksize = AES_BLOCK_SIZE, base 355 drivers/crypto/geode-aes.c .base.cra_ctxsize = sizeof(struct geode_aes_tfm_ctx), base 356 drivers/crypto/geode-aes.c .base.cra_alignmask = 15, base 357 drivers/crypto/geode-aes.c .base.cra_module = THIS_MODULE, base 1523 drivers/crypto/hifn_795x.c struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); base 1705 drivers/crypto/hifn_795x.c req->base.complete(&req->base, error); base 1979 drivers/crypto/hifn_795x.c struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); base 2000 drivers/crypto/hifn_795x.c struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); base 2070 drivers/crypto/hifn_795x.c struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); base 172 drivers/crypto/hisilicon/qm.c #define INIT_QC_COMMON(qc, base, pasid) do { \ base 175 drivers/crypto/hisilicon/qm.c (qc)->base_l = lower_32_bits(base); \ base 176 drivers/crypto/hisilicon/qm.c (qc)->base_h = upper_32_bits(base); \ base 273 drivers/crypto/hisilicon/qm.c int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number); base 653 drivers/crypto/hisilicon/qm.c static void qm_vft_data_cfg(struct hisi_qm *qm, enum vft_type type, u32 base, base 667 drivers/crypto/hisilicon/qm.c (u64)base << QM_SQC_VFT_START_SQN_SHIFT; base 670 drivers/crypto/hisilicon/qm.c tmp = (u64)base << QM_SQC_VFT_START_SQN_SHIFT | base 701 drivers/crypto/hisilicon/qm.c u32 fun_num, u32 base, u32 number) base 715 drivers/crypto/hisilicon/qm.c qm_vft_data_cfg(qm, type, base, number); base 725 drivers/crypto/hisilicon/qm.c static int qm_set_sqc_cqc_vft(struct hisi_qm *qm, u32 fun_num, u32 base, base 731 drivers/crypto/hisilicon/qm.c ret = qm_set_vft_common(qm, i, fun_num, base, number); base 739 drivers/crypto/hisilicon/qm.c static int qm_get_vft_v2(struct hisi_qm *qm, u32 *base, u32 *number) base 750 drivers/crypto/hisilicon/qm.c *base = QM_SQC_VFT_BASE_MASK_V2 & (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2); base 1516 drivers/crypto/hisilicon/qm.c int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number) base 1518 drivers/crypto/hisilicon/qm.c if (!base || !number) base 1526 drivers/crypto/hisilicon/qm.c return qm->ops->get_vft(qm, base, number); base 1544 drivers/crypto/hisilicon/qm.c int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, base 1549 drivers/crypto/hisilicon/qm.c if (base >= max_q_num || number > max_q_num || base 1550 drivers/crypto/hisilicon/qm.c (base + number) > max_q_num) base 1553 drivers/crypto/hisilicon/qm.c return qm_set_sqc_cqc_vft(qm, fun_num, base, number); base 207 drivers/crypto/hisilicon/qm.h int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number); base 208 drivers/crypto/hisilicon/qm.h int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, u32 number); base 425 drivers/crypto/hisilicon/sec/sec_algs.c base); base 536 drivers/crypto/hisilicon/sec/sec_algs.c skreq->base.complete(&skreq->base, sec_req->err); base 725 drivers/crypto/hisilicon/sec/sec_algs.c sec_req->req_base = &skreq->base; base 813 drivers/crypto/hisilicon/sec/sec_algs.c if ((skreq->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 931 drivers/crypto/hisilicon/sec/sec_algs.c .base = { base 950 drivers/crypto/hisilicon/sec/sec_algs.c .base = { base 969 drivers/crypto/hisilicon/sec/sec_algs.c .base = { base 988 drivers/crypto/hisilicon/sec/sec_algs.c .base = { base 1008 drivers/crypto/hisilicon/sec/sec_algs.c .base = { base 1027 drivers/crypto/hisilicon/sec/sec_algs.c .base = { base 1046 drivers/crypto/hisilicon/sec/sec_algs.c .base = { base 1065 drivers/crypto/hisilicon/sec/sec_algs.c .base = { base 281 drivers/crypto/hisilicon/sec/sec_drv.c void __iomem *base = info->regs[SEC_COMMON]; base 284 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(0x7, base + SEC_ALGSUB_CLK_EN_REG); base 287 drivers/crypto/hisilicon/sec/sec_drv.c if ((readl_relaxed(base + SEC_ALGSUB_CLK_ST_REG) & 0x7) == 0x7) base 298 drivers/crypto/hisilicon/sec/sec_drv.c void __iomem *base = info->regs[SEC_COMMON]; base 301 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(0x7, base + SEC_ALGSUB_CLK_DIS_REG); base 304 drivers/crypto/hisilicon/sec/sec_drv.c if ((readl_relaxed(base + SEC_ALGSUB_CLK_ST_REG) & 0x7) == 0) base 315 drivers/crypto/hisilicon/sec/sec_drv.c void __iomem *base = info->regs[SEC_COMMON]; base 319 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(1, base + SEC_ALGSUB_RST_REQ_REG); base 320 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(1, base + SEC_ALGSUB_BUILD_RST_REQ_REG); base 323 drivers/crypto/hisilicon/sec/sec_drv.c is_reset = readl_relaxed(base + SEC_ALGSUB_RST_ST_REG) & base 325 drivers/crypto/hisilicon/sec/sec_drv.c b_is_reset = readl_relaxed(base + SEC_ALGSUB_BUILD_RST_ST_REG) & base 337 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(1, base + SEC_ALGSUB_RST_DREQ_REG); base 338 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(1, base + SEC_ALGSUB_BUILD_RST_DREQ_REG); base 341 drivers/crypto/hisilicon/sec/sec_drv.c is_reset = readl_relaxed(base + SEC_ALGSUB_RST_ST_REG) & base 343 drivers/crypto/hisilicon/sec/sec_drv.c b_is_reset = readl_relaxed(base + SEC_ALGSUB_BUILD_RST_ST_REG) & base 450 drivers/crypto/hisilicon/sec/sec_drv.c void __iomem *base = info->regs[SEC_SAA]; base 455 drivers/crypto/hisilicon/sec/sec_drv.c base + SEC_IPV6_MASK_TABLE_X_REG(i)); base 555 drivers/crypto/hisilicon/sec/sec_drv.c void __iomem *base = queue->regs; base 558 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(base + SEC_Q_CFG_REG); base 563 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, base + SEC_Q_CFG_REG); base 687 drivers/crypto/hisilicon/sec/sec_drv.c void __iomem *base = queue->regs; base 690 drivers/crypto/hisilicon/sec/sec_drv.c ooo_read = readl(base + SEC_Q_OUTORDER_RD_PTR_REG); base 691 drivers/crypto/hisilicon/sec/sec_drv.c ooo_write = readl(base + SEC_Q_OUTORDER_WR_PTR_REG); base 716 drivers/crypto/hisilicon/sec/sec_drv.c writel(ooo_read, base + SEC_Q_OUTORDER_RD_PTR_REG); base 717 drivers/crypto/hisilicon/sec/sec_drv.c ooo_write = readl(base + SEC_Q_OUTORDER_WR_PTR_REG); base 860 drivers/crypto/hisilicon/sec/sec_drv.c void __iomem *base = queue->regs; base 864 drivers/crypto/hisilicon/sec/sec_drv.c read = readl(base + SEC_Q_RD_PTR_REG); base 865 drivers/crypto/hisilicon/sec/sec_drv.c write = readl(base + SEC_Q_WR_PTR_REG); base 876 drivers/crypto/hisilicon/sec/sec_drv.c writel(write, base + SEC_Q_WR_PTR_REG); base 337 drivers/crypto/hisilicon/zip/zip_crypto.c if (acomp_req->base.complete) base 354 drivers/crypto/hisilicon/zip/zip_crypto.c const char *alg_name = crypto_tfm_alg_name(&tfm->base); base 355 drivers/crypto/hisilicon/zip/zip_crypto.c struct hisi_zip_ctx *ctx = crypto_tfm_ctx(&tfm->base); base 383 drivers/crypto/hisilicon/zip/zip_crypto.c struct hisi_zip_ctx *ctx = crypto_tfm_ctx(&tfm->base); base 513 drivers/crypto/hisilicon/zip/zip_crypto.c struct hisi_zip_ctx *ctx = crypto_tfm_ctx(acomp_req->base.tfm); base 537 drivers/crypto/hisilicon/zip/zip_crypto.c struct hisi_zip_ctx *ctx = crypto_tfm_ctx(acomp_req->base.tfm); base 561 drivers/crypto/hisilicon/zip/zip_crypto.c .base = { base 575 drivers/crypto/hisilicon/zip/zip_crypto.c .base = { base 293 drivers/crypto/hisilicon/zip/zip_main.c void __iomem *base = hisi_zip->qm.io_base; base 296 drivers/crypto/hisilicon/zip/zip_main.c writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); base 297 drivers/crypto/hisilicon/zip/zip_main.c writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); base 298 drivers/crypto/hisilicon/zip/zip_main.c writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); base 299 drivers/crypto/hisilicon/zip/zip_main.c writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); base 300 drivers/crypto/hisilicon/zip/zip_main.c writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); base 303 drivers/crypto/hisilicon/zip/zip_main.c writel(AXI_M_CFG, base + QM_AXI_M_CFG); base 304 drivers/crypto/hisilicon/zip/zip_main.c writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); base 306 drivers/crypto/hisilicon/zip/zip_main.c writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); base 307 drivers/crypto/hisilicon/zip/zip_main.c writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); base 310 drivers/crypto/hisilicon/zip/zip_main.c writel(CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); base 311 drivers/crypto/hisilicon/zip/zip_main.c writel(CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); base 312 drivers/crypto/hisilicon/zip/zip_main.c writel(CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); base 313 drivers/crypto/hisilicon/zip/zip_main.c writel(CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); base 316 drivers/crypto/hisilicon/zip/zip_main.c writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); base 317 drivers/crypto/hisilicon/zip/zip_main.c writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); base 318 drivers/crypto/hisilicon/zip/zip_main.c writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); base 319 drivers/crypto/hisilicon/zip/zip_main.c writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); base 320 drivers/crypto/hisilicon/zip/zip_main.c writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); base 324 drivers/crypto/hisilicon/zip/zip_main.c base + HZIP_CLOCK_GATE_CTRL); base 329 drivers/crypto/hisilicon/zip/zip_main.c FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); base 534 drivers/crypto/hisilicon/zip/zip_main.c regset->base = qm->io_base + core_offsets[i]; base 308 drivers/crypto/img-hash.c if (req->base.complete) base 309 drivers/crypto/img-hash.c req->base.complete(&req->base, err); base 488 drivers/crypto/img-hash.c rctx->fallback_req.base.flags = req->base.flags base 552 drivers/crypto/img-hash.c rctx->fallback_req.base.flags = req->base.flags base 567 drivers/crypto/img-hash.c rctx->fallback_req.base.flags = req->base.flags base 581 drivers/crypto/img-hash.c rctx->fallback_req.base.flags = req->base.flags base 597 drivers/crypto/img-hash.c rctx->fallback_req.base.flags = req->base.flags base 610 drivers/crypto/img-hash.c rctx->fallback_req.base.flags = req->base.flags base 766 drivers/crypto/img-hash.c .base = { base 792 drivers/crypto/img-hash.c .base = { base 818 drivers/crypto/img-hash.c .base = { base 844 drivers/crypto/img-hash.c .base = { base 45 drivers/crypto/inside-secure/safexcel.c writel(0, priv->base + EIP197_FLUE_IFC_LUT(i)); base 52 drivers/crypto/inside-secure/safexcel.c writel(0, priv->base + EIP197_FLUE_CACHEBASE_LO(i)); base 53 drivers/crypto/inside-secure/safexcel.c writel(0, priv->base + EIP197_FLUE_CACHEBASE_HI(i)); base 55 drivers/crypto/inside-secure/safexcel.c priv->base + EIP197_FLUE_CONFIG(i)); base 57 drivers/crypto/inside-secure/safexcel.c writel(0, priv->base + EIP197_FLUE_OFFSETS); base 58 drivers/crypto/inside-secure/safexcel.c writel(0, priv->base + EIP197_FLUE_ARC4_OFFSET); base 69 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_CS_RAM_CTRL); base 72 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_CS_RAM_CTRL); base 95 drivers/crypto/inside-secure/safexcel.c priv->base + EIP197_CLASSIFICATION_RAMS + base 101 drivers/crypto/inside-secure/safexcel.c priv->base + EIP197_CLASSIFICATION_RAMS + base 106 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_CLASSIFICATION_RAMS + base 132 drivers/crypto/inside-secure/safexcel.c priv->base + offset); base 139 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + offset + 4); base 141 drivers/crypto/inside-secure/safexcel.c writel(0, priv->base + offset + 8); base 142 drivers/crypto/inside-secure/safexcel.c writel(0, priv->base + offset + 12); base 149 drivers/crypto/inside-secure/safexcel.c priv->base + EIP197_CLASSIFICATION_RAMS + base 167 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_CS_RAM_CTRL); base 170 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_CS_RAM_CTRL); base 171 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_CS_RAM_CTRL); base 175 drivers/crypto/inside-secure/safexcel.c writel(0, priv->base + EIP197_TRC_ECCCTRL); base 181 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_TRC_PARAMS); base 183 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_TRC_PARAMS); base 193 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_TRC_PARAMS); base 196 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_TRC_PARAMS); base 202 drivers/crypto/inside-secure/safexcel.c writel(0, priv->base + EIP197_TRC_ECCCTRL); base 232 drivers/crypto/inside-secure/safexcel.c val = readl(priv->base + EIP197_CS_RAM_CTRL); base 234 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_CS_RAM_CTRL); base 239 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_TRC_FREECHAIN); base 244 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_TRC_PARAMS2); base 250 drivers/crypto/inside-secure/safexcel.c writel(val, priv->base + EIP197_TRC_PARAMS); base 307 drivers/crypto/inside-secure/safexcel.c priv->base + EIP197_CLASSIFICATION_RAMS + i * sizeof(u32)); base 320 drivers/crypto/inside-secure/safexcel.c u32 base, pollofs; base 328 drivers/crypto/inside-secure/safexcel.c base = EIP197_PE_ICE_SCRATCH_RAM(pe); base 331 drivers/crypto/inside-secure/safexcel.c (readl_relaxed(EIP197_PE(priv) + base + base 1326 drivers/crypto/inside-secure/safexcel.c version = readl(priv->base + EIP97_HIA_AIC_BASE + EIP197_HIA_VERSION); base 1337 drivers/crypto/inside-secure/safexcel.c version = readl(priv->base + EIP197_HIA_AIC_BASE + base 1568 drivers/crypto/inside-secure/safexcel.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 1569 drivers/crypto/inside-secure/safexcel.c if (IS_ERR(priv->base)) { base 1571 drivers/crypto/inside-secure/safexcel.c return PTR_ERR(priv->base); base 1709 drivers/crypto/inside-secure/safexcel.c priv->base = pcim_iomap_table(pdev)[0]; base 1747 drivers/crypto/inside-secure/safexcel.c writel(1, priv->base + EIP197_XLX_GPIO_BASE); base 1750 drivers/crypto/inside-secure/safexcel.c writel(0, priv->base + EIP197_XLX_GPIO_BASE); base 36 drivers/crypto/inside-secure/safexcel.h #define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \ base 72 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic) base 73 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g) base 74 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r) base 75 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr) base 76 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe) base 77 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr) base 78 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse) base 79 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr) base 80 drivers/crypto/inside-secure/safexcel.h #define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg) base 81 drivers/crypto/inside-secure/safexcel.h #define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe) base 82 drivers/crypto/inside-secure/safexcel.h #define EIP197_GLOBAL(priv) ((priv)->base + (priv)->offsets.global) base 580 drivers/crypto/inside-secure/safexcel.h void *base; base 713 drivers/crypto/inside-secure/safexcel.h void __iomem *base; base 39 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_context base; base 285 drivers/crypto/inside-secure/safexcel_cipher.c if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) { base 288 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = true; base 346 drivers/crypto/inside-secure/safexcel_cipher.c if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma && base 348 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = true; base 385 drivers/crypto/inside-secure/safexcel_cipher.c if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma && base 388 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = true; base 548 drivers/crypto/inside-secure/safexcel_cipher.c static int safexcel_send_req(struct crypto_async_request *base, int ring, base 555 drivers/crypto/inside-secure/safexcel_cipher.c struct skcipher_request *areq = skcipher_request_cast(base); base 557 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(base->tfm); base 582 drivers/crypto/inside-secure/safexcel_cipher.c memcpy(ctx->base.ctxr->data + ctx->key_len / sizeof(u32), base 585 drivers/crypto/inside-secure/safexcel_cipher.c memcpy(ctx->base.ctxr->data + (ctx->key_len + base 638 drivers/crypto/inside-secure/safexcel_cipher.c memcpy(ctx->base.ctxr->data, ctx->key, ctx->key_len); base 655 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.ctxr_dma); base 678 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.ctxr_dma); base 683 drivers/crypto/inside-secure/safexcel_cipher.c safexcel_context_control(ctx, base, sreq, first_cdesc); base 749 drivers/crypto/inside-secure/safexcel_cipher.c safexcel_rdr_req_set(priv, ring, first_rdesc, base); base 774 drivers/crypto/inside-secure/safexcel_cipher.c struct crypto_async_request *base, base 778 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(base->tfm); base 804 drivers/crypto/inside-secure/safexcel_cipher.c if (ctx->base.exit_inv) { base 805 drivers/crypto/inside-secure/safexcel_cipher.c dma_pool_free(priv->context_pool, ctx->base.ctxr, base 806 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.ctxr_dma); base 814 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.ring = ring; base 817 drivers/crypto/inside-secure/safexcel_cipher.c enq_ret = crypto_enqueue_request(&priv->ring[ring].queue, base); base 877 drivers/crypto/inside-secure/safexcel_cipher.c static int safexcel_cipher_send_inv(struct crypto_async_request *base, base 880 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(base->tfm); base 884 drivers/crypto/inside-secure/safexcel_cipher.c ret = safexcel_invalidate_cache(base, priv, ctx->base.ctxr_dma, ring); base 898 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 931 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 950 drivers/crypto/inside-secure/safexcel_cipher.c struct crypto_async_request *base, base 956 drivers/crypto/inside-secure/safexcel_cipher.c int ring = ctx->base.ring; base 960 drivers/crypto/inside-secure/safexcel_cipher.c ctx = crypto_tfm_ctx(base->tfm); base 961 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.exit_inv = true; base 965 drivers/crypto/inside-secure/safexcel_cipher.c crypto_enqueue_request(&priv->ring[ring].queue, base); base 995 drivers/crypto/inside-secure/safexcel_cipher.c return safexcel_cipher_exit_inv(tfm, &req->base, sreq, &result); base 1010 drivers/crypto/inside-secure/safexcel_cipher.c return safexcel_cipher_exit_inv(tfm, &req->base, sreq, &result); base 1013 drivers/crypto/inside-secure/safexcel_cipher.c static int safexcel_queue_req(struct crypto_async_request *base, base 1017 drivers/crypto/inside-secure/safexcel_cipher.c struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(base->tfm); base 1024 drivers/crypto/inside-secure/safexcel_cipher.c if (ctx->base.ctxr) { base 1025 drivers/crypto/inside-secure/safexcel_cipher.c if (priv->flags & EIP197_TRC_CACHE && ctx->base.needs_inv) { base 1027 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = false; base 1030 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.ring = safexcel_select_ring(priv); base 1031 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.ctxr = dma_pool_zalloc(priv->context_pool, base 1032 drivers/crypto/inside-secure/safexcel_cipher.c EIP197_GFP_FLAGS(*base), base 1033 drivers/crypto/inside-secure/safexcel_cipher.c &ctx->base.ctxr_dma); base 1034 drivers/crypto/inside-secure/safexcel_cipher.c if (!ctx->base.ctxr) base 1038 drivers/crypto/inside-secure/safexcel_cipher.c ring = ctx->base.ring; base 1041 drivers/crypto/inside-secure/safexcel_cipher.c ret = crypto_enqueue_request(&priv->ring[ring].queue, base); base 1052 drivers/crypto/inside-secure/safexcel_cipher.c return safexcel_queue_req(&req->base, skcipher_request_ctx(req), base 1058 drivers/crypto/inside-secure/safexcel_cipher.c return safexcel_queue_req(&req->base, skcipher_request_ctx(req), base 1067 drivers/crypto/inside-secure/safexcel_cipher.c alg.skcipher.base); base 1074 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.send = safexcel_skcipher_send; base 1075 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.handle_result = safexcel_skcipher_handle_result; base 1086 drivers/crypto/inside-secure/safexcel_cipher.c if (!ctx->base.ctxr) base 1089 drivers/crypto/inside-secure/safexcel_cipher.c memzero_explicit(ctx->base.ctxr->data, sizeof(ctx->base.ctxr->data)); base 1108 drivers/crypto/inside-secure/safexcel_cipher.c dma_pool_free(priv->context_pool, ctx->base.ctxr, base 1109 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.ctxr_dma); base 1128 drivers/crypto/inside-secure/safexcel_cipher.c dma_pool_free(priv->context_pool, ctx->base.ctxr, base 1129 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.ctxr_dma); base 1152 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1188 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1224 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1260 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1296 drivers/crypto/inside-secure/safexcel_cipher.c if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) { base 1299 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = true; base 1335 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1362 drivers/crypto/inside-secure/safexcel_cipher.c if (ctx->base.ctxr_dma) base 1364 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = true; base 1392 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1427 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1454 drivers/crypto/inside-secure/safexcel_cipher.c if (ctx->base.ctxr_dma) { base 1456 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = true; base 1486 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1521 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1541 drivers/crypto/inside-secure/safexcel_cipher.c return safexcel_queue_req(&req->base, creq, SAFEXCEL_ENCRYPT); base 1548 drivers/crypto/inside-secure/safexcel_cipher.c return safexcel_queue_req(&req->base, creq, SAFEXCEL_DECRYPT); base 1556 drivers/crypto/inside-secure/safexcel_cipher.c alg.aead.base); base 1566 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.send = safexcel_aead_send; base 1567 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.handle_result = safexcel_aead_handle_result; base 1590 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1625 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1660 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1695 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1730 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1764 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1798 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1832 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1866 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1900 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1934 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 1973 drivers/crypto/inside-secure/safexcel_cipher.c if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) { base 1976 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = true; base 1992 drivers/crypto/inside-secure/safexcel_cipher.c if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) { base 1996 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = true; base 2027 drivers/crypto/inside-secure/safexcel_cipher.c return safexcel_queue_req(&req->base, skcipher_request_ctx(req), base 2035 drivers/crypto/inside-secure/safexcel_cipher.c return safexcel_queue_req(&req->base, skcipher_request_ctx(req), base 2050 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 2083 drivers/crypto/inside-secure/safexcel_cipher.c if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) { base 2086 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = true; base 2110 drivers/crypto/inside-secure/safexcel_cipher.c if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) { base 2113 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = true; base 2168 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 2200 drivers/crypto/inside-secure/safexcel_cipher.c if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) { base 2203 drivers/crypto/inside-secure/safexcel_cipher.c ctx->base.needs_inv = true; base 2268 drivers/crypto/inside-secure/safexcel_cipher.c return safexcel_queue_req(&req->base, creq, SAFEXCEL_ENCRYPT); base 2278 drivers/crypto/inside-secure/safexcel_cipher.c return safexcel_queue_req(&req->base, creq, SAFEXCEL_DECRYPT); base 2291 drivers/crypto/inside-secure/safexcel_cipher.c .base = { base 18 drivers/crypto/inside-secure/safexcel_hash.c struct safexcel_context base; base 112 drivers/crypto/inside-secure/safexcel_hash.c memcpy(ctx->base.ctxr->data, req->state, req->state_sz); base 148 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.ctxr->data[req->state_sz >> 2] = base 156 drivers/crypto/inside-secure/safexcel_hash.c memcpy(ctx->base.ctxr->data + (req->state_sz >> 2), base 233 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.needs_inv = true; base 310 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.ctxr_dma); base 346 drivers/crypto/inside-secure/safexcel_hash.c sglen, len, ctx->base.ctxr_dma); base 383 drivers/crypto/inside-secure/safexcel_hash.c safexcel_rdr_req_set(priv, ring, rdesc, &areq->base); base 434 drivers/crypto/inside-secure/safexcel_hash.c if (ctx->base.exit_inv) { base 435 drivers/crypto/inside-secure/safexcel_hash.c dma_pool_free(priv->context_pool, ctx->base.ctxr, base 436 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.ctxr_dma); base 443 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.ring = ring; base 490 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.ctxr_dma, ring); base 522 drivers/crypto/inside-secure/safexcel_hash.c int ring = ctx->base.ring; base 532 drivers/crypto/inside-secure/safexcel_hash.c ctx = crypto_tfm_ctx(req->base.tfm); base 533 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.exit_inv = true; base 537 drivers/crypto/inside-secure/safexcel_hash.c crypto_enqueue_request(&priv->ring[ring].queue, &req->base); base 591 drivers/crypto/inside-secure/safexcel_hash.c if (ctx->base.ctxr) { base 592 drivers/crypto/inside-secure/safexcel_hash.c if (priv->flags & EIP197_TRC_CACHE && !ctx->base.needs_inv && base 598 drivers/crypto/inside-secure/safexcel_hash.c memcmp(ctx->base.ctxr->data, req->state, req->state_sz) || base 603 drivers/crypto/inside-secure/safexcel_hash.c memcmp(ctx->base.ctxr->data + (req->state_sz>>2), base 611 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.needs_inv = true; base 613 drivers/crypto/inside-secure/safexcel_hash.c if (ctx->base.needs_inv) { base 614 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.needs_inv = false; base 618 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.ring = safexcel_select_ring(priv); base 619 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.ctxr = dma_pool_zalloc(priv->context_pool, base 620 drivers/crypto/inside-secure/safexcel_hash.c EIP197_GFP_FLAGS(areq->base), base 621 drivers/crypto/inside-secure/safexcel_hash.c &ctx->base.ctxr_dma); base 622 drivers/crypto/inside-secure/safexcel_hash.c if (!ctx->base.ctxr) base 626 drivers/crypto/inside-secure/safexcel_hash.c ring = ctx->base.ring; base 629 drivers/crypto/inside-secure/safexcel_hash.c ret = crypto_enqueue_request(&priv->ring[ring].queue, &areq->base); base 793 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.send = safexcel_ahash_send; base 794 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.handle_result = safexcel_handle_result; base 833 drivers/crypto/inside-secure/safexcel_hash.c if (!ctx->base.ctxr) base 841 drivers/crypto/inside-secure/safexcel_hash.c dma_pool_free(priv->context_pool, ctx->base.ctxr, base 842 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.ctxr_dma); base 860 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 1069 drivers/crypto/inside-secure/safexcel_hash.c if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr && base 1072 drivers/crypto/inside-secure/safexcel_hash.c ctx->base.needs_inv = true; base 1102 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 1157 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 1212 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 1282 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 1352 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 1407 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 1462 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 1532 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 1602 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 1657 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 1728 drivers/crypto/inside-secure/safexcel_hash.c .base = { base 18 drivers/crypto/inside-secure/safexcel_ring.c cdr->base = dmam_alloc_coherent(priv->dev, base 21 drivers/crypto/inside-secure/safexcel_ring.c if (!cdr->base) base 23 drivers/crypto/inside-secure/safexcel_ring.c cdr->write = cdr->base; base 24 drivers/crypto/inside-secure/safexcel_ring.c cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1); base 25 drivers/crypto/inside-secure/safexcel_ring.c cdr->read = cdr->base; base 28 drivers/crypto/inside-secure/safexcel_ring.c rdr->base = dmam_alloc_coherent(priv->dev, base 31 drivers/crypto/inside-secure/safexcel_ring.c if (!rdr->base) base 33 drivers/crypto/inside-secure/safexcel_ring.c rdr->write = rdr->base; base 34 drivers/crypto/inside-secure/safexcel_ring.c rdr->base_end = rdr->base + rdr->offset * (EIP197_DEFAULT_RING_SIZE - 1); base 35 drivers/crypto/inside-secure/safexcel_ring.c rdr->read = rdr->base; base 51 drivers/crypto/inside-secure/safexcel_ring.c (ring->read == ring->base && ring->write == ring->base_end)) base 55 drivers/crypto/inside-secure/safexcel_ring.c ring->write = ring->base; base 71 drivers/crypto/inside-secure/safexcel_ring.c ring->read = ring->base; base 91 drivers/crypto/inside-secure/safexcel_ring.c return (rdr->read - rdr->base) / rdr->offset; base 100 drivers/crypto/inside-secure/safexcel_ring.c return ((void *)rdesc - rdr->base) / rdr->offset; base 109 drivers/crypto/inside-secure/safexcel_ring.c if (ring->write == ring->base) base 377 drivers/crypto/ixp4xx_crypto.c req->base.complete(&req->base, failed); base 388 drivers/crypto/ixp4xx_crypto.c req->base.complete(&req->base, failed); base 816 drivers/crypto/ixp4xx_crypto.c u32 *flags = &tfm->base.crt_flags; base 828 drivers/crypto/ixp4xx_crypto.c ret = setup_cipher(&tfm->base, 0, key, key_len); base 831 drivers/crypto/ixp4xx_crypto.c ret = setup_cipher(&tfm->base, 1, key, key_len); base 883 drivers/crypto/ixp4xx_crypto.c gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? base 989 drivers/crypto/ixp4xx_crypto.c gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? base 1093 drivers/crypto/ixp4xx_crypto.c u32 *flags = &tfm->base.crt_flags; base 1105 drivers/crypto/ixp4xx_crypto.c ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len); base 1108 drivers/crypto/ixp4xx_crypto.c ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len); base 1111 drivers/crypto/ixp4xx_crypto.c ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey, base 1115 drivers/crypto/ixp4xx_crypto.c ret = setup_auth(&tfm->base, 1, authsize, ctx->authkey, base 1324 drivers/crypto/ixp4xx_crypto.c .base = { base 1336 drivers/crypto/ixp4xx_crypto.c .base = { base 1349 drivers/crypto/ixp4xx_crypto.c .base = { base 1361 drivers/crypto/ixp4xx_crypto.c .base = { base 1374 drivers/crypto/ixp4xx_crypto.c .base = { base 1386 drivers/crypto/ixp4xx_crypto.c .base = { base 1464 drivers/crypto/ixp4xx_crypto.c if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, base 1465 drivers/crypto/ixp4xx_crypto.c "%s"IXP_POSTFIX, cra->base.cra_name) >= base 1472 drivers/crypto/ixp4xx_crypto.c cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | base 1481 drivers/crypto/ixp4xx_crypto.c cra->base.cra_ctxsize = sizeof(struct ixp_ctx); base 1482 drivers/crypto/ixp4xx_crypto.c cra->base.cra_module = THIS_MODULE; base 1483 drivers/crypto/ixp4xx_crypto.c cra->base.cra_alignmask = 3; base 1484 drivers/crypto/ixp4xx_crypto.c cra->base.cra_priority = 300; base 1488 drivers/crypto/ixp4xx_crypto.c cra->base.cra_driver_name); base 333 drivers/crypto/marvell/cesa.c writel(cs->base, iobase + CESA_TDMA_WINDOW_BASE(i)); base 496 drivers/crypto/marvell/cesa.h struct mv_cesa_ctx base; base 507 drivers/crypto/marvell/cesa.h struct mv_cesa_ctx base; base 562 drivers/crypto/marvell/cesa.h struct mv_cesa_req base; base 601 drivers/crypto/marvell/cesa.h struct mv_cesa_req base; base 18 drivers/crypto/marvell/cipher.c struct mv_cesa_ctx base; base 23 drivers/crypto/marvell/cipher.c struct mv_cesa_ctx base; base 28 drivers/crypto/marvell/cipher.c struct mv_cesa_ctx base; base 33 drivers/crypto/marvell/cipher.c struct mv_cesa_dma_iter base; base 42 drivers/crypto/marvell/cipher.c mv_cesa_req_dma_iter_init(&iter->base, req->cryptlen); base 53 drivers/crypto/marvell/cipher.c return mv_cesa_req_dma_iter_next_op(&iter->base); base 70 drivers/crypto/marvell/cipher.c mv_cesa_dma_cleanup(&creq->base); base 77 drivers/crypto/marvell/cipher.c if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) base 85 drivers/crypto/marvell/cipher.c struct mv_cesa_engine *engine = creq->base.engine; base 119 drivers/crypto/marvell/cipher.c struct mv_cesa_engine *engine = creq->base.engine; base 138 drivers/crypto/marvell/cipher.c struct mv_cesa_req *basereq = &creq->base; base 151 drivers/crypto/marvell/cipher.c if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) base 152 drivers/crypto/marvell/cipher.c mv_cesa_dma_step(&creq->base); base 161 drivers/crypto/marvell/cipher.c struct mv_cesa_req *basereq = &creq->base; base 181 drivers/crypto/marvell/cipher.c creq->base.engine = engine; base 183 drivers/crypto/marvell/cipher.c if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) base 202 drivers/crypto/marvell/cipher.c struct mv_cesa_engine *engine = creq->base.engine; base 208 drivers/crypto/marvell/cipher.c if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) { base 211 drivers/crypto/marvell/cipher.c basereq = &creq->base; base 306 drivers/crypto/marvell/cipher.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 308 drivers/crypto/marvell/cipher.c struct mv_cesa_req *basereq = &creq->base; base 348 drivers/crypto/marvell/cipher.c mv_cesa_set_crypt_op_len(op, iter.base.op_len); base 351 drivers/crypto/marvell/cipher.c ret = mv_cesa_dma_add_op_transfers(&basereq->chain, &iter.base, base 362 drivers/crypto/marvell/cipher.c ret = mv_cesa_dma_add_op_transfers(&basereq->chain, &iter.base, base 400 drivers/crypto/marvell/cipher.c struct mv_cesa_req *basereq = &creq->base; base 455 drivers/crypto/marvell/cipher.c mv_cesa_skcipher_prepare(&req->base, engine); base 457 drivers/crypto/marvell/cipher.c ret = mv_cesa_queue_req(&req->base, &creq->base); base 459 drivers/crypto/marvell/cipher.c if (mv_cesa_req_needs_cleanup(&req->base, ret)) base 468 drivers/crypto/marvell/cipher.c struct mv_cesa_des_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 506 drivers/crypto/marvell/cipher.c .base = { base 556 drivers/crypto/marvell/cipher.c .base = { base 573 drivers/crypto/marvell/cipher.c struct mv_cesa_des3_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 614 drivers/crypto/marvell/cipher.c .base = { base 667 drivers/crypto/marvell/cipher.c .base = { base 684 drivers/crypto/marvell/cipher.c struct mv_cesa_aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 739 drivers/crypto/marvell/cipher.c .base = { base 788 drivers/crypto/marvell/cipher.c .base = { base 19 drivers/crypto/marvell/hash.c struct mv_cesa_dma_iter base; base 33 drivers/crypto/marvell/hash.c mv_cesa_req_dma_iter_init(&iter->base, len); base 43 drivers/crypto/marvell/hash.c return mv_cesa_req_dma_iter_next_op(&iter->base); base 104 drivers/crypto/marvell/hash.c mv_cesa_dma_cleanup(&creq->base); base 111 drivers/crypto/marvell/hash.c if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) base 119 drivers/crypto/marvell/hash.c if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) base 157 drivers/crypto/marvell/hash.c struct mv_cesa_engine *engine = creq->base.engine; base 267 drivers/crypto/marvell/hash.c struct mv_cesa_req *basereq = &creq->base; base 283 drivers/crypto/marvell/hash.c struct mv_cesa_req *base = &creq->base; base 286 drivers/crypto/marvell/hash.c if (base->chain.first->flags & CESA_TDMA_SET_STATE) { base 287 drivers/crypto/marvell/hash.c struct mv_cesa_engine *engine = base->engine; base 296 drivers/crypto/marvell/hash.c mv_cesa_dma_step(base); base 304 drivers/crypto/marvell/hash.c if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) base 315 drivers/crypto/marvell/hash.c if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) base 316 drivers/crypto/marvell/hash.c return mv_cesa_dma_process(&creq->base, status); base 325 drivers/crypto/marvell/hash.c struct mv_cesa_engine *engine = creq->base.engine; base 331 drivers/crypto/marvell/hash.c if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ && base 332 drivers/crypto/marvell/hash.c (creq->base.chain.last->flags & CESA_TDMA_TYPE_MSK) == CESA_TDMA_RESULT) { base 339 drivers/crypto/marvell/hash.c data = creq->base.chain.last->op->ctx.hash.hash; base 376 drivers/crypto/marvell/hash.c creq->base.engine = engine; base 378 drivers/crypto/marvell/hash.c if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) base 430 drivers/crypto/marvell/hash.c ctx->base.ops = &mv_cesa_ahash_req_ops; base 597 drivers/crypto/marvell/hash.c gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 599 drivers/crypto/marvell/hash.c struct mv_cesa_req *basereq = &creq->base; base 641 drivers/crypto/marvell/hash.c &iter.base, base 646 drivers/crypto/marvell/hash.c frag_len = iter.base.op_len; base 660 drivers/crypto/marvell/hash.c frag_len = iter.base.op_len; base 697 drivers/crypto/marvell/hash.c iter.base.len; base 763 drivers/crypto/marvell/hash.c mv_cesa_ahash_prepare(&req->base, engine); base 765 drivers/crypto/marvell/hash.c ret = mv_cesa_queue_req(&req->base, &creq->base); base 767 drivers/crypto/marvell/hash.c if (mv_cesa_req_needs_cleanup(&req->base, ret)) base 913 drivers/crypto/marvell/hash.c .base = { base 983 drivers/crypto/marvell/hash.c .base = { base 1056 drivers/crypto/marvell/hash.c .base = { base 1227 drivers/crypto/marvell/hash.c ctx->base.ops = &mv_cesa_ahash_req_ops; base 1236 drivers/crypto/marvell/hash.c struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 1290 drivers/crypto/marvell/hash.c .base = { base 1306 drivers/crypto/marvell/hash.c struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 1360 drivers/crypto/marvell/hash.c .base = { base 1396 drivers/crypto/marvell/hash.c struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 1430 drivers/crypto/marvell/hash.c .base = { base 122 drivers/crypto/mediatek/mtk-aes.c struct mtk_aes_base_ctx base; base 126 drivers/crypto/mediatek/mtk-aes.c struct mtk_aes_base_ctx base; base 135 drivers/crypto/mediatek/mtk-aes.c struct mtk_aes_base_ctx base; base 156 drivers/crypto/mediatek/mtk-aes.c return readl_relaxed(cryp->base + offset); base 162 drivers/crypto/mediatek/mtk-aes.c writel_relaxed(value, cryp->base + offset); base 567 drivers/crypto/mediatek/mtk-aes.c return container_of(ctx, struct mtk_aes_ctr_ctx, base); base 679 drivers/crypto/mediatek/mtk-aes.c &req->base); base 737 drivers/crypto/mediatek/mtk-aes.c ctx->base.start = mtk_aes_start; base 746 drivers/crypto/mediatek/mtk-aes.c ctx->base.start = mtk_aes_ctr_start; base 860 drivers/crypto/mediatek/mtk-aes.c return container_of(ctx, struct mtk_aes_gcm_ctx, base); base 1004 drivers/crypto/mediatek/mtk-aes.c return mtk_aes_handle_queue(cryp, enc, &req->base); base 1126 drivers/crypto/mediatek/mtk-aes.c ctx->base.start = mtk_aes_gcm_start; base 1147 drivers/crypto/mediatek/mtk-aes.c .base = { base 123 drivers/crypto/mediatek/mtk-platform.c writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DFE_THR_CTRL); base 124 drivers/crypto/mediatek/mtk-platform.c writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DSE_THR_CTRL); base 140 drivers/crypto/mediatek/mtk-platform.c cryp->base + DFE_CFG); base 144 drivers/crypto/mediatek/mtk-platform.c cryp->base + DSE_CFG); base 148 drivers/crypto/mediatek/mtk-platform.c cryp->base + PE_IN_DBUF_THRESH); base 152 drivers/crypto/mediatek/mtk-platform.c cryp->base + PE_IN_TBUF_THRESH); base 156 drivers/crypto/mediatek/mtk-platform.c cryp->base + PE_OUT_DBUF_THRESH); base 158 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + PE_OUT_TBUF_THRESH); base 159 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + PE_OUT_BUF_CTRL); base 168 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + DFE_THR_STAT); base 170 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + DSE_THR_STAT); base 177 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + DFE_THR_CTRL); base 178 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + DSE_THR_CTRL); base 191 drivers/crypto/mediatek/mtk-platform.c writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DFE_THR_CTRL); base 192 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + DFE_PRIO_0); base 193 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + DFE_PRIO_1); base 194 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + DFE_PRIO_2); base 195 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + DFE_PRIO_3); base 197 drivers/crypto/mediatek/mtk-platform.c writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DSE_THR_CTRL); base 198 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + DSE_PRIO_0); base 199 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + DSE_PRIO_1); base 200 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + DSE_PRIO_2); base 201 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + DSE_PRIO_3); base 218 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + CDR_CFG(i)); base 221 drivers/crypto/mediatek/mtk-platform.c writel(MTK_CNT_RST, cryp->base + CDR_PREP_COUNT(i)); base 222 drivers/crypto/mediatek/mtk-platform.c writel(MTK_CNT_RST, cryp->base + CDR_PROC_COUNT(i)); base 224 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + CDR_PREP_PNTR(i)); base 225 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + CDR_PROC_PNTR(i)); base 226 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + CDR_DMA_CFG(i)); base 229 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + CDR_BASE_ADDR_HI(i)); base 230 drivers/crypto/mediatek/mtk-platform.c writel(cryp->ring[i]->cmd_dma, cryp->base + CDR_BASE_ADDR_LO(i)); base 232 drivers/crypto/mediatek/mtk-platform.c writel(MTK_DESC_RING_SZ, cryp->base + CDR_RING_SIZE(i)); base 235 drivers/crypto/mediatek/mtk-platform.c writel(MTK_CDR_STAT_CLR, cryp->base + CDR_STAT(i)); base 244 drivers/crypto/mediatek/mtk-platform.c cryp->base + CDR_DESC_SIZE(i)); base 248 drivers/crypto/mediatek/mtk-platform.c cryp->base + CDR_CFG(i)); base 258 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + RDR_CFG(i)); base 261 drivers/crypto/mediatek/mtk-platform.c writel(MTK_CNT_RST, cryp->base + RDR_PREP_COUNT(i)); base 262 drivers/crypto/mediatek/mtk-platform.c writel(MTK_CNT_RST, cryp->base + RDR_PROC_COUNT(i)); base 264 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + RDR_PREP_PNTR(i)); base 265 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + RDR_PROC_PNTR(i)); base 266 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + RDR_DMA_CFG(i)); base 269 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + RDR_BASE_ADDR_HI(i)); base 270 drivers/crypto/mediatek/mtk-platform.c writel(cryp->ring[i]->res_dma, cryp->base + RDR_BASE_ADDR_LO(i)); base 272 drivers/crypto/mediatek/mtk-platform.c writel(MTK_DESC_RING_SZ, cryp->base + RDR_RING_SIZE(i)); base 273 drivers/crypto/mediatek/mtk-platform.c writel(MTK_RDR_STAT_CLR, cryp->base + RDR_STAT(i)); base 281 drivers/crypto/mediatek/mtk-platform.c cryp->base + RDR_THRESH(i)); base 289 drivers/crypto/mediatek/mtk-platform.c cryp->base + RDR_DESC_SIZE(i)); base 298 drivers/crypto/mediatek/mtk-platform.c cryp->base + RDR_CFG(i)); base 307 drivers/crypto/mediatek/mtk-platform.c cap.hia_ver = readl(cryp->base + HIA_VERSION); base 308 drivers/crypto/mediatek/mtk-platform.c cap.hia_opt = readl(cryp->base + HIA_OPTIONS); base 309 drivers/crypto/mediatek/mtk-platform.c cap.hw_opt = readl(cryp->base + EIP97_OPTIONS); base 315 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + EIP97_MST_CTRL); base 318 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + HIA_MST_CTRL); base 321 drivers/crypto/mediatek/mtk-platform.c writel(val, cryp->base + HIA_MST_CTRL); base 340 drivers/crypto/mediatek/mtk-platform.c cryp->base + PE_TOKEN_CTRL_STAT); base 343 drivers/crypto/mediatek/mtk-platform.c writel(MTK_AIC_G_CLR, cryp->base + AIC_G_ACK); base 350 drivers/crypto/mediatek/mtk-platform.c cryp->base + PE_INTERRUPT_CTRL_STAT); base 360 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + AIC_G_VERSION); base 362 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + AIC_VERSION(hw)); base 369 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + AIC_G_OPTIONS); base 371 drivers/crypto/mediatek/mtk-platform.c val = readl(cryp->base + AIC_OPTIONS(hw)); base 390 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + AIC_G_ENABLE_CTRL); base 391 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + AIC_G_POL_CTRL); base 392 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + AIC_G_TYPE_CTRL); base 393 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + AIC_G_ENABLE_SET); base 395 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + AIC_ENABLE_CTRL(hw)); base 396 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + AIC_POL_CTRL(hw)); base 397 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + AIC_TYPE_CTRL(hw)); base 398 drivers/crypto/mediatek/mtk-platform.c writel(0, cryp->base + AIC_ENABLE_SET(hw)); base 491 drivers/crypto/mediatek/mtk-platform.c cryp->base = devm_platform_ioremap_resource(pdev, 0); base 492 drivers/crypto/mediatek/mtk-platform.c if (IS_ERR(cryp->base)) base 493 drivers/crypto/mediatek/mtk-platform.c return PTR_ERR(cryp->base); base 211 drivers/crypto/mediatek/mtk-platform.h void __iomem *base; base 110 drivers/crypto/mediatek/mtk-sha.c struct mtk_sha_hmac_ctx base[0]; base 129 drivers/crypto/mediatek/mtk-sha.c return readl_relaxed(cryp->base + offset); base 135 drivers/crypto/mediatek/mtk-sha.c writel_relaxed(value, cryp->base + offset); base 358 drivers/crypto/mediatek/mtk-sha.c struct mtk_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm); base 359 drivers/crypto/mediatek/mtk-sha.c struct mtk_sha_hmac_ctx *bctx = tctx->base; base 411 drivers/crypto/mediatek/mtk-sha.c struct mtk_sha_hmac_ctx *bctx = tctx->base; base 644 drivers/crypto/mediatek/mtk-sha.c sha->req->base.complete(&sha->req->base, err); base 706 drivers/crypto/mediatek/mtk-sha.c struct mtk_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm); base 803 drivers/crypto/mediatek/mtk-sha.c struct mtk_sha_hmac_ctx *bctx = tctx->base; base 862 drivers/crypto/mediatek/mtk-sha.c struct mtk_sha_hmac_ctx *bctx = tctx->base; base 912 drivers/crypto/mediatek/mtk-sha.c struct mtk_sha_hmac_ctx *bctx = tctx->base; base 929 drivers/crypto/mediatek/mtk-sha.c .halg.base = { base 952 drivers/crypto/mediatek/mtk-sha.c .halg.base = { base 975 drivers/crypto/mediatek/mtk-sha.c .halg.base = { base 999 drivers/crypto/mediatek/mtk-sha.c .halg.base = { base 1025 drivers/crypto/mediatek/mtk-sha.c .halg.base = { base 1051 drivers/crypto/mediatek/mtk-sha.c .halg.base = { base 1079 drivers/crypto/mediatek/mtk-sha.c .halg.base = { base 1102 drivers/crypto/mediatek/mtk-sha.c .halg.base = { base 1126 drivers/crypto/mediatek/mtk-sha.c .halg.base = { base 1152 drivers/crypto/mediatek/mtk-sha.c .halg.base = { base 71 drivers/crypto/mxs-dcp.c void __iomem *base; base 183 drivers/crypto/mxs-dcp.c writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan)); base 186 drivers/crypto/mxs-dcp.c writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan)); base 189 drivers/crypto/mxs-dcp.c writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan)); base 195 drivers/crypto/mxs-dcp.c chan, readl(sdcp->base + MXS_DCP_STAT)); base 199 drivers/crypto/mxs-dcp.c stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan)); base 434 drivers/crypto/mxs-dcp.c skcipher_request_set_callback(subreq, req->base.flags, NULL, NULL); base 451 drivers/crypto/mxs-dcp.c struct crypto_async_request *arq = &req->base; base 464 drivers/crypto/mxs-dcp.c ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base); base 516 drivers/crypto/mxs-dcp.c tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK); base 522 drivers/crypto/mxs-dcp.c tfm->base.crt_flags &= ~CRYPTO_TFM_RES_MASK; base 523 drivers/crypto/mxs-dcp.c tfm->base.crt_flags |= crypto_sync_skcipher_get_flags(actx->fallback) & base 737 drivers/crypto/mxs-dcp.c if (strcmp(halg->base.cra_name, "sha1") == 0) base 778 drivers/crypto/mxs-dcp.c ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base); base 918 drivers/crypto/mxs-dcp.c .base = { base 945 drivers/crypto/mxs-dcp.c .base = { base 966 drivers/crypto/mxs-dcp.c stat = readl(sdcp->base + MXS_DCP_STAT); base 972 drivers/crypto/mxs-dcp.c writel(stat, sdcp->base + MXS_DCP_STAT_CLR); base 1007 drivers/crypto/mxs-dcp.c sdcp->base = devm_platform_ioremap_resource(pdev, 0); base 1008 drivers/crypto/mxs-dcp.c if (IS_ERR(sdcp->base)) base 1009 drivers/crypto/mxs-dcp.c return PTR_ERR(sdcp->base); base 1047 drivers/crypto/mxs-dcp.c ret = stmp_reset_block(sdcp->base); base 1056 drivers/crypto/mxs-dcp.c sdcp->base + MXS_DCP_CTRL); base 1060 drivers/crypto/mxs-dcp.c sdcp->base + MXS_DCP_CHANNELCTRL); base 1069 drivers/crypto/mxs-dcp.c writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT); base 1071 drivers/crypto/mxs-dcp.c writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i)); base 1072 drivers/crypto/mxs-dcp.c writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR); base 1102 drivers/crypto/mxs-dcp.c sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1); base 1118 drivers/crypto/mxs-dcp.c dcp_sha1_alg.halg.base.cra_name); base 1127 drivers/crypto/mxs-dcp.c dcp_sha256_alg.halg.base.cra_name); base 264 drivers/crypto/n2_core.c ahash_alg = container_of(alg, struct ahash_alg, halg.base); base 279 drivers/crypto/n2_core.c ahash_alg = container_of(alg, struct ahash_alg, halg.base); base 291 drivers/crypto/n2_core.c struct n2_hash_ctx base; base 316 drivers/crypto/n2_core.c rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP; base 328 drivers/crypto/n2_core.c rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP; base 342 drivers/crypto/n2_core.c rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP; base 355 drivers/crypto/n2_core.c rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP; base 439 drivers/crypto/n2_core.c ctx->base.fallback_tfm = fallback_tfm; base 454 drivers/crypto/n2_core.c crypto_free_ahash(ctx->base.fallback_tfm); base 467 drivers/crypto/n2_core.c fallback_tfm = ctx->base.fallback_tfm; base 541 drivers/crypto/n2_core.c rctx->fallback_req.base.flags = base 542 drivers/crypto/n2_core.c req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP; base 611 drivers/crypto/n2_core.c struct n2_ahash_alg *n2alg = n2_ahash_alg(req->base.tfm); base 629 drivers/crypto/n2_core.c struct n2_hmac_alg *n2alg = n2_hmac_alg(req->base.tfm); base 642 drivers/crypto/n2_core.c rctx->fallback_req.base.flags = base 643 drivers/crypto/n2_core.c req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP; base 981 drivers/crypto/n2_core.c struct crypto_tfm *tfm = req->base.tfm; base 1033 drivers/crypto/n2_core.c struct crypto_tfm *tfm = req->base.tfm; base 1414 drivers/crypto/n2_core.c struct crypto_alg *base; base 1420 drivers/crypto/n2_core.c p->child_alg = n2ahash->alg.halg.base.cra_name; base 1428 drivers/crypto/n2_core.c base = &ahash->halg.base; base 1429 drivers/crypto/n2_core.c snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "hmac(%s)", p->child_alg); base 1430 drivers/crypto/n2_core.c snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "hmac-%s-n2", p->child_alg); base 1432 drivers/crypto/n2_core.c base->cra_ctxsize = sizeof(struct n2_hmac_ctx); base 1433 drivers/crypto/n2_core.c base->cra_init = n2_hmac_cra_init; base 1434 drivers/crypto/n2_core.c base->cra_exit = n2_hmac_cra_exit; base 1439 drivers/crypto/n2_core.c pr_err("%s alg registration failed\n", base->cra_name); base 1443 drivers/crypto/n2_core.c pr_info("%s alg registered\n", base->cra_name); base 1452 drivers/crypto/n2_core.c struct crypto_alg *base; base 1478 drivers/crypto/n2_core.c base = &halg->base; base 1479 drivers/crypto/n2_core.c snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name); base 1480 drivers/crypto/n2_core.c snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->name); base 1481 drivers/crypto/n2_core.c base->cra_priority = N2_CRA_PRIORITY; base 1482 drivers/crypto/n2_core.c base->cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | base 1484 drivers/crypto/n2_core.c base->cra_blocksize = tmpl->block_size; base 1485 drivers/crypto/n2_core.c base->cra_ctxsize = sizeof(struct n2_hash_ctx); base 1486 drivers/crypto/n2_core.c base->cra_module = THIS_MODULE; base 1487 drivers/crypto/n2_core.c base->cra_init = n2_hash_cra_init; base 1488 drivers/crypto/n2_core.c base->cra_exit = n2_hash_cra_exit; base 1493 drivers/crypto/n2_core.c pr_err("%s alg registration failed\n", base->cra_name); base 1497 drivers/crypto/n2_core.c pr_info("%s alg registered\n", base->cra_name); base 27 drivers/crypto/nx/nx-aes-ccm.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&tfm->base); base 57 drivers/crypto/nx/nx-aes-ccm.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&tfm->base); base 263 drivers/crypto/nx/nx-aes-ccm.c req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP); base 305 drivers/crypto/nx/nx-aes-ccm.c req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP); base 333 drivers/crypto/nx/nx-aes-ccm.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(req->base.tfm); base 377 drivers/crypto/nx/nx-aes-ccm.c req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP); base 411 drivers/crypto/nx/nx-aes-ccm.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(req->base.tfm); base 446 drivers/crypto/nx/nx-aes-ccm.c req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP); base 482 drivers/crypto/nx/nx-aes-ccm.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(req->base.tfm); base 512 drivers/crypto/nx/nx-aes-ccm.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(req->base.tfm); base 546 drivers/crypto/nx/nx-aes-ccm.c .base = { base 566 drivers/crypto/nx/nx-aes-ccm.c .base = { base 149 drivers/crypto/nx/nx-aes-gcm.c req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP); base 220 drivers/crypto/nx/nx-aes-gcm.c req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP); base 376 drivers/crypto/nx/nx-aes-gcm.c req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP); base 480 drivers/crypto/nx/nx-aes-gcm.c .base = { base 498 drivers/crypto/nx/nx-aes-gcm.c .base = { base 61 drivers/crypto/nx/nx-aes-xcbc.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); base 170 drivers/crypto/nx/nx-aes-xcbc.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); base 295 drivers/crypto/nx/nx-aes-xcbc.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); base 369 drivers/crypto/nx/nx-aes-xcbc.c .base = { base 60 drivers/crypto/nx/nx-sha256.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); base 179 drivers/crypto/nx/nx-sha256.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); base 273 drivers/crypto/nx/nx-sha256.c .base = { base 60 drivers/crypto/nx/nx-sha512.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); base 182 drivers/crypto/nx/nx-sha512.c struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base); base 279 drivers/crypto/nx/nx-sha512.c .base = { base 36 drivers/crypto/omap-aes-gcm.c req->base.complete(&req->base, ret); base 273 drivers/crypto/omap-aes-gcm.c backlog->base.complete(&backlog->base, -EINPROGRESS); base 417 drivers/crypto/omap-aes.c struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base); base 472 drivers/crypto/omap-aes.c struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base); base 524 drivers/crypto/omap-aes.c skcipher_request_set_callback(subreq, req->base.flags, NULL, base 564 drivers/crypto/omap-aes.c crypto_sync_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags & base 765 drivers/crypto/omap-aes.c .base = { base 785 drivers/crypto/omap-aes.c .base = { base 1099 drivers/crypto/omap-aes.c dd->aead_queue.base.max_qlen = value; base 1233 drivers/crypto/omap-aes.c algp = &aalg->base; base 528 drivers/crypto/omap-des.c struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base); base 585 drivers/crypto/omap-des.c struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base); base 175 drivers/crypto/omap-sham.c struct omap_sham_hmac_ctx base[0]; base 305 drivers/crypto/omap-sham.c struct omap_sham_hmac_ctx *bctx = tctx->base; base 467 drivers/crypto/omap-sham.c struct omap_sham_hmac_ctx *bctx = tctx->base; base 983 drivers/crypto/omap-sham.c struct omap_sham_hmac_ctx *bctx = tctx->base; base 1048 drivers/crypto/omap-sham.c struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); base 1049 drivers/crypto/omap-sham.c struct omap_sham_hmac_ctx *bctx = tctx->base; base 1110 drivers/crypto/omap-sham.c if (req->base.complete) base 1111 drivers/crypto/omap-sham.c req->base.complete(&req->base, err); base 1190 drivers/crypto/omap-sham.c struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); base 1231 drivers/crypto/omap-sham.c struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); base 1244 drivers/crypto/omap-sham.c return omap_sham_shash_digest(tctx->fallback, req->base.flags, base 1302 drivers/crypto/omap-sham.c struct omap_sham_hmac_ctx *bctx = tctx->base; base 1367 drivers/crypto/omap-sham.c struct omap_sham_hmac_ctx *bctx = tctx->base; base 1426 drivers/crypto/omap-sham.c struct omap_sham_hmac_ctx *bctx = tctx->base; base 1458 drivers/crypto/omap-sham.c .halg.base = { base 1480 drivers/crypto/omap-sham.c .halg.base = { base 1503 drivers/crypto/omap-sham.c .halg.base = { base 1527 drivers/crypto/omap-sham.c .halg.base = { base 1554 drivers/crypto/omap-sham.c .halg.base = { base 1575 drivers/crypto/omap-sham.c .halg.base = { base 1597 drivers/crypto/omap-sham.c .halg.base = { base 1620 drivers/crypto/omap-sham.c .halg.base = { base 1645 drivers/crypto/omap-sham.c .halg.base = { base 1666 drivers/crypto/omap-sham.c .halg.base = { base 1688 drivers/crypto/omap-sham.c .halg.base = { base 1711 drivers/crypto/omap-sham.c .halg.base = { base 236 drivers/crypto/padlock-sha.c .base = { base 259 drivers/crypto/padlock-sha.c .base = { base 471 drivers/crypto/padlock-sha.c .base = { base 489 drivers/crypto/padlock-sha.c .base = { base 413 drivers/crypto/picoxcell_crypto.c base); base 539 drivers/crypto/picoxcell_crypto.c aead_request_set_callback(subreq, req->base.flags, base 540 drivers/crypto/picoxcell_crypto.c req->base.complete, req->base.data); base 558 drivers/crypto/picoxcell_crypto.c container_of(req->req, struct aead_request, base); base 639 drivers/crypto/picoxcell_crypto.c dev_req->req = &req->base; base 656 drivers/crypto/picoxcell_crypto.c if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 705 drivers/crypto/picoxcell_crypto.c ctx->sw_cipher = crypto_alloc_aead(alg->base.cra_name, 0, base 804 drivers/crypto/picoxcell_crypto.c cipher->base.crt_flags & base 925 drivers/crypto/picoxcell_crypto.c skcipher_request_set_callback(subreq, req->base.flags, NULL, NULL); base 938 drivers/crypto/picoxcell_crypto.c struct crypto_alg *alg = req->base.tfm->__crt_alg; base 944 drivers/crypto/picoxcell_crypto.c dev_req->req = &req->base; base 986 drivers/crypto/picoxcell_crypto.c if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) { base 1402 drivers/crypto/picoxcell_crypto.c .base = { base 1432 drivers/crypto/picoxcell_crypto.c .base = { base 1462 drivers/crypto/picoxcell_crypto.c .base = { base 1492 drivers/crypto/picoxcell_crypto.c .base = { base 1522 drivers/crypto/picoxcell_crypto.c .base = { base 1553 drivers/crypto/picoxcell_crypto.c .base = { base 1760 drivers/crypto/picoxcell_crypto.c engine->aeads[i].alg.base.cra_name); base 1763 drivers/crypto/picoxcell_crypto.c engine->aeads[i].alg.base.cra_name); base 832 drivers/crypto/qat/qat_common/qat_algs.c areq->base.complete(&areq->base, res); base 853 drivers/crypto/qat/qat_common/qat_algs.c areq->base.complete(&areq->base, res); base 1259 drivers/crypto/qat/qat_common/qat_algs.c .base = { base 1276 drivers/crypto/qat/qat_common/qat_algs.c .base = { base 1293 drivers/crypto/qat/qat_common/qat_algs.c .base = { base 1395 drivers/crypto/qat/qat_common/qat_algs.c qat_aeads[i].base.cra_flags = CRYPTO_ALG_ASYNC; base 1309 drivers/crypto/qat/qat_common/qat_asym_algs.c .base = { base 1326 drivers/crypto/qat/qat_common/qat_asym_algs.c .base = { base 1341 drivers/crypto/qat/qat_common/qat_asym_algs.c rsa.base.cra_flags = 0; base 225 drivers/crypto/qat/qat_common/qat_uclo.c struct icp_qat_uof_batch_init **base) base 229 drivers/crypto/qat/qat_common/qat_uclo.c umem_init = *base; base 237 drivers/crypto/qat/qat_common/qat_uclo.c *base = NULL; base 89 drivers/crypto/qce/ablkcipher.c gfp = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? base 227 drivers/crypto/qce/ablkcipher.c skcipher_request_set_callback(subreq, req->base.flags, base 237 drivers/crypto/qce/ablkcipher.c return tmpl->qce->async_req_enqueue(tmpl->qce, &req->base); base 22 drivers/crypto/qce/common.c return readl(qce->base + offset); base 27 drivers/crypto/qce/common.c writel(val, qce->base + offset); base 179 drivers/crypto/qce/core.c qce->base = devm_platform_ioremap_resource(pdev, 0); base 180 drivers/crypto/qce/core.c if (IS_ERR(qce->base)) base 181 drivers/crypto/qce/core.c return PTR_ERR(qce->base); base 35 drivers/crypto/qce/core.h void __iomem *base; base 127 drivers/crypto/qce/sha.c struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); base 230 drivers/crypto/qce/sha.c struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); base 299 drivers/crypto/qce/sha.c return qce->async_req_enqueue(tmpl->qce, &req->base); base 305 drivers/crypto/qce/sha.c struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); base 322 drivers/crypto/qce/sha.c return qce->async_req_enqueue(tmpl->qce, &req->base); base 328 drivers/crypto/qce/sha.c struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm); base 341 drivers/crypto/qce/sha.c return qce->async_req_enqueue(tmpl->qce, &req->base); base 348 drivers/crypto/qce/sha.c struct qce_sha_ctx *ctx = crypto_tfm_ctx(&tfm->base); base 474 drivers/crypto/qce/sha.c struct crypto_alg *base; base 495 drivers/crypto/qce/sha.c base = &alg->halg.base; base 496 drivers/crypto/qce/sha.c base->cra_blocksize = def->blocksize; base 497 drivers/crypto/qce/sha.c base->cra_priority = 300; base 498 drivers/crypto/qce/sha.c base->cra_flags = CRYPTO_ALG_ASYNC; base 499 drivers/crypto/qce/sha.c base->cra_ctxsize = sizeof(struct qce_sha_ctx); base 500 drivers/crypto/qce/sha.c base->cra_alignmask = 0; base 501 drivers/crypto/qce/sha.c base->cra_module = THIS_MODULE; base 502 drivers/crypto/qce/sha.c base->cra_init = qce_ahash_cra_init; base 504 drivers/crypto/qce/sha.c snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name); base 505 drivers/crypto/qce/sha.c snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", base 516 drivers/crypto/qce/sha.c dev_err(qce->dev, "%s registration failed\n", base->cra_name); base 521 drivers/crypto/qce/sha.c dev_dbg(qce->dev, "%s is registered\n", base->cra_name); base 30 drivers/crypto/qcom-rng.c void __iomem *base; base 48 drivers/crypto/qcom-rng.c val = readl_relaxed(rng->base + PRNG_STATUS); base 52 drivers/crypto/qcom-rng.c val = readl_relaxed(rng->base + PRNG_DATA_OUT); base 108 drivers/crypto/qcom-rng.c val = readl_relaxed(rng->base + PRNG_CONFIG); base 112 drivers/crypto/qcom-rng.c val = readl_relaxed(rng->base + PRNG_LFSR_CFG); base 115 drivers/crypto/qcom-rng.c writel(val, rng->base + PRNG_LFSR_CFG); base 117 drivers/crypto/qcom-rng.c val = readl_relaxed(rng->base + PRNG_CONFIG); base 119 drivers/crypto/qcom-rng.c writel(val, rng->base + PRNG_CONFIG); base 143 drivers/crypto/qcom-rng.c .base = { base 166 drivers/crypto/qcom-rng.c rng->base = devm_platform_ioremap_resource(pdev, 0); base 167 drivers/crypto/qcom-rng.c if (IS_ERR(rng->base)) base 168 drivers/crypto/qcom-rng.c return PTR_ERR(rng->base); base 219 drivers/crypto/rockchip/rk3288_crypto.h void (*complete)(struct crypto_async_request *base, int err); base 15 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c static void rk_crypto_complete(struct crypto_async_request *base, int err) base 17 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c if (base->complete) base 18 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c base->complete(base, err); base 27 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c return dev->enqueue(dev, &req->base); base 40 drivers/crypto/rockchip/rk3288_crypto_ahash.c static void rk_ahash_crypto_complete(struct crypto_async_request *base, int err) base 42 drivers/crypto/rockchip/rk3288_crypto_ahash.c if (base->complete) base 43 drivers/crypto/rockchip/rk3288_crypto_ahash.c base->complete(base, err); base 86 drivers/crypto/rockchip/rk3288_crypto_ahash.c rctx->fallback_req.base.flags = req->base.flags & base 99 drivers/crypto/rockchip/rk3288_crypto_ahash.c rctx->fallback_req.base.flags = req->base.flags & base 114 drivers/crypto/rockchip/rk3288_crypto_ahash.c rctx->fallback_req.base.flags = req->base.flags & base 128 drivers/crypto/rockchip/rk3288_crypto_ahash.c rctx->fallback_req.base.flags = req->base.flags & base 145 drivers/crypto/rockchip/rk3288_crypto_ahash.c rctx->fallback_req.base.flags = req->base.flags & base 158 drivers/crypto/rockchip/rk3288_crypto_ahash.c rctx->fallback_req.base.flags = req->base.flags & base 166 drivers/crypto/rockchip/rk3288_crypto_ahash.c struct rk_ahash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); base 172 drivers/crypto/rockchip/rk3288_crypto_ahash.c return dev->enqueue(dev, &req->base); base 327 drivers/crypto/rockchip/rk3288_crypto_ahash.c .base = { base 357 drivers/crypto/rockchip/rk3288_crypto_ahash.c .base = { base 387 drivers/crypto/rockchip/rk3288_crypto_ahash.c .base = { base 503 drivers/crypto/s5p-sss.c req->base.complete(&req->base, err); base 1358 drivers/crypto/s5p-sss.c if (req->base.complete) base 1359 drivers/crypto/s5p-sss.c req->base.complete(&req->base, err); base 1490 drivers/crypto/s5p-sss.c struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); base 1547 drivers/crypto/s5p-sss.c struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); base 1550 drivers/crypto/s5p-sss.c return s5p_hash_shash_digest(tctx->fallback, req->base.flags, base 1769 drivers/crypto/s5p-sss.c .halg.base = { base 1794 drivers/crypto/s5p-sss.c .halg.base = { base 1819 drivers/crypto/s5p-sss.c .halg.base = { base 2025 drivers/crypto/s5p-sss.c dev->ctx = crypto_tfm_ctx(dev->req->base.tfm); base 2318 drivers/crypto/s5p-sss.c alg->halg.base.cra_driver_name, err); base 622 drivers/crypto/sahara.c crypto_sync_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags & base 627 drivers/crypto/sahara.c tfm->base.crt_flags &= ~CRYPTO_TFM_RES_MASK; base 628 drivers/crypto/sahara.c tfm->base.crt_flags |= crypto_sync_skcipher_get_flags(ctx->fallback) & base 669 drivers/crypto/sahara.c skcipher_request_set_callback(subreq, req->base.flags, base 691 drivers/crypto/sahara.c skcipher_request_set_callback(subreq, req->base.flags, base 713 drivers/crypto/sahara.c skcipher_request_set_callback(subreq, req->base.flags, base 735 drivers/crypto/sahara.c skcipher_request_set_callback(subreq, req->base.flags, base 1108 drivers/crypto/sahara.c ret = crypto_enqueue_request(&dev->queue, &req->base); base 1248 drivers/crypto/sahara.c .halg.base = { base 1274 drivers/crypto/sahara.c .halg.base = { base 218 drivers/crypto/stm32/stm32-crc32.c .base = { base 240 drivers/crypto/stm32/stm32-crc32.c .base = { base 1021 drivers/crypto/stm32/stm32-cryp.c base); base 1030 drivers/crypto/stm32/stm32-cryp.c base); base 1044 drivers/crypto/stm32/stm32-cryp.c base); base 1052 drivers/crypto/stm32/stm32-cryp.c base); base 1884 drivers/crypto/stm32/stm32-cryp.c .base = { base 1904 drivers/crypto/stm32/stm32-cryp.c .base = { base 838 drivers/crypto/stm32/stm32-hash.c base); base 859 drivers/crypto/stm32/stm32-hash.c base); base 887 drivers/crypto/stm32/stm32-hash.c struct stm32_hash_ctx *ctx = crypto_tfm_ctx(req->base.tfm); base 1133 drivers/crypto/stm32/stm32-hash.c .base = { base 1159 drivers/crypto/stm32/stm32-hash.c .base = { base 1184 drivers/crypto/stm32/stm32-hash.c .base = { base 1210 drivers/crypto/stm32/stm32-hash.c .base = { base 1238 drivers/crypto/stm32/stm32-hash.c .base = { base 1264 drivers/crypto/stm32/stm32-hash.c .base = { base 1289 drivers/crypto/stm32/stm32-hash.c .base = { base 1315 drivers/crypto/stm32/stm32-hash.c .base = { base 48 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c writel(*(op->key + i / 4), ss->base + SS_KEY0 + i); base 53 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c writel(v, ss->base + SS_IV0 + i * 4); base 56 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c writel(mode, ss->base + SS_CTL); base 79 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c writesl(ss->base + SS_RXFIFO, mi.addr + oi, todo); base 87 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c spaces = readl(ss->base + SS_FCSR); base 95 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c readsl(ss->base + SS_TXFIFO, mo.addr + oo, todo); base 106 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c v = readl(ss->base + SS_IV0 + i * 4); base 114 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c writel(0, ss->base + SS_CTL); base 129 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c skcipher_request_set_callback(subreq, areq->base.flags, NULL, base 183 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c if (areq->cryptlen % algt->alg.crypto.base.cra_blocksize) base 210 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c writel(*(op->key + i / 4), ss->base + SS_KEY0 + i); base 215 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c writel(v, ss->base + SS_IV0 + i * 4); base 218 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c writel(mode, ss->base + SS_CTL); base 247 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c writesl(ss->base + SS_RXFIFO, mi.addr + oi, base 266 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c writesl(ss->base + SS_RXFIFO, buf, base 277 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c spaces = readl(ss->base + SS_FCSR); base 292 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c readsl(ss->base + SS_TXFIFO, mo.addr + oo, todo); base 306 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c readsl(ss->base + SS_TXFIFO, bufo, tx_cnt); base 332 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c v = readl(ss->base + SS_IV0 + i * 4); base 340 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c writel(0, ss->base + SS_CTL); base 493 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c alg.crypto.base); base 541 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c crypto_sync_skcipher_set_flags(op->fallback_tfm, tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK); base 561 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c crypto_sync_skcipher_set_flags(op->fallback_tfm, tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK); base 581 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c crypto_sync_skcipher_set_flags(op->fallback_tfm, tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK); base 39 drivers/crypto/sunxi-ss/sun4i-ss-core.c .base = { base 65 drivers/crypto/sunxi-ss/sun4i-ss-core.c .base = { base 86 drivers/crypto/sunxi-ss/sun4i-ss-core.c .base = { base 107 drivers/crypto/sunxi-ss/sun4i-ss-core.c .base = { base 129 drivers/crypto/sunxi-ss/sun4i-ss-core.c .base = { base 150 drivers/crypto/sunxi-ss/sun4i-ss-core.c .base = { base 172 drivers/crypto/sunxi-ss/sun4i-ss-core.c .base = { base 193 drivers/crypto/sunxi-ss/sun4i-ss-core.c .base = { base 211 drivers/crypto/sunxi-ss/sun4i-ss-core.c .base = { base 242 drivers/crypto/sunxi-ss/sun4i-ss-core.c ss->base = devm_platform_ioremap_resource(pdev, 0); base 243 drivers/crypto/sunxi-ss/sun4i-ss-core.c if (IS_ERR(ss->base)) { base 245 drivers/crypto/sunxi-ss/sun4i-ss-core.c return PTR_ERR(ss->base); base 334 drivers/crypto/sunxi-ss/sun4i-ss-core.c writel(SS_ENABLED, ss->base + SS_CTL); base 335 drivers/crypto/sunxi-ss/sun4i-ss-core.c v = readl(ss->base + SS_CTL); base 339 drivers/crypto/sunxi-ss/sun4i-ss-core.c writel(0, ss->base + SS_CTL); base 352 drivers/crypto/sunxi-ss/sun4i-ss-core.c ss_algs[i].alg.crypto.base.cra_name); base 360 drivers/crypto/sunxi-ss/sun4i-ss-core.c ss_algs[i].alg.hash.halg.base.cra_name); base 368 drivers/crypto/sunxi-ss/sun4i-ss-core.c ss_algs[i].alg.rng.base.cra_name); base 418 drivers/crypto/sunxi-ss/sun4i-ss-core.c writel(0, ss->base + SS_CTL); base 38 drivers/crypto/sunxi-ss/sun4i-ss-hash.c struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); base 190 drivers/crypto/sunxi-ss/sun4i-ss-hash.c __func__, crypto_tfm_alg_name(areq->base.tfm), base 220 drivers/crypto/sunxi-ss/sun4i-ss-hash.c writel(op->hash[i], ss->base + SS_IV0 + i * 4); base 223 drivers/crypto/sunxi-ss/sun4i-ss-hash.c writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL); base 289 drivers/crypto/sunxi-ss/sun4i-ss-hash.c writesl(ss->base + SS_RXFIFO, op->buf, base 301 drivers/crypto/sunxi-ss/sun4i-ss-hash.c writesl(ss->base + SS_RXFIFO, mi.addr + in_i, todo); base 307 drivers/crypto/sunxi-ss/sun4i-ss-hash.c spaces = readl(ss->base + SS_FCSR); base 347 drivers/crypto/sunxi-ss/sun4i-ss-hash.c writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL); base 350 drivers/crypto/sunxi-ss/sun4i-ss-hash.c v = readl(ss->base + SS_CTL); base 371 drivers/crypto/sunxi-ss/sun4i-ss-hash.c op->hash[i] = readl(ss->base + SS_MD0 + i * 4); base 393 drivers/crypto/sunxi-ss/sun4i-ss-hash.c writesl(ss->base + SS_RXFIFO, op->buf, nwait); base 435 drivers/crypto/sunxi-ss/sun4i-ss-hash.c writesl(ss->base + SS_RXFIFO, bf, j); base 438 drivers/crypto/sunxi-ss/sun4i-ss-hash.c writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL); base 447 drivers/crypto/sunxi-ss/sun4i-ss-hash.c v = readl(ss->base + SS_CTL); base 470 drivers/crypto/sunxi-ss/sun4i-ss-hash.c v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4)); base 475 drivers/crypto/sunxi-ss/sun4i-ss-hash.c v = cpu_to_le32(readl(ss->base + SS_MD0 + i * 4)); base 481 drivers/crypto/sunxi-ss/sun4i-ss-hash.c writel(0, ss->base + SS_CTL); base 33 drivers/crypto/sunxi-ss/sun4i-ss-prng.c writel(mode, ss->base + SS_CTL); base 38 drivers/crypto/sunxi-ss/sun4i-ss-prng.c writel(ss->seed[i], ss->base + SS_KEY0 + i * 4); base 42 drivers/crypto/sunxi-ss/sun4i-ss-prng.c readsl(ss->base + SS_TXFIFO, data, len / 4); base 48 drivers/crypto/sunxi-ss/sun4i-ss-prng.c v = readl(ss->base + SS_KEY0 + i * 4); base 53 drivers/crypto/sunxi-ss/sun4i-ss-prng.c writel(0, ss->base + SS_CTL); base 134 drivers/crypto/sunxi-ss/sun4i-ss.h void __iomem *base; base 1431 drivers/crypto/talitos.c areq->base.flags, encrypt); base 1567 drivers/crypto/talitos.c areq->base.complete(&areq->base, err); base 1650 drivers/crypto/talitos.c areq->base.flags, encrypt); base 1760 drivers/crypto/talitos.c areq->base.complete(&areq->base, err); base 1923 drivers/crypto/talitos.c nbytes, 0, 0, 0, areq->base.flags, false); base 2267 drivers/crypto/talitos.c .base = { base 2288 drivers/crypto/talitos.c .base = { base 2308 drivers/crypto/talitos.c .base = { base 2332 drivers/crypto/talitos.c .base = { base 2355 drivers/crypto/talitos.c .base = { base 2376 drivers/crypto/talitos.c .base = { base 2396 drivers/crypto/talitos.c .base = { base 2420 drivers/crypto/talitos.c .base = { base 2443 drivers/crypto/talitos.c .base = { base 2464 drivers/crypto/talitos.c .base = { base 2484 drivers/crypto/talitos.c .base = { base 2508 drivers/crypto/talitos.c .base = { base 2531 drivers/crypto/talitos.c .base = { base 2551 drivers/crypto/talitos.c .base = { base 2574 drivers/crypto/talitos.c .base = { base 2594 drivers/crypto/talitos.c .base = { base 2617 drivers/crypto/talitos.c .base = { base 2638 drivers/crypto/talitos.c .base = { base 2658 drivers/crypto/talitos.c .base = { base 2681 drivers/crypto/talitos.c .base = { base 2829 drivers/crypto/talitos.c .halg.base = { base 2844 drivers/crypto/talitos.c .halg.base = { base 2859 drivers/crypto/talitos.c .halg.base = { base 2874 drivers/crypto/talitos.c .halg.base = { base 2889 drivers/crypto/talitos.c .halg.base = { base 2904 drivers/crypto/talitos.c .halg.base = { base 2919 drivers/crypto/talitos.c .halg.base = { base 2934 drivers/crypto/talitos.c .halg.base = { base 2949 drivers/crypto/talitos.c .halg.base = { base 2964 drivers/crypto/talitos.c .halg.base = { base 2979 drivers/crypto/talitos.c .halg.base = { base 2994 drivers/crypto/talitos.c .halg.base = { base 3170 drivers/crypto/talitos.c alg = &t_alg->algt.alg.aead.base; base 3184 drivers/crypto/talitos.c alg = &t_alg->algt.alg.hash.halg.base; base 3473 drivers/crypto/talitos.c alg = &t_alg->algt.alg.aead.base; base 3479 drivers/crypto/talitos.c alg = &t_alg->algt.alg.hash.halg.base; base 38 drivers/crypto/ux500/cryp/cryp.c peripheralid2 = readl_relaxed(&device_data->base->periphId2); base 45 drivers/crypto/ux500/cryp/cryp.c readl_relaxed(&device_data->base->periphId0)) base 47 drivers/crypto/ux500/cryp/cryp.c readl_relaxed(&device_data->base->periphId1)) base 49 drivers/crypto/ux500/cryp/cryp.c readl_relaxed(&device_data->base->periphId3)) base 51 drivers/crypto/ux500/cryp/cryp.c readl_relaxed(&device_data->base->pcellId0)) base 53 drivers/crypto/ux500/cryp/cryp.c readl_relaxed(&device_data->base->pcellId1)) base 55 drivers/crypto/ux500/cryp/cryp.c readl_relaxed(&device_data->base->pcellId2)) base 57 drivers/crypto/ux500/cryp/cryp.c readl_relaxed(&device_data->base->pcellId3))) { base 72 drivers/crypto/ux500/cryp/cryp.c CRYP_PUT_BITS(&device_data->base->cr, base 93 drivers/crypto/ux500/cryp/cryp.c CRYP_SET_BITS(&device_data->base->cr, CRYP_CR_FFLUSH_MASK); base 99 drivers/crypto/ux500/cryp/cryp.c while (readl_relaxed(&device_data->base->sr) != base 147 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(cr_for_kse, &device_data->base->cr); base 170 drivers/crypto/ux500/cryp/cryp.c CRYP_WRITE_BIT(&device_data->base->cr, base 173 drivers/crypto/ux500/cryp/cryp.c CRYP_PUT_BITS(&device_data->base->cr, base 187 drivers/crypto/ux500/cryp/cryp.c return CRYP_TEST_BITS(&device_data->base->sr, base 199 drivers/crypto/ux500/cryp/cryp.c CRYP_SET_BITS(&device_data->base->dmacr, base 219 drivers/crypto/ux500/cryp/cryp.c &device_data->base->key_1_l); base 221 drivers/crypto/ux500/cryp/cryp.c &device_data->base->key_1_r); base 225 drivers/crypto/ux500/cryp/cryp.c &device_data->base->key_2_l); base 227 drivers/crypto/ux500/cryp/cryp.c &device_data->base->key_2_r); base 231 drivers/crypto/ux500/cryp/cryp.c &device_data->base->key_3_l); base 233 drivers/crypto/ux500/cryp/cryp.c &device_data->base->key_3_r); base 237 drivers/crypto/ux500/cryp/cryp.c &device_data->base->key_4_l); base 239 drivers/crypto/ux500/cryp/cryp.c &device_data->base->key_4_r); base 266 drivers/crypto/ux500/cryp/cryp.c &device_data->base->init_vect_0_l); base 268 drivers/crypto/ux500/cryp/cryp.c &device_data->base->init_vect_0_r); base 272 drivers/crypto/ux500/cryp/cryp.c &device_data->base->init_vect_1_l); base 274 drivers/crypto/ux500/cryp/cryp.c &device_data->base->init_vect_1_r); base 294 drivers/crypto/ux500/cryp/cryp.c struct cryp_register __iomem *src_reg = device_data->base; base 355 drivers/crypto/ux500/cryp/cryp.c struct cryp_register __iomem *reg = device_data->base; base 238 drivers/crypto/ux500/cryp/cryp.h struct cryp_register __iomem *base; base 221 drivers/crypto/ux500/cryp/cryp_core.c readsl(&device_data->base->dout, ctx->outdata, count); base 235 drivers/crypto/ux500/cryp/cryp_core.c writesl(&device_data->base->din, ctx->indata, count); base 245 drivers/crypto/ux500/cryp/cryp_core.c CRYP_PUT_BITS(&device_data->base->cr, base 376 drivers/crypto/ux500/cryp/cryp_core.c writel_relaxed(CRYP_IMSC_DEFAULT, &device_data->base->imsc); base 380 drivers/crypto/ux500/cryp/cryp_core.c writel_relaxed(CRYP_DMACR_DEFAULT, &device_data->base->dmacr); base 418 drivers/crypto/ux500/cryp/cryp_core.c &device_data->base->cr); base 662 drivers/crypto/ux500/cryp/cryp_core.c writesl(&device_data->base->din, indata, len); base 667 drivers/crypto/ux500/cryp/cryp_core.c readsl(&device_data->base->dout, outdata, len); base 955 drivers/crypto/ux500/cryp/cryp_core.c u32 *flags = &cipher->base.crt_flags; base 1360 drivers/crypto/ux500/cryp/cryp_core.c device_data->base = devm_ioremap_resource(dev, res); base 1361 drivers/crypto/ux500/cryp/cryp_core.c if (IS_ERR(device_data->base)) { base 1363 drivers/crypto/ux500/cryp/cryp_core.c ret = PTR_ERR(device_data->base); base 26 drivers/crypto/ux500/cryp/cryp_irq.c i = readl_relaxed(&device_data->base->imsc); base 28 drivers/crypto/ux500/cryp/cryp_irq.c writel_relaxed(i, &device_data->base->imsc); base 37 drivers/crypto/ux500/cryp/cryp_irq.c i = readl_relaxed(&device_data->base->imsc); base 39 drivers/crypto/ux500/cryp/cryp_irq.c writel_relaxed(i, &device_data->base->imsc); base 44 drivers/crypto/ux500/cryp/cryp_irq.c return (readl_relaxed(&device_data->base->mis) & irq_src) > 0; base 108 drivers/crypto/ux500/hash/hash_alg.h #define HASH_SET_DIN(val, len) writesl(&device_data->base->din, (val), (len)) base 112 drivers/crypto/ux500/hash/hash_alg.h &device_data->base->cr, \ base 118 drivers/crypto/ux500/hash/hash_alg.h &device_data->base->cr, \ base 123 drivers/crypto/ux500/hash/hash_alg.h &device_data->base->str, \ base 128 drivers/crypto/ux500/hash/hash_alg.h &device_data->base->str, \ base 365 drivers/crypto/ux500/hash/hash_alg.h struct hash_register __iomem *base; base 432 drivers/crypto/ux500/hash/hash_core.c HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK); base 453 drivers/crypto/ux500/hash/hash_core.c while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) base 458 drivers/crypto/ux500/hash/hash_core.c while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) base 596 drivers/crypto/ux500/hash/hash_core.c HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK); base 623 drivers/crypto/ux500/hash/hash_core.c HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK); base 635 drivers/crypto/ux500/hash/hash_core.c while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) base 641 drivers/crypto/ux500/hash/hash_core.c __func__, readl_relaxed(&device_data->base->din), base 642 drivers/crypto/ux500/hash/hash_core.c readl_relaxed(&device_data->base->str) & HASH_STR_NBLW_MASK); base 645 drivers/crypto/ux500/hash/hash_core.c __func__, readl_relaxed(&device_data->base->din), base 646 drivers/crypto/ux500/hash/hash_core.c readl_relaxed(&device_data->base->str) & HASH_STR_NBLW_MASK); base 648 drivers/crypto/ux500/hash/hash_core.c while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) base 695 drivers/crypto/ux500/hash/hash_core.c HASH_SET_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK); base 699 drivers/crypto/ux500/hash/hash_core.c HASH_CLEAR_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK); base 713 drivers/crypto/ux500/hash/hash_core.c HASH_CLEAR_BITS(&device_data->base->cr, base 716 drivers/crypto/ux500/hash/hash_core.c HASH_SET_BITS(&device_data->base->cr, HASH_CR_MODE_MASK); base 720 drivers/crypto/ux500/hash/hash_core.c HASH_SET_BITS(&device_data->base->cr, base 725 drivers/crypto/ux500/hash/hash_core.c HASH_CLEAR_BITS(&device_data->base->cr, base 747 drivers/crypto/ux500/hash/hash_core.c while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) base 760 drivers/crypto/ux500/hash/hash_core.c HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK); base 891 drivers/crypto/ux500/hash/hash_core.c HASH_CLEAR_BITS(&device_data->base->cr, base 894 drivers/crypto/ux500/hash/hash_core.c HASH_SET_BITS(&device_data->base->cr, base 896 drivers/crypto/ux500/hash/hash_core.c HASH_SET_BITS(&device_data->base->cr, base 930 drivers/crypto/ux500/hash/hash_core.c while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) base 1031 drivers/crypto/ux500/hash/hash_core.c while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) base 1155 drivers/crypto/ux500/hash/hash_core.c writel_relaxed(temp_cr & HASH_CR_RESUME_MASK, &device_data->base->cr); base 1157 drivers/crypto/ux500/hash/hash_core.c if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK) base 1167 drivers/crypto/ux500/hash/hash_core.c &device_data->base->csrx[count]); base 1170 drivers/crypto/ux500/hash/hash_core.c writel_relaxed(device_state->csfull, &device_data->base->csfull); base 1171 drivers/crypto/ux500/hash/hash_core.c writel_relaxed(device_state->csdatain, &device_data->base->csdatain); base 1173 drivers/crypto/ux500/hash/hash_core.c writel_relaxed(device_state->str_reg, &device_data->base->str); base 1174 drivers/crypto/ux500/hash/hash_core.c writel_relaxed(temp_cr, &device_data->base->cr); base 1201 drivers/crypto/ux500/hash/hash_core.c while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) base 1204 drivers/crypto/ux500/hash/hash_core.c temp_cr = readl_relaxed(&device_data->base->cr); base 1206 drivers/crypto/ux500/hash/hash_core.c device_state->str_reg = readl_relaxed(&device_data->base->str); base 1208 drivers/crypto/ux500/hash/hash_core.c device_state->din_reg = readl_relaxed(&device_data->base->din); base 1210 drivers/crypto/ux500/hash/hash_core.c if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK) base 1220 drivers/crypto/ux500/hash/hash_core.c readl_relaxed(&device_data->base->csrx[count]); base 1223 drivers/crypto/ux500/hash/hash_core.c device_state->csfull = readl_relaxed(&device_data->base->csfull); base 1224 drivers/crypto/ux500/hash/hash_core.c device_state->csdatain = readl_relaxed(&device_data->base->csdatain); base 1239 drivers/crypto/ux500/hash/hash_core.c if (HASH_P_ID0 == readl_relaxed(&device_data->base->periphid0) && base 1240 drivers/crypto/ux500/hash/hash_core.c HASH_P_ID1 == readl_relaxed(&device_data->base->periphid1) && base 1241 drivers/crypto/ux500/hash/hash_core.c HASH_P_ID2 == readl_relaxed(&device_data->base->periphid2) && base 1242 drivers/crypto/ux500/hash/hash_core.c HASH_P_ID3 == readl_relaxed(&device_data->base->periphid3) && base 1243 drivers/crypto/ux500/hash/hash_core.c HASH_CELL_ID0 == readl_relaxed(&device_data->base->cellid0) && base 1244 drivers/crypto/ux500/hash/hash_core.c HASH_CELL_ID1 == readl_relaxed(&device_data->base->cellid1) && base 1245 drivers/crypto/ux500/hash/hash_core.c HASH_CELL_ID2 == readl_relaxed(&device_data->base->cellid2) && base 1246 drivers/crypto/ux500/hash/hash_core.c HASH_CELL_ID3 == readl_relaxed(&device_data->base->cellid3)) { base 1282 drivers/crypto/ux500/hash/hash_core.c temp_hx_val = readl_relaxed(&device_data->base->hx[count]); base 1527 drivers/crypto/ux500/hash/hash_core.c .halg.base = { base 1550 drivers/crypto/ux500/hash/hash_core.c .halg.base = { base 1574 drivers/crypto/ux500/hash/hash_core.c .halg.base = { base 1598 drivers/crypto/ux500/hash/hash_core.c .halg.base = { base 1625 drivers/crypto/ux500/hash/hash_core.c hash_algs[i].hash.halg.base.cra_driver_name); base 1675 drivers/crypto/ux500/hash/hash_core.c device_data->base = devm_ioremap_resource(dev, res); base 1676 drivers/crypto/ux500/hash/hash_core.c if (IS_ERR(device_data->base)) { base 1678 drivers/crypto/ux500/hash/hash_core.c ret = PTR_ERR(device_data->base); base 29 drivers/crypto/virtio/virtio_crypto_algs.c struct virtio_crypto_request base; base 61 drivers/crypto/virtio/virtio_crypto_algs.c container_of(vc_req, struct virtio_crypto_sym_request, base); base 348 drivers/crypto/virtio/virtio_crypto_algs.c struct virtio_crypto_request *vc_req = &vc_sym_req->base; base 491 drivers/crypto/virtio/virtio_crypto_algs.c struct virtio_crypto_request *vc_req = &vc_sym_req->base; base 516 drivers/crypto/virtio/virtio_crypto_algs.c struct virtio_crypto_request *vc_req = &vc_sym_req->base; base 564 drivers/crypto/virtio/virtio_crypto_algs.c struct ablkcipher_request *req = container_of(vreq, struct ablkcipher_request, base); base 567 drivers/crypto/virtio/virtio_crypto_algs.c struct virtio_crypto_request *vc_req = &vc_sym_req->base; base 590 drivers/crypto/virtio/virtio_crypto_algs.c virtcrypto_clear_request(&vc_sym_req->base); base 592 drivers/crypto/virtio/virtio_crypto_algs.c crypto_finalize_ablkcipher_request(vc_sym_req->base.dataq->engine, base 118 drivers/crypto/vmx/aes_cbc.c .base.cra_name = "cbc(aes)", base 119 drivers/crypto/vmx/aes_cbc.c .base.cra_driver_name = "p8_aes_cbc", base 120 drivers/crypto/vmx/aes_cbc.c .base.cra_module = THIS_MODULE, base 121 drivers/crypto/vmx/aes_cbc.c .base.cra_priority = 2000, base 122 drivers/crypto/vmx/aes_cbc.c .base.cra_flags = CRYPTO_ALG_NEED_FALLBACK, base 123 drivers/crypto/vmx/aes_cbc.c .base.cra_blocksize = AES_BLOCK_SIZE, base 124 drivers/crypto/vmx/aes_cbc.c .base.cra_ctxsize = sizeof(struct p8_aes_cbc_ctx), base 133 drivers/crypto/vmx/aes_ctr.c .base.cra_name = "ctr(aes)", base 134 drivers/crypto/vmx/aes_ctr.c .base.cra_driver_name = "p8_aes_ctr", base 135 drivers/crypto/vmx/aes_ctr.c .base.cra_module = THIS_MODULE, base 136 drivers/crypto/vmx/aes_ctr.c .base.cra_priority = 2000, base 137 drivers/crypto/vmx/aes_ctr.c .base.cra_flags = CRYPTO_ALG_NEED_FALLBACK, base 138 drivers/crypto/vmx/aes_ctr.c .base.cra_blocksize = 1, base 139 drivers/crypto/vmx/aes_ctr.c .base.cra_ctxsize = sizeof(struct p8_aes_ctr_ctx), base 147 drivers/crypto/vmx/aes_xts.c .base.cra_name = "xts(aes)", base 148 drivers/crypto/vmx/aes_xts.c .base.cra_driver_name = "p8_aes_xts", base 149 drivers/crypto/vmx/aes_xts.c .base.cra_module = THIS_MODULE, base 150 drivers/crypto/vmx/aes_xts.c .base.cra_priority = 2000, base 151 drivers/crypto/vmx/aes_xts.c .base.cra_flags = CRYPTO_ALG_NEED_FALLBACK, base 152 drivers/crypto/vmx/aes_xts.c .base.cra_blocksize = AES_BLOCK_SIZE, base 153 drivers/crypto/vmx/aes_xts.c .base.cra_ctxsize = sizeof(struct p8_aes_xts_ctx), base 176 drivers/crypto/vmx/ghash.c .base = { base 205 drivers/devfreq/event/exynos-nocp.c void __iomem *base; base 218 drivers/devfreq/event/exynos-nocp.c base = devm_ioremap_resource(dev, res); base 219 drivers/devfreq/event/exynos-nocp.c if (IS_ERR(base)) base 220 drivers/devfreq/event/exynos-nocp.c return PTR_ERR(base); base 224 drivers/devfreq/event/exynos-nocp.c nocp->regmap = devm_regmap_init_mmio(dev, base, base 609 drivers/devfreq/event/exynos-ppmu.c void __iomem *base; base 619 drivers/devfreq/event/exynos-ppmu.c base = devm_ioremap_resource(dev, res); base 620 drivers/devfreq/event/exynos-ppmu.c if (IS_ERR(base)) base 621 drivers/devfreq/event/exynos-ppmu.c return PTR_ERR(base); base 624 drivers/devfreq/event/exynos-ppmu.c info->regmap = devm_regmap_init_mmio(dev, base, base 140 drivers/dma-buf/dma-buf.c loff_t base; base 151 drivers/dma-buf/dma-buf.c base = dmabuf->size; base 153 drivers/dma-buf/dma-buf.c base = 0; base 160 drivers/dma-buf/dma-buf.c return base + offset; base 36 drivers/dma-buf/dma-fence-array.c cmpxchg(&array->base.error, PENDING_ERROR, error); base 42 drivers/dma-buf/dma-fence-array.c cmpxchg(&array->base.error, PENDING_ERROR, 0); base 51 drivers/dma-buf/dma-fence-array.c dma_fence_signal(&array->base); base 52 drivers/dma-buf/dma-fence-array.c dma_fence_put(&array->base); base 67 drivers/dma-buf/dma-fence-array.c dma_fence_put(&array->base); base 86 drivers/dma-buf/dma-fence-array.c dma_fence_get(&array->base); base 92 drivers/dma-buf/dma-fence-array.c dma_fence_put(&array->base); base 165 drivers/dma-buf/dma-fence-array.c dma_fence_init(&array->base, &dma_fence_array_ops, &array->lock, base 173 drivers/dma-buf/dma-fence-array.c array->base.error = PENDING_ERROR; base 97 drivers/dma-buf/dma-fence-chain.c if (!chain || chain->base.seqno < seqno) base 100 drivers/dma-buf/dma-fence-chain.c dma_fence_chain_for_each(*pfence, &chain->base) { base 101 drivers/dma-buf/dma-fence-chain.c if ((*pfence)->context != chain->base.context || base 105 drivers/dma-buf/dma-fence-chain.c dma_fence_put(&chain->base); base 128 drivers/dma-buf/dma-fence-chain.c if (!dma_fence_chain_enable_signaling(&chain->base)) base 130 drivers/dma-buf/dma-fence-chain.c dma_fence_signal(&chain->base); base 131 drivers/dma-buf/dma-fence-chain.c dma_fence_put(&chain->base); base 147 drivers/dma-buf/dma-fence-chain.c dma_fence_get(&head->base); base 148 drivers/dma-buf/dma-fence-chain.c dma_fence_chain_for_each(fence, &head->base) { base 159 drivers/dma-buf/dma-fence-chain.c dma_fence_put(&head->base); base 253 drivers/dma-buf/dma-fence-chain.c dma_fence_init(&chain->base, &dma_fence_chain_ops, base 433 drivers/dma-buf/dma-fence.c struct dma_fence_cb base; base 441 drivers/dma-buf/dma-fence.c container_of(cb, struct default_wait_cb, base); base 496 drivers/dma-buf/dma-fence.c cb.base.func = dma_fence_default_wait_cb; base 498 drivers/dma-buf/dma-fence.c list_add(&cb.base.node, &fence->cb_list); base 514 drivers/dma-buf/dma-fence.c if (!list_empty(&cb.base.node)) base 515 drivers/dma-buf/dma-fence.c list_del(&cb.base.node); base 593 drivers/dma-buf/dma-fence.c if (dma_fence_add_callback(fence, &cb[i].base, base 621 drivers/dma-buf/dma-fence.c dma_fence_remove_callback(fences[i], &cb[i].base); base 52 drivers/dma-buf/seqno-fence.c dma_fence_free(&f->base); base 20 drivers/dma-buf/st-dma-fence.c struct dma_fence base; base 23 drivers/dma-buf/st-dma-fence.c return container_of(f, struct mock_fence, base); base 92 drivers/dma-buf/st-dma-fence.c dma_fence_init(&f->base, &mock_ops, &f->lock, 0, 0); base 94 drivers/dma-buf/st-dma-fence.c return &f->base; base 68 drivers/dma-buf/sw_sync.c return container_of(fence, struct sync_pt, base); base 203 drivers/dma-buf/sw_sync.c if (!timeline_fence_signaled(&pt->base)) base 217 drivers/dma-buf/sw_sync.c dma_fence_signal_locked(&pt->base); base 243 drivers/dma-buf/sw_sync.c dma_fence_init(&pt->base, &timeline_fence_ops, &obj->lock, base 248 drivers/dma-buf/sw_sync.c if (!dma_fence_is_signaled_locked(&pt->base)) { base 258 drivers/dma-buf/sw_sync.c cmp = value - other->base.seqno; base 264 drivers/dma-buf/sw_sync.c if (dma_fence_get_rcu(&other->base)) { base 317 drivers/dma-buf/sw_sync.c dma_fence_set_error(&pt->base, -ENOENT); base 318 drivers/dma-buf/sw_sync.c dma_fence_signal_locked(&pt->base); base 350 drivers/dma-buf/sw_sync.c sync_file = sync_file_create(&pt->base); base 351 drivers/dma-buf/sw_sync.c dma_fence_put(&pt->base); base 116 drivers/dma-buf/sync_debug.c sync_print_fence(s, &pt->base, false); base 60 drivers/dma-buf/sync_debug.h struct dma_fence base; base 169 drivers/dma-buf/sync_file.c sync_file->fence = &array->base; base 158 drivers/dma/amba-pl08x.c void __iomem *base; base 282 drivers/dma/amba-pl08x.c void __iomem *base; base 424 drivers/dma/amba-pl08x.c phychan->base + FTDMAC020_CH_SIZE); base 516 drivers/dma/amba-pl08x.c phychan->base + PL080S_CH_CONTROL2); base 547 drivers/dma/amba-pl08x.c while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id)) base 656 drivers/dma/amba-pl08x.c pl08x->base + PL080_ERR_CLEAR); base 657 drivers/dma/amba-pl08x.c writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR); base 667 drivers/dma/amba-pl08x.c writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR); base 668 drivers/dma/amba-pl08x.c writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR); base 677 drivers/dma/amba-pl08x.c bytes = readl(ch->base + FTDMAC020_CH_SIZE); base 683 drivers/dma/amba-pl08x.c val = readl(ch->base + PL080S_CH_CONTROL2); base 2286 drivers/dma/amba-pl08x.c writel(PL080_CONFIG_ENABLE, pl08x->base + FTDMAC020_CSR); base 2289 drivers/dma/amba-pl08x.c writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG); base 2298 drivers/dma/amba-pl08x.c err = readl(pl08x->base + PL080_ERR_STATUS); base 2302 drivers/dma/amba-pl08x.c writel(err, pl08x->base + PL080_ERR_CLEAR); base 2304 drivers/dma/amba-pl08x.c tc = readl(pl08x->base + PL080_TC_STATUS); base 2306 drivers/dma/amba-pl08x.c writel(tc, pl08x->base + PL080_TC_CLEAR); base 2730 drivers/dma/amba-pl08x.c pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); base 2731 drivers/dma/amba-pl08x.c if (!pl08x->base) { base 2739 drivers/dma/amba-pl08x.c val = readl(pl08x->base + FTDMAC020_REVISION); base 2742 drivers/dma/amba-pl08x.c val = readl(pl08x->base + FTDMAC020_FEATURE); base 2855 drivers/dma/amba-pl08x.c writel(0x0000FFFF, pl08x->base + PL080_ERR_CLEAR); base 2857 drivers/dma/amba-pl08x.c writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); base 2858 drivers/dma/amba-pl08x.c writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); base 2880 drivers/dma/amba-pl08x.c ch->base = pl08x->base + PL080_Cx_BASE(i); base 2883 drivers/dma/amba-pl08x.c ch->reg_busy = ch->base + FTDMAC020_CH_BUSY; base 2884 drivers/dma/amba-pl08x.c ch->reg_config = ch->base + FTDMAC020_CH_CFG; base 2885 drivers/dma/amba-pl08x.c ch->reg_control = ch->base + FTDMAC020_CH_CSR; base 2886 drivers/dma/amba-pl08x.c ch->reg_src = ch->base + FTDMAC020_CH_SRC_ADDR; base 2887 drivers/dma/amba-pl08x.c ch->reg_dst = ch->base + FTDMAC020_CH_DST_ADDR; base 2888 drivers/dma/amba-pl08x.c ch->reg_lli = ch->base + FTDMAC020_CH_LLP; base 2891 drivers/dma/amba-pl08x.c ch->reg_config = ch->base + vd->config_offset; base 2892 drivers/dma/amba-pl08x.c ch->reg_control = ch->base + PL080_CH_CONTROL; base 2893 drivers/dma/amba-pl08x.c ch->reg_src = ch->base + PL080_CH_SRC_ADDR; base 2894 drivers/dma/amba-pl08x.c ch->reg_dst = ch->base + PL080_CH_DST_ADDR; base 2895 drivers/dma/amba-pl08x.c ch->reg_lli = ch->base + PL080_CH_LLI; base 2984 drivers/dma/amba-pl08x.c iounmap(pl08x->base); base 1963 drivers/dma/at_xdmac.c void __iomem *base; base 1974 drivers/dma/at_xdmac.c base = devm_ioremap_resource(&pdev->dev, res); base 1975 drivers/dma/at_xdmac.c if (IS_ERR(base)) base 1976 drivers/dma/at_xdmac.c return PTR_ERR(base); base 1983 drivers/dma/at_xdmac.c reg = readl_relaxed(base + AT_XDMAC_GTYPE); base 1999 drivers/dma/at_xdmac.c atxdmac->regs = base; base 50 drivers/dma/bcm2835-dma.c void __iomem *base; base 171 drivers/dma/bcm2835-dma.c #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n)) base 834 drivers/dma/bcm2835-dma.c c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id); base 887 drivers/dma/bcm2835-dma.c void __iomem *base; base 912 drivers/dma/bcm2835-dma.c base = devm_ioremap_resource(&pdev->dev, res); base 913 drivers/dma/bcm2835-dma.c if (IS_ERR(base)) base 914 drivers/dma/bcm2835-dma.c return PTR_ERR(base); base 916 drivers/dma/bcm2835-dma.c od->base = base; base 1313 drivers/dma/coh901318.c struct coh901318_base *base; base 1423 drivers/dma/coh901318.c struct powersave *pm = &cohc->base->pm; base 1434 drivers/dma/coh901318.c struct powersave *pm = &cohc->base->pm; base 1446 drivers/dma/coh901318.c void __iomem *virtbase = cohc->base->virtbase; base 1457 drivers/dma/coh901318.c void __iomem *virtbase = cohc->base->virtbase; base 1470 drivers/dma/coh901318.c void __iomem *virtbase = cohc->base->virtbase; base 1489 drivers/dma/coh901318.c void __iomem *virtbase = cohc->base->virtbase; base 1631 drivers/dma/coh901318.c left = readl(cohc->base->virtbase + base 1637 drivers/dma/coh901318.c ladd = readl(cohc->base->virtbase + base 1689 drivers/dma/coh901318.c void __iomem *virtbase = cohc->base->virtbase; base 1742 drivers/dma/coh901318.c val = readl(cohc->base->virtbase + COH901318_CX_CFG + base 1747 drivers/dma/coh901318.c writel(val, cohc->base->virtbase + COH901318_CX_CFG + base 1769 drivers/dma/coh901318.c struct coh901318_base *base; base 1777 drivers/dma/coh901318.c if (&args->base->dma_slave == chan->device && base 1788 drivers/dma/coh901318.c .base = ofdma->of_dma_data, base 1805 drivers/dma/coh901318.c void __iomem *virtbase = cohc->base->virtbase; base 1897 drivers/dma/coh901318.c coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli); base 1987 drivers/dma/coh901318.c struct coh901318_base *base = dev_id; base 1989 drivers/dma/coh901318.c void __iomem *virtbase = base->virtbase; base 1995 drivers/dma/coh901318.c dev_warn(base->dev, "spurious DMA IRQ from no channel!\n"); base 2008 drivers/dma/coh901318.c cohc = &base->chans[ch]; base 2054 drivers/dma/coh901318.c cohc = &base->chans[ch]; base 2102 drivers/dma/coh901318.c void __iomem *virtbase = cohc->base->virtbase; base 2123 drivers/dma/coh901318.c coh901318_lli_free(&cohc->base->pool, &cohd->lli); base 2132 drivers/dma/coh901318.c coh901318_lli_free(&cohc->base->pool, &cohd->lli); base 2181 drivers/dma/coh901318.c writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG + base 2183 drivers/dma/coh901318.c writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL + base 2239 drivers/dma/coh901318.c lli = coh901318_lli_alloc(&cohc->base->pool, lli_len); base 2245 drivers/dma/coh901318.c &cohc->base->pool, lli, src, size, dest, base 2352 drivers/dma/coh901318.c lli = coh901318_lli_alloc(&cohc->base->pool, len); base 2360 drivers/dma/coh901318.c ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len, base 2590 drivers/dma/coh901318.c struct coh901318_base *base) base 2600 drivers/dma/coh901318.c cohc = &base->chans[i]; base 2602 drivers/dma/coh901318.c cohc->base = base; base 2630 drivers/dma/coh901318.c struct coh901318_base *base; base 2645 drivers/dma/coh901318.c base = devm_kzalloc(&pdev->dev, base 2650 drivers/dma/coh901318.c if (!base) base 2653 drivers/dma/coh901318.c base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4); base 2655 drivers/dma/coh901318.c base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io)); base 2656 drivers/dma/coh901318.c if (!base->virtbase) base 2659 drivers/dma/coh901318.c base->dev = &pdev->dev; base 2660 drivers/dma/coh901318.c spin_lock_init(&base->pm.lock); base 2661 drivers/dma/coh901318.c base->pm.started_channels = 0; base 2663 drivers/dma/coh901318.c COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base); base 2670 drivers/dma/coh901318.c "coh901318", base); base 2674 drivers/dma/coh901318.c base->irq = irq; base 2676 drivers/dma/coh901318.c err = coh901318_pool_create(&base->pool, &pdev->dev, base 2683 drivers/dma/coh901318.c coh901318_base_init(&base->dma_slave, dma_slave_channels, base 2684 drivers/dma/coh901318.c base); base 2686 drivers/dma/coh901318.c dma_cap_zero(base->dma_slave.cap_mask); base 2687 drivers/dma/coh901318.c dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); base 2689 drivers/dma/coh901318.c base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources; base 2690 drivers/dma/coh901318.c base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources; base 2691 drivers/dma/coh901318.c base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg; base 2692 drivers/dma/coh901318.c base->dma_slave.device_tx_status = coh901318_tx_status; base 2693 drivers/dma/coh901318.c base->dma_slave.device_issue_pending = coh901318_issue_pending; base 2694 drivers/dma/coh901318.c base->dma_slave.device_config = coh901318_dma_slave_config; base 2695 drivers/dma/coh901318.c base->dma_slave.device_pause = coh901318_pause; base 2696 drivers/dma/coh901318.c base->dma_slave.device_resume = coh901318_resume; base 2697 drivers/dma/coh901318.c base->dma_slave.device_terminate_all = coh901318_terminate_all; base 2698 drivers/dma/coh901318.c base->dma_slave.dev = &pdev->dev; base 2700 drivers/dma/coh901318.c err = dma_async_device_register(&base->dma_slave); base 2706 drivers/dma/coh901318.c coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels, base 2707 drivers/dma/coh901318.c base); base 2709 drivers/dma/coh901318.c dma_cap_zero(base->dma_memcpy.cap_mask); base 2710 drivers/dma/coh901318.c dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); base 2712 drivers/dma/coh901318.c base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources; base 2713 drivers/dma/coh901318.c base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources; base 2714 drivers/dma/coh901318.c base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy; base 2715 drivers/dma/coh901318.c base->dma_memcpy.device_tx_status = coh901318_tx_status; base 2716 drivers/dma/coh901318.c base->dma_memcpy.device_issue_pending = coh901318_issue_pending; base 2717 drivers/dma/coh901318.c base->dma_memcpy.device_config = coh901318_dma_slave_config; base 2718 drivers/dma/coh901318.c base->dma_memcpy.device_pause = coh901318_pause; base 2719 drivers/dma/coh901318.c base->dma_memcpy.device_resume = coh901318_resume; base 2720 drivers/dma/coh901318.c base->dma_memcpy.device_terminate_all = coh901318_terminate_all; base 2721 drivers/dma/coh901318.c base->dma_memcpy.dev = &pdev->dev; base 2726 drivers/dma/coh901318.c base->dma_memcpy.copy_align = DMAENGINE_ALIGN_4_BYTES; base 2727 drivers/dma/coh901318.c err = dma_async_device_register(&base->dma_memcpy); base 2733 drivers/dma/coh901318.c base); base 2737 drivers/dma/coh901318.c platform_set_drvdata(pdev, base); base 2739 drivers/dma/coh901318.c base->virtbase); base 2744 drivers/dma/coh901318.c dma_async_device_unregister(&base->dma_memcpy); base 2746 drivers/dma/coh901318.c dma_async_device_unregister(&base->dma_slave); base 2748 drivers/dma/coh901318.c coh901318_pool_destroy(&base->pool); base 2751 drivers/dma/coh901318.c static void coh901318_base_remove(struct coh901318_base *base, const int *pick_chans) base 2759 drivers/dma/coh901318.c cohc = &base->chans[i]; base 2769 drivers/dma/coh901318.c struct coh901318_base *base = platform_get_drvdata(pdev); base 2771 drivers/dma/coh901318.c devm_free_irq(&pdev->dev, base->irq, base); base 2773 drivers/dma/coh901318.c coh901318_base_remove(base, dma_slave_channels); base 2774 drivers/dma/coh901318.c coh901318_base_remove(base, dma_memcpy_channels); base 2777 drivers/dma/coh901318.c dma_async_device_unregister(&base->dma_memcpy); base 2778 drivers/dma/coh901318.c dma_async_device_unregister(&base->dma_slave); base 2779 drivers/dma/coh901318.c coh901318_pool_destroy(&base->pool); base 130 drivers/dma/dma-axi-dmac.c void __iomem *base; base 160 drivers/dma/dma-axi-dmac.c writel(val, axi_dmac->base + reg); base 165 drivers/dma/dma-axi-dmac.c return readl(axi_dmac->base + reg); base 847 drivers/dma/dma-axi-dmac.c dmac->base = devm_ioremap_resource(&pdev->dev, res); base 848 drivers/dma/dma-axi-dmac.c if (IS_ERR(dmac->base)) base 849 drivers/dma/dma-axi-dmac.c return PTR_ERR(dmac->base); base 925 drivers/dma/dma-axi-dmac.c regmap = devm_regmap_init_mmio(&pdev->dev, dmac->base, base 1339 drivers/dma/ep93xx_dma.c edmac->regs = cdata->base; base 178 drivers/dma/imx-dma.c void __iomem *base; base 260 drivers/dma/imx-dma.c __raw_writel(val, imxdma->base + offset); base 265 drivers/dma/imx-dma.c return __raw_readl(imxdma->base + offset); base 1076 drivers/dma/imx-dma.c imxdma->base = devm_ioremap_resource(&pdev->dev, res); base 1077 drivers/dma/imx-dma.c if (IS_ERR(imxdma->base)) base 1078 drivers/dma/imx-dma.c return PTR_ERR(imxdma->base); base 93 drivers/dma/k3dma.c void __iomem *base; base 101 drivers/dma/k3dma.c void __iomem *base; base 139 drivers/dma/k3dma.c val = readl_relaxed(phy->base + CX_CFG); base 141 drivers/dma/k3dma.c writel_relaxed(val, phy->base + CX_CFG); base 143 drivers/dma/k3dma.c val = readl_relaxed(phy->base + CX_CFG); base 145 drivers/dma/k3dma.c writel_relaxed(val, phy->base + CX_CFG); base 156 drivers/dma/k3dma.c writel_relaxed(val, d->base + INT_TC1_RAW); base 157 drivers/dma/k3dma.c writel_relaxed(val, d->base + INT_TC2_RAW); base 158 drivers/dma/k3dma.c writel_relaxed(val, d->base + INT_ERR1_RAW); base 159 drivers/dma/k3dma.c writel_relaxed(val, d->base + INT_ERR2_RAW); base 164 drivers/dma/k3dma.c writel_relaxed(hw->lli, phy->base + CX_LLI); base 165 drivers/dma/k3dma.c writel_relaxed(hw->count, phy->base + CX_CNT0); base 166 drivers/dma/k3dma.c writel_relaxed(hw->saddr, phy->base + CX_SRC); base 167 drivers/dma/k3dma.c writel_relaxed(hw->daddr, phy->base + CX_DST); base 168 drivers/dma/k3dma.c writel_relaxed(hw->config, phy->base + CX_CFG); base 175 drivers/dma/k3dma.c cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10); base 182 drivers/dma/k3dma.c return readl_relaxed(phy->base + CX_LLI); base 187 drivers/dma/k3dma.c return readl_relaxed(d->base + CH_STAT); base 194 drivers/dma/k3dma.c writel_relaxed(0x0, d->base + CH_PRI); base 197 drivers/dma/k3dma.c writel_relaxed(0xffff, d->base + INT_TC1_MASK); base 198 drivers/dma/k3dma.c writel_relaxed(0xffff, d->base + INT_TC2_MASK); base 199 drivers/dma/k3dma.c writel_relaxed(0xffff, d->base + INT_ERR1_MASK); base 200 drivers/dma/k3dma.c writel_relaxed(0xffff, d->base + INT_ERR2_MASK); base 203 drivers/dma/k3dma.c writel_relaxed(0x0, d->base + INT_TC1_MASK); base 204 drivers/dma/k3dma.c writel_relaxed(0x0, d->base + INT_TC2_MASK); base 205 drivers/dma/k3dma.c writel_relaxed(0x0, d->base + INT_ERR1_MASK); base 206 drivers/dma/k3dma.c writel_relaxed(0x0, d->base + INT_ERR2_MASK); base 215 drivers/dma/k3dma.c u32 stat = readl_relaxed(d->base + INT_STAT); base 216 drivers/dma/k3dma.c u32 tc1 = readl_relaxed(d->base + INT_TC1); base 217 drivers/dma/k3dma.c u32 tc2 = readl_relaxed(d->base + INT_TC2); base 218 drivers/dma/k3dma.c u32 err1 = readl_relaxed(d->base + INT_ERR1); base 219 drivers/dma/k3dma.c u32 err2 = readl_relaxed(d->base + INT_ERR2); base 251 drivers/dma/k3dma.c writel_relaxed(irq_chan, d->base + INT_TC1_RAW); base 252 drivers/dma/k3dma.c writel_relaxed(irq_chan, d->base + INT_TC2_RAW); base 253 drivers/dma/k3dma.c writel_relaxed(err1, d->base + INT_ERR1_RAW); base 254 drivers/dma/k3dma.c writel_relaxed(err2, d->base + INT_ERR2_RAW); base 859 drivers/dma/k3dma.c d->base = devm_ioremap_resource(&op->dev, iores); base 860 drivers/dma/k3dma.c if (IS_ERR(d->base)) base 861 drivers/dma/k3dma.c return PTR_ERR(d->base); base 914 drivers/dma/k3dma.c p->base = d->base + i * 0x40; base 103 drivers/dma/mediatek/mtk-cqdma.c void __iomem *base; base 171 drivers/dma/mediatek/mtk-cqdma.c return readl(pc->base + reg); base 176 drivers/dma/mediatek/mtk-cqdma.c writel_relaxed(val, pc->base + reg); base 210 drivers/dma/mediatek/mtk-cqdma.c return readl_poll_timeout(pc->base + MTK_CQDMA_EN, base 216 drivers/dma/mediatek/mtk-cqdma.c return readl_poll_timeout_atomic(pc->base + MTK_CQDMA_EN, base 830 drivers/dma/mediatek/mtk-cqdma.c cqdma->pc[i]->base = devm_ioremap_resource(&pdev->dev, res); base 831 drivers/dma/mediatek/mtk-cqdma.c if (IS_ERR(cqdma->pc[i]->base)) base 832 drivers/dma/mediatek/mtk-cqdma.c return PTR_ERR(cqdma->pc[i]->base); base 234 drivers/dma/mediatek/mtk-hsdma.c void __iomem *base; base 271 drivers/dma/mediatek/mtk-hsdma.c return readl(hsdma->base + reg); base 276 drivers/dma/mediatek/mtk-hsdma.c writel(val, hsdma->base + reg); base 309 drivers/dma/mediatek/mtk-hsdma.c return readl_poll_timeout(hsdma->base + MTK_HSDMA_GLO, status, base 909 drivers/dma/mediatek/mtk-hsdma.c hsdma->base = devm_ioremap_resource(&pdev->dev, res); base 910 drivers/dma/mediatek/mtk-hsdma.c if (IS_ERR(hsdma->base)) base 911 drivers/dma/mediatek/mtk-hsdma.c return PTR_ERR(hsdma->base); base 98 drivers/dma/mediatek/mtk-uart-apdma.c void __iomem *base; base 124 drivers/dma/mediatek/mtk-uart-apdma.c writel(val, c->base + reg); base 129 drivers/dma/mediatek/mtk-uart-apdma.c return readl(c->base + reg); base 287 drivers/dma/mediatek/mtk-uart-apdma.c ret = readx_poll_timeout(readl, c->base + VFF_EN, base 402 drivers/dma/mediatek/mtk-uart-apdma.c ret = readx_poll_timeout(readl, c->base + VFF_FLUSH, base 415 drivers/dma/mediatek/mtk-uart-apdma.c ret = readx_poll_timeout(readl, c->base + VFF_EN, base 541 drivers/dma/mediatek/mtk-uart-apdma.c c->base = devm_ioremap_resource(&pdev->dev, res); base 542 drivers/dma/mediatek/mtk-uart-apdma.c if (IS_ERR(c->base)) { base 543 drivers/dma/mediatek/mtk-uart-apdma.c rc = PTR_ERR(c->base); base 119 drivers/dma/mmp_pdma.c void __iomem *base; base 125 drivers/dma/mmp_pdma.c void __iomem *base; base 149 drivers/dma/mmp_pdma.c writel(addr, phy->base + reg); base 160 drivers/dma/mmp_pdma.c writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); base 162 drivers/dma/mmp_pdma.c dalgn = readl(phy->base + DALGN); base 167 drivers/dma/mmp_pdma.c writel(dalgn, phy->base + DALGN); base 170 drivers/dma/mmp_pdma.c writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg); base 181 drivers/dma/mmp_pdma.c writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg); base 187 drivers/dma/mmp_pdma.c u32 dint = readl(phy->base + DINT); base 194 drivers/dma/mmp_pdma.c dcsr = readl(phy->base + reg); base 195 drivers/dma/mmp_pdma.c writel(dcsr, phy->base + reg); base 217 drivers/dma/mmp_pdma.c u32 dint = readl(pdev->base + DINT); base 285 drivers/dma/mmp_pdma.c writel(0, pchan->phy->base + reg); base 785 drivers/dma/mmp_pdma.c curr = readl(chan->phy->base + DTADR(chan->phy->idx)); base 787 drivers/dma/mmp_pdma.c curr = readl(chan->phy->base + DSADR(chan->phy->idx)); base 980 drivers/dma/mmp_pdma.c phy->base = pdev->base; base 1046 drivers/dma/mmp_pdma.c pdev->base = devm_ioremap_resource(pdev->dev, iores); base 1047 drivers/dma/mmp_pdma.c if (IS_ERR(pdev->base)) base 1048 drivers/dma/mmp_pdma.c return PTR_ERR(pdev->base); base 132 drivers/dma/mmp_tdma.c void __iomem *base; base 575 drivers/dma/mmp_tdma.c tdmac->reg_base = tdev->base + idx * 4; base 657 drivers/dma/mmp_tdma.c tdev->base = devm_ioremap_resource(&pdev->dev, iores); base 658 drivers/dma/mmp_tdma.c if (IS_ERR(tdev->base)) base 659 drivers/dma/mmp_tdma.c return PTR_ERR(tdev->base); base 136 drivers/dma/moxart-dma.c void __iomem *base; base 202 drivers/dma/moxart-dma.c ctrl = readl(ch->base + REG_OFF_CTRL); base 204 drivers/dma/moxart-dma.c writel(ctrl, ch->base + REG_OFF_CTRL); base 221 drivers/dma/moxart-dma.c ctrl = readl(ch->base + REG_OFF_CTRL); base 264 drivers/dma/moxart-dma.c writel(ctrl, ch->base + REG_OFF_CTRL); base 374 drivers/dma/moxart-dma.c writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE); base 375 drivers/dma/moxart-dma.c writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST); base 389 drivers/dma/moxart-dma.c writel(d->dma_cycles, ch->base + REG_OFF_CYCLES); base 399 drivers/dma/moxart-dma.c ctrl = readl(ch->base + REG_OFF_CTRL); base 401 drivers/dma/moxart-dma.c writel(ctrl, ch->base + REG_OFF_CTRL); base 468 drivers/dma/moxart-dma.c cycles = readl(ch->base + REG_OFF_CYCLES); base 536 drivers/dma/moxart-dma.c ctrl = readl(ch->base + REG_OFF_CTRL); base 539 drivers/dma/moxart-dma.c __func__, ch, ch->base, ctrl); base 560 drivers/dma/moxart-dma.c writel(ctrl, ch->base + REG_OFF_CTRL); base 601 drivers/dma/moxart-dma.c ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE; base 608 drivers/dma/moxart-dma.c __func__, i, ch->ch_num, ch->base); base 486 drivers/dma/mv_xor.c void __iomem *base = mv_chan->mmr_high_base; base 531 drivers/dma/mv_xor.c win_enable = readl(base + WINDOW_BAR_ENABLE(0)); base 539 drivers/dma/mv_xor.c base + WINDOW_BASE(i)); base 540 drivers/dma/mv_xor.c writel(size & 0xffff0000, base + WINDOW_SIZE(i)); base 548 drivers/dma/mv_xor.c writel(win_enable, base + WINDOW_BAR_ENABLE(0)); base 549 drivers/dma/mv_xor.c writel(win_enable, base + WINDOW_BAR_ENABLE(1)); base 1166 drivers/dma/mv_xor.c void __iomem *base = xordev->xor_high_base; base 1171 drivers/dma/mv_xor.c writel(0, base + WINDOW_BASE(i)); base 1172 drivers/dma/mv_xor.c writel(0, base + WINDOW_SIZE(i)); base 1174 drivers/dma/mv_xor.c writel(0, base + WINDOW_REMAP_HIGH(i)); base 1180 drivers/dma/mv_xor.c writel((cs->base & 0xffff0000) | base 1182 drivers/dma/mv_xor.c dram->mbus_dram_target_id, base + WINDOW_BASE(i)); base 1183 drivers/dma/mv_xor.c writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); base 1186 drivers/dma/mv_xor.c xordev->win_start[i] = cs->base; base 1187 drivers/dma/mv_xor.c xordev->win_end[i] = cs->base + cs->size - 1; base 1193 drivers/dma/mv_xor.c writel(win_enable, base + WINDOW_BAR_ENABLE(0)); base 1194 drivers/dma/mv_xor.c writel(win_enable, base + WINDOW_BAR_ENABLE(1)); base 1195 drivers/dma/mv_xor.c writel(0, base + WINDOW_OVERRIDE_CTRL(0)); base 1196 drivers/dma/mv_xor.c writel(0, base + WINDOW_OVERRIDE_CTRL(1)); base 1202 drivers/dma/mv_xor.c void __iomem *base = xordev->xor_high_base; base 1207 drivers/dma/mv_xor.c writel(0, base + WINDOW_BASE(i)); base 1208 drivers/dma/mv_xor.c writel(0, base + WINDOW_SIZE(i)); base 1210 drivers/dma/mv_xor.c writel(0, base + WINDOW_REMAP_HIGH(i)); base 1216 drivers/dma/mv_xor.c writel(0xffff0000, base + WINDOW_SIZE(0)); base 1220 drivers/dma/mv_xor.c writel(win_enable, base + WINDOW_BAR_ENABLE(0)); base 1221 drivers/dma/mv_xor.c writel(win_enable, base + WINDOW_BAR_ENABLE(1)); base 1222 drivers/dma/mv_xor.c writel(0, base + WINDOW_OVERRIDE_CTRL(0)); base 1223 drivers/dma/mv_xor.c writel(0, base + WINDOW_OVERRIDE_CTRL(1)); base 141 drivers/dma/mxs-dma.c void __iomem *base; base 221 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); base 225 drivers/dma/mxs-dma.c void __iomem *reg_dbg1 = mxs_dma->base + base 246 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); base 260 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id)); base 268 drivers/dma/mxs-dma.c writel(2, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id)); base 270 drivers/dma/mxs-dma.c writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id)); base 291 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); base 294 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); base 309 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR); base 312 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR); base 353 drivers/dma/mxs-dma.c completed = readl(mxs_dma->base + HW_APBHX_CTRL1); base 358 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR); base 361 drivers/dma/mxs-dma.c err = readl(mxs_dma->base + HW_APBHX_CTRL2); base 373 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR); base 396 drivers/dma/mxs-dma.c writel(1, mxs_dma->base + base 681 drivers/dma/mxs-dma.c bar = readl(mxs_dma->base + base 700 drivers/dma/mxs-dma.c ret = stmp_reset_block(mxs_dma->base); base 707 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); base 709 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); base 714 drivers/dma/mxs-dma.c mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); base 794 drivers/dma/mxs-dma.c mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores); base 795 drivers/dma/mxs-dma.c if (IS_ERR(mxs_dma->base)) base 796 drivers/dma/mxs-dma.c return PTR_ERR(mxs_dma->base); base 198 drivers/dma/nbpfaxi.c void __iomem *base; base 224 drivers/dma/nbpfaxi.c void __iomem *base; base 301 drivers/dma/nbpfaxi.c u32 data = ioread32(chan->base + offset); base 303 drivers/dma/nbpfaxi.c __func__, chan->base, offset, data); base 310 drivers/dma/nbpfaxi.c iowrite32(data, chan->base + offset); base 312 drivers/dma/nbpfaxi.c __func__, chan->base, offset, data); base 318 drivers/dma/nbpfaxi.c u32 data = ioread32(nbpf->base + offset); base 320 drivers/dma/nbpfaxi.c __func__, nbpf->base, offset, data); base 327 drivers/dma/nbpfaxi.c iowrite32(data, nbpf->base + offset); base 329 drivers/dma/nbpfaxi.c __func__, nbpf->base, offset, data); base 1245 drivers/dma/nbpfaxi.c chan->base = nbpf->base + NBPF_REG_CHAN_OFFSET + NBPF_REG_CHAN_SIZE * n; base 1252 drivers/dma/nbpfaxi.c dev_dbg(dma_dev->dev, "%s(): channel %d: -> %p\n", __func__, n, chan->base); base 1315 drivers/dma/nbpfaxi.c nbpf->base = devm_ioremap_resource(dev, iomem); base 1316 drivers/dma/nbpfaxi.c if (IS_ERR(nbpf->base)) base 1317 drivers/dma/nbpfaxi.c return PTR_ERR(nbpf->base); base 181 drivers/dma/owl-dma.c void __iomem *base; base 216 drivers/dma/owl-dma.c void __iomem *base; base 234 drivers/dma/owl-dma.c regval = readl(pchan->base + reg); base 241 drivers/dma/owl-dma.c writel(val, pchan->base + reg); base 246 drivers/dma/owl-dma.c writel(data, pchan->base + reg); base 251 drivers/dma/owl-dma.c return readl(pchan->base + reg); base 258 drivers/dma/owl-dma.c regval = readl(od->base + reg); base 265 drivers/dma/owl-dma.c writel(val, od->base + reg); base 270 drivers/dma/owl-dma.c writel(data, od->base + reg); base 275 drivers/dma/owl-dma.c return readl(od->base + reg); base 1057 drivers/dma/owl-dma.c od->base = devm_ioremap_resource(&pdev->dev, res); base 1058 drivers/dma/owl-dma.c if (IS_ERR(od->base)) base 1059 drivers/dma/owl-dma.c return PTR_ERR(od->base); base 1135 drivers/dma/owl-dma.c pchan->base = od->base + OWL_DMA_CHAN_BASE(i); base 473 drivers/dma/pl330.c void __iomem *base; base 865 drivers/dma/pl330.c void __iomem *regs = thrd->dmac->base; base 885 drivers/dma/pl330.c void __iomem *regs = thrd->dmac->base; base 910 drivers/dma/pl330.c void __iomem *regs = thrd->dmac->base; base 968 drivers/dma/pl330.c void __iomem *regs = thrd->dmac->base; base 995 drivers/dma/pl330.c void __iomem *regs = thrd->dmac->base; base 1597 drivers/dma/pl330.c void __iomem *regs = pl330->base; base 1635 drivers/dma/pl330.c regs = pl330->base; base 1812 drivers/dma/pl330.c void __iomem *regs = pl330->base; base 2369 drivers/dma/pl330.c void __iomem *regs = thrd->dmac->base; base 3026 drivers/dma/pl330.c pl330->base = devm_ioremap_resource(&adev->dev, res); base 3027 drivers/dma/pl330.c if (IS_ERR(pl330->base)) base 3028 drivers/dma/pl330.c return PTR_ERR(pl330->base); base 99 drivers/dma/pxa_dma.c void __iomem *base; base 127 drivers/dma/pxa_dma.c void __iomem *base; base 146 drivers/dma/pxa_dma.c readl_relaxed((phy)->base + _reg((phy)->idx)) base 150 drivers/dma/pxa_dma.c _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \ base 158 drivers/dma/pxa_dma.c writel((val), (phy)->base + _reg((phy)->idx)); \ base 165 drivers/dma/pxa_dma.c writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \ base 196 drivers/dma/pxa_dma.c drcmr = readl_relaxed(phy->base + pxad_drcmr(i)); base 421 drivers/dma/pxa_dma.c writel_relaxed(0, chan->phy->base + reg); base 465 drivers/dma/pxa_dma.c writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg); base 587 drivers/dma/pxa_dma.c u32 dint = readl(phy->base + DINT); base 671 drivers/dma/pxa_dma.c u32 dint = readl(pdev->base + DINT); base 1264 drivers/dma/pxa_dma.c phy->base = pdev->base; base 1371 drivers/dma/pxa_dma.c pdev->base = devm_ioremap_resource(&op->dev, iores); base 1372 drivers/dma/pxa_dma.c if (IS_ERR(pdev->base)) base 1373 drivers/dma/pxa_dma.c return PTR_ERR(pdev->base); base 193 drivers/dma/s3c24xx-dma.c void __iomem *base; base 239 drivers/dma/s3c24xx-dma.c void __iomem *base; base 254 drivers/dma/s3c24xx-dma.c unsigned int val = readl(phy->base + S3C24XX_DSTAT); base 357 drivers/dma/s3c24xx-dma.c writel(S3C24XX_DMASKTRIG_STOP, phy->base + S3C24XX_DMASKTRIG); base 374 drivers/dma/s3c24xx-dma.c u32 tc = readl(phy->base + S3C24XX_DSTAT) & S3C24XX_DSTAT_CURRTC_MASK; base 469 drivers/dma/s3c24xx-dma.c phy->base + S3C24XX_DMAREQSEL); base 480 drivers/dma/s3c24xx-dma.c writel_relaxed(0, phy->base + S3C24XX_DMAREQSEL); base 483 drivers/dma/s3c24xx-dma.c writel_relaxed(dsg->src_addr, phy->base + S3C24XX_DISRC); base 484 drivers/dma/s3c24xx-dma.c writel_relaxed(txd->disrcc, phy->base + S3C24XX_DISRCC); base 485 drivers/dma/s3c24xx-dma.c writel_relaxed(dsg->dst_addr, phy->base + S3C24XX_DIDST); base 486 drivers/dma/s3c24xx-dma.c writel_relaxed(txd->didstc, phy->base + S3C24XX_DIDSTC); base 487 drivers/dma/s3c24xx-dma.c writel_relaxed(dcon, phy->base + S3C24XX_DCON); base 489 drivers/dma/s3c24xx-dma.c val = readl_relaxed(phy->base + S3C24XX_DMASKTRIG); base 497 drivers/dma/s3c24xx-dma.c writel(val, phy->base + S3C24XX_DMASKTRIG); base 1219 drivers/dma/s3c24xx-dma.c s3cdma->base = devm_ioremap_resource(&pdev->dev, res); base 1220 drivers/dma/s3c24xx-dma.c if (IS_ERR(s3cdma->base)) base 1221 drivers/dma/s3c24xx-dma.c return PTR_ERR(s3cdma->base); base 1236 drivers/dma/s3c24xx-dma.c phy->base = s3cdma->base + (i * sdata->stride); base 101 drivers/dma/sa11x0-dma.c void __iomem *base; base 119 drivers/dma/sa11x0-dma.c void __iomem *base; base 163 drivers/dma/sa11x0-dma.c void __iomem *base = p->base; base 170 drivers/dma/sa11x0-dma.c dcsr = readl_relaxed(base + DMA_DCSR_R); base 212 drivers/dma/sa11x0-dma.c writel_relaxed(sg->addr, base + dbsx); base 213 drivers/dma/sa11x0-dma.c writel_relaxed(sg->len, base + dbtx); base 214 drivers/dma/sa11x0-dma.c writel(dcsr, base + DMA_DCSR_S); base 255 drivers/dma/sa11x0-dma.c dcsr = readl_relaxed(p->base + DMA_DCSR_R); base 261 drivers/dma/sa11x0-dma.c p->base + DMA_DCSR_C); base 268 drivers/dma/sa11x0-dma.c readl_relaxed(p->base + DMA_DDAR), base 269 drivers/dma/sa11x0-dma.c readl_relaxed(p->base + DMA_DBSA), base 270 drivers/dma/sa11x0-dma.c readl_relaxed(p->base + DMA_DBTA), base 271 drivers/dma/sa11x0-dma.c readl_relaxed(p->base + DMA_DBSB), base 272 drivers/dma/sa11x0-dma.c readl_relaxed(p->base + DMA_DBTB)); base 312 drivers/dma/sa11x0-dma.c WARN_ON(readl_relaxed(p->base + DMA_DCSR_R) & base 317 drivers/dma/sa11x0-dma.c p->base + DMA_DCSR_C); base 318 drivers/dma/sa11x0-dma.c writel_relaxed(txd->ddar, p->base + DMA_DDAR); base 406 drivers/dma/sa11x0-dma.c dcsr = readl_relaxed(p->base + DMA_DCSR_R); base 414 drivers/dma/sa11x0-dma.c return readl_relaxed(p->base + reg); base 714 drivers/dma/sa11x0-dma.c writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_C); base 740 drivers/dma/sa11x0-dma.c writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_S); base 772 drivers/dma/sa11x0-dma.c p->base + DMA_DCSR_C); base 925 drivers/dma/sa11x0-dma.c d->base = ioremap(res->start, resource_size(res)); base 926 drivers/dma/sa11x0-dma.c if (!d->base) { base 938 drivers/dma/sa11x0-dma.c p->base = d->base + i * DMA_SIZE; base 941 drivers/dma/sa11x0-dma.c p->base + DMA_DCSR_C); base 942 drivers/dma/sa11x0-dma.c writel_relaxed(0, p->base + DMA_DDAR); base 980 drivers/dma/sa11x0-dma.c iounmap(d->base); base 998 drivers/dma/sa11x0-dma.c iounmap(d->base); base 1013 drivers/dma/sa11x0-dma.c dcsr = saved_dcsr = readl_relaxed(p->base + DMA_DCSR_R); base 1015 drivers/dma/sa11x0-dma.c writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_C); base 1016 drivers/dma/sa11x0-dma.c dcsr = readl_relaxed(p->base + DMA_DCSR_R); base 1021 drivers/dma/sa11x0-dma.c p->dbs[0] = readl_relaxed(p->base + DMA_DBSB); base 1022 drivers/dma/sa11x0-dma.c p->dbt[0] = readl_relaxed(p->base + DMA_DBTB); base 1023 drivers/dma/sa11x0-dma.c p->dbs[1] = readl_relaxed(p->base + DMA_DBSA); base 1024 drivers/dma/sa11x0-dma.c p->dbt[1] = readl_relaxed(p->base + DMA_DBTA); base 1028 drivers/dma/sa11x0-dma.c p->dbs[0] = readl_relaxed(p->base + DMA_DBSA); base 1029 drivers/dma/sa11x0-dma.c p->dbt[0] = readl_relaxed(p->base + DMA_DBTA); base 1030 drivers/dma/sa11x0-dma.c p->dbs[1] = readl_relaxed(p->base + DMA_DBSB); base 1031 drivers/dma/sa11x0-dma.c p->dbt[1] = readl_relaxed(p->base + DMA_DBTB); base 1036 drivers/dma/sa11x0-dma.c writel(DCSR_STRTA | DCSR_STRTB, p->base + DMA_DCSR_C); base 1050 drivers/dma/sa11x0-dma.c u32 dcsr = readl_relaxed(p->base + DMA_DCSR_R); base 1062 drivers/dma/sa11x0-dma.c writel_relaxed(txd->ddar, p->base + DMA_DDAR); base 1064 drivers/dma/sa11x0-dma.c writel_relaxed(p->dbs[0], p->base + DMA_DBSA); base 1065 drivers/dma/sa11x0-dma.c writel_relaxed(p->dbt[0], p->base + DMA_DBTA); base 1066 drivers/dma/sa11x0-dma.c writel_relaxed(p->dbs[1], p->base + DMA_DBSB); base 1067 drivers/dma/sa11x0-dma.c writel_relaxed(p->dbt[1], p->base + DMA_DBTB); base 1068 drivers/dma/sa11x0-dma.c writel_relaxed(p->dcsr, p->base + DMA_DCSR_S); base 27 drivers/dma/sh/shdma.h void __iomem *base; base 80 drivers/dma/sh/shdmac.c __raw_writel(data, sh_dc->base + reg); base 85 drivers/dma/sh/shdmac.c return __raw_readl(sh_dc->base + reg); base 112 drivers/dma/sh/shdmac.c __raw_writel(data, sh_dc->base + shdev->chcr_offset); base 119 drivers/dma/sh/shdmac.c return __raw_readl(sh_dc->base + shdev->chcr_offset); base 537 drivers/dma/sh/shdmac.c sh_chan->base = shdev->chan_reg + chan_pdata->offset; base 122 drivers/dma/sirf-dma.c void __iomem *base; base 127 drivers/dma/sirf-dma.c int cid, int burst_mode, void __iomem *base); base 133 drivers/dma/sirf-dma.c int cid, int burst_mode, void __iomem *base); base 163 drivers/dma/sirf-dma.c int cid, int burst_mode, void __iomem *base) base 171 drivers/dma/sirf-dma.c base + SIRFSOC_DMA_CH_CTRL); base 174 drivers/dma/sirf-dma.c writel_relaxed(sdesc->xlen, base + SIRFSOC_DMA_CH_XLEN); base 175 drivers/dma/sirf-dma.c writel_relaxed(sdesc->ylen, base + SIRFSOC_DMA_CH_YLEN); base 176 drivers/dma/sirf-dma.c writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_ATLAS7); base 178 drivers/dma/sirf-dma.c base + SIRFSOC_DMA_MUL_ATLAS7); base 182 drivers/dma/sirf-dma.c 0x3, base + SIRFSOC_DMA_CH_CTRL); base 187 drivers/dma/sirf-dma.c base + SIRFSOC_DMA_INT_EN_ATLAS7); base 188 drivers/dma/sirf-dma.c writel(sdesc->addr, base + SIRFSOC_DMA_CH_ADDR); base 190 drivers/dma/sirf-dma.c writel(0x10001, base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7); base 194 drivers/dma/sirf-dma.c int cid, int burst_mode, void __iomem *base) base 196 drivers/dma/sirf-dma.c writel_relaxed(1, base + SIRFSOC_DMA_IOBG_SCMD_EN); base 197 drivers/dma/sirf-dma.c writel_relaxed((1 << cid), base + SIRFSOC_DMA_EARLY_RESP_SET); base 198 drivers/dma/sirf-dma.c writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_0 + cid * 4); base 201 drivers/dma/sirf-dma.c base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL); base 202 drivers/dma/sirf-dma.c writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN); base 203 drivers/dma/sirf-dma.c writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN); base 204 drivers/dma/sirf-dma.c writel_relaxed(readl_relaxed(base + SIRFSOC_DMA_INT_EN) | base 205 drivers/dma/sirf-dma.c (1 << cid), base + SIRFSOC_DMA_INT_EN); base 206 drivers/dma/sirf-dma.c writel(sdesc->addr >> 2, base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR); base 209 drivers/dma/sirf-dma.c readl_relaxed(base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7), base 210 drivers/dma/sirf-dma.c base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7); base 216 drivers/dma/sirf-dma.c int cid, int burst_mode, void __iomem *base) base 218 drivers/dma/sirf-dma.c writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_0 + cid * 4); base 221 drivers/dma/sirf-dma.c base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL); base 222 drivers/dma/sirf-dma.c writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN); base 223 drivers/dma/sirf-dma.c writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN); base 224 drivers/dma/sirf-dma.c writel_relaxed(readl_relaxed(base + SIRFSOC_DMA_INT_EN) | base 225 drivers/dma/sirf-dma.c (1 << cid), base + SIRFSOC_DMA_INT_EN); base 226 drivers/dma/sirf-dma.c writel(sdesc->addr >> 2, base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR); base 229 drivers/dma/sirf-dma.c readl_relaxed(base + SIRFSOC_DMA_CH_LOOP_CTRL), base 230 drivers/dma/sirf-dma.c base + SIRFSOC_DMA_CH_LOOP_CTRL); base 241 drivers/dma/sirf-dma.c void __iomem *base; base 247 drivers/dma/sirf-dma.c base = sdma->base; base 257 drivers/dma/sirf-dma.c sdma->exec_desc(sdesc, cid, schan->mode, base); base 277 drivers/dma/sirf-dma.c is = readl(sdma->base + SIRFSOC_DMA_CH_INT); base 278 drivers/dma/sirf-dma.c reg = sdma->base + SIRFSOC_DMA_CH_INT; base 300 drivers/dma/sirf-dma.c is = readl(sdma->base + SIRFSOC_DMA_INT_ATLAS7); base 302 drivers/dma/sirf-dma.c reg = sdma->base + SIRFSOC_DMA_INT_ATLAS7; base 453 drivers/dma/sirf-dma.c writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_INT_EN_CLR); base 454 drivers/dma/sirf-dma.c writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_INT); base 456 drivers/dma/sirf-dma.c sdma->base + base 458 drivers/dma/sirf-dma.c writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID); base 461 drivers/dma/sirf-dma.c writel_relaxed(0, sdma->base + SIRFSOC_DMA_INT_EN_ATLAS7); base 463 drivers/dma/sirf-dma.c sdma->base + SIRFSOC_DMA_INT_ATLAS7); base 464 drivers/dma/sirf-dma.c writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7); base 465 drivers/dma/sirf-dma.c writel_relaxed(0, sdma->base + SIRFSOC_DMA_VALID_ATLAS7); base 468 drivers/dma/sirf-dma.c writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) & base 469 drivers/dma/sirf-dma.c ~(1 << cid), sdma->base + SIRFSOC_DMA_INT_EN); base 470 drivers/dma/sirf-dma.c writel_relaxed(readl_relaxed(sdma->base + base 473 drivers/dma/sirf-dma.c sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); base 474 drivers/dma/sirf-dma.c writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID); base 500 drivers/dma/sirf-dma.c sdma->base + base 504 drivers/dma/sirf-dma.c writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7); base 507 drivers/dma/sirf-dma.c writel_relaxed(readl_relaxed(sdma->base + base 510 drivers/dma/sirf-dma.c sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); base 533 drivers/dma/sirf-dma.c sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7); base 537 drivers/dma/sirf-dma.c sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7); base 540 drivers/dma/sirf-dma.c writel_relaxed(readl_relaxed(sdma->base + base 543 drivers/dma/sirf-dma.c sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL); base 674 drivers/dma/sirf-dma.c dma_pos = readl_relaxed(sdma->base + SIRFSOC_DMA_CUR_DATA_ADDR); base 677 drivers/dma/sirf-dma.c sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR) << 2; base 888 drivers/dma/sirf-dma.c sdma->base = devm_ioremap(dev, regs_start, regs_size); base 889 drivers/dma/sirf-dma.c if (!sdma->base) { base 1045 drivers/dma/sirf-dma.c save->ctrl[ch] = readl_relaxed(sdma->base + base 1048 drivers/dma/sirf-dma.c save->interrupt_en = readl_relaxed(sdma->base + int_offset); base 1083 drivers/dma/sirf-dma.c writel_relaxed(save->interrupt_en, sdma->base + int_offset); base 1092 drivers/dma/sirf-dma.c sdma->base + width_offset + ch * 4); base 1094 drivers/dma/sirf-dma.c sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_XLEN); base 1096 drivers/dma/sirf-dma.c sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_YLEN); base 1098 drivers/dma/sirf-dma.c sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_CTRL); base 1101 drivers/dma/sirf-dma.c sdma->base + SIRFSOC_DMA_CH_ADDR); base 1104 drivers/dma/sirf-dma.c sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_ADDR); base 336 drivers/dma/ste_dma40.c void *base; base 392 drivers/dma/ste_dma40.c void *base; base 474 drivers/dma/ste_dma40.c struct d40_base *base; base 620 drivers/dma/ste_dma40.c return chan->base->virtbase + D40_DREG_PCBASE + base 639 drivers/dma/ste_dma40.c void *base; base 647 drivers/dma/ste_dma40.c base = d40d->lli_pool.pre_alloc_lli; base 649 drivers/dma/ste_dma40.c d40d->lli_pool.base = NULL; base 653 drivers/dma/ste_dma40.c base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); base 654 drivers/dma/ste_dma40.c d40d->lli_pool.base = base; base 656 drivers/dma/ste_dma40.c if (d40d->lli_pool.base == NULL) base 661 drivers/dma/ste_dma40.c d40d->lli_log.src = PTR_ALIGN(base, align); base 666 drivers/dma/ste_dma40.c d40d->lli_phy.src = PTR_ALIGN(base, align); base 669 drivers/dma/ste_dma40.c d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev, base 674 drivers/dma/ste_dma40.c if (dma_mapping_error(d40c->base->dev, base 676 drivers/dma/ste_dma40.c kfree(d40d->lli_pool.base); base 677 drivers/dma/ste_dma40.c d40d->lli_pool.base = NULL; base 689 drivers/dma/ste_dma40.c dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr, base 692 drivers/dma/ste_dma40.c kfree(d40d->lli_pool.base); base 693 drivers/dma/ste_dma40.c d40d->lli_pool.base = NULL; base 708 drivers/dma/ste_dma40.c spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); base 717 drivers/dma/ste_dma40.c if (!d40c->base->lcla_pool.alloc_map[idx]) { base 718 drivers/dma/ste_dma40.c d40c->base->lcla_pool.alloc_map[idx] = d40d; base 725 drivers/dma/ste_dma40.c spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); base 740 drivers/dma/ste_dma40.c spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); base 745 drivers/dma/ste_dma40.c if (d40c->base->lcla_pool.alloc_map[idx] == d40d) { base 746 drivers/dma/ste_dma40.c d40c->base->lcla_pool.alloc_map[idx] = NULL; base 755 drivers/dma/ste_dma40.c spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); base 785 drivers/dma/ste_dma40.c desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT); base 798 drivers/dma/ste_dma40.c kmem_cache_free(d40c->base->desc_slab, d40d); base 810 drivers/dma/ste_dma40.c void __iomem *base = chan_base(chan); base 812 drivers/dma/ste_dma40.c writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); base 813 drivers/dma/ste_dma40.c writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT); base 814 drivers/dma/ste_dma40.c writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR); base 815 drivers/dma/ste_dma40.c writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK); base 817 drivers/dma/ste_dma40.c writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); base 818 drivers/dma/ste_dma40.c writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT); base 819 drivers/dma/ste_dma40.c writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR); base 820 drivers/dma/ste_dma40.c writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK); base 830 drivers/dma/ste_dma40.c struct d40_lcla_pool *pool = &chan->base->lcla_pool; base 837 drivers/dma/ste_dma40.c bool use_esram_lcla = chan->base->plat_data->use_esram_lcla; base 890 drivers/dma/ste_dma40.c struct d40_log_lli *lcla = pool->base + lcla_offset; base 924 drivers/dma/ste_dma40.c dma_sync_single_range_for_device(chan->base->dev, base 1054 drivers/dma/ste_dma40.c spin_lock_irqsave(&d40c->base->execmd_lock, flags); base 1057 drivers/dma/ste_dma40.c active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; base 1059 drivers/dma/ste_dma40.c active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; base 1104 drivers/dma/ste_dma40.c spin_unlock_irqrestore(&d40c->base->execmd_lock, flags); base 1274 drivers/dma/ste_dma40.c active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; base 1276 drivers/dma/ste_dma40.c active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; base 1358 drivers/dma/ste_dma40.c writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); base 1363 drivers/dma/ste_dma40.c writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); base 1428 drivers/dma/ste_dma40.c pm_runtime_get_sync(d40c->base->dev); base 1432 drivers/dma/ste_dma40.c pm_runtime_mark_last_busy(d40c->base->dev); base 1433 drivers/dma/ste_dma40.c pm_runtime_put_autosuspend(d40c->base->dev); base 1453 drivers/dma/ste_dma40.c pm_runtime_get_sync(d40c->base->dev); base 1459 drivers/dma/ste_dma40.c pm_runtime_mark_last_busy(d40c->base->dev); base 1460 drivers/dma/ste_dma40.c pm_runtime_put_autosuspend(d40c->base->dev); base 1498 drivers/dma/ste_dma40.c pm_runtime_get_sync(d40c->base->dev); base 1561 drivers/dma/ste_dma40.c pm_runtime_mark_last_busy(d40c->base->dev); base 1562 drivers/dma/ste_dma40.c pm_runtime_put_autosuspend(d40c->base->dev); base 1647 drivers/dma/ste_dma40.c struct d40_base *base = data; base 1648 drivers/dma/ste_dma40.c u32 *regs = base->regs_interrupt; base 1649 drivers/dma/ste_dma40.c struct d40_interrupt_lookup *il = base->gen_dmac.il; base 1650 drivers/dma/ste_dma40.c u32 il_size = base->gen_dmac.il_size; base 1652 drivers/dma/ste_dma40.c spin_lock_irqsave(&base->interrupt_lock, flags); base 1656 drivers/dma/ste_dma40.c regs[i] = readl(base->virtbase + il[i].src); base 1671 drivers/dma/ste_dma40.c d40c = base->lookup_phy_chans[idx]; base 1673 drivers/dma/ste_dma40.c d40c = base->lookup_log_chans[il[row].offset + idx]; base 1684 drivers/dma/ste_dma40.c writel(BIT(idx), base->virtbase + il[row].clr); base 1691 drivers/dma/ste_dma40.c d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n", base 1697 drivers/dma/ste_dma40.c spin_unlock_irqrestore(&base->interrupt_lock, flags); base 1713 drivers/dma/ste_dma40.c if ((is_log && conf->dev_type > d40c->base->num_log_chans) || base 1714 drivers/dma/ste_dma40.c (!is_log && conf->dev_type > d40c->base->num_phy_chans) || base 1845 drivers/dma/ste_dma40.c phys = d40c->base->phy_res; base 1846 drivers/dma/ste_dma40.c num_phy_chans = d40c->base->num_phy_chans; base 1880 drivers/dma/ste_dma40.c for (j = 0; j < d40c->base->num_phy_chans; j += 8) { base 1901 drivers/dma/ste_dma40.c for (j = 0; j < d40c->base->num_phy_chans; j += 8) { base 1951 drivers/dma/ste_dma40.c d40c->base->lookup_log_chans[d40c->log_num] = d40c; base 1953 drivers/dma/ste_dma40.c d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c; base 2021 drivers/dma/ste_dma40.c pm_runtime_get_sync(d40c->base->dev); base 2031 drivers/dma/ste_dma40.c d40c->base->lookup_log_chans[d40c->log_num] = NULL; base 2033 drivers/dma/ste_dma40.c d40c->base->lookup_phy_chans[phy->num] = NULL; base 2036 drivers/dma/ste_dma40.c pm_runtime_mark_last_busy(d40c->base->dev); base 2037 drivers/dma/ste_dma40.c pm_runtime_put_autosuspend(d40c->base->dev); base 2044 drivers/dma/ste_dma40.c pm_runtime_mark_last_busy(d40c->base->dev); base 2045 drivers/dma/ste_dma40.c pm_runtime_put_autosuspend(d40c->base->dev); base 2062 drivers/dma/ste_dma40.c active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; base 2064 drivers/dma/ste_dma40.c active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; base 2164 drivers/dma/ste_dma40.c dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr, base 2302 drivers/dma/ste_dma40.c struct d40_gen_dmac *dmac = &d40c->base->gen_dmac; base 2322 drivers/dma/ste_dma40.c writel(bit, d40c->base->virtbase + prioreg + group * 4); base 2323 drivers/dma/ste_dma40.c writel(bit, d40c->base->virtbase + rtreg + group * 4); base 2328 drivers/dma/ste_dma40.c if (d40c->base->rev < 3) base 2416 drivers/dma/ste_dma40.c pm_runtime_get_sync(d40c->base->dev); base 2422 drivers/dma/ste_dma40.c d40c->lcpa = d40c->base->lcpa_base + base 2425 drivers/dma/ste_dma40.c d40c->lcpa = d40c->base->lcpa_base + base 2448 drivers/dma/ste_dma40.c pm_runtime_mark_last_busy(d40c->base->dev); base 2449 drivers/dma/ste_dma40.c pm_runtime_put_autosuspend(d40c->base->dev); base 2594 drivers/dma/ste_dma40.c pm_runtime_get_sync(d40c->base->dev); base 2600 drivers/dma/ste_dma40.c pm_runtime_mark_last_busy(d40c->base->dev); base 2601 drivers/dma/ste_dma40.c pm_runtime_put_autosuspend(d40c->base->dev); base 2603 drivers/dma/ste_dma40.c pm_runtime_mark_last_busy(d40c->base->dev); base 2604 drivers/dma/ste_dma40.c pm_runtime_put_autosuspend(d40c->base->dev); base 2681 drivers/dma/ste_dma40.c dev_dbg(d40c->base->dev, base 2697 drivers/dma/ste_dma40.c dev_dbg(d40c->base->dev, base 2709 drivers/dma/ste_dma40.c dev_err(d40c->base->dev, base 2716 drivers/dma/ste_dma40.c dev_err(d40c->base->dev, "no address supplied\n"); base 2721 drivers/dma/ste_dma40.c dev_err(d40c->base->dev, base 2769 drivers/dma/ste_dma40.c dev_dbg(d40c->base->dev, base 2782 drivers/dma/ste_dma40.c static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, base 2793 drivers/dma/ste_dma40.c d40c->base = base; base 2815 drivers/dma/ste_dma40.c static void d40_ops_init(struct d40_base *base, struct dma_device *dev) base 2844 drivers/dma/ste_dma40.c dev->dev = base->dev; base 2847 drivers/dma/ste_dma40.c static int __init d40_dmaengine_init(struct d40_base *base, base 2852 drivers/dma/ste_dma40.c d40_chan_init(base, &base->dma_slave, base->log_chans, base 2853 drivers/dma/ste_dma40.c 0, base->num_log_chans); base 2855 drivers/dma/ste_dma40.c dma_cap_zero(base->dma_slave.cap_mask); base 2856 drivers/dma/ste_dma40.c dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); base 2857 drivers/dma/ste_dma40.c dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); base 2859 drivers/dma/ste_dma40.c d40_ops_init(base, &base->dma_slave); base 2861 drivers/dma/ste_dma40.c err = dmaenginem_async_device_register(&base->dma_slave); base 2864 drivers/dma/ste_dma40.c d40_err(base->dev, "Failed to register slave channels\n"); base 2868 drivers/dma/ste_dma40.c d40_chan_init(base, &base->dma_memcpy, base->log_chans, base 2869 drivers/dma/ste_dma40.c base->num_log_chans, base->num_memcpy_chans); base 2871 drivers/dma/ste_dma40.c dma_cap_zero(base->dma_memcpy.cap_mask); base 2872 drivers/dma/ste_dma40.c dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); base 2874 drivers/dma/ste_dma40.c d40_ops_init(base, &base->dma_memcpy); base 2876 drivers/dma/ste_dma40.c err = dmaenginem_async_device_register(&base->dma_memcpy); base 2879 drivers/dma/ste_dma40.c d40_err(base->dev, base 2884 drivers/dma/ste_dma40.c d40_chan_init(base, &base->dma_both, base->phy_chans, base 2887 drivers/dma/ste_dma40.c dma_cap_zero(base->dma_both.cap_mask); base 2888 drivers/dma/ste_dma40.c dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); base 2889 drivers/dma/ste_dma40.c dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); base 2890 drivers/dma/ste_dma40.c dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); base 2892 drivers/dma/ste_dma40.c d40_ops_init(base, &base->dma_both); base 2893 drivers/dma/ste_dma40.c err = dmaenginem_async_device_register(&base->dma_both); base 2896 drivers/dma/ste_dma40.c d40_err(base->dev, base 2909 drivers/dma/ste_dma40.c struct d40_base *base = dev_get_drvdata(dev); base 2916 drivers/dma/ste_dma40.c if (base->lcpa_regulator) base 2917 drivers/dma/ste_dma40.c ret = regulator_disable(base->lcpa_regulator); base 2923 drivers/dma/ste_dma40.c struct d40_base *base = dev_get_drvdata(dev); base 2926 drivers/dma/ste_dma40.c if (base->lcpa_regulator) { base 2927 drivers/dma/ste_dma40.c ret = regulator_enable(base->lcpa_regulator); base 2952 drivers/dma/ste_dma40.c static void d40_save_restore_registers(struct d40_base *base, bool save) base 2957 drivers/dma/ste_dma40.c for (i = 0; i < base->num_phy_chans; i++) { base 2961 drivers/dma/ste_dma40.c if (base->phy_res[i].reserved) base 2964 drivers/dma/ste_dma40.c addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA; base 2967 drivers/dma/ste_dma40.c dma40_backup(addr, &base->reg_val_backup_chan[idx], base 2974 drivers/dma/ste_dma40.c dma40_backup(base->virtbase, base->reg_val_backup, base 2979 drivers/dma/ste_dma40.c if (base->gen_dmac.backup) base 2980 drivers/dma/ste_dma40.c dma40_backup(base->virtbase, base->reg_val_backup_v4, base 2981 drivers/dma/ste_dma40.c base->gen_dmac.backup, base 2982 drivers/dma/ste_dma40.c base->gen_dmac.backup_size, base 2988 drivers/dma/ste_dma40.c struct d40_base *base = dev_get_drvdata(dev); base 2990 drivers/dma/ste_dma40.c d40_save_restore_registers(base, true); base 2993 drivers/dma/ste_dma40.c if (base->rev != 1) base 2994 drivers/dma/ste_dma40.c writel_relaxed(base->gcc_pwr_off_mask, base 2995 drivers/dma/ste_dma40.c base->virtbase + D40_DREG_GCC); base 3002 drivers/dma/ste_dma40.c struct d40_base *base = dev_get_drvdata(dev); base 3004 drivers/dma/ste_dma40.c d40_save_restore_registers(base, false); base 3007 drivers/dma/ste_dma40.c base->virtbase + D40_DREG_GCC); base 3021 drivers/dma/ste_dma40.c static int __init d40_phy_res_init(struct d40_base *base) base 3029 drivers/dma/ste_dma40.c val[0] = readl(base->virtbase + D40_DREG_PRSME); base 3030 drivers/dma/ste_dma40.c val[1] = readl(base->virtbase + D40_DREG_PRSMO); base 3032 drivers/dma/ste_dma40.c for (i = 0; i < base->num_phy_chans; i++) { base 3033 drivers/dma/ste_dma40.c base->phy_res[i].num = i; base 3037 drivers/dma/ste_dma40.c base->phy_res[i].allocated_src = D40_ALLOC_PHY; base 3038 drivers/dma/ste_dma40.c base->phy_res[i].allocated_dst = D40_ALLOC_PHY; base 3039 drivers/dma/ste_dma40.c base->phy_res[i].reserved = true; base 3047 drivers/dma/ste_dma40.c base->phy_res[i].allocated_src = D40_ALLOC_FREE; base 3048 drivers/dma/ste_dma40.c base->phy_res[i].allocated_dst = D40_ALLOC_FREE; base 3049 drivers/dma/ste_dma40.c base->phy_res[i].reserved = false; base 3052 drivers/dma/ste_dma40.c spin_lock_init(&base->phy_res[i].lock); base 3056 drivers/dma/ste_dma40.c for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) { base 3057 drivers/dma/ste_dma40.c int chan = base->plat_data->disabled_channels[i]; base 3059 drivers/dma/ste_dma40.c base->phy_res[chan].allocated_src = D40_ALLOC_PHY; base 3060 drivers/dma/ste_dma40.c base->phy_res[chan].allocated_dst = D40_ALLOC_PHY; base 3061 drivers/dma/ste_dma40.c base->phy_res[chan].reserved = true; base 3070 drivers/dma/ste_dma40.c for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) { base 3071 drivers/dma/ste_dma40.c int chan = base->plat_data->soft_lli_chans[i]; base 3073 drivers/dma/ste_dma40.c base->phy_res[chan].use_soft_lli = true; base 3076 drivers/dma/ste_dma40.c dev_info(base->dev, "%d of %d physical DMA channels available\n", base 3077 drivers/dma/ste_dma40.c num_phy_chans_avail, base->num_phy_chans); base 3080 drivers/dma/ste_dma40.c val[0] = readl(base->virtbase + D40_DREG_PRTYP); base 3082 drivers/dma/ste_dma40.c for (i = 0; i < base->num_phy_chans; i++) { base 3084 drivers/dma/ste_dma40.c if (base->phy_res[i].allocated_src == D40_ALLOC_FREE && base 3086 drivers/dma/ste_dma40.c dev_info(base->dev, base 3099 drivers/dma/ste_dma40.c writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC); base 3100 drivers/dma/ste_dma40.c base->gcc_pwr_off_mask = gcc; base 3111 drivers/dma/ste_dma40.c struct d40_base *base; base 3197 drivers/dma/ste_dma40.c base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + base 3201 drivers/dma/ste_dma40.c if (base == NULL) base 3204 drivers/dma/ste_dma40.c base->rev = rev; base 3205 drivers/dma/ste_dma40.c base->clk = clk; base 3206 drivers/dma/ste_dma40.c base->num_memcpy_chans = num_memcpy_chans; base 3207 drivers/dma/ste_dma40.c base->num_phy_chans = num_phy_chans; base 3208 drivers/dma/ste_dma40.c base->num_log_chans = num_log_chans; base 3209 drivers/dma/ste_dma40.c base->phy_start = res->start; base 3210 drivers/dma/ste_dma40.c base->phy_size = resource_size(res); base 3211 drivers/dma/ste_dma40.c base->virtbase = virtbase; base 3212 drivers/dma/ste_dma40.c base->plat_data = plat_data; base 3213 drivers/dma/ste_dma40.c base->dev = &pdev->dev; base 3214 drivers/dma/ste_dma40.c base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4); base 3215 drivers/dma/ste_dma40.c base->log_chans = &base->phy_chans[num_phy_chans]; base 3217 drivers/dma/ste_dma40.c if (base->plat_data->num_of_phy_chans == 14) { base 3218 drivers/dma/ste_dma40.c base->gen_dmac.backup = d40_backup_regs_v4b; base 3219 drivers/dma/ste_dma40.c base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B; base 3220 drivers/dma/ste_dma40.c base->gen_dmac.interrupt_en = D40_DREG_CPCMIS; base 3221 drivers/dma/ste_dma40.c base->gen_dmac.interrupt_clear = D40_DREG_CPCICR; base 3222 drivers/dma/ste_dma40.c base->gen_dmac.realtime_en = D40_DREG_CRSEG1; base 3223 drivers/dma/ste_dma40.c base->gen_dmac.realtime_clear = D40_DREG_CRCEG1; base 3224 drivers/dma/ste_dma40.c base->gen_dmac.high_prio_en = D40_DREG_CPSEG1; base 3225 drivers/dma/ste_dma40.c base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1; base 3226 drivers/dma/ste_dma40.c base->gen_dmac.il = il_v4b; base 3227 drivers/dma/ste_dma40.c base->gen_dmac.il_size = ARRAY_SIZE(il_v4b); base 3228 drivers/dma/ste_dma40.c base->gen_dmac.init_reg = dma_init_reg_v4b; base 3229 drivers/dma/ste_dma40.c base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b); base 3231 drivers/dma/ste_dma40.c if (base->rev >= 3) { base 3232 drivers/dma/ste_dma40.c base->gen_dmac.backup = d40_backup_regs_v4a; base 3233 drivers/dma/ste_dma40.c base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A; base 3235 drivers/dma/ste_dma40.c base->gen_dmac.interrupt_en = D40_DREG_PCMIS; base 3236 drivers/dma/ste_dma40.c base->gen_dmac.interrupt_clear = D40_DREG_PCICR; base 3237 drivers/dma/ste_dma40.c base->gen_dmac.realtime_en = D40_DREG_RSEG1; base 3238 drivers/dma/ste_dma40.c base->gen_dmac.realtime_clear = D40_DREG_RCEG1; base 3239 drivers/dma/ste_dma40.c base->gen_dmac.high_prio_en = D40_DREG_PSEG1; base 3240 drivers/dma/ste_dma40.c base->gen_dmac.high_prio_clear = D40_DREG_PCEG1; base 3241 drivers/dma/ste_dma40.c base->gen_dmac.il = il_v4a; base 3242 drivers/dma/ste_dma40.c base->gen_dmac.il_size = ARRAY_SIZE(il_v4a); base 3243 drivers/dma/ste_dma40.c base->gen_dmac.init_reg = dma_init_reg_v4a; base 3244 drivers/dma/ste_dma40.c base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a); base 3247 drivers/dma/ste_dma40.c base->phy_res = kcalloc(num_phy_chans, base 3248 drivers/dma/ste_dma40.c sizeof(*base->phy_res), base 3250 drivers/dma/ste_dma40.c if (!base->phy_res) base 3253 drivers/dma/ste_dma40.c base->lookup_phy_chans = kcalloc(num_phy_chans, base 3254 drivers/dma/ste_dma40.c sizeof(*base->lookup_phy_chans), base 3256 drivers/dma/ste_dma40.c if (!base->lookup_phy_chans) base 3259 drivers/dma/ste_dma40.c base->lookup_log_chans = kcalloc(num_log_chans, base 3260 drivers/dma/ste_dma40.c sizeof(*base->lookup_log_chans), base 3262 drivers/dma/ste_dma40.c if (!base->lookup_log_chans) base 3265 drivers/dma/ste_dma40.c base->reg_val_backup_chan = kmalloc_array(base->num_phy_chans, base 3268 drivers/dma/ste_dma40.c if (!base->reg_val_backup_chan) base 3271 drivers/dma/ste_dma40.c base->lcla_pool.alloc_map = kcalloc(num_phy_chans base 3273 drivers/dma/ste_dma40.c sizeof(*base->lcla_pool.alloc_map), base 3275 drivers/dma/ste_dma40.c if (!base->lcla_pool.alloc_map) base 3278 drivers/dma/ste_dma40.c base->regs_interrupt = kmalloc_array(base->gen_dmac.il_size, base 3279 drivers/dma/ste_dma40.c sizeof(*base->regs_interrupt), base 3281 drivers/dma/ste_dma40.c if (!base->regs_interrupt) base 3284 drivers/dma/ste_dma40.c base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc), base 3287 drivers/dma/ste_dma40.c if (base->desc_slab == NULL) base 3291 drivers/dma/ste_dma40.c return base; base 3293 drivers/dma/ste_dma40.c kfree(base->regs_interrupt); base 3295 drivers/dma/ste_dma40.c kfree(base->lcla_pool.alloc_map); base 3297 drivers/dma/ste_dma40.c kfree(base->reg_val_backup_chan); base 3299 drivers/dma/ste_dma40.c kfree(base->lookup_log_chans); base 3301 drivers/dma/ste_dma40.c kfree(base->lookup_phy_chans); base 3303 drivers/dma/ste_dma40.c kfree(base->phy_res); base 3305 drivers/dma/ste_dma40.c kfree(base); base 3319 drivers/dma/ste_dma40.c static void __init d40_hw_init(struct d40_base *base) base 3327 drivers/dma/ste_dma40.c struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg; base 3328 drivers/dma/ste_dma40.c u32 reg_size = base->gen_dmac.init_reg_size; base 3332 drivers/dma/ste_dma40.c base->virtbase + dma_init_reg[i].reg); base 3335 drivers/dma/ste_dma40.c for (i = 0; i < base->num_phy_chans; i++) { base 3339 drivers/dma/ste_dma40.c if (base->phy_res[base->num_phy_chans - i - 1].allocated_src base 3357 drivers/dma/ste_dma40.c writel(prmseo[1], base->virtbase + D40_DREG_PRMSE); base 3358 drivers/dma/ste_dma40.c writel(prmseo[0], base->virtbase + D40_DREG_PRMSO); base 3359 drivers/dma/ste_dma40.c writel(activeo[1], base->virtbase + D40_DREG_ACTIVE); base 3360 drivers/dma/ste_dma40.c writel(activeo[0], base->virtbase + D40_DREG_ACTIVO); base 3363 drivers/dma/ste_dma40.c writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en); base 3366 drivers/dma/ste_dma40.c writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear); base 3369 drivers/dma/ste_dma40.c base->gen_dmac.init_reg = NULL; base 3370 drivers/dma/ste_dma40.c base->gen_dmac.init_reg_size = 0; base 3373 drivers/dma/ste_dma40.c static int __init d40_lcla_allocate(struct d40_base *base) base 3375 drivers/dma/ste_dma40.c struct d40_lcla_pool *pool = &base->lcla_pool; base 3392 drivers/dma/ste_dma40.c base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; base 3396 drivers/dma/ste_dma40.c base->lcla_pool.pages); base 3399 drivers/dma/ste_dma40.c d40_err(base->dev, "Failed to allocate %d pages.\n", base 3400 drivers/dma/ste_dma40.c base->lcla_pool.pages); base 3404 drivers/dma/ste_dma40.c free_pages(page_list[j], base->lcla_pool.pages); base 3414 drivers/dma/ste_dma40.c free_pages(page_list[j], base->lcla_pool.pages); base 3417 drivers/dma/ste_dma40.c base->lcla_pool.base = (void *)page_list[i]; base 3423 drivers/dma/ste_dma40.c dev_warn(base->dev, base 3425 drivers/dma/ste_dma40.c __func__, base->lcla_pool.pages); base 3426 drivers/dma/ste_dma40.c base->lcla_pool.base_unaligned = kmalloc(SZ_1K * base 3427 drivers/dma/ste_dma40.c base->num_phy_chans + base 3430 drivers/dma/ste_dma40.c if (!base->lcla_pool.base_unaligned) { base 3435 drivers/dma/ste_dma40.c base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned, base 3439 drivers/dma/ste_dma40.c pool->dma_addr = dma_map_single(base->dev, pool->base, base 3440 drivers/dma/ste_dma40.c SZ_1K * base->num_phy_chans, base 3442 drivers/dma/ste_dma40.c if (dma_mapping_error(base->dev, pool->dma_addr)) { base 3448 drivers/dma/ste_dma40.c writel(virt_to_phys(base->lcla_pool.base), base 3449 drivers/dma/ste_dma40.c base->virtbase + D40_DREG_LCLA); base 3512 drivers/dma/ste_dma40.c struct d40_base *base; base 3529 drivers/dma/ste_dma40.c base = d40_hw_detect_init(pdev); base 3530 drivers/dma/ste_dma40.c if (!base) base 3533 drivers/dma/ste_dma40.c num_reserved_chans = d40_phy_res_init(base); base 3535 drivers/dma/ste_dma40.c platform_set_drvdata(pdev, base); base 3537 drivers/dma/ste_dma40.c spin_lock_init(&base->interrupt_lock); base 3538 drivers/dma/ste_dma40.c spin_lock_init(&base->execmd_lock); base 3547 drivers/dma/ste_dma40.c base->lcpa_size = resource_size(res); base 3548 drivers/dma/ste_dma40.c base->phy_lcpa = res->start; base 3558 drivers/dma/ste_dma40.c val = readl(base->virtbase + D40_DREG_LCPA); base 3564 drivers/dma/ste_dma40.c writel(res->start, base->virtbase + D40_DREG_LCPA); base 3566 drivers/dma/ste_dma40.c base->lcpa_base = ioremap(res->start, resource_size(res)); base 3567 drivers/dma/ste_dma40.c if (!base->lcpa_base) { base 3573 drivers/dma/ste_dma40.c if (base->plat_data->use_esram_lcla) { base 3582 drivers/dma/ste_dma40.c base->lcla_pool.base = ioremap(res->start, base 3584 drivers/dma/ste_dma40.c if (!base->lcla_pool.base) { base 3589 drivers/dma/ste_dma40.c writel(res->start, base->virtbase + D40_DREG_LCLA); base 3592 drivers/dma/ste_dma40.c ret = d40_lcla_allocate(base); base 3599 drivers/dma/ste_dma40.c spin_lock_init(&base->lcla_pool.lock); base 3601 drivers/dma/ste_dma40.c base->irq = platform_get_irq(pdev, 0); base 3603 drivers/dma/ste_dma40.c ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); base 3609 drivers/dma/ste_dma40.c if (base->plat_data->use_esram_lcla) { base 3611 drivers/dma/ste_dma40.c base->lcpa_regulator = regulator_get(base->dev, "lcla_esram"); base 3612 drivers/dma/ste_dma40.c if (IS_ERR(base->lcpa_regulator)) { base 3614 drivers/dma/ste_dma40.c ret = PTR_ERR(base->lcpa_regulator); base 3615 drivers/dma/ste_dma40.c base->lcpa_regulator = NULL; base 3619 drivers/dma/ste_dma40.c ret = regulator_enable(base->lcpa_regulator); base 3623 drivers/dma/ste_dma40.c regulator_put(base->lcpa_regulator); base 3624 drivers/dma/ste_dma40.c base->lcpa_regulator = NULL; base 3629 drivers/dma/ste_dma40.c writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC); base 3631 drivers/dma/ste_dma40.c pm_runtime_irq_safe(base->dev); base 3632 drivers/dma/ste_dma40.c pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY); base 3633 drivers/dma/ste_dma40.c pm_runtime_use_autosuspend(base->dev); base 3634 drivers/dma/ste_dma40.c pm_runtime_mark_last_busy(base->dev); base 3635 drivers/dma/ste_dma40.c pm_runtime_set_active(base->dev); base 3636 drivers/dma/ste_dma40.c pm_runtime_enable(base->dev); base 3638 drivers/dma/ste_dma40.c ret = d40_dmaengine_init(base, num_reserved_chans); base 3642 drivers/dma/ste_dma40.c base->dev->dma_parms = &base->dma_parms; base 3643 drivers/dma/ste_dma40.c ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE); base 3649 drivers/dma/ste_dma40.c d40_hw_init(base); base 3658 drivers/dma/ste_dma40.c dev_info(base->dev, "initialized\n"); base 3661 drivers/dma/ste_dma40.c kmem_cache_destroy(base->desc_slab); base 3662 drivers/dma/ste_dma40.c if (base->virtbase) base 3663 drivers/dma/ste_dma40.c iounmap(base->virtbase); base 3665 drivers/dma/ste_dma40.c if (base->lcla_pool.base && base->plat_data->use_esram_lcla) { base 3666 drivers/dma/ste_dma40.c iounmap(base->lcla_pool.base); base 3667 drivers/dma/ste_dma40.c base->lcla_pool.base = NULL; base 3670 drivers/dma/ste_dma40.c if (base->lcla_pool.dma_addr) base 3671 drivers/dma/ste_dma40.c dma_unmap_single(base->dev, base->lcla_pool.dma_addr, base 3672 drivers/dma/ste_dma40.c SZ_1K * base->num_phy_chans, base 3675 drivers/dma/ste_dma40.c if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) base 3676 drivers/dma/ste_dma40.c free_pages((unsigned long)base->lcla_pool.base, base 3677 drivers/dma/ste_dma40.c base->lcla_pool.pages); base 3679 drivers/dma/ste_dma40.c kfree(base->lcla_pool.base_unaligned); base 3681 drivers/dma/ste_dma40.c if (base->phy_lcpa) base 3682 drivers/dma/ste_dma40.c release_mem_region(base->phy_lcpa, base 3683 drivers/dma/ste_dma40.c base->lcpa_size); base 3684 drivers/dma/ste_dma40.c if (base->phy_start) base 3685 drivers/dma/ste_dma40.c release_mem_region(base->phy_start, base 3686 drivers/dma/ste_dma40.c base->phy_size); base 3687 drivers/dma/ste_dma40.c if (base->clk) { base 3688 drivers/dma/ste_dma40.c clk_disable_unprepare(base->clk); base 3689 drivers/dma/ste_dma40.c clk_put(base->clk); base 3692 drivers/dma/ste_dma40.c if (base->lcpa_regulator) { base 3693 drivers/dma/ste_dma40.c regulator_disable(base->lcpa_regulator); base 3694 drivers/dma/ste_dma40.c regulator_put(base->lcpa_regulator); base 3697 drivers/dma/ste_dma40.c kfree(base->lcla_pool.alloc_map); base 3698 drivers/dma/ste_dma40.c kfree(base->lookup_log_chans); base 3699 drivers/dma/ste_dma40.c kfree(base->lookup_phy_chans); base 3700 drivers/dma/ste_dma40.c kfree(base->phy_res); base 3701 drivers/dma/ste_dma40.c kfree(base); base 208 drivers/dma/stm32-dma.c void __iomem *base; base 238 drivers/dma/stm32-dma.c return readl_relaxed(dmadev->base + reg); base 243 drivers/dma/stm32-dma.c writel_relaxed(val, dmadev->base + reg); base 1293 drivers/dma/stm32-dma.c dmadev->base = devm_ioremap_resource(&pdev->dev, res); base 1294 drivers/dma/stm32-dma.c if (IS_ERR(dmadev->base)) base 1295 drivers/dma/stm32-dma.c return PTR_ERR(dmadev->base); base 273 drivers/dma/stm32-mdma.c void __iomem *base; base 313 drivers/dma/stm32-mdma.c return readl_relaxed(dmadev->base + reg); base 318 drivers/dma/stm32-mdma.c writel_relaxed(val, dmadev->base + reg); base 324 drivers/dma/stm32-mdma.c void __iomem *addr = dmadev->base + reg; base 332 drivers/dma/stm32-mdma.c void __iomem *addr = dmadev->base + reg; base 445 drivers/dma/stm32-mdma.c dmadev->base + STM32_MDMA_CISR(id), cisr, base 1350 drivers/dma/stm32-mdma.c status = readl_relaxed(dmadev->base + STM32_MDMA_GISR0); base 1354 drivers/dma/stm32-mdma.c status = readl_relaxed(dmadev->base + STM32_MDMA_GISR1); base 1394 drivers/dma/stm32-mdma.c status = readl_relaxed(dmadev->base + STM32_MDMA_CESR(id)); base 1575 drivers/dma/stm32-mdma.c dmadev->base = devm_ioremap_resource(&pdev->dev, res); base 1576 drivers/dma/stm32-mdma.c if (IS_ERR(dmadev->base)) base 1577 drivers/dma/stm32-mdma.c return PTR_ERR(dmadev->base); base 127 drivers/dma/sun4i-dma.c void __iomem *base; base 166 drivers/dma/sun4i-dma.c void __iomem *base; base 270 drivers/dma/sun4i-dma.c writel_relaxed(d->src, pchan->base + SUN4I_DDMA_SRC_ADDR_REG); base 271 drivers/dma/sun4i-dma.c writel_relaxed(d->dst, pchan->base + SUN4I_DDMA_DST_ADDR_REG); base 272 drivers/dma/sun4i-dma.c writel_relaxed(d->len, pchan->base + SUN4I_DDMA_BYTE_COUNT_REG); base 273 drivers/dma/sun4i-dma.c writel_relaxed(d->para, pchan->base + SUN4I_DDMA_PARA_REG); base 274 drivers/dma/sun4i-dma.c writel_relaxed(d->cfg, pchan->base + SUN4I_DDMA_CFG_REG); base 276 drivers/dma/sun4i-dma.c writel_relaxed(d->src, pchan->base + SUN4I_NDMA_SRC_ADDR_REG); base 277 drivers/dma/sun4i-dma.c writel_relaxed(d->dst, pchan->base + SUN4I_NDMA_DST_ADDR_REG); base 278 drivers/dma/sun4i-dma.c writel_relaxed(d->len, pchan->base + SUN4I_NDMA_BYTE_COUNT_REG); base 279 drivers/dma/sun4i-dma.c writel_relaxed(d->cfg, pchan->base + SUN4I_NDMA_CFG_REG); base 293 drivers/dma/sun4i-dma.c reg = readl_relaxed(priv->base + SUN4I_DMA_IRQ_ENABLE_REG); base 305 drivers/dma/sun4i-dma.c writel_relaxed(reg, priv->base + SUN4I_DMA_IRQ_ENABLE_REG); base 880 drivers/dma/sun4i-dma.c writel(0, pchan->base + SUN4I_DDMA_CFG_REG); base 882 drivers/dma/sun4i-dma.c writel(0, pchan->base + SUN4I_NDMA_CFG_REG); base 973 drivers/dma/sun4i-dma.c bytes += readl(pchan->base + SUN4I_DDMA_BYTE_COUNT_REG); base 975 drivers/dma/sun4i-dma.c bytes += readl(pchan->base + SUN4I_NDMA_BYTE_COUNT_REG); base 1014 drivers/dma/sun4i-dma.c pendirq = readl_relaxed(priv->base + SUN4I_DMA_IRQ_PENDING_STATUS_REG); base 1082 drivers/dma/sun4i-dma.c irqs = readl_relaxed(priv->base + SUN4I_DMA_IRQ_ENABLE_REG); base 1084 drivers/dma/sun4i-dma.c priv->base + SUN4I_DMA_IRQ_ENABLE_REG); base 1088 drivers/dma/sun4i-dma.c writel_relaxed(pendirq, priv->base + SUN4I_DMA_IRQ_PENDING_STATUS_REG); base 1108 drivers/dma/sun4i-dma.c pendirq = readl_relaxed(priv->base + base 1130 drivers/dma/sun4i-dma.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 1131 drivers/dma/sun4i-dma.c if (IS_ERR(priv->base)) base 1132 drivers/dma/sun4i-dma.c return PTR_ERR(priv->base); base 1188 drivers/dma/sun4i-dma.c priv->pchans[i].base = priv->base + base 1192 drivers/dma/sun4i-dma.c priv->pchans[i].base = priv->base + base 1215 drivers/dma/sun4i-dma.c writel(0, priv->base + SUN4I_DMA_IRQ_ENABLE_REG); base 1216 drivers/dma/sun4i-dma.c writel(0xFFFFFFFF, priv->base + SUN4I_DMA_IRQ_PENDING_STATUS_REG); base 169 drivers/dma/sun6i-dma.c void __iomem *base; base 187 drivers/dma/sun6i-dma.c void __iomem *base; base 234 drivers/dma/sun6i-dma.c DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)), base 235 drivers/dma/sun6i-dma.c DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)), base 236 drivers/dma/sun6i-dma.c DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)), base 237 drivers/dma/sun6i-dma.c DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)), base 238 drivers/dma/sun6i-dma.c DMA_STAT, readl(sdev->base + DMA_STAT)); base 244 drivers/dma/sun6i-dma.c phys_addr_t reg = virt_to_phys(pchan->base); base 257 drivers/dma/sun6i-dma.c readl(pchan->base + DMA_CHAN_ENABLE), base 259 drivers/dma/sun6i-dma.c readl(pchan->base + DMA_CHAN_PAUSE), base 261 drivers/dma/sun6i-dma.c readl(pchan->base + DMA_CHAN_LLI_ADDR), base 263 drivers/dma/sun6i-dma.c readl(pchan->base + DMA_CHAN_CUR_CFG), base 265 drivers/dma/sun6i-dma.c readl(pchan->base + DMA_CHAN_CUR_SRC), base 267 drivers/dma/sun6i-dma.c readl(pchan->base + DMA_CHAN_CUR_DST), base 269 drivers/dma/sun6i-dma.c readl(pchan->base + DMA_CHAN_CUR_CNT), base 271 drivers/dma/sun6i-dma.c readl(pchan->base + DMA_CHAN_CUR_PARA)); base 297 drivers/dma/sun6i-dma.c writel(SUN8I_DMA_GATE_ENABLE, sdev->base + SUN8I_DMA_GATE); base 302 drivers/dma/sun6i-dma.c writel(SUNXI_H3_DMA_GATE_ENABLE, sdev->base + SUNXI_H3_DMA_GATE); base 348 drivers/dma/sun6i-dma.c pos = readl(pchan->base + DMA_CHAN_LLI_ADDR); base 349 drivers/dma/sun6i-dma.c bytes = readl(pchan->base + DMA_CHAN_CUR_CNT); base 455 drivers/dma/sun6i-dma.c irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg)); base 459 drivers/dma/sun6i-dma.c writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); base 461 drivers/dma/sun6i-dma.c writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR); base 462 drivers/dma/sun6i-dma.c writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE); base 544 drivers/dma/sun6i-dma.c status = readl(sdev->base + DMA_IRQ_STAT(i)); base 551 drivers/dma/sun6i-dma.c writel(status, sdev->base + DMA_IRQ_STAT(i)); base 849 drivers/dma/sun6i-dma.c pchan->base + DMA_CHAN_PAUSE); base 872 drivers/dma/sun6i-dma.c pchan->base + DMA_CHAN_PAUSE); base 911 drivers/dma/sun6i-dma.c writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE); base 912 drivers/dma/sun6i-dma.c writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE); base 1029 drivers/dma/sun6i-dma.c writel(0, sdev->base + DMA_IRQ_EN(0)); base 1030 drivers/dma/sun6i-dma.c writel(0, sdev->base + DMA_IRQ_EN(1)); base 1249 drivers/dma/sun6i-dma.c sdc->base = devm_ioremap_resource(&pdev->dev, res); base 1250 drivers/dma/sun6i-dma.c if (IS_ERR(sdc->base)) base 1251 drivers/dma/sun6i-dma.c return PTR_ERR(sdc->base); base 1352 drivers/dma/sun6i-dma.c pchan->base = sdc->base + 0x100 + i * 0x40; base 241 drivers/dma/ti/edma.c void __iomem *base; base 304 drivers/dma/ti/edma.c return (unsigned int)__raw_readl(ecc->base + offset); base 309 drivers/dma/ti/edma.c __raw_writel(val, ecc->base + offset); base 470 drivers/dma/ti/edma.c memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); base 479 drivers/dma/ti/edma.c memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); base 2312 drivers/dma/ti/edma.c ecc->base = devm_ioremap_resource(dev, mem); base 2313 drivers/dma/ti/edma.c if (IS_ERR(ecc->base)) base 2314 drivers/dma/ti/edma.c return PTR_ERR(ecc->base); base 29 drivers/dma/ti/omap-dma.c void __iomem *base; base 335 drivers/dma/ti/omap-dma.c omap_dma_write(val, r->type, od->base + r->offset); base 344 drivers/dma/ti/omap-dma.c return omap_dma_read(r->type, od->base + r->offset); base 382 drivers/dma/ti/omap-dma.c c->channel_base = od->base + od->plat->channel_stride * lch; base 1472 drivers/dma/ti/omap-dma.c od->base = devm_ioremap_resource(&pdev->dev, res); base 1473 drivers/dma/ti/omap-dma.c if (IS_ERR(od->base)) base 1474 drivers/dma/ti/omap-dma.c return PTR_ERR(od->base); base 111 drivers/dma/zx_dma.c void __iomem *base; base 119 drivers/dma/zx_dma.c void __iomem *base; base 142 drivers/dma/zx_dma.c val = readl_relaxed(phy->base + REG_ZX_CTRL); base 145 drivers/dma/zx_dma.c writel_relaxed(val, phy->base + REG_ZX_CTRL); base 148 drivers/dma/zx_dma.c writel_relaxed(val, d->base + REG_ZX_TC_IRQ_RAW); base 149 drivers/dma/zx_dma.c writel_relaxed(val, d->base + REG_ZX_SRC_ERR_IRQ_RAW); base 150 drivers/dma/zx_dma.c writel_relaxed(val, d->base + REG_ZX_DST_ERR_IRQ_RAW); base 151 drivers/dma/zx_dma.c writel_relaxed(val, d->base + REG_ZX_CFG_ERR_IRQ_RAW); base 156 drivers/dma/zx_dma.c writel_relaxed(hw->saddr, phy->base + REG_ZX_SRC_ADDR); base 157 drivers/dma/zx_dma.c writel_relaxed(hw->daddr, phy->base + REG_ZX_DST_ADDR); base 158 drivers/dma/zx_dma.c writel_relaxed(hw->src_x, phy->base + REG_ZX_TX_X_COUNT); base 159 drivers/dma/zx_dma.c writel_relaxed(0, phy->base + REG_ZX_TX_ZY_COUNT); base 160 drivers/dma/zx_dma.c writel_relaxed(0, phy->base + REG_ZX_SRC_ZY_STEP); base 161 drivers/dma/zx_dma.c writel_relaxed(0, phy->base + REG_ZX_DST_ZY_STEP); base 162 drivers/dma/zx_dma.c writel_relaxed(hw->lli, phy->base + REG_ZX_LLI_ADDR); base 163 drivers/dma/zx_dma.c writel_relaxed(hw->ctr, phy->base + REG_ZX_CTRL); base 168 drivers/dma/zx_dma.c return readl_relaxed(phy->base + REG_ZX_LLI_ADDR); base 173 drivers/dma/zx_dma.c return readl_relaxed(d->base + REG_ZX_STATUS); base 179 drivers/dma/zx_dma.c writel_relaxed(0x0, d->base + REG_ZX_DMA_ARB); base 181 drivers/dma/zx_dma.c writel_relaxed(0xffffffff, d->base + REG_ZX_TC_IRQ_RAW); base 182 drivers/dma/zx_dma.c writel_relaxed(0xffffffff, d->base + REG_ZX_SRC_ERR_IRQ_RAW); base 183 drivers/dma/zx_dma.c writel_relaxed(0xffffffff, d->base + REG_ZX_DST_ERR_IRQ_RAW); base 184 drivers/dma/zx_dma.c writel_relaxed(0xffffffff, d->base + REG_ZX_CFG_ERR_IRQ_RAW); base 276 drivers/dma/zx_dma.c u32 tc = readl_relaxed(d->base + REG_ZX_TC_IRQ); base 277 drivers/dma/zx_dma.c u32 serr = readl_relaxed(d->base + REG_ZX_SRC_ERR_IRQ); base 278 drivers/dma/zx_dma.c u32 derr = readl_relaxed(d->base + REG_ZX_DST_ERR_IRQ); base 279 drivers/dma/zx_dma.c u32 cfg = readl_relaxed(d->base + REG_ZX_CFG_ERR_IRQ); base 307 drivers/dma/zx_dma.c writel_relaxed(irq_chan, d->base + REG_ZX_TC_IRQ_RAW); base 308 drivers/dma/zx_dma.c writel_relaxed(serr, d->base + REG_ZX_SRC_ERR_IRQ_RAW); base 309 drivers/dma/zx_dma.c writel_relaxed(derr, d->base + REG_ZX_DST_ERR_IRQ_RAW); base 310 drivers/dma/zx_dma.c writel_relaxed(cfg, d->base + REG_ZX_CFG_ERR_IRQ_RAW); base 696 drivers/dma/zx_dma.c val = readl_relaxed(c->phy->base + REG_ZX_CTRL); base 698 drivers/dma/zx_dma.c writel_relaxed(val, c->phy->base + REG_ZX_CTRL); base 708 drivers/dma/zx_dma.c val = readl_relaxed(c->phy->base + REG_ZX_CTRL); base 710 drivers/dma/zx_dma.c writel_relaxed(val, c->phy->base + REG_ZX_CTRL); base 768 drivers/dma/zx_dma.c d->base = devm_ioremap_resource(&op->dev, iores); base 769 drivers/dma/zx_dma.c if (IS_ERR(d->base)) base 770 drivers/dma/zx_dma.c return PTR_ERR(d->base); base 807 drivers/dma/zx_dma.c p->base = d->base + i * 0x40; base 618 drivers/edac/altera_edac.c writel(priv->ce_clear_mask, drvdata->base); base 623 drivers/edac/altera_edac.c writel(priv->ue_clear_mask, drvdata->base); base 681 drivers/edac/altera_edac.c writel(error_mask, (drvdata->base + priv->set_err_ofst)); base 682 drivers/edac/altera_edac.c writel(priv->ecc_enable_mask, (drvdata->base + base 816 drivers/edac/altera_edac.c drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); base 817 drivers/edac/altera_edac.c if (!drvdata->base) { base 902 drivers/edac/altera_edac.c void __iomem *base = device->base; base 905 drivers/edac/altera_edac.c if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask) base 917 drivers/edac/altera_edac.c void __iomem *base = dci->base; base 921 drivers/edac/altera_edac.c base + ALTR_A10_ECC_INTSTAT_OFST); base 927 drivers/edac/altera_edac.c base + ALTR_A10_ECC_INTSTAT_OFST); base 1043 drivers/edac/altera_edac.c uintptr_t base; base 1059 drivers/edac/altera_edac.c base = res.start; base 1061 drivers/edac/altera_edac.c ecc_mgr_map = regmap_init(NULL, NULL, (void *)base, base 1247 drivers/edac/altera_edac.c void __iomem *base = device->base; base 1256 drivers/edac/altera_edac.c (base + ALTR_A10_ECC_INITSTAT_OFST))) base 1260 drivers/edac/altera_edac.c writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST)); base 1332 drivers/edac/altera_edac.c void __iomem *base = device->base; base 1335 drivers/edac/altera_edac.c if ((readl(base) & prv->ecc_enable_mask) == base 1704 drivers/edac/altera_edac.c void __iomem *base = ad->base; base 1709 drivers/edac/altera_edac.c base + ALTR_A10_ECC_INTSTAT_OFST); base 1714 drivers/edac/altera_edac.c base + ALTR_A10_ECC_INTSTAT_OFST); base 1801 drivers/edac/altera_edac.c void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); base 1833 drivers/edac/altera_edac.c void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); base 1845 drivers/edac/altera_edac.c writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST); base 1847 drivers/edac/altera_edac.c writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST); base 1849 drivers/edac/altera_edac.c writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); base 1851 drivers/edac/altera_edac.c writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); base 1853 drivers/edac/altera_edac.c writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1, base 1854 drivers/edac/altera_edac.c drvdata->base + ECC_BLK_WDATA0_OFST); base 1855 drivers/edac/altera_edac.c writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST), base 1856 drivers/edac/altera_edac.c drvdata->base + ECC_BLK_WDATA1_OFST); base 1857 drivers/edac/altera_edac.c writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST), base 1858 drivers/edac/altera_edac.c drvdata->base + ECC_BLK_WDATA2_OFST); base 1859 drivers/edac/altera_edac.c writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST), base 1860 drivers/edac/altera_edac.c drvdata->base + ECC_BLK_WDATA3_OFST); base 1863 drivers/edac/altera_edac.c writel(readl(drvdata->base + ECC_BLK_RECC0_OFST), base 1864 drivers/edac/altera_edac.c drvdata->base + ECC_BLK_WECC0_OFST); base 1865 drivers/edac/altera_edac.c writel(readl(drvdata->base + ECC_BLK_RECC1_OFST), base 1866 drivers/edac/altera_edac.c drvdata->base + ECC_BLK_WECC1_OFST); base 1868 drivers/edac/altera_edac.c writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); base 1870 drivers/edac/altera_edac.c writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); base 1872 drivers/edac/altera_edac.c writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); base 1874 drivers/edac/altera_edac.c writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); base 2007 drivers/edac/altera_edac.c altdev->base = devm_ioremap_resource(edac->dev, &res); base 2008 drivers/edac/altera_edac.c if (IS_ERR(altdev->base)) { base 2009 drivers/edac/altera_edac.c rc = PTR_ERR(altdev->base); base 2149 drivers/edac/altera_edac.c ed->base + ALTR_A10_ECC_INTSTAT_OFST); base 2150 drivers/edac/altera_edac.c err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST); base 2189 drivers/edac/altera_edac.c uintptr_t base; base 2203 drivers/edac/altera_edac.c base = res.start; base 2206 drivers/edac/altera_edac.c (void *)base, base 375 drivers/edac/altera_edac.h void __iomem *base; base 392 drivers/edac/amd64_edac.c u64 *base, u64 *mask) base 413 drivers/edac/amd64_edac.c *base = (csbase & GENMASK_ULL(15, 5)) << 6; base 414 drivers/edac/amd64_edac.c *base |= (csbase & GENMASK_ULL(30, 19)) << 8; base 438 drivers/edac/amd64_edac.c *base = (csbase & base_bits) << addr_shift; base 467 drivers/edac/amd64_edac.c u64 base, mask; base 475 drivers/edac/amd64_edac.c get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); base 479 drivers/edac/amd64_edac.c if ((input_addr & mask) == (base & mask)) { base 959 drivers/edac/amd64_edac.c u32 *base, *base_sec; base 968 drivers/edac/amd64_edac.c base = &pvt->csels[umc].csbases[cs]; base 974 drivers/edac/amd64_edac.c if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) base 976 drivers/edac/amd64_edac.c umc, cs, *base, base_reg); base 1232 drivers/edac/amd64_edac.c amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); base 1241 drivers/edac/amd64_edac.c amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); base 3205 drivers/edac/amd64_edac.c u32 base = get_umc_base(i); base 3208 drivers/edac/amd64_edac.c if (amd_smn_read(nid, base + UMCCH_SDP_CTRL, &value)) base 3216 drivers/edac/amd64_edac.c if (amd_smn_read(nid, base + UMCCH_UMC_CAP_HI, &value)) base 143 drivers/edac/amd64_edac.h #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) base 314 drivers/edac/amd64_edac.h struct reg_pair base; base 415 drivers/edac/amd64_edac.h u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; base 420 drivers/edac/amd64_edac.h return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; base 520 drivers/edac/amd64_edac.h return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; base 72 drivers/edac/armada_xp_edac.c void __iomem *base; base 134 drivers/edac/armada_xp_edac.c data_h = readl(drvdata->base + SDRAM_ERR_DATA_H_REG); base 135 drivers/edac/armada_xp_edac.c data_l = readl(drvdata->base + SDRAM_ERR_DATA_L_REG); base 136 drivers/edac/armada_xp_edac.c recv_ecc = readl(drvdata->base + SDRAM_ERR_RECV_ECC_REG); base 137 drivers/edac/armada_xp_edac.c calc_ecc = readl(drvdata->base + SDRAM_ERR_CALC_ECC_REG); base 138 drivers/edac/armada_xp_edac.c addr = readl(drvdata->base + SDRAM_ERR_ADDR_REG); base 139 drivers/edac/armada_xp_edac.c cnt_sbe = readl(drvdata->base + SDRAM_ERR_SBE_COUNT_REG); base 140 drivers/edac/armada_xp_edac.c cnt_dbe = readl(drvdata->base + SDRAM_ERR_DBE_COUNT_REG); base 141 drivers/edac/armada_xp_edac.c cause_err = readl(drvdata->base + SDRAM_ERR_CAUSE_ERR_REG); base 142 drivers/edac/armada_xp_edac.c cause_msg = readl(drvdata->base + SDRAM_ERR_CAUSE_MSG_REG); base 146 drivers/edac/armada_xp_edac.c drvdata->base + SDRAM_ERR_CAUSE_ERR_REG); base 148 drivers/edac/armada_xp_edac.c drvdata->base + SDRAM_ERR_CAUSE_MSG_REG); base 152 drivers/edac/armada_xp_edac.c writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG); base 154 drivers/edac/armada_xp_edac.c writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG); base 226 drivers/edac/armada_xp_edac.c config = readl(drvdata->base + SDRAM_CONFIG_REG); base 234 drivers/edac/armada_xp_edac.c addr_ctrl = readl(drvdata->base + SDRAM_ADDR_CTRL_REG); base 235 drivers/edac/armada_xp_edac.c rank_ctrl = readl(drvdata->base + SDRAM_RANK_CTRL_REG); base 290 drivers/edac/armada_xp_edac.c void __iomem *base; base 299 drivers/edac/armada_xp_edac.c base = devm_ioremap_resource(&pdev->dev, r); base 300 drivers/edac/armada_xp_edac.c if (IS_ERR(base)) { base 302 drivers/edac/armada_xp_edac.c return PTR_ERR(base); base 305 drivers/edac/armada_xp_edac.c config = readl(base + SDRAM_CONFIG_REG); base 320 drivers/edac/armada_xp_edac.c drvdata->base = base; base 342 drivers/edac/armada_xp_edac.c writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG); base 345 drivers/edac/armada_xp_edac.c writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_ERR_REG); base 346 drivers/edac/armada_xp_edac.c writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_MSG_REG); base 349 drivers/edac/armada_xp_edac.c writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG); base 350 drivers/edac/armada_xp_edac.c writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG); base 384 drivers/edac/armada_xp_edac.c void __iomem *base; base 401 drivers/edac/armada_xp_edac.c writel(0, drvdata->base + AURORA_ERR_INJECT_CTL_REG); base 402 drivers/edac/armada_xp_edac.c writel(drvdata->inject_mask, drvdata->base + AURORA_ERR_INJECT_MASK_REG); base 403 drivers/edac/armada_xp_edac.c writel(drvdata->inject_addr | drvdata->inject_ctl, drvdata->base + AURORA_ERR_INJECT_CTL_REG); base 416 drivers/edac/armada_xp_edac.c cnt = readl(drvdata->base + AURORA_ERR_CNT_REG); base 417 drivers/edac/armada_xp_edac.c attr_cap = readl(drvdata->base + AURORA_ERR_ATTR_CAP_REG); base 418 drivers/edac/armada_xp_edac.c addr_cap = readl(drvdata->base + AURORA_ERR_ADDR_CAP_REG); base 419 drivers/edac/armada_xp_edac.c way_cap = readl(drvdata->base + AURORA_ERR_WAY_CAP_REG); base 425 drivers/edac/armada_xp_edac.c writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG); base 474 drivers/edac/armada_xp_edac.c writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG); base 518 drivers/edac/armada_xp_edac.c void __iomem *base; base 527 drivers/edac/armada_xp_edac.c base = devm_ioremap_resource(&pdev->dev, r); base 528 drivers/edac/armada_xp_edac.c if (IS_ERR(base)) { base 530 drivers/edac/armada_xp_edac.c return PTR_ERR(base); base 533 drivers/edac/armada_xp_edac.c l2x0_aux_ctrl = readl(base + L2X0_AUX_CTRL); base 545 drivers/edac/armada_xp_edac.c drvdata->base = base; base 556 drivers/edac/armada_xp_edac.c writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG); base 557 drivers/edac/armada_xp_edac.c writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG); base 19 drivers/edac/highbank_l2_edac.c void __iomem *base; base 30 drivers/edac/highbank_l2_edac.c writel(1, drvdata->base + SR_CLR_SB_ECC_INTR); base 34 drivers/edac/highbank_l2_edac.c writel(1, drvdata->base + SR_CLR_DB_ECC_INTR); base 81 drivers/edac/highbank_l2_edac.c drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); base 82 drivers/edac/highbank_l2_edac.c if (!drvdata->base) { base 153 drivers/edac/highbank_mc_edac.c void __iomem *base; base 194 drivers/edac/highbank_mc_edac.c base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); base 195 drivers/edac/highbank_mc_edac.c if (!base) { base 202 drivers/edac/highbank_mc_edac.c drvdata->mc_err_base = base + settings->err_offset; base 203 drivers/edac/highbank_mc_edac.c drvdata->mc_int_base = base + settings->int_offset; base 69 drivers/edac/i10nm_base.c u64 base; base 85 drivers/edac/i10nm_base.c base = I10NM_GET_SCK_MMIO_BASE(reg); base 87 drivers/edac/i10nm_base.c j++, base, reg); base 109 drivers/edac/i10nm_base.c i, base + off, size, reg); base 111 drivers/edac/i10nm_base.c mbase = ioremap(base + off, size); base 114 drivers/edac/i10nm_base.c base + off); base 75 drivers/edac/pnd2_edac.c u64 base; base 232 drivers/edac/pnd2_edac.c return U64_LSHIFT(hi.base, 32) | U64_LSHIFT(lo.base, 15); base 268 drivers/edac/pnd2_edac.c char *base; base 295 drivers/edac/pnd2_edac.c base = ioremap((resource_size_t)addr, size); base 296 drivers/edac/pnd2_edac.c if (!base) base 300 drivers/edac/pnd2_edac.c *(u32 *)(data + 4) = *(u32 *)(base + off + 4); base 301 drivers/edac/pnd2_edac.c *(u32 *)data = *(u32 *)(base + off); base 303 drivers/edac/pnd2_edac.c iounmap(base); base 339 drivers/edac/pnd2_edac.c static void mk_region(char *name, struct region *rp, u64 base, u64 limit) base 342 drivers/edac/pnd2_edac.c rp->base = base; base 344 drivers/edac/pnd2_edac.c edac_dbg(2, "Region:%s [%llx, %llx]\n", name, base, limit); base 347 drivers/edac/pnd2_edac.c static void mk_region_mask(char *name, struct region *rp, u64 base, u64 mask) base 357 drivers/edac/pnd2_edac.c if (base & ~mask) { base 361 drivers/edac/pnd2_edac.c rp->base = base; base 362 drivers/edac/pnd2_edac.c rp->limit = (base | ~mask) & GENMASK_ULL(PND_MAX_PHYS_BIT, 0); base 364 drivers/edac/pnd2_edac.c edac_dbg(2, "Region:%s [%llx, %llx]\n", name, base, rp->limit); base 372 drivers/edac/pnd2_edac.c return rp->base <= addr && addr <= rp->limit; base 679 drivers/edac/pnd2_edac.c contig_base = remove_mmio_gap(as0.base); base 687 drivers/edac/pnd2_edac.c contig_base = remove_mmio_gap(as1.base); base 701 drivers/edac/pnd2_edac.c contig_base = remove_mmio_gap(as2.base); base 44 drivers/edac/pnd2_edac.h u32 base: 17; base 48 drivers/edac/pnd2_edac.h u32 base : 7; base 244 drivers/edac/ppc4xx_edac.c return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, base 245 drivers/edac/ppc4xx_edac.c dcr_host->base + SDRAM_DCR_DATA_OFFSET, base 261 drivers/edac/ppc4xx_edac.c return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, base 262 drivers/edac/ppc4xx_edac.c dcr_host->base + SDRAM_DCR_DATA_OFFSET, base 356 drivers/edac/skx_base.c u32 base, wayness, chnilvoffset; base 361 drivers/edac/skx_base.c SKX_GET_TADBASE(res->dev, res->imc, i, base); base 363 drivers/edac/skx_base.c if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness)) base 372 drivers/edac/skx_base.c skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)]; base 373 drivers/edac/skx_base.c chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)]; base 345 drivers/edac/synopsys_edac.c enum mem_type (*get_mtype)(const void __iomem *base); base 346 drivers/edac/synopsys_edac.c enum dev_type (*get_dtype)(const void __iomem *base); base 347 drivers/edac/synopsys_edac.c bool (*get_ecc_state)(void __iomem *base); base 361 drivers/edac/synopsys_edac.c void __iomem *base; base 363 drivers/edac/synopsys_edac.c base = priv->baseaddr; base 366 drivers/edac/synopsys_edac.c regval = readl(base + STAT_OFST); base 373 drivers/edac/synopsys_edac.c regval = readl(base + CE_LOG_OFST); base 378 drivers/edac/synopsys_edac.c regval = readl(base + CE_ADDR_OFST); base 382 drivers/edac/synopsys_edac.c p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); base 388 drivers/edac/synopsys_edac.c regval = readl(base + UE_LOG_OFST); base 392 drivers/edac/synopsys_edac.c regval = readl(base + UE_ADDR_OFST); base 396 drivers/edac/synopsys_edac.c p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); base 400 drivers/edac/synopsys_edac.c writel(clearval, base + ECC_CTRL_OFST); base 401 drivers/edac/synopsys_edac.c writel(0x0, base + ECC_CTRL_OFST); base 416 drivers/edac/synopsys_edac.c void __iomem *base; base 418 drivers/edac/synopsys_edac.c base = priv->baseaddr; base 421 drivers/edac/synopsys_edac.c regval = readl(base + ECC_STAT_OFST); base 432 drivers/edac/synopsys_edac.c regval = readl(base + ECC_CEADDR0_OFST); base 434 drivers/edac/synopsys_edac.c regval = readl(base + ECC_CEADDR1_OFST); base 440 drivers/edac/synopsys_edac.c p->ceinfo.data = readl(base + ECC_CSYND0_OFST); base 442 drivers/edac/synopsys_edac.c readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST), base 443 drivers/edac/synopsys_edac.c readl(base + ECC_CSYND2_OFST)); base 448 drivers/edac/synopsys_edac.c regval = readl(base + ECC_UEADDR0_OFST); base 450 drivers/edac/synopsys_edac.c regval = readl(base + ECC_UEADDR1_OFST); base 456 drivers/edac/synopsys_edac.c p->ueinfo.data = readl(base + ECC_UESYND0_OFST); base 460 drivers/edac/synopsys_edac.c writel(clearval, base + ECC_CLR_OFST); base 461 drivers/edac/synopsys_edac.c writel(0x0, base + ECC_CLR_OFST); base 591 drivers/edac/synopsys_edac.c static enum dev_type zynq_get_dtype(const void __iomem *base) base 596 drivers/edac/synopsys_edac.c width = readl(base + CTRL_OFST); base 622 drivers/edac/synopsys_edac.c static enum dev_type zynqmp_get_dtype(const void __iomem *base) base 627 drivers/edac/synopsys_edac.c width = readl(base + CTRL_OFST); base 654 drivers/edac/synopsys_edac.c static bool zynq_get_ecc_state(void __iomem *base) base 659 drivers/edac/synopsys_edac.c dt = zynq_get_dtype(base); base 663 drivers/edac/synopsys_edac.c ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK; base 678 drivers/edac/synopsys_edac.c static bool zynqmp_get_ecc_state(void __iomem *base) base 683 drivers/edac/synopsys_edac.c dt = zynqmp_get_dtype(base); base 687 drivers/edac/synopsys_edac.c ecctype = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK; base 718 drivers/edac/synopsys_edac.c static enum mem_type zynq_get_mtype(const void __iomem *base) base 723 drivers/edac/synopsys_edac.c memtype = readl(base + T_ZQ_OFST); base 742 drivers/edac/synopsys_edac.c static enum mem_type zynqmp_get_mtype(const void __iomem *base) base 747 drivers/edac/synopsys_edac.c memtype = readl(base + CTRL_OFST); base 59 drivers/firewire/nosy.h #define DMA_BREG(base, chan) (base + chan * 0x20) base 60 drivers/firewire/nosy.h #define DMA_SREG(base, chan) (base + chan * 0x10) base 164 drivers/firewire/ohci.c struct fw_iso_context base; base 2728 drivers/firewire/ohci.c ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, base 2730 drivers/firewire/ohci.c ctx->base.callback_data); base 2738 drivers/firewire/ohci.c if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { base 2739 drivers/firewire/ohci.c if (ctx->base.drop_overflow_headers) base 2752 drivers/firewire/ohci.c if (ctx->base.header_size > 0) base 2754 drivers/firewire/ohci.c if (ctx->base.header_size > 4) base 2756 drivers/firewire/ohci.c if (ctx->base.header_size > 8) base 2757 drivers/firewire/ohci.c memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); base 2758 drivers/firewire/ohci.c ctx->header_length += ctx->base.header_size; base 2825 drivers/firewire/ohci.c ctx->base.callback.mc(&ctx->base, base 2827 drivers/firewire/ohci.c ctx->base.callback_data); base 2841 drivers/firewire/ohci.c ctx->base.callback.mc(&ctx->base, base 2843 drivers/firewire/ohci.c ctx->base.callback_data); base 2903 drivers/firewire/ohci.c if (ctx->base.drop_overflow_headers) base 3007 drivers/firewire/ohci.c return &ctx->base; base 3030 drivers/firewire/ohci.c static int ohci_start_iso(struct fw_iso_context *base, base 3033 drivers/firewire/ohci.c struct iso_context *ctx = container_of(base, struct iso_context, base); base 3042 drivers/firewire/ohci.c switch (ctx->base.type) { base 3060 drivers/firewire/ohci.c match = (tags << 28) | (sync << 8) | ctx->base.channel; base 3080 drivers/firewire/ohci.c static int ohci_stop_iso(struct fw_iso_context *base) base 3082 drivers/firewire/ohci.c struct fw_ohci *ohci = fw_ohci(base->card); base 3083 drivers/firewire/ohci.c struct iso_context *ctx = container_of(base, struct iso_context, base); base 3086 drivers/firewire/ohci.c switch (ctx->base.type) { base 3105 drivers/firewire/ohci.c static void ohci_free_iso_context(struct fw_iso_context *base) base 3107 drivers/firewire/ohci.c struct fw_ohci *ohci = fw_ohci(base->card); base 3108 drivers/firewire/ohci.c struct iso_context *ctx = container_of(base, struct iso_context, base); base 3112 drivers/firewire/ohci.c ohci_stop_iso(base); base 3118 drivers/firewire/ohci.c switch (base->type) { base 3127 drivers/firewire/ohci.c ohci->ir_context_channels |= 1ULL << base->channel; base 3142 drivers/firewire/ohci.c static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) base 3144 drivers/firewire/ohci.c struct fw_ohci *ohci = fw_ohci(base->card); base 3148 drivers/firewire/ohci.c switch (base->type) { base 3181 drivers/firewire/ohci.c ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); base 3187 drivers/firewire/ohci.c ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); base 3247 drivers/firewire/ohci.c IT_HEADER_CHANNEL(ctx->base.channel) | base 3248 drivers/firewire/ohci.c IT_HEADER_SPEED(ctx->base.speed)); base 3312 drivers/firewire/ohci.c packet_count = packet->header_length / ctx->base.header_size; base 3313 drivers/firewire/ohci.c header_size = max(ctx->base.header_size, (size_t)8); base 3433 drivers/firewire/ohci.c static int ohci_queue_iso(struct fw_iso_context *base, base 3438 drivers/firewire/ohci.c struct iso_context *ctx = container_of(base, struct iso_context, base); base 3443 drivers/firewire/ohci.c switch (base->type) { base 3459 drivers/firewire/ohci.c static void ohci_flush_queue_iso(struct fw_iso_context *base) base 3462 drivers/firewire/ohci.c &container_of(base, struct iso_context, base)->context; base 3467 drivers/firewire/ohci.c static int ohci_flush_iso_completions(struct fw_iso_context *base) base 3469 drivers/firewire/ohci.c struct iso_context *ctx = container_of(base, struct iso_context, base); base 3477 drivers/firewire/ohci.c switch (base->type) { base 276 drivers/firewire/sbp2.c struct sbp2_orb base; base 305 drivers/firewire/sbp2.c struct sbp2_orb base; base 540 drivers/firewire/sbp2.c container_of(base_orb, struct sbp2_management_orb, base); base 563 drivers/firewire/sbp2.c kref_init(&orb->base.kref); base 596 drivers/firewire/sbp2.c orb->base.callback = complete_management_orb; base 598 drivers/firewire/sbp2.c orb->base.request_bus = base 601 drivers/firewire/sbp2.c if (dma_mapping_error(device->card->device, orb->base.request_bus)) base 604 drivers/firewire/sbp2.c sbp2_send_orb(&orb->base, lu, node_id, generation, base 612 drivers/firewire/sbp2.c orb->base.rcode); base 616 drivers/firewire/sbp2.c if (orb->base.rcode != RCODE_COMPLETE) { base 618 drivers/firewire/sbp2.c orb->base.rcode); base 632 drivers/firewire/sbp2.c dma_unmap_single(device->card->device, orb->base.request_bus, base 640 drivers/firewire/sbp2.c kref_put(&orb->base.kref, free_orb); base 1338 drivers/firewire/sbp2.c container_of(base_orb, struct sbp2_command_orb, base); base 1373 drivers/firewire/sbp2.c dma_unmap_single(device->card->device, orb->base.request_bus, base 1454 drivers/firewire/sbp2.c orb->base.rcode = -1; base 1455 drivers/firewire/sbp2.c kref_init(&orb->base.kref); base 1474 drivers/firewire/sbp2.c orb->base.callback = complete_command_orb; base 1475 drivers/firewire/sbp2.c orb->base.request_bus = base 1478 drivers/firewire/sbp2.c if (dma_mapping_error(device->card->device, orb->base.request_bus)) { base 1483 drivers/firewire/sbp2.c sbp2_send_orb(&orb->base, lu, lu->tgt->node_id, generation, base 1487 drivers/firewire/sbp2.c kref_put(&orb->base.kref, free_orb); base 118 drivers/firmware/broadcom/bcm47xx_nvram.c int bcm47xx_nvram_init_from_mem(u32 base, u32 lim) base 123 drivers/firmware/broadcom/bcm47xx_nvram.c iobase = ioremap_nocache(base, lim); base 613 drivers/firmware/efi/efi.c memblock_reserve(rsv->entry[i].base, base 1011 drivers/firmware/efi/efi.c rsv->entry[index].base = addr; base 1039 drivers/firmware/efi/efi.c rsv->entry[0].base = addr; base 57 drivers/firmware/efi/rci2-table.c u16 *base = (u16 *)rci2_base; base 66 drivers/firmware/efi/rci2-table.c chksum += *base; base 68 drivers/firmware/efi/rci2-table.c base++; base 72 drivers/firmware/efi/rci2-table.c buf[0] = *(u8 *)base; base 802 drivers/firmware/qemu_fw_cfg.c phys_addr_t base; base 821 drivers/firmware/qemu_fw_cfg.c &base, &consumed, base 835 drivers/firmware/qemu_fw_cfg.c res[0].start = base; base 836 drivers/firmware/qemu_fw_cfg.c res[0].end = base + size - 1; base 32 drivers/fpga/dfl-afu-error.c void __iomem *base; base 34 drivers/fpga/dfl-afu-error.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR); base 36 drivers/fpga/dfl-afu-error.c writeq(mask ? ERROR_MASK : 0, base + PORT_ERROR_MASK); base 116 drivers/fpga/dfl-afu-error.c void __iomem *base; base 119 drivers/fpga/dfl-afu-error.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR); base 122 drivers/fpga/dfl-afu-error.c error = readq(base + PORT_ERROR); base 147 drivers/fpga/dfl-afu-error.c void __iomem *base; base 150 drivers/fpga/dfl-afu-error.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR); base 153 drivers/fpga/dfl-afu-error.c error = readq(base + PORT_FIRST_ERROR); base 165 drivers/fpga/dfl-afu-error.c void __iomem *base; base 168 drivers/fpga/dfl-afu-error.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR); base 171 drivers/fpga/dfl-afu-error.c req0 = readq(base + PORT_MALFORMED_REQ0); base 172 drivers/fpga/dfl-afu-error.c req1 = readq(base + PORT_MALFORMED_REQ1); base 38 drivers/fpga/dfl-afu-main.c void __iomem *base; base 46 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER); base 49 drivers/fpga/dfl-afu-main.c v = readq(base + PORT_HDR_CTRL); base 51 drivers/fpga/dfl-afu-main.c writeq(v, base + PORT_HDR_CTRL); base 68 drivers/fpga/dfl-afu-main.c void __iomem *base; base 74 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER); base 77 drivers/fpga/dfl-afu-main.c v = readq(base + PORT_HDR_CTRL); base 79 drivers/fpga/dfl-afu-main.c writeq(v, base + PORT_HDR_CTRL); base 86 drivers/fpga/dfl-afu-main.c if (readq_poll_timeout(base + PORT_HDR_CTRL, v, v & PORT_CTRL_SFTRST, base 132 drivers/fpga/dfl-afu-main.c void __iomem *base; base 134 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER); base 136 drivers/fpga/dfl-afu-main.c return FIELD_GET(PORT_CAP_PORT_NUM, readq(base + PORT_HDR_CAP)); base 152 drivers/fpga/dfl-afu-main.c void __iomem *base; base 155 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 158 drivers/fpga/dfl-afu-main.c v = readq(base + PORT_HDR_CTRL); base 169 drivers/fpga/dfl-afu-main.c void __iomem *base; base 176 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 179 drivers/fpga/dfl-afu-main.c v = readq(base + PORT_HDR_CTRL); base 182 drivers/fpga/dfl-afu-main.c writeq(v, base + PORT_HDR_CTRL); base 193 drivers/fpga/dfl-afu-main.c void __iomem *base; base 196 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 199 drivers/fpga/dfl-afu-main.c v = readq(base + PORT_HDR_STS); base 210 drivers/fpga/dfl-afu-main.c void __iomem *base; base 216 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 219 drivers/fpga/dfl-afu-main.c writeq(PORT_STS_AP1_EVT, base + PORT_HDR_STS); base 231 drivers/fpga/dfl-afu-main.c void __iomem *base; base 234 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 237 drivers/fpga/dfl-afu-main.c v = readq(base + PORT_HDR_STS); base 248 drivers/fpga/dfl-afu-main.c void __iomem *base; base 254 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 257 drivers/fpga/dfl-afu-main.c writeq(PORT_STS_AP2_EVT, base + PORT_HDR_STS); base 268 drivers/fpga/dfl-afu-main.c void __iomem *base; base 271 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 274 drivers/fpga/dfl-afu-main.c v = readq(base + PORT_HDR_STS); base 287 drivers/fpga/dfl-afu-main.c void __iomem *base; base 292 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 295 drivers/fpga/dfl-afu-main.c writeq(userclk_freq_cmd, base + PORT_HDR_USRCLK_CMD0); base 308 drivers/fpga/dfl-afu-main.c void __iomem *base; base 313 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 316 drivers/fpga/dfl-afu-main.c writeq(userclk_freqcntr_cmd, base + PORT_HDR_USRCLK_CMD1); base 329 drivers/fpga/dfl-afu-main.c void __iomem *base; base 331 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 334 drivers/fpga/dfl-afu-main.c userclk_freqsts = readq(base + PORT_HDR_USRCLK_STS0); base 347 drivers/fpga/dfl-afu-main.c void __iomem *base; base 349 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 352 drivers/fpga/dfl-afu-main.c userclk_freqcntrsts = readq(base + PORT_HDR_USRCLK_STS1); base 378 drivers/fpga/dfl-afu-main.c void __iomem *base; base 380 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); base 382 drivers/fpga/dfl-afu-main.c if (dfl_feature_revision(base) > 0) { base 446 drivers/fpga/dfl-afu-main.c void __iomem *base; base 449 drivers/fpga/dfl-afu-main.c base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_AFU); base 457 drivers/fpga/dfl-afu-main.c guidl = readq(base + GUID_L); base 458 drivers/fpga/dfl-afu-main.c guidh = readq(base + GUID_H); base 45 drivers/fpga/dfl-fme-error.c void __iomem *base; base 48 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 51 drivers/fpga/dfl-fme-error.c value = readq(base + PCIE0_ERROR); base 62 drivers/fpga/dfl-fme-error.c void __iomem *base; base 69 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 72 drivers/fpga/dfl-fme-error.c writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK); base 74 drivers/fpga/dfl-fme-error.c v = readq(base + PCIE0_ERROR); base 76 drivers/fpga/dfl-fme-error.c writeq(v, base + PCIE0_ERROR); base 80 drivers/fpga/dfl-fme-error.c writeq(0ULL, base + PCIE0_ERROR_MASK); base 90 drivers/fpga/dfl-fme-error.c void __iomem *base; base 93 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 96 drivers/fpga/dfl-fme-error.c value = readq(base + PCIE1_ERROR); base 107 drivers/fpga/dfl-fme-error.c void __iomem *base; base 114 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 117 drivers/fpga/dfl-fme-error.c writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK); base 119 drivers/fpga/dfl-fme-error.c v = readq(base + PCIE1_ERROR); base 121 drivers/fpga/dfl-fme-error.c writeq(v, base + PCIE1_ERROR); base 125 drivers/fpga/dfl-fme-error.c writeq(0ULL, base + PCIE1_ERROR_MASK); base 134 drivers/fpga/dfl-fme-error.c void __iomem *base; base 136 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 139 drivers/fpga/dfl-fme-error.c (unsigned long long)readq(base + RAS_NONFAT_ERROR)); base 146 drivers/fpga/dfl-fme-error.c void __iomem *base; base 148 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 151 drivers/fpga/dfl-fme-error.c (unsigned long long)readq(base + RAS_CATFAT_ERROR)); base 159 drivers/fpga/dfl-fme-error.c void __iomem *base; base 162 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 165 drivers/fpga/dfl-fme-error.c v = readq(base + RAS_ERROR_INJECT); base 177 drivers/fpga/dfl-fme-error.c void __iomem *base; base 187 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 190 drivers/fpga/dfl-fme-error.c v = readq(base + RAS_ERROR_INJECT); base 193 drivers/fpga/dfl-fme-error.c writeq(v, base + RAS_ERROR_INJECT); base 204 drivers/fpga/dfl-fme-error.c void __iomem *base; base 207 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 210 drivers/fpga/dfl-fme-error.c value = readq(base + FME_ERROR); base 221 drivers/fpga/dfl-fme-error.c void __iomem *base; base 228 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 231 drivers/fpga/dfl-fme-error.c writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK); base 233 drivers/fpga/dfl-fme-error.c v = readq(base + FME_ERROR); base 235 drivers/fpga/dfl-fme-error.c writeq(v, base + FME_ERROR); base 240 drivers/fpga/dfl-fme-error.c writeq(dfl_feature_revision(base) ? 0ULL : MBP_ERROR, base 241 drivers/fpga/dfl-fme-error.c base + FME_ERROR_MASK); base 251 drivers/fpga/dfl-fme-error.c void __iomem *base; base 254 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 257 drivers/fpga/dfl-fme-error.c value = readq(base + FME_FIRST_ERROR); base 268 drivers/fpga/dfl-fme-error.c void __iomem *base; base 271 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 274 drivers/fpga/dfl-fme-error.c value = readq(base + FME_NEXT_ERROR); base 317 drivers/fpga/dfl-fme-error.c void __iomem *base; base 319 drivers/fpga/dfl-fme-error.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR); base 324 drivers/fpga/dfl-fme-error.c if (dfl_feature_revision(base)) base 325 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : 0, base + FME_ERROR_MASK); base 327 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : MBP_ERROR, base + FME_ERROR_MASK); base 329 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : 0, base + PCIE0_ERROR_MASK); base 330 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : 0, base + PCIE1_ERROR_MASK); base 331 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : 0, base + RAS_NONFAT_ERROR_MASK); base 332 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : 0, base + RAS_CATFAT_ERROR_MASK); base 28 drivers/fpga/dfl-fme-main.c void __iomem *base; base 31 drivers/fpga/dfl-fme-main.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); base 33 drivers/fpga/dfl-fme-main.c v = readq(base + FME_HDR_CAP); base 47 drivers/fpga/dfl-fme-main.c void __iomem *base; base 50 drivers/fpga/dfl-fme-main.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); base 52 drivers/fpga/dfl-fme-main.c v = readq(base + FME_HDR_BITSTREAM_ID); base 65 drivers/fpga/dfl-fme-main.c void __iomem *base; base 68 drivers/fpga/dfl-fme-main.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); base 70 drivers/fpga/dfl-fme-main.c v = readq(base + FME_HDR_BITSTREAM_MD); base 79 drivers/fpga/dfl-fme-main.c void __iomem *base; base 82 drivers/fpga/dfl-fme-main.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); base 84 drivers/fpga/dfl-fme-main.c v = readq(base + FME_HDR_CAP); base 94 drivers/fpga/dfl-fme-main.c void __iomem *base; base 97 drivers/fpga/dfl-fme-main.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); base 99 drivers/fpga/dfl-fme-main.c v = readq(base + FME_HDR_CAP); base 109 drivers/fpga/dfl-fme-main.c void __iomem *base; base 112 drivers/fpga/dfl-fme-main.c base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER); base 114 drivers/fpga/dfl-fme-main.c v = readq(base + FME_HDR_CAP); base 91 drivers/fpga/dfl-pci.c void __iomem *base; base 101 drivers/fpga/dfl-pci.c base = cci_pci_ioremap_bar(pcidev, 0); base 102 drivers/fpga/dfl-pci.c if (!base) { base 112 drivers/fpga/dfl-pci.c if (dfl_feature_is_fme(base)) { base 116 drivers/fpga/dfl-pci.c dfl_fpga_enum_info_add_dfl(info, start, len, base); base 122 drivers/fpga/dfl-pci.c v = readq(base + FME_HDR_CAP); base 128 drivers/fpga/dfl-pci.c v = readq(base + FME_HDR_PORT_OFST(i)); base 140 drivers/fpga/dfl-pci.c base = cci_pci_ioremap_bar(pcidev, bar); base 141 drivers/fpga/dfl-pci.c if (!base) base 148 drivers/fpga/dfl-pci.c base + offset); base 150 drivers/fpga/dfl-pci.c } else if (dfl_feature_is_port(base)) { base 154 drivers/fpga/dfl-pci.c dfl_fpga_enum_info_add_dfl(info, start, len, base); base 1154 drivers/fpga/dfl.c void __iomem *base; base 1157 drivers/fpga/dfl.c base = dfl_get_feature_ioaddr_by_id(fme_dev, FME_FEATURE_ID_HEADER); base 1159 drivers/fpga/dfl.c v = readq(base + FME_HDR_PORT_OFST(port_id)); base 1165 drivers/fpga/dfl.c writeq(v, base + FME_HDR_PORT_OFST(port_id)); base 346 drivers/fpga/dfl.h static inline bool dfl_feature_is_fme(void __iomem *base) base 348 drivers/fpga/dfl.h u64 v = readq(base + DFH); base 354 drivers/fpga/dfl.h static inline bool dfl_feature_is_port(void __iomem *base) base 356 drivers/fpga/dfl.h u64 v = readq(base + DFH); base 362 drivers/fpga/dfl.h static inline u8 dfl_feature_revision(void __iomem *base) base 364 drivers/fpga/dfl.h return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH)); base 759 drivers/fsi/fsi-master-ast-cf.c void __iomem *base) base 761 drivers/fsi/fsi-master-ast-cf.c iowrite16be(master->gpio_clk_vreg, base + HDR_CLOCK_GPIO_VADDR); base 762 drivers/fsi/fsi-master-ast-cf.c iowrite16be(master->gpio_clk_dreg, base + HDR_CLOCK_GPIO_DADDR); base 763 drivers/fsi/fsi-master-ast-cf.c iowrite16be(master->gpio_dat_vreg, base + HDR_DATA_GPIO_VADDR); base 764 drivers/fsi/fsi-master-ast-cf.c iowrite16be(master->gpio_dat_dreg, base + HDR_DATA_GPIO_DADDR); base 765 drivers/fsi/fsi-master-ast-cf.c iowrite16be(master->gpio_tra_vreg, base + HDR_TRANS_GPIO_VADDR); base 766 drivers/fsi/fsi-master-ast-cf.c iowrite16be(master->gpio_tra_dreg, base + HDR_TRANS_GPIO_DADDR); base 767 drivers/fsi/fsi-master-ast-cf.c iowrite8(master->gpio_clk_bit, base + HDR_CLOCK_GPIO_BIT); base 768 drivers/fsi/fsi-master-ast-cf.c iowrite8(master->gpio_dat_bit, base + HDR_DATA_GPIO_BIT); base 769 drivers/fsi/fsi-master-ast-cf.c iowrite8(master->gpio_tra_bit, base + HDR_TRANS_GPIO_BIT); base 774 drivers/fsi/fsi-master-ast-cf.c void __iomem *base = master->cf_mem + HDR_OFFSET; base 776 drivers/fsi/fsi-master-ast-cf.c setup_common_fw_config(master, base); base 777 drivers/fsi/fsi-master-ast-cf.c iowrite32be(FW_CONTROL_USE_STOP, base + HDR_FW_CONTROL); base 782 drivers/fsi/fsi-master-ast-cf.c void __iomem *base = master->cf_mem + HDR_OFFSET; base 784 drivers/fsi/fsi-master-ast-cf.c setup_common_fw_config(master, base); base 785 drivers/fsi/fsi-master-ast-cf.c iowrite32be(FW_CONTROL_CONT_CLOCK|FW_CONTROL_DUMMY_RD, base + HDR_FW_CONTROL); base 27 drivers/gpio/gpio-104-dio-48e.c static unsigned int base[MAX_NUM_DIO48E]; base 29 drivers/gpio/gpio-104-dio-48e.c module_param_hw_array(base, uint, ioport, &num_dio48e, 0); base 30 drivers/gpio/gpio-104-dio-48e.c MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses"); base 52 drivers/gpio/gpio-104-dio-48e.c unsigned base; base 70 drivers/gpio/gpio-104-dio-48e.c const unsigned control_addr = dio48egpio->base + 3 + control_port*4; base 111 drivers/gpio/gpio-104-dio-48e.c const unsigned control_addr = dio48egpio->base + 3 + control_port*4; base 144 drivers/gpio/gpio-104-dio-48e.c outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port); base 171 drivers/gpio/gpio-104-dio-48e.c port_state = inb(dio48egpio->base + in_port); base 214 drivers/gpio/gpio-104-dio-48e.c port_state = inb(dio48egpio->base + ports[i]); base 238 drivers/gpio/gpio-104-dio-48e.c outb(dio48egpio->out_state[port], dio48egpio->base + out_port); base 271 drivers/gpio/gpio-104-dio-48e.c outb(dio48egpio->out_state[port], dio48egpio->base + out_port); base 305 drivers/gpio/gpio-104-dio-48e.c inb(dio48egpio->base + 0xB); base 325 drivers/gpio/gpio-104-dio-48e.c outb(0x00, dio48egpio->base + 0xF); base 326 drivers/gpio/gpio-104-dio-48e.c outb(0x00, dio48egpio->base + 0xB); base 372 drivers/gpio/gpio-104-dio-48e.c outb(0x00, dio48egpio->base + 0xF); base 409 drivers/gpio/gpio-104-dio-48e.c if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) { base 411 drivers/gpio/gpio-104-dio-48e.c base[id], base[id] + DIO48E_EXTENT); base 418 drivers/gpio/gpio-104-dio-48e.c dio48egpio->chip.base = -1; base 428 drivers/gpio/gpio-104-dio-48e.c dio48egpio->base = base[id]; base 439 drivers/gpio/gpio-104-dio-48e.c outb(0x80, base[id] + 3); base 440 drivers/gpio/gpio-104-dio-48e.c outb(0x00, base[id]); base 441 drivers/gpio/gpio-104-dio-48e.c outb(0x00, base[id] + 1); base 442 drivers/gpio/gpio-104-dio-48e.c outb(0x00, base[id] + 2); base 443 drivers/gpio/gpio-104-dio-48e.c outb(0x00, base[id] + 3); base 444 drivers/gpio/gpio-104-dio-48e.c outb(0x80, base[id] + 7); base 445 drivers/gpio/gpio-104-dio-48e.c outb(0x00, base[id] + 4); base 446 drivers/gpio/gpio-104-dio-48e.c outb(0x00, base[id] + 5); base 447 drivers/gpio/gpio-104-dio-48e.c outb(0x00, base[id] + 6); base 448 drivers/gpio/gpio-104-dio-48e.c outb(0x00, base[id] + 7); base 451 drivers/gpio/gpio-104-dio-48e.c inb(base[id] + 0xB); base 27 drivers/gpio/gpio-104-idi-48.c static unsigned int base[MAX_NUM_IDI_48]; base 29 drivers/gpio/gpio-104-idi-48.c module_param_hw_array(base, uint, ioport, &num_idi_48, 0); base 30 drivers/gpio/gpio-104-idi-48.c MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses"); base 50 drivers/gpio/gpio-104-idi-48.c unsigned base; base 77 drivers/gpio/gpio-104-idi-48.c return !!(inb(idi48gpio->base + base_offset) & mask); base 120 drivers/gpio/gpio-104-idi-48.c port_state = inb(idi48gpio->base + ports[i]); base 155 drivers/gpio/gpio-104-idi-48.c outb(idi48gpio->cos_enb, idi48gpio->base + 7); base 189 drivers/gpio/gpio-104-idi-48.c outb(idi48gpio->cos_enb, idi48gpio->base + 7); base 231 drivers/gpio/gpio-104-idi-48.c cos_status = inb(idi48gpio->base + 7); base 282 drivers/gpio/gpio-104-idi-48.c if (!devm_request_region(dev, base[id], IDI_48_EXTENT, name)) { base 284 drivers/gpio/gpio-104-idi-48.c base[id], base[id] + IDI_48_EXTENT); base 291 drivers/gpio/gpio-104-idi-48.c idi48gpio->chip.base = -1; base 298 drivers/gpio/gpio-104-idi-48.c idi48gpio->base = base[id]; base 310 drivers/gpio/gpio-104-idi-48.c outb(0, base[id] + 7); base 311 drivers/gpio/gpio-104-idi-48.c inb(base[id] + 7); base 26 drivers/gpio/gpio-104-idio-16.c static unsigned int base[MAX_NUM_IDIO_16]; base 28 drivers/gpio/gpio-104-idio-16.c module_param_hw_array(base, uint, ioport, &num_idio_16, 0); base 29 drivers/gpio/gpio-104-idio-16.c MODULE_PARM_DESC(base, "ACCES 104-IDIO-16 base addresses"); base 47 drivers/gpio/gpio-104-idio-16.c unsigned base; base 80 drivers/gpio/gpio-104-idio-16.c return !!(inb(idio16gpio->base + 1) & mask); base 82 drivers/gpio/gpio-104-idio-16.c return !!(inb(idio16gpio->base + 5) & (mask>>8)); base 92 drivers/gpio/gpio-104-idio-16.c *bits |= (unsigned long)inb(idio16gpio->base + 1) << 16; base 94 drivers/gpio/gpio-104-idio-16.c *bits |= (unsigned long)inb(idio16gpio->base + 5) << 24; base 116 drivers/gpio/gpio-104-idio-16.c outb(idio16gpio->out_state >> 8, idio16gpio->base + 4); base 118 drivers/gpio/gpio-104-idio-16.c outb(idio16gpio->out_state, idio16gpio->base); base 135 drivers/gpio/gpio-104-idio-16.c outb(idio16gpio->out_state, idio16gpio->base); base 137 drivers/gpio/gpio-104-idio-16.c outb(idio16gpio->out_state >> 8, idio16gpio->base + 4); base 158 drivers/gpio/gpio-104-idio-16.c outb(0, idio16gpio->base + 2); base 177 drivers/gpio/gpio-104-idio-16.c inb(idio16gpio->base + 2); base 212 drivers/gpio/gpio-104-idio-16.c outb(0, idio16gpio->base + 1); base 237 drivers/gpio/gpio-104-idio-16.c if (!devm_request_region(dev, base[id], IDIO_16_EXTENT, name)) { base 239 drivers/gpio/gpio-104-idio-16.c base[id], base[id] + IDIO_16_EXTENT); base 246 drivers/gpio/gpio-104-idio-16.c idio16gpio->chip.base = -1; base 256 drivers/gpio/gpio-104-idio-16.c idio16gpio->base = base[id]; base 268 drivers/gpio/gpio-104-idio-16.c outb(0, base[id] + 2); base 269 drivers/gpio/gpio-104-idio-16.c outb(0, base[id] + 1); base 140 drivers/gpio/gpio-74x164.c chip->gpio_chip.base = -1; base 257 drivers/gpio/gpio-adnp.c chip->base = -1; base 279 drivers/gpio/gpio-adnp.c unsigned int base = i << adnp->reg_shift, bit; base 323 drivers/gpio/gpio-adnp.c base + bit); base 128 drivers/gpio/gpio-adp5520.c gc->base = pdata->gpio_start; base 354 drivers/gpio/gpio-adp5588.c gc->base = -1; base 358 drivers/gpio/gpio-adp5588.c gc->base = pdata->gpio_start; base 401 drivers/gpio/gpio-adp5588.c ret = pdata->setup(client, gc->base, gc->ngpio, pdata->context); base 420 drivers/gpio/gpio-adp5588.c dev->gpio_chip.base, dev->gpio_chip.ngpio, base 75 drivers/gpio/gpio-altera-a10sr.c .base = -1, base 36 drivers/gpio/gpio-amd-fch.c void __iomem *base; base 44 drivers/gpio/gpio-amd-fch.c return priv->base + priv->pdata->gpio_reg[gpio]*sizeof(u32); base 161 drivers/gpio/gpio-amd-fch.c priv->gc.base = -1; base 171 drivers/gpio/gpio-amd-fch.c priv->base = devm_ioremap_resource(&pdev->dev, &amd_fch_gpio_iores); base 172 drivers/gpio/gpio-amd-fch.c if (IS_ERR(priv->base)) base 173 drivers/gpio/gpio-amd-fch.c return PTR_ERR(priv->base); base 165 drivers/gpio/gpio-amd8111.c .base = -1, base 181 drivers/gpio/gpio-arizona.c arizona_gpio->gpio_chip.base = pdata->gpio_base; base 183 drivers/gpio/gpio-arizona.c arizona_gpio->gpio_chip.base = -1; base 57 drivers/gpio/gpio-aspeed.c void __iomem *base; base 214 drivers/gpio/gpio-aspeed.c return gpio->base + bank->val_regs + GPIO_VAL_VALUE; base 216 drivers/gpio/gpio-aspeed.c return gpio->base + bank->rdata_reg; base 218 drivers/gpio/gpio-aspeed.c return gpio->base + bank->val_regs + GPIO_VAL_DIR; base 220 drivers/gpio/gpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; base 222 drivers/gpio/gpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; base 224 drivers/gpio/gpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; base 226 drivers/gpio/gpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; base 228 drivers/gpio/gpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; base 230 drivers/gpio/gpio-aspeed.c return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; base 232 drivers/gpio/gpio-aspeed.c return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; base 234 drivers/gpio/gpio-aspeed.c return gpio->base + bank->tolerance_regs; base 236 drivers/gpio/gpio-aspeed.c return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; base 238 drivers/gpio/gpio-aspeed.c return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; base 747 drivers/gpio/gpio-aspeed.c return pinctrl_gpio_request(chip->base + offset); base 752 drivers/gpio/gpio-aspeed.c pinctrl_gpio_free(chip->base + offset); base 875 drivers/gpio/gpio-aspeed.c cycles = ioread32(gpio->base + debounce_timers[i]); base 911 drivers/gpio/gpio-aspeed.c iowrite32(requested_cycles, gpio->base + debounce_timers[i]); base 1150 drivers/gpio/gpio-aspeed.c gpio->base = devm_platform_ioremap_resource(pdev, 0); base 1151 drivers/gpio/gpio-aspeed.c if (IS_ERR(gpio->base)) base 1152 drivers/gpio/gpio-aspeed.c return PTR_ERR(gpio->base); base 1183 drivers/gpio/gpio-aspeed.c gpio->chip.base = -1; base 31 drivers/gpio/gpio-ath79.c void __iomem *base; base 45 drivers/gpio/gpio-ath79.c return readl(ctrl->base + reg); base 51 drivers/gpio/gpio-ath79.c writel(val, ctrl->base + reg); base 262 drivers/gpio/gpio-ath79.c ctrl->base = devm_ioremap_nocache(dev, res->start, resource_size(res)); base 263 drivers/gpio/gpio-ath79.c if (!ctrl->base) base 268 drivers/gpio/gpio-ath79.c ctrl->base + AR71XX_GPIO_REG_IN, base 269 drivers/gpio/gpio-ath79.c ctrl->base + AR71XX_GPIO_REG_SET, base 270 drivers/gpio/gpio-ath79.c ctrl->base + AR71XX_GPIO_REG_CLEAR, base 271 drivers/gpio/gpio-ath79.c oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, base 272 drivers/gpio/gpio-ath79.c oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, base 279 drivers/gpio/gpio-ath79.c ctrl->gc.base = 0; base 335 drivers/gpio/gpio-bcm-kona.c .base = 0, base 207 drivers/gpio/gpio-bd70528.c bdgpio->gpio.base = -1; base 98 drivers/gpio/gpio-bd9571mwv.c .base = -1, base 105 drivers/gpio/gpio-brcmstb.c return hwirq - (bank->gc.base - bank->parent_priv->gpio_base); base 131 drivers/gpio/gpio-brcmstb.c int hwirq = offset + (gc->base - priv->gpio_base); base 276 drivers/gpio/gpio-brcmstb.c int hwbase = bank->gc.base - priv->gpio_base; base 433 drivers/gpio/gpio-brcmstb.c offset = gpiospec->args[0] - (gc->base - priv->gpio_base); base 714 drivers/gpio/gpio-brcmstb.c gc->base = gpio_base; base 738 drivers/gpio/gpio-brcmstb.c gc->base, gc->ngpio, bank->width); base 158 drivers/gpio/gpio-bt8xx.c c->base = modparam_gpiobase; base 197 drivers/gpio/gpio-cadence.c cgpio->gc.base = -1; base 63 drivers/gpio/gpio-clps711x.c gc->base = -1; base 167 drivers/gpio/gpio-creg-snps.c hcg->gc.base = -1; base 349 drivers/gpio/gpio-crystalcove.c cg->chip.base = -1; base 48 drivers/gpio/gpio-cs5535.c resource_size_t base; base 63 drivers/gpio/gpio-cs5535.c unsigned long addr = chip->base + 0x80 + reg; base 88 drivers/gpio/gpio-cs5535.c outl(1 << offset, chip->base + reg); base 110 drivers/gpio/gpio-cs5535.c outl(1 << (offset + 16), chip->base + reg); base 136 drivers/gpio/gpio-cs5535.c val = inl(chip->base + reg); base 139 drivers/gpio/gpio-cs5535.c val = inl(chip->base + 0x80 + reg); base 182 drivers/gpio/gpio-cs5535.c val = inl(chip->base + offset); base 194 drivers/gpio/gpio-cs5535.c outl(val, chip->base + offset); base 291 drivers/gpio/gpio-cs5535.c .base = 0, base 330 drivers/gpio/gpio-cs5535.c cs5535_gpio_chip.base = res->start; base 192 drivers/gpio/gpio-da9052.c .base = -1, base 210 drivers/gpio/gpio-da9052.c gpio->gp.base = pdata->gpio_base; base 129 drivers/gpio/gpio-da9055.c .base = -1, base 147 drivers/gpio/gpio-da9055.c gpio->gp.base = pdata->gpio_base; base 256 drivers/gpio/gpio-davinci.c chips->chip.base = pdata->no_auto_base ? pdata->base : -1; base 467 drivers/gpio/gpio-dln2.c dln2->gpio.base = -1; base 526 drivers/gpio/gpio-dwapb.c port->gc.base = pp->gpio_base; base 95 drivers/gpio/gpio-eic-sprd.c void __iomem *base[SPRD_EIC_MAX_BANK]; base 137 drivers/gpio/gpio-eic-sprd.c return sprd_eic->base[bank]; base 144 drivers/gpio/gpio-eic-sprd.c void __iomem *base = base 150 drivers/gpio/gpio-eic-sprd.c tmp = readl_relaxed(base + reg); base 157 drivers/gpio/gpio-eic-sprd.c writel_relaxed(tmp, base + reg); base 164 drivers/gpio/gpio-eic-sprd.c void __iomem *base = base 167 drivers/gpio/gpio-eic-sprd.c return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); base 212 drivers/gpio/gpio-eic-sprd.c void __iomem *base = base 215 drivers/gpio/gpio-eic-sprd.c u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK; base 218 drivers/gpio/gpio-eic-sprd.c writel_relaxed(value, base + reg); base 507 drivers/gpio/gpio-eic-sprd.c void __iomem *base = sprd_eic_offset_base(sprd_eic, bank); base 512 drivers/gpio/gpio-eic-sprd.c reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) & base 516 drivers/gpio/gpio-eic-sprd.c reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) & base 520 drivers/gpio/gpio-eic-sprd.c reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) & base 524 drivers/gpio/gpio-eic-sprd.c reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) & base 598 drivers/gpio/gpio-eic-sprd.c sprd_eic->base[i] = devm_platform_ioremap_resource(pdev, i); base 599 drivers/gpio/gpio-eic-sprd.c if (IS_ERR(sprd_eic->base[i])) base 605 drivers/gpio/gpio-eic-sprd.c sprd_eic->chip.base = -1; base 232 drivers/gpio/gpio-em.c return pinctrl_gpio_request(chip->base + offset); base 237 drivers/gpio/gpio-em.c pinctrl_gpio_free(chip->base + offset); base 325 drivers/gpio/gpio-em.c gpio_chip->base = -1; base 38 drivers/gpio/gpio-ep93xx.c void __iomem *base; base 62 drivers/gpio/gpio-ep93xx.c writeb_relaxed(0, epg->base + int_en_register_offset[port]); base 65 drivers/gpio/gpio-ep93xx.c epg->base + int_type2_register_offset[port]); base 68 drivers/gpio/gpio-ep93xx.c epg->base + int_type1_register_offset[port]); base 71 drivers/gpio/gpio-ep93xx.c epg->base + int_en_register_offset[port]); base 104 drivers/gpio/gpio-ep93xx.c epg->base + int_debounce_register_offset[port]); base 123 drivers/gpio/gpio-ep93xx.c stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); base 128 drivers/gpio/gpio-ep93xx.c stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); base 165 drivers/gpio/gpio-ep93xx.c writeb(port_mask, epg->base + eoi_register_offset[port]); base 181 drivers/gpio/gpio-ep93xx.c writeb(port_mask, epg->base + eoi_register_offset[port]); base 279 drivers/gpio/gpio-ep93xx.c int base; base 290 drivers/gpio/gpio-ep93xx.c .base = _base, \ base 334 drivers/gpio/gpio-ep93xx.c void __iomem *data = epg->base + bank->data; base 335 drivers/gpio/gpio-ep93xx.c void __iomem *dir = epg->base + bank->dir; base 345 drivers/gpio/gpio-ep93xx.c gc->base = bank->base; base 413 drivers/gpio/gpio-ep93xx.c epg->base = devm_platform_ioremap_resource(pdev, 0); base 414 drivers/gpio/gpio-ep93xx.c if (IS_ERR(epg->base)) base 415 drivers/gpio/gpio-ep93xx.c return PTR_ERR(epg->base); base 161 drivers/gpio/gpio-exar.c exar_gpio->gpio_chip.base = -1; base 74 drivers/gpio/gpio-f7188x.c static inline int superio_inb(int base, int reg) base 76 drivers/gpio/gpio-f7188x.c outb(reg, base); base 77 drivers/gpio/gpio-f7188x.c return inb(base + 1); base 80 drivers/gpio/gpio-f7188x.c static int superio_inw(int base, int reg) base 84 drivers/gpio/gpio-f7188x.c outb(reg++, base); base 85 drivers/gpio/gpio-f7188x.c val = inb(base + 1) << 8; base 86 drivers/gpio/gpio-f7188x.c outb(reg, base); base 87 drivers/gpio/gpio-f7188x.c val |= inb(base + 1); base 92 drivers/gpio/gpio-f7188x.c static inline void superio_outb(int base, int reg, int val) base 94 drivers/gpio/gpio-f7188x.c outb(reg, base); base 95 drivers/gpio/gpio-f7188x.c outb(val, base + 1); base 98 drivers/gpio/gpio-f7188x.c static inline int superio_enter(int base) base 101 drivers/gpio/gpio-f7188x.c if (!request_muxed_region(base, 2, DRVNAME)) { base 102 drivers/gpio/gpio-f7188x.c pr_err(DRVNAME "I/O address 0x%04x already in use\n", base); base 107 drivers/gpio/gpio-f7188x.c outb(SIO_UNLOCK_KEY, base); base 108 drivers/gpio/gpio-f7188x.c outb(SIO_UNLOCK_KEY, base); base 113 drivers/gpio/gpio-f7188x.c static inline void superio_select(int base, int ld) base 115 drivers/gpio/gpio-f7188x.c outb(SIO_LDSEL, base); base 116 drivers/gpio/gpio-f7188x.c outb(ld, base + 1); base 119 drivers/gpio/gpio-f7188x.c static inline void superio_exit(int base) base 121 drivers/gpio/gpio-f7188x.c outb(SIO_LOCK_KEY, base); base 122 drivers/gpio/gpio-f7188x.c release_region(base, 2); base 149 drivers/gpio/gpio-f7188x.c .base = _base, \ base 156 drivers/gpio/gpio-f7188x.c #define gpio_dir(base) (base + 0) base 157 drivers/gpio/gpio-f7188x.c #define gpio_data_out(base) (base + 1) base 158 drivers/gpio/gpio-f7188x.c #define gpio_data_in(base) (base + 2) base 160 drivers/gpio/gpio-f7188x.c #define gpio_out_mode(base) (base + 3) base 52 drivers/gpio/gpio-ftgpio010.c void __iomem *base; base 61 drivers/gpio/gpio-ftgpio010.c writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR); base 70 drivers/gpio/gpio-ftgpio010.c val = readl(g->base + GPIO_INT_EN); base 72 drivers/gpio/gpio-ftgpio010.c writel(val, g->base + GPIO_INT_EN); base 81 drivers/gpio/gpio-ftgpio010.c val = readl(g->base + GPIO_INT_EN); base 83 drivers/gpio/gpio-ftgpio010.c writel(val, g->base + GPIO_INT_EN); base 93 drivers/gpio/gpio-ftgpio010.c reg_type = readl(g->base + GPIO_INT_TYPE); base 94 drivers/gpio/gpio-ftgpio010.c reg_level = readl(g->base + GPIO_INT_LEVEL); base 95 drivers/gpio/gpio-ftgpio010.c reg_both = readl(g->base + GPIO_INT_BOTH_EDGE); base 130 drivers/gpio/gpio-ftgpio010.c writel(reg_type, g->base + GPIO_INT_TYPE); base 131 drivers/gpio/gpio-ftgpio010.c writel(reg_level, g->base + GPIO_INT_LEVEL); base 132 drivers/gpio/gpio-ftgpio010.c writel(reg_both, g->base + GPIO_INT_BOTH_EDGE); base 149 drivers/gpio/gpio-ftgpio010.c stat = readl(g->base + GPIO_INT_STAT_RAW); base 192 drivers/gpio/gpio-ftgpio010.c val = readl(g->base + GPIO_DEBOUNCE_PRESCALE); base 201 drivers/gpio/gpio-ftgpio010.c val = readl(g->base + GPIO_DEBOUNCE_EN); base 203 drivers/gpio/gpio-ftgpio010.c writel(val, g->base + GPIO_DEBOUNCE_EN); base 207 drivers/gpio/gpio-ftgpio010.c val = readl(g->base + GPIO_DEBOUNCE_EN); base 217 drivers/gpio/gpio-ftgpio010.c writel(deb_div, g->base + GPIO_DEBOUNCE_PRESCALE); base 220 drivers/gpio/gpio-ftgpio010.c writel(val, g->base + GPIO_DEBOUNCE_EN); base 239 drivers/gpio/gpio-ftgpio010.c g->base = devm_platform_ioremap_resource(pdev, 0); base 240 drivers/gpio/gpio-ftgpio010.c if (IS_ERR(g->base)) base 241 drivers/gpio/gpio-ftgpio010.c return PTR_ERR(g->base); base 261 drivers/gpio/gpio-ftgpio010.c g->base + GPIO_DATA_IN, base 262 drivers/gpio/gpio-ftgpio010.c g->base + GPIO_DATA_SET, base 263 drivers/gpio/gpio-ftgpio010.c g->base + GPIO_DATA_CLR, base 264 drivers/gpio/gpio-ftgpio010.c g->base + GPIO_DIR, base 272 drivers/gpio/gpio-ftgpio010.c g->gc.base = -1; base 302 drivers/gpio/gpio-ftgpio010.c writel(0x0, g->base + GPIO_INT_EN); base 303 drivers/gpio/gpio-ftgpio010.c writel(0x0, g->base + GPIO_INT_MASK); base 304 drivers/gpio/gpio-ftgpio010.c writel(~0x0, g->base + GPIO_INT_CLR); base 307 drivers/gpio/gpio-ftgpio010.c writel(0x0, g->base + GPIO_DEBOUNCE_EN); base 314 drivers/gpio/gpio-ftgpio010.c dev_info(dev, "FTGPIO010 @%p registered\n", g->base); base 82 drivers/gpio/gpio-ge.c gc->base = -1; base 25 drivers/gpio/gpio-gpio-mm.c static unsigned int base[MAX_NUM_GPIOMM]; base 27 drivers/gpio/gpio-gpio-mm.c module_param_hw_array(base, uint, ioport, &num_gpiomm, 0); base 28 drivers/gpio/gpio-gpio-mm.c MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses"); base 45 drivers/gpio/gpio-gpio-mm.c unsigned int base; base 64 drivers/gpio/gpio-gpio-mm.c const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4; base 103 drivers/gpio/gpio-gpio-mm.c const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4; base 136 drivers/gpio/gpio-gpio-mm.c outb(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port); base 160 drivers/gpio/gpio-gpio-mm.c port_state = inb(gpiommgpio->base + in_port); base 203 drivers/gpio/gpio-gpio-mm.c port_state = inb(gpiommgpio->base + ports[i]); base 228 drivers/gpio/gpio-gpio-mm.c outb(gpiommgpio->out_state[port], gpiommgpio->base + out_port); base 261 drivers/gpio/gpio-gpio-mm.c outb(gpiommgpio->out_state[port], gpiommgpio->base + out_port); base 293 drivers/gpio/gpio-gpio-mm.c if (!devm_request_region(dev, base[id], GPIOMM_EXTENT, name)) { base 295 drivers/gpio/gpio-gpio-mm.c base[id], base[id] + GPIOMM_EXTENT); base 302 drivers/gpio/gpio-gpio-mm.c gpiommgpio->chip.base = -1; base 312 drivers/gpio/gpio-gpio-mm.c gpiommgpio->base = base[id]; base 323 drivers/gpio/gpio-gpio-mm.c outb(0x80, base[id] + 3); base 324 drivers/gpio/gpio-gpio-mm.c outb(0x00, base[id]); base 325 drivers/gpio/gpio-gpio-mm.c outb(0x00, base[id] + 1); base 326 drivers/gpio/gpio-gpio-mm.c outb(0x00, base[id] + 2); base 327 drivers/gpio/gpio-gpio-mm.c outb(0x80, base[id] + 7); base 328 drivers/gpio/gpio-gpio-mm.c outb(0x00, base[id] + 4); base 329 drivers/gpio/gpio-gpio-mm.c outb(0x00, base[id] + 5); base 330 drivers/gpio/gpio-gpio-mm.c outb(0x00, base[id] + 6); base 365 drivers/gpio/gpio-grgpio.c gc->base = -1; base 430 drivers/gpio/gpio-grgpio.c priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off"); base 82 drivers/gpio/gpio-gw-pld.c gw->chip.base = -1; base 143 drivers/gpio/gpio-htc-egpio.c pr_debug("egpio_get_value(%d)\n", chip->base + offset); base 183 drivers/gpio/gpio-htc-egpio.c chip->label, offset, offset+chip->base, value); base 335 drivers/gpio/gpio-htc-egpio.c chip->base = pdata->chip[i].gpio_base; base 275 drivers/gpio/gpio-ich.c chip->base = modparam_gpiobase; base 465 drivers/gpio/gpio-ich.c dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base, base 466 drivers/gpio/gpio-ich.c ichx_priv.chip.base + ichx_priv.chip.ngpio - 1); base 276 drivers/gpio/gpio-intel-mid.c u32 base, gpio, mask; base 281 drivers/gpio/gpio-intel-mid.c for (base = 0; base < priv->chip.ngpio; base += 32) { base 282 drivers/gpio/gpio-intel-mid.c gedr = gpio_reg(&priv->chip, base, GEDR); base 289 drivers/gpio/gpio-intel-mid.c base + gpio)); base 300 drivers/gpio/gpio-intel-mid.c unsigned base; base 302 drivers/gpio/gpio-intel-mid.c for (base = 0; base < priv->chip.ngpio; base += 32) { base 304 drivers/gpio/gpio-intel-mid.c reg = gpio_reg(&priv->chip, base, GRER); base 307 drivers/gpio/gpio-intel-mid.c reg = gpio_reg(&priv->chip, base, GFER); base 310 drivers/gpio/gpio-intel-mid.c reg = gpio_reg(&priv->chip, base, GEDR); base 330 drivers/gpio/gpio-intel-mid.c void __iomem *base; base 349 drivers/gpio/gpio-intel-mid.c base = pcim_iomap_table(pdev)[1]; base 351 drivers/gpio/gpio-intel-mid.c irq_base = readl(base); base 352 drivers/gpio/gpio-intel-mid.c gpio_base = readl(sizeof(u32) + base); base 369 drivers/gpio/gpio-intel-mid.c priv->chip.base = gpio_base; base 21 drivers/gpio/gpio-iop.c void __iomem *base; base 28 drivers/gpio/gpio-iop.c base = devm_platform_ioremap_resource(pdev, 0); base 29 drivers/gpio/gpio-iop.c if (IS_ERR(base)) base 30 drivers/gpio/gpio-iop.c return PTR_ERR(base); base 32 drivers/gpio/gpio-iop.c err = bgpio_init(gc, &pdev->dev, 1, base + IOP3XX_GPID, base 33 drivers/gpio/gpio-iop.c base + IOP3XX_GPOD, NULL, NULL, base + IOP3XX_GPOE, 0); base 37 drivers/gpio/gpio-iop.c gc->base = 0; base 277 drivers/gpio/gpio-it87.c .base = -1 base 58 drivers/gpio/gpio-ixp4xx.c void __iomem *base; base 67 drivers/gpio/gpio-ixp4xx.c __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); base 134 drivers/gpio/gpio-ixp4xx.c val = __raw_readl(g->base + int_reg); base 136 drivers/gpio/gpio-ixp4xx.c __raw_writel(val, g->base + int_reg); base 138 drivers/gpio/gpio-ixp4xx.c __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); base 141 drivers/gpio/gpio-ixp4xx.c val = __raw_readl(g->base + int_reg); base 143 drivers/gpio/gpio-ixp4xx.c __raw_writel(val, g->base + int_reg); base 146 drivers/gpio/gpio-ixp4xx.c val = __raw_readl(g->base + IXP4XX_REG_GPOE); base 148 drivers/gpio/gpio-ixp4xx.c __raw_writel(val, g->base + IXP4XX_REG_GPOE); base 206 drivers/gpio/gpio-ixp4xx.c g->base = devm_ioremap_resource(dev, res); base 207 drivers/gpio/gpio-ixp4xx.c if (IS_ERR(g->base)) base 208 drivers/gpio/gpio-ixp4xx.c return PTR_ERR(g->base); base 244 drivers/gpio/gpio-ixp4xx.c __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK); base 263 drivers/gpio/gpio-ixp4xx.c g->base + IXP4XX_REG_GPIN, base 264 drivers/gpio/gpio-ixp4xx.c g->base + IXP4XX_REG_GPOUT, base 267 drivers/gpio/gpio-ixp4xx.c g->base + IXP4XX_REG_GPOE, base 280 drivers/gpio/gpio-ixp4xx.c g->gc.base = 0; base 176 drivers/gpio/gpio-janz-ttl.c gpio->base = -1; base 159 drivers/gpio/gpio-kempld.c chip->base = pdata->gpio_base; base 161 drivers/gpio/gpio-kempld.c chip->base = -1; base 104 drivers/gpio/gpio-loongson.c gc->base = 0; base 69 drivers/gpio/gpio-loongson1.c gc->base = pdev->id * 32; base 183 drivers/gpio/gpio-lp3943.c .base = -1, base 137 drivers/gpio/gpio-lp873x.c .base = -1, base 146 drivers/gpio/gpio-lp87565.c .base = -1, base 43 drivers/gpio/gpio-lpc18xx.c void __iomem *base; base 50 drivers/gpio/gpio-lpc18xx.c void __iomem *base; base 59 drivers/gpio/gpio-lpc18xx.c u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL); base 66 drivers/gpio/gpio-lpc18xx.c writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL); base 72 drivers/gpio/gpio-lpc18xx.c writel_relaxed(BIT(pin), ic->base + reg); base 237 drivers/gpio/gpio-lpc18xx.c ic->base = devm_ioremap_resource(dev, &res); base 238 drivers/gpio/gpio-lpc18xx.c if (IS_ERR(ic->base)) { base 239 drivers/gpio/gpio-lpc18xx.c ret = PTR_ERR(ic->base); base 261 drivers/gpio/gpio-lpc18xx.c devm_iounmap(dev, ic->base); base 271 drivers/gpio/gpio-lpc18xx.c writeb(value ? 1 : 0, gc->base + offset); base 277 drivers/gpio/gpio-lpc18xx.c return !!readb(gc->base + offset); base 291 drivers/gpio/gpio-lpc18xx.c dir = readl(gc->base + LPC18XX_REG_DIR(port)); base 296 drivers/gpio/gpio-lpc18xx.c writel(dir, gc->base + LPC18XX_REG_DIR(port)); base 343 drivers/gpio/gpio-lpc18xx.c gc->base = devm_platform_ioremap_resource(pdev, 0); base 351 drivers/gpio/gpio-lpc18xx.c gc->base = devm_ioremap_resource(dev, &res); base 353 drivers/gpio/gpio-lpc18xx.c if (IS_ERR(gc->base)) base 354 drivers/gpio/gpio-lpc18xx.c return PTR_ERR(gc->base); base 407 drivers/gpio/gpio-lpc32xx.c .base = LPC32XX_GPIO_P0_GRP, base 423 drivers/gpio/gpio-lpc32xx.c .base = LPC32XX_GPIO_P1_GRP, base 438 drivers/gpio/gpio-lpc32xx.c .base = LPC32XX_GPIO_P2_GRP, base 454 drivers/gpio/gpio-lpc32xx.c .base = LPC32XX_GPIO_P3_GRP, base 468 drivers/gpio/gpio-lpc32xx.c .base = LPC32XX_GPI_P3_GRP, base 482 drivers/gpio/gpio-lpc32xx.c .base = LPC32XX_GPO_P3_GRP, base 236 drivers/gpio/gpio-lynxpoint.c u32 base, pin; base 239 drivers/gpio/gpio-lynxpoint.c for (base = 0; base < lg->chip.ngpio; base += 32) { base 240 drivers/gpio/gpio-lynxpoint.c reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); base 241 drivers/gpio/gpio-lynxpoint.c ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); base 252 drivers/gpio/gpio-lynxpoint.c irq = irq_find_mapping(lg->chip.irq.domain, base + pin); base 307 drivers/gpio/gpio-lynxpoint.c unsigned base; base 309 drivers/gpio/gpio-lynxpoint.c for (base = 0; base < lg->chip.ngpio; base += 32) { base 311 drivers/gpio/gpio-lynxpoint.c reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); base 314 drivers/gpio/gpio-lynxpoint.c reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); base 365 drivers/gpio/gpio-lynxpoint.c gc->base = -1; base 165 drivers/gpio/gpio-madera.c madera_gpio->gpio_chip.base = pdata->gpio_base; base 167 drivers/gpio/gpio-madera.c madera_gpio->gpio_chip.base = -1; base 421 drivers/gpio/gpio-max3191x.c max3191x->gpio.base = -1; base 176 drivers/gpio/gpio-max730x.c ts->chip.base = pdata->base; base 178 drivers/gpio/gpio-max730x.c ts->chip.base = -1; base 234 drivers/gpio/gpio-max732x.c unsigned base = off & ~0x7; base 237 drivers/gpio/gpio-max732x.c max732x_gpio_set_mask(gc, base, mask, val << (off & 0x7)); base 594 drivers/gpio/gpio-max732x.c gc->base = gpio_start; base 707 drivers/gpio/gpio-max732x.c ret = pdata->setup(client, chip->gpio_chip.base, base 725 drivers/gpio/gpio-max732x.c ret = pdata->teardown(client, chip->gpio_chip.base, base 293 drivers/gpio/gpio-max77620.c mgpio->gpio_chip.base = -1; base 162 drivers/gpio/gpio-max77650.c chip->gc.base = -1; base 38 drivers/gpio/gpio-mb86s7x.c void __iomem *base; base 51 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + PFR(gpio)); base 53 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + PFR(gpio)); base 68 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + PFR(gpio)); base 70 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + PFR(gpio)); base 83 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + DDR(gpio)); base 85 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + DDR(gpio)); base 101 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + PDR(gpio)); base 106 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + PDR(gpio)); base 108 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + DDR(gpio)); base 110 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + DDR(gpio)); base 121 drivers/gpio/gpio-mb86s7x.c return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio)); base 132 drivers/gpio/gpio-mb86s7x.c val = readl(gchip->base + PDR(gpio)); base 137 drivers/gpio/gpio-mb86s7x.c writel(val, gchip->base + PDR(gpio)); base 167 drivers/gpio/gpio-mb86s7x.c gchip->base = devm_platform_ioremap_resource(pdev, 0); base 168 drivers/gpio/gpio-mb86s7x.c if (IS_ERR(gchip->base)) base 169 drivers/gpio/gpio-mb86s7x.c return PTR_ERR(gchip->base); base 193 drivers/gpio/gpio-mb86s7x.c gchip->gc.base = -1; base 78 drivers/gpio/gpio-mc33880.c if (!pdata || !pdata->base) { base 104 drivers/gpio/gpio-mc33880.c mc->chip.base = pdata->base; base 86 drivers/gpio/gpio-mc9s08dz60.c mc9s->chip.base = -1; base 338 drivers/gpio/gpio-merrifield.c unsigned long base, gpio; base 343 drivers/gpio/gpio-merrifield.c for (base = 0; base < priv->chip.ngpio; base += 32) { base 344 drivers/gpio/gpio-merrifield.c void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); base 345 drivers/gpio/gpio-merrifield.c void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); base 357 drivers/gpio/gpio-merrifield.c irq = irq_find_mapping(gc->irq.domain, base + gpio); base 368 drivers/gpio/gpio-merrifield.c unsigned int base; base 370 drivers/gpio/gpio-merrifield.c for (base = 0; base < priv->chip.ngpio; base += 32) { base 372 drivers/gpio/gpio-merrifield.c reg = gpio_reg(&priv->chip, base, GRER); base 375 drivers/gpio/gpio-merrifield.c reg = gpio_reg(&priv->chip, base, GFER); base 402 drivers/gpio/gpio-merrifield.c void __iomem *base; base 416 drivers/gpio/gpio-merrifield.c base = pcim_iomap_table(pdev)[1]; base 418 drivers/gpio/gpio-merrifield.c irq_base = readl(base); base 419 drivers/gpio/gpio-merrifield.c gpio_base = readl(sizeof(u32) + base); base 441 drivers/gpio/gpio-merrifield.c priv->chip.base = gpio_base; base 79 drivers/gpio/gpio-ml-ioh.c void __iomem *base; base 229 drivers/gpio/gpio-ml-ioh.c gpio->base = -1; base 383 drivers/gpio/gpio-ml-ioh.c chip->base, handle_simple_irq); base 409 drivers/gpio/gpio-ml-ioh.c void __iomem *base; base 425 drivers/gpio/gpio-ml-ioh.c base = pci_iomap(pdev, 1, 0); base 426 drivers/gpio/gpio-ml-ioh.c if (!base) { base 441 drivers/gpio/gpio-ml-ioh.c chip->base = base; base 442 drivers/gpio/gpio-ml-ioh.c chip->reg = chip->base; base 493 drivers/gpio/gpio-ml-ioh.c pci_iounmap(pdev, base); base 519 drivers/gpio/gpio-ml-ioh.c pci_iounmap(pdev, chip->base); base 43 drivers/gpio/gpio-mlxbf.c void __iomem *base; base 61 drivers/gpio/gpio-mlxbf.c gs->base = devm_platform_ioremap_resource(pdev, 0); base 62 drivers/gpio/gpio-mlxbf.c if (IS_ERR(gs->base)) base 63 drivers/gpio/gpio-mlxbf.c return PTR_ERR(gs->base); base 67 drivers/gpio/gpio-mlxbf.c gs->base + MLXBF_GPIO_PIN_STATE, base 70 drivers/gpio/gpio-mlxbf.c gs->base + MLXBF_GPIO_PIN_DIR_O, base 71 drivers/gpio/gpio-mlxbf.c gs->base + MLXBF_GPIO_PIN_DIR_I, base 95 drivers/gpio/gpio-mlxbf.c gs->csave_regs.scratchpad = readq(gs->base + MLXBF_GPIO_SCRATCHPAD); base 97 drivers/gpio/gpio-mlxbf.c readq(gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD); base 99 drivers/gpio/gpio-mlxbf.c readq(gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD); base 101 drivers/gpio/gpio-mlxbf.c readq(gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD); base 103 drivers/gpio/gpio-mlxbf.c readq(gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD); base 104 drivers/gpio/gpio-mlxbf.c gs->csave_regs.pin_dir_i = readq(gs->base + MLXBF_GPIO_PIN_DIR_I); base 105 drivers/gpio/gpio-mlxbf.c gs->csave_regs.pin_dir_o = readq(gs->base + MLXBF_GPIO_PIN_DIR_O); base 114 drivers/gpio/gpio-mlxbf.c writeq(gs->csave_regs.scratchpad, gs->base + MLXBF_GPIO_SCRATCHPAD); base 116 drivers/gpio/gpio-mlxbf.c gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD); base 118 drivers/gpio/gpio-mlxbf.c gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD); base 120 drivers/gpio/gpio-mlxbf.c gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD); base 122 drivers/gpio/gpio-mlxbf.c gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD); base 123 drivers/gpio/gpio-mlxbf.c writeq(gs->csave_regs.pin_dir_i, gs->base + MLXBF_GPIO_PIN_DIR_I); base 124 drivers/gpio/gpio-mlxbf.c writeq(gs->csave_regs.pin_dir_o, gs->base + MLXBF_GPIO_PIN_DIR_O); base 599 drivers/gpio/gpio-mmio.c gc->base = -1; base 689 drivers/gpio/gpio-mmio.c pdata->base = -1; base 768 drivers/gpio/gpio-mmio.c gc->base = pdata->base; base 378 drivers/gpio/gpio-mockup.c int rv, base; base 383 drivers/gpio/gpio-mockup.c rv = device_property_read_u32(dev, "gpio-base", &base); base 385 drivers/gpio/gpio-mockup.c base = -1; base 409 drivers/gpio/gpio-mockup.c gc->base = base; base 473 drivers/gpio/gpio-mockup.c int i, prop, num_chips, err = 0, base; base 508 drivers/gpio/gpio-mockup.c base = gpio_mockup_range_base(i); base 509 drivers/gpio/gpio-mockup.c if (base >= 0) base 511 drivers/gpio/gpio-mockup.c base); base 513 drivers/gpio/gpio-mockup.c ngpio = base < 0 ? gpio_mockup_range_ngpio(i) base 514 drivers/gpio/gpio-mockup.c : gpio_mockup_range_ngpio(i) - base; base 146 drivers/gpio/gpio-moxtet.c chip->gpio_chip.base = -1; base 276 drivers/gpio/gpio-msic.c mg->chip.base = pdata->gpio_base; base 55 drivers/gpio/gpio-mt7621.c void __iomem *base; base 73 drivers/gpio/gpio-mt7621.c gc->write_reg(mtk->base + offset, val); base 83 drivers/gpio/gpio-mt7621.c return gc->read_reg(mtk->base + offset); base 225 drivers/gpio/gpio-mt7621.c dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE); base 226 drivers/gpio/gpio-mt7621.c set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE); base 227 drivers/gpio/gpio-mt7621.c ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); base 228 drivers/gpio/gpio-mt7621.c diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); base 307 drivers/gpio/gpio-mt7621.c mtk->base = devm_platform_ioremap_resource(pdev, 0); base 308 drivers/gpio/gpio-mt7621.c if (IS_ERR(mtk->base)) base 309 drivers/gpio/gpio-mt7621.c return PTR_ERR(mtk->base); base 347 drivers/gpio/gpio-mvebu.c ret = pinctrl_gpio_direction_input(chip->base + pin); base 367 drivers/gpio/gpio-mvebu.c ret = pinctrl_gpio_direction_output(chip->base + pin); base 834 drivers/gpio/gpio-mvebu.c mvpwm->chip.base = -1; base 871 drivers/gpio/gpio-mvebu.c seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); base 1038 drivers/gpio/gpio-mvebu.c void __iomem *base; base 1040 drivers/gpio/gpio-mvebu.c base = devm_platform_ioremap_resource(pdev, 0); base 1041 drivers/gpio/gpio-mvebu.c if (IS_ERR(base)) base 1042 drivers/gpio/gpio-mvebu.c return PTR_ERR(base); base 1044 drivers/gpio/gpio-mvebu.c mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, base 1060 drivers/gpio/gpio-mvebu.c base = devm_platform_ioremap_resource(pdev, 1); base 1061 drivers/gpio/gpio-mvebu.c if (IS_ERR(base)) base 1062 drivers/gpio/gpio-mvebu.c return PTR_ERR(base); base 1065 drivers/gpio/gpio-mvebu.c devm_regmap_init_mmio(&pdev->dev, base, base 1144 drivers/gpio/gpio-mvebu.c mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; base 60 drivers/gpio/gpio-mxc.c void __iomem *base; base 178 drivers/gpio/gpio-mxc.c void __iomem *reg = port->base; base 214 drivers/gpio/gpio-mxc.c val = readl(port->base + GPIO_EDGE_SEL); base 217 drivers/gpio/gpio-mxc.c port->base + GPIO_EDGE_SEL); base 220 drivers/gpio/gpio-mxc.c port->base + GPIO_EDGE_SEL); base 230 drivers/gpio/gpio-mxc.c writel(1 << gpio_idx, port->base + GPIO_ISR); base 237 drivers/gpio/gpio-mxc.c void __iomem *reg = port->base; base 284 drivers/gpio/gpio-mxc.c irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); base 302 drivers/gpio/gpio-mxc.c irq_msk = readl(port->base + GPIO_IMR); base 306 drivers/gpio/gpio-mxc.c irq_stat = readl(port->base + GPIO_ISR) & irq_msk; base 351 drivers/gpio/gpio-mxc.c port->base, handle_level_irq); base 426 drivers/gpio/gpio-mxc.c port->base = devm_platform_ioremap_resource(pdev, 0); base 427 drivers/gpio/gpio-mxc.c if (IS_ERR(port->base)) base 428 drivers/gpio/gpio-mxc.c return PTR_ERR(port->base); base 459 drivers/gpio/gpio-mxc.c writel(0, port->base + GPIO_IMR); base 460 drivers/gpio/gpio-mxc.c writel(~0, port->base + GPIO_ISR); base 481 drivers/gpio/gpio-mxc.c port->base + GPIO_PSR, base 482 drivers/gpio/gpio-mxc.c port->base + GPIO_DR, NULL, base 483 drivers/gpio/gpio-mxc.c port->base + GPIO_GDIR, NULL, base 494 drivers/gpio/gpio-mxc.c port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : base 538 drivers/gpio/gpio-mxc.c port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1); base 539 drivers/gpio/gpio-mxc.c port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2); base 540 drivers/gpio/gpio-mxc.c port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR); base 541 drivers/gpio/gpio-mxc.c port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR); base 542 drivers/gpio/gpio-mxc.c port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL); base 543 drivers/gpio/gpio-mxc.c port->gpio_saved_reg.dr = readl(port->base + GPIO_DR); base 551 drivers/gpio/gpio-mxc.c writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1); base 552 drivers/gpio/gpio-mxc.c writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2); base 553 drivers/gpio/gpio-mxc.c writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR); base 554 drivers/gpio/gpio-mxc.c writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR); base 555 drivers/gpio/gpio-mxc.c writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL); base 556 drivers/gpio/gpio-mxc.c writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); base 48 drivers/gpio/gpio-mxs.c void __iomem *base; base 87 drivers/gpio/gpio-mxs.c val = readl(port->base + PINCTRL_DIN(port)) & pin_mask; base 111 drivers/gpio/gpio-mxs.c pin_addr = port->base + PINCTRL_IRQLEV(port); base 114 drivers/gpio/gpio-mxs.c writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET); base 117 drivers/gpio/gpio-mxs.c writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET); base 121 drivers/gpio/gpio-mxs.c pin_addr = port->base + PINCTRL_IRQPOL(port); base 127 drivers/gpio/gpio-mxs.c writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR); base 139 drivers/gpio/gpio-mxs.c pin_addr = port->base + PINCTRL_IRQPOL(port); base 157 drivers/gpio/gpio-mxs.c irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) & base 158 drivers/gpio/gpio-mxs.c readl(port->base + PINCTRL_IRQEN(port)); base 199 drivers/gpio/gpio-mxs.c port->base, handle_level_irq); base 250 drivers/gpio/gpio-mxs.c dir = readl(port->base + PINCTRL_DOE(port)); base 278 drivers/gpio/gpio-mxs.c static void __iomem *base; base 300 drivers/gpio/gpio-mxs.c if (!base) { base 302 drivers/gpio/gpio-mxs.c base = of_iomap(parent, 0); base 304 drivers/gpio/gpio-mxs.c if (!base) base 307 drivers/gpio/gpio-mxs.c port->base = base; base 310 drivers/gpio/gpio-mxs.c writel(0, port->base + PINCTRL_PIN2IRQ(port)); base 311 drivers/gpio/gpio-mxs.c writel(0, port->base + PINCTRL_IRQEN(port)); base 314 drivers/gpio/gpio-mxs.c writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR); base 339 drivers/gpio/gpio-mxs.c port->base + PINCTRL_DIN(port), base 340 drivers/gpio/gpio-mxs.c port->base + PINCTRL_DOUT(port) + MXS_SET, base 341 drivers/gpio/gpio-mxs.c port->base + PINCTRL_DOUT(port) + MXS_CLR, base 342 drivers/gpio/gpio-mxs.c port->base + PINCTRL_DOE(port), NULL, 0); base 348 drivers/gpio/gpio-mxs.c port->gc.base = port->id * 32; base 359 drivers/gpio/gpio-mxs.c iounmap(port->base); base 102 drivers/gpio/gpio-octeon.c chip->base = 0; base 47 drivers/gpio/gpio-omap.c void __iomem *base; base 109 drivers/gpio/gpio-omap.c bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, base 118 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; base 136 drivers/gpio/gpio-omap.c bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, base 147 drivers/gpio/gpio-omap.c bank->base + bank->regs->debounce_en); base 159 drivers/gpio/gpio-omap.c writel_relaxed(0, bank->base + bank->regs->debounce_en); base 197 drivers/gpio/gpio-omap.c writel_relaxed(debounce, bank->base + bank->regs->debounce); base 199 drivers/gpio/gpio-omap.c val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); base 243 drivers/gpio/gpio-omap.c bank->base + bank->regs->debounce_en); base 247 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.debounce, bank->base + base 273 drivers/gpio/gpio-omap.c void __iomem *base = bank->base; base 276 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit, base 278 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit, base 286 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit, base 288 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit, base 292 drivers/gpio/gpio-omap.c readl_relaxed(bank->base + bank->regs->leveldetect0); base 294 drivers/gpio/gpio-omap.c readl_relaxed(bank->base + bank->regs->leveldetect1); base 296 drivers/gpio/gpio-omap.c readl_relaxed(bank->base + bank->regs->risingdetect); base 298 drivers/gpio/gpio-omap.c readl_relaxed(bank->base + bank->regs->fallingdetect); base 325 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->irqctrl; base 334 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; base 374 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->pinctrl; base 381 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->ctrl; base 395 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->ctrl; base 408 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->direction; base 469 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; base 476 drivers/gpio/gpio-omap.c reg = bank->base + bank->regs->irqstatus2; base 492 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; base 507 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; base 534 drivers/gpio/gpio-omap.c omap_gpio_rmw(bank->base + bank->regs->wkup_en, base 565 drivers/gpio/gpio-omap.c isr_reg = bank->base + bank->regs->irqstatus; base 715 drivers/gpio/gpio-omap.c void __iomem *mask_reg = bank->base + base 729 drivers/gpio/gpio-omap.c void __iomem *mask_reg = bank->base + base 808 drivers/gpio/gpio-omap.c return !!(readl_relaxed(bank->base + bank->regs->direction) & base 830 drivers/gpio/gpio-omap.c reg = bank->base + bank->regs->datain; base 832 drivers/gpio/gpio-omap.c reg = bank->base + bank->regs->dataout; base 854 drivers/gpio/gpio-omap.c void __iomem *base = bank->base; base 857 drivers/gpio/gpio-omap.c direction = readl_relaxed(base + bank->regs->direction); base 861 drivers/gpio/gpio-omap.c val |= readl_relaxed(base + bank->regs->datain) & m; base 865 drivers/gpio/gpio-omap.c val |= readl_relaxed(base + bank->regs->dataout) & m; base 920 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->dataout; base 941 drivers/gpio/gpio-omap.c rev = readw_relaxed(bank->base + bank->regs->revision); base 950 drivers/gpio/gpio-omap.c void __iomem *base = bank->base; base 957 drivers/gpio/gpio-omap.c writel_relaxed(l, bank->base + bank->regs->irqenable); base 961 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->irqenable, l, base 963 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->irqstatus, l, base 966 drivers/gpio/gpio-omap.c writel_relaxed(0, base + bank->regs->debounce_en); base 969 drivers/gpio/gpio-omap.c bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); base 972 drivers/gpio/gpio-omap.c writel_relaxed(0, base + bank->regs->ctrl); base 1001 drivers/gpio/gpio-omap.c bank->chip.base = OMAP_MPUIO(0); base 1008 drivers/gpio/gpio-omap.c bank->chip.base = gpio; base 1059 drivers/gpio/gpio-omap.c void __iomem *base = p->base; base 1061 drivers/gpio/gpio-omap.c p->context.ctrl = readl_relaxed(base + regs->ctrl); base 1062 drivers/gpio/gpio-omap.c p->context.oe = readl_relaxed(base + regs->direction); base 1063 drivers/gpio/gpio-omap.c p->context.wake_en = readl_relaxed(base + regs->wkup_en); base 1064 drivers/gpio/gpio-omap.c p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); base 1065 drivers/gpio/gpio-omap.c p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); base 1066 drivers/gpio/gpio-omap.c p->context.risingdetect = readl_relaxed(base + regs->risingdetect); base 1067 drivers/gpio/gpio-omap.c p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); base 1068 drivers/gpio/gpio-omap.c p->context.irqenable1 = readl_relaxed(base + regs->irqenable); base 1069 drivers/gpio/gpio-omap.c p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); base 1070 drivers/gpio/gpio-omap.c p->context.dataout = readl_relaxed(base + regs->dataout); base 1078 drivers/gpio/gpio-omap.c void __iomem *base = bank->base; base 1080 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.wake_en, base + regs->wkup_en); base 1081 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.ctrl, base + regs->ctrl); base 1082 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0); base 1083 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1); base 1084 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.risingdetect, base + regs->risingdetect); base 1085 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect); base 1086 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.dataout, base + regs->dataout); base 1087 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.oe, base + regs->direction); base 1090 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.debounce, base + regs->debounce); base 1092 drivers/gpio/gpio-omap.c base + regs->debounce_en); base 1095 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.irqenable1, base + regs->irqenable); base 1096 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.irqenable2, base + regs->irqenable2); base 1102 drivers/gpio/gpio-omap.c void __iomem *base = bank->base; base 1105 drivers/gpio/gpio-omap.c bank->saved_datain = readl_relaxed(base + bank->regs->datain); base 1130 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake); base 1131 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake); base 1177 drivers/gpio/gpio-omap.c bank->base + bank->regs->fallingdetect); base 1179 drivers/gpio/gpio-omap.c bank->base + bank->regs->risingdetect); base 1182 drivers/gpio/gpio-omap.c l = readl_relaxed(bank->base + bank->regs->datain); base 1212 drivers/gpio/gpio-omap.c old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); base 1213 drivers/gpio/gpio-omap.c old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); base 1216 drivers/gpio/gpio-omap.c writel_relaxed(old0 | gen, bank->base + base 1218 drivers/gpio/gpio-omap.c writel_relaxed(old1 | gen, bank->base + base 1223 drivers/gpio/gpio-omap.c writel_relaxed(old0 | l, bank->base + base 1225 drivers/gpio/gpio-omap.c writel_relaxed(old1 | l, bank->base + base 1228 drivers/gpio/gpio-omap.c writel_relaxed(old0, bank->base + bank->regs->leveldetect0); base 1229 drivers/gpio/gpio-omap.c writel_relaxed(old1, bank->base + bank->regs->leveldetect1); base 1422 drivers/gpio/gpio-omap.c bank->base = devm_platform_ioremap_resource(pdev, 0); base 1423 drivers/gpio/gpio-omap.c if (IS_ERR(bank->base)) { base 1424 drivers/gpio/gpio-omap.c return PTR_ERR(bank->base); base 178 drivers/gpio/gpio-palmas.c palmas_gpio->gpio_chip.base = palmas_pdata->gpio_base; base 180 drivers/gpio/gpio-palmas.c palmas_gpio->gpio_chip.base = -1; base 555 drivers/gpio/gpio-pca953x.c gc->base = chip->gpio_start; base 1015 drivers/gpio/gpio-pca953x.c ret = pdata->setup(client, chip->gpio_chip.base, base 1035 drivers/gpio/gpio-pca953x.c ret = pdata->teardown(client, chip->gpio_chip.base, base 256 drivers/gpio/gpio-pcf857x.c gpio->chip.base = pdata ? pdata->gpio_base : -1; base 377 drivers/gpio/gpio-pcf857x.c gpio->chip.base, gpio->chip.ngpio, base 402 drivers/gpio/gpio-pcf857x.c gpio->chip.base, gpio->chip.ngpio, base 87 drivers/gpio/gpio-pch.c void __iomem *base; base 213 drivers/gpio/gpio-pch.c gpio->base = -1; base 322 drivers/gpio/gpio-pch.c chip->base, handle_simple_irq); base 366 drivers/gpio/gpio-pch.c chip->base = pcim_iomap_table(pdev)[1]; base 375 drivers/gpio/gpio-pch.c chip->reg = chip->base; base 152 drivers/gpio/gpio-pci-idio-16.c void __iomem *base; base 161 drivers/gpio/gpio-pci-idio-16.c base = &idio16gpio->reg->out8_15; base 163 drivers/gpio/gpio-pci-idio-16.c base = &idio16gpio->reg->out0_7; base 168 drivers/gpio/gpio-pci-idio-16.c out_state = ioread8(base) | mask; base 170 drivers/gpio/gpio-pci-idio-16.c out_state = ioread8(base) & ~mask; base 172 drivers/gpio/gpio-pci-idio-16.c iowrite8(out_state, base); base 336 drivers/gpio/gpio-pci-idio-16.c idio16gpio->chip.base = -1; base 257 drivers/gpio/gpio-pcie-idio-24.c void __iomem *base; base 272 drivers/gpio/gpio-pcie-idio-24.c base = &idio24gpio->reg->ttl_out0_7; base 275 drivers/gpio/gpio-pcie-idio-24.c base = &idio24gpio->reg->out16_23; base 277 drivers/gpio/gpio-pcie-idio-24.c base = &idio24gpio->reg->out8_15; base 279 drivers/gpio/gpio-pcie-idio-24.c base = &idio24gpio->reg->out0_7; base 284 drivers/gpio/gpio-pcie-idio-24.c out_state = ioread8(base) | mask; base 286 drivers/gpio/gpio-pcie-idio-24.c out_state = ioread8(base) & ~mask; base 288 drivers/gpio/gpio-pcie-idio-24.c iowrite8(out_state, base); base 508 drivers/gpio/gpio-pcie-idio-24.c idio24gpio->chip.base = -1; base 122 drivers/gpio/gpio-pisosr.c .base = -1, base 52 drivers/gpio/gpio-pl061.c void __iomem *base; base 66 drivers/gpio/gpio-pl061.c return !(readb(pl061->base + GPIODIR) & BIT(offset)); base 76 drivers/gpio/gpio-pl061.c gpiodir = readb(pl061->base + GPIODIR); base 78 drivers/gpio/gpio-pl061.c writeb(gpiodir, pl061->base + GPIODIR); base 92 drivers/gpio/gpio-pl061.c writeb(!!value << offset, pl061->base + (BIT(offset + 2))); base 93 drivers/gpio/gpio-pl061.c gpiodir = readb(pl061->base + GPIODIR); base 95 drivers/gpio/gpio-pl061.c writeb(gpiodir, pl061->base + GPIODIR); base 101 drivers/gpio/gpio-pl061.c writeb(!!value << offset, pl061->base + (BIT(offset + 2))); base 111 drivers/gpio/gpio-pl061.c return !!readb(pl061->base + (BIT(offset + 2))); base 118 drivers/gpio/gpio-pl061.c writeb(!!value << offset, pl061->base + (BIT(offset + 2))); base 146 drivers/gpio/gpio-pl061.c gpioiev = readb(pl061->base + GPIOIEV); base 147 drivers/gpio/gpio-pl061.c gpiois = readb(pl061->base + GPIOIS); base 148 drivers/gpio/gpio-pl061.c gpioibe = readb(pl061->base + GPIOIBE); base 200 drivers/gpio/gpio-pl061.c writeb(gpiois, pl061->base + GPIOIS); base 201 drivers/gpio/gpio-pl061.c writeb(gpioibe, pl061->base + GPIOIBE); base 202 drivers/gpio/gpio-pl061.c writeb(gpioiev, pl061->base + GPIOIEV); base 219 drivers/gpio/gpio-pl061.c pending = readb(pl061->base + GPIOMIS); base 237 drivers/gpio/gpio-pl061.c gpioie = readb(pl061->base + GPIOIE) & ~mask; base 238 drivers/gpio/gpio-pl061.c writeb(gpioie, pl061->base + GPIOIE); base 250 drivers/gpio/gpio-pl061.c gpioie = readb(pl061->base + GPIOIE) | mask; base 251 drivers/gpio/gpio-pl061.c writeb(gpioie, pl061->base + GPIOIE); base 270 drivers/gpio/gpio-pl061.c writeb(mask, pl061->base + GPIOIC); base 293 drivers/gpio/gpio-pl061.c pl061->base = devm_ioremap_resource(dev, &adev->res); base 294 drivers/gpio/gpio-pl061.c if (IS_ERR(pl061->base)) base 295 drivers/gpio/gpio-pl061.c return PTR_ERR(pl061->base); base 303 drivers/gpio/gpio-pl061.c pl061->gc.base = -1; base 324 drivers/gpio/gpio-pl061.c writeb(0, pl061->base + GPIOIE); /* disable irqs */ base 361 drivers/gpio/gpio-pl061.c pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); base 362 drivers/gpio/gpio-pl061.c pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); base 363 drivers/gpio/gpio-pl061.c pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); base 364 drivers/gpio/gpio-pl061.c pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); base 365 drivers/gpio/gpio-pl061.c pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); base 390 drivers/gpio/gpio-pl061.c writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); base 391 drivers/gpio/gpio-pl061.c writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); base 392 drivers/gpio/gpio-pl061.c writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); base 393 drivers/gpio/gpio-pl061.c writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); base 332 drivers/gpio/gpio-pmic-eic-sprd.c pmic_eic->chip.base = -1; base 202 drivers/gpio/gpio-pxa.c void __iomem *base; base 206 drivers/gpio/gpio-pxa.c base = gpio_bank_base(&pchip->chip, gpio); base 207 drivers/gpio/gpio-pxa.c gpdr = readl_relaxed(base + GPDR_OFFSET); base 213 drivers/gpio/gpio-pxa.c gafr = readl_relaxed(base + GAFR_OFFSET); base 262 drivers/gpio/gpio-pxa.c void __iomem *base = gpio_bank_base(chip, offset); base 268 drivers/gpio/gpio-pxa.c ret = pinctrl_gpio_direction_input(chip->base + offset); base 275 drivers/gpio/gpio-pxa.c value = readl_relaxed(base + GPDR_OFFSET); base 276 drivers/gpio/gpio-pxa.c if (__gpio_is_inverted(chip->base + offset)) base 280 drivers/gpio/gpio-pxa.c writel_relaxed(value, base + GPDR_OFFSET); base 289 drivers/gpio/gpio-pxa.c void __iomem *base = gpio_bank_base(chip, offset); base 294 drivers/gpio/gpio-pxa.c writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); base 297 drivers/gpio/gpio-pxa.c ret = pinctrl_gpio_direction_output(chip->base + offset); base 304 drivers/gpio/gpio-pxa.c tmp = readl_relaxed(base + GPDR_OFFSET); base 305 drivers/gpio/gpio-pxa.c if (__gpio_is_inverted(chip->base + offset)) base 309 drivers/gpio/gpio-pxa.c writel_relaxed(tmp, base + GPDR_OFFSET); base 317 drivers/gpio/gpio-pxa.c void __iomem *base = gpio_bank_base(chip, offset); base 318 drivers/gpio/gpio-pxa.c u32 gplr = readl_relaxed(base + GPLR_OFFSET); base 325 drivers/gpio/gpio-pxa.c void __iomem *base = gpio_bank_base(chip, offset); base 328 drivers/gpio/gpio-pxa.c base + (value ? GPSR_OFFSET : GPCR_OFFSET)); base 491 drivers/gpio/gpio-pxa.c void __iomem *base = gpio_bank_base(&pchip->chip, gpio); base 493 drivers/gpio/gpio-pxa.c writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET); base 501 drivers/gpio/gpio-pxa.c void __iomem *base = gpio_bank_base(&pchip->chip, gpio); base 506 drivers/gpio/gpio-pxa.c grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio); base 507 drivers/gpio/gpio-pxa.c gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio); base 508 drivers/gpio/gpio-pxa.c writel_relaxed(grer, base + GRER_OFFSET); base 509 drivers/gpio/gpio-pxa.c writel_relaxed(gfer, base + GFER_OFFSET); base 222 drivers/gpio/gpio-raspberrypi-exp.c rpi_gpio->gc.base = -1; base 118 drivers/gpio/gpio-rc5t583.c rc5t583_gpio->gpio_chip.base = -1; base 122 drivers/gpio/gpio-rc5t583.c rc5t583_gpio->gpio_chip.base = pdata->gpio_base; base 36 drivers/gpio/gpio-rcar.c void __iomem *base; base 66 drivers/gpio/gpio-rcar.c return ioread32(p->base + offs); base 72 drivers/gpio/gpio-rcar.c iowrite32(value, p->base + offs); base 256 drivers/gpio/gpio-rcar.c error = pinctrl_gpio_request(chip->base + offset); base 267 drivers/gpio/gpio-rcar.c pinctrl_gpio_free(chip->base + offset); base 464 drivers/gpio/gpio-rcar.c p->base = devm_platform_ioremap_resource(pdev, 0); base 465 drivers/gpio/gpio-rcar.c if (IS_ERR(p->base)) { base 466 drivers/gpio/gpio-rcar.c ret = PTR_ERR(p->base); base 482 drivers/gpio/gpio-rcar.c gpio_chip->base = -1; base 161 drivers/gpio/gpio-rdc321x.c rdc321x_gpio_dev->chip.base = 0; base 131 drivers/gpio/gpio-reg.c int base, int num, const char *label, u32 direction, u32 def_out, base 156 drivers/gpio/gpio-reg.c r->gc.base = base; base 98 drivers/gpio/gpio-sa1100.c .base = 0, base 112 drivers/gpio/gpio-sa1100.c void *base = sgc->membase; base 118 drivers/gpio/gpio-sa1100.c writel_relaxed(grer, base + R_GRER); base 119 drivers/gpio/gpio-sa1100.c writel_relaxed(gfer, base + R_GFER); base 201 drivers/gpio/gpio-sama5d2-piobu.c piobu->chip.base = -1, base 32 drivers/gpio/gpio-sch.c unsigned base = 0; base 36 drivers/gpio/gpio-sch.c base += 0x20; base 39 drivers/gpio/gpio-sch.c return base + reg + gpio / 8; base 54 drivers/gpio/gpio-sch311x.c unsigned short base; base 63 drivers/gpio/gpio-sch311x.c .base = 10, base 68 drivers/gpio/gpio-sch311x.c .base = 20, base 73 drivers/gpio/gpio-sch311x.c .base = 30, base 78 drivers/gpio/gpio-sch311x.c .base = 40, base 83 drivers/gpio/gpio-sch311x.c .base = 50, base 88 drivers/gpio/gpio-sch311x.c .base = 60, base 300 drivers/gpio/gpio-sch311x.c block->chip.base = sch311x_gpio_blocks[i].base; base 227 drivers/gpio/gpio-siox.c ddata->gchip.base = -1; base 46 drivers/gpio/gpio-spear-spics.c void __iomem *base; base 69 drivers/gpio/gpio-spear-spics.c tmp = readl_relaxed(spics->base + spics->perip_cfg); base 79 drivers/gpio/gpio-spear-spics.c writel_relaxed(tmp, spics->base + spics->perip_cfg); base 100 drivers/gpio/gpio-spear-spics.c tmp = readl_relaxed(spics->base + spics->perip_cfg); base 103 drivers/gpio/gpio-spear-spics.c writel_relaxed(tmp, spics->base + spics->perip_cfg); base 115 drivers/gpio/gpio-spear-spics.c tmp = readl_relaxed(spics->base + spics->perip_cfg); base 117 drivers/gpio/gpio-spear-spics.c writel_relaxed(tmp, spics->base + spics->perip_cfg); base 131 drivers/gpio/gpio-spear-spics.c spics->base = devm_platform_ioremap_resource(pdev, 0); base 132 drivers/gpio/gpio-spear-spics.c if (IS_ERR(spics->base)) base 133 drivers/gpio/gpio-spear-spics.c return PTR_ERR(spics->base); base 154 drivers/gpio/gpio-spear-spics.c spics->chip.base = -1; base 37 drivers/gpio/gpio-sprd.c void __iomem *base; base 45 drivers/gpio/gpio-sprd.c return sprd_gpio->base + SPRD_GPIO_BANK_SIZE * bank; base 52 drivers/gpio/gpio-sprd.c void __iomem *base = sprd_gpio_bank_base(sprd_gpio, base 58 drivers/gpio/gpio-sprd.c tmp = readl_relaxed(base + reg); base 65 drivers/gpio/gpio-sprd.c writel_relaxed(tmp, base + reg); base 72 drivers/gpio/gpio-sprd.c void __iomem *base = sprd_gpio_bank_base(sprd_gpio, base 75 drivers/gpio/gpio-sprd.c return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset))); base 194 drivers/gpio/gpio-sprd.c void __iomem *base = sprd_gpio_bank_base(sprd_gpio, bank); base 195 drivers/gpio/gpio-sprd.c unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) & base 232 drivers/gpio/gpio-sprd.c sprd_gpio->base = devm_platform_ioremap_resource(pdev, 0); base 233 drivers/gpio/gpio-sprd.c if (IS_ERR(sprd_gpio->base)) base 234 drivers/gpio/gpio-sprd.c return PTR_ERR(sprd_gpio->base); base 240 drivers/gpio/gpio-sprd.c sprd_gpio->chip.base = -1; base 125 drivers/gpio/gpio-sta2x11.c gpio->base = gpio_base; base 284 drivers/gpio/gpio-sta2x11.c int i, nr, base; base 289 drivers/gpio/gpio-sta2x11.c base = chip->irq_base + i * GSTA_GPIO_PER_BLOCK; base 292 drivers/gpio/gpio-sta2x11.c irq = base + nr; base 349 drivers/gpio/gpio-stmpe.c unsigned gpio = gc->base; base 473 drivers/gpio/gpio-stmpe.c stmpe_gpio->chip.base = -1; base 224 drivers/gpio/gpio-stp-xway.c chip->gc.base = -1; base 253 drivers/gpio/gpio-syscon.c priv->chip.base = -1; base 42 drivers/gpio/gpio-tb10x.c void __iomem *base; base 50 drivers/gpio/gpio-tb10x.c return ioread32(gpio->base + offs); base 56 drivers/gpio/gpio-tb10x.c iowrite32(val, gpio->base + offs); base 126 drivers/gpio/gpio-tb10x.c tb10x_gpio->base = devm_platform_ioremap_resource(pdev, 0); base 127 drivers/gpio/gpio-tb10x.c if (IS_ERR(tb10x_gpio->base)) base 128 drivers/gpio/gpio-tb10x.c return PTR_ERR(tb10x_gpio->base); base 141 drivers/gpio/gpio-tb10x.c tb10x_gpio->base + OFFSET_TO_REG_DATA, base 144 drivers/gpio/gpio-tb10x.c tb10x_gpio->base + OFFSET_TO_REG_DDR, base 151 drivers/gpio/gpio-tb10x.c tb10x_gpio->gc.base = -1; base 201 drivers/gpio/gpio-tb10x.c gc->reg_base = tb10x_gpio->base; base 314 drivers/gpio/gpio-tc3589x.c tc3589x_gpio->chip.base = -1; base 136 drivers/gpio/gpio-tegra.c return pinctrl_gpio_request(chip->base + offset); base 143 drivers/gpio/gpio-tegra.c pinctrl_gpio_free(chip->base + offset); base 176 drivers/gpio/gpio-tegra.c ret = pinctrl_gpio_direction_input(chip->base + offset); base 180 drivers/gpio/gpio-tegra.c chip->base + offset, ret); base 196 drivers/gpio/gpio-tegra.c ret = pinctrl_gpio_direction_output(chip->base + offset); base 200 drivers/gpio/gpio-tegra.c chip->base + offset, ret); base 595 drivers/gpio/gpio-tegra.c tgi->gc.base = 0; base 66 drivers/gpio/gpio-tegra186.c void __iomem *base; base 97 drivers/gpio/gpio-tegra186.c return gpio->base + port->offset + pin * 0x20; base 104 drivers/gpio/gpio-tegra186.c void __iomem *base; base 107 drivers/gpio/gpio-tegra186.c base = tegra186_gpio_get_base(gpio, offset); base 108 drivers/gpio/gpio-tegra186.c if (WARN_ON(base == NULL)) base 111 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); base 122 drivers/gpio/gpio-tegra186.c void __iomem *base; base 125 drivers/gpio/gpio-tegra186.c base = tegra186_gpio_get_base(gpio, offset); base 126 drivers/gpio/gpio-tegra186.c if (WARN_ON(base == NULL)) base 129 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); base 131 drivers/gpio/gpio-tegra186.c writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); base 133 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); base 136 drivers/gpio/gpio-tegra186.c writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); base 145 drivers/gpio/gpio-tegra186.c void __iomem *base; base 151 drivers/gpio/gpio-tegra186.c base = tegra186_gpio_get_base(gpio, offset); base 152 drivers/gpio/gpio-tegra186.c if (WARN_ON(base == NULL)) base 156 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); base 158 drivers/gpio/gpio-tegra186.c writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); base 160 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); base 163 drivers/gpio/gpio-tegra186.c writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); base 171 drivers/gpio/gpio-tegra186.c void __iomem *base; base 174 drivers/gpio/gpio-tegra186.c base = tegra186_gpio_get_base(gpio, offset); base 175 drivers/gpio/gpio-tegra186.c if (WARN_ON(base == NULL)) base 178 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); base 180 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); base 182 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_INPUT); base 191 drivers/gpio/gpio-tegra186.c void __iomem *base; base 194 drivers/gpio/gpio-tegra186.c base = tegra186_gpio_get_base(gpio, offset); base 195 drivers/gpio/gpio-tegra186.c if (WARN_ON(base == NULL)) base 198 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); base 204 drivers/gpio/gpio-tegra186.c writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); base 240 drivers/gpio/gpio-tegra186.c void __iomem *base; base 242 drivers/gpio/gpio-tegra186.c base = tegra186_gpio_get_base(gpio, data->hwirq); base 243 drivers/gpio/gpio-tegra186.c if (WARN_ON(base == NULL)) base 246 drivers/gpio/gpio-tegra186.c writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); base 252 drivers/gpio/gpio-tegra186.c void __iomem *base; base 255 drivers/gpio/gpio-tegra186.c base = tegra186_gpio_get_base(gpio, data->hwirq); base 256 drivers/gpio/gpio-tegra186.c if (WARN_ON(base == NULL)) base 259 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); base 261 drivers/gpio/gpio-tegra186.c writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); base 267 drivers/gpio/gpio-tegra186.c void __iomem *base; base 270 drivers/gpio/gpio-tegra186.c base = tegra186_gpio_get_base(gpio, data->hwirq); base 271 drivers/gpio/gpio-tegra186.c if (WARN_ON(base == NULL)) base 274 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); base 276 drivers/gpio/gpio-tegra186.c writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); base 282 drivers/gpio/gpio-tegra186.c void __iomem *base; base 285 drivers/gpio/gpio-tegra186.c base = tegra186_gpio_get_base(gpio, data->hwirq); base 286 drivers/gpio/gpio-tegra186.c if (WARN_ON(base == NULL)) base 289 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); base 323 drivers/gpio/gpio-tegra186.c writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); base 345 drivers/gpio/gpio-tegra186.c void __iomem *base = gpio->base + port->offset; base 353 drivers/gpio/gpio-tegra186.c value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); base 421 drivers/gpio/gpio-tegra186.c gpio->base = devm_ioremap_resource(&pdev->dev, res); base 422 drivers/gpio/gpio-tegra186.c if (IS_ERR(gpio->base)) base 423 drivers/gpio/gpio-tegra186.c return PTR_ERR(gpio->base); base 453 drivers/gpio/gpio-tegra186.c gpio->gpio.base = -1; base 529 drivers/gpio/gpio-tegra186.c #define TEGRA186_MAIN_GPIO_PORT(port, base, count, controller) \ base 532 drivers/gpio/gpio-tegra186.c .offset = base, \ base 569 drivers/gpio/gpio-tegra186.c #define TEGRA186_AON_GPIO_PORT(port, base, count, controller) \ base 572 drivers/gpio/gpio-tegra186.c .offset = base, \ base 594 drivers/gpio/gpio-tegra186.c #define TEGRA194_MAIN_GPIO_PORT(port, base, count, controller) \ base 597 drivers/gpio/gpio-tegra186.c .offset = base, \ base 639 drivers/gpio/gpio-tegra186.c #define TEGRA194_AON_GPIO_PORT(port, base, count, controller) \ base 642 drivers/gpio/gpio-tegra186.c .offset = base, \ base 567 drivers/gpio/gpio-thunderx.c chip->base = -1; /* System allocated */ base 583 drivers/gpio/gpio-thunderx.c ngpio, chip->base); base 251 drivers/gpio/gpio-timberdale.c gc->base = pdata->gpio_base; base 98 drivers/gpio/gpio-tpic2810.c .base = -1, base 75 drivers/gpio/gpio-tps65086.c .base = -1, base 183 drivers/gpio/gpio-tps65218.c .base = -1, base 105 drivers/gpio/gpio-tps6586x.c tps6586x_gpio->gpio_chip.base = pdata->gpio_base; base 107 drivers/gpio/gpio-tps6586x.c tps6586x_gpio->gpio_chip.base = -1; base 144 drivers/gpio/gpio-tps65910.c tps65910_gpio->gpio_chip.base = pdata->gpio_base; base 146 drivers/gpio/gpio-tps65910.c tps65910_gpio->gpio_chip.base = -1; base 93 drivers/gpio/gpio-tps65912.c .base = -1, base 146 drivers/gpio/gpio-tps68470.c tps68470_gpio->gc.base = -1; base 267 drivers/gpio/gpio-tqmx86.c chip->base = -1; base 112 drivers/gpio/gpio-ts4900.c .base = -1, base 346 drivers/gpio/gpio-ts5500.c priv->gpio_chip.base = -1; base 142 drivers/gpio/gpio-twl4030.c u8 base = REG_GPIODATADIR1 + d_bnk; base 145 drivers/gpio/gpio-twl4030.c ret = gpio_twl4030_read(base); base 152 drivers/gpio/gpio-twl4030.c ret = gpio_twl4030_write(base, reg); base 161 drivers/gpio/gpio-twl4030.c u8 base = REG_GPIODATADIR1 + d_bnk; base 164 drivers/gpio/gpio-twl4030.c ret = gpio_twl4030_read(base); base 178 drivers/gpio/gpio-twl4030.c u8 base = 0; base 181 drivers/gpio/gpio-twl4030.c base = REG_SETGPIODATAOUT1 + d_bnk; base 183 drivers/gpio/gpio-twl4030.c base = REG_CLEARGPIODATAOUT1 + d_bnk; base 185 drivers/gpio/gpio-twl4030.c return gpio_twl4030_write(base, d_msk); base 192 drivers/gpio/gpio-twl4030.c u8 base = 0; base 195 drivers/gpio/gpio-twl4030.c base = REG_GPIODATAIN1 + d_bnk; base 196 drivers/gpio/gpio-twl4030.c ret = gpio_twl4030_read(base); base 533 drivers/gpio/gpio-twl4030.c priv->gpio_chip.base = -1; base 583 drivers/gpio/gpio-twl4030.c status = pdata->setup(&pdev->dev, priv->gpio_chip.base, base 601 drivers/gpio/gpio-twl4030.c status = pdata->teardown(&pdev->dev, priv->gpio_chip.base, base 84 drivers/gpio/gpio-twl6040.c twl6040gpo_chip.base = -1; base 56 drivers/gpio/gpio-ucb1400.c ucb->gc.base = ucb->gpio_offset; base 227 drivers/gpio/gpio-uniphier.c u32 base, parent_base, size; base 237 drivers/gpio/gpio-uniphier.c base = be32_to_cpu(*range++); base 241 drivers/gpio/gpio-uniphier.c if (base <= hwirq && hwirq < base + size) base 242 drivers/gpio/gpio-uniphier.c return hwirq - base + parent_base; base 390 drivers/gpio/gpio-uniphier.c chip->base = -1; base 33 drivers/gpio/gpio-vf610.c void __iomem *base; base 120 drivers/gpio/gpio-vf610.c return pinctrl_gpio_direction_input(chip->base + gpio); base 134 drivers/gpio/gpio-vf610.c return pinctrl_gpio_direction_output(chip->base + gpio); base 147 drivers/gpio/gpio-vf610.c irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); base 150 drivers/gpio/gpio-vf610.c vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); base 164 drivers/gpio/gpio-vf610.c vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); base 207 drivers/gpio/gpio-vf610.c void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); base 216 drivers/gpio/gpio-vf610.c void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); base 256 drivers/gpio/gpio-vf610.c port->base = devm_platform_ioremap_resource(pdev, 0); base 257 drivers/gpio/gpio-vf610.c if (IS_ERR(port->base)) base 258 drivers/gpio/gpio-vf610.c return PTR_ERR(port->base); base 305 drivers/gpio/gpio-vf610.c gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT; base 324 drivers/gpio/gpio-vf610.c vf610_gpio_writel(0, port->base + PORT_PCR(i)); base 327 drivers/gpio/gpio-vf610.c vf610_gpio_writel(~0, port->base + PORT_ISFR); base 400 drivers/gpio/gpio-viperboard.c vb_gpio->gpioa.base = -1; base 417 drivers/gpio/gpio-viperboard.c vb_gpio->gpiob.base = -1; base 221 drivers/gpio/gpio-vx855.c c->base = 0; base 434 drivers/gpio/gpio-wcove.c wg->chip.base = -1; base 131 drivers/gpio/gpio-winbond.c unsigned long base; base 142 drivers/gpio/gpio-winbond.c static int winbond_sio_enter(unsigned long base) base 144 drivers/gpio/gpio-winbond.c if (!request_muxed_region(base, 2, WB_GPIO_DRIVER_NAME)) base 151 drivers/gpio/gpio-winbond.c outb(WB_SIO_EXT_ENTER_KEY, base); base 152 drivers/gpio/gpio-winbond.c outb(WB_SIO_EXT_ENTER_KEY, base); base 157 drivers/gpio/gpio-winbond.c static void winbond_sio_select_logical(unsigned long base, u8 dev) base 159 drivers/gpio/gpio-winbond.c outb(WB_SIO_REG_LOGICAL, base); base 160 drivers/gpio/gpio-winbond.c outb(dev, base + 1); base 163 drivers/gpio/gpio-winbond.c static void winbond_sio_leave(unsigned long base) base 165 drivers/gpio/gpio-winbond.c outb(WB_SIO_EXT_EXIT_KEY, base); base 167 drivers/gpio/gpio-winbond.c release_region(base, 2); base 170 drivers/gpio/gpio-winbond.c static void winbond_sio_reg_write(unsigned long base, u8 reg, u8 data) base 172 drivers/gpio/gpio-winbond.c outb(reg, base); base 173 drivers/gpio/gpio-winbond.c outb(data, base + 1); base 176 drivers/gpio/gpio-winbond.c static u8 winbond_sio_reg_read(unsigned long base, u8 reg) base 178 drivers/gpio/gpio-winbond.c outb(reg, base); base 179 drivers/gpio/gpio-winbond.c return inb(base + 1); base 182 drivers/gpio/gpio-winbond.c static void winbond_sio_reg_bset(unsigned long base, u8 reg, u8 bit) base 186 drivers/gpio/gpio-winbond.c val = winbond_sio_reg_read(base, reg); base 188 drivers/gpio/gpio-winbond.c winbond_sio_reg_write(base, reg, val); base 191 drivers/gpio/gpio-winbond.c static void winbond_sio_reg_bclear(unsigned long base, u8 reg, u8 bit) base 195 drivers/gpio/gpio-winbond.c val = winbond_sio_reg_read(base, reg); base 197 drivers/gpio/gpio-winbond.c winbond_sio_reg_write(base, reg, val); base 200 drivers/gpio/gpio-winbond.c static bool winbond_sio_reg_btest(unsigned long base, u8 reg, u8 bit) base 202 drivers/gpio/gpio-winbond.c return winbond_sio_reg_read(base, reg) & BIT(bit); base 385 drivers/gpio/gpio-winbond.c unsigned long *base = gpiochip_get_data(gc); base 391 drivers/gpio/gpio-winbond.c val = winbond_sio_enter(*base); base 395 drivers/gpio/gpio-winbond.c winbond_sio_select_logical(*base, info->dev); base 397 drivers/gpio/gpio-winbond.c val = winbond_sio_reg_btest(*base, info->datareg, offset); base 398 drivers/gpio/gpio-winbond.c if (winbond_sio_reg_btest(*base, info->invreg, offset)) base 401 drivers/gpio/gpio-winbond.c winbond_sio_leave(*base); base 408 drivers/gpio/gpio-winbond.c unsigned long *base = gpiochip_get_data(gc); base 415 drivers/gpio/gpio-winbond.c ret = winbond_sio_enter(*base); base 419 drivers/gpio/gpio-winbond.c winbond_sio_select_logical(*base, info->dev); base 421 drivers/gpio/gpio-winbond.c winbond_sio_reg_bset(*base, info->ioreg, offset); base 423 drivers/gpio/gpio-winbond.c winbond_sio_leave(*base); base 432 drivers/gpio/gpio-winbond.c unsigned long *base = gpiochip_get_data(gc); base 439 drivers/gpio/gpio-winbond.c ret = winbond_sio_enter(*base); base 443 drivers/gpio/gpio-winbond.c winbond_sio_select_logical(*base, info->dev); base 445 drivers/gpio/gpio-winbond.c winbond_sio_reg_bclear(*base, info->ioreg, offset); base 447 drivers/gpio/gpio-winbond.c if (winbond_sio_reg_btest(*base, info->invreg, offset)) base 451 drivers/gpio/gpio-winbond.c winbond_sio_reg_bset(*base, info->datareg, offset); base 453 drivers/gpio/gpio-winbond.c winbond_sio_reg_bclear(*base, info->datareg, offset); base 455 drivers/gpio/gpio-winbond.c winbond_sio_leave(*base); base 463 drivers/gpio/gpio-winbond.c unsigned long *base = gpiochip_get_data(gc); base 469 drivers/gpio/gpio-winbond.c if (winbond_sio_enter(*base) != 0) base 472 drivers/gpio/gpio-winbond.c winbond_sio_select_logical(*base, info->dev); base 474 drivers/gpio/gpio-winbond.c if (winbond_sio_reg_btest(*base, info->invreg, offset)) base 478 drivers/gpio/gpio-winbond.c winbond_sio_reg_bset(*base, info->datareg, offset); base 480 drivers/gpio/gpio-winbond.c winbond_sio_reg_bclear(*base, info->datareg, offset); base 482 drivers/gpio/gpio-winbond.c winbond_sio_leave(*base); base 486 drivers/gpio/gpio-winbond.c .base = -1, base 496 drivers/gpio/gpio-winbond.c static void winbond_gpio_configure_port0_pins(unsigned long base) base 500 drivers/gpio/gpio-winbond.c val = winbond_sio_reg_read(base, WB_SIO_REG_GPIO1_MF); base 510 drivers/gpio/gpio-winbond.c winbond_sio_reg_write(base, WB_SIO_REG_GPIO1_MF, val); base 513 drivers/gpio/gpio-winbond.c static void winbond_gpio_configure_port1_check_i2c(unsigned long base) base 515 drivers/gpio/gpio-winbond.c params.i2cgpio = !winbond_sio_reg_btest(base, WB_SIO_REG_I2C_PS, base 521 drivers/gpio/gpio-winbond.c static bool winbond_gpio_configure_port(unsigned long base, unsigned int idx) base 529 drivers/gpio/gpio-winbond.c winbond_sio_select_logical(base, conflict->dev); base 531 drivers/gpio/gpio-winbond.c if (winbond_sio_reg_btest(base, conflict->testreg, base 546 drivers/gpio/gpio-winbond.c winbond_gpio_configure_port0_pins(base); base 548 drivers/gpio/gpio-winbond.c winbond_gpio_configure_port1_check_i2c(base); base 550 drivers/gpio/gpio-winbond.c winbond_sio_select_logical(base, info->dev); base 552 drivers/gpio/gpio-winbond.c winbond_sio_reg_bset(base, info->enablereg, info->enablebit); base 555 drivers/gpio/gpio-winbond.c winbond_sio_reg_bset(base, info->outputreg, base 558 drivers/gpio/gpio-winbond.c winbond_sio_reg_bclear(base, info->outputreg, base 562 drivers/gpio/gpio-winbond.c winbond_sio_reg_btest(base, info->outputreg, base 570 drivers/gpio/gpio-winbond.c static int winbond_gpio_configure(unsigned long base) base 575 drivers/gpio/gpio-winbond.c if (!winbond_gpio_configure_port(base, i)) base 586 drivers/gpio/gpio-winbond.c static int winbond_gpio_check_chip(unsigned long base) base 591 drivers/gpio/gpio-winbond.c ret = winbond_sio_enter(base); base 595 drivers/gpio/gpio-winbond.c chip = winbond_sio_reg_read(base, WB_SIO_REG_CHIP_MSB) << 8; base 596 drivers/gpio/gpio-winbond.c chip |= winbond_sio_reg_read(base, WB_SIO_REG_CHIP_LSB); base 598 drivers/gpio/gpio-winbond.c pr_notice("chip ID at %lx is %.4x\n", base, chip); base 606 drivers/gpio/gpio-winbond.c winbond_sio_leave(base); base 629 drivers/gpio/gpio-winbond.c if (params.base != 0) base 630 drivers/gpio/gpio-winbond.c return winbond_gpio_check_chip(params.base) == 0; base 636 drivers/gpio/gpio-winbond.c params.base = WB_SIO_BASE; base 637 drivers/gpio/gpio-winbond.c ret = winbond_gpio_check_chip(params.base); base 643 drivers/gpio/gpio-winbond.c params.base = WB_SIO_BASE_HIGH; base 644 drivers/gpio/gpio-winbond.c return winbond_gpio_check_chip(params.base) == 0; base 651 drivers/gpio/gpio-winbond.c if (params.base == 0) base 654 drivers/gpio/gpio-winbond.c ret = winbond_sio_enter(params.base); base 658 drivers/gpio/gpio-winbond.c ret = winbond_gpio_configure(params.base); base 660 drivers/gpio/gpio-winbond.c winbond_sio_leave(params.base); base 681 drivers/gpio/gpio-winbond.c return devm_gpiochip_add_data(dev, &winbond_gpio_chip, ¶ms.base); base 694 drivers/gpio/gpio-winbond.c module_param_named(base, params.base, ulong, 0444); base 695 drivers/gpio/gpio-winbond.c MODULE_PARM_DESC(base, base 161 drivers/gpio/gpio-wm831x.c int gpio = i + chip->base; base 276 drivers/gpio/gpio-wm831x.c wm831x_gpio->gpio_chip.base = pdata->gpio_base; base 278 drivers/gpio/gpio-wm831x.c wm831x_gpio->gpio_chip.base = -1; base 120 drivers/gpio/gpio-wm8350.c wm8350_gpio->gpio_chip.base = pdata->gpio_base; base 122 drivers/gpio/gpio-wm8350.c wm8350_gpio->gpio_chip.base = -1; base 194 drivers/gpio/gpio-wm8994.c int gpio = i + chip->base; base 278 drivers/gpio/gpio-wm8994.c wm8994_gpio->gpio_chip.base = pdata->gpio_base; base 280 drivers/gpio/gpio-wm8994.c wm8994_gpio->gpio_chip.base = -1; base 24 drivers/gpio/gpio-ws16c48.c static unsigned int base[MAX_NUM_WS16C48]; base 26 drivers/gpio/gpio-ws16c48.c module_param_hw_array(base, uint, ioport, &num_ws16c48, 0); base 27 drivers/gpio/gpio-ws16c48.c MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses"); base 50 drivers/gpio/gpio-ws16c48.c unsigned base; base 73 drivers/gpio/gpio-ws16c48.c outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); base 95 drivers/gpio/gpio-ws16c48.c outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); base 118 drivers/gpio/gpio-ws16c48.c port_state = inb(ws16c48gpio->base + port); base 161 drivers/gpio/gpio-ws16c48.c port_state = inb(ws16c48gpio->base + i); base 189 drivers/gpio/gpio-ws16c48.c outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); base 224 drivers/gpio/gpio-ws16c48.c outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); base 252 drivers/gpio/gpio-ws16c48.c outb(0x80, ws16c48gpio->base + 7); base 253 drivers/gpio/gpio-ws16c48.c outb(port_state & ~mask, ws16c48gpio->base + 8 + port); base 254 drivers/gpio/gpio-ws16c48.c outb(port_state | mask, ws16c48gpio->base + 8 + port); base 255 drivers/gpio/gpio-ws16c48.c outb(0xC0, ws16c48gpio->base + 7); base 277 drivers/gpio/gpio-ws16c48.c outb(0x80, ws16c48gpio->base + 7); base 278 drivers/gpio/gpio-ws16c48.c outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); base 279 drivers/gpio/gpio-ws16c48.c outb(0xC0, ws16c48gpio->base + 7); base 301 drivers/gpio/gpio-ws16c48.c outb(0x80, ws16c48gpio->base + 7); base 302 drivers/gpio/gpio-ws16c48.c outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); base 303 drivers/gpio/gpio-ws16c48.c outb(0xC0, ws16c48gpio->base + 7); base 337 drivers/gpio/gpio-ws16c48.c outb(0x40, ws16c48gpio->base + 7); base 338 drivers/gpio/gpio-ws16c48.c outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port); base 339 drivers/gpio/gpio-ws16c48.c outb(0xC0, ws16c48gpio->base + 7); base 363 drivers/gpio/gpio-ws16c48.c int_pending = inb(ws16c48gpio->base + 6) & 0x7; base 370 drivers/gpio/gpio-ws16c48.c int_id = inb(ws16c48gpio->base + 8 + port); base 376 drivers/gpio/gpio-ws16c48.c int_pending = inb(ws16c48gpio->base + 6) & 0x7; base 408 drivers/gpio/gpio-ws16c48.c if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) { base 410 drivers/gpio/gpio-ws16c48.c base[id], base[id] + WS16C48_EXTENT); base 417 drivers/gpio/gpio-ws16c48.c ws16c48gpio->chip.base = -1; base 427 drivers/gpio/gpio-ws16c48.c ws16c48gpio->base = base[id]; base 438 drivers/gpio/gpio-ws16c48.c outb(0x80, base[id] + 7); base 439 drivers/gpio/gpio-ws16c48.c outb(0, base[id] + 8); base 440 drivers/gpio/gpio-ws16c48.c outb(0, base[id] + 9); base 441 drivers/gpio/gpio-ws16c48.c outb(0, base[id] + 10); base 442 drivers/gpio/gpio-ws16c48.c outb(0xC0, base[id] + 7); base 32 drivers/gpio/gpio-xgene.c void __iomem *base; base 45 drivers/gpio/gpio-xgene.c return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); base 57 drivers/gpio/gpio-xgene.c setval = ioread32(chip->base + bank_offset); base 62 drivers/gpio/gpio-xgene.c iowrite32(setval, chip->base + bank_offset); base 83 drivers/gpio/gpio-xgene.c return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); base 97 drivers/gpio/gpio-xgene.c dirval = ioread32(chip->base + bank_offset); base 99 drivers/gpio/gpio-xgene.c iowrite32(dirval, chip->base + bank_offset); base 118 drivers/gpio/gpio-xgene.c dirval = ioread32(chip->base + bank_offset); base 120 drivers/gpio/gpio-xgene.c iowrite32(dirval, chip->base + bank_offset); base 136 drivers/gpio/gpio-xgene.c gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset); base 149 drivers/gpio/gpio-xgene.c iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset); base 174 drivers/gpio/gpio-xgene.c gpio->base = devm_ioremap_nocache(&pdev->dev, res->start, base 176 drivers/gpio/gpio-xgene.c if (!gpio->base) { base 191 drivers/gpio/gpio-xgene.c gpio->chip.base = -1; base 320 drivers/gpio/gpio-xilinx.c chip->gc.base = -1; base 375 drivers/gpio/gpio-xlp.c gc->base = 0; base 143 drivers/gpio/gpio-xra1403.c chip->base + i, label, base 178 drivers/gpio/gpio-xra1403.c xra->chip.base = -1; base 127 drivers/gpio/gpio-xtensa.c .base = -1, base 136 drivers/gpio/gpio-xtensa.c .base = -1, base 162 drivers/gpio/gpio-zevio.c .base = 0, base 43 drivers/gpio/gpio-zx.c void __iomem *base; base 57 drivers/gpio/gpio-zx.c gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); base 59 drivers/gpio/gpio-zx.c writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); base 76 drivers/gpio/gpio-zx.c gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); base 78 drivers/gpio/gpio-zx.c writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); base 81 drivers/gpio/gpio-zx.c writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1); base 83 drivers/gpio/gpio-zx.c writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0); base 93 drivers/gpio/gpio-zx.c return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset)); base 101 drivers/gpio/gpio-zx.c writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1); base 103 drivers/gpio/gpio-zx.c writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0); base 120 drivers/gpio/gpio-zx.c gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV); base 121 drivers/gpio/gpio-zx.c gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE); base 122 drivers/gpio/gpio-zx.c gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP); base 123 drivers/gpio/gpio-zx.c gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN); base 147 drivers/gpio/gpio-zx.c writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE); base 148 drivers/gpio/gpio-zx.c writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP); base 149 drivers/gpio/gpio-zx.c writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN); base 150 drivers/gpio/gpio-zx.c writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV); base 166 drivers/gpio/gpio-zx.c pending = readw_relaxed(chip->base + ZX_GPIO_MIS); base 167 drivers/gpio/gpio-zx.c writew_relaxed(pending, chip->base + ZX_GPIO_IC); base 185 drivers/gpio/gpio-zx.c gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask; base 186 drivers/gpio/gpio-zx.c writew_relaxed(gpioie, chip->base + ZX_GPIO_IM); base 187 drivers/gpio/gpio-zx.c gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask; base 188 drivers/gpio/gpio-zx.c writew_relaxed(gpioie, chip->base + ZX_GPIO_IE); base 200 drivers/gpio/gpio-zx.c gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask; base 201 drivers/gpio/gpio-zx.c writew_relaxed(gpioie, chip->base + ZX_GPIO_IM); base 202 drivers/gpio/gpio-zx.c gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask; base 203 drivers/gpio/gpio-zx.c writew_relaxed(gpioie, chip->base + ZX_GPIO_IE); base 225 drivers/gpio/gpio-zx.c chip->base = devm_platform_ioremap_resource(pdev, 0); base 226 drivers/gpio/gpio-zx.c if (IS_ERR(chip->base)) base 227 drivers/gpio/gpio-zx.c return PTR_ERR(chip->base); base 240 drivers/gpio/gpio-zx.c chip->gc.base = ZX_GPIO_NR * id; base 249 drivers/gpio/gpio-zx.c writew_relaxed(0xffff, chip->base + ZX_GPIO_IM); base 250 drivers/gpio/gpio-zx.c writew_relaxed(0, chip->base + ZX_GPIO_IE); base 870 drivers/gpio/gpio-zynq.c chip->base = of_alias_get_id(pdev->dev.of_node, "gpio"); base 732 drivers/gpio/gpiolib-of.c gc->base = -1; base 417 drivers/gpio/gpiolib-sysfs.c return sprintf(buf, "%d\n", chip->base); base 419 drivers/gpio/gpiolib-sysfs.c static DEVICE_ATTR_RO(base); base 768 drivers/gpio/gpiolib-sysfs.c "gpiochip%d", chip->base); base 116 drivers/gpio/gpiolib.c if (gdev->base <= gpio && base 117 drivers/gpio/gpiolib.c gdev->base + gdev->ngpio > gpio) { base 119 drivers/gpio/gpiolib.c return &gdev->descs[gpio - gdev->base]; base 165 drivers/gpio/gpiolib.c return desc->gdev->base + (desc - &desc->gdev->descs[0]); base 186 drivers/gpio/gpiolib.c int base = ARCH_NR_GPIOS - ngpio; base 190 drivers/gpio/gpiolib.c if (gdev->base + gdev->ngpio <= base) base 194 drivers/gpio/gpiolib.c base = gdev->base - ngpio; base 197 drivers/gpio/gpiolib.c if (gpio_is_valid(base)) { base 198 drivers/gpio/gpiolib.c pr_debug("%s: found new base at %d\n", __func__, base); base 199 drivers/gpio/gpiolib.c return base; base 266 drivers/gpio/gpiolib.c if (gdev->base + gdev->ngpio <= next->base) { base 273 drivers/gpio/gpiolib.c if (prev->base + prev->ngpio <= gdev->base) { base 285 drivers/gpio/gpiolib.c if (prev->base + prev->ngpio <= gdev->base base 286 drivers/gpio/gpiolib.c && gdev->base + gdev->ngpio <= next->base) { base 1097 drivers/gpio/gpiolib.c !pinctrl_gpio_can_use_line(chip->base + lineinfo.line_offset)) base 1209 drivers/gpio/gpiolib.c __func__, gdev->base, gdev->base + gdev->ngpio - 1, base 1274 drivers/gpio/gpiolib.c int base = chip->base; base 1350 drivers/gpio/gpiolib.c if (base < 0) { base 1351 drivers/gpio/gpiolib.c base = gpiochip_find_base(chip->ngpio); base 1352 drivers/gpio/gpiolib.c if (base < 0) { base 1353 drivers/gpio/gpiolib.c ret = base; base 1363 drivers/gpio/gpiolib.c chip->base = base; base 1365 drivers/gpio/gpiolib.c gdev->base = base; base 1470 drivers/gpio/gpiolib.c gdev->base, gdev->base + gdev->ngpio - 1, base 2504 drivers/gpio/gpiolib.c return pinctrl_gpio_request(chip->gpiodev->base + offset); base 2515 drivers/gpio/gpiolib.c pinctrl_gpio_free(chip->gpiodev->base + offset); base 2528 drivers/gpio/gpiolib.c return pinctrl_gpio_set_config(chip->gpiodev->base + offset, config); base 2564 drivers/gpio/gpiolib.c pin_range->range.base = gdev->base + gpio_offset; base 2622 drivers/gpio/gpiolib.c pin_range->range.base = gdev->base + gpio_offset; base 4961 drivers/gpio/gpiolib.c unsigned gpio = gdev->base; base 5046 drivers/gpio/gpiolib.c gdev->base, gdev->base + gdev->ngpio - 1); base 52 drivers/gpio/gpiolib.h int base; base 32 drivers/gpio/sgpio-aspeed.c void __iomem *base; base 95 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->val_regs + GPIO_VAL_VALUE; base 97 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->rdata_reg; base 99 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; base 101 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; base 103 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; base 105 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; base 107 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; base 447 drivers/gpio/sgpio-aspeed.c gpio->base = devm_platform_ioremap_resource(pdev, 0); base 448 drivers/gpio/sgpio-aspeed.c if (IS_ERR(gpio->base)) base 449 drivers/gpio/sgpio-aspeed.c return PTR_ERR(gpio->base); base 495 drivers/gpio/sgpio-aspeed.c gpio->base + ASPEED_SGPIO_CTRL); base 510 drivers/gpio/sgpio-aspeed.c gpio->chip.base = -1; base 389 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint64_t base; base 133 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c *aperture_base = adev->doorbell.base; base 72 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h struct dma_fence base; base 76 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t base[8] = { base 96 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL - base 77 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c dma_fence_init(&fence->base, &amdkfd_fence_ops, &fence->lock, base 90 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c fence = container_of(f, struct amdgpu_amdkfd_fence, base); base 313 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t base[2] = { base 327 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL - base 917 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint64_t base = page_table_base | AMDGPU_PTE_VALID; base 937 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); base 938 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); base 233 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t base[2] = { base 241 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL - base 89 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c if (entry->bo_va->base.vm == avm) base 221 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c struct dma_resv *resv = bo->tbo.base.resv; base 246 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c if (f->context == ef->base.context) base 312 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c struct amdgpu_bo *pd = vm->root.base.bo; base 333 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo); base 348 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c struct amdgpu_bo *pd = vm->root.base.bo; base 629 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c if ((vm && vm != entry->bo_va->base.vm) || base 651 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c if ((vm && vm != entry->bo_va->base.vm) || base 656 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c amdgpu_vm_get_pd_bo(entry->bo_va->base.vm, &ctx->list, base 711 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c struct amdgpu_vm *vm = bo_va->base.vm; base 747 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c amdgpu_bo_size(entry->bo_va->base.bo), base 812 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c struct amdgpu_bo *pd = peer_vm->root.base.bo; base 815 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c sync, pd->tbo.base.resv, base 872 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c *ef = dma_fence_get(&info->eviction_fence->base); base 878 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c ret = amdgpu_bo_reserve(vm->root.base.bo, true); base 886 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c ret = amdgpu_bo_sync_wait(vm->root.base.bo, base 890 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c ret = dma_resv_reserve_shared(vm->root.base.bo->tbo.base.resv, 1); base 893 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c amdgpu_bo_fence(vm->root.base.bo, base 894 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c &vm->process_info->eviction_fence->base, true); base 895 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c amdgpu_bo_unreserve(vm->root.base.bo); base 909 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c amdgpu_bo_unreserve(vm->root.base.bo); base 914 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c dma_fence_put(&info->eviction_fence->base); base 995 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c struct amdgpu_bo *pd = vm->root.base.bo; base 1017 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c dma_fence_put(&process_info->eviction_fence->base); base 1062 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c struct amdgpu_bo *pd = avm->root.base.bo; base 1291 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c drm_gem_object_put_unlocked(&mem->bo->tbo.base); base 1389 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c if (entry->bo_va->base.vm == vm && !entry->is_mapped) { base 1416 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c &avm->process_info->eviction_fence->base, base 1468 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c if (entry->bo_va->base.vm == vm && entry->is_mapped) { base 1633 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c drm_gem_object_get(&bo->tbo.base); base 2065 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c process_info->eviction_fence->base.context, base 2072 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c dma_fence_put(&process_info->eviction_fence->base); base 2074 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c *ef = dma_fence_get(&new_fence->base); base 2080 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c &process_info->eviction_fence->base, true); base 2085 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c struct amdgpu_bo *bo = peer_vm->root.base.bo; base 2087 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true); base 2137 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c ret = dma_resv_reserve_shared(gws_bo->tbo.base.resv, 1); base 2140 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true); base 35 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c struct cgs_device base; base 496 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c cgs_device->base.ops = &amdgpu_cgs_ops; base 491 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_connector_property_change_mode(&amdgpu_encoder->base); base 506 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_connector_property_change_mode(&amdgpu_encoder->base); base 521 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_connector_property_change_mode(&amdgpu_encoder->base); base 535 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_connector_property_change_mode(&amdgpu_encoder->base); base 549 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_connector_property_change_mode(&amdgpu_encoder->base); base 563 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_connector_property_change_mode(&amdgpu_encoder->base); base 603 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_connector_property_change_mode(&amdgpu_encoder->base); base 804 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c amdgpu_connector_property_change_mode(&amdgpu_encoder->base); base 1556 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c connector = &amdgpu_connector->base; base 1589 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_init_with_ddc(dev, &amdgpu_connector->base, base 1593 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_helper_add(&amdgpu_connector->base, base 1598 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1601 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1610 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_init_with_ddc(dev, &amdgpu_connector->base, base 1614 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_helper_add(&amdgpu_connector->base, base 1616 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1619 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1622 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1626 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1630 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1635 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1647 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1654 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_init_with_ddc(dev, &amdgpu_connector->base, base 1658 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_helper_add(&amdgpu_connector->base, base 1660 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1678 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_init_with_ddc(dev, &amdgpu_connector->base, base 1682 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); base 1684 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1687 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1703 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_init_with_ddc(dev, &amdgpu_connector->base, base 1707 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); base 1709 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1712 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1733 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_init_with_ddc(dev, &amdgpu_connector->base, base 1737 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); base 1739 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1742 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1745 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1748 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1751 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1756 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1760 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1765 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1788 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_init_with_ddc(dev, &amdgpu_connector->base, base 1792 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); base 1793 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1796 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1799 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1802 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1805 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1809 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1813 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1837 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_init_with_ddc(dev, &amdgpu_connector->base, base 1841 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); base 1843 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1846 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1849 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1852 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1855 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1859 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1863 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1884 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_init_with_ddc(dev, &amdgpu_connector->base, base 1888 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); base 1889 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 1908 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_init_with_ddc(dev, &amdgpu_connector->base, base 1912 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); base 1913 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c drm_object_attach_property(&amdgpu_connector->base.base, base 405 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c .resv = bo->tbo.base.resv, base 729 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c struct dma_resv *resv = bo->tbo.base.resv; base 922 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo); base 1286 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c r = drm_sched_job_init(&job->base, entity, p->filp); base 1310 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c p->fence = dma_fence_get(&job->base.s_fence->finished); base 1328 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c priority = job->base.s_priority; base 1329 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c drm_sched_entity_push_job(&job->base, entity); base 1342 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c drm_sched_job_cleanup(&job->base); base 1724 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo) base 1727 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c *bo = mapping->bo_va->base.bo; base 1731 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket) base 594 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c adev->doorbell.base = 0; base 607 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c adev->doorbell.base = pci_resource_start(adev->pdev, 2); base 624 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c adev->doorbell.ptr = ioremap(adev->doorbell.base, base 3570 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c drm_sched_increase_karma(&job->base); base 3802 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c job ? job->base.id : -1, hive->hive_id); base 3809 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c job ? job->base.id : -1); base 3850 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c drm_sched_stop(&ring->sched, job ? &job->base : NULL); base 3861 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c if (job && job->base.s_fence->parent && base 3862 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c dma_fence_is_signaled(job->base.s_fence->parent)) base 80 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c struct drm_crtc *crtc = &amdgpu_crtc->base; base 111 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); base 208 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl, base 220 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c work->base = amdgpu_bo_gpu_offset(new_abo); base 531 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c rfb->base.obj[0] = obj; base 532 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); base 533 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); base 535 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c rfb->base.obj[0] = NULL; base 576 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c return &amdgpu_fb->base; base 33 drivers/gpu/drm/amd/amdgpu/amdgpu_display.h #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) base 168 drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c dma_resv_add_excl_fence(obj, &array->base); base 169 drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c dma_fence_put(&array->base); base 219 drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c r = __dma_resv_make_exclusive(bo->tbo.base.resv); base 396 drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c return &bo->tbo.base; base 29 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h resource_size_t base; base 241 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c fb = &rfbdev->rfb.base; base 257 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base; base 295 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c if (rfb->base.obj[0]) { base 296 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c amdgpufb_destroy_pinned_object(rfb->base.obj[0]); base 297 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c rfb->base.obj[0] = NULL; base 298 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c drm_framebuffer_unregister_private(&rfb->base); base 299 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c drm_framebuffer_cleanup(&rfb->base); base 380 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]); base 389 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0])) base 53 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c struct dma_fence base; base 82 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); base 84 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c if (__f->base.ops == &amdgpu_fence_ops) base 151 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c dma_fence_init(&fence->base, &amdgpu_fence_ops, base 177 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c rcu_assign_pointer(*ptr, dma_fence_get(&fence->base)); base 179 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c *f = &fence->base; base 654 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); base 88 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c *obj = &bo->tbo.base; base 137 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) base 251 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c r = amdgpu_bo_reserve(vm->root.base.bo, false); base 255 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c resv = vm->root.base.bo->tbo.base.resv; base 265 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c abo->parent = amdgpu_bo_ref(vm->root.base.bo); base 267 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c amdgpu_bo_unreserve(vm->root.base.bo); base 438 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, base 675 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c struct amdgpu_vm_bo_base *base; base 694 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c info.bo_size = robj->tbo.base.size; base 714 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c for (base = robj->vm_bo; base; base = base->next) base 716 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) { base 825 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c dma_buf = READ_ONCE(bo->tbo.base.dma_buf); base 826 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c attachment = READ_ONCE(bo->tbo.base.import_attach); base 34 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, tbo.base) base 145 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c u64 base) base 149 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c mc->vram_start = base; base 228 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h u64 base); base 146 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c fence_ctx = job->base.s_fence ? base 147 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c job->base.s_fence->scheduled.context : 0; base 137 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c fence = &array->base; base 244 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c r = amdgpu_sync_fence(adev, sync, &array->base, false); base 246 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c ring->vmid_wait = &array->base; base 47 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), base 76 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c (*job)->base.sched = &adev->rings[0]->sched; base 107 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched); base 112 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c f = job->base.s_fence ? &job->base.s_fence->finished : job->fence; base 152 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c r = drm_sched_job_init(&job->base, entity, owner); base 157 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c *f = dma_fence_get(&job->base.s_fence->finished); base 159 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c priority = job->base.s_priority; base 160 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c drm_sched_entity_push_job(&job->base, entity); base 173 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c job->base.sched = &ring->sched; base 205 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c &job->base.s_fence->finished, base 224 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c finished = &job->base.s_fence->finished; base 36 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h container_of((sched_job), struct amdgpu_job, base) base 43 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h struct drm_sched_job base; base 472 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c if (crtc && crtc->base.id == info->mode_crtc.id) { base 1073 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); base 1079 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); base 1139 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c &adev->mode_info.crtcs[pipe]->base.hwmode); base 182 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, base 56 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) base 57 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) base 58 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) base 59 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) base 61 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base) base 302 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h struct drm_framebuffer base; base 381 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h struct drm_crtc base; base 451 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h struct drm_encoder base; base 525 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h struct i2c_adapter base; base 533 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h struct drm_connector base; base 557 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h struct amdgpu_connector base; base 85 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c if (bo->tbo.base.import_attach) base 86 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); base 87 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c drm_gem_object_release(&bo->tbo.base); base 551 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c drm_gem_private_object_init(adev->ddev, &bo->tbo.base, size); base 593 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); base 616 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c dma_resv_unlock(bo->tbo.base.resv); base 637 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c bp.resv = bo->tbo.base.resv; base 678 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv, base 684 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c dma_resv_unlock((*bo_ptr)->tbo.base.resv); base 781 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false, base 1159 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c dma_resv_assert_held(bo->tbo.base.resv); base 1308 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c dma_resv_lock(bo->base.resv, NULL); base 1310 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); base 1316 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c dma_resv_unlock(bo->base.resv); base 1391 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c struct dma_resv *resv = bo->tbo.base.resv; base 1416 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, owner, false); base 1436 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && base 61 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h struct amdgpu_vm_bo_base base; base 194 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); base 36 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence->finished) base 173 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __string(ring, to_amdgpu_ring(job->base.sched)->name) base 178 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __entry->sched_job_id = job->base.id; base 180 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __entry->context = job->base.s_fence->finished.context; base 181 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __entry->seqno = job->base.s_fence->finished.seqno; base 182 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __assign_str(ring, to_amdgpu_ring(job->base.sched)->name) base 198 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __string(ring, to_amdgpu_ring(job->base.sched)->name) base 203 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __entry->sched_job_id = job->base.id; base 205 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __entry->context = job->base.s_fence->finished.context; base 206 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __entry->seqno = job->base.s_fence->finished.seqno; base 207 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __assign_str(ring, to_amdgpu_ring(job->base.sched)->name) base 256 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __entry->bo = bo_va ? bo_va->base.bo : NULL; base 280 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __entry->bo = bo_va ? bo_va->base.bo : NULL; base 471 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __string(ring, sched_job->base.sched->name); base 479 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __assign_str(ring, sched_job->base.sched->name) base 480 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __entry->id = sched_job->base.id; base 231 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c return drm_vma_node_verify_access(&abo->tbo.base.vma_node, base 444 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c bo->base.resv, &fence); base 714 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c mem->bus.base = 0; base 738 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c mem->bus.base = adev->gmc.aper_base; base 758 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + base 1487 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c !dma_resv_test_signaled_rcu(bo->base.resv, true)) base 1494 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c flist = dma_resv_get_list(bo->base.resv); base 1498 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c dma_resv_held(bo->base.resv)); base 1076 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, base 1088 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv, base 291 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, base 295 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c base->vm = vm; base 296 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c base->bo = bo; base 297 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c base->next = NULL; base 298 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c INIT_LIST_HEAD(&base->vm_status); base 302 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c base->next = bo->vm_bo; base 303 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c bo->vm_bo = base; base 305 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) base 310 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_vm_bo_relocated(base); base 312 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_vm_bo_idle(base); base 323 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_vm_bo_evicted(base); base 336 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_bo *parent = pt->base.bo->parent; base 341 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c return container_of(parent->vm_bo, struct amdgpu_vm_pt, base); base 392 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c BUG_ON(!cursor->entry->base.bo); base 562 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c entry->tv.bo = &vm->root.base.bo->tbo; base 586 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) base 735 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base); base 831 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c else if (!vm->root.base.bo || vm->root.base.bo->shadow) base 834 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (vm->root.base.bo) base 835 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c bp->resv = vm->root.base.bo->tbo.base.resv; base 871 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (entry->base.bo) base 883 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c pt->parent = amdgpu_bo_ref(cursor->parent->base.bo); base 884 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_vm_bo_base_init(&entry->base, vm, pt); base 905 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (entry->base.bo) { base 906 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c entry->base.bo->vm_bo = NULL; base 907 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c list_del(&entry->base.vm_status); base 908 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_bo_unref(&entry->base.bo->shadow); base 909 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_bo_unref(&entry->base.bo); base 1143 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_vm_bo_base *base; base 1145 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c for (base = bo->vm_bo; base; base = base->next) { base 1146 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (base->vm != vm) base 1149 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c return container_of(base, struct amdgpu_bo_va, base); base 1195 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_bo *bo = parent->base.bo, *pbo; base 1203 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags); base 1223 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (entry->base.bo && !entry->base.moved) base 1224 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_vm_bo_relocated(&entry->base); base 1259 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c base.vm_status); base 1260 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_vm_bo_idle(&entry->base); base 1404 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c pt = cursor.entry->base.bo; base 1685 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_bo *bo = bo_va->base.bo; base 1686 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_vm *vm = bo_va->base.vm; base 1709 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c exclusive = dma_resv_get_excl(bo->tbo.base.resv); base 1719 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (clear || (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)) base 1724 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (!clear && bo_va->base.moved) { base 1725 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c bo_va->base.moved = false; base 1750 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) { base 1754 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_vm_bo_evicted(&bo_va->base); base 1756 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_vm_bo_idle(&bo_va->base); base 1758 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_vm_bo_done(&bo_va->base); base 1886 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct dma_resv *resv = vm->root.base.bo->tbo.base.resv; base 1989 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { base 1999 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c base.vm_status); base 2000 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c resv = bo_va->base.bo->tbo.base.resv; base 2048 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_vm_bo_base_init(&bo_va->base, vm, bo); base 2081 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_vm *vm = bo_va->base.vm; base 2082 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_bo *bo = bo_va->base.bo; base 2091 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv && base 2092 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c !bo_va->base.moved) { base 2093 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c list_move(&bo_va->base.vm_status, &vm->moved); base 2121 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_bo *bo = bo_va->base.bo; base 2122 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_vm *vm = bo_va->base.vm; base 2186 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_bo *bo = bo_va->base.bo; base 2206 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); base 2244 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_vm *vm = bo_va->base.vm; base 2419 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (mapping->bo_va && mapping->bo_va->base.bo) { base 2422 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c bo = mapping->bo_va->base.bo; base 2423 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (dma_resv_locking_ctx(bo->tbo.base.resv) != base 2446 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_bo *bo = bo_va->base.bo; base 2447 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_vm *vm = bo_va->base.vm; base 2448 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c struct amdgpu_vm_bo_base **base; base 2451 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) base 2454 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c for (base = &bo_va->base.bo->vm_bo; *base; base 2455 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c base = &(*base)->next) { base 2456 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (*base != &bo_va->base) base 2459 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c *base = bo_va->base.next; base 2465 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c list_del(&bo_va->base.vm_status); base 2515 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) { base 2526 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) base 2656 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c return dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv, base 2731 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c r = dma_resv_reserve_shared(root->tbo.base.resv, 1); base 2735 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_vm_bo_base_init(&vm->root.base, vm, root); base 2741 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_bo_unreserve(vm->root.base.bo); base 2761 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_bo_unreserve(vm->root.base.bo); base 2764 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_bo_unref(&vm->root.base.bo->shadow); base 2765 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_bo_unref(&vm->root.base.bo); base 2766 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c vm->root.base.bo = NULL; base 2798 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c if (vm->root.entries[i].base.bo) base 2830 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c r = amdgpu_bo_reserve(vm->root.base.bo, true); base 2857 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo); base 2892 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_bo_unref(&vm->root.base.bo->shadow); base 2908 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c amdgpu_bo_unreserve(vm->root.base.bo); base 2981 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c root = amdgpu_bo_ref(vm->root.base.bo); base 2990 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c WARN_ON(vm->root.base.bo); base 148 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h struct amdgpu_vm_bo_base base; base 55 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c r = amdgpu_bo_sync_wait(p->vm->root.base.bo, owner, true); base 63 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c struct amdgpu_bo *root = p->vm->root.base.bo; base 75 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c r = amdgpu_sync_resv(p->adev, &p->job->sync, root->tbo.base.resv, base 96 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c struct amdgpu_bo *root = p->vm->root.base.bo; base 104 drivers/gpu/drm/amd/amdgpu/atom.c static uint32_t atom_iio_execute(struct atom_context *ctx, int base, base 110 drivers/gpu/drm/amd/amdgpu/atom.c switch (CU8(base)) { base 112 drivers/gpu/drm/amd/amdgpu/atom.c base++; base 115 drivers/gpu/drm/amd/amdgpu/atom.c temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1)); base 116 drivers/gpu/drm/amd/amdgpu/atom.c base += 3; base 119 drivers/gpu/drm/amd/amdgpu/atom.c ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); base 120 drivers/gpu/drm/amd/amdgpu/atom.c base += 3; base 124 drivers/gpu/drm/amd/amdgpu/atom.c ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << base 125 drivers/gpu/drm/amd/amdgpu/atom.c CU8(base + 2)); base 126 drivers/gpu/drm/amd/amdgpu/atom.c base += 3; base 130 drivers/gpu/drm/amd/amdgpu/atom.c (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + base 132 drivers/gpu/drm/amd/amdgpu/atom.c base += 3; base 136 drivers/gpu/drm/amd/amdgpu/atom.c ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << base 137 drivers/gpu/drm/amd/amdgpu/atom.c CU8(base + 3)); base 139 drivers/gpu/drm/amd/amdgpu/atom.c ((index >> CU8(base + 2)) & base 140 drivers/gpu/drm/amd/amdgpu/atom.c (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + base 142 drivers/gpu/drm/amd/amdgpu/atom.c base += 4; base 146 drivers/gpu/drm/amd/amdgpu/atom.c ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << base 147 drivers/gpu/drm/amd/amdgpu/atom.c CU8(base + 3)); base 149 drivers/gpu/drm/amd/amdgpu/atom.c ((data >> CU8(base + 2)) & base 150 drivers/gpu/drm/amd/amdgpu/atom.c (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + base 152 drivers/gpu/drm/amd/amdgpu/atom.c base += 4; base 156 drivers/gpu/drm/amd/amdgpu/atom.c ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << base 157 drivers/gpu/drm/amd/amdgpu/atom.c CU8(base + 3)); base 160 drivers/gpu/drm/amd/amdgpu/atom.c io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - base 162 drivers/gpu/drm/amd/amdgpu/atom.c (base base 165 drivers/gpu/drm/amd/amdgpu/atom.c << CU8(base + 3); base 166 drivers/gpu/drm/amd/amdgpu/atom.c base += 4; base 1203 drivers/gpu/drm/amd/amdgpu/atom.c int base = CU16(ctx->cmd_table + 4 + 2 * index); base 1209 drivers/gpu/drm/amd/amdgpu/atom.c if (!base) base 1212 drivers/gpu/drm/amd/amdgpu/atom.c len = CU16(base + ATOM_CT_SIZE_PTR); base 1213 drivers/gpu/drm/amd/amdgpu/atom.c ws = CU8(base + ATOM_CT_WS_PTR); base 1214 drivers/gpu/drm/amd/amdgpu/atom.c ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; base 1215 drivers/gpu/drm/amd/amdgpu/atom.c ptr = base + ATOM_CT_CODE_PTR; base 1217 drivers/gpu/drm/amd/amdgpu/atom.c SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); base 1221 drivers/gpu/drm/amd/amdgpu/atom.c ectx.start = base; base 1239 drivers/gpu/drm/amd/amdgpu/atom.c base, len, ws, ps, ptr - 1); base 1285 drivers/gpu/drm/amd/amdgpu/atom.c static void atom_index_iio(struct atom_context *ctx, int base) base 1290 drivers/gpu/drm/amd/amdgpu/atom.c while (CU8(base) == ATOM_IIO_START) { base 1291 drivers/gpu/drm/amd/amdgpu/atom.c ctx->iio[CU8(base + 1)] = base + 2; base 1292 drivers/gpu/drm/amd/amdgpu/atom.c base += 2; base 1293 drivers/gpu/drm/amd/amdgpu/atom.c while (CU8(base) != ATOM_IIO_END) base 1294 drivers/gpu/drm/amd/amdgpu/atom.c base += atom_iio_len[CU8(base)]; base 1295 drivers/gpu/drm/amd/amdgpu/atom.c base += 3; base 1301 drivers/gpu/drm/amd/amdgpu/atom.c int base; base 1326 drivers/gpu/drm/amd/amdgpu/atom.c base = CU16(ATOM_ROM_TABLE_PTR); base 1328 drivers/gpu/drm/amd/amdgpu/atom.c (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, base 1335 drivers/gpu/drm/amd/amdgpu/atom.c ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); base 1336 drivers/gpu/drm/amd/amdgpu/atom.c ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); base 459 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c SET_PIXEL_CLOCK_PS_ALLOCATION base; base 66 drivers/gpu/drm/amd/amdgpu/atombios_dp.c unsigned char *base; base 74 drivers/gpu/drm/amd/amdgpu/atombios_dp.c base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1); base 76 drivers/gpu/drm/amd/amdgpu/atombios_dp.c amdgpu_atombios_copy_swap(base, send, send_bytes, true); base 114 drivers/gpu/drm/amd/amdgpu/atombios_dp.c amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false); base 192 drivers/gpu/drm/amd/amdgpu/atombios_dp.c amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; base 313 drivers/gpu/drm/amd/amdgpu/atombios_dp.c struct drm_device *dev = amdgpu_connector->base.dev; base 72 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c struct drm_device *dev = amdgpu_encoder->base.dev; base 85 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c struct drm_encoder *encoder = &amdgpu_encoder->base; base 86 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c struct drm_device *dev = amdgpu_encoder->base.dev; base 154 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c struct drm_device *dev = amdgpu_encoder->base.dev; base 168 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c struct drm_device *dev = amdgpu_encoder->base.dev; base 231 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c struct drm_device *dev = amdgpu_encoder->base.dev; base 1180 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c struct drm_device *dev = amdgpu_connector->base.dev; base 2001 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c struct drm_device *dev = encoder->base.dev; base 46 drivers/gpu/drm/amd/amdgpu/atombios_i2c.c unsigned char *base; base 54 drivers/gpu/drm/amd/amdgpu/atombios_i2c.c base = (unsigned char *)adev->mode_info.atom_context->scratch; base 104 drivers/gpu/drm/amd/amdgpu/atombios_i2c.c amdgpu_atombios_copy_swap(buf, base, num, false); base 239 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; base 602 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (amdgpu_crtc->base.enabled && mode) { base 637 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (amdgpu_crtc->base.enabled && mode) { base 1024 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c struct drm_display_mode *mode = &amdgpu_crtc->base.mode; base 1031 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (amdgpu_crtc->base.enabled && num_heads && mode) { base 1161 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (adev->mode_info.crtcs[i]->base.enabled) base 1165 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c mode = &adev->mode_info.crtcs[i]->base.mode; base 2681 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); base 2683 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); base 2718 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); base 3154 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); base 3158 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c drm_crtc_vblank_put(&amdgpu_crtc->base); base 3484 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c encoder = &amdgpu_encoder->base; base 257 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; base 628 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (amdgpu_crtc->base.enabled && mode) { base 663 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (amdgpu_crtc->base.enabled && mode) { base 1050 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c struct drm_display_mode *mode = &amdgpu_crtc->base.mode; base 1057 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (amdgpu_crtc->base.enabled && num_heads && mode) { base 1187 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (adev->mode_info.crtcs[i]->base.enabled) base 1191 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c mode = &adev->mode_info.crtcs[i]->base.mode; base 2789 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); base 2791 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); base 2826 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); base 3280 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); base 3284 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c drm_crtc_vblank_put(&amdgpu_crtc->base); base 3610 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c encoder = &amdgpu_encoder->base; base 194 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; base 823 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c struct drm_display_mode *mode = &amdgpu_crtc->base.mode; base 835 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (amdgpu_crtc->base.enabled && num_heads && mode) { base 1004 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (amdgpu_crtc->base.enabled && mode) { base 1029 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (amdgpu_crtc->base.enabled && mode) { base 1066 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (adev->mode_info.crtcs[i]->base.enabled) base 1070 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c mode0 = &adev->mode_info.crtcs[i]->base.mode; base 1071 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c mode1 = &adev->mode_info.crtcs[i+1]->base.mode; base 2569 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); base 2571 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); base 2586 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); base 3031 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); base 3035 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c drm_crtc_vblank_put(&amdgpu_crtc->base); base 3294 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c encoder = &amdgpu_encoder->base; base 187 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; base 539 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (amdgpu_crtc->base.enabled && mode) { base 572 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (amdgpu_crtc->base.enabled && mode) { base 959 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c struct drm_display_mode *mode = &amdgpu_crtc->base.mode; base 966 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (amdgpu_crtc->base.enabled && num_heads && mode) { base 1098 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (adev->mode_info.crtcs[i]->base.enabled) base 1102 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c mode = &adev->mode_info.crtcs[i]->base.mode; base 2589 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs); base 2591 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); base 2606 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs); base 3123 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); base 3127 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c drm_crtc_vblank_put(&amdgpu_crtc->base); base 3372 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c encoder = &amdgpu_encoder->base; base 232 drivers/gpu/drm/amd/amdgpu/dce_virtual.c drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs); base 234 drivers/gpu/drm/amd/amdgpu/dce_virtual.c drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); base 242 drivers/gpu/drm/amd/amdgpu/dce_virtual.c drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs); base 675 drivers/gpu/drm/amd/amdgpu/dce_virtual.c drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); base 679 drivers/gpu/drm/amd/amdgpu/dce_virtual.c drm_crtc_vblank_put(&amdgpu_crtc->base); base 691 drivers/gpu/drm/amd/amdgpu/dce_virtual.c struct drm_device *ddev = amdgpu_crtc->base.dev; base 2081 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u32 data, base; base 2100 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); base 2101 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base); base 2104 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); base 2105 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base); base 2108 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); base 2109 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base); base 2112 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); base 2113 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base); base 2116 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); base 2117 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base); base 2120 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); base 2121 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base); base 36 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); base 38 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; base 39 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c base <<= 24; base 41 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c return base; base 577 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c u64 base = 0; base 580 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c base = gfxhub_v2_0_get_fb_location(adev); base 582 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c amdgpu_gmc_vram_location(adev, &adev->gmc, base); base 228 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base 229 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c base <<= 24; base 231 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c amdgpu_gmc_vram_location(adev, mc, base); base 245 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base 246 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c base <<= 24; base 248 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c amdgpu_gmc_vram_location(adev, mc, base); base 433 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c u64 base = 0; base 436 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base 437 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c base <<= 24; base 439 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c amdgpu_gmc_vram_location(adev, mc, base); base 1015 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c u64 base = 0; base 1018 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c base = mmhub_v9_4_get_fb_location(adev); base 1020 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c base = mmhub_v1_0_get_fb_location(adev); base 1023 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; base 1024 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c amdgpu_gmc_vram_location(adev, mc, base); base 43 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); base 46 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; base 47 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c base <<= 24; base 52 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c adev->gmc.fb_start = base; base 55 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c return base; base 41 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE); base 44 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; base 45 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c base <<= 24; base 50 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c adev->gmc.fb_start = base; base 53 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c return base; base 135 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c lower_32_bits(adev->doorbell.base)); base 137 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c upper_32_bits(adev->doorbell.base)); base 105 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c lower_32_bits(adev->doorbell.base)); base 107 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c upper_32_bits(adev->doorbell.base)); base 168 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c lower_32_bits(adev->doorbell.base)); base 170 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c upper_32_bits(adev->doorbell.base)); base 108 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c u32 base; base 112 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c base = adev->reg_offset[GC_HWIP][0][1]; base 116 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c base = adev->reg_offset[GC_HWIP][0][0]; base 121 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c return base + internal_offset; base 1442 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c uint64_t base = (uintptr_t)alternate_aperture_base; base 1443 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c uint64_t limit = base + alternate_aperture_size - 1; base 1445 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 || base 1451 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c qpd->sh_mem_ape1_base = base >> 16; base 281 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c #define MAKE_GPUVM_APP_LIMIT(base, size) \ base 282 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c (((uint64_t)(base) & 0xFFFFFF0000000000UL) + (size) - 1) base 287 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c #define MAKE_SCRATCH_APP_LIMIT(base) \ base 288 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c (((uint64_t)base & 0xFFFFFFFF00000000UL) | 0xFFFFFFFF) base 292 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c #define MAKE_LDS_APP_LIMIT(base) \ base 293 drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c (((uint64_t)(base) & 0xFFFFFFFF00000000UL) | 0xFFFFFFFF) base 166 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c acrtc->base.state); base 189 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c acrtc->base.state); base 305 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state); base 317 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); base 323 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); base 326 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_crtc_vblank_put(&amdgpu_crtc->base); base 343 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); base 346 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c list_add_tail(&e->base.link, &adev->ddev->vblank_event_list); base 377 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c acrtc_state = to_dm_crtc_state(acrtc->base.state); base 389 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_crtc_handle_vblank(&acrtc->base); base 421 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c acrtc_state = to_dm_crtc_state(acrtc->base.state); base 432 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_crtc_handle_vblank(&acrtc->base); base 437 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); base 909 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector, aconnector->base.base.id); base 1217 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (aconnector->base.force && new_connection_type == dc_connection_none) base 1326 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct drm_connector *connector = &aconnector->base; base 1344 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (aconnector->base.force != DRM_FORCE_UNSPECIFIED base 1462 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct drm_connector *connector = &aconnector->base; base 1478 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (aconnector->base.force && new_connection_type == dc_connection_none) { base 1486 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) base 1497 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) base 1585 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct drm_connector *connector = &aconnector->base; base 1605 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (aconnector->base.force && new_connection_type == dc_connection_none) { base 1974 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); base 1986 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c return &new_state->base; base 2039 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &state->base, base 2340 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (aconnector->base.force && new_connection_type == dc_connection_none) { base 2672 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); base 2774 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c const struct drm_framebuffer *fb = &afb->base; base 3553 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dm_state ? &dm_state->base : NULL; base 3571 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_connector = &aconnector->base; base 3591 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { base 3600 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &aconnector->base.modes, base 3630 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &mode, &aconnector->base, con_state, NULL); base 3633 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &mode, &aconnector->base, con_state, old_stream); base 3703 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c crtc->state = &state->base; base 3722 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); base 3742 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c return &state->base; base 3824 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && base 3828 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c connected = (aconnector->base.force == DRM_FORCE_ON); base 3970 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c i2c_del_adapter(&aconnector->i2c->base); base 3994 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c state->base.max_requested_bpc = 8; base 3999 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c __drm_atomic_helper_connector_reset(connector, &state->base); base 4015 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); base 4024 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c return &new_state->base; base 4052 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (!aconnector->base.edid_blob_ptr) { base 4054 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.name); base 4056 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.force = DRM_FORCE_OFF; base 4057 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.override_edid = false; base 4061 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c edid = (struct edid *) aconnector->base.edid_blob_ptr->data; base 4071 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (aconnector->base.force == DRM_FORCE_ON) { base 4093 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.override_edid = true; base 4116 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && base 4443 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); base 4456 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); base 4463 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c return &dm_plane_state->base; base 4803 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &acrtc->base, base 4811 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); base 4814 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (acrtc->base.funcs->reset) base 4815 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c acrtc->base.funcs->reset(&acrtc->base); base 4821 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c acrtc->base.enabled = false; base 4825 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, base 4827 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); base 5040 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (aconnector->base.funcs->reset) base 5041 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.funcs->reset(&aconnector->base); base 5045 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.interlace_allowed = false; base 5046 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.doublescan_allowed = false; base 5047 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.stereo_allowed = false; base 5048 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.dpms = DRM_MODE_DPMS_OFF; base 5059 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; base 5060 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.ycbcr_420_allowed = base 5064 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; base 5065 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.ycbcr_420_allowed = base 5069 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; base 5075 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_object_attach_property(&aconnector->base.base, base 5079 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_object_attach_property(&aconnector->base.base, base 5082 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_object_attach_property(&aconnector->base.base, base 5085 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_object_attach_property(&aconnector->base.base, base 5089 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); base 5092 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.state->max_bpc = 8; base 5093 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aconnector->base.state->max_requested_bpc = 8; base 5097 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_object_attach_property(&aconnector->base.base, base 5105 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &aconnector->base.base, base 5109 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &aconnector->base); base 5169 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c i2c->base.owner = THIS_MODULE; base 5170 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c i2c->base.class = I2C_CLASS_DDC; base 5171 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c i2c->base.dev.parent = &adev->pdev->dev; base 5172 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c i2c->base.algo = &amdgpu_dm_i2c_algo; base 5173 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); base 5174 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c i2c_set_adapdata(&i2c->base, i2c); base 5208 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c res = i2c_add_adapter(&i2c->base); base 5219 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &aconnector->base, base 5230 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &aconnector->base, base 5241 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &aconnector->base, &aencoder->base); base 5243 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_connector_register(&aconnector->base); base 5288 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &aencoder->base, base 5293 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); base 5300 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); base 5319 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_crtc_vblank_on(&acrtc->base); base 5330 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_crtc_vblank_off(&acrtc->base); base 5482 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c assert_spin_locked(&acrtc->base.dev->event_lock); base 5485 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c acrtc->event = acrtc->base.state->event; base 5491 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c acrtc->base.state->event = NULL; base 5569 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c new_crtc_state->base.crtc->base.id, base 5570 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c (int)new_crtc_state->base.vrr_enabled, base 5602 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c config.state = new_crtc_state->base.vrr_enabled ? base 5637 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dm_set_vupdate_irq(new_state->base.crtc, true); base 5638 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_crtc_vblank_get(new_state->base.crtc); base 5640 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c __func__, new_state->base.crtc->base.id); base 5645 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dm_set_vupdate_irq(new_state->base.crtc, false); base 5646 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_crtc_vblank_put(new_state->base.crtc); base 5648 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c __func__, new_state->base.crtc->base.id); base 5766 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true, base 5876 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (acrtc_attach->base.state->event) { base 6205 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, base 6234 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c __func__, acrtc->base.base.id); base 6286 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); base 6297 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); base 6298 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); base 6321 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, base 6409 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_send_event_locked(dev, &new_crtc_state->event->base); base 6443 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct drm_plane *plane = disconnected_acrtc->base.primary; base 6465 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); base 6513 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); base 6523 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dm_force_atomic_commit(&aconnector->base); base 6569 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c "timed out\n", crtc->base.id, crtc->name); base 6583 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c to_amdgpu_dm_connector(new_con_state->base.connector); base 6584 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct drm_display_mode *mode = &new_crtc_state->base.mode; base 6593 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c config.state = new_crtc_state->base.vrr_enabled ? base 6651 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &aconnector->base); base 6653 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &aconnector->base); base 6680 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c __func__, acrtc->base.base.id); base 6737 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c crtc->base.id); base 6781 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c crtc->base.id); base 6829 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (dm_new_crtc_state->base.color_mgmt_changed || base 6976 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c plane->base.id, old_plane_crtc->base.id); base 7023 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c plane->base.id, new_plane_crtc->base.id); base 7413 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); base 7417 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drm_atomic_get_new_crtc_state(state, &acrtc->base))) base 246 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h struct drm_connector base; base 292 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) base 302 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h struct drm_plane_state base; base 307 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h struct drm_crtc_state base; base 331 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) base 334 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h struct drm_private_state base; base 339 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) base 342 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h struct drm_connector_state base; base 353 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h container_of((x), struct dm_connector_state, base) base 303 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c (struct amdgpu_device *)crtc->base.state->dev->dev_private; base 312 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, °amma_size); base 316 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, ®amma_size); base 380 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c if (crtc->base.ctm) { base 381 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c ctm = (struct drm_color_ctm *)crtc->base.ctm->data; base 424 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, base 783 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c if (connector->base.status != connector_status_connected) base 789 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); base 948 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c struct dentry *dir = connector->base.debugfs_entry; base 950 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || base 951 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { base 440 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c aconnector, aconnector->base.base.id); base 445 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c aconnector, aconnector->base.base.id); base 462 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c aconnector, aconnector->base.base.id); base 533 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; base 582 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c ddc = &aconnector->i2c->base; base 589 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c edid = drm_get_edid(&aconnector->base, ddc); base 610 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c aconnector->base.name); base 152 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drm_encoder_cleanup(&amdgpu_encoder->base); base 206 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c &aconnector->base, base 241 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c &aconnector->base, aconnector->edid); base 252 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c return &amdgpu_dm_connector->mst_encoder->base; base 274 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c struct drm_device *dev = connector->base.dev; base 283 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c encoder = &amdgpu_encoder->base; base 288 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c &amdgpu_encoder->base, base 304 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c struct drm_device *dev = master->base.dev; base 313 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c connector = &aconnector->base; base 335 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drm_connector_attach_encoder(&aconnector->base, base 336 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c &aconnector->mst_encoder->base); base 339 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c &connector->base, base 343 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c &connector->base, base 356 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c aconnector, connector->base.id, aconnector->mst_port); base 360 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c DRM_DEBUG_KMS(":%d\n", connector->base.id); base 369 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c struct drm_device *dev = master->base.dev; base 374 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c aconnector, connector->base.id, aconnector->mst_port); base 414 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c aconnector->dm_dp_aux.aux.dev = aconnector->base.kdev; base 420 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c aconnector->base.name, dm->adev->dev); base 55 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c bp->base.ctx->logger base 107 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c return &bp->base; base 116 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c kfree(bp->base.bios_local_image); base 117 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c kfree(bp->base.integrated_info); base 1118 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (bios_parser_get_embedded_panel_info(&bp->base, &panel_info) base 1649 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (bios_parser_get_embedded_panel_info(&bp->base, &panel_info) base 2012 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c *id_list = (uint16_t *)bios_get_image(&bp->base, offset, *number * sizeof(uint16_t)); base 2860 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c bp->base.funcs = &vbios_funcs; base 2861 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c bp->base.bios = init->bios; base 2862 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c bp->base.bios_size = bp->base.bios[BIOS_IMAGE_SIZE_OFFSET] * BIOS_IMAGE_SIZE_UNIT; base 2864 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c bp->base.ctx = init->ctx; base 2865 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c bp->base.bios_local_image = NULL; base 2922 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); base 2923 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; base 69 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c bp->base.ctx->logger base 116 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c kfree(bp->base.bios_local_image); base 117 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c kfree(bp->base.integrated_info); base 1937 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c bp->base.funcs = &vbios_funcs; base 1938 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c bp->base.bios = init->bios; base 1939 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; base 1941 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c bp->base.ctx = init->ctx; base 1943 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c bp->base.bios_local_image = NULL; base 1998 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); base 1999 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; base 2015 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c return &bp->base; base 39 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h #define GET_IMAGE(type, offset) ((type *) bios_get_image(&bp->base, offset, sizeof(type))) base 54 drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal.h struct dc_bios base; base 70 drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal.h container_of(dc_bios, struct bios_parser, base) base 55 drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h struct dc_bios base; base 72 drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h container_of(dc_bios, struct bios_parser, base) base 38 drivers/gpu/drm/amd/display/dc/bios/command_table.c (amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \ base 43 drivers/gpu/drm/amd/display/dc/bios/command_table.c amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \ base 47 drivers/gpu/drm/amd/display/dc/bios/command_table.c bios_cmd_table_para_revision(bp->base.ctx->driver_context, \ base 42 drivers/gpu/drm/amd/display/dc/bios/command_table2.c bp->base.ctx->logger base 50 drivers/gpu/drm/amd/display/dc/bios/command_table2.c (amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \ base 55 drivers/gpu/drm/amd/display/dc/bios/command_table2.c amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \ base 59 drivers/gpu/drm/amd/display/dc/bios/command_table2.c bios_cmd_table_para_revision(bp->base.ctx->driver_context, \ base 143 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c return &clk_mgr->base; base 237 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu; base 274 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug; base 275 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; base 327 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; base 438 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c struct clk_mgr *base = &clk_mgr->base; base 445 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c base->ctx = ctx; base 446 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c base->funcs = &dce_funcs; base 293 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c clk_mgr->base.funcs = &dce110_funcs; base 128 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; base 129 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c struct dc *core_dc = clk_mgr->base.ctx->dc; base 171 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; base 180 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c if (!ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev)) base 238 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c clk_mgr->base.funcs = &dce112_funcs; base 60 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; base 136 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr->base.dprefclk_khz = 600000; base 137 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr->base.funcs = &dce120_funcs; base 143 drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c clk_mgr->base.dprefclk_khz = 625000; base 45 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; base 47 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; base 77 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) base 120 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz; base 121 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; base 122 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; base 256 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.ctx = ctx; base 258 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.funcs = &rv1_clk_funcs; base 266 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->base.dprefclk_khz = 600000; base 91 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c struct dc *core_dc = clk_mgr->base.ctx->dc; base 121 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c clk_mgr->base.dprefclk_khz / 1000); base 107 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { base 148 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c bool going_up = clk_mgr->base.clks.dispclk_khz < khz; base 153 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.clks.dispclk_khz = khz; base 169 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c bool going_up = clk_mgr->base.clks.dppclk_khz < khz; base 174 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.clks.dppclk_khz = khz; base 281 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { base 298 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { base 433 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.ctx = ctx; base 435 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.funcs = &dcn2_funcs; base 447 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved base 482 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR base 100 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { base 101 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) base 526 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.ctx = ctx; base 527 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.funcs = &dcn21_funcs; base 544 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.dprefclk_khz = 600000; base 555 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c rn_dump_clk_registers(&s, &clk_mgr->base, &log_info); base 556 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.dprefclk_khz = s.dprefclk; base 558 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (clk_mgr->base.dprefclk_khz != 600000) { base 559 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.dprefclk_khz = 600000; base 564 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (clk_mgr->base.dprefclk_khz == 0) base 565 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.dprefclk_khz = 600000; base 570 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->base.bw_params = &rn_bw_params; base 574 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id); base 585 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c build_watermark_ranges(clk_mgr->base.bw_params, &ranges); base 85 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c struct dc *core_dc = clk_mgr->base.ctx->dc; base 116 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c clk_mgr->base.dprefclk_khz / 1000); base 38 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c container_of(abm, struct dce_abm, base) base 50 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c abm_dce->base.ctx base 216 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c dce_abm_set_pipe(&abm_dce->base, controller_id); base 456 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c struct abm *base = &abm_dce->base; base 458 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c base->ctx = ctx; base 459 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c base->funcs = &dce_funcs; base 460 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c base->stored_backlight_registers.BL_PWM_CNTL = 0; base 461 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c base->stored_backlight_registers.BL_PWM_CNTL2 = 0; base 462 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0; base 463 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0; base 464 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c base->dmcu_is_running = false; base 486 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c abm_dce->base.funcs = &dce_funcs; base 488 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c return &abm_dce->base; base 495 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c if (abm_dce->base.dmcu_is_running == true) base 496 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c abm_dce->base.funcs->set_abm_immediate_disable(*abm); base 230 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h struct abm base; base 34 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c container_of(audio, struct dce_audio, base) base 37 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c aud->base.ctx base 950 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c audio->base.ctx = ctx; base 951 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c audio->base.inst = inst; base 952 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c audio->base.funcs = &funcs; base 957 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c return &audio->base; base 125 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h struct audio base; base 36 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c aux110->base.ctx base 46 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c container_of((ptr), struct aux_engine_dce110, base) base 49 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c FROM_AUX_ENGINE(container_of((ptr), struct dce_aux, base)) base 52 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c container_of((ptr), struct dce_aux, base) base 423 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c aux_engine110->base.ddc = NULL; base 424 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c aux_engine110->base.ctx = ctx; base 425 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c aux_engine110->base.delay = 0; base 426 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c aux_engine110->base.max_defer_write_retry = 0; base 427 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c aux_engine110->base.inst = inst; base 431 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c return &aux_engine110->base; base 103 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h struct dce_aux base; base 36 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c container_of(clocks, struct dce_clk_mgr, base) base 46 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->base.ctx base 254 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu; base 343 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug; base 344 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; base 401 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; base 469 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; base 814 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c struct clk_mgr *base = &clk_mgr_dce->base; base 817 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c base->ctx = ctx; base 818 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c base->funcs = &dce_funcs; base 861 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return &clk_mgr_dce->base; base 884 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->base.funcs = &dce110_funcs; base 886 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return &clk_mgr_dce->base; base 909 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->base.funcs = &dce112_funcs; base 911 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return &clk_mgr_dce->base; base 931 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->base.funcs = &dce120_funcs; base 933 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return &clk_mgr_dce->base; base 952 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c clk_mgr_dce->base.funcs = &dce120_funcs; base 954 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c return &clk_mgr_dce->base; base 46 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->base.ctx base 635 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c bp_ss_params.pll_id = clk_src->base.id; base 737 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c bp_params.pll_id = clk_src->base.id; base 1322 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->base.ctx = ctx; base 1324 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->base.id = id; base 1325 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->base.funcs = &dce110_clk_src_funcs; base 1378 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL) base 1419 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->base.ctx = ctx; base 1421 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->base.id = id; base 1422 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->base.funcs = &dce112_clk_src_funcs; base 1450 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->base.funcs = &dcn20_clk_src_funcs; base 31 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h container_of(clk_src, struct dce110_clk_src, base) base 164 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h struct clock_source base; base 38 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c container_of(dmcu, struct dce_dmcu, base) base 48 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dmcu_dce->base.ctx base 828 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c struct dmcu *base = &dmcu_dce->base; base 830 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c base->ctx = ctx; base 831 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c base->funcs = &dce_funcs; base 832 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c base->cached_wait_loop_number = 0; base 855 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dmcu_dce->base.funcs = &dce_funcs; base 857 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c return &dmcu_dce->base; base 877 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dmcu_dce->base.funcs = &dcn10_funcs; base 879 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c return &dmcu_dce->base; base 900 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dmcu_dce->base.funcs = &dcn20_funcs; base 902 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c return &dmcu_dce->base; base 910 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c if (dmcu_dce->base.dmcu_state == DMCU_RUNNING) base 911 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dmcu_dce->base.funcs->set_psr_enable(*dmcu, false, true); base 181 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h struct dmcu base; base 40 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c ipp_dce->base.ctx base 254 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c ipp_dce->base.ctx = ctx; base 255 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c ipp_dce->base.inst = inst; base 256 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c ipp_dce->base.funcs = &dce_ipp_funcs; base 32 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h container_of(ipp, struct dce_ipp, base) base 223 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h struct input_pixel_processor base; base 61 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.ctx base 63 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.ctx->logger base 129 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c struct dc_bios *bp = enc110->base.ctx->dc_bios; base 263 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c struct dc_context *ctx = enc110->base.ctx; base 393 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT); base 495 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c struct dc_context *ctx = enc110->base.ctx; base 496 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enum hpd_source_id hpd_source = enc110->base.hpd_source; base 574 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enum hpd_source_id hpd_source = enc110->base.hpd_source; base 595 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock; base 636 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.features.max_hdmi_deep_color; base 647 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock)) base 651 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c if (!enc110->base.features.hdmi_ycbcr420_supported && base 655 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c if (!enc110->base.features.flags.bits.HDMI_6GB_EN && base 658 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c if (enc110->base.ctx->dc->debug.hdmi20_disable && base 686 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.funcs = &dce110_lnk_enc_funcs; base 687 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.ctx = init_data->ctx; base 688 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.id = init_data->encoder; base 690 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.hpd_source = init_data->hpd_source; base 691 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.connector = init_data->connector; base 693 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; base 695 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.features = *enc_features; base 697 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.transmitter = init_data->transmitter; base 708 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.output_signals = base 732 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c switch (enc110->base.transmitter) { base 734 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.preferred_engine = ENGINE_ID_DIGA; base 737 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.preferred_engine = ENGINE_ID_DIGB; base 740 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.preferred_engine = ENGINE_ID_DIGC; base 743 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.preferred_engine = ENGINE_ID_DIGD; base 746 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.preferred_engine = ENGINE_ID_DIGE; base 749 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.preferred_engine = ENGINE_ID_DIGF; base 752 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.preferred_engine = ENGINE_ID_DIGG; base 756 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; base 760 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.features.flags.bits.HDMI_6GB_EN = 1; base 762 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios, base 763 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.id, &bp_cap_info); base 767 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.features.flags.bits.IS_HBR2_CAPABLE = base 769 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.features.flags.bits.IS_HBR3_CAPABLE = base 771 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; base 777 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c if (enc110->base.ctx->dc->debug.hdmi20_disable) { base 778 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c enc110->base.features.flags.bits.HDMI_6GB_EN = 0; base 835 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.transmitter = enc110->base.transmitter; base 836 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.connector_obj_id = enc110->base.connector; base 839 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.hpd_sel = enc110->base.hpd_source; base 841 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c if (enc110->base.connector.id == CONNECTOR_ID_EDP) base 853 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c if (enc110->base.connector.id == CONNECTOR_ID_LVDS) { base 927 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.connector_obj_id = enc110->base.connector; base 930 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.transmitter = enc110->base.transmitter; base 938 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.hpd_sel = enc110->base.hpd_source; base 963 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.connector_obj_id = enc110->base.connector; base 966 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.transmitter = enc110->base.transmitter; base 971 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.hpd_sel = enc110->base.hpd_source; base 1001 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.connector_obj_id = enc110->base.connector; base 1004 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.transmitter = enc110->base.transmitter; base 1008 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.hpd_sel = enc110->base.hpd_source; base 1043 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.transmitter = enc110->base.transmitter; base 1047 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.hpd_sel = enc110->base.hpd_source; base 1089 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.transmitter = enc110->base.transmitter; base 1090 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.hpd_sel = enc110->base.hpd_source; base 1092 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.connector_obj_id = enc110->base.connector; base 1123 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.transmitter = enc110->base.transmitter; base 1124 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.connector_obj_id = enc110->base.connector; base 1126 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.hpd_sel = enc110->base.hpd_source; base 1372 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c struct dc_context *ctx = enc110->base.ctx; base 1386 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c struct dc_context *ctx = enc110->base.ctx; base 32 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h container_of(link_encoder, struct dce110_link_encoder, base) base 157 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h struct link_encoder base; base 31 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.ctx base 776 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.ctx = ctx; base 778 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.inst = inst; base 779 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.funcs = &dce_mi_funcs; base 795 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.funcs = &dce112_mi_funcs; base 807 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->base.funcs = &dce120_mi_funcs; base 32 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h container_of(mem_input, struct dce_mem_input, base) base 331 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h struct mem_input base; base 43 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c opp110->base.ctx base 551 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c opp110->base.funcs = &funcs; base 553 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c opp110->base.ctx = ctx; base 555 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c opp110->base.inst = inst; base 33 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h container_of(opp, struct dce110_opp, base) base 266 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h container_of(opp, struct dce110_opp, base) base 269 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h struct output_pixel_processor base; base 34 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c enc110->base.ctx->logger base 60 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c container_of(audio, struct dce110_stream_encoder, base) base 63 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c enc110->base.ctx base 561 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c cntl.engine_id = enc110->base.id; base 567 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (enc110->base.bp->funcs->encoder_control( base 568 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c enc110->base.bp, &cntl) != BP_RESULT_OK) base 674 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c cntl.engine_id = enc110->base.id; base 681 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (enc110->base.bp->funcs->encoder_control( base 682 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c enc110->base.bp, &cntl) != BP_RESULT_OK) base 699 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c cntl.engine_id = enc110->base.id; base 705 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (enc110->base.bp->funcs->encoder_control( base 706 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c enc110->base.bp, &cntl) != BP_RESULT_OK) base 1663 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c enc110->base.funcs = &dce110_str_enc_funcs; base 1664 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c enc110->base.ctx = ctx; base 1665 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c enc110->base.id = eng_id; base 1666 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c enc110->base.bp = bp; base 32 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h container_of(stream_encoder, struct dce110_stream_encoder, base) base 698 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h struct stream_encoder base; base 40 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c xfm_dce->base.ctx base 42 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c xfm_dce->base.ctx->logger base 158 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { base 1350 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c xfm_dce->base.ctx = ctx; base 1352 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c xfm_dce->base.inst = inst; base 1353 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c xfm_dce->base.funcs = &dce_transform_funcs; base 33 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h container_of(transform, struct dce_transform, base) base 470 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h struct transform base; base 432 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &tg110->base; base 447 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &enc110->base; base 523 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &dce_mi->base; base 544 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &transform->base; base 559 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &ipp->base; base 584 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &enc110->base; base 599 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &opp->base; base 616 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &aux_engine->base; base 667 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c clk_src->base.dp_clk_src = dp_clk_src; base 668 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &clk_src->base; base 686 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 687 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.opps[i] != NULL) base 688 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce110_opp_destroy(&pool->base.opps[i]); base 690 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.transforms[i] != NULL) base 691 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce100_transform_destroy(&pool->base.transforms[i]); base 693 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.ipps[i] != NULL) base 694 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce_ipp_destroy(&pool->base.ipps[i]); base 696 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.mis[i] != NULL) { base 697 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); base 698 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.mis[i] = NULL; base 701 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.timing_generators[i] != NULL) { base 702 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); base 703 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.timing_generators[i] = NULL; base 707 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 708 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.engines[i] != NULL) base 709 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce110_engine_destroy(&pool->base.engines[i]); base 710 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.hw_i2cs[i] != NULL) { base 711 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c kfree(pool->base.hw_i2cs[i]); base 712 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.hw_i2cs[i] = NULL; base 714 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.sw_i2cs[i] != NULL) { base 715 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c kfree(pool->base.sw_i2cs[i]); base 716 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.sw_i2cs[i] = NULL; base 720 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c for (i = 0; i < pool->base.stream_enc_count; i++) { base 721 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.stream_enc[i] != NULL) base 722 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); base 725 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 726 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.clock_sources[i] != NULL) base 727 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce100_clock_source_destroy(&pool->base.clock_sources[i]); base 730 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.dp_clock_source != NULL) base 731 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce100_clock_source_destroy(&pool->base.dp_clock_source); base 733 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c for (i = 0; i < pool->base.audio_count; i++) { base 734 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.audios[i] != NULL) base 735 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce_aud_destroy(&pool->base.audios[i]); base 738 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.abm != NULL) base 739 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce_abm_destroy(&pool->base.abm); base 741 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.dmcu != NULL) base 742 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dce_dmcu_destroy(&pool->base.dmcu); base 744 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.irqs != NULL) base 745 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dal_irq_service_destroy(&pool->base.irqs); base 918 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.res_cap = &res_cap; base 919 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.funcs = &dce100_res_pool_funcs; base 920 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; base 925 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.dp_clock_source = base 928 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.clock_sources[0] = base 930 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.clock_sources[1] = base 932 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.clock_sources[2] = base 934 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.clk_src_count = 3; base 937 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.dp_clock_source = base 940 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.clock_sources[0] = base 942 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.clock_sources[1] = base 944 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.clk_src_count = 2; base 947 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.dp_clock_source == NULL) { base 953 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 954 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.clock_sources[i] == NULL) { base 961 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.dmcu = dce_dmcu_create(ctx, base 965 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.dmcu == NULL) { base 971 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.abm = dce_abm_create(ctx, base 975 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.abm == NULL) { base 984 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.irqs = dal_irq_service_dce110_create(&init_data); base 985 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (!pool->base.irqs) base 992 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; base 993 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.pipe_count = res_cap.num_timing_generator; base 994 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; base 1000 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 1001 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.timing_generators[i] = base 1006 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.timing_generators[i] == NULL) { base 1012 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.mis[i] = dce100_mem_input_create(ctx, i); base 1013 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.mis[i] == NULL) { base 1020 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.ipps[i] = dce100_ipp_create(ctx, i); base 1021 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.ipps[i] == NULL) { base 1028 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.transforms[i] = dce100_transform_create(ctx, i); base 1029 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.transforms[i] == NULL) { base 1036 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.opps[i] = dce100_opp_create(ctx, i); base 1037 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.opps[i] == NULL) { base 1045 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 1046 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.engines[i] = dce100_aux_engine_create(ctx, i); base 1047 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.engines[i] == NULL) { base 1053 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i); base 1054 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (pool->base.hw_i2cs[i] == NULL) { base 1060 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c pool->base.sw_i2cs[i] = NULL; base 1063 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c dc->caps.max_planes = pool->base.pipe_count; base 1068 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c if (!resource_construct(num_virtual_links, dc, &pool->base, base 1093 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c return &pool->base; base 41 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c cp110->base.ctx->logger base 122 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c value = dm_read_reg(cp110->base.ctx, addr); base 406 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c return &cp110->base; base 497 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.options.raw = 0; base 498 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.options.bits.FBC_SUPPORT = true; base 501 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.lpt_channels_num = 1; base 502 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.options.bits.DUMMY_BACKEND = false; base 510 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.options.bits.CLK_GATING_DISABLED = false; base 512 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.ctx = ctx; base 513 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.embedded_panel_h_size = 0; base 514 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.embedded_panel_v_size = 0; base 515 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.memory_bus_width = ctx->asic_id.vram_width; base 516 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.allocated_size = 0; base 517 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.preferred_requested_size = 0; base 518 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; base 519 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.banks_num = 0; base 520 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.raw_size = 0; base 521 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.channel_interleave_size = 0; base 522 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.dram_channels_num = 0; base 523 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.lpt_channels_num = 0; base 524 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.attached_inst = CONTROLLER_ID_UNDEFINED; base 525 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.is_enabled = false; base 526 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c compressor->base.funcs = &dce110_compressor_funcs; base 31 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h container_of(compressor, struct dce110_compressor, base) base 39 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h struct compressor base; base 45 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 53 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 74 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 88 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 110 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 124 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 157 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE); base 159 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c dm_write_reg(mem_input110->base.ctx, base 202 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 224 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 255 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 263 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 271 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 279 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 287 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 295 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 304 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 313 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 322 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 331 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 356 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 371 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 418 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 423 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 433 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 443 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 465 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c mem_input110->base.ctx, base 476 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE); base 607 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT); base 611 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c dm_write_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT, value); base 613 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL); base 617 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL, value); base 619 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL); base 622 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL, value); base 624 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C); base 628 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C, value); base 630 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C); base 633 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C, value); base 1038 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c dce_mi->base.funcs = &dce110_mem_input_v_funcs; base 1039 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c dce_mi->base.ctx = ctx; base 113 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c struct dc_context *ctx = xfm_dce->base.ctx; base 364 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c struct dc_context *ctx = xfm_dce->base.ctx; base 90 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c value = dm_read_reg(xfm_dce->base.ctx, base 99 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 113 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CONTROL, 0); base 151 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL, base 162 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 173 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 190 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 223 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c xfm_dce->base.ctx, base 255 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 287 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 319 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 351 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 383 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 415 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 447 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 464 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 467 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, base 478 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, addr, rgb->red_reg); base 479 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, addr, rgb->green_reg); base 480 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, addr, rgb->blue_reg); base 482 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, addr, base 484 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, addr, base 486 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c dm_write_reg(xfm_dce->base.ctx, addr, base 50 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c opp110->base.funcs = &funcs; base 52 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c opp110->base.ctx = ctx; base 473 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &tg110->base; base 489 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &enc110->base; base 569 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &dce_mi->base; base 590 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &transform->base; base 605 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &ipp->base; base 630 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &enc110->base; base 645 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &opp->base; base 662 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &aux_engine->base; base 713 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c clk_src->base.dp_clk_src = dp_clk_src; base 714 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &clk_src->base; base 743 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 744 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.opps[i] != NULL) base 745 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce110_opp_destroy(&pool->base.opps[i]); base 747 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.transforms[i] != NULL) base 748 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce110_transform_destroy(&pool->base.transforms[i]); base 750 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.ipps[i] != NULL) base 751 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce_ipp_destroy(&pool->base.ipps[i]); base 753 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.mis[i] != NULL) { base 754 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); base 755 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.mis[i] = NULL; base 758 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.timing_generators[i] != NULL) { base 759 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); base 760 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.timing_generators[i] = NULL; base 764 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 765 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.engines[i] != NULL) base 766 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce110_engine_destroy(&pool->base.engines[i]); base 767 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.hw_i2cs[i] != NULL) { base 768 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c kfree(pool->base.hw_i2cs[i]); base 769 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.hw_i2cs[i] = NULL; base 771 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.sw_i2cs[i] != NULL) { base 772 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c kfree(pool->base.sw_i2cs[i]); base 773 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.sw_i2cs[i] = NULL; base 777 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c for (i = 0; i < pool->base.stream_enc_count; i++) { base 778 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.stream_enc[i] != NULL) base 779 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); base 782 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 783 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.clock_sources[i] != NULL) { base 784 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce110_clock_source_destroy(&pool->base.clock_sources[i]); base 788 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.dp_clock_source != NULL) base 789 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce110_clock_source_destroy(&pool->base.dp_clock_source); base 791 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c for (i = 0; i < pool->base.audio_count; i++) { base 792 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.audios[i] != NULL) { base 793 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce_aud_destroy(&pool->base.audios[i]); base 797 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.abm != NULL) base 798 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce_abm_destroy(&pool->base.abm); base 800 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.dmcu != NULL) base 801 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dce_dmcu_destroy(&pool->base.dmcu); base 803 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.irqs != NULL) { base 804 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dal_irq_service_destroy(&pool->base.irqs); base 1192 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->opps[pool->pipe_count] = &dce110_oppv->base; base 1193 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; base 1194 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->mis[pool->pipe_count] = &dce110_miv->base; base 1195 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->transforms[pool->pipe_count] = &dce110_xfmv->base; base 1282 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); base 1283 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.funcs = &dce110_res_pool_funcs; base 1289 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.pipe_count = pool->base.res_cap->num_timing_generator; base 1290 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.underlay_pipe_index = pool->base.pipe_count; base 1291 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; base 1304 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.dp_clock_source = base 1307 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.clock_sources[0] = base 1310 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.clock_sources[1] = base 1314 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.clk_src_count = 2; base 1319 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.dp_clock_source == NULL) { base 1325 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 1326 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.clock_sources[i] == NULL) { base 1333 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.dmcu = dce_dmcu_create(ctx, base 1337 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.dmcu == NULL) { base 1343 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.abm = dce_abm_create(ctx, base 1347 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.abm == NULL) { base 1356 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.irqs = dal_irq_service_dce110_create(&init_data); base 1357 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (!pool->base.irqs) base 1361 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 1362 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.timing_generators[i] = dce110_timing_generator_create( base 1364 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.timing_generators[i] == NULL) { base 1370 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.mis[i] = dce110_mem_input_create(ctx, i); base 1371 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.mis[i] == NULL) { base 1378 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.ipps[i] = dce110_ipp_create(ctx, i); base 1379 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.ipps[i] == NULL) { base 1386 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.transforms[i] = dce110_transform_create(ctx, i); base 1387 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.transforms[i] == NULL) { base 1394 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.opps[i] = dce110_opp_create(ctx, i); base 1395 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.opps[i] == NULL) { base 1403 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 1404 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.engines[i] = dce110_aux_engine_create(ctx, i); base 1405 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.engines[i] == NULL) { base 1411 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i); base 1412 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pool->base.hw_i2cs[i] == NULL) { base 1418 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pool->base.sw_i2cs[i] = NULL; base 1424 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (!underlay_create(ctx, &pool->base)) base 1427 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (!resource_construct(num_virtual_links, dc, &pool->base, base 1434 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dc->caps.max_planes = pool->base.pipe_count; base 1436 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c for (i = 0; i < pool->base.underlay_pipe_index; ++i) base 1439 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap; base 1464 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c return &pool->base; base 35 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h container_of(pool, struct dce110_resource_pool, base) base 38 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h struct resource_pool base; base 347 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->base.funcs->enable_advanced_request(tg, true, &patched_crtc_timing); base 2251 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->base.inst = instance; base 2255 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->base.funcs = &dce110_tg_funcs; base 2257 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->base.ctx = ctx; base 2258 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tg110->base.bp = ctx->dc_bios; base 97 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h struct timing_generator base; base 118 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h container_of(tg, struct dce110_timing_generator, base) base 695 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->base.funcs = &dce110_tg_v_funcs; base 697 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->base.ctx = ctx; base 698 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tg110->base.bp = ctx->dc_bios; base 84 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c struct dc_context *ctx = xfm_dce->base.ctx; base 164 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c struct dc_context *ctx = xfm_dce->base.ctx; base 240 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { base 266 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c dm_write_reg(xfm_dce->base.ctx, base 270 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c dm_write_reg(xfm_dce->base.ctx, base 280 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c value = dm_read_reg(xfm_dce->base.ctx, mmSCLV_UPDATE); base 282 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c dm_write_reg(xfm_dce->base.ctx, mmSCLV_UPDATE, value); base 291 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c struct dc_context *ctx = xfm_dce->base.ctx; base 396 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c struct dc_context *ctx = xfm_dce->base.ctx; base 511 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c value = dm_read_reg(xfm_dce->base.ctx, mmLBV_MEMORY_CTRL); base 519 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c dm_write_reg(xfm_dce->base.ctx, mmLBV_MEMORY_CTRL, value); base 705 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c xfm_dce->base.ctx = ctx; base 707 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c xfm_dce->base.funcs = &dce110_xfmv_funcs; base 40 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c cp110->base.ctx->logger base 104 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c return cp110->base.raw_size * cp110->base.banks_num * base 105 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c cp110->base.dram_channels_num; base 112 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (cp110->base.options.bits.LPT_MC_CONFIG == 1) { base 120 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c switch (cp110->base.dram_channels_num) { base 151 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c switch (cp110->base.banks_num) { base 198 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c switch (cp110->base.channel_interleave_size) { base 234 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c switch (cp110->base.raw_size) { base 276 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (cp110->base.embedded_panel_h_size != 0 && base 277 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c cp110->base.embedded_panel_v_size != 0 && base 279 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c (cp110->base.embedded_panel_h_size * base 280 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c cp110->base.embedded_panel_v_size))) base 302 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c value = dm_read_reg(cp110->base.ctx, addr); base 796 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.raw = 0; base 797 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.bits.FBC_SUPPORT = true; base 798 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.bits.LPT_SUPPORT = true; base 800 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.lpt_channels_num = 1; base 801 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.bits.DUMMY_BACKEND = false; base 805 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (compressor->base.memory_bus_width == 64) base 806 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.bits.LPT_SUPPORT = false; base 808 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.options.bits.CLK_GATING_DISABLED = false; base 810 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.ctx = ctx; base 811 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.embedded_panel_h_size = 0; base 812 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.embedded_panel_v_size = 0; base 813 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.memory_bus_width = ctx->asic_id.vram_width; base 814 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.allocated_size = 0; base 815 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.preferred_requested_size = 0; base 816 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; base 817 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.banks_num = 0; base 818 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.raw_size = 0; base 819 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.channel_interleave_size = 0; base 820 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.dram_channels_num = 0; base 821 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.lpt_channels_num = 0; base 822 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.attached_inst = 0; base 823 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.is_enabled = false; base 827 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.embedded_panel_h_size = base 829 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c compressor->base.embedded_panel_v_size = base 843 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c return &cp110->base; base 31 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h container_of(compressor, struct dce112_compressor, base) base 39 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h struct compressor base; base 451 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &tg110->base; base 467 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &enc110->base; base 537 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &dce_mi->base; base 559 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &transform->base; base 588 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &enc110->base; base 603 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &ipp->base; base 618 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &opp->base; base 635 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &aux_engine->base; base 686 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c clk_src->base.dp_clk_src = dp_clk_src; base 687 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &clk_src->base; base 705 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 706 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.opps[i] != NULL) base 707 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce110_opp_destroy(&pool->base.opps[i]); base 709 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.transforms[i] != NULL) base 710 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce112_transform_destroy(&pool->base.transforms[i]); base 712 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.ipps[i] != NULL) base 713 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce_ipp_destroy(&pool->base.ipps[i]); base 715 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.mis[i] != NULL) { base 716 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); base 717 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.mis[i] = NULL; base 720 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.timing_generators[i] != NULL) { base 721 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); base 722 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.timing_generators[i] = NULL; base 726 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 727 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.engines[i] != NULL) base 728 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce110_engine_destroy(&pool->base.engines[i]); base 729 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.hw_i2cs[i] != NULL) { base 730 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c kfree(pool->base.hw_i2cs[i]); base 731 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.hw_i2cs[i] = NULL; base 733 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.sw_i2cs[i] != NULL) { base 734 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c kfree(pool->base.sw_i2cs[i]); base 735 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.sw_i2cs[i] = NULL; base 739 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c for (i = 0; i < pool->base.stream_enc_count; i++) { base 740 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.stream_enc[i] != NULL) base 741 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); base 744 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 745 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.clock_sources[i] != NULL) { base 746 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce112_clock_source_destroy(&pool->base.clock_sources[i]); base 750 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.dp_clock_source != NULL) base 751 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce112_clock_source_destroy(&pool->base.dp_clock_source); base 753 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c for (i = 0; i < pool->base.audio_count; i++) { base 754 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.audios[i] != NULL) { base 755 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce_aud_destroy(&pool->base.audios[i]); base 759 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.abm != NULL) base 760 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce_abm_destroy(&pool->base.abm); base 762 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.dmcu != NULL) base 763 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dce_dmcu_destroy(&pool->base.dmcu); base 765 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.irqs != NULL) { base 766 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dal_irq_service_destroy(&pool->base.irqs); base 1153 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); base 1154 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.funcs = &dce112_res_pool_funcs; base 1159 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; base 1160 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.pipe_count = pool->base.res_cap->num_timing_generator; base 1161 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; base 1172 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.clock_sources[DCE112_CLK_SRC_PLL0] = base 1177 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.clock_sources[DCE112_CLK_SRC_PLL1] = base 1182 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.clock_sources[DCE112_CLK_SRC_PLL2] = base 1187 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.clock_sources[DCE112_CLK_SRC_PLL3] = base 1192 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.clock_sources[DCE112_CLK_SRC_PLL4] = base 1197 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.clock_sources[DCE112_CLK_SRC_PLL5] = base 1202 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL; base 1204 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.dp_clock_source = dce112_clock_source_create( base 1209 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 1210 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.clock_sources[i] == NULL) { base 1217 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.dmcu = dce_dmcu_create(ctx, base 1221 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.dmcu == NULL) { base 1227 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.abm = dce_abm_create(ctx, base 1231 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.abm == NULL) { base 1240 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.irqs = dal_irq_service_dce110_create(&init_data); base 1241 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (!pool->base.irqs) base 1245 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 1246 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.timing_generators[i] = base 1251 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.timing_generators[i] == NULL) { base 1257 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.mis[i] = dce112_mem_input_create(ctx, i); base 1258 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.mis[i] == NULL) { base 1265 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.ipps[i] = dce112_ipp_create(ctx, i); base 1266 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.ipps[i] == NULL) { base 1273 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.transforms[i] = dce112_transform_create(ctx, i); base 1274 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.transforms[i] == NULL) { base 1281 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.opps[i] = dce112_opp_create( base 1284 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.opps[i] == NULL) { base 1292 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 1293 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.engines[i] = dce112_aux_engine_create(ctx, i); base 1294 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.engines[i] == NULL) { base 1300 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i); base 1301 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (pool->base.hw_i2cs[i] == NULL) { base 1307 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c pool->base.sw_i2cs[i] = NULL; base 1310 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c if (!resource_construct(num_virtual_links, dc, &pool->base, base 1314 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c dc->caps.max_planes = pool->base.pipe_count; base 1344 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c return &pool->base; base 393 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &opp->base; base 409 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &aux_engine->base; base 499 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c clk_src->base.dp_clk_src = dp_clk_src; base 500 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &clk_src->base; base 539 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &tg110->base; base 552 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 553 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.opps[i] != NULL) base 554 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce110_opp_destroy(&pool->base.opps[i]); base 556 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.transforms[i] != NULL) base 557 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce120_transform_destroy(&pool->base.transforms[i]); base 559 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.ipps[i] != NULL) base 560 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce_ipp_destroy(&pool->base.ipps[i]); base 562 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.mis[i] != NULL) { base 563 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); base 564 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.mis[i] = NULL; base 567 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.irqs != NULL) { base 568 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dal_irq_service_destroy(&pool->base.irqs); base 571 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.timing_generators[i] != NULL) { base 572 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); base 573 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.timing_generators[i] = NULL; base 577 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 578 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.engines[i] != NULL) base 579 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce110_engine_destroy(&pool->base.engines[i]); base 580 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.hw_i2cs[i] != NULL) { base 581 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c kfree(pool->base.hw_i2cs[i]); base 582 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.hw_i2cs[i] = NULL; base 584 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.sw_i2cs[i] != NULL) { base 585 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c kfree(pool->base.sw_i2cs[i]); base 586 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.sw_i2cs[i] = NULL; base 590 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c for (i = 0; i < pool->base.audio_count; i++) { base 591 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.audios[i]) base 592 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce_aud_destroy(&pool->base.audios[i]); base 595 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c for (i = 0; i < pool->base.stream_enc_count; i++) { base 596 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.stream_enc[i] != NULL) base 597 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); base 600 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 601 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.clock_sources[i] != NULL) base 603 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c &pool->base.clock_sources[i]); base 606 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.dp_clock_source != NULL) base 607 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce120_clock_source_destroy(&pool->base.dp_clock_source); base 609 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.abm != NULL) base 610 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce_abm_destroy(&pool->base.abm); base 612 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.dmcu != NULL) base 613 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dce_dmcu_destroy(&pool->base.dmcu); base 669 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &enc110->base; base 684 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &ipp->base; base 700 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &enc110->base; base 806 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &dce_mi->base; base 822 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &transform->base; base 996 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.res_cap = &res_cap; base 997 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.funcs = &dce120_res_pool_funcs; base 1000 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.pipe_count = res_cap.num_timing_generator; base 1001 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; base 1002 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; base 1016 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.clock_sources[DCE120_CLK_SRC_PLL0] = base 1020 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.clock_sources[DCE120_CLK_SRC_PLL1] = base 1024 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.clock_sources[DCE120_CLK_SRC_PLL2] = base 1028 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.clock_sources[DCE120_CLK_SRC_PLL3] = base 1032 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.clock_sources[DCE120_CLK_SRC_PLL4] = base 1036 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.clock_sources[DCE120_CLK_SRC_PLL5] = base 1040 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL; base 1042 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.dp_clock_source = base 1047 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 1048 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.clock_sources[i] == NULL) { base 1055 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.dmcu = dce_dmcu_create(ctx, base 1059 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.dmcu == NULL) { base 1065 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.abm = dce_abm_create(ctx, base 1069 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.abm == NULL) { base 1077 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); base 1078 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (!pool->base.irqs) base 1087 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 1095 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.timing_generators[j] = base 1100 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.timing_generators[j] == NULL) { base 1106 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.mis[j] = dce120_mem_input_create(ctx, i); base 1108 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.mis[j] == NULL) { base 1115 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.ipps[j] = dce120_ipp_create(ctx, i); base 1116 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.ipps[i] == NULL) { base 1123 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.transforms[j] = dce120_transform_create(ctx, i); base 1124 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.transforms[i] == NULL) { base 1131 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.opps[j] = dce120_opp_create( base 1134 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.opps[j] == NULL) { base 1144 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 1145 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.engines[i] = dce120_aux_engine_create(ctx, i); base 1146 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.engines[i] == NULL) { base 1152 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i); base 1153 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (pool->base.hw_i2cs[i] == NULL) { base 1159 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.sw_i2cs[i] = NULL; base 1163 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.pipe_count = j; base 1164 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c pool->base.timing_generator_count = j; base 1171 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs)) base 1178 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c dc->caps.max_planes = pool->base.pipe_count; base 1210 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c return &pool->base; base 43 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__) base 46 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__) base 1247 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->base.inst = instance; base 1251 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->base.funcs = &dce120_tg_funcs; base 1253 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->base.ctx = ctx; base 1254 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tg110->base.bp = ctx->dc_bios; base 464 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &tg110->base; base 479 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &opp->base; base 496 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &aux_engine->base; base 559 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &enc110->base; base 635 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &dce_mi->base; base 657 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &transform->base; base 682 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &enc110->base; base 700 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c clk_src->base.dp_clk_src = dp_clk_src; base 701 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &clk_src->base; base 727 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &ipp->base; base 734 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 735 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.opps[i] != NULL) base 736 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce110_opp_destroy(&pool->base.opps[i]); base 738 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.transforms[i] != NULL) base 739 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_transform_destroy(&pool->base.transforms[i]); base 741 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.ipps[i] != NULL) base 742 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce_ipp_destroy(&pool->base.ipps[i]); base 744 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.mis[i] != NULL) { base 745 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); base 746 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.mis[i] = NULL; base 749 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.timing_generators[i] != NULL) { base 750 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); base 751 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.timing_generators[i] = NULL; base 755 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 756 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.engines[i] != NULL) base 757 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce110_engine_destroy(&pool->base.engines[i]); base 758 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.hw_i2cs[i] != NULL) { base 759 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c kfree(pool->base.hw_i2cs[i]); base 760 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.hw_i2cs[i] = NULL; base 762 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.sw_i2cs[i] != NULL) { base 763 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c kfree(pool->base.sw_i2cs[i]); base 764 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.sw_i2cs[i] = NULL; base 768 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.stream_enc_count; i++) { base 769 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.stream_enc[i] != NULL) base 770 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); base 773 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 774 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.clock_sources[i] != NULL) { base 775 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_destroy(&pool->base.clock_sources[i]); base 779 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.abm != NULL) base 780 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce_abm_destroy(&pool->base.abm); base 782 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.dmcu != NULL) base 783 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce_dmcu_destroy(&pool->base.dmcu); base 785 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.dp_clock_source != NULL) base 786 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce80_clock_source_destroy(&pool->base.dp_clock_source); base 788 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.audio_count; i++) { base 789 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.audios[i] != NULL) { base 790 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dce_aud_destroy(&pool->base.audios[i]); base 794 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.irqs != NULL) { base 795 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dal_irq_service_destroy(&pool->base.irqs); base 884 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.res_cap = &res_cap; base 885 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.funcs = &dce80_res_pool_funcs; base 891 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; base 892 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.pipe_count = res_cap.num_timing_generator; base 893 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.timing_generator_count = res_cap.num_timing_generator; base 906 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.dp_clock_source = base 909 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[0] = base 911 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[1] = base 913 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[2] = base 915 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clk_src_count = 3; base 918 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.dp_clock_source = base 921 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[0] = base 923 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[1] = base 925 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clk_src_count = 2; base 928 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.dp_clock_source == NULL) { base 934 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 935 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.clock_sources[i] == NULL) { base 942 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.dmcu = dce_dmcu_create(ctx, base 946 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.dmcu == NULL) { base 952 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.abm = dce_abm_create(ctx, base 956 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.abm == NULL) { base 965 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.irqs = dal_irq_service_dce80_create(&init_data); base 966 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (!pool->base.irqs) base 970 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 971 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.timing_generators[i] = dce80_timing_generator_create( base 973 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.timing_generators[i] == NULL) { base 979 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.mis[i] = dce80_mem_input_create(ctx, i); base 980 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.mis[i] == NULL) { base 986 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.ipps[i] = dce80_ipp_create(ctx, i); base 987 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.ipps[i] == NULL) { base 993 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.transforms[i] = dce80_transform_create(ctx, i); base 994 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.transforms[i] == NULL) { base 1000 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.opps[i] = dce80_opp_create(ctx, i); base 1001 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.opps[i] == NULL) { base 1008 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 1009 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.engines[i] = dce80_aux_engine_create(ctx, i); base 1010 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.engines[i] == NULL) { base 1016 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); base 1017 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.hw_i2cs[i] == NULL) { base 1023 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); base 1024 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.sw_i2cs[i] == NULL) { base 1032 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dc->caps.max_planes = pool->base.pipe_count; base 1039 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (!resource_construct(num_virtual_links, dc, &pool->base, base 1064 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &pool->base; base 1081 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.res_cap = &res_cap_81; base 1082 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.funcs = &dce80_res_pool_funcs; base 1088 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; base 1089 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.pipe_count = res_cap_81.num_timing_generator; base 1090 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.timing_generator_count = res_cap_81.num_timing_generator; base 1103 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.dp_clock_source = base 1106 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[0] = base 1108 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[1] = base 1110 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[2] = base 1112 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clk_src_count = 3; base 1115 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.dp_clock_source = base 1118 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[0] = base 1120 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[1] = base 1122 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clk_src_count = 2; base 1125 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.dp_clock_source == NULL) { base 1131 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 1132 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.clock_sources[i] == NULL) { base 1139 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.dmcu = dce_dmcu_create(ctx, base 1143 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.dmcu == NULL) { base 1149 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.abm = dce_abm_create(ctx, base 1153 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.abm == NULL) { base 1162 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.irqs = dal_irq_service_dce80_create(&init_data); base 1163 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (!pool->base.irqs) base 1167 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 1168 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.timing_generators[i] = dce80_timing_generator_create( base 1170 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.timing_generators[i] == NULL) { base 1176 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.mis[i] = dce80_mem_input_create(ctx, i); base 1177 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.mis[i] == NULL) { base 1183 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.ipps[i] = dce80_ipp_create(ctx, i); base 1184 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.ipps[i] == NULL) { base 1190 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.transforms[i] = dce80_transform_create(ctx, i); base 1191 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.transforms[i] == NULL) { base 1197 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.opps[i] = dce80_opp_create(ctx, i); base 1198 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.opps[i] == NULL) { base 1205 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 1206 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.engines[i] = dce80_aux_engine_create(ctx, i); base 1207 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.engines[i] == NULL) { base 1213 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); base 1214 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.hw_i2cs[i] == NULL) { base 1220 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); base 1221 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.sw_i2cs[i] == NULL) { base 1229 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dc->caps.max_planes = pool->base.pipe_count; base 1236 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (!resource_construct(num_virtual_links, dc, &pool->base, base 1261 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &pool->base; base 1278 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.res_cap = &res_cap_83; base 1279 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.funcs = &dce80_res_pool_funcs; base 1285 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; base 1286 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.pipe_count = res_cap_83.num_timing_generator; base 1287 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.timing_generator_count = res_cap_83.num_timing_generator; base 1300 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.dp_clock_source = base 1303 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[0] = base 1305 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[1] = base 1307 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clk_src_count = 2; base 1310 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.dp_clock_source = base 1313 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clock_sources[0] = base 1315 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.clk_src_count = 1; base 1318 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.dp_clock_source == NULL) { base 1324 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 1325 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.clock_sources[i] == NULL) { base 1332 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.dmcu = dce_dmcu_create(ctx, base 1336 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.dmcu == NULL) { base 1342 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.abm = dce_abm_create(ctx, base 1346 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.abm == NULL) { base 1355 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.irqs = dal_irq_service_dce80_create(&init_data); base 1356 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (!pool->base.irqs) base 1360 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 1361 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.timing_generators[i] = dce80_timing_generator_create( base 1363 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.timing_generators[i] == NULL) { base 1369 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.mis[i] = dce80_mem_input_create(ctx, i); base 1370 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.mis[i] == NULL) { base 1376 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.ipps[i] = dce80_ipp_create(ctx, i); base 1377 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.ipps[i] == NULL) { base 1383 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.transforms[i] = dce80_transform_create(ctx, i); base 1384 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.transforms[i] == NULL) { base 1390 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.opps[i] = dce80_opp_create(ctx, i); base 1391 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.opps[i] == NULL) { base 1398 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 1399 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.engines[i] = dce80_aux_engine_create(ctx, i); base 1400 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.engines[i] == NULL) { base 1406 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); base 1407 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.hw_i2cs[i] == NULL) { base 1413 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); base 1414 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (pool->base.sw_i2cs[i] == NULL) { base 1422 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c dc->caps.max_planes = pool->base.pipe_count; base 1429 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c if (!resource_construct(num_virtual_links, dc, &pool->base, base 1454 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c return &pool->base; base 231 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->base.inst = instance; base 235 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->base.funcs = &dce80_tg_funcs; base 237 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->base.ctx = ctx; base 238 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c tg110->base.bp = ctx->dc_bios; base 45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->base.ctx base 569 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->base.ctx = ctx; base 571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->base.inst = inst; base 572 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->base.funcs = &dcn10_dpp_funcs; base 573 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->base.caps = &dcn10_dpp_cap; base 31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h container_of(dpp, struct dcn10_dpp, base) base 1345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct dpp base; base 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx base 149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx, base 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx, base 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx, base 251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx, base 406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); base 435 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); base 505 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->base.ctx, base 560 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); base 588 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); base 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->base.ctx base 207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { base 489 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (dpp->base.ctx->dc->debug.use_max_lb) base 492 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->base.caps->dscl_calc_lb_num_partitions( base 499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->base.caps->dscl_calc_lb_num_partitions( base 508 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->base.caps->dscl_calc_lb_num_partitions( base 516 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->base.caps->dscl_calc_lb_num_partitions( base 647 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) base 661 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c - visual_confirm_on * 4 * (dpp->base.inst + 1)); base 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c dwbc10->base.ctx base 45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c container_of(dwbc_base, struct dcn10_dwbc, base) base 125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c dwbc10->base.ctx = ctx; base 127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c dwbc10->base.inst = inst; base 128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c dwbc10->base.funcs = &dcn10_dwbc_funcs; base 256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h struct dwbc base; base 34 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1->base.ctx base 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1->base.ctx->logger base 860 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dc *dc = hubbub1->base.ctx->dc; base 873 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c if (!hubbub1->base.funcs->dcc_support_pixel_format(input->format, &bpe)) base 876 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c if (!hubbub1->base.funcs->dcc_support_swizzle(input->swizzle_mode, bpe, base 960 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1->base.ctx = ctx; base 962 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1->base.funcs = &hubbub1_funcs; base 33 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h container_of(hubbub, struct dcn10_hubbub, base) base 302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h struct hubbub base; base 35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1->base.ctx base 1261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1->base.funcs = &dcn10_hubp_funcs; base 1262 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1->base.ctx = ctx; base 1266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1->base.inst = inst; base 1267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1->base.opp_id = OPP_ID_INVALID; base 1268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1->base.mpcc_id = 0xf; base 31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h container_of(hubp, struct dcn10_hubp, base) base 653 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp base; base 40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c ippn10->base.ctx base 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c ippn10->base.ctx = ctx; base 71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c ippn10->base.inst = inst; base 72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c ippn10->base.funcs = &dcn10_ipp_funcs; base 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c ippn10->base.ctx = ctx; base 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c ippn10->base.inst = inst; base 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c ippn10->base.funcs = &dcn20_ipp_funcs; base 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h container_of(ipp, struct dcn10_ipp, base) base 183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h struct input_pixel_processor base; base 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.ctx base 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.ctx->logger base 101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c struct dc_bios *bp = enc10->base.ctx->dc_bios; base 363 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT); base 562 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enum hpd_source_id hpd_source = enc10->base.hpd_source; base 583 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock; base 624 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.features.max_hdmi_deep_color; base 635 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10))) base 639 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c if (!enc10->base.features.hdmi_ycbcr420_supported && base 643 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c if (!enc10->base.features.flags.bits.HDMI_6GB_EN && base 646 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c if (enc10->base.ctx->dc->debug.hdmi20_disable && base 657 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c if (!enc10->base.features.dp_ycbcr420_supported) base 678 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.funcs = &dcn10_lnk_enc_funcs; base 679 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.ctx = init_data->ctx; base 680 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.id = init_data->encoder; base 682 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.hpd_source = init_data->hpd_source; base 683 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.connector = init_data->connector; base 685 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; base 687 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.features = *enc_features; base 689 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.transmitter = init_data->transmitter; base 700 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.output_signals = base 726 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c switch (enc10->base.transmitter) { base 728 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGA; base 731 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGB; base 734 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGC; base 737 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGD; base 740 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGE; base 743 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGF; base 746 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGG; base 750 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; base 754 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.features.flags.bits.HDMI_6GB_EN = 1; base 756 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios, base 757 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.id, &bp_cap_info); base 761 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.features.flags.bits.IS_HBR2_CAPABLE = base 763 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.features.flags.bits.IS_HBR3_CAPABLE = base 765 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; base 766 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.features.flags.bits.DP_IS_USB_C = base 773 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c if (enc10->base.ctx->dc->debug.hdmi20_disable) { base 774 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enc10->base.features.flags.bits.HDMI_6GB_EN = 0; base 828 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.transmitter = enc10->base.transmitter; base 829 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.connector_obj_id = enc10->base.connector; base 832 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.hpd_sel = enc10->base.hpd_source; base 834 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c if (enc10->base.connector.id == CONNECTOR_ID_EDP) base 846 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c if (enc10->base.connector.id == CONNECTOR_ID_LVDS) { base 924 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.transmitter = enc10->base.transmitter; base 932 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.hpd_sel = enc10->base.hpd_source; base 966 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.transmitter = enc10->base.transmitter; base 970 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.hpd_sel = enc10->base.hpd_source; base 1005 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.transmitter = enc10->base.transmitter; base 1009 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.hpd_sel = enc10->base.hpd_source; base 1055 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.transmitter = enc10->base.transmitter; base 1056 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.hpd_sel = enc10->base.hpd_source; base 1058 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.connector_obj_id = enc10->base.connector; base 1089 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.transmitter = enc10->base.transmitter; base 1090 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.connector_obj_id = enc10->base.connector; base 1092 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.hpd_sel = enc10->base.hpd_source; base 1391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c enum hpd_source_id hpd_source = enc10->base.hpd_source; base 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h container_of(link_encoder, struct dcn10_link_encoder, base) base 395 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h struct link_encoder base; base 33 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc10->base.ctx base 477 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc10->base.ctx = ctx; base 479 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc10->base.funcs = &dcn10_mpc_funcs; base 489 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc1_init_mpcc(&mpc10->base.mpcc_array[i], i); base 31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h container_of(mpc_base, struct dcn10_mpc, base) base 119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h struct mpc base; base 40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c oppn10->base.ctx base 415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c oppn10->base.ctx = ctx; base 416 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c oppn10->base.inst = inst; base 417 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c oppn10->base.funcs = &dcn10_opp_funcs; base 31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h container_of(opp, struct dcn10_opp, base) base 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h struct output_pixel_processor base; base 35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->base.ctx base 1522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->base.funcs = &dcn10_tg_funcs; base 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h container_of(tg, struct optc, base) base 499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h struct timing_generator base; base 597 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &dpp->base; base 613 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &ipp->base; base 630 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &opp->base; base 647 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &aux_engine->base; base 697 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &mpc10->base; base 708 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c hubbub1_construct(&dcn10_hubbub->base, ctx, base 713 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &dcn10_hubbub->base; base 726 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c tgn10->base.inst = instance; base 727 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c tgn10->base.ctx = ctx; base 735 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &tgn10->base; base 767 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &enc10->base; base 785 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c clk_src->base.dp_clk_src = dp_clk_src; base 786 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &clk_src->base; base 822 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &enc1->base; base 889 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c for (i = 0; i < pool->base.stream_enc_count; i++) { base 890 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.stream_enc[i] != NULL) { base 891 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); base 892 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.stream_enc[i] = NULL; base 896 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.mpc != NULL) { base 897 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kfree(TO_DCN10_MPC(pool->base.mpc)); base 898 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.mpc = NULL; base 901 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.hubbub != NULL) { base 902 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kfree(pool->base.hubbub); base 903 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.hubbub = NULL; base 906 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 907 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.opps[i] != NULL) base 908 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); base 910 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.dpps[i] != NULL) base 911 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dcn10_dpp_destroy(&pool->base.dpps[i]); base 913 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.ipps[i] != NULL) base 914 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); base 916 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.hubps[i] != NULL) { base 917 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kfree(TO_DCN10_HUBP(pool->base.hubps[i])); base 918 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.hubps[i] = NULL; base 921 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.irqs != NULL) { base 922 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dal_irq_service_destroy(&pool->base.irqs); base 925 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.timing_generators[i] != NULL) { base 926 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); base 927 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.timing_generators[i] = NULL; base 931 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 932 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.engines[i] != NULL) base 933 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dce110_engine_destroy(&pool->base.engines[i]); base 934 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.hw_i2cs[i] != NULL) { base 935 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kfree(pool->base.hw_i2cs[i]); base 936 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.hw_i2cs[i] = NULL; base 938 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.sw_i2cs[i] != NULL) { base 939 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kfree(pool->base.sw_i2cs[i]); base 940 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.sw_i2cs[i] = NULL; base 944 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c for (i = 0; i < pool->base.audio_count; i++) { base 945 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.audios[i]) base 946 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dce_aud_destroy(&pool->base.audios[i]); base 949 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 950 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.clock_sources[i] != NULL) { base 951 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dcn10_clock_source_destroy(&pool->base.clock_sources[i]); base 952 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.clock_sources[i] = NULL; base 956 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.dp_clock_source != NULL) { base 957 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dcn10_clock_source_destroy(&pool->base.dp_clock_source); base 958 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.dp_clock_source = NULL; base 961 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.abm != NULL) base 962 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dce_abm_destroy(&pool->base.abm); base 964 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.dmcu != NULL) base 965 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dce_dmcu_destroy(&pool->base.dmcu); base 967 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kfree(pool->base.pp_smu); base 982 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &hubp1->base; base 1284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.res_cap = &rv2_res_cap; base 1286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.res_cap = &res_cap; base 1287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.funcs = &dcn10_res_pool_funcs; base 1297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; base 1300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.pipe_count = pool->base.res_cap->num_timing_generator; base 1303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.pipe_count = 3; base 1323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = base 1327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = base 1331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = base 1337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = base 1343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; base 1346 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; base 1348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.dp_clock_source = base 1354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 1355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.clock_sources[i] == NULL) { base 1362 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.dmcu = dcn10_dmcu_create(ctx, base 1366 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.dmcu == NULL) { base 1372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.abm = dce_abm_create(ctx, base 1376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.abm == NULL) { base 1418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.pp_smu = dcn10_pp_smu_create(ctx); base 1424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.pp_smu != NULL base 1425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) base 1432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dc->res_pool = &pool->base; base 1439 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.irqs = dal_irq_service_dcn10_create(&init_data); base 1440 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (!pool->base.irqs) base 1447 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 1454 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.hubps[j] = dcn10_hubp_create(ctx, i); base 1455 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.hubps[j] == NULL) { base 1462 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.ipps[j] = dcn10_ipp_create(ctx, i); base 1463 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.ipps[j] == NULL) { base 1470 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.dpps[j] = dcn10_dpp_create(ctx, i); base 1471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.dpps[j] == NULL) { base 1478 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.opps[j] = dcn10_opp_create(ctx, i); base 1479 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.opps[j] == NULL) { base 1486 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.timing_generators[j] = dcn10_timing_generator_create( base 1488 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.timing_generators[j] == NULL) { base 1497 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 1498 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); base 1499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.engines[i] == NULL) { base 1505 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); base 1506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.hw_i2cs[i] == NULL) { base 1512 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.sw_i2cs[i] = NULL; base 1516 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.pipe_count = j; base 1517 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.timing_generator_count = j; base 1522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dc->dml.ip.max_num_dpp = pool->base.pipe_count; base 1523 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dc->dcn_ip->max_num_dpp = pool->base.pipe_count; base 1525 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.mpc = dcn10_mpc_create(ctx); base 1526 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.mpc == NULL) { base 1532 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.hubbub = dcn10_hubbub_create(ctx); base 1533 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.hubbub == NULL) { base 1539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (!resource_construct(num_virtual_links, dc, &pool->base, base 1545 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dc->caps.max_planes = pool->base.pipe_count; base 1572 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return &pool->base; base 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h container_of(pool, struct dcn10_resource_pool, base) base 39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h struct resource_pool base; base 34 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c enc1->base.ctx->logger base 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c enc1->base.ctx base 502 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c cntl.engine_id = enc1->base.id; base 508 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c if (enc1->base.bp->funcs->encoder_control( base 509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c enc1->base.bp, &cntl) != BP_RESULT_OK) base 608 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c cntl.engine_id = enc1->base.id; base 615 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c if (enc1->base.bp->funcs->encoder_control( base 616 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c enc1->base.bp, &cntl) != BP_RESULT_OK) base 1603 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c enc1->base.funcs = &dcn10_str_enc_funcs; base 1604 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c enc1->base.ctx = ctx; base 1605 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c enc1->base.id = eng_id; base 1606 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c enc1->base.bp = bp; base 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h container_of(stream_encoder, struct dcn10_stream_encoder, base) base 505 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h struct stream_encoder base; base 33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c container_of(dccg, struct dcn_dccg, base) base 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c dccg_dcn->base.ctx base 125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) { base 163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c struct dccg *base; base 170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c base = &dccg_dcn->base; base 171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c base->ctx = ctx; base 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c base->funcs = &dccg2_funcs; base 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c return &dccg_dcn->base; base 94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h struct dccg base; base 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->base.ctx base 502 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->base.ctx = ctx; base 504 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->base.inst = inst; base 505 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->base.funcs = &dcn20_dpp_funcs; base 506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->base.caps = &dcn20_dpp_cap; base 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h container_of(dpp, struct dcn20_dpp, base) base 627 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct dpp base; base 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp->base.ctx base 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); base 286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); base 62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc20->base.ctx base 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc->base.ctx = ctx; base 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc->base.inst = inst; base 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc->base.funcs = &dcn20_dsc_funcs; base 699 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) { base 33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h container_of(dsc, struct dcn20_dsc, base) base 555 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h struct display_stream_compressor base; base 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c dwbc20->base.ctx base 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c dwbc20->base.ctx->logger base 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c DC_LOG_DWB("%s SUPPORTED! inst = %d", __func__, dwbc20->base.inst); base 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c DC_LOG_DWB("%s NOT SUPPORTED! inst = %d", __func__, dwbc20->base.inst); base 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst); base 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst); base 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c DC_LOG_DWB("%s inst = %d, ENABLED", __func__, dwbc20->base.inst); base 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c DC_LOG_DWB("%s inst = %d, Disabled", __func__, dwbc20->base.inst); base 166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst); base 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c DC_LOG_DWB("%s inst = %d, scaling", __func__, dwbc20->base.inst); base 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c dwbc20->base.inst, stereo_params->stereo_enabled); base 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst); base 239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst); base 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst); base 323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c dwbc20->base.ctx = ctx; base 325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c dwbc20->base.inst = inst; base 326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c dwbc20->base.funcs = &dcn20_dwbc_funcs; base 28 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h container_of(dwbc_base, struct dcn20_dwbc, base) base 416 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h struct dwbc base; base 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c dwbc20->base.ctx base 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c container_of(dwbc_base, struct dcn20_dwbc, base) base 35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1->base.ctx base 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1->base.ctx base 581 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true && base 582 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false) base 612 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub->base.ctx = ctx; base 614 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub->base.funcs = &hubbub2_funcs; base 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h container_of(hubbub, struct dcn20_hubbub, base) base 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h struct hubbub base; base 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2->base.ctx base 1280 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2->base.funcs = &dcn20_hubp_funcs; base 1281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2->base.ctx = ctx; base 1285 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2->base.inst = inst; base 1286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2->base.opp_id = OPP_ID_INVALID; base 1287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2->base.mpcc_id = 0xf; base 32 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h container_of(hubp, struct dcn20_hubp, base) base 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp base; base 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.ctx base 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.ctx->logger base 363 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.funcs = &dcn20_link_enc_funcs; base 364 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.ctx = init_data->ctx; base 365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.id = init_data->encoder; base 367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.hpd_source = init_data->hpd_source; base 368 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.connector = init_data->connector; base 370 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; base 372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.features = *enc_features; base 374 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.transmitter = init_data->transmitter; base 385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.output_signals = base 411 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c switch (enc10->base.transmitter) { base 413 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGA; base 416 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGB; base 419 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGC; base 422 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGD; base 425 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGE; base 428 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGF; base 431 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_DIGG; base 435 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; base 439 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.features.flags.bits.HDMI_6GB_EN = 1; base 441 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios, base 442 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.id, &bp_cap_info); base 446 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.features.flags.bits.IS_HBR2_CAPABLE = base 448 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.features.flags.bits.IS_HBR3_CAPABLE = base 450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; base 451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.features.flags.bits.DP_IS_USB_C = base 458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c if (enc10->base.ctx->dc->debug.hdmi20_disable) { base 459 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c enc10->base.features.flags.bits.HDMI_6GB_EN = 0; base 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c mcif_wb20->base.ctx base 315 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c mcif_wb20->base.ctx = ctx; base 317 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c mcif_wb20->base.inst = inst; base 318 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c mcif_wb20->base.funcs = &dcn20_mmhubbub_funcs; base 30 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h container_of(mcif_wb_base, struct dcn20_mmhubbub, base) base 513 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h struct mcif_wb base; base 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->base.ctx base 161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->base.ctx, base 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->base.ctx, base 309 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs); base 336 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs); base 524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->base.ctx = ctx; base 526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->base.funcs = &dcn20_mpc_funcs; base 536 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc2_init_mpcc(&mpc20->base.mpcc_array[i], i); base 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h container_of(mpc_base, struct dcn20_mpc, base) base 238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h struct mpc base; base 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c oppn20->base.ctx base 346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c oppn20->base.ctx = ctx; base 347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c oppn20->base.inst = inst; base 348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c oppn20->base.funcs = &dcn20_opp_funcs; base 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h container_of(opp, struct dcn20_opp, base) base 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h struct output_pixel_processor base; base 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->base.ctx base 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->base.funcs = &dcn20_tg_funcs; base 984 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &dpp->base; base 1004 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &ipp->base; base 1021 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &opp->base; base 1038 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &aux_engine->base; base 1088 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &mpc20->base; base 1115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &hubbub->base; base 1128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c tgn10->base.inst = instance; base 1129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c tgn10->base.ctx = ctx; base 1137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &tgn10->base; base 1169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &enc20->enc10.base; base 1187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c clk_src->base.dp_clk_src = dp_clk_src; base 1188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &clk_src->base; base 1230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &enc1->base; base 1293 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &dsc->base; base 1298 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(container_of(*dsc, struct dcn20_dsc, base)); base 1308 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.stream_enc_count; i++) { base 1309 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.stream_enc[i] != NULL) { base 1310 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); base 1311 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.stream_enc[i] = NULL; base 1316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.res_cap->num_dsc; i++) { base 1317 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dscs[i] != NULL) base 1318 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn20_dsc_destroy(&pool->base.dscs[i]); base 1322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.mpc != NULL) { base 1323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(TO_DCN20_MPC(pool->base.mpc)); base 1324 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.mpc = NULL; base 1326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.hubbub != NULL) { base 1327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(pool->base.hubbub); base 1328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.hubbub = NULL; base 1330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 1331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dpps[i] != NULL) base 1332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn20_dpp_destroy(&pool->base.dpps[i]); base 1334 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.ipps[i] != NULL) base 1335 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); base 1337 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.hubps[i] != NULL) { base 1338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(TO_DCN20_HUBP(pool->base.hubps[i])); base 1339 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.hubps[i] = NULL; base 1342 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.irqs != NULL) { base 1343 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dal_irq_service_destroy(&pool->base.irqs); base 1347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 1348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.engines[i] != NULL) base 1349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dce110_engine_destroy(&pool->base.engines[i]); base 1350 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.hw_i2cs[i] != NULL) { base 1351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(pool->base.hw_i2cs[i]); base 1352 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.hw_i2cs[i] = NULL; base 1354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.sw_i2cs[i] != NULL) { base 1355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(pool->base.sw_i2cs[i]); base 1356 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.sw_i2cs[i] = NULL; base 1360 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.res_cap->num_opp; i++) { base 1361 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.opps[i] != NULL) base 1362 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); base 1365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { base 1366 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.timing_generators[i] != NULL) { base 1367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); base 1368 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.timing_generators[i] = NULL; base 1372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.res_cap->num_dwb; i++) { base 1373 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dwbc[i] != NULL) { base 1374 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); base 1375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.dwbc[i] = NULL; base 1377 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.mcif_wb[i] != NULL) { base 1378 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); base 1379 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.mcif_wb[i] = NULL; base 1383 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.audio_count; i++) { base 1384 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.audios[i]) base 1385 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dce_aud_destroy(&pool->base.audios[i]); base 1388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 1389 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.clock_sources[i] != NULL) { base 1390 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn20_clock_source_destroy(&pool->base.clock_sources[i]); base 1391 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.clock_sources[i] = NULL; base 1395 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dp_clock_source != NULL) { base 1396 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn20_clock_source_destroy(&pool->base.dp_clock_source); base 1397 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.dp_clock_source = NULL; base 1401 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.abm != NULL) base 1402 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dce_abm_destroy(&pool->base.abm); base 1404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dmcu != NULL) base 1405 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dce_dmcu_destroy(&pool->base.dmcu); base 1407 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dccg != NULL) base 1408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn_dccg_destroy(&pool->base.dccg); base 1410 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.pp_smu != NULL) base 1411 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn20_pp_smu_destroy(&pool->base.pp_smu); base 1427 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &hubp2->base; base 3037 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->dwbc[i] = &dwbc20->base; base 3064 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->mcif_wb[i] = &mcif_wb20->base; base 3393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.pp_smu) { base 3401 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { base 3402 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) base 3403 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); base 3408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { base 3409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) base 3410 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); base 3424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; base 3425 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c loaded_ip->max_num_dpp = pool->base.pipe_count; base 3447 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.funcs = &dcn20_res_pool_funcs; base 3450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.res_cap = &res_cap_nv14; base 3451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.pipe_count = 5; base 3452 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.mpcc_count = 5; base 3454 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.res_cap = &res_cap_nv10; base 3455 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.pipe_count = 6; base 3456 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.mpcc_count = 6; base 3461 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; base 3476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.pipe_count = 4; base 3477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.mpcc_count = pool->base.pipe_count; base 3493 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = base 3497 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = base 3501 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = base 3505 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = base 3509 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = base 3513 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = base 3517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; base 3519 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.dp_clock_source = base 3524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 3525 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.clock_sources[i] == NULL) { base 3532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); base 3533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dccg == NULL) { base 3539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.dmcu = dcn20_dmcu_create(ctx, base 3543 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dmcu == NULL) { base 3549 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.abm = dce_abm_create(ctx, base 3553 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.abm == NULL) { base 3559 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.pp_smu = dcn20_pp_smu_create(ctx); base 3608 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.pp_smu->nv_funcs.set_wm_ranges) base 3609 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); base 3613 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.irqs = dal_irq_service_dcn20_create(&init_data); base 3614 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!pool->base.irqs) base 3618 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 3619 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.hubps[i] = dcn20_hubp_create(ctx, i); base 3620 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.hubps[i] == NULL) { base 3627 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.ipps[i] = dcn20_ipp_create(ctx, i); base 3628 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.ipps[i] == NULL) { base 3635 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.dpps[i] = dcn20_dpp_create(ctx, i); base 3636 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dpps[i] == NULL) { base 3643 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 3644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); base 3645 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.engines[i] == NULL) { base 3651 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); base 3652 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.hw_i2cs[i] == NULL) { base 3658 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.sw_i2cs[i] = NULL; base 3661 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.res_cap->num_opp; i++) { base 3662 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.opps[i] = dcn20_opp_create(ctx, i); base 3663 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.opps[i] == NULL) { base 3671 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { base 3672 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.timing_generators[i] = dcn20_timing_generator_create( base 3674 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.timing_generators[i] == NULL) { base 3681 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.timing_generator_count = i; base 3683 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.mpc = dcn20_mpc_create(ctx); base 3684 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.mpc == NULL) { base 3690 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.hubbub = dcn20_hubbub_create(ctx); base 3691 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.hubbub == NULL) { base 3698 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0; i < pool->base.res_cap->num_dsc; i++) { base 3699 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.dscs[i] = dcn20_dsc_create(ctx, i); base 3700 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.dscs[i] == NULL) { base 3708 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!dcn20_dwbc_create(ctx, &pool->base)) { base 3713 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!dcn20_mmhubbub_create(ctx, &pool->base)) { base 3719 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!resource_construct(num_virtual_links, dc, &pool->base, base 3726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dc->caps.max_planes = pool->base.pipe_count; base 3753 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &pool->base; base 32 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h container_of(pool, struct dcn20_resource_pool, base) base 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h struct resource_pool base; base 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c enc1->base.ctx->logger base 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c enc1->base.ctx base 607 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c enc1->base.funcs = &dcn20_str_enc_funcs; base 608 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c enc1->base.ctx = ctx; base 609 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c enc1->base.id = eng_id; base 610 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c enc1->base.bp = bp; base 34 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub1->base.ctx->logger base 36 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub1->base.ctx base 46 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub1->base.ctx base 596 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub->base.ctx = ctx; base 598 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub->base.funcs = &hubbub21_funcs; base 34 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21->base.ctx base 234 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21->base.funcs = &dcn21_hubp_funcs; base 235 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21->base.ctx = ctx; base 239 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21->base.inst = inst; base 240 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21->base.opp_id = OPP_ID_INVALID; base 241 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21->base.mpcc_id = 0xf; base 33 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h container_of(hubp, struct dcn21_hubp, base) base 106 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h struct hubp base; base 653 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &ipp->base; base 668 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &dpp->base; base 689 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &aux_engine->base; base 836 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.stream_enc_count; i++) { base 837 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.stream_enc[i] != NULL) { base 838 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); base 839 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.stream_enc[i] = NULL; base 844 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.res_cap->num_dsc; i++) { base 845 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dscs[i] != NULL) base 846 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn20_dsc_destroy(&pool->base.dscs[i]); base 850 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.mpc != NULL) { base 851 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(TO_DCN20_MPC(pool->base.mpc)); base 852 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.mpc = NULL; base 854 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.hubbub != NULL) { base 855 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(pool->base.hubbub); base 856 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.hubbub = NULL; base 858 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 859 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dpps[i] != NULL) base 860 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn20_dpp_destroy(&pool->base.dpps[i]); base 862 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.ipps[i] != NULL) base 863 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); base 865 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.hubps[i] != NULL) { base 866 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(TO_DCN20_HUBP(pool->base.hubps[i])); base 867 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.hubps[i] = NULL; base 870 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.irqs != NULL) { base 871 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dal_irq_service_destroy(&pool->base.irqs); base 875 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 876 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.engines[i] != NULL) base 877 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dce110_engine_destroy(&pool->base.engines[i]); base 878 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.hw_i2cs[i] != NULL) { base 879 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(pool->base.hw_i2cs[i]); base 880 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.hw_i2cs[i] = NULL; base 882 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.sw_i2cs[i] != NULL) { base 883 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(pool->base.sw_i2cs[i]); base 884 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.sw_i2cs[i] = NULL; base 888 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.res_cap->num_opp; i++) { base 889 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.opps[i] != NULL) base 890 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); base 893 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { base 894 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.timing_generators[i] != NULL) { base 895 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); base 896 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.timing_generators[i] = NULL; base 900 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.res_cap->num_dwb; i++) { base 901 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dwbc[i] != NULL) { base 902 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); base 903 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.dwbc[i] = NULL; base 905 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.mcif_wb[i] != NULL) { base 906 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); base 907 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.mcif_wb[i] = NULL; base 911 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.audio_count; i++) { base 912 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.audios[i]) base 913 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dce_aud_destroy(&pool->base.audios[i]); base 916 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 917 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.clock_sources[i] != NULL) { base 918 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn20_clock_source_destroy(&pool->base.clock_sources[i]); base 919 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.clock_sources[i] = NULL; base 923 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dp_clock_source != NULL) { base 924 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn20_clock_source_destroy(&pool->base.dp_clock_source); base 925 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.dp_clock_source = NULL; base 929 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.abm != NULL) base 930 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dce_abm_destroy(&pool->base.abm); base 932 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dmcu != NULL) base 933 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dce_dmcu_destroy(&pool->base.dmcu); base 936 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dmcub != NULL) base 937 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn21_dmcub_destroy(&pool->base.dmcub); base 940 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dccg != NULL) base 941 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn_dccg_destroy(&pool->base.dccg); base 943 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.pp_smu != NULL) base 944 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn20_pp_smu_destroy(&pool->base.pp_smu); base 1137 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c clk_src->base.dp_clk_src = dp_clk_src; base 1138 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &clk_src->base; base 1157 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &hubp21->base; base 1189 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &hubbub->base; base 1205 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &opp->base; base 1218 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c tgn10->base.inst = instance; base 1219 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c tgn10->base.ctx = ctx; base 1227 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &tgn10->base; base 1244 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &mpc20->base; base 1270 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &dsc->base; base 1280 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; base 1281 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn2_1_ip.max_num_dpp = pool->base.pipe_count; base 1380 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &enc1->base; base 1448 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.res_cap = &res_cap_rn; base 1452 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.res_cap = &res_cap_rn_FPGA_4pipe; base 1455 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.funcs = &dcn21_res_pool_funcs; base 1460 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; base 1462 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.pipe_count = 4; base 1476 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.pipe_count = 4; base 1489 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = base 1493 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = base 1497 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = base 1502 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; base 1505 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.dp_clock_source = base 1510 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.clk_src_count; i++) { base 1511 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.clock_sources[i] == NULL) { base 1518 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); base 1519 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dccg == NULL) { base 1526 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.dmcub = dcn21_dmcub_create(ctx, base 1530 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dmcub == NULL) { base 1537 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.pp_smu = dcn21_pp_smu_create(ctx); base 1542 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.irqs = dal_irq_service_dcn21_create(&init_data); base 1543 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (!pool->base.irqs) base 1547 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.pipe_count; i++) { base 1548 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.hubps[i] = dcn21_hubp_create(ctx, i); base 1549 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.hubps[i] == NULL) { base 1556 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.ipps[i] = dcn21_ipp_create(ctx, i); base 1557 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.ipps[i] == NULL) { base 1564 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.dpps[i] = dcn21_dpp_create(ctx, i); base 1565 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dpps[i] == NULL) { base 1573 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.res_cap->num_ddc; i++) { base 1574 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); base 1575 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.engines[i] == NULL) { base 1581 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i); base 1582 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.hw_i2cs[i] == NULL) { base 1588 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.sw_i2cs[i] = NULL; base 1591 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.res_cap->num_opp; i++) { base 1592 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.opps[i] = dcn21_opp_create(ctx, i); base 1593 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.opps[i] == NULL) { base 1601 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { base 1602 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.timing_generators[i] = dcn21_timing_generator_create( base 1604 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.timing_generators[i] == NULL) { base 1611 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.timing_generator_count = i; base 1613 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.mpc = dcn21_mpc_create(ctx); base 1614 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.mpc == NULL) { base 1620 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.hubbub = dcn21_hubbub_create(ctx); base 1621 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.hubbub == NULL) { base 1628 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0; i < pool->base.res_cap->num_dsc; i++) { base 1629 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.dscs[i] = dcn21_dsc_create(ctx, i); base 1630 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.dscs[i] == NULL) { base 1638 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (!dcn20_dwbc_create(ctx, &pool->base)) { base 1643 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (!dcn20_mmhubbub_create(ctx, &pool->base)) { base 1649 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (!resource_construct(num_virtual_links, dc, &pool->base, base 1656 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dc->caps.max_planes = pool->base.pipe_count; base 1683 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &pool->base; base 32 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h container_of(pool, struct dcn21_resource_pool, base) base 39 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h struct resource_pool base; base 108 drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h static inline double dml_log(double x, double base) base 110 drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h return (double) dcn_bw_log(x, base); base 125 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c ddc->base.regs = &ddc_data_regs[en].gpio; base 129 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c ddc->base.regs = &ddc_clk_regs[en].gpio; base 148 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c hpd->base.regs = &hpd_regs[en].gpio; base 138 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c ddc->base.regs = &ddc_data_regs[en].gpio; base 142 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c ddc->base.regs = &ddc_clk_regs[en].gpio; base 161 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c hpd->base.regs = &hpd_regs[en].gpio; base 125 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c ddc->base.regs = &ddc_data_regs[en].gpio; base 129 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c ddc->base.regs = &ddc_clk_regs[en].gpio; base 148 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c hpd->base.regs = &hpd_regs[en].gpio; base 158 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c generic->base.regs = &generic_regs[en].gpio; base 170 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c ddc->base.regs = &ddc_data_regs[en].gpio; base 174 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c ddc->base.regs = &ddc_clk_regs[en].gpio; base 193 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c hpd->base.regs = &hpd_regs[en].gpio; base 177 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c ddc->base.regs = &ddc_data_regs_dcn[en].gpio; base 181 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; base 200 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c hpd->base.regs = &hpd_regs[en].gpio; base 210 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c generic->base.regs = &generic_regs[en].gpio; base 167 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c generic->base.regs = &generic_regs[en].gpio; base 179 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c ddc->base.regs = &ddc_data_regs_dcn[en].gpio; base 183 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; base 202 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c hpd->base.regs = &hpd_regs[en].gpio; base 45 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c ddc->base.base.ctx base 54 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c dal_hw_gpio_destruct(&pin->base); base 80 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c hw_gpio = &ddc->base; base 98 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) { base 178 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && base 179 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { base 188 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && base 189 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { base 198 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && base 199 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { base 229 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c dal_hw_gpio_construct(&ddc->base, id, en, ctx); base 230 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c ddc->base.base.funcs = &funcs; base 257 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c return &hw_ddc->base.base; base 32 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h struct hw_gpio base; base 39 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_ddc, base) base 43 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c generic->base.base.ctx base 55 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c dal_hw_gpio_construct(&pin->base, id, en, ctx); base 61 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c dal_hw_gpio_destruct(&pin->base); base 109 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c generic->base.base.funcs = &funcs; base 137 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c return &hw_generic->base.base; base 33 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h struct hw_gpio base; base 40 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_generic, base) base 38 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c gpio->base.ctx base 145 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c gpio->base.mode = mode; base 185 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c pin->base.ctx = ctx; base 186 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c pin->base.id = id; base 187 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c pin->base.en = en; base 188 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c pin->base.mode = GPIO_MODE_UNKNOWN; base 189 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c pin->base.opened = false; base 202 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c ASSERT(!pin->base.opened); base 32 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h container_of((ptr), struct hw_gpio, base) base 94 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h struct hw_gpio_pin base; base 110 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h container_of((hw_gpio_pin), struct hw_gpio, base) base 43 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c hpd->base.base.ctx base 55 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c dal_hw_gpio_construct(&pin->base, id, en, ctx); base 61 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c dal_hw_gpio_destruct(&pin->base); base 139 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c hpd->base.base.funcs = &funcs; base 166 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c return &hw_hpd->base.base; base 32 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h struct hw_gpio base; base 39 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_hpd, base) base 70 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h container_of(clk_mgr, struct clk_mgr_internal, base) base 73 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h clk_mgr->base.ctx base 193 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h struct clk_mgr base; base 127 drivers/gpu/drm/amd/display/modules/color/color_gamma.c struct fixed31_32 base; base 133 drivers/gpu/drm/amd/display/modules/color/color_gamma.c base = dc_fixpt_div( base 138 drivers/gpu/drm/amd/display/modules/color/color_gamma.c *out_y = dc_fixpt_pow(base, m2); base 156 drivers/gpu/drm/amd/display/modules/color/color_gamma.c struct fixed31_32 base, div; base 164 drivers/gpu/drm/amd/display/modules/color/color_gamma.c base = dc_fixpt_sub(l_pow_m1, c1); base 166 drivers/gpu/drm/amd/display/modules/color/color_gamma.c if (dc_fixpt_lt(base, dc_fixpt_zero)) base 167 drivers/gpu/drm/amd/display/modules/color/color_gamma.c base = dc_fixpt_zero; base 171 drivers/gpu/drm/amd/display/modules/color/color_gamma.c *out_y = dc_fixpt_pow(dc_fixpt_div(base, div), base 67 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static int uPow(int base, int exponent); /* Returns base^exponent an INT */ base 524 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static int uPow(int base, int power) base 529 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h return (base)*uPow(base, power - 1); base 13 drivers/gpu/drm/arm/display/include/malidp_io.h malidp_read32(u32 __iomem *base, u32 offset) base 15 drivers/gpu/drm/arm/display/include/malidp_io.h return readl((base + (offset >> 2))); base 19 drivers/gpu/drm/arm/display/include/malidp_io.h malidp_write32(u32 __iomem *base, u32 offset, u32 v) base 21 drivers/gpu/drm/arm/display/include/malidp_io.h writel(v, (base + (offset >> 2))); base 25 drivers/gpu/drm/arm/display/include/malidp_io.h malidp_write64(u32 __iomem *base, u32 offset, u64 v) base 27 drivers/gpu/drm/arm/display/include/malidp_io.h writel(lower_32_bits(v), (base + (offset >> 2))); base 28 drivers/gpu/drm/arm/display/include/malidp_io.h writel(upper_32_bits(v), (base + (offset >> 2) + 1)); base 32 drivers/gpu/drm/arm/display/include/malidp_io.h malidp_write32_mask(u32 __iomem *base, u32 offset, u32 m, u32 v) base 34 drivers/gpu/drm/arm/display/include/malidp_io.h u32 tmp = malidp_read32(base, offset); base 37 drivers/gpu/drm/arm/display/include/malidp_io.h malidp_write32(base, offset, v | tmp); base 41 drivers/gpu/drm/arm/display/include/malidp_io.h malidp_write_group(u32 __iomem *base, u32 offset, int num, const u32 *values) base 46 drivers/gpu/drm/arm/display/include/malidp_io.h malidp_write32(base, offset + i * 4, values[i]); base 172 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct drm_framebuffer *fb = &kfb->base; base 349 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*layer), base 447 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*wb_layer), base 586 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*compiz), base 743 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*scaler), base 851 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*splitter), base 921 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*merger), base 998 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*improc), base 1125 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*ctrlr), base 15 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.h struct komeda_pipeline base; base 44 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.h #define to_d71_pipeline(x) container_of(x, struct d71_pipeline, base) base 25 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c if (!kcrtc_st->base.active) { base 30 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL; base 84 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c struct komeda_dev *mdev = kcrtc->base.dev->dev_private; base 86 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(kcrtc->base.state); base 87 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c struct drm_display_mode *mode = &kcrtc_st->base.adjusted_mode; base 137 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c struct komeda_dev *mdev = kcrtc->base.dev->dev_private; base 173 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c struct drm_crtc *crtc = &kcrtc->base; base 183 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c drm_writeback_signal_completion(&wb_conn->base, 0); base 186 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c drm_crtc_index(&kcrtc->base)); base 210 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c drm_crtc_index(&kcrtc->base)); base 222 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c struct komeda_dev *mdev = kcrtc->base.dev->dev_private; base 239 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c conn_st = wb_conn ? wb_conn->base.base.state : NULL; base 241 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c drm_writeback_queue_job(&wb_conn->base, conn_st); base 356 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c struct drm_crtc *crtc = kcrtc_st->base.crtc; base 358 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c unsigned long pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000; base 444 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c crtc->state = &state->base; base 459 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c __drm_atomic_helper_crtc_duplicate_state(crtc, &new->base); base 465 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c return &new->base; base 541 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c drm_for_each_plane(plane, &kms->base) { base 547 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c if (kplane->layer->base.pipeline == crtc->master) base 557 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c struct drm_crtc *crtc = &kcrtc->base; base 560 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c err = drm_crtc_init_with_planes(&kms->base, crtc, base 43 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c struct drm_framebuffer *fb = &kfb->base; base 115 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c struct drm_framebuffer *fb = &kfb->base; base 180 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c drm_helper_mode_fill_fb_struct(dev, &kfb->base, mode_cmd); base 182 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c if (kfb->base.modifier) base 189 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c ret = drm_framebuffer_init(dev, &kfb->base, &komeda_fb_funcs); base 198 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c return &kfb->base; base 201 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c for (i = 0; i < kfb->base.format->num_planes; i++) base 202 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c drm_gem_object_put_unlocked(kfb->base.obj[i]); base 211 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c const struct drm_framebuffer *fb = &kfb->base; base 241 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c struct drm_framebuffer *fb = &kfb->base; base 270 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c struct drm_framebuffer *fb = &kfb->base; base 18 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h struct drm_framebuffer base; base 36 drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h #define to_kfb(dfb) container_of(dfb, struct komeda_fb, base) base 114 drivers/gpu/drm/arm/display/komeda/komeda_kms.c if (!last || (new->base.zpos > last->base.zpos)) { base 121 drivers/gpu/drm/arm/display/komeda/komeda_kms.c if (new->base.zpos < node->base.zpos) { base 124 drivers/gpu/drm/arm/display/komeda/komeda_kms.c } else if (node->base.zpos == new->base.zpos) { base 125 drivers/gpu/drm/arm/display/komeda/komeda_kms.c struct drm_plane *a = node->base.plane; base 126 drivers/gpu/drm/arm/display/komeda/komeda_kms.c struct drm_plane *b = new->base.plane; base 132 drivers/gpu/drm/arm/display/komeda/komeda_kms.c a->name, b->name, node->base.zpos); base 153 drivers/gpu/drm/arm/display/komeda/komeda_kms.c crtc->base.id, crtc->name); base 172 drivers/gpu/drm/arm/display/komeda/komeda_kms.c plane_st = &kplane_st->base; base 186 drivers/gpu/drm/arm/display/komeda/komeda_kms.c plane->base.id, plane->name, base 242 drivers/gpu/drm/arm/display/komeda/komeda_kms.c struct drm_mode_config *config = &kms->base.mode_config; base 244 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm_mode_config_init(&kms->base); base 268 drivers/gpu/drm/arm/display/komeda/komeda_kms.c drm = &kms->base; base 341 drivers/gpu/drm/arm/display/komeda/komeda_kms.c struct drm_device *drm = &kms->base; base 23 drivers/gpu/drm/arm/display/komeda/komeda_kms.h struct drm_plane base; base 44 drivers/gpu/drm/arm/display/komeda/komeda_kms.h struct drm_plane_state base; base 57 drivers/gpu/drm/arm/display/komeda/komeda_kms.h struct drm_writeback_connector base; base 68 drivers/gpu/drm/arm/display/komeda/komeda_kms.h struct drm_crtc base; base 94 drivers/gpu/drm/arm/display/komeda/komeda_kms.h struct drm_crtc_state base; base 120 drivers/gpu/drm/arm/display/komeda/komeda_kms.h struct drm_device base; base 128 drivers/gpu/drm/arm/display/komeda/komeda_kms.h #define to_kplane(p) container_of(p, struct komeda_plane, base) base 129 drivers/gpu/drm/arm/display/komeda/komeda_kms.h #define to_kplane_st(p) container_of(p, struct komeda_plane_state, base) base 130 drivers/gpu/drm/arm/display/komeda/komeda_kms.h #define to_kconn(p) container_of(p, struct komeda_wb_connector, base) base 131 drivers/gpu/drm/arm/display/komeda/komeda_kms.h #define to_kcrtc(p) container_of(p, struct komeda_crtc, base) base 132 drivers/gpu/drm/arm/display/komeda/komeda_kms.h #define to_kcrtc_st(p) container_of(p, struct komeda_crtc_state, base) base 133 drivers/gpu/drm/arm/display/komeda/komeda_kms.h #define to_kdev(p) container_of(p, struct komeda_kms_dev, base) base 134 drivers/gpu/drm/arm/display/komeda/komeda_kms.h #define to_wb_conn(x) container_of(x, struct drm_writeback_connector, base) base 139 drivers/gpu/drm/arm/display/komeda/komeda_kms.h struct drm_connector *conn = wb_conn ? &wb_conn->base.base : NULL; base 290 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c int index = left->base.id - KOMEDA_COMPONENT_LAYER0; base 331 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c slave = komeda_component_pickup_input(&master->compiz->base, base 222 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_comp(__c) (((__c) == NULL) ? NULL : &((__c)->base)) base 226 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component base; base 240 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component_state base; base 252 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component base; base 261 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component_state base; base 275 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component base; base 286 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component_state base; base 293 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component base; base 299 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component_state base; base 305 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component base; base 310 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component_state base; base 316 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component base; base 325 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component_state base; base 331 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component base; base 336 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_component_state base; base 447 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_layer(c) container_of(c, struct komeda_layer, base) base 448 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_compiz(c) container_of(c, struct komeda_compiz, base) base 449 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_scaler(c) container_of(c, struct komeda_scaler, base) base 450 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_splitter(c) container_of(c, struct komeda_splitter, base) base 451 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_merger(c) container_of(c, struct komeda_merger, base) base 452 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_improc(c) container_of(c, struct komeda_improc, base) base 453 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_ctrlr(c) container_of(c, struct komeda_timing_ctrlr, base) base 455 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_layer_st(c) container_of(c, struct komeda_layer_state, base) base 456 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_compiz_st(c) container_of(c, struct komeda_compiz_state, base) base 457 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_scaler_st(c) container_of(c, struct komeda_scaler_state, base) base 458 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_splitter_st(c) container_of(c, struct komeda_splitter_state, base) base 459 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_merger_st(c) container_of(c, struct komeda_merger_state, base) base 460 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_improc_st(c) container_of(c, struct komeda_improc_state, base) base 461 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h #define to_ctrlr_st(c) container_of(c, struct komeda_timing_ctrlr_state, base) base 292 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c if (layer->base.id == KOMEDA_COMPONENT_WB_LAYER) { base 325 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct drm_plane_state *plane_st = &kplane_st->base; base 336 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st = komeda_component_get_state_and_set_user(&layer->base, base 365 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c err = komeda_component_validate_private(&layer->base, c_st); base 370 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&dflow->input, &layer->base, 0); base 395 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st = komeda_component_get_state_and_set_user(&wb_layer->base, base 405 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c for (i = 0; i < kfb->base.format->num_planes; i++) base 409 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_add_input(&st->base, &dflow->input, 0); base 410 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&dflow->input, &wb_layer->base, 0); base 471 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_pipeline *pipe = scaler->base.pipeline; base 475 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c &kcrtc_st->base.adjusted_mode, base 491 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct drm_atomic_state *drm_st = kcrtc_st->base.state; base 511 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st = komeda_component_get_state_and_set_user(&scaler->base, base 512 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c drm_st, user, kcrtc_st->base.crtc); base 535 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_add_input(&st->base, &dflow->input, 0); base 536 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&dflow->input, &scaler->base, 0); base 572 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st = komeda_component_get_state_and_set_user(&splitter->base, base 578 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_split_data_flow(splitter->base.pipeline->scalers[0], base 586 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_add_input(&st->base, &dflow->input, 0); base 587 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&l_output->input, &splitter->base, 0); base 588 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&r_output->input, &splitter->base, 1); base 622 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st = komeda_component_get_state_and_set_user(&merger->base, base 623 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c kcrtc_st->base.state, kcrtc_st->base.crtc, kcrtc_st->base.crtc); base 634 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&output->input, &merger->base, 0); base 642 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct drm_display_mode *m = &kcrtc_st->base.adjusted_mode; base 655 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct drm_atomic_state *drm_st = kcrtc_st->base.state; base 672 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st = komeda_component_get_state_and_set_user(&compiz->base, drm_st, base 673 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c kcrtc_st->base.crtc, kcrtc_st->base.crtc); base 689 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c old_st = komeda_component_get_old_state(&compiz->base, drm_st); base 697 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&dflow->input, &compiz->base, 0); base 710 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st = komeda_component_get_state_and_set_user(&compiz->base, base 711 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c state->base.state, state->base.crtc, state->base.crtc); base 719 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&dflow->input, &compiz->base, 0); base 745 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct drm_crtc *crtc = kcrtc_st->base.crtc; base 749 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st = komeda_component_get_state_and_set_user(&improc->base, base 750 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c kcrtc_st->base.state, crtc, crtc); base 759 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_add_input(&st->base, &dflow->input, 0); base 760 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&dflow->input, &improc->base, 0); base 770 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct drm_crtc *crtc = kcrtc_st->base.crtc; base 774 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st = komeda_component_get_state_and_set_user(&ctrlr->base, base 775 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c kcrtc_st->base.state, crtc, crtc); base 781 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_add_input(&st->base, &dflow->input, 0); base 782 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&dflow->input, &ctrlr->base, 0); base 791 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_scaler *scaler = layer->base.pipeline->scalers[0]; base 825 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c pipe->merger->base.supported_inputs : 0; base 835 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct drm_plane *plane = kplane_st->base.plane; base 836 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_pipeline *pipe = layer->base.pipeline; base 840 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c layer->base.name, plane->base.id, plane->name, base 1038 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct drm_plane *plane = kplane_st->base.plane; base 1039 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_pipeline *pipe = left->base.pipeline; base 1048 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c left->base.name, right->base.name, base 1049 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c plane->base.id, plane->name, base 1107 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_pipeline *pipe = wb_layer->base.pipeline; base 1201 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct drm_atomic_state *drm_st = kcrtc_st->base.state; base 23 drivers/gpu/drm/arm/display/komeda/komeda_plane.c struct komeda_pipeline *pipe = kplane->layer->base.pipeline; base 147 drivers/gpu/drm/arm/display/komeda/komeda_plane.c state->base.rotation = DRM_MODE_ROTATE_0; base 148 drivers/gpu/drm/arm/display/komeda/komeda_plane.c state->base.pixel_blend_mode = DRM_MODE_BLEND_PREMULTI; base 149 drivers/gpu/drm/arm/display/komeda/komeda_plane.c state->base.alpha = DRM_BLEND_ALPHA_OPAQUE; base 150 drivers/gpu/drm/arm/display/komeda/komeda_plane.c state->base.zpos = kplane->layer->base.id; base 151 drivers/gpu/drm/arm/display/komeda/komeda_plane.c state->base.color_encoding = DRM_COLOR_YCBCR_BT601; base 152 drivers/gpu/drm/arm/display/komeda/komeda_plane.c state->base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; base 153 drivers/gpu/drm/arm/display/komeda/komeda_plane.c plane->state = &state->base; base 170 drivers/gpu/drm/arm/display/komeda/komeda_plane.c __drm_atomic_helper_plane_duplicate_state(plane, &new->base); base 172 drivers/gpu/drm/arm/display/komeda/komeda_plane.c return &new->base; base 251 drivers/gpu/drm/arm/display/komeda/komeda_plane.c struct komeda_dev *mdev = kms->base.dev_private; base 252 drivers/gpu/drm/arm/display/komeda/komeda_plane.c struct komeda_component *c = &layer->base; base 262 drivers/gpu/drm/arm/display/komeda/komeda_plane.c plane = &kplane->base; base 268 drivers/gpu/drm/arm/display/komeda/komeda_plane.c err = drm_universal_plane_init(&kms->base, plane, base 309 drivers/gpu/drm/arm/display/komeda/komeda_plane.c err = drm_plane_create_zpos_property(plane, layer->base.id, 0, 8); base 28 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c komeda_component_state_reset(&st->base); base 29 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c __drm_atomic_helper_private_obj_duplicate_state(obj, &st->base.obj); base 31 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c return &st->base.obj; base 57 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c st->base.component = &layer->base; base 58 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c drm_atomic_private_obj_init(&kms->base, &layer->base.obj, &st->base.obj, base 72 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c komeda_component_state_reset(&st->base); base 73 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c __drm_atomic_helper_private_obj_duplicate_state(obj, &st->base.obj); base 75 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c return &st->base.obj; base 99 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c st->base.component = &scaler->base; base 100 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c drm_atomic_private_obj_init(&kms->base, base 101 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c &scaler->base.obj, &st->base.obj, base 115 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c komeda_component_state_reset(&st->base); base 116 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c __drm_atomic_helper_private_obj_duplicate_state(obj, &st->base.obj); base 118 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c return &st->base.obj; base 142 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c st->base.component = &compiz->base; base 143 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c drm_atomic_private_obj_init(&kms->base, &compiz->base.obj, &st->base.obj, base 158 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c komeda_component_state_reset(&st->base); base 159 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c __drm_atomic_helper_private_obj_duplicate_state(obj, &st->base.obj); base 161 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c return &st->base.obj; base 185 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c st->base.component = &splitter->base; base 186 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c drm_atomic_private_obj_init(&kms->base, base 187 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c &splitter->base.obj, &st->base.obj, base 202 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c komeda_component_state_reset(&st->base); base 203 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c __drm_atomic_helper_private_obj_duplicate_state(obj, &st->base.obj); base 205 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c return &st->base.obj; base 228 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c st->base.component = &merger->base; base 229 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c drm_atomic_private_obj_init(&kms->base, base 230 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c &merger->base.obj, &st->base.obj, base 245 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c komeda_component_state_reset(&st->base); base 246 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c __drm_atomic_helper_private_obj_duplicate_state(obj, &st->base.obj); base 248 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c return &st->base.obj; base 272 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c st->base.component = &improc->base; base 273 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c drm_atomic_private_obj_init(&kms->base, &improc->base.obj, &st->base.obj, base 288 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c komeda_component_state_reset(&st->base); base 289 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c __drm_atomic_helper_private_obj_duplicate_state(obj, &st->base.obj); base 291 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c return &st->base.obj; base 315 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c st->base.component = &ctrlr->base; base 316 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c drm_atomic_private_obj_init(&kms->base, &ctrlr->base.obj, &st->base.obj, base 360 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c drm_atomic_private_obj_init(&kms->base, &pipe->obj, &st->obj, base 427 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c struct drm_mode_config *config = &kms->base.mode_config; base 25 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c dflow->input.component = &wb_layer->base.pipeline->compiz->base; base 141 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c struct komeda_dev *mdev = kms->base.dev_private; base 156 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c wb_conn = &kwb_conn->base; base 157 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c wb_conn->encoder.possible_crtcs = BIT(drm_crtc_index(&kcrtc->base)); base 163 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c err = drm_writeback_connector_init(&kms->base, wb_conn, base 173 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c drm_connector_helper_add(&wb_conn->base, &komeda_wb_conn_helper_funcs); base 160 drivers/gpu/drm/arm/malidp_crtc.c (crtc->state->gamma_lut->base.id == state->gamma_lut->base.id)) base 215 drivers/gpu/drm/arm/malidp_crtc.c if (crtc->state->ctm && (crtc->state->ctm->base.id == base 216 drivers/gpu/drm/arm/malidp_crtc.c state->ctm->base.id)) base 423 drivers/gpu/drm/arm/malidp_crtc.c (1 << drm_connector_index(&malidp->mw_connector.base))) base 453 drivers/gpu/drm/arm/malidp_crtc.c __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); base 462 drivers/gpu/drm/arm/malidp_crtc.c return &state->base; base 486 drivers/gpu/drm/arm/malidp_crtc.c __drm_atomic_helper_crtc_reset(crtc, &state->base); base 77 drivers/gpu/drm/arm/malidp_drv.c if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id != base 78 drivers/gpu/drm/arm/malidp_drv.c old_state->gamma_lut->base.id)) base 104 drivers/gpu/drm/arm/malidp_drv.c if (!old_state->ctm || (crtc->state->ctm->base.id != base 105 drivers/gpu/drm/arm/malidp_drv.c old_state->ctm->base.id)) base 50 drivers/gpu/drm/arm/malidp_drv.h struct drm_plane base; base 62 drivers/gpu/drm/arm/malidp_drv.h struct drm_plane_state base; base 73 drivers/gpu/drm/arm/malidp_drv.h #define to_malidp_plane(x) container_of(x, struct malidp_plane, base) base 74 drivers/gpu/drm/arm/malidp_drv.h #define to_malidp_plane_state(x) container_of(x, struct malidp_plane_state, base) base 77 drivers/gpu/drm/arm/malidp_drv.h struct drm_crtc_state base; base 85 drivers/gpu/drm/arm/malidp_drv.h #define to_malidp_crtc_state(x) container_of(x, struct malidp_crtc_state, base) base 508 drivers/gpu/drm/arm/malidp_hw.c u32 base = MALIDP500_SE_MEMWRITE_BASE; base 520 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT); base 523 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW); base 524 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH); base 525 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE); base 528 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW); base 529 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH); base 530 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, pitches[0], base + MALIDP_MW_P1_STRIDE); base 555 drivers/gpu/drm/arm/malidp_hw.c u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); base 560 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC); base 849 drivers/gpu/drm/arm/malidp_hw.c u32 base = MALIDP550_SE_MEMWRITE_BASE; base 857 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT); base 860 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW); base 861 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH); base 862 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE); base 865 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW); base 866 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH); base 867 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, pitches[0], base + MALIDP_MW_P1_STRIDE); base 892 drivers/gpu/drm/arm/malidp_hw.c u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); base 896 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC); base 1151 drivers/gpu/drm/arm/malidp_hw.c u32 base = malidp_get_block_base(hwdev, block); base 1154 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ); base 1156 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS); base 63 drivers/gpu/drm/arm/malidp_hw.h u16 base; /* address offset for the register bank */ base 303 drivers/gpu/drm/arm/malidp_hw.h u32 base = malidp_get_block_base(hwdev, block); base 305 drivers/gpu/drm/arm/malidp_hw.h malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); base 311 drivers/gpu/drm/arm/malidp_hw.h u32 base = malidp_get_block_base(hwdev, block); base 313 drivers/gpu/drm/arm/malidp_hw.h malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); base 25 drivers/gpu/drm/arm/malidp_mw.c struct drm_connector_state base; base 73 drivers/gpu/drm/arm/malidp_mw.c __drm_atomic_helper_connector_reset(connector, &mw_state->base); base 103 drivers/gpu/drm/arm/malidp_mw.c __drm_atomic_helper_connector_duplicate_state(connector, &mw_state->base); base 105 drivers/gpu/drm/arm/malidp_mw.c return &mw_state->base; base 219 drivers/gpu/drm/arm/malidp_mw.c drm_connector_helper_add(&malidp->mw_connector.base, base 242 drivers/gpu/drm/arm/malidp_mw.c struct drm_connector_state *conn_state = mw_conn->base.state; base 88 drivers/gpu/drm/arm/malidp_planes.c __drm_atomic_helper_plane_destroy_state(&state->base); base 93 drivers/gpu/drm/arm/malidp_planes.c __drm_atomic_helper_plane_reset(plane, &state->base); base 109 drivers/gpu/drm/arm/malidp_planes.c __drm_atomic_helper_plane_duplicate_state(plane, &state->base); base 117 drivers/gpu/drm/arm/malidp_planes.c return &state->base; base 317 drivers/gpu/drm/arm/malidp_planes.c iommu_get_domain_for_dev(mp->base.dev->dev); base 343 drivers/gpu/drm/arm/malidp_planes.c obj = drm_gem_fb_get_obj(ms->base.fb, i); base 457 drivers/gpu/drm/arm/malidp_planes.c if (malidp_partial_prefetch_supported(ms->base.fb->format->format, base 458 drivers/gpu/drm/arm/malidp_planes.c ms->base.fb->modifier, base 459 drivers/gpu/drm/arm/malidp_planes.c ms->base.rotation)) { base 634 drivers/gpu/drm/arm/malidp_planes.c unsigned int block_h = drm_format_info_block_height(mp->base.state->fb->format, i); base 637 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + base 691 drivers/gpu/drm/arm/malidp_planes.c plane->layer->base + plane->layer->yuv2rgb_offset + base 711 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + mp->layer->mmu_ctrl_offset); base 720 drivers/gpu/drm/arm/malidp_planes.c struct drm_plane *plane = &mp->base; base 821 drivers/gpu/drm/arm/malidp_planes.c val = malidp_hw_read(mp->hwdev, mp->layer->base); base 823 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, mp->layer->base); base 839 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP_LAYER_SIZE); base 842 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP_LAYER_COMP_SIZE); base 846 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP_LAYER_OFFSET); base 854 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP550_LS_ENABLE); base 857 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP550_LS_R1_IN_SIZE); base 863 drivers/gpu/drm/arm/malidp_planes.c val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); base 906 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP_LAYER_CONTROL); base 916 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP_LAYER_CONTROL); base 986 drivers/gpu/drm/arm/malidp_planes.c ret = drm_universal_plane_init(drm, &plane->base, crtcs, base 994 drivers/gpu/drm/arm/malidp_planes.c drm_plane_helper_add(&plane->base, base 999 drivers/gpu/drm/arm/malidp_planes.c drm_plane_create_alpha_property(&plane->base); base 1000 drivers/gpu/drm/arm/malidp_planes.c drm_plane_create_blend_mode_property(&plane->base, blend_caps); base 1007 drivers/gpu/drm/arm/malidp_planes.c drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags); base 1009 drivers/gpu/drm/arm/malidp_planes.c plane->layer->base + MALIDP_LAYER_COMPOSE); base 1017 drivers/gpu/drm/arm/malidp_planes.c ret = drm_plane_create_color_properties(&plane->base, base 69 drivers/gpu/drm/armada/armada_510.c dcrtc->base + LCD_CFG_RDREG4F); base 73 drivers/gpu/drm/armada/armada_510.c dcrtc->base + LCD_SPU_ADV_REG); base 85 drivers/gpu/drm/armada/armada_crtc.c void __iomem *reg = dcrtc->base + regs->offset; base 118 drivers/gpu/drm/armada/armada_crtc.c dcrtc->base + LCD_SPU_DUMB_CTRL); base 137 drivers/gpu/drm/armada/armada_crtc.c void __iomem *base = drm_to_armada_crtc(crtc)->base; base 144 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_SRAM_PARA1); base 148 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_SRAM_WRDAT); base 150 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_SRAM_CTRL); base 151 drivers/gpu/drm/armada/armada_crtc.c readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); base 153 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_SRAM_WRDAT); base 155 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_SRAM_CTRL); base 156 drivers/gpu/drm/armada/armada_crtc.c readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); base 158 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_SRAM_WRDAT); base 160 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_SRAM_CTRL); base 161 drivers/gpu/drm/armada/armada_crtc.c readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); base 164 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_DMA_CTRL0); base 166 drivers/gpu/drm/armada/armada_crtc.c armada_updatel(0, CFG_GAMMA_ENA, base + LCD_SPU_DMA_CTRL0); base 168 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_SRAM_PARA1); base 232 drivers/gpu/drm/armada/armada_crtc.c writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); base 240 drivers/gpu/drm/armada/armada_crtc.c writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); base 241 drivers/gpu/drm/armada/armada_crtc.c if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) base 242 drivers/gpu/drm/armada/armada_crtc.c writel(0, dcrtc->base + LCD_SPU_IRQ_ISR); base 249 drivers/gpu/drm/armada/armada_crtc.c void __iomem *base = dcrtc->base; base 264 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); base 266 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPUT_V_H_TOTAL); base 268 drivers/gpu/drm/armada/armada_crtc.c val = readl_relaxed(base + LCD_SPU_ADV_REG); base 271 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(val, base + LCD_SPU_ADV_REG); base 281 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_HWC_OVSA_HPXL_VLN); base 283 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_HWC_HPXL_VLN); base 287 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_DMA_CTRL0); base 308 drivers/gpu/drm/armada/armada_crtc.c u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); base 315 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); base 347 drivers/gpu/drm/armada/armada_crtc.c crtc->base.id, crtc->name, DRM_MODE_ARG(adj)); base 418 drivers/gpu/drm/armada/armada_crtc.c DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); base 434 drivers/gpu/drm/armada/armada_crtc.c DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); base 448 drivers/gpu/drm/armada/armada_crtc.c DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); base 475 drivers/gpu/drm/armada/armada_crtc.c DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); base 510 drivers/gpu/drm/armada/armada_crtc.c DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); base 541 drivers/gpu/drm/armada/armada_crtc.c static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix, base 567 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_SRAM_WRDAT); base 569 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_SRAM_CTRL); base 570 drivers/gpu/drm/armada/armada_crtc.c readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); base 580 drivers/gpu/drm/armada/armada_crtc.c static void armada_drm_crtc_cursor_tran(void __iomem *base) base 586 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT); base 588 drivers/gpu/drm/armada/armada_crtc.c base + LCD_SPU_SRAM_CTRL); base 639 drivers/gpu/drm/armada/armada_crtc.c armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); base 645 drivers/gpu/drm/armada/armada_crtc.c para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); base 647 drivers/gpu/drm/armada/armada_crtc.c dcrtc->base + LCD_SPU_SRAM_PARA1); base 655 drivers/gpu/drm/armada/armada_crtc.c armada_drm_crtc_cursor_tran(dcrtc->base); base 662 drivers/gpu/drm/armada/armada_crtc.c armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); base 672 drivers/gpu/drm/armada/armada_crtc.c armada_load_cursor_argb(dcrtc->base, pix, s, w, h); base 771 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA); base 839 drivers/gpu/drm/armada/armada_crtc.c dcrtc->crtc.base.id, dcrtc->crtc.name, desired_hz); base 870 drivers/gpu/drm/armada/armada_crtc.c dcrtc->crtc.base.id, dcrtc->crtc.name, base 890 drivers/gpu/drm/armada/armada_crtc.c dcrtc->crtc.base.id, dcrtc->crtc.name, base 907 drivers/gpu/drm/armada/armada_crtc.c void __iomem *base; base 910 drivers/gpu/drm/armada/armada_crtc.c base = devm_ioremap_resource(dev, res); base 911 drivers/gpu/drm/armada/armada_crtc.c if (IS_ERR(base)) base 912 drivers/gpu/drm/armada/armada_crtc.c return PTR_ERR(base); base 924 drivers/gpu/drm/armada/armada_crtc.c dcrtc->base = base; base 932 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); base 933 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR); base 935 drivers/gpu/drm/armada/armada_crtc.c dcrtc->base + LCD_SPU_IOPAD_CONTROL); base 936 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0); base 939 drivers/gpu/drm/armada/armada_crtc.c CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); base 940 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); base 941 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); base 942 drivers/gpu/drm/armada/armada_crtc.c readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); base 943 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); base 957 drivers/gpu/drm/armada/armada_crtc.c armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0); base 41 drivers/gpu/drm/armada/armada_crtc.h void __iomem *base; base 38 drivers/gpu/drm/armada/armada_debugfs.c u32 v = readl_relaxed(dcrtc->base + i); base 77 drivers/gpu/drm/armada/armada_debugfs.c v = readl(dcrtc->base + reg); base 80 drivers/gpu/drm/armada/armada_debugfs.c writel(v, dcrtc->base + reg); base 29 drivers/gpu/drm/armada/armada_overlay.c struct armada_plane_state base; base 40 drivers/gpu/drm/armada/armada_overlay.c container_of(s, struct armada_overlay_state, base.base) base 77 drivers/gpu/drm/armada/armada_overlay.c DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); base 83 drivers/gpu/drm/armada/armada_overlay.c plane->base.id, plane->name, base 84 drivers/gpu/drm/armada/armada_overlay.c state->crtc->base.id, state->crtc->name, base 85 drivers/gpu/drm/armada/armada_overlay.c state->fb->base.id, base 221 drivers/gpu/drm/armada/armada_overlay.c DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); base 227 drivers/gpu/drm/armada/armada_overlay.c plane->base.id, plane->name, base 228 drivers/gpu/drm/armada/armada_overlay.c old_state->crtc->base.id, old_state->crtc->name, base 229 drivers/gpu/drm/armada/armada_overlay.c old_state->fb->base.id); base 322 drivers/gpu/drm/armada/armada_overlay.c __drm_atomic_helper_plane_reset(plane, &state->base.base); base 323 drivers/gpu/drm/armada/armada_overlay.c state->base.base.color_encoding = DEFAULT_ENCODING; base 324 drivers/gpu/drm/armada/armada_overlay.c state->base.base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; base 339 drivers/gpu/drm/armada/armada_overlay.c &state->base.base); base 340 drivers/gpu/drm/armada/armada_overlay.c return &state->base.base; base 568 drivers/gpu/drm/armada/armada_overlay.c mobj = &overlay->base; base 85 drivers/gpu/drm/armada/armada_plane.c plane->base.id, plane->name, base 86 drivers/gpu/drm/armada/armada_plane.c state->fb ? state->fb->base.id : 0); base 101 drivers/gpu/drm/armada/armada_plane.c plane->base.id, plane->name, base 102 drivers/gpu/drm/armada/armada_plane.c old_state->fb ? old_state->fb->base.id : 0); base 167 drivers/gpu/drm/armada/armada_plane.c DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); base 173 drivers/gpu/drm/armada/armada_plane.c plane->base.id, plane->name, base 174 drivers/gpu/drm/armada/armada_plane.c state->crtc->base.id, state->crtc->name, base 175 drivers/gpu/drm/armada/armada_plane.c state->fb->base.id, base 251 drivers/gpu/drm/armada/armada_plane.c DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name); base 257 drivers/gpu/drm/armada/armada_plane.c plane->base.id, plane->name, base 258 drivers/gpu/drm/armada/armada_plane.c old_state->crtc->base.id, old_state->crtc->name, base 259 drivers/gpu/drm/armada/armada_plane.c old_state->fb->base.id); base 289 drivers/gpu/drm/armada/armada_plane.c __drm_atomic_helper_plane_reset(plane, &st->base); base 301 drivers/gpu/drm/armada/armada_plane.c __drm_atomic_helper_plane_duplicate_state(plane, &st->base); base 303 drivers/gpu/drm/armada/armada_plane.c return &st->base; base 5 drivers/gpu/drm/armada/armada_plane.h struct drm_plane_state base; base 15 drivers/gpu/drm/armada/armada_plane.h container_of(st, struct armada_plane_state, base) base 8 drivers/gpu/drm/aspeed/aspeed_gfx.h void __iomem *base; base 33 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c ctrl1 = readl(priv->base + CRT_CTRL1); base 52 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(ctrl1, priv->base + CRT_CTRL1); base 59 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 ctrl1 = readl(priv->base + CRT_CTRL1); base 60 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 ctrl2 = readl(priv->base + CRT_CTRL2); base 65 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(ctrl1 | CRT_CTRL_EN, priv->base + CRT_CTRL1); base 66 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(ctrl2 | CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2); base 71 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 ctrl1 = readl(priv->base + CRT_CTRL1); base 72 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 ctrl2 = readl(priv->base + CRT_CTRL2); base 74 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(ctrl1 & ~CRT_CTRL_EN, priv->base + CRT_CTRL1); base 75 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(ctrl2 & ~CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2); base 96 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c ctrl1 = readl(priv->base + CRT_CTRL1); base 110 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(ctrl1, priv->base + CRT_CTRL1); base 114 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c priv->base + CRT_HORIZ0); base 116 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c priv->base + CRT_HORIZ1); base 121 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c priv->base + CRT_VERT0); base 123 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c priv->base + CRT_VERT1); base 132 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c priv->base + CRT_OFFSET); base 138 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(G5_CRT_THROD_VAL, priv->base + CRT_THROD); base 189 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(gem->paddr, priv->base + CRT_ADDR); base 195 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 reg = readl(priv->base + CRT_CTRL1); base 198 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(reg | CRT_CTRL_VERTICAL_INTR_STS, priv->base + CRT_CTRL1); base 201 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(reg, priv->base + CRT_CTRL1); base 209 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 reg = readl(priv->base + CRT_CTRL1); base 212 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(reg, priv->base + CRT_CTRL1); base 215 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(reg | CRT_CTRL_VERTICAL_INTR_STS, priv->base + CRT_CTRL1); base 83 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c reg = readl(priv->base + CRT_CTRL1); base 87 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c writel(reg, priv->base + CRT_CTRL1); base 109 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c priv->base = devm_ioremap_resource(drm->dev, res); base 110 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c if (IS_ERR(priv->base)) base 111 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c return PTR_ERR(priv->base); base 149 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c writel(0, priv->base + CRT_CTRL1); base 150 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c writel(0, priv->base + CRT_CTRL2); base 78 drivers/gpu/drm/ast/ast_drv.c ap->ranges[0].base = pci_resource_start(pdev, 0); base 175 drivers/gpu/drm/ast/ast_drv.h uint32_t base, uint8_t index, base 178 drivers/gpu/drm/ast/ast_drv.h ast_io_write16(ast, base, ((u16)val << 8) | index); base 182 drivers/gpu/drm/ast/ast_drv.h uint32_t base, uint8_t index, base 185 drivers/gpu/drm/ast/ast_drv.h uint32_t base, uint8_t index); base 187 drivers/gpu/drm/ast/ast_drv.h uint32_t base, uint8_t index, uint8_t mask); base 226 drivers/gpu/drm/ast/ast_drv.h struct drm_connector base; base 231 drivers/gpu/drm/ast/ast_drv.h struct drm_crtc base; base 236 drivers/gpu/drm/ast/ast_drv.h struct drm_encoder base; base 239 drivers/gpu/drm/ast/ast_drv.h #define to_ast_crtc(x) container_of(x, struct ast_crtc, base) base 240 drivers/gpu/drm/ast/ast_drv.h #define to_ast_connector(x) container_of(x, struct ast_connector, base) base 241 drivers/gpu/drm/ast/ast_drv.h #define to_ast_encoder(x) container_of(x, struct ast_encoder, base) base 41 drivers/gpu/drm/ast/ast_main.c uint32_t base, uint8_t index, base 45 drivers/gpu/drm/ast/ast_main.c ast_io_write8(ast, base, index); base 46 drivers/gpu/drm/ast/ast_main.c tmp = (ast_io_read8(ast, base + 1) & mask) | val; base 47 drivers/gpu/drm/ast/ast_main.c ast_set_index_reg(ast, base, index, tmp); base 51 drivers/gpu/drm/ast/ast_main.c uint32_t base, uint8_t index) base 54 drivers/gpu/drm/ast/ast_main.c ast_io_write8(ast, base, index); base 55 drivers/gpu/drm/ast/ast_main.c ret = ast_io_read8(ast, base + 1); base 60 drivers/gpu/drm/ast/ast_main.c uint32_t base, uint8_t index, uint8_t mask) base 63 drivers/gpu/drm/ast/ast_main.c ast_io_write8(ast, base, index); base 64 drivers/gpu/drm/ast/ast_main.c ret = ast_io_read8(ast, base + 1) & mask; base 560 drivers/gpu/drm/ast/ast_main.c *obj = &gbo->bo.base; base 678 drivers/gpu/drm/ast/ast_mode.c drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs); base 679 drivers/gpu/drm/ast/ast_mode.c drm_mode_crtc_set_gamma_size(&crtc->base, 256); base 680 drivers/gpu/drm/ast/ast_mode.c drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs); base 742 drivers/gpu/drm/ast/ast_mode.c drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs, base 744 drivers/gpu/drm/ast/ast_mode.c drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs); base 746 drivers/gpu/drm/ast/ast_mode.c ast_encoder->base.possible_crtcs = 1; base 772 drivers/gpu/drm/ast/ast_mode.c drm_connector_update_edid_property(&ast_connector->base, edid); base 777 drivers/gpu/drm/ast/ast_mode.c drm_connector_update_edid_property(&ast_connector->base, NULL); base 869 drivers/gpu/drm/ast/ast_mode.c connector = &ast_connector->base; base 903 drivers/gpu/drm/ast/ast_mode.c void *base; base 922 drivers/gpu/drm/ast/ast_mode.c base = drm_gem_vram_kmap(gbo, true, NULL); base 923 drivers/gpu/drm/ast/ast_mode.c if (IS_ERR(base)) { base 924 drivers/gpu/drm/ast/ast_mode.c ret = PTR_ERR(base); base 34 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c struct drm_crtc_state base; base 41 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c return container_of(state, struct atmel_hlcdc_crtc_state, base); base 53 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c struct drm_crtc base; base 62 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c return container_of(crtc, struct atmel_hlcdc_crtc, base); base 384 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c struct drm_device *dev = crtc->base.dev; base 389 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c drm_crtc_send_vblank_event(&crtc->base, crtc->event); base 390 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c drm_crtc_vblank_put(&crtc->base); base 415 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c crtc->state = &state->base; base 431 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); base 436 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c return &state->base; base 512 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c ret = drm_crtc_init_with_planes(dev, &crtc->base, &primary->base, base 513 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c &cursor->base, &atmel_hlcdc_crtc_funcs, base 518 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c crtc->id = drm_crtc_index(&crtc->base); base 526 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c overlay->base.possible_crtcs = 1 << crtc->id; base 530 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs); base 531 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c drm_crtc_vblank_reset(&crtc->base); base 533 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE); base 534 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c drm_crtc_enable_color_mgmt(&crtc->base, 0, false, base 537 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c dc->crtc = &crtc->base; base 542 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c atmel_hlcdc_crtc_destroy(&crtc->base); base 275 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h struct drm_plane base; base 282 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h return container_of(p, struct atmel_hlcdc_plane, base); base 45 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c struct drm_plane_state base; base 76 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c return container_of(s, struct atmel_hlcdc_plane_state, base); base 362 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c const struct drm_format_info *format = state->base.fb->format; base 376 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) { base 384 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c ATMEL_HLCDC_LAYER_GA(state->base.alpha); base 400 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c ret = atmel_hlcdc_format_to_plane_mode(state->base.fb->format->format, base 405 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c if ((state->base.fb->format->format == DRM_FORMAT_YUV422 || base 406 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c state->base.fb->format->format == DRM_FORMAT_NV61) && base 407 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c drm_rotation_90_or_270(state->base.rotation)) base 417 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c struct drm_crtc *crtc = state->base.crtc; base 442 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c struct drm_framebuffer *fb = state->base.fb; base 532 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c &primary->base); base 601 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c struct drm_framebuffer *fb = state->base.fb; base 608 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c if (!state->base.crtc || !fb) base 651 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c switch (state->base.rotation & DRM_MODE_ROTATE_MASK) { base 696 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c if (drm_rotation_90_or_270(state->base.rotation)) { base 709 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c state->base.fb->format->has_alpha)) base 745 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c if (!state->base.visible) { base 779 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c ret = drm_plane_create_alpha_property(&plane->base); base 787 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c ret = drm_plane_create_rotation_property(&plane->base, base 831 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c dev_dbg(plane->base.dev->dev, "overrun on plane %s\n", base 881 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c if (state->base.fb) base 882 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c drm_framebuffer_put(state->base.fb); base 896 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c __drm_atomic_helper_plane_reset(p, &state->base); base 916 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c if (copy->base.fb) base 917 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c drm_framebuffer_get(copy->base.fb); base 919 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c return ©->base; base 971 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c ret = drm_universal_plane_init(dev, &plane->base, 0, base 979 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c drm_plane_helper_add(&plane->base, base 454 drivers/gpu/drm/bridge/cdns-dsi.c struct mipi_dsi_host base; base 475 drivers/gpu/drm/bridge/cdns-dsi.c return container_of(host, struct cdns_dsi, base); base 655 drivers/gpu/drm/bridge/cdns-dsi.c dev_err(dsi->base.dev, base 709 drivers/gpu/drm/bridge/cdns-dsi.c pm_runtime_put(dsi->base.dev); base 790 drivers/gpu/drm/bridge/cdns-dsi.c if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0)) base 886 drivers/gpu/drm/bridge/cdns-dsi.c dev_err(dsi->base.dev, "Unsupported DSI format\n"); base 952 drivers/gpu/drm/bridge/cdns-dsi.c np = of_graph_get_remote_node(dsi->base.dev->of_node, DSI_OUTPUT_PORT, base 1253 drivers/gpu/drm/bridge/cdns-dsi.c dsi->base.dev = &pdev->dev; base 1254 drivers/gpu/drm/bridge/cdns-dsi.c dsi->base.ops = &cdns_dsi_ops; base 1256 drivers/gpu/drm/bridge/cdns-dsi.c ret = mipi_dsi_host_register(&dsi->base); base 1277 drivers/gpu/drm/bridge/cdns-dsi.c mipi_dsi_host_unregister(&dsi->base); base 235 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c void __iomem *base = dw->data.base; base 244 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c base + HDMI_IH_AHBDMAAUD_STAT0); base 250 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c dw_hdmi_writel(start, base + HDMI_AHB_DMA_STRADDR0); base 251 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c dw_hdmi_writel(stop, base + HDMI_AHB_DMA_STPADDR0); base 253 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, base + HDMI_AHB_DMA_MASK); base 254 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb(HDMI_AHB_DMA_START_START, base + HDMI_AHB_DMA_START); base 265 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(~0, dw->data.base + HDMI_AHB_DMA_MASK); base 266 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, dw->data.base + HDMI_AHB_DMA_STOP); base 275 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c stat = readb_relaxed(dw->data.base + HDMI_IH_AHBDMAAUD_STAT0); base 279 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(stat, dw->data.base + HDMI_IH_AHBDMAAUD_STAT0); base 322 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c void __iomem *base = dw->data.base; base 349 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c base + HDMI_AHB_DMA_CONF0); base 352 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(~0, base + HDMI_AHB_DMA_POL); base 353 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(~0, base + HDMI_AHB_DMA_BUFFPOL); base 356 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(~0, base + HDMI_AHB_DMA_MASK); base 357 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(~0, base + HDMI_IH_AHBDMAAUD_STAT0); base 367 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); base 378 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c dw->data.base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); base 433 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD); base 434 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0); base 435 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1); base 528 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c data->base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); base 529 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c revision = readb_relaxed(data->base + HDMI_REVISION_ID); base 9 drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h void __iomem *base; base 2822 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c audio.base = hdmi->regs; base 229 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c void __iomem *base; base 285 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c writel(val, dsi->base + reg); base 290 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c return readl(dsi->base + reg); base 377 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, base 388 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, base 420 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, base 443 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, base 453 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, base 775 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, base 780 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, base 999 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c if (!plat_data->base) { base 1004 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c dsi->base = devm_ioremap_resource(dev, res); base 1005 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c if (IS_ERR(dsi->base)) base 1009 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c dsi->base = plat_data->base; base 231 drivers/gpu/drm/bridge/tc358767.c struct drm_dp_link base; base 440 drivers/gpu/drm/bridge/tc358767.c if (tc->link.base.num_lanes == 2) base 442 drivers/gpu/drm/bridge/tc358767.c if (tc->link.base.rate != 162000) base 669 drivers/gpu/drm/bridge/tc358767.c ret = drm_dp_link_probe(&tc->aux, &tc->link.base); base 672 drivers/gpu/drm/bridge/tc358767.c if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) { base 674 drivers/gpu/drm/bridge/tc358767.c tc->link.base.rate = 270000; base 677 drivers/gpu/drm/bridge/tc358767.c if (tc->link.base.num_lanes > 2) { base 679 drivers/gpu/drm/bridge/tc358767.c tc->link.base.num_lanes = 2; base 699 drivers/gpu/drm/bridge/tc358767.c tc->link.base.revision >> 4, tc->link.base.revision & 0x0f, base 700 drivers/gpu/drm/bridge/tc358767.c (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps", base 701 drivers/gpu/drm/bridge/tc358767.c tc->link.base.num_lanes, base 702 drivers/gpu/drm/bridge/tc358767.c (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? base 742 drivers/gpu/drm/bridge/tc358767.c out_bw = tc->link.base.num_lanes * tc->link.base.rate; base 904 drivers/gpu/drm/bridge/tc358767.c ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); base 914 drivers/gpu/drm/bridge/tc358767.c if (tc->link.base.num_lanes == 2) base 977 drivers/gpu/drm/bridge/tc358767.c ret = drm_dp_link_configure(aux, &tc->link.base); base 1021 drivers/gpu/drm/bridge/tc358767.c ((tc->link.base.capabilities & base 1102 drivers/gpu/drm/bridge/tc358767.c if (tc->link.base.num_lanes == 2) { base 1173 drivers/gpu/drm/bridge/tc358767.c if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) base 1299 drivers/gpu/drm/bridge/tc358767.c avail = tc->link.base.num_lanes * tc->link.base.rate; base 90 drivers/gpu/drm/cirrus/cirrus_drv.h #define to_cirrus_crtc(x) container_of(x, struct cirrus_crtc, base) base 91 drivers/gpu/drm/cirrus/cirrus_drv.h #define to_cirrus_encoder(x) container_of(x, struct cirrus_encoder, base) base 94 drivers/gpu/drm/cirrus/cirrus_drv.h struct drm_crtc base; base 107 drivers/gpu/drm/cirrus/cirrus_drv.h struct drm_encoder base; base 112 drivers/gpu/drm/cirrus/cirrus_drv.h struct drm_connector base; base 167 drivers/gpu/drm/cirrus/cirrus_drv.h #define to_cirrus_obj(x) container_of(x, struct cirrus_gem_object, base) base 332 drivers/gpu/drm/drm_agpsupport.c entry->bound = dev->agp->base + (page << PAGE_SHIFT); base 334 drivers/gpu/drm/drm_agpsupport.c dev->agp->base, entry->bound); base 429 drivers/gpu/drm/drm_agpsupport.c head->base = head->agp_info.aper_base; base 317 drivers/gpu/drm/drm_atomic.c crtc->base.id, crtc->name, crtc_state, state); base 338 drivers/gpu/drm/drm_atomic.c crtc->base.id, crtc->name); base 348 drivers/gpu/drm/drm_atomic.c crtc->base.id, crtc->name); base 355 drivers/gpu/drm/drm_atomic.c crtc->base.id, crtc->name); base 372 drivers/gpu/drm/drm_atomic.c crtc->base.id, crtc->name); base 384 drivers/gpu/drm/drm_atomic.c drm_printf(p, "crtc[%u]: %s\n", crtc->base.id, crtc->name); base 418 drivers/gpu/drm/drm_atomic.c connector->base.id, connector->name); base 428 drivers/gpu/drm/drm_atomic.c connector->base.id, connector->name, base 429 drivers/gpu/drm/drm_atomic.c state->crtc->base.id); base 436 drivers/gpu/drm/drm_atomic.c connector->base.id, connector->name); base 495 drivers/gpu/drm/drm_atomic.c plane->base.id, plane->name, plane_state, state); base 552 drivers/gpu/drm/drm_atomic.c plane->base.id, plane->name); base 556 drivers/gpu/drm/drm_atomic.c plane->base.id, plane->name); base 567 drivers/gpu/drm/drm_atomic.c crtc->base.id, crtc->name, base 568 drivers/gpu/drm/drm_atomic.c plane->base.id, plane->name); base 578 drivers/gpu/drm/drm_atomic.c plane->base.id, plane->name, base 591 drivers/gpu/drm/drm_atomic.c plane->base.id, plane->name, base 607 drivers/gpu/drm/drm_atomic.c plane->base.id, plane->name, base 632 drivers/gpu/drm/drm_atomic.c plane->base.id, plane->name, clips->x1, base 642 drivers/gpu/drm/drm_atomic.c plane->base.id, plane->name); base 656 drivers/gpu/drm/drm_atomic.c drm_printf(p, "plane[%u]: %s\n", plane->base.id, plane->name); base 658 drivers/gpu/drm/drm_atomic.c drm_printf(p, "\tfb=%u\n", state->fb ? state->fb->base.id : 0); base 985 drivers/gpu/drm/drm_atomic.c connector->base.id, connector->name, base 1006 drivers/gpu/drm/drm_atomic.c drm_printf(p, "connector[%u]: %s\n", connector->base.id, connector->name); base 1012 drivers/gpu/drm/drm_atomic.c drm_printf(p, "\tfb=%d\n", state->writeback_job->fb->base.id); base 1055 drivers/gpu/drm/drm_atomic.c crtc->base.id, crtc->name, state); base 1109 drivers/gpu/drm/drm_atomic.c crtc->base.id, crtc->name, state); base 1153 drivers/gpu/drm/drm_atomic.c plane->base.id, plane->name); base 1162 drivers/gpu/drm/drm_atomic.c crtc->base.id, crtc->name); base 1171 drivers/gpu/drm/drm_atomic.c conn->base.id, conn->name); base 1190 drivers/gpu/drm/drm_atomic.c crtc->base.id, crtc->name); base 143 drivers/gpu/drm/drm_atomic_helper.c new_encoder->base.id, new_encoder->name, base 144 drivers/gpu/drm/drm_atomic_helper.c connector->base.id, connector->name); base 180 drivers/gpu/drm/drm_atomic_helper.c encoder->base.id, encoder->name, base 181 drivers/gpu/drm/drm_atomic_helper.c connector->state->crtc->base.id, base 183 drivers/gpu/drm/drm_atomic_helper.c connector->base.id, connector->name); base 195 drivers/gpu/drm/drm_atomic_helper.c encoder->base.id, encoder->name, base 196 drivers/gpu/drm/drm_atomic_helper.c new_conn_state->crtc->base.id, new_conn_state->crtc->name, base 197 drivers/gpu/drm/drm_atomic_helper.c connector->base.id, connector->name); base 279 drivers/gpu/drm/drm_atomic_helper.c encoder->base.id, encoder->name, base 280 drivers/gpu/drm/drm_atomic_helper.c encoder_crtc->base.id, encoder_crtc->name); base 302 drivers/gpu/drm/drm_atomic_helper.c connector->base.id, base 319 drivers/gpu/drm/drm_atomic_helper.c connector->base.id, base 350 drivers/gpu/drm/drm_atomic_helper.c connector->base.id, connector->name); base 366 drivers/gpu/drm/drm_atomic_helper.c connector->base.id, base 373 drivers/gpu/drm/drm_atomic_helper.c new_encoder->base.id, base 375 drivers/gpu/drm/drm_atomic_helper.c new_connector_state->crtc->base.id, base 384 drivers/gpu/drm/drm_atomic_helper.c connector->base.id, base 386 drivers/gpu/drm/drm_atomic_helper.c new_encoder->base.id, base 388 drivers/gpu/drm/drm_atomic_helper.c new_connector_state->crtc->base.id, base 401 drivers/gpu/drm/drm_atomic_helper.c connector->base.id, base 403 drivers/gpu/drm/drm_atomic_helper.c new_encoder->base.id, base 405 drivers/gpu/drm/drm_atomic_helper.c new_connector_state->crtc->base.id, base 460 drivers/gpu/drm/drm_atomic_helper.c encoder->base.id, encoder->name); base 468 drivers/gpu/drm/drm_atomic_helper.c encoder->base.id, encoder->name); base 492 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 510 drivers/gpu/drm/drm_atomic_helper.c encoder->base.id, encoder->name); base 523 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 625 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 631 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 647 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 653 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 709 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name, base 885 drivers/gpu/drm/drm_atomic_helper.c plane->base.id, plane->name); base 901 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 1027 drivers/gpu/drm/drm_atomic_helper.c encoder->base.id, encoder->name); base 1064 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 1191 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 1215 drivers/gpu/drm/drm_atomic_helper.c encoder->base.id, encoder->name); base 1316 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 1339 drivers/gpu/drm/drm_atomic_helper.c encoder->base.id, encoder->name); base 1468 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 1508 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 1922 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 2061 drivers/gpu/drm/drm_atomic_helper.c new_crtc_state->event->base.completion = &commit->flip_done; base 2062 drivers/gpu/drm/drm_atomic_helper.c new_crtc_state->event->base.completion_release = release_crtc_commit; base 2139 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 2147 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 2160 drivers/gpu/drm/drm_atomic_helper.c conn->base.id, conn->name); base 2168 drivers/gpu/drm/drm_atomic_helper.c conn->base.id, conn->name); base 2181 drivers/gpu/drm/drm_atomic_helper.c plane->base.id, plane->name); base 2189 drivers/gpu/drm/drm_atomic_helper.c plane->base.id, plane->name); base 3326 drivers/gpu/drm/drm_atomic_helper.c crtc->base.id, crtc->name); base 89 drivers/gpu/drm/drm_atomic_uapi.c mode->name, crtc->base.id, crtc->name, state); base 94 drivers/gpu/drm/drm_atomic_uapi.c crtc->base.id, crtc->name, state); base 132 drivers/gpu/drm/drm_atomic_uapi.c crtc->base.id, crtc->name, base 141 drivers/gpu/drm/drm_atomic_uapi.c crtc->base.id, crtc->name, base 150 drivers/gpu/drm/drm_atomic_uapi.c state->mode.name, crtc->base.id, crtc->name, base 155 drivers/gpu/drm/drm_atomic_uapi.c crtc->base.id, crtc->name, state); base 206 drivers/gpu/drm/drm_atomic_uapi.c plane->base.id, plane->name, plane_state, base 207 drivers/gpu/drm/drm_atomic_uapi.c crtc->base.id, crtc->name); base 210 drivers/gpu/drm/drm_atomic_uapi.c plane->base.id, plane->name, plane_state); base 234 drivers/gpu/drm/drm_atomic_uapi.c fb->base.id, plane->base.id, plane->name, base 238 drivers/gpu/drm/drm_atomic_uapi.c plane->base.id, plane->name, plane_state); base 328 drivers/gpu/drm/drm_atomic_uapi.c connector->base.id, connector->name, base 329 drivers/gpu/drm/drm_atomic_uapi.c conn_state, crtc->base.id, crtc->name); base 332 drivers/gpu/drm/drm_atomic_uapi.c connector->base.id, connector->name, base 476 drivers/gpu/drm/drm_atomic_uapi.c crtc->base.id, crtc->name, base 477 drivers/gpu/drm/drm_atomic_uapi.c property->base.id, property->name); base 495 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->mode_blob) ? state->mode_blob->base.id : 0; base 499 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0; base 501 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->ctm) ? state->ctm->base.id : 0; base 503 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0; base 568 drivers/gpu/drm/drm_atomic_uapi.c plane->base.id, plane->name, val); base 591 drivers/gpu/drm/drm_atomic_uapi.c plane->base.id, plane->name, base 592 drivers/gpu/drm/drm_atomic_uapi.c property->base.id, property->name); base 608 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->fb) ? state->fb->base.id : 0; base 612 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->crtc) ? state->crtc->base.id : 0; base 643 drivers/gpu/drm/drm_atomic_uapi.c state->fb_damage_clips->base.id : 0; base 665 drivers/gpu/drm/drm_atomic_uapi.c fb->base.id, conn_state); base 774 drivers/gpu/drm/drm_atomic_uapi.c connector->base.id, connector->name, base 775 drivers/gpu/drm/drm_atomic_uapi.c property->base.id, property->name); base 791 drivers/gpu/drm/drm_atomic_uapi.c *val = (state->crtc) ? state->crtc->base.id : 0; base 833 drivers/gpu/drm/drm_atomic_uapi.c state->hdr_output_metadata->base.id : 0; base 904 drivers/gpu/drm/drm_atomic_uapi.c e->event.base.type = DRM_EVENT_FLIP_COMPLETE; base 905 drivers/gpu/drm/drm_atomic_uapi.c e->event.base.length = sizeof(e->event); base 906 drivers/gpu/drm/drm_atomic_uapi.c e->event.vbl.crtc_id = crtc->base.id; base 1140 drivers/gpu/drm/drm_atomic_uapi.c ret = drm_event_reserve_init(dev, file_priv, &e->base, base 1141 drivers/gpu/drm/drm_atomic_uapi.c &e->event.base); base 1173 drivers/gpu/drm/drm_atomic_uapi.c crtc_state->event->base.fence = fence; base 1252 drivers/gpu/drm/drm_atomic_uapi.c if (event && (event->base.fence || event->base.file_priv)) { base 1253 drivers/gpu/drm/drm_atomic_uapi.c drm_event_cancel_free(dev, &event->base); base 208 drivers/gpu/drm/drm_blend.c drm_object_attach_property(&plane->base, prop, DRM_BLEND_ALPHA_OPAQUE); base 276 drivers/gpu/drm/drm_blend.c drm_object_attach_property(&plane->base, prop, rotation); base 359 drivers/gpu/drm/drm_blend.c drm_object_attach_property(&plane->base, prop, zpos); base 398 drivers/gpu/drm/drm_blend.c drm_object_attach_property(&plane->base, prop, zpos); base 419 drivers/gpu/drm/drm_blend.c return sa->plane->base.id - sb->plane->base.id; base 434 drivers/gpu/drm/drm_blend.c crtc->base.id, crtc->name); base 453 drivers/gpu/drm/drm_blend.c plane->base.id, plane->name, base 464 drivers/gpu/drm/drm_blend.c plane->base.id, plane->name, i); base 593 drivers/gpu/drm/drm_blend.c drm_object_attach_property(&plane->base, prop, DRM_MODE_BLEND_PREMULTI); base 286 drivers/gpu/drm/drm_bufs.c if (map->offset < dev->agp->base || base 287 drivers/gpu/drm/drm_bufs.c map->offset > dev->agp->base + base 289 drivers/gpu/drm/drm_bufs.c map->offset += dev->agp->base; base 742 drivers/gpu/drm/drm_bufs.c agp_offset = dev->agp->base + request->agp_start; base 352 drivers/gpu/drm/drm_client.c ret = drm_mode_rmfb(buffer->client->dev, buffer->fb->base.id, buffer->client->file); base 355 drivers/gpu/drm/drm_client.c "Error removing FB:%u (%d)\n", buffer->fb->base.id, ret); base 215 drivers/gpu/drm/drm_client_modeset.c DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id, base 326 drivers/gpu/drm/drm_client_modeset.c connector->base.id); base 388 drivers/gpu/drm/drm_client_modeset.c connector->base.id); base 394 drivers/gpu/drm/drm_client_modeset.c connector->base.id, connector->tile_group ? connector->tile_group->id : 0); base 639 drivers/gpu/drm/drm_client_modeset.c connector->state->crtc->base.id, base 780 drivers/gpu/drm/drm_client_modeset.c mode->name, crtc->base.id, offset->x, offset->y); base 1091 drivers/gpu/drm/drm_client_modeset.c drm_object_property_set_value(&connector->base, base 162 drivers/gpu/drm/drm_color_mgmt.c drm_object_attach_property(&crtc->base, base 164 drivers/gpu/drm/drm_color_mgmt.c drm_object_attach_property(&crtc->base, base 170 drivers/gpu/drm/drm_color_mgmt.c drm_object_attach_property(&crtc->base, base 174 drivers/gpu/drm/drm_color_mgmt.c drm_object_attach_property(&crtc->base, base 176 drivers/gpu/drm/drm_color_mgmt.c drm_object_attach_property(&crtc->base, base 443 drivers/gpu/drm/drm_color_mgmt.c drm_object_attach_property(&plane->base, prop, default_encoding); base 462 drivers/gpu/drm/drm_color_mgmt.c drm_object_attach_property(&plane->base, prop, default_range); base 155 drivers/gpu/drm/drm_connector.c container_of(kref, struct drm_connector, base.refcount); base 158 drivers/gpu/drm/drm_connector.c drm_mode_object_unregister(dev, &connector->base); base 176 drivers/gpu/drm/drm_connector.c drm_mode_object_unregister(dev, &connector->base); base 208 drivers/gpu/drm/drm_connector.c ret = __drm_mode_object_add(dev, &connector->base, base 214 drivers/gpu/drm/drm_connector.c connector->base.properties = &connector->properties; base 267 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, base 270 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, base 274 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, base 277 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, base 282 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, config->prop_crtc_id, 0); base 294 drivers/gpu/drm/drm_connector.c drm_mode_object_unregister(dev, &connector->base); base 347 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, base 386 drivers/gpu/drm/drm_connector.c connector->encoder_ids[i] = encoder->base.id; base 460 drivers/gpu/drm/drm_connector.c drm_mode_object_unregister(dev, &connector->base); base 511 drivers/gpu/drm/drm_connector.c drm_mode_object_register(connector->dev, &connector->base); base 657 drivers/gpu/drm/drm_connector.c if (!refcount_dec_and_test(&conn->base.refcount.refcount)) base 692 drivers/gpu/drm/drm_connector.c } while (!kref_get_unless_zero(&iter->conn->base.refcount)); base 1264 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, base 1316 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, base 1319 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, base 1322 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, base 1325 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, base 1579 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, prop, 0); base 1637 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, base 1798 drivers/gpu/drm/drm_connector.c &connector->base, base 1828 drivers/gpu/drm/drm_connector.c &connector->base, base 1843 drivers/gpu/drm/drm_connector.c &connector->base, base 1890 drivers/gpu/drm/drm_connector.c drm_object_property_set_value(&connector->base, base 1898 drivers/gpu/drm/drm_connector.c &connector->base, base 1962 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, prop, max); base 1982 drivers/gpu/drm/drm_connector.c drm_object_property_set_value(&connector->base, base 2033 drivers/gpu/drm/drm_connector.c drm_object_attach_property(&connector->base, prop, base 2053 drivers/gpu/drm/drm_connector.c drm_object_property_set_value(&connector->base, property, value); base 2147 drivers/gpu/drm/drm_connector.c if (put_user(encoder->base.id, encoder_ptr + copied)) { base 2156 drivers/gpu/drm/drm_connector.c out_resp->connector_id = connector->base.id; base 2215 drivers/gpu/drm/drm_connector.c out_resp->encoder_id = encoder->base.id; base 2221 drivers/gpu/drm/drm_connector.c ret = drm_mode_object_get_properties(&connector->base, file_priv->atomic, base 253 drivers/gpu/drm/drm_crtc.c ret = drm_mode_object_add(dev, &crtc->base, DRM_MODE_OBJECT_CRTC); base 268 drivers/gpu/drm/drm_crtc.c drm_mode_object_unregister(dev, &crtc->base); base 275 drivers/gpu/drm/drm_crtc.c "CRTC:%d-%s", crtc->base.id, crtc->name); base 277 drivers/gpu/drm/drm_crtc.c crtc->base.properties = &crtc->properties; base 291 drivers/gpu/drm/drm_crtc.c drm_mode_object_unregister(dev, &crtc->base); base 296 drivers/gpu/drm/drm_crtc.c drm_object_attach_property(&crtc->base, config->prop_active, 0); base 297 drivers/gpu/drm/drm_crtc.c drm_object_attach_property(&crtc->base, config->prop_mode_id, 0); base 298 drivers/gpu/drm/drm_crtc.c drm_object_attach_property(&crtc->base, base 300 drivers/gpu/drm/drm_crtc.c drm_object_attach_property(&crtc->base, base 332 drivers/gpu/drm/drm_crtc.c drm_mode_object_unregister(dev, &crtc->base); base 379 drivers/gpu/drm/drm_crtc.c crtc_resp->fb_id = plane->state->fb->base.id; base 381 drivers/gpu/drm/drm_crtc.c crtc_resp->fb_id = plane->fb->base.id; base 556 drivers/gpu/drm/drm_crtc.c DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); base 561 drivers/gpu/drm/drm_crtc.c if (crtc_req->mode_valid && !drm_lease_held(file_priv, plane->base.id)) base 693 drivers/gpu/drm/drm_crtc.c connector->base.id, base 342 drivers/gpu/drm/drm_crtc_helper.c DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); base 382 drivers/gpu/drm/drm_crtc_helper.c encoder->base.id, encoder->name, mode->name); base 536 drivers/gpu/drm/drm_crtc_helper.c set->crtc->base.id, set->crtc->name, base 537 drivers/gpu/drm/drm_crtc_helper.c set->fb->base.id, base 541 drivers/gpu/drm/drm_crtc_helper.c set->crtc->base.id, set->crtc->name); base 691 drivers/gpu/drm/drm_crtc_helper.c connector->base.id, connector->name, base 692 drivers/gpu/drm/drm_crtc_helper.c new_crtc->base.id, new_crtc->name); base 695 drivers/gpu/drm/drm_crtc_helper.c connector->base.id, connector->name); base 714 drivers/gpu/drm/drm_crtc_helper.c set->crtc->base.id, set->crtc->name); base 721 drivers/gpu/drm/drm_crtc_helper.c DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id, base 101 drivers/gpu/drm/drm_damage_helper.c drm_object_attach_property(&plane->base, config->prop_fb_damage_clips, base 3279 drivers/gpu/drm/drm_dp_mst_topology.c port->connector->base.id, port->connector->name, base 3345 drivers/gpu/drm/drm_dp_mst_topology.c port, &topology_state->base); base 3784 drivers/gpu/drm/drm_dp_mst_topology.c __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); base 3801 drivers/gpu/drm/drm_dp_mst_topology.c return &state->base; base 3933 drivers/gpu/drm/drm_dp_mst_topology.c return to_dp_mst_topology_state(drm_atomic_get_private_obj_state(state, &mgr->base)); base 3990 drivers/gpu/drm/drm_dp_mst_topology.c drm_atomic_private_obj_init(dev, &mgr->base, base 3991 drivers/gpu/drm/drm_dp_mst_topology.c &mst_state->base, base 4015 drivers/gpu/drm/drm_dp_mst_topology.c drm_atomic_private_obj_fini(&mgr->base); base 1618 drivers/gpu/drm/drm_edid.c connector->base.id, connector->name, num_modes); base 1701 drivers/gpu/drm/drm_edid.c u8 *base; base 1713 drivers/gpu/drm/drm_edid.c base = new; base 1720 drivers/gpu/drm/drm_edid.c memcpy(base, block, EDID_LENGTH); base 1721 drivers/gpu/drm/drm_edid.c base += EDID_LENGTH; base 4722 drivers/gpu/drm/drm_edid.c struct displayid_hdr *base; base 4724 drivers/gpu/drm/drm_edid.c base = (struct displayid_hdr *)&displayid[idx]; base 4727 drivers/gpu/drm/drm_edid.c base->rev, base->bytes, base->prod_id, base->ext_count); base 4729 drivers/gpu/drm/drm_edid.c if (base->bytes + 5 > length - idx) base 4731 drivers/gpu/drm/drm_edid.c for (i = idx; i <= base->bytes + 5; i++) { base 119 drivers/gpu/drm/drm_encoder.c ret = drm_mode_object_add(dev, &encoder->base, DRM_MODE_OBJECT_ENCODER); base 135 drivers/gpu/drm/drm_encoder.c encoder->base.id); base 147 drivers/gpu/drm/drm_encoder.c drm_mode_object_unregister(dev, &encoder->base); base 179 drivers/gpu/drm/drm_encoder.c drm_mode_object_unregister(dev, &encoder->base); base 235 drivers/gpu/drm/drm_encoder.c if (crtc && drm_lease_held(file_priv, crtc->base.id)) base 236 drivers/gpu/drm/drm_encoder.c enc_resp->crtc_id = crtc->base.id; base 242 drivers/gpu/drm/drm_encoder.c enc_resp->encoder_id = encoder->base.id; base 90 drivers/gpu/drm/drm_encoder_slave.c encoder->slave_funcs->set_config(&encoder->base, base 362 drivers/gpu/drm/drm_framebuffer.c DRM_DEBUG_KMS("[FB:%d]\n", fb->base.id); base 363 drivers/gpu/drm/drm_framebuffer.c r->fb_id = fb->base.id; base 693 drivers/gpu/drm/drm_framebuffer.c container_of(kref, struct drm_framebuffer, base.refcount); base 700 drivers/gpu/drm/drm_framebuffer.c drm_mode_object_unregister(dev, &fb->base); base 736 drivers/gpu/drm/drm_framebuffer.c ret = __drm_mode_object_add(dev, &fb->base, DRM_MODE_OBJECT_FB, base 746 drivers/gpu/drm/drm_framebuffer.c drm_mode_object_register(dev, &fb->base); base 800 drivers/gpu/drm/drm_framebuffer.c drm_mode_object_unregister(dev, &fb->base); base 1076 drivers/gpu/drm/drm_framebuffer.c drm_printf(&p, "framebuffer[%u]:\n", fb->base.id); base 61 drivers/gpu/drm/drm_gem_cma_helper.c cma_obj = container_of(gem_obj, struct drm_gem_cma_object, base); base 117 drivers/gpu/drm/drm_gem_cma_helper.c drm_gem_object_put_unlocked(&cma_obj->base); base 151 drivers/gpu/drm/drm_gem_cma_helper.c gem_obj = &cma_obj->base; base 187 drivers/gpu/drm/drm_gem_cma_helper.c dma_free_wc(gem_obj->dev->dev, cma_obj->base.size, base 282 drivers/gpu/drm/drm_gem_cma_helper.c ret = dma_mmap_wc(cma_obj->base.dev->dev, vma, cma_obj->vaddr, base 505 drivers/gpu/drm/drm_gem_cma_helper.c return &cma_obj->base; base 604 drivers/gpu/drm/drm_gem_cma_helper.c cma_obj->base.funcs = &drm_cma_gem_default_funcs; base 606 drivers/gpu/drm/drm_gem_cma_helper.c return &cma_obj->base; base 140 drivers/gpu/drm/drm_gem_shmem_helper.c struct drm_gem_object *obj = &shmem->base; base 184 drivers/gpu/drm/drm_gem_shmem_helper.c struct drm_gem_object *obj = &shmem->base; base 247 drivers/gpu/drm/drm_gem_shmem_helper.c struct drm_gem_object *obj = &shmem->base; base 307 drivers/gpu/drm/drm_gem_shmem_helper.c struct drm_gem_object *obj = &shmem->base; base 356 drivers/gpu/drm/drm_gem_shmem_helper.c ret = drm_gem_handle_create(file_priv, &shmem->base, handle); base 358 drivers/gpu/drm/drm_gem_shmem_helper.c drm_gem_object_put_unlocked(&shmem->base); base 553 drivers/gpu/drm/drm_gem_shmem_helper.c vma->vm_pgoff -= drm_vma_node_start(&shmem->base.vma_node); base 622 drivers/gpu/drm/drm_gem_shmem_helper.c sgt = drm_gem_shmem_get_sg_table(&shmem->base); base 684 drivers/gpu/drm/drm_gem_shmem_helper.c return &shmem->base; base 689 drivers/gpu/drm/drm_gem_shmem_helper.c drm_gem_object_put_unlocked(&shmem->base); base 29 drivers/gpu/drm/drm_gem_vram_helper.c drm_gem_object_release(&gbo->bo.base); base 85 drivers/gpu/drm/drm_gem_vram_helper.c if (!gbo->bo.base.funcs) base 86 drivers/gpu/drm/drm_gem_vram_helper.c gbo->bo.base.funcs = &drm_gem_vram_object_funcs; base 88 drivers/gpu/drm/drm_gem_vram_helper.c ret = drm_gem_object_init(dev, &gbo->bo.base, size); base 106 drivers/gpu/drm/drm_gem_vram_helper.c drm_gem_object_release(&gbo->bo.base); base 171 drivers/gpu/drm/drm_gem_vram_helper.c return drm_vma_node_offset_addr(&gbo->bo.base.vma_node); base 386 drivers/gpu/drm/drm_gem_vram_helper.c ret = drm_gem_handle_create(file, &gbo->bo.base, &handle); base 390 drivers/gpu/drm/drm_gem_vram_helper.c drm_gem_object_put_unlocked(&gbo->bo.base); base 399 drivers/gpu/drm/drm_gem_vram_helper.c drm_gem_object_put_unlocked(&gbo->bo.base); base 449 drivers/gpu/drm/drm_gem_vram_helper.c return drm_vma_node_verify_access(&gbo->bo.base.vma_node, base 599 drivers/gpu/drm/drm_gem_vram_helper.c void *base; base 604 drivers/gpu/drm/drm_gem_vram_helper.c base = drm_gem_vram_kmap(gbo, true, NULL); base 605 drivers/gpu/drm/drm_gem_vram_helper.c if (IS_ERR(base)) { base 609 drivers/gpu/drm/drm_gem_vram_helper.c return base; base 405 drivers/gpu/drm/drm_hdcp.c drm_object_attach_property(&connector->base, prop, base 421 drivers/gpu/drm/drm_hdcp.c drm_object_attach_property(&connector->base, prop, base 167 drivers/gpu/drm/drm_lease.c if (_drm_lease_held_master(master, crtc->base.id)) { base 444 drivers/gpu/drm/drm_lease.c ret = idr_alloc(leases, &drm_lease_idr_object, crtc->primary->base.id, crtc->primary->base.id + 1, GFP_KERNEL); base 451 drivers/gpu/drm/drm_lease.c ret = idr_alloc(leases, &drm_lease_idr_object, crtc->cursor->base.id, crtc->cursor->base.id + 1, GFP_KERNEL); base 262 drivers/gpu/drm/drm_mipi_dbi.c DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect)); base 111 drivers/gpu/drm/drm_mode_config.c put_user(fb->base.id, fb_id + count)) { base 128 drivers/gpu/drm/drm_mode_config.c if (drm_lease_held(file_priv, crtc->base.id)) { base 130 drivers/gpu/drm/drm_mode_config.c put_user(crtc->base.id, crtc_id + count)) base 141 drivers/gpu/drm/drm_mode_config.c put_user(encoder->base.id, encoder_id + count)) base 156 drivers/gpu/drm/drm_mode_config.c if (drm_lease_held(file_priv, connector->base.id)) { base 158 drivers/gpu/drm/drm_mode_config.c put_user(connector->base.id, connector_id + count)) { base 498 drivers/gpu/drm/drm_mode_config.c drm_printf(&p, "framebuffer[%u]:\n", fb->base.id); base 500 drivers/gpu/drm/drm_mode_config.c drm_framebuffer_free(&fb->base.refcount); base 357 drivers/gpu/drm/drm_mode_object.c if (put_user(prop->base.id, prop_ptr + count)) base 426 drivers/gpu/drm/drm_mode_object.c if (obj->properties->properties[i]->base.id == prop_id) base 149 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->modifiers_property, base 150 drivers/gpu/drm/drm_plane.c blob->base.id); base 193 drivers/gpu/drm/drm_plane.c ret = drm_mode_object_add(dev, &plane->base, DRM_MODE_OBJECT_PLANE); base 199 drivers/gpu/drm/drm_plane.c plane->base.properties = &plane->properties; base 206 drivers/gpu/drm/drm_plane.c drm_mode_object_unregister(dev, &plane->base); base 234 drivers/gpu/drm/drm_plane.c drm_mode_object_unregister(dev, &plane->base); base 251 drivers/gpu/drm/drm_plane.c drm_mode_object_unregister(dev, &plane->base); base 265 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, base 270 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->prop_fb_id, 0); base 271 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->prop_in_fence_fd, -1); base 272 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->prop_crtc_id, 0); base 273 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->prop_crtc_x, 0); base 274 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->prop_crtc_y, 0); base 275 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->prop_crtc_w, 0); base 276 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->prop_crtc_h, 0); base 277 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->prop_src_x, 0); base 278 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->prop_src_y, 0); base 279 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->prop_src_w, 0); base 280 drivers/gpu/drm/drm_plane.c drm_object_attach_property(&plane->base, config->prop_src_h, 0); base 363 drivers/gpu/drm/drm_plane.c drm_mode_object_unregister(dev, &plane->base); base 463 drivers/gpu/drm/drm_plane.c struct drm_mode_object *obj = &plane->base; base 500 drivers/gpu/drm/drm_plane.c if (drm_lease_held(file_priv, plane->base.id)) { base 502 drivers/gpu/drm/drm_plane.c put_user(plane->base.id, plane_ptr + count)) base 527 drivers/gpu/drm/drm_plane.c if (plane->state && plane->state->crtc && drm_lease_held(file_priv, plane->state->crtc->base.id)) base 528 drivers/gpu/drm/drm_plane.c plane_resp->crtc_id = plane->state->crtc->base.id; base 529 drivers/gpu/drm/drm_plane.c else if (!plane->state && plane->crtc && drm_lease_held(file_priv, plane->crtc->base.id)) base 530 drivers/gpu/drm/drm_plane.c plane_resp->crtc_id = plane->crtc->base.id; base 535 drivers/gpu/drm/drm_plane.c plane_resp->fb_id = plane->state->fb->base.id; base 537 drivers/gpu/drm/drm_plane.c plane_resp->fb_id = plane->fb->base.id; base 542 drivers/gpu/drm/drm_plane.c plane_resp->plane_id = plane->base.id; base 963 drivers/gpu/drm/drm_plane.c if (!drm_lease_held(file_priv, crtc->cursor->base.id)) { base 1070 drivers/gpu/drm/drm_plane.c if (!drm_lease_held(file_priv, plane->base.id)) base 1169 drivers/gpu/drm/drm_plane.c e->event.base.type = DRM_EVENT_FLIP_COMPLETE; base 1170 drivers/gpu/drm/drm_plane.c e->event.base.length = sizeof(e->event); base 1172 drivers/gpu/drm/drm_plane.c e->event.vbl.crtc_id = crtc->base.id; base 1174 drivers/gpu/drm/drm_plane.c ret = drm_event_reserve_init(dev, file_priv, &e->base, &e->event.base); base 1193 drivers/gpu/drm/drm_plane.c drm_event_cancel_free(dev, &e->base); base 285 drivers/gpu/drm/drm_print.c readl(regset->base + regset->regs[i].offset)); base 405 drivers/gpu/drm/drm_probe_helper.c DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, base 450 drivers/gpu/drm/drm_probe_helper.c connector->base.id, base 475 drivers/gpu/drm/drm_probe_helper.c connector->base.id, connector->name); base 538 drivers/gpu/drm/drm_probe_helper.c DRM_DEBUG_KMS("[CONNECTOR:%d:%s] probed modes :\n", connector->base.id, base 647 drivers/gpu/drm/drm_probe_helper.c connector->base.id, base 794 drivers/gpu/drm/drm_probe_helper.c connector->base.id, base 122 drivers/gpu/drm/drm_property.c ret = drm_mode_object_add(dev, &property->base, DRM_MODE_OBJECT_PROPERTY); base 453 drivers/gpu/drm/drm_property.c drm_mode_object_unregister(dev, &property->base); base 532 drivers/gpu/drm/drm_property.c container_of(kref, struct drm_property_blob, base.refcount); base 538 drivers/gpu/drm/drm_property.c drm_mode_object_unregister(blob->dev, &blob->base); base 581 drivers/gpu/drm/drm_property.c ret = __drm_mode_object_add(dev, &blob->base, DRM_MODE_OBJECT_BLOB, base 608 drivers/gpu/drm/drm_property.c drm_mode_object_put(&blob->base); base 636 drivers/gpu/drm/drm_property.c drm_mode_object_get(&blob->base); base 718 drivers/gpu/drm/drm_property.c new_blob->base.id : 0); base 811 drivers/gpu/drm/drm_property.c out_resp->blob_id = blob->base.id; base 912 drivers/gpu/drm/drm_property.c *ref = &blob->base; base 240 drivers/gpu/drm/drm_syncobj.c rcu_assign_pointer(syncobj->fence, &chain->base); base 138 drivers/gpu/drm/drm_sysfs.c connector->base.id, base 369 drivers/gpu/drm/drm_sysfs.c WARN_ON(!drm_mode_obj_find_prop_id(&connector->base, base 370 drivers/gpu/drm/drm_sysfs.c property->base.id)); base 373 drivers/gpu/drm/drm_sysfs.c "CONNECTOR=%u", connector->base.id); base 375 drivers/gpu/drm/drm_sysfs.c "PROPERTY=%u", property->base.id); base 551 drivers/gpu/drm/drm_vblank.c crtc->base.id); base 558 drivers/gpu/drm/drm_vblank.c crtc->base.id, mode->crtc_htotal, base 561 drivers/gpu/drm/drm_vblank.c crtc->base.id, dotclock, framedur_ns, linedur_ns); base 835 drivers/gpu/drm/drm_vblank.c switch (e->event.base.type) { base 854 drivers/gpu/drm/drm_vblank.c trace_drm_vblank_event_delivered(e->base.file_priv, e->pipe, seq); base 855 drivers/gpu/drm/drm_vblank.c drm_send_event_locked(dev, &e->base); base 906 drivers/gpu/drm/drm_vblank.c list_add_tail(&e->base.link, &dev->vblank_event_list); base 1172 drivers/gpu/drm/drm_vblank.c list_for_each_entry_safe(e, t, &dev->vblank_event_list, base.link) { base 1178 drivers/gpu/drm/drm_vblank.c list_del(&e->base.link); base 1469 drivers/gpu/drm/drm_vblank.c e->event.base.type = DRM_EVENT_VBLANK; base 1470 drivers/gpu/drm/drm_vblank.c e->event.base.length = sizeof(e->event.vbl); base 1476 drivers/gpu/drm/drm_vblank.c e->event.vbl.crtc_id = crtc->base.id; base 1492 drivers/gpu/drm/drm_vblank.c ret = drm_event_reserve_init_locked(dev, file_priv, &e->base, base 1493 drivers/gpu/drm/drm_vblank.c &e->event.base); base 1512 drivers/gpu/drm/drm_vblank.c list_add_tail(&e->base.link, &dev->vblank_event_list); base 1610 drivers/gpu/drm/drm_vblank.c if (drm_lease_held(file_priv, crtc->base.id)) { base 1720 drivers/gpu/drm/drm_vblank.c list_for_each_entry_safe(e, t, &dev->vblank_event_list, base.link) { base 1729 drivers/gpu/drm/drm_vblank.c list_del(&e->base.link); base 1935 drivers/gpu/drm/drm_vblank.c e->event.base.type = DRM_EVENT_CRTC_SEQUENCE; base 1936 drivers/gpu/drm/drm_vblank.c e->event.base.length = sizeof(e->event.seq); base 1952 drivers/gpu/drm/drm_vblank.c ret = drm_event_reserve_init_locked(dev, file_priv, &e->base, base 1953 drivers/gpu/drm/drm_vblank.c &e->event.base); base 1966 drivers/gpu/drm/drm_vblank.c list_add_tail(&e->base.link, &dev->vblank_event_list); base 116 drivers/gpu/drm/drm_vram_mm_helper.c mem->bus.base = 0; base 121 drivers/gpu/drm/drm_vram_mm_helper.c mem->bus.base = vmm->vram_base; base 90 drivers/gpu/drm/drm_writeback.c return wb_connector->base.dev->driver->name; base 181 drivers/gpu/drm/drm_writeback.c struct drm_connector *connector = &wb_connector->base; base 219 drivers/gpu/drm/drm_writeback.c "CONNECTOR:%d-%s", connector->base.id, connector->name); base 221 drivers/gpu/drm/drm_writeback.c drm_object_attach_property(&connector->base, base 224 drivers/gpu/drm/drm_writeback.c drm_object_attach_property(&connector->base, base 227 drivers/gpu/drm/drm_writeback.c drm_object_attach_property(&connector->base, base 229 drivers/gpu/drm/drm_writeback.c blob->base.id); base 267 drivers/gpu/drm/drm_writeback.c connector->base.helper_private; base 319 drivers/gpu/drm/drm_writeback.c connector->base.helper_private; base 405 drivers/gpu/drm/drm_writeback.c if (WARN_ON(wb_connector->base.connector_type != base 97 drivers/gpu/drm/etnaviv/etnaviv_drv.h static inline size_t size_vstruct(size_t nelem, size_t elem_size, size_t base) base 99 drivers/gpu/drm/etnaviv/etnaviv_drv.h if (elem_size && nelem > (SIZE_MAX - base) / elem_size) base 101 drivers/gpu/drm/etnaviv/etnaviv_drv.h return base + nelem * elem_size; base 142 drivers/gpu/drm/etnaviv/etnaviv_dump.c file_size += obj->base.size; base 143 drivers/gpu/drm/etnaviv/etnaviv_dump.c n_bomap_pages += obj->base.size >> PAGE_SHIFT; base 212 drivers/gpu/drm/etnaviv/etnaviv_dump.c for (j = 0; j < obj->base.size >> PAGE_SHIFT; j++) base 218 drivers/gpu/drm/etnaviv/etnaviv_dump.c vaddr = etnaviv_gem_vmap(&obj->base); base 220 drivers/gpu/drm/etnaviv/etnaviv_dump.c memcpy(iter.data, vaddr, obj->base.size); base 223 drivers/gpu/drm/etnaviv/etnaviv_dump.c obj->base.size); base 22 drivers/gpu/drm/etnaviv/etnaviv_gem.c struct drm_device *dev = etnaviv_obj->base.dev; base 35 drivers/gpu/drm/etnaviv/etnaviv_gem.c struct drm_device *dev = etnaviv_obj->base.dev; base 60 drivers/gpu/drm/etnaviv/etnaviv_gem.c struct drm_device *dev = etnaviv_obj->base.dev; base 61 drivers/gpu/drm/etnaviv/etnaviv_gem.c struct page **p = drm_gem_get_pages(&etnaviv_obj->base); base 82 drivers/gpu/drm/etnaviv/etnaviv_gem.c drm_gem_put_pages(&etnaviv_obj->base, etnaviv_obj->pages, base 102 drivers/gpu/drm/etnaviv/etnaviv_gem.c struct drm_device *dev = etnaviv_obj->base.dev; base 103 drivers/gpu/drm/etnaviv/etnaviv_gem.c int npages = etnaviv_obj->base.size >> PAGE_SHIFT; base 148 drivers/gpu/drm/etnaviv/etnaviv_gem.c get_file(etnaviv_obj->base.filp); base 150 drivers/gpu/drm/etnaviv/etnaviv_gem.c vma->vm_file = etnaviv_obj->base.filp; base 247 drivers/gpu/drm/etnaviv/etnaviv_gem.c drm_gem_object_put_unlocked(&etnaviv_obj->base); base 361 drivers/gpu/drm/etnaviv/etnaviv_gem.c return vmap(pages, obj->base.size >> PAGE_SHIFT, base 492 drivers/gpu/drm/etnaviv/etnaviv_gem.c struct drm_gem_object *obj = &etnaviv_obj->base; base 596 drivers/gpu/drm/etnaviv/etnaviv_gem.c *obj = &etnaviv_obj->base; base 662 drivers/gpu/drm/etnaviv/etnaviv_gem.c int ret, pinned = 0, npages = etnaviv_obj->base.size >> PAGE_SHIFT; base 703 drivers/gpu/drm/etnaviv/etnaviv_gem.c int npages = etnaviv_obj->base.size >> PAGE_SHIFT; base 740 drivers/gpu/drm/etnaviv/etnaviv_gem.c etnaviv_gem_obj_add(dev, &etnaviv_obj->base); base 742 drivers/gpu/drm/etnaviv/etnaviv_gem.c ret = drm_gem_handle_create(file, &etnaviv_obj->base, handle); base 745 drivers/gpu/drm/etnaviv/etnaviv_gem.c drm_gem_object_put_unlocked(&etnaviv_obj->base); base 35 drivers/gpu/drm/etnaviv/etnaviv_gem.h struct drm_gem_object base; base 61 drivers/gpu/drm/etnaviv/etnaviv_gem.h return container_of(obj, struct etnaviv_gem_object, base); base 74 drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c dma_buf_vunmap(etnaviv_obj->base.import_attach->dmabuf, base 83 drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c drm_prime_gem_destroy(&etnaviv_obj->base, etnaviv_obj->sgt); base 90 drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c return dma_buf_vmap(etnaviv_obj->base.import_attach->dmabuf); base 96 drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c return dma_buf_mmap(etnaviv_obj->base.dma_buf, vma, 0); base 134 drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c etnaviv_gem_obj_add(dev, &etnaviv_obj->base); base 136 drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c return &etnaviv_obj->base; base 139 drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c drm_gem_object_put_unlocked(&etnaviv_obj->base); base 114 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c struct drm_gem_object *obj = &submit->bos[i].obj->base; base 128 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c struct drm_gem_object *obj = &submit->bos[i].obj->base; base 161 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c obj = &submit->bos[contended].obj->base; base 182 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c struct dma_resv *robj = bo->obj->base.resv; base 213 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c struct drm_gem_object *obj = &submit->bos[i].obj->base; base 234 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c mapping = etnaviv_gem_mapping_get(&etnaviv_obj->base, base 313 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c if (r->reloc_offset > bo->obj->base.size - sizeof(*ptr)) { base 346 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c if (r->read_offset >= bo->obj->base.size - sizeof(u32)) { base 366 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c submit->pmrs[i].bo_vma = etnaviv_gem_vmap(&bo->obj->base); base 403 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c drm_gem_object_put_unlocked(&etnaviv_obj->base); base 1006 drivers/gpu/drm/etnaviv/etnaviv_gpu.c struct dma_fence base; base 1011 drivers/gpu/drm/etnaviv/etnaviv_gpu.c return container_of(fence, struct etnaviv_fence, base); base 1030 drivers/gpu/drm/etnaviv/etnaviv_gpu.c return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; base 1037 drivers/gpu/drm/etnaviv/etnaviv_gpu.c kfree_rcu(f, base.rcu); base 1063 drivers/gpu/drm/etnaviv/etnaviv_gpu.c dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, base 1066 drivers/gpu/drm/etnaviv/etnaviv_gpu.c return &f->base; base 22 drivers/gpu/drm/etnaviv/etnaviv_iommu.c struct etnaviv_iommu_context base; base 30 drivers/gpu/drm/etnaviv/etnaviv_iommu.c return container_of(context, struct etnaviv_iommuv1_context, base); base 156 drivers/gpu/drm/etnaviv/etnaviv_iommu.c context = &v1_context->base; base 31 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c struct etnaviv_iommu_context base; base 44 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c return container_of(context, struct etnaviv_iommuv2_context, base); base 76 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c dma_alloc_wc(v2_context->base.global->dev, SZ_4K, base 292 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c context = &v2_context->base; base 135 drivers/gpu/drm/etnaviv/etnaviv_mmu.c etnaviv_obj->sgt, etnaviv_obj->base.size); base 260 drivers/gpu/drm/etnaviv/etnaviv_mmu.c etnaviv_obj->base.size, va); base 263 drivers/gpu/drm/etnaviv/etnaviv_mmu.c etnaviv_obj->base.size); base 268 drivers/gpu/drm/etnaviv/etnaviv_mmu.c ret = etnaviv_iommu_map(context, node->start, sgt, etnaviv_obj->base.size, base 198 drivers/gpu/drm/exynos/exynos5433_drm_decon.c struct drm_display_mode *m = &crtc->base.mode; base 323 drivers/gpu/drm/exynos/exynos5433_drm_decon.c to_exynos_plane_state(plane.base.state); base 324 drivers/gpu/drm/exynos/exynos5433_drm_decon.c unsigned int alpha = state->base.alpha; base 329 drivers/gpu/drm/exynos/exynos5433_drm_decon.c pixel_alpha = state->base.pixel_blend_mode; base 403 drivers/gpu/drm/exynos/exynos5433_drm_decon.c to_exynos_plane_state(plane->base.state); base 405 drivers/gpu/drm/exynos/exynos5433_drm_decon.c struct drm_framebuffer *fb = state->base.fb; base 412 drivers/gpu/drm/exynos/exynos5433_drm_decon.c if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) { base 641 drivers/gpu/drm/exynos/exynos5433_drm_decon.c ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, base 677 drivers/gpu/drm/exynos/exynos5433_drm_decon.c drm_crtc_handle_vblank(&ctx->crtc->base); base 155 drivers/gpu/drm/exynos/exynos7_drm_decon.c struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; base 383 drivers/gpu/drm/exynos/exynos7_drm_decon.c to_exynos_plane_state(plane->base.state); base 385 drivers/gpu/drm/exynos/exynos7_drm_decon.c struct drm_framebuffer *fb = state->base.fb; base 599 drivers/gpu/drm/exynos/exynos7_drm_decon.c drm_crtc_handle_vblank(&ctx->crtc->base); base 638 drivers/gpu/drm/exynos/exynos7_drm_decon.c ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, base 120 drivers/gpu/drm/exynos/exynos_drm_crtc.c struct drm_crtc *crtc = &exynos_crtc->base; base 190 drivers/gpu/drm/exynos/exynos_drm_crtc.c crtc = &exynos_crtc->base; base 228 drivers/gpu/drm/exynos/exynos_drm_crtc.c encoder->possible_crtcs = drm_crtc_mask(&crtc->base); base 29 drivers/gpu/drm/exynos/exynos_drm_drv.h #define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc, base) base 30 drivers/gpu/drm/exynos/exynos_drm_drv.h #define to_exynos_plane(x) container_of(x, struct exynos_drm_plane, base) base 64 drivers/gpu/drm/exynos/exynos_drm_drv.h struct drm_plane_state base; base 74 drivers/gpu/drm/exynos/exynos_drm_drv.h return container_of(state, struct exynos_drm_plane_state, base); base 88 drivers/gpu/drm/exynos/exynos_drm_drv.h struct drm_plane base; base 170 drivers/gpu/drm/exynos/exynos_drm_drv.h struct drm_crtc base; base 76 drivers/gpu/drm/exynos/exynos_drm_fb.c fb->obj[i] = &exynos_gem[i]->base; base 457 drivers/gpu/drm/exynos/exynos_drm_fimd.c struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; base 642 drivers/gpu/drm/exynos/exynos_drm_fimd.c to_exynos_plane_state(plane.base.state); base 644 drivers/gpu/drm/exynos/exynos_drm_fimd.c unsigned int alpha = state->base.alpha; base 649 drivers/gpu/drm/exynos/exynos_drm_fimd.c pixel_alpha = state->base.pixel_blend_mode; base 792 drivers/gpu/drm/exynos/exynos_drm_fimd.c to_exynos_plane_state(plane->base.state); base 794 drivers/gpu/drm/exynos/exynos_drm_fimd.c struct drm_framebuffer *fb = state->base.fb; base 998 drivers/gpu/drm/exynos/exynos_drm_fimd.c drm_crtc_handle_vblank(&ctx->crtc->base); base 1038 drivers/gpu/drm/exynos/exynos_drm_fimd.c drm_crtc_handle_vblank(&ctx->crtc->base); base 1078 drivers/gpu/drm/exynos/exynos_drm_fimd.c ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, base 199 drivers/gpu/drm/exynos/exynos_drm_g2d.c struct drm_pending_event base; base 373 drivers/gpu/drm/exynos/exynos_drm_g2d.c list_add_tail(&node->event->base.link, &file_priv->event_list); base 920 drivers/gpu/drm/exynos/exynos_drm_g2d.c struct drm_exynos_pending_g2d_event, base.link); base 927 drivers/gpu/drm/exynos/exynos_drm_g2d.c drm_send_event(drm_dev, &e->base); base 1174 drivers/gpu/drm/exynos/exynos_drm_g2d.c e->event.base.type = DRM_EXYNOS_G2D_EVENT; base 1175 drivers/gpu/drm/exynos/exynos_drm_g2d.c e->event.base.length = sizeof(e->event); base 1178 drivers/gpu/drm/exynos/exynos_drm_g2d.c ret = drm_event_reserve_init(drm_dev, file, &e->base, &e->event.base); base 1289 drivers/gpu/drm/exynos/exynos_drm_g2d.c drm_event_cancel_free(drm_dev, &node->event->base); base 22 drivers/gpu/drm/exynos/exynos_drm_gem.c struct drm_device *dev = exynos_gem->base.dev; base 108 drivers/gpu/drm/exynos/exynos_drm_gem.c struct drm_device *dev = exynos_gem->base.dev; base 149 drivers/gpu/drm/exynos/exynos_drm_gem.c struct drm_gem_object *obj = &exynos_gem->base; base 183 drivers/gpu/drm/exynos/exynos_drm_gem.c obj = &exynos_gem->base; base 242 drivers/gpu/drm/exynos/exynos_drm_gem.c drm_gem_object_release(&exynos_gem->base); base 261 drivers/gpu/drm/exynos/exynos_drm_gem.c ret = exynos_drm_gem_handle_create(&exynos_gem->base, file_priv, base 294 drivers/gpu/drm/exynos/exynos_drm_gem.c struct drm_device *drm_dev = exynos_gem->base.dev; base 374 drivers/gpu/drm/exynos/exynos_drm_gem.c ret = exynos_drm_gem_handle_create(&exynos_gem->base, file_priv, base 516 drivers/gpu/drm/exynos/exynos_drm_gem.c return &exynos_gem->base; base 521 drivers/gpu/drm/exynos/exynos_drm_gem.c drm_gem_object_release(&exynos_gem->base); base 14 drivers/gpu/drm/exynos/exynos_drm_gem.h #define to_exynos_gem(x) container_of(x, struct exynos_drm_gem, base) base 44 drivers/gpu/drm/exynos/exynos_drm_gem.h struct drm_gem_object base; base 89 drivers/gpu/drm/exynos/exynos_drm_gem.h drm_gem_object_put_unlocked(&exynos_gem->base); base 252 drivers/gpu/drm/exynos/exynos_drm_ipp.c struct drm_pending_event base; base 401 drivers/gpu/drm/exynos/exynos_drm_ipp.c drm_event_cancel_free(ipp->drm_dev, &task->event->base); base 704 drivers/gpu/drm/exynos/exynos_drm_ipp.c e->event.base.type = DRM_EXYNOS_IPP_EVENT; base 705 drivers/gpu/drm/exynos/exynos_drm_ipp.c e->event.base.length = sizeof(e->event); base 708 drivers/gpu/drm/exynos/exynos_drm_ipp.c ret = drm_event_reserve_init(task->ipp->drm_dev, file_priv, &e->base, base 709 drivers/gpu/drm/exynos/exynos_drm_ipp.c &e->event.base); base 729 drivers/gpu/drm/exynos/exynos_drm_ipp.c drm_send_event(task->ipp->drm_dev, &task->event->base); base 57 drivers/gpu/drm/exynos/exynos_drm_plane.c struct drm_plane_state *state = &exynos_state->base; base 137 drivers/gpu/drm/exynos/exynos_drm_plane.c __drm_atomic_helper_plane_reset(plane, &exynos_state->base); base 153 drivers/gpu/drm/exynos/exynos_drm_plane.c __drm_atomic_helper_plane_duplicate_state(plane, ©->base); base 154 drivers/gpu/drm/exynos/exynos_drm_plane.c return ©->base; base 179 drivers/gpu/drm/exynos/exynos_drm_plane.c struct drm_framebuffer *fb = state->base.fb; base 203 drivers/gpu/drm/exynos/exynos_drm_plane.c struct drm_crtc *crtc = state->base.crtc; base 302 drivers/gpu/drm/exynos/exynos_drm_plane.c struct drm_plane *plane = &exynos_plane->base; base 304 drivers/gpu/drm/exynos/exynos_drm_plane.c err = drm_universal_plane_init(dev, &exynos_plane->base, base 315 drivers/gpu/drm/exynos/exynos_drm_plane.c drm_plane_helper_add(&exynos_plane->base, &plane_helper_funcs); base 320 drivers/gpu/drm/exynos/exynos_drm_plane.c exynos_plane_attach_zpos_property(&exynos_plane->base, config->zpos, base 112 drivers/gpu/drm/exynos/exynos_drm_vidi.c struct drm_plane_state *state = plane->base.state; base 133 drivers/gpu/drm/exynos/exynos_drm_vidi.c drm_crtc_vblank_on(&crtc->base); base 140 drivers/gpu/drm/exynos/exynos_drm_vidi.c drm_crtc_vblank_off(&crtc->base); base 162 drivers/gpu/drm/exynos/exynos_drm_vidi.c if (drm_crtc_handle_vblank(&ctx->crtc->base)) base 402 drivers/gpu/drm/exynos/exynos_drm_vidi.c ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, base 353 drivers/gpu/drm/exynos/exynos_mixer.c u32 base, shadow; base 364 drivers/gpu/drm/exynos/exynos_mixer.c base = mixer_reg_read(ctx, MXR_CFG); base 366 drivers/gpu/drm/exynos/exynos_mixer.c if (base != shadow) base 369 drivers/gpu/drm/exynos/exynos_mixer.c base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0)); base 371 drivers/gpu/drm/exynos/exynos_mixer.c if (base != shadow) base 374 drivers/gpu/drm/exynos/exynos_mixer.c base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(1)); base 376 drivers/gpu/drm/exynos/exynos_mixer.c if (base != shadow) base 504 drivers/gpu/drm/exynos/exynos_mixer.c struct drm_display_mode *mode = &ctx->crtc->base.state->adjusted_mode; base 515 drivers/gpu/drm/exynos/exynos_mixer.c to_exynos_plane_state(plane->base.state); base 516 drivers/gpu/drm/exynos/exynos_mixer.c struct drm_framebuffer *fb = state->base.fb; base 517 drivers/gpu/drm/exynos/exynos_mixer.c unsigned int priority = state->base.normalized_zpos + 1; base 590 drivers/gpu/drm/exynos/exynos_mixer.c mixer_cfg_vp_blend(ctx, state->base.alpha); base 602 drivers/gpu/drm/exynos/exynos_mixer.c to_exynos_plane_state(plane->base.state); base 603 drivers/gpu/drm/exynos/exynos_mixer.c struct drm_framebuffer *fb = state->base.fb; base 604 drivers/gpu/drm/exynos/exynos_mixer.c unsigned int priority = state->base.normalized_zpos + 1; base 615 drivers/gpu/drm/exynos/exynos_mixer.c pixel_alpha = state->base.pixel_blend_mode; base 678 drivers/gpu/drm/exynos/exynos_mixer.c mixer_cfg_gfx_blend(ctx, win, pixel_alpha, state->base.alpha); base 762 drivers/gpu/drm/exynos/exynos_mixer.c drm_crtc_handle_vblank(&ctx->crtc->base); base 1194 drivers/gpu/drm/exynos/exynos_mixer.c ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, base 84 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c struct drm_connector *con = &fsl_dev->connector.base; base 245 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c void __iomem *base; base 264 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c base = devm_ioremap_resource(dev, res); base 265 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c if (IS_ERR(base)) { base 266 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c ret = PTR_ERR(base); base 276 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c fsl_dev->regmap = devm_regmap_init_mmio(dev, base, base 306 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c pix_clk_in_name, 0, base + DCU_DIV_RATIO, base 12 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h struct drm_connector base; base 20 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h return con ? container_of(con, struct fsl_dcu_drm_connector, base) base 91 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c struct drm_connector *connector = &fsl_dev->connector.base; base 231 drivers/gpu/drm/gma500/accel_2d.c struct drm_device *dev = psbfb->base.dev; base 314 drivers/gpu/drm/gma500/accel_2d.c struct drm_device *dev = psbfb->base.dev; base 481 drivers/gpu/drm/gma500/cdv_device.c drm_object_attach_property(&connector->base, prop, 0); base 511 drivers/gpu/drm/gma500/cdv_device.c drm_object_attach_property(&connector->base, prop, 0); base 533 drivers/gpu/drm/gma500/cdv_device.c .base = DSPABASE, base 558 drivers/gpu/drm/gma500/cdv_device.c .base = DSPBBASE, base 268 drivers/gpu/drm/gma500/cdv_intel_crt.c connector = &gma_connector->base; base 273 drivers/gpu/drm/gma500/cdv_intel_crt.c encoder = &gma_encoder->base; base 310 drivers/gpu/drm/gma500/cdv_intel_crt.c drm_encoder_cleanup(&gma_encoder->base); base 311 drivers/gpu/drm/gma500/cdv_intel_crt.c drm_connector_cleanup(&gma_connector->base); base 381 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = intel_encoder->base.dev; base 401 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = intel_encoder->base.dev; base 416 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = intel_encoder->base.dev; base 443 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = intel_encoder->base.dev; base 475 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = intel_encoder->base.dev; base 495 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = intel_encoder->base.dev; base 575 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = encoder->base.dev; base 865 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->adapter.dev.parent = connector->base.kdev; base 1390 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = encoder->base.dev; base 1435 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = encoder->base.dev; base 1501 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = encoder->base.dev; base 1595 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = encoder->base.dev; base 1681 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_device *dev = encoder->base.dev; base 1851 drivers/gpu/drm/gma500/cdv_intel_dp.c ret = drm_object_property_set_value(&connector->base, property, val); base 1887 drivers/gpu/drm/gma500/cdv_intel_dp.c if (encoder->base.crtc) { base 1888 drivers/gpu/drm/gma500/cdv_intel_dp.c struct drm_crtc *crtc = encoder->base.crtc; base 2018 drivers/gpu/drm/gma500/cdv_intel_dp.c connector = &gma_connector->base; base 2019 drivers/gpu/drm/gma500/cdv_intel_dp.c encoder = &gma_encoder->base; base 178 drivers/gpu/drm/gma500/cdv_intel_hdmi.c if (drm_object_property_get_value(&connector->base, base 185 drivers/gpu/drm/gma500/cdv_intel_hdmi.c if (drm_object_property_set_value(&connector->base, base 304 drivers/gpu/drm/gma500/cdv_intel_hdmi.c connector = &gma_connector->base; base 309 drivers/gpu/drm/gma500/cdv_intel_hdmi.c encoder = &gma_encoder->base; base 330 drivers/gpu/drm/gma500/cdv_intel_hdmi.c drm_object_attach_property(&connector->base, base 442 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (drm_object_property_get_value(&connector->base, base 450 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (drm_object_property_set_value(&connector->base, base 465 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (drm_object_property_set_value(&connector->base, base 609 drivers/gpu/drm/gma500/cdv_intel_lvds.c connector = &gma_connector->base; base 612 drivers/gpu/drm/gma500/cdv_intel_lvds.c encoder = &gma_encoder->base; base 635 drivers/gpu/drm/gma500/cdv_intel_lvds.c drm_object_attach_property(&connector->base, base 638 drivers/gpu/drm/gma500/cdv_intel_lvds.c drm_object_attach_property(&connector->base, base 82 drivers/gpu/drm/gma500/framebuffer.c struct drm_device *dev = psbfb->base.dev; base 83 drivers/gpu/drm/gma500/framebuffer.c struct gtt_range *gtt = to_gtt_range(psbfb->base.obj[0]); base 103 drivers/gpu/drm/gma500/framebuffer.c struct drm_device *dev = psbfb->base.dev; base 105 drivers/gpu/drm/gma500/framebuffer.c struct gtt_range *gtt = to_gtt_range(psbfb->base.obj[0]); base 230 drivers/gpu/drm/gma500/framebuffer.c drm_helper_mode_fill_fb_struct(dev, &fb->base, mode_cmd); base 231 drivers/gpu/drm/gma500/framebuffer.c fb->base.obj[0] = >->gem; base 232 drivers/gpu/drm/gma500/framebuffer.c ret = drm_framebuffer_init(dev, &fb->base, &psb_fb_funcs); base 269 drivers/gpu/drm/gma500/framebuffer.c return &fb->base; base 387 drivers/gpu/drm/gma500/framebuffer.c fb = &psbfb->base; base 410 drivers/gpu/drm/gma500/framebuffer.c info->apertures->ranges[0].base = dev->mode_config.fb_base; base 422 drivers/gpu/drm/gma500/framebuffer.c psbfb->base.width, psbfb->base.height); base 498 drivers/gpu/drm/gma500/framebuffer.c drm_framebuffer_unregister_private(&psbfb->base); base 499 drivers/gpu/drm/gma500/framebuffer.c drm_framebuffer_cleanup(&psbfb->base); base 501 drivers/gpu/drm/gma500/framebuffer.c if (psbfb->base.obj[0]) base 502 drivers/gpu/drm/gma500/framebuffer.c drm_gem_object_put_unlocked(psbfb->base.obj[0]); base 580 drivers/gpu/drm/gma500/framebuffer.c struct drm_encoder *encoder = &gma_encoder->base; base 17 drivers/gpu/drm/gma500/framebuffer.h struct drm_framebuffer base; base 27 drivers/gpu/drm/gma500/framebuffer.h #define to_psb_fb(x) container_of(x, struct psb_framebuffer, base) base 116 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->base, offset + start); base 117 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->base); base 119 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->base, offset); base 120 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->base); base 237 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->base, REG_READ(map->base)); base 284 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->base, REG_READ(map->base)); base 285 drivers/gpu/drm/gma500/gma_display.c REG_READ(map->base); base 329 drivers/gpu/drm/gma500/gma_display.c uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; base 343 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(base, 0); base 420 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(base, addr); base 557 drivers/gpu/drm/gma500/gma_display.c crtc_state->saveDSPBASE = REG_READ(map->base); base 611 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->base, crtc_state->saveDSPBASE); base 617 drivers/gpu/drm/gma500/gma_display.c REG_WRITE(map->base, crtc_state->saveDSPBASE); base 655 drivers/gpu/drm/gma500/gma_display.c return &gma_encoder->base; base 662 drivers/gpu/drm/gma500/gma_display.c drm_connector_attach_encoder(&connector->base, base 663 drivers/gpu/drm/gma500/gma_display.c &encoder->base); base 21 drivers/gpu/drm/gma500/intel_bios.c u8 *base = (u8 *)bdb; base 32 drivers/gpu/drm/gma500/intel_bios.c current_id = *(base + index); base 34 drivers/gpu/drm/gma500/intel_bios.c current_size = *((u16 *)(base + index)); base 37 drivers/gpu/drm/gma500/intel_bios.c return base + index; base 994 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c connector = &dsi_connector->base.base; base 995 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c encoder = &dpi_output->base.base.base; base 1015 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c dsi_connector->base.encoder = &dpi_output->base.base; base 1017 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c return &dpi_output->base; base 45 drivers/gpu/drm/gma500/mdfld_dsi_dpi.h struct mdfld_dsi_encoder base; base 55 drivers/gpu/drm/gma500/mdfld_dsi_dpi.h container_of(dsi_encoder, struct mdfld_dsi_dpi_output, base) base 272 drivers/gpu/drm/gma500/mdfld_dsi_output.c if (drm_object_property_get_value(&connector->base, property, &val)) base 278 drivers/gpu/drm/gma500/mdfld_dsi_output.c if (drm_object_property_set_value(&connector->base, base 303 drivers/gpu/drm/gma500/mdfld_dsi_output.c if (drm_object_property_set_value(&connector->base, property, base 389 drivers/gpu/drm/gma500/mdfld_dsi_output.c return &dsi_config->encoder->base.base; base 550 drivers/gpu/drm/gma500/mdfld_dsi_output.c connector = &dsi_connector->base.base; base 551 drivers/gpu/drm/gma500/mdfld_dsi_output.c dsi_connector->base.save = mdfld_dsi_connector_save; base 552 drivers/gpu/drm/gma500/mdfld_dsi_output.c dsi_connector->base.restore = mdfld_dsi_connector_restore; base 565 drivers/gpu/drm/gma500/mdfld_dsi_output.c drm_object_attach_property(&connector->base, base 568 drivers/gpu/drm/gma500/mdfld_dsi_output.c drm_object_attach_property(&connector->base, base 586 drivers/gpu/drm/gma500/mdfld_dsi_output.c encoder->base.type = (pipe == 0) ? INTEL_OUTPUT_MIPI : base 230 drivers/gpu/drm/gma500/mdfld_dsi_output.h struct gma_connector base; base 241 drivers/gpu/drm/gma500/mdfld_dsi_output.h struct gma_encoder base; base 276 drivers/gpu/drm/gma500/mdfld_dsi_output.h return container_of(gma_connector, struct mdfld_dsi_connector, base); base 286 drivers/gpu/drm/gma500/mdfld_dsi_output.h return container_of(gma_encoder, struct mdfld_dsi_encoder, base); base 248 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->base, REG_READ(map->base)); base 249 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->base); base 360 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->base, REG_READ(map->base)); base 385 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->base, REG_READ(map->base)); base 401 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->base, REG_READ(map->base)); base 436 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_WRITE(map->base, REG_READ(map->base)); base 437 drivers/gpu/drm/gma500/mdfld_intel_display.c REG_READ(map->base); base 791 drivers/gpu/drm/gma500/mdfld_intel_display.c drm_object_property_get_value(&connector->base, base 274 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE_WITH_AUX(map->base, base 275 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ_WITH_AUX(map->base, i), i); base 299 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE_WITH_AUX(map->base, base 300 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ(map->base), i); base 301 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ_WITH_AUX(map->base, i); base 427 drivers/gpu/drm/gma500/oaktrail_crtc.c drm_object_property_get_value(&connector->base, base 640 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_WRITE(map->base, offset); base 641 drivers/gpu/drm/gma500/oaktrail_crtc.c REG_READ(map->base); base 472 drivers/gpu/drm/gma500/oaktrail_device.c .base = MRST_DSPABASE, base 496 drivers/gpu/drm/gma500/oaktrail_device.c .base = DSPBBASE, base 236 drivers/gpu/drm/gma500/oaktrail_hdmi.c void __iomem *base; base 240 drivers/gpu/drm/gma500/oaktrail_hdmi.c base = ioremap((resource_size_t)scu_ipc_mmio, scu_len); base 241 drivers/gpu/drm/gma500/oaktrail_hdmi.c if (base == NULL) { base 247 drivers/gpu/drm/gma500/oaktrail_hdmi.c writel(0xff11d118, base + 0x0c); base 248 drivers/gpu/drm/gma500/oaktrail_hdmi.c writel(0x7fffffdf, base + 0x80); base 249 drivers/gpu/drm/gma500/oaktrail_hdmi.c writel(0x42005, base + 0x0); base 250 drivers/gpu/drm/gma500/oaktrail_hdmi.c scu_busy_loop(base); base 253 drivers/gpu/drm/gma500/oaktrail_hdmi.c writel(0xff11d118, base + 0x0c); base 254 drivers/gpu/drm/gma500/oaktrail_hdmi.c writel(0x7fffffff, base + 0x80); base 255 drivers/gpu/drm/gma500/oaktrail_hdmi.c writel(0x42005, base + 0x0); base 256 drivers/gpu/drm/gma500/oaktrail_hdmi.c scu_busy_loop(base); base 258 drivers/gpu/drm/gma500/oaktrail_hdmi.c iounmap(base); base 650 drivers/gpu/drm/gma500/oaktrail_hdmi.c connector = &gma_connector->base; base 651 drivers/gpu/drm/gma500/oaktrail_hdmi.c encoder = &gma_encoder->base; base 253 drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c void __iomem *base; base 258 drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c base = ioremap((resource_size_t)gpio_base, gpio_len); base 259 drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c if (base == NULL) { base 264 drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c temp = readl(base + 0x44); base 266 drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c writel((temp | 0x00000a00), (base + 0x44)); base 267 drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c temp = readl(base + 0x44); base 270 drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c iounmap(base); base 124 drivers/gpu/drm/gma500/oaktrail_lvds.c &connector->base, base 306 drivers/gpu/drm/gma500/oaktrail_lvds.c connector = &gma_connector->base; base 307 drivers/gpu/drm/gma500/oaktrail_lvds.c encoder = &gma_encoder->base; base 326 drivers/gpu/drm/gma500/oaktrail_lvds.c drm_object_attach_property(&connector->base, base 329 drivers/gpu/drm/gma500/oaktrail_lvds.c drm_object_attach_property(&connector->base, base 310 drivers/gpu/drm/gma500/opregion.c void __iomem *base; base 322 drivers/gpu/drm/gma500/opregion.c base = acpi_os_ioremap(opregion_phy, 8*1024); base 323 drivers/gpu/drm/gma500/opregion.c if (!base) base 326 drivers/gpu/drm/gma500/opregion.c if (memcmp(base, OPREGION_SIGNATURE, 16)) { base 332 drivers/gpu/drm/gma500/opregion.c opregion->header = base; base 333 drivers/gpu/drm/gma500/opregion.c opregion->vbt = base + OPREGION_VBT_OFFSET; base 335 drivers/gpu/drm/gma500/opregion.c opregion->lid_state = base + ACPI_CLID; base 340 drivers/gpu/drm/gma500/opregion.c opregion->acpi = base + OPREGION_ACPI_OFFSET; base 345 drivers/gpu/drm/gma500/opregion.c opregion->asle = base + OPREGION_ASLE_OFFSET; base 351 drivers/gpu/drm/gma500/opregion.c iounmap(base); base 192 drivers/gpu/drm/gma500/psb_device.c list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) base 194 drivers/gpu/drm/gma500/psb_device.c connector->save(&connector->base); base 231 drivers/gpu/drm/gma500/psb_device.c list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) base 233 drivers/gpu/drm/gma500/psb_device.c connector->restore(&connector->base); base 267 drivers/gpu/drm/gma500/psb_device.c .base = DSPABASE, base 291 drivers/gpu/drm/gma500/psb_device.c .base = DSPBBASE, base 283 drivers/gpu/drm/gma500/psb_drv.h u32 base; base 315 drivers/gpu/drm/gma500/psb_drv.h u32 base; base 452 drivers/gpu/drm/gma500/psb_intel_display.c u32 base[3] = { CURABASE, CURBBASE, CURCBASE }; base 474 drivers/gpu/drm/gma500/psb_intel_display.c REG_WRITE(base[gma_crtc->pipe], 0); base 501 drivers/gpu/drm/gma500/psb_intel_display.c drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs); base 506 drivers/gpu/drm/gma500/psb_intel_display.c drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256); base 516 drivers/gpu/drm/gma500/psb_intel_display.c drm_crtc_helper_add(&gma_crtc->base, base 520 drivers/gpu/drm/gma500/psb_intel_display.c gma_crtc->mode_set.crtc = &gma_crtc->base; base 523 drivers/gpu/drm/gma500/psb_intel_display.c dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base; base 524 drivers/gpu/drm/gma500/psb_intel_display.c dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base; base 110 drivers/gpu/drm/gma500/psb_intel_drv.h struct drm_encoder base; base 130 drivers/gpu/drm/gma500/psb_intel_drv.h struct drm_connector base; base 158 drivers/gpu/drm/gma500/psb_intel_drv.h struct drm_crtc base; base 188 drivers/gpu/drm/gma500/psb_intel_drv.h container_of(x, struct gma_crtc, base) base 190 drivers/gpu/drm/gma500/psb_intel_drv.h container_of(x, struct gma_connector, base) base 192 drivers/gpu/drm/gma500/psb_intel_drv.h container_of(x, struct gma_encoder, base) base 194 drivers/gpu/drm/gma500/psb_intel_drv.h container_of(x, struct psb_intel_framebuffer, base) base 561 drivers/gpu/drm/gma500/psb_intel_lvds.c if (drm_object_property_get_value(&connector->base, base 569 drivers/gpu/drm/gma500/psb_intel_lvds.c if (drm_object_property_set_value(&connector->base, base 584 drivers/gpu/drm/gma500/psb_intel_lvds.c if (drm_object_property_set_value(&connector->base, base 677 drivers/gpu/drm/gma500/psb_intel_lvds.c connector = &gma_connector->base; base 681 drivers/gpu/drm/gma500/psb_intel_lvds.c encoder = &gma_encoder->base; base 701 drivers/gpu/drm/gma500/psb_intel_lvds.c drm_object_attach_property(&connector->base, base 704 drivers/gpu/drm/gma500/psb_intel_lvds.c drm_object_attach_property(&connector->base, base 68 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct gma_encoder base; base 143 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct gma_connector base; base 198 drivers/gpu/drm/gma500/psb_intel_sdvo.c return container_of(encoder, struct psb_intel_sdvo, base.base); base 204 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct psb_intel_sdvo, base); base 209 drivers/gpu/drm/gma500/psb_intel_sdvo.c return container_of(to_gma_connector(connector), struct psb_intel_sdvo_connector, base); base 229 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_device *dev = psb_intel_sdvo->base.base.dev; base 1441 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->base.needs_tv_clock = false; base 1445 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->base.needs_tv_clock = true; base 1676 drivers/gpu/drm/gma500/psb_intel_sdvo.c ret = drm_object_property_set_value(&connector->base, property, val); base 1731 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_object_property_set_value(&connector->base, base 1743 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_object_property_set_value(&connector->base, base 1755 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_object_property_set_value(&connector->base, base 1767 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_object_property_set_value(&connector->base, base 1802 drivers/gpu/drm/gma500/psb_intel_sdvo.c if (psb_intel_sdvo->base.base.crtc) { base 1803 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_crtc *crtc = psb_intel_sdvo->base.base.crtc; base 1816 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(&gma_encoder->base); base 1824 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_encoder *encoder = &gma_attached_encoder(connector)->base; base 2017 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_connector_init(encoder->base.base.dev, base 2018 drivers/gpu/drm/gma500/psb_intel_sdvo.c &connector->base.base, base 2020 drivers/gpu/drm/gma500/psb_intel_sdvo.c connector->base.base.connector_type); base 2022 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_connector_helper_add(&connector->base.base, base 2025 drivers/gpu/drm/gma500/psb_intel_sdvo.c connector->base.base.interlace_allowed = 0; base 2026 drivers/gpu/drm/gma500/psb_intel_sdvo.c connector->base.base.doublescan_allowed = 0; base 2027 drivers/gpu/drm/gma500/psb_intel_sdvo.c connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; base 2029 drivers/gpu/drm/gma500/psb_intel_sdvo.c connector->base.save = psb_intel_sdvo_save; base 2030 drivers/gpu/drm/gma500/psb_intel_sdvo.c connector->base.restore = psb_intel_sdvo_restore; base 2032 drivers/gpu/drm/gma500/psb_intel_sdvo.c gma_connector_attach_encoder(&connector->base, &encoder->base); base 2033 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_connector_register(&connector->base.base); base 2050 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_encoder *encoder = &psb_intel_sdvo->base.base; base 2067 drivers/gpu/drm/gma500/psb_intel_sdvo.c intel_connector = &psb_intel_sdvo_connector->base; base 2068 drivers/gpu/drm/gma500/psb_intel_sdvo.c connector = &intel_connector->base; base 2077 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | base 2090 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_encoder *encoder = &psb_intel_sdvo->base.base; base 2099 drivers/gpu/drm/gma500/psb_intel_sdvo.c intel_connector = &psb_intel_sdvo_connector->base; base 2100 drivers/gpu/drm/gma500/psb_intel_sdvo.c connector = &intel_connector->base; base 2108 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->base.needs_tv_clock = true; base 2109 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; base 2129 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_encoder *encoder = &psb_intel_sdvo->base.base; base 2138 drivers/gpu/drm/gma500/psb_intel_sdvo.c intel_connector = &psb_intel_sdvo_connector->base; base 2139 drivers/gpu/drm/gma500/psb_intel_sdvo.c connector = &intel_connector->base; base 2152 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | base 2163 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_encoder *encoder = &psb_intel_sdvo->base.base; base 2172 drivers/gpu/drm/gma500/psb_intel_sdvo.c intel_connector = &psb_intel_sdvo_connector->base; base 2173 drivers/gpu/drm/gma500/psb_intel_sdvo.c connector = &intel_connector->base; base 2185 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | base 2203 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->base.needs_tv_clock = false; base 2251 drivers/gpu/drm/gma500/psb_intel_sdvo.c psb_intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1); base 2260 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_device *dev = psb_intel_sdvo->base.base.dev; base 2296 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_object_attach_property(&psb_intel_sdvo_connector->base.base.base, base 2312 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_object_attach_property(&connector->base, \ base 2325 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_device *dev = psb_intel_sdvo->base.base.dev; base 2326 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_connector *connector = &psb_intel_sdvo_connector->base.base; base 2349 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_object_attach_property(&connector->base, base 2358 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_object_attach_property(&connector->base, base 2385 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_object_attach_property(&connector->base, base 2394 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_object_attach_property(&connector->base, base 2426 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_object_attach_property(&connector->base, base 2440 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_device *dev = psb_intel_sdvo->base.base.dev; base 2441 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct drm_connector *connector = &psb_intel_sdvo_connector->base.base; base 2534 drivers/gpu/drm/gma500/psb_intel_sdvo.c gma_encoder = &psb_intel_sdvo->base; base 2536 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_encoder_init(dev, &gma_encoder->base, &psb_intel_sdvo_enc_funcs, base 2555 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_encoder_helper_add(&gma_encoder->base, &psb_intel_sdvo_helper_funcs); base 2598 drivers/gpu/drm/gma500/psb_intel_sdvo.c drm_encoder_cleanup(&gma_encoder->base); base 66 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c void *base; base 96 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c base = drm_gem_vram_kmap(gbo, true, NULL); base 97 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c if (IS_ERR(base)) { base 98 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c ret = PTR_ERR(base); base 125 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c info->screen_base = base; base 128 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c info->fix.smem_start = gbo->bo.mem.bus.offset + gbo->bo.mem.bus.base; base 69 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c *obj = &gbo->bo.base; base 77 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c void __iomem *base; base 310 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val) base 317 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(reg_write, base + PHY_TST_CTRL1); base 318 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(0x02, base + PHY_TST_CTRL0); base 319 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(0x00, base + PHY_TST_CTRL0); base 324 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + PHY_TST_CTRL1); base 325 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(0x02, base + PHY_TST_CTRL0); base 326 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(0x00, base + PHY_TST_CTRL0); base 329 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c static void dsi_set_phy_timer(void __iomem *base, base 339 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + PHY_IF_CFG); base 344 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = readl(base + CLKMGR_CFG) | phy->clk_division; base 345 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + CLKMGR_CFG); base 350 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time); base 351 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time); base 352 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10), base 354 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10), base 356 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8), base 358 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8), base 362 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c static void dsi_set_mipi_phy(void __iomem *base, base 371 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_set_phy_timer(base, phy, lanes); base 376 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(0, base + PHY_RSTZ); base 377 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(0, base + PHY_TST_CTRL0); base 378 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(1, base + PHY_TST_CTRL0); base 379 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(0, base + PHY_TST_CTRL0); base 385 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, CLK_TLPX, phy->clk_t_lpx); base 386 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, CLK_THS_PREPARE, phy->clk_t_hs_prepare); base 387 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, CLK_THS_ZERO, phy->clk_t_hs_zero); base 388 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, CLK_THS_TRAIL, phy->clk_t_hs_trial); base 389 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, CLK_TWAKEUP, phy->clk_t_wakeup); base 396 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, DATA_TLPX(i), phy->data_t_lpx); base 397 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, DATA_THS_PREPARE(i), base 399 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, DATA_THS_ZERO(i), phy->data_t_hs_zero); base 400 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, DATA_THS_TRAIL(i), phy->data_t_hs_trial); base 401 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, DATA_TTA_GO(i), phy->data_t_ta_go); base 402 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, DATA_TTA_GET(i), phy->data_t_ta_get); base 403 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, DATA_TWAKEUP(i), phy->data_t_wakeup); base 410 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, PHY_CFG_I, phy->hstx_ckg_sel); base 413 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, PHY_CFG_PLL_I, val); base 414 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, PHY_CFG_PLL_II, phy->pll_fbd_p); base 415 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, PHY_CFG_PLL_III, phy->pll_fbd_s); base 417 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, PHY_CFG_PLL_IV, val); base 420 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_phy_tst_set(base, PHY_CFG_PLL_V, val); base 422 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(PHY_ENABLECLK, base + PHY_RSTZ); base 424 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(PHY_ENABLECLK | PHY_UNSHUTDOWNZ, base + PHY_RSTZ); base 426 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ, base + PHY_RSTZ); base 434 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c val = readl(base + PHY_STATUS); base 446 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c static void dsi_set_mode_timing(void __iomem *base, base 461 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + DPI_COLOR_CODING); base 465 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + DPI_CFG_POL); base 494 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(hsa_time, base + VID_HSA_TIME); base 495 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(hbp_time, base + VID_HBP_TIME); base 496 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(hline_time, base + VID_HLINE_TIME); base 498 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(vsw, base + VID_VSA_LINES); base 499 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(vbp, base + VID_VBP_LINES); base 500 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(vfp, base + VID_VFP_LINES); base 501 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(mode->vdisplay, base + VID_VACTIVE_LINES); base 502 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(mode->hdisplay, base + VID_PKT_SIZE); base 512 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c static void dsi_set_video_mode(void __iomem *base, unsigned long flags) base 530 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(val, base + VID_MODE_CFG); base 532 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(PHY_TXREQUESTCLKHS, base + LPCLK_CTRL); base 533 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(DSI_VIDEO_MODE, base + MODE_CFG); base 542 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c void __iomem *base = ctx->base; base 552 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(RESET, base + PWR_UP); base 555 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_set_mipi_phy(base, phy, dsi->lanes); base 558 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_set_mode_timing(base, phy->lane_byte_clk_kHz, mode, dsi->format); base 561 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_set_video_mode(base, dsi->mode_flags); base 564 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(POWERUP, base + PWR_UP); base 574 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c void __iomem *base = ctx->base; base 579 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(0, base + PWR_UP); base 580 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(0, base + LPCLK_CTRL); base 581 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c writel(0, base + PHY_RSTZ); base 842 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c ctx->base = devm_ioremap_resource(&pdev->dev, res); base 843 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c if (IS_ERR(ctx->base)) { base 845 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c return PTR_ERR(ctx->base); base 43 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c void __iomem *base; base 94 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) base 101 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst, base 105 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num) base 112 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c tmp = readl(base + ADE_RELOAD_DIS(reg_num)); base 118 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c void __iomem *base = ctx->base; base 121 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST, base 124 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(0, base + ADE_OVLY1_TRANS_CFG); base 125 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(0, base + ADE_OVLY_CTL); base 126 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(0, base + ADE_OVLYX_CTL(OUT_OVLY)); base 128 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(MASK(32), base + ADE_SOFT_RST_SEL(0)); base 129 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(MASK(32), base + ADE_SOFT_RST_SEL(1)); base 130 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(MASK(32), base + ADE_RELOAD_DIS(0)); base 131 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(MASK(32), base + ADE_RELOAD_DIS(1)); base 136 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST, base 174 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c void __iomem *base = ctx->base; base 193 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0); base 195 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(hsw - 1, base + LDI_HRZ_CTRL1); base 196 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0); base 198 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(vsw - 1, base + LDI_VRT_CTRL1); base 201 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c base + LDI_DSP_SIZE); base 202 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(plr_flags, base + LDI_PLR_CTRL); base 206 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY)); base 209 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6)); base 211 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6)); base 212 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0); base 248 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c void __iomem *base = ctx->base; base 250 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(ADE_DISABLE, base + LDI_CTRL); base 252 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT); base 279 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c void __iomem *base = ctx->base; base 284 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, base 294 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c void __iomem *base = ctx->base; base 301 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, base 309 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c void __iomem *base = ctx->base; base 312 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c status = readl(base + LDI_MSK_INT); base 317 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST, base 327 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c void __iomem *base = ctx->base; base 331 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY)); base 332 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0); base 335 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG); base 338 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(ADE_ENABLE, base + ADE_EN); base 340 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(NORMAL_MODE, base + LDI_WORK_MODE); base 342 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c base + LDI_CTRL); base 344 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT); base 348 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_rdma_dump_regs(void __iomem *base, u32 ch) base 360 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = ade_read_reload_bit(base, RDMA_OFST + ch); base 362 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_ctrl); base 364 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_addr); base 366 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_size); base 368 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_stride); base 370 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_space); base 372 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + reg_en); base 376 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_clip_dump_regs(void __iomem *base, u32 ch) base 380 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = ade_read_reload_bit(base, CLIP_OFST + ch); base 382 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_CLIP_DISABLE(ch)); base 384 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_CLIP_SIZE0(ch)); base 386 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_CLIP_SIZE1(ch)); base 390 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch) base 395 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_OVLY_CH_XY0(ovly_ch)); base 397 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_OVLY_CH_XY1(ovly_ch)); base 399 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_OVLY_CH_CTL(ovly_ch)); base 403 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp) base 407 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = ade_read_reload_bit(base, OVLY_OFST + comp); base 409 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp)); base 411 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c val = readl(base + ADE_OVLY_CTL); base 415 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_dump_regs(void __iomem *base) base 422 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_rdma_dump_regs(base, i); base 425 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_clip_dump_regs(base, i); base 428 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_compositor_routing_dump_regs(base, i); base 432 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_dump_overlay_compositor_regs(base, OUT_OVLY); base 435 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_dump_regs(void __iomem *base) { } base 456 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_dump_regs(ctx->base); base 507 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c void __iomem *base = ctx->base; base 511 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_dump_regs(base); base 513 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(ADE_ENABLE, base + ADE_EN); base 548 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb, base 574 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel((fmt << 16) & 0x1f0000, base + reg_ctrl); base 575 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(addr, base + reg_addr); base 576 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel((in_h << 16) | stride, base + reg_size); base 577 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(stride, base + reg_stride); base 578 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(in_h * stride, base + reg_space); base 579 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(ADE_ENABLE, base + reg_en); base 580 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_reload_bit(base, RDMA_OFST + ch, 0); base 583 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_rdma_disable(void __iomem *base, u32 ch) base 589 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(0, base + reg_en); base 590 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_reload_bit(base, RDMA_OFST + ch, 1); base 593 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x, base 616 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(disable_val, base + ADE_CLIP_DISABLE(ch)); base 617 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch)); base 618 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch)); base 619 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_reload_bit(base, CLIP_OFST + ch, 0); base 622 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_clip_disable(void __iomem *base, u32 ch) base 624 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(1, base + ADE_CLIP_DISABLE(ch)); base 625 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_reload_bit(base, CLIP_OFST + ch, 1); base 663 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_compositor_routing_set(void __iomem *base, u8 ch, base 681 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch)); base 682 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch)); base 688 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(val, base + ADE_OVLY_CH_CTL(ovly_ch)); base 690 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch), base 694 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c static void ade_compositor_routing_disable(void __iomem *base, u32 ch) base 699 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST, base 702 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch), base 716 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c void __iomem *base = ctx->base; base 729 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_rdma_set(base, fb, ch, src_y, in_h, fmt); base 732 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_clip_set(base, ch, fb->width, src_x, in_w, in_h); base 739 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_compositor_routing_set(base, ch, crtc_x, crtc_y, in_w, in_h, fmt); base 745 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c void __iomem *base = ctx->base; base 751 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_rdma_disable(base, ch); base 754 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_clip_disable(base, ch); base 757 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_compositor_routing_disable(base, ch); base 856 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ctx->base = devm_ioremap_resource(dev, res); base 857 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c if (IS_ERR(ctx->base)) { base 120 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c ctx = driver_data->alloc_hw_ctx(pdev, &kirin_priv->crtc.base); base 137 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c ret = kirin_drm_plane_init(dev, &kirin_priv->planes[ch].base, base 146 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c prim_plane = &kirin_priv->planes[driver_data->prim_plane].base; base 147 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c ret = kirin_drm_crtc_init(dev, &kirin_priv->crtc.base, base 11 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h container_of(crtc, struct kirin_crtc, base) base 14 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h container_of(plane, struct kirin_plane, base) base 23 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h struct drm_crtc base; base 29 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h struct drm_plane base; base 217 drivers/gpu/drm/i2c/ch7006_drv.c drm_object_property_set_value(&connector->base, base 259 drivers/gpu/drm/i2c/ch7006_drv.c drm_object_attach_property(&connector->base, conf->tv_select_subconnector_property, base 261 drivers/gpu/drm/i2c/ch7006_drv.c drm_object_attach_property(&connector->base, conf->tv_subconnector_property, base 263 drivers/gpu/drm/i2c/ch7006_drv.c drm_object_attach_property(&connector->base, conf->tv_left_margin_property, base 265 drivers/gpu/drm/i2c/ch7006_drv.c drm_object_attach_property(&connector->base, conf->tv_bottom_margin_property, base 267 drivers/gpu/drm/i2c/ch7006_drv.c drm_object_attach_property(&connector->base, conf->tv_mode_property, base 269 drivers/gpu/drm/i2c/ch7006_drv.c drm_object_attach_property(&connector->base, conf->tv_brightness_property, base 271 drivers/gpu/drm/i2c/ch7006_drv.c drm_object_attach_property(&connector->base, conf->tv_contrast_property, base 273 drivers/gpu/drm/i2c/ch7006_drv.c drm_object_attach_property(&connector->base, conf->tv_flicker_reduction_property, base 275 drivers/gpu/drm/i2c/ch7006_drv.c drm_object_attach_property(&connector->base, priv->scale_property, base 365 drivers/gpu/drm/i810/i810_dma.c dev_priv->ring.map.offset = dev->agp->base + init->ring_start; base 722 drivers/gpu/drm/i810/i810_dma.c unsigned long start = address - dev->agp->base; base 1041 drivers/gpu/drm/i810/i810_dma.c unsigned long start = address - dev->agp->base; base 78 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 79 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 121 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); base 148 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); base 203 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 204 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 268 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 269 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 279 drivers/gpu/drm/i915/display/icl_dsi.c &pipe_config->base.adjusted_mode; base 306 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 307 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 348 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 349 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 364 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 365 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 375 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 376 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 424 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 425 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 476 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 477 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 495 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 496 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 561 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 562 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 577 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 578 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 594 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 595 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 626 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 627 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 628 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); base 768 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 769 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 771 drivers/gpu/drm/i915/display/icl_dsi.c &pipe_config->base.adjusted_mode; base 888 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 889 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 909 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 910 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 960 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 990 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 991 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1042 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1066 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1067 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1089 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1101 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1102 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1142 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1143 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1164 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1165 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1192 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1217 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1219 drivers/gpu/drm/i915/display/icl_dsi.c &pipe_config->base.adjusted_mode; base 1244 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1245 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 1246 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1252 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; base 1254 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->base.adjusted_mode.crtc_clock *= 2; base 1266 drivers/gpu/drm/i915/display/icl_dsi.c base); base 1268 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 1272 drivers/gpu/drm/i915/display/icl_dsi.c &pipe_config->base.adjusted_mode; base 1295 drivers/gpu/drm/i915/display/icl_dsi.c get_dsi_io_power_domains(to_i915(encoder->base.dev), base 1296 drivers/gpu/drm/i915/display/icl_dsi.c enc_to_intel_dsi(&encoder->base)); base 1302 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1303 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1429 drivers/gpu/drm/i915/display/icl_dsi.c struct drm_device *dev = intel_dsi->base.base.dev; base 1534 drivers/gpu/drm/i915/display/icl_dsi.c drm_connector_attach_scaling_mode_property(&connector->base, base 1537 drivers/gpu/drm/i915/display/icl_dsi.c connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; base 1539 drivers/gpu/drm/i915/display/icl_dsi.c connector->base.display_info.panel_orientation = base 1541 drivers/gpu/drm/i915/display/icl_dsi.c drm_connector_init_panel_orientation_property(&connector->base, base 1569 drivers/gpu/drm/i915/display/icl_dsi.c encoder = &intel_dsi->base; base 1571 drivers/gpu/drm/i915/display/icl_dsi.c connector = &intel_connector->base; base 1574 drivers/gpu/drm/i915/display/icl_dsi.c drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, base 1644 drivers/gpu/drm/i915/display/icl_dsi.c drm_encoder_cleanup(&encoder->base); base 67 drivers/gpu/drm/i915/display/intel_atomic.c property->base.id, property->name); base 104 drivers/gpu/drm/i915/display/intel_atomic.c property->base.id, property->name); base 144 drivers/gpu/drm/i915/display/intel_atomic.c new_conn_state->base.colorspace != old_conn_state->base.colorspace || base 145 drivers/gpu/drm/i915/display/intel_atomic.c new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio || base 146 drivers/gpu/drm/i915/display/intel_atomic.c new_conn_state->base.content_type != old_conn_state->base.content_type || base 147 drivers/gpu/drm/i915/display/intel_atomic.c new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode || base 148 drivers/gpu/drm/i915/display/intel_atomic.c !blob_equal(new_conn_state->base.hdr_output_metadata, base 149 drivers/gpu/drm/i915/display/intel_atomic.c old_conn_state->base.hdr_output_metadata)) base 173 drivers/gpu/drm/i915/display/intel_atomic.c __drm_atomic_helper_connector_duplicate_state(connector, &state->base); base 174 drivers/gpu/drm/i915/display/intel_atomic.c return &state->base; base 195 drivers/gpu/drm/i915/display/intel_atomic.c __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base); base 209 drivers/gpu/drm/i915/display/intel_atomic.c return &crtc_state->base; base 233 drivers/gpu/drm/i915/display/intel_atomic.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); base 253 drivers/gpu/drm/i915/display/intel_atomic.c if (plane_state && plane_state->base.fb && base 254 drivers/gpu/drm/i915/display/intel_atomic.c plane_state->base.fb->format->is_yuv && base 255 drivers/gpu/drm/i915/display/intel_atomic.c plane_state->base.fb->format->num_planes > 1) { base 256 drivers/gpu/drm/i915/display/intel_atomic.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 320 drivers/gpu/drm/i915/display/intel_atomic.c struct drm_atomic_state *drm_state = crtc_state->base.state; base 358 drivers/gpu/drm/i915/display/intel_atomic.c idx = intel_crtc->base.base.id; base 379 drivers/gpu/drm/i915/display/intel_atomic.c plane->base.id); base 388 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->base.planes_changed = true; base 392 drivers/gpu/drm/i915/display/intel_atomic.c idx = plane->base.id; base 416 drivers/gpu/drm/i915/display/intel_atomic.c if (!state || drm_atomic_state_init(dev, &state->base) < 0) { base 421 drivers/gpu/drm/i915/display/intel_atomic.c return &state->base; base 427 drivers/gpu/drm/i915/display/intel_atomic.c drm_atomic_state_default_clear(&state->base); base 436 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); base 59 drivers/gpu/drm/i915/display/intel_atomic_plane.c __drm_atomic_helper_plane_reset(&plane->base, &plane_state->base); base 67 drivers/gpu/drm/i915/display/intel_atomic_plane.c intel_plane_destroy_state(&plane->base, plane->base.state); base 91 drivers/gpu/drm/i915/display/intel_atomic_plane.c state = &intel_state->base; base 121 drivers/gpu/drm/i915/display/intel_atomic_plane.c const struct drm_framebuffer *fb = plane_state->base.fb; base 124 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (!plane_state->base.visible) base 146 drivers/gpu/drm/i915/display/intel_atomic_plane.c struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane); base 153 drivers/gpu/drm/i915/display/intel_atomic_plane.c new_plane_state->base.visible = false; base 155 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (!new_plane_state->base.crtc && !old_plane_state->base.crtc) base 163 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (new_plane_state->base.visible) base 166 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (new_plane_state->base.visible && base 167 drivers/gpu/drm/i915/display/intel_atomic_plane.c is_planar_yuv_format(new_plane_state->base.fb->format->format)) base 170 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (new_plane_state->base.visible && base 171 drivers/gpu/drm/i915/display/intel_atomic_plane.c new_plane_state->base.fb->format->format == DRM_FORMAT_C8) base 174 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (new_plane_state->base.visible || old_plane_state->base.visible) base 188 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (new_plane_state->base.crtc) base 189 drivers/gpu/drm/i915/display/intel_atomic_plane.c return to_intel_crtc(new_plane_state->base.crtc); base 191 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (old_plane_state->base.crtc) base 192 drivers/gpu/drm/i915/display/intel_atomic_plane.c return to_intel_crtc(old_plane_state->base.crtc); base 212 drivers/gpu/drm/i915/display/intel_atomic_plane.c new_plane_state->base.visible = false; base 273 drivers/gpu/drm/i915/display/intel_atomic_plane.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 275 drivers/gpu/drm/i915/display/intel_atomic_plane.c trace_intel_update_plane(&plane->base, crtc); base 283 drivers/gpu/drm/i915/display/intel_atomic_plane.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 285 drivers/gpu/drm/i915/display/intel_atomic_plane.c trace_intel_update_plane(&plane->base, crtc); base 292 drivers/gpu/drm/i915/display/intel_atomic_plane.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 294 drivers/gpu/drm/i915/display/intel_atomic_plane.c trace_intel_disable_plane(&plane->base, crtc); base 321 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (new_plane_state->base.visible) { base 361 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (new_plane_state->base.visible) base 236 drivers/gpu/drm/i915/display/intel_audio.c &crtc_state->base.adjusted_mode; base 314 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 335 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 375 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 422 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 474 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 506 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 556 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 557 drivers/gpu/drm/i915/display/intel_audio.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 602 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 603 drivers/gpu/drm/i915/display/intel_audio.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 690 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 692 drivers/gpu/drm/i915/display/intel_audio.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 695 drivers/gpu/drm/i915/display/intel_audio.c &crtc_state->base.adjusted_mode; base 702 drivers/gpu/drm/i915/display/intel_audio.c connector->base.id, connector->name); base 705 drivers/gpu/drm/i915/display/intel_audio.c connector->base.id, base 707 drivers/gpu/drm/i915/display/intel_audio.c connector->encoder->base.id, base 724 drivers/gpu/drm/i915/display/intel_audio.c if (acomp && acomp->base.audio_ops && base 725 drivers/gpu/drm/i915/display/intel_audio.c acomp->base.audio_ops->pin_eld_notify) { base 729 drivers/gpu/drm/i915/display/intel_audio.c acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, base 751 drivers/gpu/drm/i915/display/intel_audio.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 753 drivers/gpu/drm/i915/display/intel_audio.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 767 drivers/gpu/drm/i915/display/intel_audio.c if (acomp && acomp->base.audio_ops && base 768 drivers/gpu/drm/i915/display/intel_audio.c acomp->base.audio_ops->pin_eld_notify) { base 772 drivers/gpu/drm/i915/display/intel_audio.c acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, base 984 drivers/gpu/drm/i915/display/intel_audio.c if (!encoder || !encoder->base.crtc) { base 990 drivers/gpu/drm/i915/display/intel_audio.c crtc = to_intel_crtc(encoder->base.crtc); base 1050 drivers/gpu/drm/i915/display/intel_audio.c if (WARN_ON(acomp->base.ops || acomp->base.dev)) base 1057 drivers/gpu/drm/i915/display/intel_audio.c acomp->base.ops = &i915_audio_component_ops; base 1058 drivers/gpu/drm/i915/display/intel_audio.c acomp->base.dev = i915_kdev; base 1075 drivers/gpu/drm/i915/display/intel_audio.c acomp->base.ops = NULL; base 1076 drivers/gpu/drm/i915/display/intel_audio.c acomp->base.dev = NULL; base 84 drivers/gpu/drm/i915/display/intel_bios.c const u8 *base = _bdb; base 95 drivers/gpu/drm/i915/display/intel_bios.c current_id = *(base + index); base 96 drivers/gpu/drm/i915/display/intel_bios.c current_size = _get_blocksize(base + index); base 103 drivers/gpu/drm/i915/display/intel_bios.c return base + index; base 267 drivers/gpu/drm/i915/display/intel_bw.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 288 drivers/gpu/drm/i915/display/intel_bw.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 328 drivers/gpu/drm/i915/display/intel_bw.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 331 drivers/gpu/drm/i915/display/intel_bw.c bw_state = drm_atomic_get_private_obj_state(&state->base, base 341 drivers/gpu/drm/i915/display/intel_bw.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 412 drivers/gpu/drm/i915/display/intel_bw.c __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); base 414 drivers/gpu/drm/i915/display/intel_bw.c return &state->base; base 437 drivers/gpu/drm/i915/display/intel_bw.c &state->base, &intel_bw_funcs); base 18 drivers/gpu/drm/i915/display/intel_bw.h struct drm_private_state base; base 24 drivers/gpu/drm/i915/display/intel_bw.h #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base) base 2118 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 2220 drivers/gpu/drm/i915/display/intel_cdclk.c to_i915(crtc_state->base.crtc->dev); base 2223 drivers/gpu/drm/i915/display/intel_cdclk.c if (!crtc_state->base.enable) base 2296 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 2331 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 2342 drivers/gpu/drm/i915/display/intel_cdclk.c if (crtc_state->base.enable) base 2359 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 2418 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 2428 drivers/gpu/drm/i915/display/intel_cdclk.c if (!crtc_state->base.enable) base 2489 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 2531 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 2564 drivers/gpu/drm/i915/display/intel_cdclk.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 104 drivers/gpu/drm/i915/display/intel_color.c return !crtc_state->base.degamma_lut && base 105 drivers/gpu/drm/i915/display/intel_color.c !crtc_state->base.ctm && base 106 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.gamma_lut && base 107 drivers/gpu/drm/i915/display/intel_color.c lut_is_legacy(crtc_state->base.gamma_lut); base 141 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 169 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 192 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 206 drivers/gpu/drm/i915/display/intel_color.c const struct drm_color_ctm *ctm = crtc_state->base.ctm->data; base 257 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 258 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 261 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.ctm) { base 296 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 297 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 299 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.ctm) { base 325 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 326 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 329 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.ctm) { base 330 drivers/gpu/drm/i915/display/intel_color.c const struct drm_color_ctm *ctm = crtc_state->base.ctm->data; base 391 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 392 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 422 drivers/gpu/drm/i915/display/intel_color.c i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut); base 427 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 428 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 440 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 441 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 455 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 456 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 465 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 466 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 492 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 511 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 512 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; base 523 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 534 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 535 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; base 560 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 587 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 613 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 635 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 636 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; base 637 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut; base 658 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 659 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; base 660 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut; base 681 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 682 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 685 drivers/gpu/drm/i915/display/intel_color.c const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data; base 720 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 721 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 747 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; base 748 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 758 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.degamma_lut) base 789 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 790 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 802 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 803 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 804 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *blob = crtc_state->base.gamma_lut; base 831 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 832 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 833 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *blob = crtc_state->base.gamma_lut; base 883 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; base 884 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 886 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.degamma_lut) base 919 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 946 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 961 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 962 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; base 963 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut; base 981 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 988 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 995 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 997 drivers/gpu/drm/i915/display/intel_color.c to_intel_atomic_state(new_crtc_state->base.state); base 1001 drivers/gpu/drm/i915/display/intel_color.c return !old_crtc_state->base.gamma_lut && base 1002 drivers/gpu/drm/i915/display/intel_color.c !old_crtc_state->base.degamma_lut; base 1007 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 1009 drivers/gpu/drm/i915/display/intel_color.c to_intel_atomic_state(new_crtc_state->base.state); base 1021 drivers/gpu/drm/i915/display/intel_color.c return !old_crtc_state->base.gamma_lut; base 1026 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 1028 drivers/gpu/drm/i915/display/intel_color.c to_intel_atomic_state(new_crtc_state->base.state); base 1039 drivers/gpu/drm/i915/display/intel_color.c !old_crtc_state->base.gamma_lut; base 1044 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 1051 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 1060 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1075 drivers/gpu/drm/i915/display/intel_color.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 1076 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1078 drivers/gpu/drm/i915/display/intel_color.c to_intel_atomic_state(new_crtc_state->base.state); base 1083 drivers/gpu/drm/i915/display/intel_color.c if (!new_crtc_state->base.active || base 1084 drivers/gpu/drm/i915/display/intel_color.c drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) base 1126 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 1127 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; base 1128 drivers/gpu/drm/i915/display/intel_color.c const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut; base 1176 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.gamma_lut && base 1197 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.degamma_lut) base 1199 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.ctm) base 1201 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.gamma_lut) base 1262 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.gamma_lut && base 1290 drivers/gpu/drm/i915/display/intel_color.c else if (crtc_state->base.gamma_lut && base 1291 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.degamma_lut) base 1305 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.degamma_lut || base 1323 drivers/gpu/drm/i915/display/intel_color.c (crtc_state->base.gamma_lut || base 1324 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.degamma_lut) && base 1329 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.ctm || limited_color_range; base 1362 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.gamma_lut && base 1367 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.degamma_lut || base 1369 drivers/gpu/drm/i915/display/intel_color.c crtc_state->base.ctm || crtc_state->limited_color_range; base 1388 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.degamma_lut) base 1391 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.gamma_lut && base 1395 drivers/gpu/drm/i915/display/intel_color.c if (!crtc_state->base.gamma_lut || base 1408 drivers/gpu/drm/i915/display/intel_color.c if (crtc_state->base.ctm) base 1437 drivers/gpu/drm/i915/display/intel_color.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1440 drivers/gpu/drm/i915/display/intel_color.c drm_mode_crtc_set_gamma_size(&crtc->base, 256); base 1485 drivers/gpu/drm/i915/display/intel_color.c drm_crtc_enable_color_mgmt(&crtc->base, base 53 drivers/gpu/drm/i915/display/intel_connector.c __drm_atomic_helper_connector_reset(&connector->base, base 54 drivers/gpu/drm/i915/display/intel_connector.c &conn_state->base); base 84 drivers/gpu/drm/i915/display/intel_connector.c kfree(to_intel_digital_connector_state(connector->base.state)); base 145 drivers/gpu/drm/i915/display/intel_connector.c drm_connector_attach_encoder(&connector->base, &encoder->base); base 163 drivers/gpu/drm/i915/display/intel_connector.c struct drm_device *dev = connector->base.dev; base 167 drivers/gpu/drm/i915/display/intel_connector.c if (!connector->base.state->crtc) base 170 drivers/gpu/drm/i915/display/intel_connector.c return to_intel_crtc(connector->base.state->crtc)->pipe; base 237 drivers/gpu/drm/i915/display/intel_connector.c drm_object_attach_property(&connector->base, prop, 0); base 265 drivers/gpu/drm/i915/display/intel_connector.c drm_object_attach_property(&connector->base, prop, 0); base 272 drivers/gpu/drm/i915/display/intel_connector.c drm_object_attach_property(&connector->base, base 281 drivers/gpu/drm/i915/display/intel_connector.c drm_object_attach_property(&connector->base, base 55 drivers/gpu/drm/i915/display/intel_crt.c struct intel_encoder base; base 65 drivers/gpu/drm/i915/display/intel_crt.c return container_of(encoder, struct intel_crt, base); base 92 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 111 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 135 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); base 137 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; base 143 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 147 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | base 151 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); base 153 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); base 162 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 164 drivers/gpu/drm/i915/display/intel_crt.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 165 drivers/gpu/drm/i915/display/intel_crt.c const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; base 231 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 242 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 262 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 273 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 274 drivers/gpu/drm/i915/display/intel_crt.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 290 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 291 drivers/gpu/drm/i915/display/intel_crt.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 361 drivers/gpu/drm/i915/display/intel_crt.c &pipe_config->base.adjusted_mode; base 376 drivers/gpu/drm/i915/display/intel_crt.c &pipe_config->base.adjusted_mode; base 391 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 393 drivers/gpu/drm/i915/display/intel_crt.c &pipe_config->base.adjusted_mode; base 491 drivers/gpu/drm/i915/display/intel_crt.c reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); base 516 drivers/gpu/drm/i915/display/intel_crt.c intel_hpd_enable(dev_priv, crt->base.hpd_pin); base 605 drivers/gpu/drm/i915/display/intel_crt.c struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); base 610 drivers/gpu/drm/i915/display/intel_crt.c BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); base 641 drivers/gpu/drm/i915/display/intel_crt.c struct drm_device *dev = crt->base.base.dev; base 791 drivers/gpu/drm/i915/display/intel_crt.c struct intel_encoder *intel_encoder = &crt->base; base 797 drivers/gpu/drm/i915/display/intel_crt.c connector->base.id, connector->name, base 882 drivers/gpu/drm/i915/display/intel_crt.c struct intel_encoder *intel_encoder = &crt->base; base 991 drivers/gpu/drm/i915/display/intel_crt.c connector = &intel_connector->base; base 993 drivers/gpu/drm/i915/display/intel_crt.c drm_connector_init(&dev_priv->drm, &intel_connector->base, base 996 drivers/gpu/drm/i915/display/intel_crt.c drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, base 999 drivers/gpu/drm/i915/display/intel_crt.c intel_connector_attach_encoder(intel_connector, &crt->base); base 1001 drivers/gpu/drm/i915/display/intel_crt.c crt->base.type = INTEL_OUTPUT_ANALOG; base 1002 drivers/gpu/drm/i915/display/intel_crt.c crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); base 1004 drivers/gpu/drm/i915/display/intel_crt.c crt->base.crtc_mask = (1 << 0); base 1006 drivers/gpu/drm/i915/display/intel_crt.c crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); base 1016 drivers/gpu/drm/i915/display/intel_crt.c crt->base.power_domain = POWER_DOMAIN_PORT_CRT; base 1020 drivers/gpu/drm/i915/display/intel_crt.c crt->base.hpd_pin = HPD_CRT; base 1021 drivers/gpu/drm/i915/display/intel_crt.c crt->base.hotplug = intel_encoder_hotplug; base 1025 drivers/gpu/drm/i915/display/intel_crt.c crt->base.port = PORT_E; base 1026 drivers/gpu/drm/i915/display/intel_crt.c crt->base.get_config = hsw_crt_get_config; base 1027 drivers/gpu/drm/i915/display/intel_crt.c crt->base.get_hw_state = intel_ddi_get_hw_state; base 1028 drivers/gpu/drm/i915/display/intel_crt.c crt->base.compute_config = hsw_crt_compute_config; base 1029 drivers/gpu/drm/i915/display/intel_crt.c crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; base 1030 drivers/gpu/drm/i915/display/intel_crt.c crt->base.pre_enable = hsw_pre_enable_crt; base 1031 drivers/gpu/drm/i915/display/intel_crt.c crt->base.enable = hsw_enable_crt; base 1032 drivers/gpu/drm/i915/display/intel_crt.c crt->base.disable = hsw_disable_crt; base 1033 drivers/gpu/drm/i915/display/intel_crt.c crt->base.post_disable = hsw_post_disable_crt; base 1036 drivers/gpu/drm/i915/display/intel_crt.c crt->base.compute_config = pch_crt_compute_config; base 1037 drivers/gpu/drm/i915/display/intel_crt.c crt->base.disable = pch_disable_crt; base 1038 drivers/gpu/drm/i915/display/intel_crt.c crt->base.post_disable = pch_post_disable_crt; base 1040 drivers/gpu/drm/i915/display/intel_crt.c crt->base.compute_config = intel_crt_compute_config; base 1041 drivers/gpu/drm/i915/display/intel_crt.c crt->base.disable = intel_disable_crt; base 1043 drivers/gpu/drm/i915/display/intel_crt.c crt->base.port = PORT_NONE; base 1044 drivers/gpu/drm/i915/display/intel_crt.c crt->base.get_config = intel_crt_get_config; base 1045 drivers/gpu/drm/i915/display/intel_crt.c crt->base.get_hw_state = intel_crt_get_hw_state; base 1046 drivers/gpu/drm/i915/display/intel_crt.c crt->base.enable = intel_enable_crt; base 1072 drivers/gpu/drm/i915/display/intel_crt.c intel_crt_reset(&crt->base.base); base 922 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 959 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1068 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_device *dev = crtc->base.dev; base 1073 drivers/gpu/drm/i915/display/intel_ddi.c for_each_encoder_on_crtc(dev, &crtc->base, encoder) { base 1199 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 1201 drivers/gpu/drm/i915/display/intel_ddi.c enc_to_dig_port(&encoder->base); base 1211 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_device *dev = crtc->base.dev; base 1215 drivers/gpu/drm/i915/display/intel_ddi.c for_each_encoder_on_crtc(dev, &crtc->base, encoder) { base 1482 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->base.adjusted_mode.crtc_clock = dotclock; base 1488 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1514 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1610 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1681 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1697 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1698 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1751 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1752 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1766 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1768 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1798 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) base 1800 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) base 1853 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1854 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1879 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_device *dev = intel_encoder->base.dev; base 1909 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_device *dev = intel_connector->base.dev; base 1912 drivers/gpu/drm/i915/display/intel_ddi.c int type = intel_connector->base.connector_type; base 1972 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_device *dev = encoder->base.dev; base 2114 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2126 drivers/gpu/drm/i915/display/intel_ddi.c dig_port = enc_to_dig_port(&encoder->base); base 2152 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 2153 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 2170 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 2200 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); base 2201 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2244 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2270 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2271 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 2331 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2395 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2404 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 2519 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2530 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 2589 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2709 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2745 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); base 2746 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_encoder *encoder = &dport->base; base 2763 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); base 2764 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_encoder *encoder = &dport->base; base 2792 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2827 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2842 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2855 drivers/gpu/drm/i915/display/intel_ddi.c if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { base 2869 drivers/gpu/drm/i915/display/intel_ddi.c ddi_clk_needed = encoder->base.crtc; base 2921 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2977 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2998 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); base 2999 drivers/gpu/drm/i915/display/intel_ddi.c enum port port = dig_port->base.port; base 3030 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); base 3031 drivers/gpu/drm/i915/display/intel_ddi.c enum port port = dig_port->base.port; base 3062 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); base 3063 drivers/gpu/drm/i915/display/intel_ddi.c enum port port = intel_dig_port->base.port; base 3135 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3154 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3171 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3172 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3175 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); base 3239 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); base 3241 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3244 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); base 3280 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 3281 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 3308 drivers/gpu/drm/i915/display/intel_ddi.c enc_to_intel_lspcon(&encoder->base); base 3313 drivers/gpu/drm/i915/display/intel_ddi.c enc_to_dig_port(&encoder->base); base 3325 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3353 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3354 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); base 3386 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3387 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); base 3409 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3439 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3473 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3474 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3513 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3514 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); base 3522 drivers/gpu/drm/i915/display/intel_ddi.c connector->base.id, connector->name); base 3590 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3619 drivers/gpu/drm/i915/display/intel_ddi.c connector->base.id, connector->name); base 3638 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3700 drivers/gpu/drm/i915/display/intel_ddi.c intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes); base 3701 drivers/gpu/drm/i915/display/intel_ddi.c if (crtc_state && crtc_state->base.active) base 3710 drivers/gpu/drm/i915/display/intel_ddi.c intel_tc_port_put_link(enc_to_dig_port(&encoder->base)); base 3718 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3719 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); base 3746 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3747 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); base 3763 drivers/gpu/drm/i915/display/intel_ddi.c to_i915(intel_dig_port->base.base.dev); base 3764 drivers/gpu/drm/i915/display/intel_ddi.c enum port port = intel_dig_port->base.port; base 3830 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3831 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); base 3849 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->base.adjusted_mode.flags |= flags; base 3978 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 3979 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 4027 drivers/gpu/drm/i915/display/intel_ddi.c enum port port = intel_dig_port->base.port; base 4076 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 4077 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base); base 4087 drivers/gpu/drm/i915/display/intel_ddi.c if (!connector || connector->base.status != connector_status_connected) base 4095 drivers/gpu/drm/i915/display/intel_ddi.c conn_state = connector->base.state; base 4101 drivers/gpu/drm/i915/display/intel_ddi.c ret = drm_modeset_lock(&crtc->base.mutex, ctx); base 4105 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state = to_intel_crtc_state(crtc->base.state); base 4109 drivers/gpu/drm/i915/display/intel_ddi.c if (!crtc_state->base.active) base 4141 drivers/gpu/drm/i915/display/intel_ddi.c return modeset_pipe(&crtc->base, ctx); base 4149 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); base 4159 drivers/gpu/drm/i915/display/intel_ddi.c if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) base 4203 drivers/gpu/drm/i915/display/intel_ddi.c enum port port = intel_dig_port->base.port; base 4217 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); base 4219 drivers/gpu/drm/i915/display/intel_ddi.c if (dport->base.port != PORT_A) base 4246 drivers/gpu/drm/i915/display/intel_ddi.c struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); base 4247 drivers/gpu/drm/i915/display/intel_ddi.c enum port port = intel_dport->base.port; base 4311 drivers/gpu/drm/i915/display/intel_ddi.c intel_encoder = &intel_dig_port->base; base 4312 drivers/gpu/drm/i915/display/intel_ddi.c encoder = &intel_encoder->base; base 521 drivers/gpu/drm/i915/display/intel_display.c return drm_atomic_crtc_needs_modeset(&state->base); base 635 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 671 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc_state->base.crtc->dev; base 729 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc_state->base.crtc->dev; base 785 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc_state->base.crtc->dev; base 879 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 880 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 939 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 940 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 1017 drivers/gpu/drm/i915/display/intel_display.c return crtc->active && crtc->base.primary->state->fb && base 1018 drivers/gpu/drm/i915/display/intel_display.c crtc->config->base.adjusted_mode.crtc_clock; base 1050 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1072 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 1073 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1280 drivers/gpu/drm/i915/display/intel_display.c plane->base.name, onoff(state), onoff(cur_state)); base 1288 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1378 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1392 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1411 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1441 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1486 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1531 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1532 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1595 drivers/gpu/drm/i915/display/intel_display.c switch (dport->base.port) { base 1616 drivers/gpu/drm/i915/display/intel_display.c port_name(dport->base.port), base 1622 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1623 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1756 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1766 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 1786 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1788 drivers/gpu/drm/i915/display/intel_display.c drm_crtc_set_max_vblank_count(&crtc->base, base 1790 drivers/gpu/drm/i915/display/intel_display.c drm_crtc_vblank_on(&crtc->base); base 1795 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 1796 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1853 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 1854 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 2060 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 2061 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 2194 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = state->base.fb; base 2295 drivers/gpu/drm/i915/display/intel_display.c return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane, base 2296 drivers/gpu/drm/i915/display/intel_display.c state->base.rotation, base 2370 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *intel_plane = to_intel_plane(state->base.plane); base 2371 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); base 2372 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = state->base.fb; base 2373 drivers/gpu/drm/i915/display/intel_display.c unsigned int rotation = state->base.rotation; base 2510 drivers/gpu/drm/i915/display/intel_display.c plane = to_intel_plane(crtc->base.primary); base 2561 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 2562 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 2563 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 2601 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 2602 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 2603 drivers/gpu/drm/i915/display/intel_display.c unsigned int rotation = plane_state->base.rotation; base 2610 drivers/gpu/drm/i915/display/intel_display.c if (!plane_state->base.visible) base 2783 drivers/gpu/drm/i915/display/intel_display.c if (mul_u32_u32(max_size, tile_size) > obj->base.size) { base 2785 drivers/gpu/drm/i915/display/intel_display.c mul_u32_u32(max_size, tile_size), obj->base.size); base 2796 drivers/gpu/drm/i915/display/intel_display.c to_i915(plane_state->base.plane->dev); base 2797 drivers/gpu/drm/i915/display/intel_display.c struct drm_framebuffer *fb = plane_state->base.fb; base 2800 drivers/gpu/drm/i915/display/intel_display.c unsigned int rotation = plane_state->base.rotation; base 2811 drivers/gpu/drm/i915/display/intel_display.c src_x = plane_state->base.src.x1 >> 16; base 2812 drivers/gpu/drm/i915/display/intel_display.c src_y = plane_state->base.src.y1 >> 16; base 2813 drivers/gpu/drm/i915/display/intel_display.c src_w = drm_rect_width(&plane_state->base.src) >> 16; base 2814 drivers/gpu/drm/i915/display/intel_display.c src_h = drm_rect_height(&plane_state->base.src) >> 16; base 2819 drivers/gpu/drm/i915/display/intel_display.c drm_rect_translate(&plane_state->base.src, base 2824 drivers/gpu/drm/i915/display/intel_display.c drm_rect_rotate(&plane_state->base.src, base 2909 drivers/gpu/drm/i915/display/intel_display.c to_intel_framebuffer(plane_state->base.fb); base 2910 drivers/gpu/drm/i915/display/intel_display.c unsigned int rotation = plane_state->base.rotation; base 2916 drivers/gpu/drm/i915/display/intel_display.c num_planes = fb->base.format->num_planes; base 2930 drivers/gpu/drm/i915/display/intel_display.c intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation); base 2933 drivers/gpu/drm/i915/display/intel_display.c plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation); base 2947 drivers/gpu/drm/i915/display/intel_display.c drm_rect_rotate(&plane_state->base.src, base 2948 drivers/gpu/drm/i915/display/intel_display.c fb->base.width << 16, fb->base.height << 16, base 3037 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 3040 drivers/gpu/drm/i915/display/intel_display.c struct drm_framebuffer *fb = &plane_config->fb->base; base 3041 drivers/gpu/drm/i915/display/intel_display.c u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); base 3042 drivers/gpu/drm/i915/display/intel_display.c u32 size_aligned = round_up(plane_config->base + plane_config->size, base 3115 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 3117 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.visible = visible; base 3120 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.plane_mask |= drm_plane_mask(&plane->base); base 3122 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base); base 3127 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 3138 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.plane_mask) base 3146 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc_state(crtc->base.state); base 3148 drivers/gpu/drm/i915/display/intel_display.c to_intel_plane_state(plane->base.state); base 3151 drivers/gpu/drm/i915/display/intel_display.c plane->base.base.id, plane->base.name, base 3152 drivers/gpu/drm/i915/display/intel_display.c crtc->base.base.id, crtc->base.name); base 3159 drivers/gpu/drm/i915/display/intel_display.c intel_pre_disable_primary_noatomic(&crtc->base); base 3174 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = intel_crtc->base.dev; base 3177 drivers/gpu/drm/i915/display/intel_display.c struct drm_plane *primary = intel_crtc->base.primary; base 3188 drivers/gpu/drm/i915/display/intel_display.c fb = &plane_config->fb->base; base 3201 drivers/gpu/drm/i915/display/intel_display.c if (c == &intel_crtc->base) base 3211 drivers/gpu/drm/i915/display/intel_display.c if (intel_plane_ggtt_offset(state) == plane_config->base) { base 3212 drivers/gpu/drm/i915/display/intel_display.c fb = state->base.fb; base 3230 drivers/gpu/drm/i915/display/intel_display.c intel_state->base.rotation = plane_config->rotation; base 3232 drivers/gpu/drm/i915/display/intel_display.c intel_state->base.rotation); base 3234 drivers/gpu/drm/i915/display/intel_display.c intel_fb_pitch(fb, 0, intel_state->base.rotation); base 3264 drivers/gpu/drm/i915/display/intel_display.c intel_state->base.src = drm_plane_state_src(plane_state); base 3265 drivers/gpu/drm/i915/display/intel_display.c intel_state->base.dst = drm_plane_state_dest(plane_state); base 3271 drivers/gpu/drm/i915/display/intel_display.c plane_state->crtc = &intel_crtc->base; base 3353 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 3390 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); base 3391 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 3392 drivers/gpu/drm/i915/display/intel_display.c unsigned int rotation = plane_state->base.rotation; base 3393 drivers/gpu/drm/i915/display/intel_display.c int x = plane_state->base.src.x1 >> 16; base 3394 drivers/gpu/drm/i915/display/intel_display.c int y = plane_state->base.src.y1 >> 16; base 3395 drivers/gpu/drm/i915/display/intel_display.c int w = drm_rect_width(&plane_state->base.src) >> 16; base 3396 drivers/gpu/drm/i915/display/intel_display.c int h = drm_rect_height(&plane_state->base.src) >> 16; base 3474 drivers/gpu/drm/i915/display/intel_display.c drm_rect_translate(&plane_state->base.src, base 3475 drivers/gpu/drm/i915/display/intel_display.c (x << 16) - plane_state->base.src.x1, base 3476 drivers/gpu/drm/i915/display/intel_display.c (y << 16) - plane_state->base.src.y1); base 3483 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 3484 drivers/gpu/drm/i915/display/intel_display.c unsigned int rotation = plane_state->base.rotation; base 3487 drivers/gpu/drm/i915/display/intel_display.c int x = plane_state->base.src.x1 >> 17; base 3488 drivers/gpu/drm/i915/display/intel_display.c int y = plane_state->base.src.y1 >> 17; base 3489 drivers/gpu/drm/i915/display/intel_display.c int w = drm_rect_width(&plane_state->base.src) >> 17; base 3490 drivers/gpu/drm/i915/display/intel_display.c int h = drm_rect_height(&plane_state->base.src) >> 17; base 3512 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 3513 drivers/gpu/drm/i915/display/intel_display.c int src_x = plane_state->base.src.x1 >> 16; base 3514 drivers/gpu/drm/i915/display/intel_display.c int src_y = plane_state->base.src.y1 >> 16; base 3533 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 3540 drivers/gpu/drm/i915/display/intel_display.c if (!plane_state->base.visible) base 3573 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 3597 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 3598 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 3617 drivers/gpu/drm/i915/display/intel_display.c to_i915(plane_state->base.plane->dev); base 3618 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 3619 drivers/gpu/drm/i915/display/intel_display.c unsigned int rotation = plane_state->base.rotation; base 3671 drivers/gpu/drm/i915/display/intel_display.c to_i915(plane_state->base.plane->dev); base 3680 drivers/gpu/drm/i915/display/intel_display.c if (!plane_state->base.visible) base 3683 drivers/gpu/drm/i915/display/intel_display.c src_x = plane_state->base.src.x1 >> 16; base 3684 drivers/gpu/drm/i915/display/intel_display.c src_y = plane_state->base.src.y1 >> 16; base 3698 drivers/gpu/drm/i915/display/intel_display.c drm_rect_translate(&plane_state->base.src, base 3699 drivers/gpu/drm/i915/display/intel_display.c (src_x << 16) - plane_state->base.src.x1, base 3700 drivers/gpu/drm/i915/display/intel_display.c (src_y << 16) - plane_state->base.src.y1); base 3704 drivers/gpu/drm/i915/display/intel_display.c unsigned int rotation = plane_state->base.rotation; base 3705 drivers/gpu/drm/i915/display/intel_display.c int src_w = drm_rect_width(&plane_state->base.src) >> 16; base 3706 drivers/gpu/drm/i915/display/intel_display.c int src_h = drm_rect_height(&plane_state->base.src) >> 16; base 3725 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 3743 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 3750 drivers/gpu/drm/i915/display/intel_display.c ret = drm_atomic_helper_check_plane_state(&plane_state->base, base 3751 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->base, base 3763 drivers/gpu/drm/i915/display/intel_display.c if (!plane_state->base.visible) base 3779 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 3784 drivers/gpu/drm/i915/display/intel_display.c int crtc_x = plane_state->base.dst.x1; base 3785 drivers/gpu/drm/i915/display/intel_display.c int crtc_y = plane_state->base.dst.y1; base 3786 drivers/gpu/drm/i915/display/intel_display.c int crtc_w = drm_rect_width(&plane_state->base.dst); base 3787 drivers/gpu/drm/i915/display/intel_display.c int crtc_h = drm_rect_height(&plane_state->base.dst); base 3849 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 3880 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 3914 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = intel_crtc->base.dev; base 3927 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); base 3957 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 3958 drivers/gpu/drm/i915/display/intel_display.c unsigned int rotation = plane_state->base.rotation; base 4027 drivers/gpu/drm/i915/display/intel_display.c if (!plane_state->base.fb->format->has_alpha) base 4030 drivers/gpu/drm/i915/display/intel_display.c switch (plane_state->base.pixel_blend_mode) { base 4038 drivers/gpu/drm/i915/display/intel_display.c MISSING_CASE(plane_state->base.pixel_blend_mode); base 4045 drivers/gpu/drm/i915/display/intel_display.c if (!plane_state->base.fb->format->has_alpha) base 4048 drivers/gpu/drm/i915/display/intel_display.c switch (plane_state->base.pixel_blend_mode) { base 4056 drivers/gpu/drm/i915/display/intel_display.c MISSING_CASE(plane_state->base.pixel_blend_mode); base 4122 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 4141 drivers/gpu/drm/i915/display/intel_display.c to_i915(plane_state->base.plane->dev); base 4142 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 4143 drivers/gpu/drm/i915/display/intel_display.c unsigned int rotation = plane_state->base.rotation; base 4153 drivers/gpu/drm/i915/display/intel_display.c if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709) base 4156 drivers/gpu/drm/i915/display/intel_display.c if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE) base 4178 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 4197 drivers/gpu/drm/i915/display/intel_display.c to_i915(plane_state->base.plane->dev); base 4198 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 4199 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 4206 drivers/gpu/drm/i915/display/intel_display.c if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709) base 4211 drivers/gpu/drm/i915/display/intel_display.c if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE) base 4375 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 4400 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 4401 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 4404 drivers/gpu/drm/i915/display/intel_display.c crtc->base.mode = new_crtc_state->base.mode; base 4438 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 4481 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 4582 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 4715 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 4833 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); base 4834 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); base 4870 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = intel_crtc->base.dev; base 4994 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 4995 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 4996 drivers/gpu/drm/i915/display/intel_display.c int clock = crtc_state->base.adjusted_mode.crtc_clock; base 5110 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5111 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 5153 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5154 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 5183 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5190 drivers/gpu/drm/i915/display/intel_display.c for_each_new_connector_in_state(&state->base, connector, connector_state, i) { base 5191 drivers/gpu/drm/i915/display/intel_display.c if (connector_state->crtc != &crtc->base) base 5215 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5216 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 5269 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->base.adjusted_mode; base 5299 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5300 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 5416 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc(crtc_state->base.crtc); base 5417 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); base 5419 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->base.adjusted_mode; base 5435 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && base 5507 drivers/gpu/drm/i915/display/intel_display.c const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; base 5513 drivers/gpu/drm/i915/display/intel_display.c return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, base 5533 drivers/gpu/drm/i915/display/intel_display.c to_intel_plane(plane_state->base.plane); base 5534 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); base 5535 drivers/gpu/drm/i915/display/intel_display.c struct drm_framebuffer *fb = plane_state->base.fb; base 5537 drivers/gpu/drm/i915/display/intel_display.c bool force_detach = !fb || !plane_state->base.visible; base 5546 drivers/gpu/drm/i915/display/intel_display.c drm_plane_index(&intel_plane->base), base 5548 drivers/gpu/drm/i915/display/intel_display.c drm_rect_width(&plane_state->base.src) >> 16, base 5549 drivers/gpu/drm/i915/display/intel_display.c drm_rect_height(&plane_state->base.src) >> 16, base 5550 drivers/gpu/drm/i915/display/intel_display.c drm_rect_width(&plane_state->base.dst), base 5551 drivers/gpu/drm/i915/display/intel_display.c drm_rect_height(&plane_state->base.dst), base 5560 drivers/gpu/drm/i915/display/intel_display.c intel_plane->base.base.id, base 5561 drivers/gpu/drm/i915/display/intel_display.c intel_plane->base.name); base 5595 drivers/gpu/drm/i915/display/intel_display.c intel_plane->base.base.id, intel_plane->base.name, base 5596 drivers/gpu/drm/i915/display/intel_display.c fb->base.id, fb->format->format); base 5613 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5614 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 5650 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5651 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 5671 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5672 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 5707 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5708 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 5735 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = intel_crtc->base.dev; base 5817 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 5818 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 5833 drivers/gpu/drm/i915/display/intel_display.c (new_crtc_state->base.color_mgmt_changed || base 5844 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 5845 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 5860 drivers/gpu/drm/i915/display/intel_display.c (new_crtc_state->base.color_mgmt_changed || base 5870 drivers/gpu/drm/i915/display/intel_display.c old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED) base 5901 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 5902 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 5904 drivers/gpu/drm/i915/display/intel_display.c struct drm_atomic_state *state = old_crtc_state->base.state; base 5908 drivers/gpu/drm/i915/display/intel_display.c struct drm_plane *primary = crtc->base.primary; base 5912 drivers/gpu/drm/i915/display/intel_display.c intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); base 5914 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->update_wm_post && pipe_config->base.active) base 5929 drivers/gpu/drm/i915/display/intel_display.c intel_post_enable_primary(&crtc->base, pipe_config); base 5944 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 5945 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 5947 drivers/gpu/drm/i915/display/intel_display.c struct drm_atomic_state *state = old_crtc_state->base.state; base 5948 drivers/gpu/drm/i915/display/intel_display.c struct drm_plane *primary = crtc->base.primary; base 5969 drivers/gpu/drm/i915/display/intel_display.c (modeset || !new_primary_state->base.visible)) base 5992 drivers/gpu/drm/i915/display/intel_display.c if (HAS_GMCH(dev_priv) && old_crtc_state->base.active && base 6004 drivers/gpu/drm/i915/display/intel_display.c old_crtc_state->base.active) base 6038 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 6056 drivers/gpu/drm/i915/display/intel_display.c if (old_plane_state->base.visible) base 6078 drivers/gpu/drm/i915/display/intel_display.c return &dp_to_dig_port(connector->mst_port)->base; base 6080 drivers/gpu/drm/i915/display/intel_display.c encoder = intel_attached_encoder(&connector->base); base 6108 drivers/gpu/drm/i915/display/intel_display.c for_each_oldnew_connector_in_state(&state->base, conn, base 6135 drivers/gpu/drm/i915/display/intel_display.c for_each_oldnew_connector_in_state(&state->base, conn, base 6163 drivers/gpu/drm/i915/display/intel_display.c for_each_new_connector_in_state(&state->base, conn, conn_state, i) { base 6167 drivers/gpu/drm/i915/display/intel_display.c if (conn_state->crtc != &crtc->base) base 6183 drivers/gpu/drm/i915/display/intel_display.c for_each_new_connector_in_state(&state->base, conn, conn_state, i) { base 6187 drivers/gpu/drm/i915/display/intel_display.c if (conn_state->crtc != &crtc->base) base 6203 drivers/gpu/drm/i915/display/intel_display.c for_each_new_connector_in_state(&state->base, conn, conn_state, i) { base 6207 drivers/gpu/drm/i915/display/intel_display.c if (conn_state->crtc != &crtc->base) base 6224 drivers/gpu/drm/i915/display/intel_display.c for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { base 6228 drivers/gpu/drm/i915/display/intel_display.c if (old_conn_state->crtc != &crtc->base) base 6245 drivers/gpu/drm/i915/display/intel_display.c for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { base 6249 drivers/gpu/drm/i915/display/intel_display.c if (old_conn_state->crtc != &crtc->base) base 6265 drivers/gpu/drm/i915/display/intel_display.c for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { base 6269 drivers/gpu/drm/i915/display/intel_display.c if (old_conn_state->crtc != &crtc->base) base 6285 drivers/gpu/drm/i915/display/intel_display.c for_each_new_connector_in_state(&state->base, conn, conn_state, i) { base 6289 drivers/gpu/drm/i915/display/intel_display.c if (conn_state->crtc != &crtc->base) base 6299 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 6300 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(crtc->base.primary); base 6308 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = pipe_config->base.crtc; base 6403 drivers/gpu/drm/i915/display/intel_display.c return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; base 6422 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 6442 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = pipe_config->base.crtc; base 6551 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 6552 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 6567 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = old_crtc_state->base.crtc; base 6626 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = old_crtc_state->base.crtc; base 6660 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 6661 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 6749 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); base 6750 drivers/gpu/drm/i915/display/intel_display.c enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); base 6790 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 6791 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 6797 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.active) base 6807 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.encoder_mask) { base 6825 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 6826 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 6854 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = pipe_config->base.crtc; base 6910 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 6911 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 6920 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = pipe_config->base.crtc; base 6970 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 6971 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 6986 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = old_crtc_state->base.crtc; base 7052 drivers/gpu/drm/i915/display/intel_display.c to_intel_plane_state(plane->base.state); base 7054 drivers/gpu/drm/i915/display/intel_display.c if (plane_state->base.visible) base 7061 drivers/gpu/drm/i915/display/intel_display.c crtc->base.id, crtc->name); base 7078 drivers/gpu/drm/i915/display/intel_display.c crtc->base.id, crtc->name); base 7088 drivers/gpu/drm/i915/display/intel_display.c encoder->base.crtc = NULL; base 7142 drivers/gpu/drm/i915/display/intel_display.c connector->base.base.id, base 7143 drivers/gpu/drm/i915/display/intel_display.c connector->base.name); base 7154 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(!crtc_state->base.active, base 7160 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(conn_state->best_encoder != &encoder->base, base 7163 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, base 7166 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(crtc_state && crtc_state->base.active, base 7175 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.enable && crtc_state->has_pch_encoder) base 7185 drivers/gpu/drm/i915/display/intel_display.c struct drm_atomic_state *state = pipe_config->base.state; base 7257 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = intel_crtc->base.dev; base 7258 drivers/gpu/drm/i915/display/intel_display.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 7304 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 7305 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 7334 drivers/gpu/drm/i915/display/intel_display.c to_i915(crtc_state->base.crtc->dev); base 7336 drivers/gpu/drm/i915/display/intel_display.c to_intel_atomic_state(crtc_state->base.state); base 7364 drivers/gpu/drm/i915/display/intel_display.c const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 7375 drivers/gpu/drm/i915/display/intel_display.c pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; base 7408 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 7413 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.adjusted_mode.crtc_clock; base 7422 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 7423 drivers/gpu/drm/i915/display/intel_display.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 7449 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.ctm) { base 7567 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 7622 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 7623 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 7649 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 7650 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 7740 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 7840 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 7962 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.crtc = &crtc->base; base 8001 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 8074 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 8122 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 8123 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 8126 drivers/gpu/drm/i915/display/intel_display.c const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; base 8184 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 8185 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 8199 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 8205 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; base 8206 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; base 8210 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_hblank_start = base 8212 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_hblank_end = base 8216 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; base 8217 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; base 8220 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; base 8221 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; base 8225 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vblank_start = base 8227 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vblank_end = base 8231 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; base 8232 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; base 8235 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; base 8236 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vtotal += 1; base 8237 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vblank_end += 1; base 8244 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 8252 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; base 8253 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; base 8259 drivers/gpu/drm/i915/display/intel_display.c mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; base 8260 drivers/gpu/drm/i915/display/intel_display.c mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; base 8261 drivers/gpu/drm/i915/display/intel_display.c mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; base 8262 drivers/gpu/drm/i915/display/intel_display.c mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; base 8264 drivers/gpu/drm/i915/display/intel_display.c mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; base 8265 drivers/gpu/drm/i915/display/intel_display.c mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; base 8266 drivers/gpu/drm/i915/display/intel_display.c mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; base 8267 drivers/gpu/drm/i915/display/intel_display.c mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; base 8269 drivers/gpu/drm/i915/display/intel_display.c mode->flags = pipe_config->base.adjusted_mode.flags; base 8272 drivers/gpu/drm/i915/display/intel_display.c mode->clock = pipe_config->base.adjusted_mode.crtc_clock; base 8281 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 8282 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 8318 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { base 8341 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 8377 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 8419 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 8453 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 8538 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 8564 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 8592 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 8594 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(crtc->base.primary); base 8597 drivers/gpu/drm/i915/display/intel_display.c u32 val, base, offset; base 8614 drivers/gpu/drm/i915/display/intel_display.c fb = &intel_fb->base; base 8640 drivers/gpu/drm/i915/display/intel_display.c base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; base 8646 drivers/gpu/drm/i915/display/intel_display.c base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; base 8648 drivers/gpu/drm/i915/display/intel_display.c base = I915_READ(DSPADDR(i9xx_plane)); base 8650 drivers/gpu/drm/i915/display/intel_display.c plane_config->base = base; base 8664 drivers/gpu/drm/i915/display/intel_display.c crtc->base.name, plane->base.name, fb->width, fb->height, base 8665 drivers/gpu/drm/i915/display/intel_display.c fb->format->cpp[0] * 8, base, fb->pitches[0], base 8674 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 8708 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 8750 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 8751 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(crtc->base.primary); base 8752 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 8769 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 8873 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_clock = base 9389 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 9390 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 9417 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) base 9433 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 9434 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 9441 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) base 9452 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 9453 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 9495 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 9535 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 9636 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 9638 drivers/gpu/drm/i915/display/intel_display.c to_intel_atomic_state(crtc_state->base.state); base 9692 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 9710 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 9763 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 9795 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 9797 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(crtc->base.primary); base 9800 drivers/gpu/drm/i915/display/intel_display.c u32 val, base, offset, stride_mult, tiling, alpha; base 9817 drivers/gpu/drm/i915/display/intel_display.c fb = &intel_fb->base; base 9889 drivers/gpu/drm/i915/display/intel_display.c base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000; base 9890 drivers/gpu/drm/i915/display/intel_display.c plane_config->base = base; base 9907 drivers/gpu/drm/i915/display/intel_display.c crtc->base.name, plane->base.name, fb->width, fb->height, base 9908 drivers/gpu/drm/i915/display/intel_display.c fb->format->cpp[0] * 8, base, fb->pitches[0], base 9921 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 9945 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 10052 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 10054 drivers/gpu/drm/i915/display/intel_display.c to_intel_atomic_state(crtc_state->base.state); base 10205 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 10301 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 10354 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 10403 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 10507 drivers/gpu/drm/i915/display/intel_display.c to_i915(plane_state->base.plane->dev); base 10508 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 10510 drivers/gpu/drm/i915/display/intel_display.c u32 base; base 10513 drivers/gpu/drm/i915/display/intel_display.c base = sg_dma_address(obj->mm.pages->sgl); base 10515 drivers/gpu/drm/i915/display/intel_display.c base = intel_plane_ggtt_offset(plane_state); base 10517 drivers/gpu/drm/i915/display/intel_display.c base += plane_state->color_plane[0].offset; base 10521 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.rotation & DRM_MODE_ROTATE_180) base 10522 drivers/gpu/drm/i915/display/intel_display.c base += (plane_state->base.crtc_h * base 10523 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.crtc_w - 1) * fb->format->cpp[0]; base 10525 drivers/gpu/drm/i915/display/intel_display.c return base; base 10530 drivers/gpu/drm/i915/display/intel_display.c int x = plane_state->base.crtc_x; base 10531 drivers/gpu/drm/i915/display/intel_display.c int y = plane_state->base.crtc_y; base 10552 drivers/gpu/drm/i915/display/intel_display.c &plane_state->base.plane->dev->mode_config; base 10553 drivers/gpu/drm/i915/display/intel_display.c int width = plane_state->base.crtc_w; base 10554 drivers/gpu/drm/i915/display/intel_display.c int height = plane_state->base.crtc_h; base 10570 drivers/gpu/drm/i915/display/intel_display.c if (!plane_state->base.visible) base 10573 drivers/gpu/drm/i915/display/intel_display.c src_x = plane_state->base.src_x >> 16; base 10574 drivers/gpu/drm/i915/display/intel_display.c src_y = plane_state->base.src_y >> 16; base 10593 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 10601 drivers/gpu/drm/i915/display/intel_display.c ret = drm_atomic_helper_check_plane_state(&plane_state->base, base 10602 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->base, base 10613 drivers/gpu/drm/i915/display/intel_display.c if (!plane_state->base.visible) base 10651 drivers/gpu/drm/i915/display/intel_display.c int width = plane_state->base.crtc_w; base 10663 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 10677 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.crtc_w, base 10678 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.crtc_h); base 10682 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(plane_state->base.visible && base 10706 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 10707 drivers/gpu/drm/i915/display/intel_display.c u32 cntl = 0, base = 0, pos = 0, size = 0; base 10710 drivers/gpu/drm/i915/display/intel_display.c if (plane_state && plane_state->base.visible) { base 10711 drivers/gpu/drm/i915/display/intel_display.c unsigned int width = plane_state->base.crtc_w; base 10712 drivers/gpu/drm/i915/display/intel_display.c unsigned int height = plane_state->base.crtc_h; base 10719 drivers/gpu/drm/i915/display/intel_display.c base = intel_cursor_base(plane_state); base 10728 drivers/gpu/drm/i915/display/intel_display.c if (plane->cursor.base != base || base 10732 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE_FW(CURBASE(PIPE_A), base); base 10737 drivers/gpu/drm/i915/display/intel_display.c plane->cursor.base = base; base 10756 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 10780 drivers/gpu/drm/i915/display/intel_display.c return plane->base.dev->mode_config.cursor_width * 4; base 10785 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 10786 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 10808 drivers/gpu/drm/i915/display/intel_display.c to_i915(plane_state->base.plane->dev); base 10814 drivers/gpu/drm/i915/display/intel_display.c switch (plane_state->base.crtc_w) { base 10825 drivers/gpu/drm/i915/display/intel_display.c MISSING_CASE(plane_state->base.crtc_w); base 10829 drivers/gpu/drm/i915/display/intel_display.c if (plane_state->base.rotation & DRM_MODE_ROTATE_180) base 10838 drivers/gpu/drm/i915/display/intel_display.c to_i915(plane_state->base.plane->dev); base 10839 drivers/gpu/drm/i915/display/intel_display.c int width = plane_state->base.crtc_w; base 10840 drivers/gpu/drm/i915/display/intel_display.c int height = plane_state->base.crtc_h; base 10862 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.rotation & DRM_MODE_ROTATE_0) { base 10876 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 10877 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 10878 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 10893 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.crtc_w, base 10894 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.crtc_h); base 10898 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(plane_state->base.visible && base 10901 drivers/gpu/drm/i915/display/intel_display.c if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) { base 10903 drivers/gpu/drm/i915/display/intel_display.c fb->pitches[0], plane_state->base.crtc_w); base 10918 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.visible && plane_state->base.crtc_x < 0) { base 10932 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 10934 drivers/gpu/drm/i915/display/intel_display.c u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; base 10937 drivers/gpu/drm/i915/display/intel_display.c if (plane_state && plane_state->base.visible) { base 10941 drivers/gpu/drm/i915/display/intel_display.c if (plane_state->base.crtc_h != plane_state->base.crtc_w) base 10942 drivers/gpu/drm/i915/display/intel_display.c fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1); base 10944 drivers/gpu/drm/i915/display/intel_display.c base = intel_cursor_base(plane_state); base 10973 drivers/gpu/drm/i915/display/intel_display.c if (plane->cursor.base != base || base 10980 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE_FW(CURBASE(pipe), base); base 10982 drivers/gpu/drm/i915/display/intel_display.c plane->cursor.base = base; base 10987 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE_FW(CURBASE(pipe), base); base 11002 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 11054 drivers/gpu/drm/i915/display/intel_display.c return &intel_fb->base; base 11095 drivers/gpu/drm/i915/display/intel_display.c struct drm_encoder *encoder = &intel_encoder->base; base 11106 drivers/gpu/drm/i915/display/intel_display.c connector->base.id, connector->name, base 11107 drivers/gpu/drm/i915/display/intel_display.c encoder->base.id, encoder->name); base 11192 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.active = crtc_state->base.enable = true; base 11197 drivers/gpu/drm/i915/display/intel_display.c ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); base 11250 drivers/gpu/drm/i915/display/intel_display.c struct drm_encoder *encoder = &intel_encoder->base; base 11255 drivers/gpu/drm/i915/display/intel_display.c connector->base.id, connector->name, base 11256 drivers/gpu/drm/i915/display/intel_display.c encoder->base.id, encoder->name); base 11287 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 11395 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 11405 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_clock = base 11414 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 11435 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.crtc = &crtc->base; base 11474 drivers/gpu/drm/i915/display/intel_display.c if (new->base.visible != cur->base.visible) base 11477 drivers/gpu/drm/i915/display/intel_display.c if (!cur->base.fb || !new->base.fb) base 11480 drivers/gpu/drm/i915/display/intel_display.c if (cur->base.fb->modifier != new->base.fb->modifier || base 11481 drivers/gpu/drm/i915/display/intel_display.c cur->base.rotation != new->base.rotation || base 11482 drivers/gpu/drm/i915/display/intel_display.c drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || base 11483 drivers/gpu/drm/i915/display/intel_display.c drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || base 11484 drivers/gpu/drm/i915/display/intel_display.c drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || base 11485 drivers/gpu/drm/i915/display/intel_display.c drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) base 11493 drivers/gpu/drm/i915/display/intel_display.c int src_w = drm_rect_width(&state->base.src) >> 16; base 11494 drivers/gpu/drm/i915/display/intel_display.c int src_h = drm_rect_height(&state->base.src) >> 16; base 11495 drivers/gpu/drm/i915/display/intel_display.c int dst_w = drm_rect_width(&state->base.dst); base 11496 drivers/gpu/drm/i915/display/intel_display.c int dst_h = drm_rect_height(&state->base.dst); base 11506 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 11507 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 11508 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 11510 drivers/gpu/drm/i915/display/intel_display.c bool was_crtc_enabled = old_crtc_state->base.active; base 11511 drivers/gpu/drm/i915/display/intel_display.c bool is_crtc_enabled = crtc_state->base.active; base 11513 drivers/gpu/drm/i915/display/intel_display.c struct drm_framebuffer *fb = plane_state->base.fb; base 11522 drivers/gpu/drm/i915/display/intel_display.c was_visible = old_plane_state->base.visible; base 11523 drivers/gpu/drm/i915/display/intel_display.c visible = plane_state->base.visible; base 11539 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.visible = visible = false; base 11547 drivers/gpu/drm/i915/display/intel_display.c if (fb != old_plane_state->base.fb) base 11554 drivers/gpu/drm/i915/display/intel_display.c crtc->base.base.id, crtc->base.name, base 11555 drivers/gpu/drm/i915/display/intel_display.c plane->base.base.id, plane->base.name, base 11556 drivers/gpu/drm/i915/display/intel_display.c fb ? fb->base.id : -1); base 11559 drivers/gpu/drm/i915/display/intel_display.c plane->base.base.id, plane->base.name, base 11649 drivers/gpu/drm/i915/display/intel_display.c if (connector_state->crtc != &crtc->base) base 11686 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 11687 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 11688 drivers/gpu/drm/i915/display/intel_display.c struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state); base 11705 drivers/gpu/drm/i915/display/intel_display.c if (plane_state->slave && !plane_state->base.visible) { base 11750 drivers/gpu/drm/i915/display/intel_display.c DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name); base 11758 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 11760 drivers/gpu/drm/i915/display/intel_display.c to_intel_atomic_state(new_crtc_state->base.state); base 11860 drivers/gpu/drm/i915/display/intel_display.c if (connector->base.state->crtc) base 11861 drivers/gpu/drm/i915/display/intel_display.c drm_connector_put(&connector->base); base 11863 drivers/gpu/drm/i915/display/intel_display.c if (connector->base.encoder) { base 11864 drivers/gpu/drm/i915/display/intel_display.c connector->base.state->best_encoder = base 11865 drivers/gpu/drm/i915/display/intel_display.c connector->base.encoder; base 11866 drivers/gpu/drm/i915/display/intel_display.c connector->base.state->crtc = base 11867 drivers/gpu/drm/i915/display/intel_display.c connector->base.encoder->crtc; base 11869 drivers/gpu/drm/i915/display/intel_display.c drm_connector_get(&connector->base); base 11871 drivers/gpu/drm/i915/display/intel_display.c connector->base.state->best_encoder = NULL; base 11872 drivers/gpu/drm/i915/display/intel_display.c connector->base.state->crtc = NULL; base 11906 drivers/gpu/drm/i915/display/intel_display.c connector->base.id, connector->name, base 11920 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 11921 drivers/gpu/drm/i915/display/intel_display.c struct drm_atomic_state *state = pipe_config->base.state; base 11940 drivers/gpu/drm/i915/display/intel_display.c if (connector_state->crtc != &crtc->base) base 12046 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 12047 drivers/gpu/drm/i915/display/intel_display.c const struct drm_framebuffer *fb = plane_state->base.fb; base 12052 drivers/gpu/drm/i915/display/intel_display.c plane->base.base.id, plane->base.name, base 12053 drivers/gpu/drm/i915/display/intel_display.c yesno(plane_state->base.visible)); base 12058 drivers/gpu/drm/i915/display/intel_display.c plane->base.base.id, plane->base.name, base 12059 drivers/gpu/drm/i915/display/intel_display.c fb->base.id, fb->width, fb->height, base 12061 drivers/gpu/drm/i915/display/intel_display.c yesno(plane_state->base.visible)); base 12063 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.rotation, plane_state->scaler_id); base 12064 drivers/gpu/drm/i915/display/intel_display.c if (plane_state->base.visible) base 12066 drivers/gpu/drm/i915/display/intel_display.c DRM_RECT_FP_ARG(&plane_state->base.src), base 12067 drivers/gpu/drm/i915/display/intel_display.c DRM_RECT_ARG(&plane_state->base.dst)); base 12074 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 12075 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 12082 drivers/gpu/drm/i915/display/intel_display.c crtc->base.base.id, crtc->base.name, base 12083 drivers/gpu/drm/i915/display/intel_display.c yesno(pipe_config->base.enable), context); base 12085 drivers/gpu/drm/i915/display/intel_display.c if (!pipe_config->base.enable) base 12090 drivers/gpu/drm/i915/display/intel_display.c yesno(pipe_config->base.active), base 12130 drivers/gpu/drm/i915/display/intel_display.c drm_mode_debug_printmodeline(&pipe_config->base.mode); base 12132 drivers/gpu/drm/i915/display/intel_display.c drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); base 12133 drivers/gpu/drm/i915/display/intel_display.c intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); base 12174 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = state->base.dev; base 12192 drivers/gpu/drm/i915/display/intel_display.c drm_atomic_get_new_connector_state(&state->base, base 12242 drivers/gpu/drm/i915/display/intel_display.c to_i915(crtc_state->base.crtc->dev); base 12265 drivers/gpu/drm/i915/display/intel_display.c BUILD_BUG_ON(offsetof(struct intel_crtc_state, base)); base 12266 drivers/gpu/drm/i915/display/intel_display.c memcpy(&crtc_state->base + 1, &saved_state->base + 1, base 12267 drivers/gpu/drm/i915/display/intel_display.c sizeof(*crtc_state) - sizeof(crtc_state->base)); base 12276 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = pipe_config->base.crtc; base 12277 drivers/gpu/drm/i915/display/intel_display.c struct drm_atomic_state *state = pipe_config->base.state; base 12297 drivers/gpu/drm/i915/display/intel_display.c if (!(pipe_config->base.adjusted_mode.flags & base 12299 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; base 12301 drivers/gpu/drm/i915/display/intel_display.c if (!(pipe_config->base.adjusted_mode.flags & base 12303 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; base 12320 drivers/gpu/drm/i915/display/intel_display.c drm_mode_get_hv_timing(&pipe_config->base.mode, base 12353 drivers/gpu/drm/i915/display/intel_display.c drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, base 12378 drivers/gpu/drm/i915/display/intel_display.c pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock base 12542 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(current_config->base.crtc->dev); base 12545 drivers/gpu/drm/i915/display/intel_display.c (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) && base 12546 drivers/gpu/drm/i915/display/intel_display.c !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED); base 12717 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); base 12718 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); base 12719 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); base 12720 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); base 12721 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); base 12722 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); base 12724 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); base 12725 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); base 12726 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); base 12727 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); base 12728 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); base 12729 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); base 12744 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, base 12748 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, base 12750 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, base 12752 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, base 12754 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, base 12833 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); base 12863 drivers/gpu/drm/i915/display/intel_display.c int dotclock = pipe_config->base.adjusted_mode.crtc_clock; base 12878 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 12891 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active) base 13022 drivers/gpu/drm/i915/display/intel_display.c for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) { base 13026 drivers/gpu/drm/i915/display/intel_display.c if (new_conn_state->crtc != &crtc->base) base 13052 drivers/gpu/drm/i915/display/intel_display.c encoder->base.base.id, base 13053 drivers/gpu/drm/i915/display/intel_display.c encoder->base.name); base 13055 drivers/gpu/drm/i915/display/intel_display.c for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, base 13057 drivers/gpu/drm/i915/display/intel_display.c if (old_conn_state->best_encoder == &encoder->base) base 13060 drivers/gpu/drm/i915/display/intel_display.c if (new_conn_state->best_encoder != &encoder->base) base 13065 drivers/gpu/drm/i915/display/intel_display.c encoder->base.crtc, base 13072 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(!!encoder->base.crtc != enabled, base 13075 drivers/gpu/drm/i915/display/intel_display.c !!encoder->base.crtc, enabled); base 13077 drivers/gpu/drm/i915/display/intel_display.c if (!encoder->base.crtc) { base 13093 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 13100 drivers/gpu/drm/i915/display/intel_display.c state = old_crtc_state->base.state; base 13101 drivers/gpu/drm/i915/display/intel_display.c __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->base); base 13104 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.crtc = &crtc->base; base 13105 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.state = state; base 13107 drivers/gpu/drm/i915/display/intel_display.c DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name); base 13113 drivers/gpu/drm/i915/display/intel_display.c active = new_crtc_state->base.active; base 13115 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(new_crtc_state->base.active != active, base 13117 drivers/gpu/drm/i915/display/intel_display.c "(expected %i, found %i)\n", new_crtc_state->base.active, active); base 13119 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(crtc->active != new_crtc_state->base.active, base 13121 drivers/gpu/drm/i915/display/intel_display.c "(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active); base 13123 drivers/gpu/drm/i915/display/intel_display.c for_each_encoder_on_crtc(dev, &crtc->base, encoder) { base 13127 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(active != new_crtc_state->base.active, base 13129 drivers/gpu/drm/i915/display/intel_display.c encoder->base.base.id, active, new_crtc_state->base.active); base 13141 drivers/gpu/drm/i915/display/intel_display.c if (!new_crtc_state->base.active) base 13164 drivers/gpu/drm/i915/display/intel_display.c plane_state->base.visible); base 13201 drivers/gpu/drm/i915/display/intel_display.c crtc_mask = drm_crtc_mask(&crtc->base); base 13203 drivers/gpu/drm/i915/display/intel_display.c if (new_crtc_state->base.active) base 13206 drivers/gpu/drm/i915/display/intel_display.c pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask); base 13210 drivers/gpu/drm/i915/display/intel_display.c pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask); base 13227 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 13234 drivers/gpu/drm/i915/display/intel_display.c unsigned int crtc_mask = drm_crtc_mask(&crtc->base); base 13239 drivers/gpu/drm/i915/display/intel_display.c pipe_name(drm_crtc_index(&crtc->base))); base 13242 drivers/gpu/drm/i915/display/intel_display.c pipe_name(drm_crtc_index(&crtc->base))); base 13281 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 13282 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 13312 drivers/gpu/drm/i915/display/intel_display.c const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; base 13329 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 13362 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.active || base 13380 drivers/gpu/drm/i915/display/intel_display.c for_each_intel_crtc(state->base.dev, crtc) { base 13381 drivers/gpu/drm/i915/display/intel_display.c crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); base 13387 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.active || base 13408 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 13415 drivers/gpu/drm/i915/display/intel_display.c crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); base 13425 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 13436 drivers/gpu/drm/i915/display/intel_display.c crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); base 13440 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.active || needs_modeset(crtc_state)) base 13443 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.mode_changed = true; base 13445 drivers/gpu/drm/i915/display/intel_display.c ret = drm_atomic_add_affected_connectors(&state->base, base 13446 drivers/gpu/drm/i915/display/intel_display.c &crtc->base); base 13450 drivers/gpu/drm/i915/display/intel_display.c ret = drm_atomic_add_affected_planes(&state->base, base 13451 drivers/gpu/drm/i915/display/intel_display.c &crtc->base); base 13461 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 13483 drivers/gpu/drm/i915/display/intel_display.c if (new_crtc_state->base.active) base 13488 drivers/gpu/drm/i915/display/intel_display.c if (old_crtc_state->base.active != new_crtc_state->base.active) base 13489 drivers/gpu/drm/i915/display/intel_display.c state->active_pipe_changes |= drm_crtc_mask(&crtc->base); base 13573 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = state->base.dev; base 13589 drivers/gpu/drm/i915/display/intel_display.c new_crtc_state->base.mode_changed = false; base 13624 drivers/gpu/drm/i915/display/intel_display.c if (new_crtc_state->base.mode.private_flags != base 13625 drivers/gpu/drm/i915/display/intel_display.c old_crtc_state->base.mode.private_flags) base 13626 drivers/gpu/drm/i915/display/intel_display.c new_crtc_state->base.mode_changed = true; base 13629 drivers/gpu/drm/i915/display/intel_display.c ret = drm_atomic_helper_check_modeset(dev, &state->base); base 13638 drivers/gpu/drm/i915/display/intel_display.c if (!new_crtc_state->base.enable) { base 13653 drivers/gpu/drm/i915/display/intel_display.c ret = drm_dp_mst_atomic_check(&state->base); base 13669 drivers/gpu/drm/i915/display/intel_display.c ret = drm_atomic_helper_check_planes(dev, &state->base); base 13712 drivers/gpu/drm/i915/display/intel_display.c return drm_atomic_helper_prepare_planes(state->base.dev, base 13713 drivers/gpu/drm/i915/display/intel_display.c &state->base); base 13718 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 13719 drivers/gpu/drm/i915/display/intel_display.c struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)]; base 13722 drivers/gpu/drm/i915/display/intel_display.c return (u32)drm_crtc_accurate_vblank_count(&crtc->base); base 13724 drivers/gpu/drm/i915/display/intel_display.c return crtc->base.funcs->get_vblank_counter(&crtc->base); base 13732 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = state->base.dev; base 13737 drivers/gpu/drm/i915/display/intel_display.c to_intel_plane(crtc->base.primary)); base 13747 drivers/gpu/drm/i915/display/intel_display.c (new_crtc_state->base.color_mgmt_changed || base 13779 drivers/gpu/drm/i915/display/intel_display.c if (!new_crtc_state->base.active) base 13789 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 13802 drivers/gpu/drm/i915/display/intel_display.c if (new_crtc_state->base.active) base 13820 drivers/gpu/drm/i915/display/intel_display.c unsigned int cmask = drm_crtc_mask(&crtc->base); base 13824 drivers/gpu/drm/i915/display/intel_display.c if (updated & cmask || !new_crtc_state->base.active) base 13843 drivers/gpu/drm/i915/display/intel_display.c !new_crtc_state->base.active_changed && base 13869 drivers/gpu/drm/i915/display/intel_display.c drm_atomic_state_put(&state->base); base 13883 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); base 13922 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = state->base.dev; base 13932 drivers/gpu/drm/i915/display/intel_display.c drm_atomic_helper_wait_for_dependencies(&state->base); base 13950 drivers/gpu/drm/i915/display/intel_display.c if (old_crtc_state->base.active) { base 13972 drivers/gpu/drm/i915/display/intel_display.c if (!new_crtc_state->base.active && base 13985 drivers/gpu/drm/i915/display/intel_display.c drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); base 14007 drivers/gpu/drm/i915/display/intel_display.c if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) { base 14009 drivers/gpu/drm/i915/display/intel_display.c drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event); base 14012 drivers/gpu/drm/i915/display/intel_display.c new_crtc_state->base.event = NULL; base 14040 drivers/gpu/drm/i915/display/intel_display.c drm_atomic_helper_wait_for_flip_done(dev, &state->base); base 14043 drivers/gpu/drm/i915/display/intel_display.c if (new_crtc_state->base.active && base 14046 drivers/gpu/drm/i915/display/intel_display.c (new_crtc_state->base.color_mgmt_changed || base 14079 drivers/gpu/drm/i915/display/intel_display.c drm_atomic_helper_commit_hw_done(&state->base); base 14101 drivers/gpu/drm/i915/display/intel_display.c INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); base 14102 drivers/gpu/drm/i915/display/intel_display.c queue_work(system_highpri_wq, &state->base.commit_work); base 14108 drivers/gpu/drm/i915/display/intel_display.c container_of(work, struct intel_atomic_state, base.commit_work); base 14127 drivers/gpu/drm/i915/display/intel_display.c &to_i915(state->base.dev)->atomic_helper; base 14146 drivers/gpu/drm/i915/display/intel_display.c intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->base.fb), base 14147 drivers/gpu/drm/i915/display/intel_display.c to_intel_frontbuffer(new_plane_state->base.fb), base 14161 drivers/gpu/drm/i915/display/intel_display.c drm_atomic_state_get(&state->base); base 14182 drivers/gpu/drm/i915/display/intel_display.c if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) { base 14190 drivers/gpu/drm/i915/display/intel_display.c state->base.legacy_cursor_update = false; base 14201 drivers/gpu/drm/i915/display/intel_display.c ret = drm_atomic_helper_setup_commit(&state->base, nonblock); base 14203 drivers/gpu/drm/i915/display/intel_display.c ret = drm_atomic_helper_swap_state(&state->base, true); base 14208 drivers/gpu/drm/i915/display/intel_display.c drm_atomic_helper_cleanup_planes(dev, &state->base); base 14227 drivers/gpu/drm/i915/display/intel_display.c drm_atomic_state_get(&state->base); base 14228 drivers/gpu/drm/i915/display/intel_display.c INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); base 14232 drivers/gpu/drm/i915/display/intel_display.c queue_work(dev_priv->modeset_wq, &state->base.commit_work); base 14234 drivers/gpu/drm/i915/display/intel_display.c queue_work(system_unbound_wq, &state->base.commit_work); base 14304 drivers/gpu/drm/i915/display/intel_display.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 14305 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 14306 drivers/gpu/drm/i915/display/intel_display.c struct drm_framebuffer *fb = plane_state->base.fb; base 14394 drivers/gpu/drm/i915/display/intel_display.c old_obj->base.resv, NULL, base 14438 drivers/gpu/drm/i915/display/intel_display.c obj->base.resv, NULL, base 14444 drivers/gpu/drm/i915/display/intel_display.c fence = dma_resv_get_excl_rcu(obj->base.resv); base 14501 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 14502 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 14506 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.enable) base 14509 drivers/gpu/drm/i915/display/intel_display.c crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; base 14510 drivers/gpu/drm/i915/display/intel_display.c max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; base 14535 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 14548 drivers/gpu/drm/i915/display/intel_display.c if (new_crtc_state->base.color_mgmt_changed || base 14569 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 14594 drivers/gpu/drm/i915/display/intel_display.c old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED) base 14706 drivers/gpu/drm/i915/display/intel_display.c if (!crtc_state->base.active || needs_modeset(crtc_state) || base 14800 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_destroy_state(crtc, &new_crtc_state->base); base 14907 drivers/gpu/drm/i915/display/intel_display.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, base 14913 drivers/gpu/drm/i915/display/intel_display.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, base 14934 drivers/gpu/drm/i915/display/intel_display.c drm_plane_create_rotation_property(&plane->base, base 14938 drivers/gpu/drm/i915/display/intel_display.c drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); base 14979 drivers/gpu/drm/i915/display/intel_display.c cursor->cursor.base = ~0; base 14987 drivers/gpu/drm/i915/display/intel_display.c ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, base 14998 drivers/gpu/drm/i915/display/intel_display.c drm_plane_create_rotation_property(&cursor->base, base 15003 drivers/gpu/drm/i915/display/intel_display.c drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); base 15018 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 15120 drivers/gpu/drm/i915/display/intel_display.c __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->base); base 15167 drivers/gpu/drm/i915/display/intel_display.c ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, base 15168 drivers/gpu/drm/i915/display/intel_display.c &primary->base, &cursor->base, base 15190 drivers/gpu/drm/i915/display/intel_display.c drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); base 15194 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); base 15228 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = encoder->base.dev; base 15538 drivers/gpu/drm/i915/display/intel_display.c encoder->base.possible_crtcs = encoder->crtc_mask; base 15539 drivers/gpu/drm/i915/display/intel_display.c encoder->base.possible_clones = base 15569 drivers/gpu/drm/i915/display/intel_display.c return drm_gem_handle_create(file, &obj->base, handle); base 15596 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); base 15597 drivers/gpu/drm/i915/display/intel_display.c struct drm_framebuffer *fb = &intel_fb->base; base 15708 drivers/gpu/drm/i915/display/intel_display.c fb->obj[i] = &obj->base; base 16046 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; base 16387 drivers/gpu/drm/i915/display/intel_display.c to_intel_plane(crtc->base.primary); base 16398 drivers/gpu/drm/i915/display/intel_display.c plane->base.base.id, plane->base.name); base 16407 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 16410 drivers/gpu/drm/i915/display/intel_display.c for_each_encoder_on_crtc(dev, &crtc->base, encoder) base 16418 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = encoder->base.dev; base 16421 drivers/gpu/drm/i915/display/intel_display.c for_each_connector_on_encoder(dev, &encoder->base, connector) base 16437 drivers/gpu/drm/i915/display/intel_display.c struct drm_device *dev = crtc->base.dev; base 16439 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); base 16450 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active) { base 16456 drivers/gpu/drm/i915/display/intel_display.c to_intel_plane_state(plane->base.state); base 16458 drivers/gpu/drm/i915/display/intel_display.c if (plane_state->base.visible && base 16459 drivers/gpu/drm/i915/display/intel_display.c plane->base.type != DRM_PLANE_TYPE_PRIMARY) base 16475 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active && !intel_crtc_has_encoders(crtc)) base 16476 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_disable_noatomic(&crtc->base, ctx); base 16478 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active || HAS_GMCH(dev_priv)) { base 16509 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 16522 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.active && base 16529 drivers/gpu/drm/i915/display/intel_display.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 16531 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); base 16533 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc_state(crtc->base.state) : NULL; base 16539 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.active; base 16550 drivers/gpu/drm/i915/display/intel_display.c encoder->base.base.id, base 16551 drivers/gpu/drm/i915/display/intel_display.c encoder->base.name); base 16560 drivers/gpu/drm/i915/display/intel_display.c encoder->base.base.id, base 16561 drivers/gpu/drm/i915/display/intel_display.c encoder->base.name); base 16564 drivers/gpu/drm/i915/display/intel_display.c best_encoder = connector->base.state->best_encoder; base 16565 drivers/gpu/drm/i915/display/intel_display.c connector->base.state->best_encoder = &encoder->base; base 16569 drivers/gpu/drm/i915/display/intel_display.c connector->base.state); base 16572 drivers/gpu/drm/i915/display/intel_display.c connector->base.state); base 16574 drivers/gpu/drm/i915/display/intel_display.c connector->base.state->best_encoder = best_encoder; base 16576 drivers/gpu/drm/i915/display/intel_display.c encoder->base.crtc = NULL; base 16583 drivers/gpu/drm/i915/display/intel_display.c connector->base.dpms = DRM_MODE_DPMS_OFF; base 16584 drivers/gpu/drm/i915/display/intel_display.c connector->base.encoder = NULL; base 16635 drivers/gpu/drm/i915/display/intel_display.c to_intel_plane_state(plane->base.state); base 16643 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(crtc->base.state); base 16648 drivers/gpu/drm/i915/display/intel_display.c plane->base.base.id, plane->base.name, base 16654 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc_state(crtc->base.state); base 16674 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc_state(crtc->base.state); base 16676 drivers/gpu/drm/i915/display/intel_display.c __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); base 16678 drivers/gpu/drm/i915/display/intel_display.c __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base); base 16680 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.active = crtc_state->base.enable = base 16683 drivers/gpu/drm/i915/display/intel_display.c crtc->base.enabled = crtc_state->base.enable; base 16684 drivers/gpu/drm/i915/display/intel_display.c crtc->active = crtc_state->base.active; base 16686 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active) base 16690 drivers/gpu/drm/i915/display/intel_display.c crtc->base.base.id, crtc->base.name, base 16691 drivers/gpu/drm/i915/display/intel_display.c enableddisabled(crtc_state->base.active)); base 16711 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc_state(crtc->base.state); base 16713 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active && base 16730 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(crtc->base.state); base 16732 drivers/gpu/drm/i915/display/intel_display.c encoder->base.crtc = &crtc->base; base 16735 drivers/gpu/drm/i915/display/intel_display.c encoder->base.crtc = NULL; base 16739 drivers/gpu/drm/i915/display/intel_display.c encoder->base.base.id, encoder->base.name, base 16740 drivers/gpu/drm/i915/display/intel_display.c enableddisabled(encoder->base.crtc), base 16747 drivers/gpu/drm/i915/display/intel_display.c connector->base.dpms = DRM_MODE_DPMS_ON; base 16750 drivers/gpu/drm/i915/display/intel_display.c connector->base.encoder = &encoder->base; base 16752 drivers/gpu/drm/i915/display/intel_display.c if (encoder->base.crtc && base 16753 drivers/gpu/drm/i915/display/intel_display.c encoder->base.crtc->state->active) { base 16759 drivers/gpu/drm/i915/display/intel_display.c encoder->base.crtc->state->connector_mask |= base 16760 drivers/gpu/drm/i915/display/intel_display.c drm_connector_mask(&connector->base); base 16761 drivers/gpu/drm/i915/display/intel_display.c encoder->base.crtc->state->encoder_mask |= base 16762 drivers/gpu/drm/i915/display/intel_display.c drm_encoder_mask(&encoder->base); base 16766 drivers/gpu/drm/i915/display/intel_display.c connector->base.dpms = DRM_MODE_DPMS_OFF; base 16767 drivers/gpu/drm/i915/display/intel_display.c connector->base.encoder = NULL; base 16770 drivers/gpu/drm/i915/display/intel_display.c connector->base.base.id, connector->base.name, base 16771 drivers/gpu/drm/i915/display/intel_display.c enableddisabled(connector->base.encoder)); base 16779 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc_state(crtc->base.state); base 16783 drivers/gpu/drm/i915/display/intel_display.c memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); base 16784 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active) { base 16785 drivers/gpu/drm/i915/display/intel_display.c intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); base 16786 drivers/gpu/drm/i915/display/intel_display.c crtc->base.mode.hdisplay = crtc_state->pipe_src_w; base 16787 drivers/gpu/drm/i915/display/intel_display.c crtc->base.mode.vdisplay = crtc_state->pipe_src_h; base 16788 drivers/gpu/drm/i915/display/intel_display.c intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); base 16789 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); base 16800 drivers/gpu/drm/i915/display/intel_display.c crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; base 16810 drivers/gpu/drm/i915/display/intel_display.c drm_calc_timestamping_constants(&crtc->base, base 16811 drivers/gpu/drm/i915/display/intel_display.c &crtc_state->base.adjusted_mode); base 16821 drivers/gpu/drm/i915/display/intel_display.c to_intel_plane_state(plane->base.state); base 16827 drivers/gpu/drm/i915/display/intel_display.c if (plane_state->base.visible) base 16853 drivers/gpu/drm/i915/display/intel_display.c if (!encoder->base.crtc) base 16856 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(encoder->base.crtc->state); base 16968 drivers/gpu/drm/i915/display/intel_display.c intel_tc_port_sanitize(enc_to_dig_port(&encoder->base)); base 16981 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(crtc->base.state); base 16983 drivers/gpu/drm/i915/display/intel_display.c drm_crtc_vblank_reset(&crtc->base); base 16985 drivers/gpu/drm/i915/display/intel_display.c if (crtc_state->base.active) base 16995 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(crtc->base.state); base 17030 drivers/gpu/drm/i915/display/intel_display.c crtc_state = to_intel_crtc_state(crtc->base.state); base 17176 drivers/gpu/drm/i915/display/intel_display.c u32 base; base 17246 drivers/gpu/drm/i915/display/intel_display.c error->cursor[i].base = I915_READ(CURBASE(i)); base 17334 drivers/gpu/drm/i915/display/intel_display.c err_printf(m, " BASE: %08x\n", error->cursor[i].base); base 326 drivers/gpu/drm/i915/display/intel_display.h base.head) base 331 drivers/gpu/drm/i915/display/intel_display.h base.head) \ base 333 drivers/gpu/drm/i915/display/intel_display.h drm_plane_mask(&intel_plane->base))) base 338 drivers/gpu/drm/i915/display/intel_display.h base.head) \ base 344 drivers/gpu/drm/i915/display/intel_display.h base.head) base 349 drivers/gpu/drm/i915/display/intel_display.h base.head) \ base 350 drivers/gpu/drm/i915/display/intel_display.h for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) base 355 drivers/gpu/drm/i915/display/intel_display.h base.head) base 365 drivers/gpu/drm/i915/display/intel_display.h list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ base 366 drivers/gpu/drm/i915/display/intel_display.h for_each_if((intel_encoder)->base.crtc == (__crtc)) base 369 drivers/gpu/drm/i915/display/intel_display.h list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ base 370 drivers/gpu/drm/i915/display/intel_display.h for_each_if((intel_connector)->base.encoder == (__encoder)) base 374 drivers/gpu/drm/i915/display/intel_display.h (__i) < (__state)->base.dev->mode_config.num_total_plane && \ base 375 drivers/gpu/drm/i915/display/intel_display.h ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ base 376 drivers/gpu/drm/i915/display/intel_display.h (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ base 382 drivers/gpu/drm/i915/display/intel_display.h (__i) < (__state)->base.dev->mode_config.num_total_plane && \ base 383 drivers/gpu/drm/i915/display/intel_display.h ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ base 384 drivers/gpu/drm/i915/display/intel_display.h (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ base 390 drivers/gpu/drm/i915/display/intel_display.h (__i) < (__state)->base.dev->mode_config.num_crtc && \ base 391 drivers/gpu/drm/i915/display/intel_display.h ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ base 392 drivers/gpu/drm/i915/display/intel_display.h (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ base 398 drivers/gpu/drm/i915/display/intel_display.h (__i) < (__state)->base.dev->mode_config.num_total_plane && \ base 399 drivers/gpu/drm/i915/display/intel_display.h ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ base 400 drivers/gpu/drm/i915/display/intel_display.h (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ base 401 drivers/gpu/drm/i915/display/intel_display.h (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ base 407 drivers/gpu/drm/i915/display/intel_display.h (__i) < (__state)->base.dev->mode_config.num_crtc && \ base 408 drivers/gpu/drm/i915/display/intel_display.h ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ base 409 drivers/gpu/drm/i915/display/intel_display.h (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ base 410 drivers/gpu/drm/i915/display/intel_display.h (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ base 554 drivers/gpu/drm/i915/display/intel_display_power.c dig_port = enc_to_dig_port(&encoder->base); base 1208 drivers/gpu/drm/i915/display/intel_display_power.c intel_crt_reset(&encoder->base); base 1581 drivers/gpu/drm/i915/display/intel_display_power.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1583 drivers/gpu/drm/i915/display/intel_display_power.c enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); base 1584 drivers/gpu/drm/i915/display/intel_display_power.c enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); base 86 drivers/gpu/drm/i915/display/intel_display_types.h struct drm_framebuffer base; base 127 drivers/gpu/drm/i915/display/intel_display_types.h struct drm_encoder base; base 394 drivers/gpu/drm/i915/display/intel_display_types.h struct drm_connector base; base 429 drivers/gpu/drm/i915/display/intel_display_types.h struct drm_connector_state base; base 435 drivers/gpu/drm/i915/display/intel_display_types.h #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) base 450 drivers/gpu/drm/i915/display/intel_display_types.h struct drm_atomic_state base; base 511 drivers/gpu/drm/i915/display/intel_display_types.h struct drm_plane_state base; base 581 drivers/gpu/drm/i915/display/intel_display_types.h u32 base; base 745 drivers/gpu/drm/i915/display/intel_display_types.h struct drm_crtc_state base; base 991 drivers/gpu/drm/i915/display/intel_display_types.h struct drm_crtc base; base 1033 drivers/gpu/drm/i915/display/intel_display_types.h struct drm_plane base; base 1042 drivers/gpu/drm/i915/display/intel_display_types.h u32 base, cntl, size; base 1086 drivers/gpu/drm/i915/display/intel_display_types.h #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) base 1087 drivers/gpu/drm/i915/display/intel_display_types.h #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) base 1088 drivers/gpu/drm/i915/display/intel_display_types.h #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) base 1089 drivers/gpu/drm/i915/display/intel_display_types.h #define to_intel_connector(x) container_of(x, struct intel_connector, base) base 1090 drivers/gpu/drm/i915/display/intel_display_types.h #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) base 1091 drivers/gpu/drm/i915/display/intel_display_types.h #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) base 1092 drivers/gpu/drm/i915/display/intel_display_types.h #define to_intel_plane(x) container_of(x, struct intel_plane, base) base 1093 drivers/gpu/drm/i915/display/intel_display_types.h #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) base 1255 drivers/gpu/drm/i915/display/intel_display_types.h struct intel_encoder base; base 1291 drivers/gpu/drm/i915/display/intel_display_types.h struct intel_encoder base; base 1300 drivers/gpu/drm/i915/display/intel_display_types.h switch (dport->base.port) { base 1314 drivers/gpu/drm/i915/display/intel_display_types.h switch (dport->base.port) { base 1381 drivers/gpu/drm/i915/display/intel_display_types.h base.base); base 1389 drivers/gpu/drm/i915/display/intel_display_types.h return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base); base 1395 drivers/gpu/drm/i915/display/intel_display_types.h return container_of(encoder, struct intel_dp_mst_encoder, base.base); base 1411 drivers/gpu/drm/i915/display/intel_display_types.h return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg); base 1438 drivers/gpu/drm/i915/display/intel_display_types.h return to_i915(dp_to_dig_port(intel_dp)->base.base.dev); base 1452 drivers/gpu/drm/i915/display/intel_display_types.h drm_atomic_get_plane_state(&state->base, &plane->base); base 1464 drivers/gpu/drm/i915/display/intel_display_types.h return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base, base 1465 drivers/gpu/drm/i915/display/intel_display_types.h &plane->base)); base 1472 drivers/gpu/drm/i915/display/intel_display_types.h return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, base 1473 drivers/gpu/drm/i915/display/intel_display_types.h &plane->base)); base 1480 drivers/gpu/drm/i915/display/intel_display_types.h return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, base 1481 drivers/gpu/drm/i915/display/intel_display_types.h &crtc->base)); base 1488 drivers/gpu/drm/i915/display/intel_display_types.h return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, base 1489 drivers/gpu/drm/i915/display/intel_display_types.h &crtc->base)); base 151 drivers/gpu/drm/i915/display/intel_dp.c return intel_dig_port->base.type == INTEL_OUTPUT_EDP; base 156 drivers/gpu/drm/i915/display/intel_dp.c return enc_to_intel_dp(&intel_attached_encoder(connector)->base); base 255 drivers/gpu/drm/i915/display/intel_dp.c struct intel_encoder *encoder = &intel_dig_port->base; base 256 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 277 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); base 278 drivers/gpu/drm/i915/display/intel_dp.c enum port port = dig_port->base.port; base 300 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); base 301 drivers/gpu/drm/i915/display/intel_dp.c enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); base 331 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); base 333 drivers/gpu/drm/i915/display/intel_dp.c &dev_priv->vbt.ddi_port_info[dig_port->base.port]; base 736 drivers/gpu/drm/i915/display/intel_dp.c pipe_name(pipe), port_name(intel_dig_port->base.port))) base 740 drivers/gpu/drm/i915/display/intel_dp.c pipe_name(pipe), port_name(intel_dig_port->base.port)); base 806 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 860 drivers/gpu/drm/i915/display/intel_dp.c port_name(intel_dig_port->base.port)); base 949 drivers/gpu/drm/i915/display/intel_dp.c enum port port = intel_dig_port->base.port; base 999 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 1230 drivers/gpu/drm/i915/display/intel_dp.c to_i915(intel_dig_port->base.base.dev); base 1260 drivers/gpu/drm/i915/display/intel_dp.c to_i915(intel_dig_port->base.base.dev); base 1261 drivers/gpu/drm/i915/display/intel_dp.c enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); base 1289 drivers/gpu/drm/i915/display/intel_dp.c to_i915(intel_dig_port->base.base.dev); base 1291 drivers/gpu/drm/i915/display/intel_dp.c enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); base 1677 drivers/gpu/drm/i915/display/intel_dp.c struct intel_encoder *encoder = &dig_port->base; base 1730 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1882 drivers/gpu/drm/i915/display/intel_dp.c if (intel_connector->base.display_info.bpc == 0 && base 1948 drivers/gpu/drm/i915/display/intel_dp.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 2001 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); base 2002 drivers/gpu/drm/i915/display/intel_dp.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 2106 drivers/gpu/drm/i915/display/intel_dp.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 2107 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 2194 drivers/gpu/drm/i915/display/intel_dp.c &crtc_state->base.adjusted_mode; base 2195 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 2223 drivers/gpu/drm/i915/display/intel_dp.c &crtc_state->base.adjusted_mode; base 2245 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2246 drivers/gpu/drm/i915/display/intel_dp.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 2247 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 2248 drivers/gpu/drm/i915/display/intel_dp.c struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base); base 2250 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); base 2263 drivers/gpu/drm/i915/display/intel_dp.c lspcon_ycbcr420_config(&intel_connector->base, pipe_config); base 2265 drivers/gpu/drm/i915/display/intel_dp.c ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base, base 2358 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2359 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 2361 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 2362 drivers/gpu/drm/i915/display/intel_dp.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 2571 drivers/gpu/drm/i915/display/intel_dp.c port_name(intel_dig_port->base.port)); base 2591 drivers/gpu/drm/i915/display/intel_dp.c port_name(intel_dig_port->base.port)); base 2617 drivers/gpu/drm/i915/display/intel_dp.c port_name(dp_to_dig_port(intel_dp)->base.port)); base 2636 drivers/gpu/drm/i915/display/intel_dp.c port_name(intel_dig_port->base.port)); base 2699 drivers/gpu/drm/i915/display/intel_dp.c port_name(dp_to_dig_port(intel_dp)->base.port)); base 2721 drivers/gpu/drm/i915/display/intel_dp.c port_name(dp_to_dig_port(intel_dp)->base.port)); base 2725 drivers/gpu/drm/i915/display/intel_dp.c port_name(dp_to_dig_port(intel_dp)->base.port))) base 2781 drivers/gpu/drm/i915/display/intel_dp.c port_name(dig_port->base.port)); base 2784 drivers/gpu/drm/i915/display/intel_dp.c port_name(dig_port->base.port)); base 2903 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = intel_attached_dp(&connector->base); base 2925 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); base 2930 drivers/gpu/drm/i915/display/intel_dp.c port_name(dig_port->base.port), base 2949 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 2950 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 2989 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 2990 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 3124 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3125 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3145 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3146 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3149 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 3184 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->base.adjusted_mode.flags |= flags; base 3201 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->base.adjusted_mode.crtc_clock = base 3230 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3264 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3291 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3310 drivers/gpu/drm/i915/display/intel_dp.c enum port port = intel_dig_port->base.port; base 3414 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3415 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3416 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 3475 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3488 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); base 3509 drivers/gpu/drm/i915/display/intel_dp.c pipe_name(pipe), port_name(intel_dig_port->base.port)); base 3524 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3545 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 3546 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 3547 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 3647 drivers/gpu/drm/i915/display/intel_dp.c struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; base 3666 drivers/gpu/drm/i915/display/intel_dp.c struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; base 3710 drivers/gpu/drm/i915/display/intel_dp.c struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; base 3796 drivers/gpu/drm/i915/display/intel_dp.c struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; base 3979 drivers/gpu/drm/i915/display/intel_dp.c enum port port = intel_dig_port->base.port; base 4024 drivers/gpu/drm/i915/display/intel_dp.c to_i915(intel_dig_port->base.base.dev); base 4036 drivers/gpu/drm/i915/display/intel_dp.c enum port port = intel_dig_port->base.port; base 4066 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 4067 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 4068 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 4231 drivers/gpu/drm/i915/display/intel_dp.c to_i915(dp_to_dig_port(intel_dp)->base.base.dev); base 4396 drivers/gpu/drm/i915/display/intel_dp.c &dp_to_dig_port(intel_dp)->base; base 4498 drivers/gpu/drm/i915/display/intel_dp.c intel_dig_port->write_infoframe(&intel_dig_port->base, base 4613 drivers/gpu/drm/i915/display/intel_dp.c struct drm_connector *connector = &intel_connector->base; base 4796 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 4797 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 4806 drivers/gpu/drm/i915/display/intel_dp.c if (!connector || connector->base.status != connector_status_connected) base 4814 drivers/gpu/drm/i915/display/intel_dp.c conn_state = connector->base.state; base 4820 drivers/gpu/drm/i915/display/intel_dp.c ret = drm_modeset_lock(&crtc->base.mutex, ctx); base 4824 drivers/gpu/drm/i915/display/intel_dp.c crtc_state = to_intel_crtc_state(crtc->base.state); base 4828 drivers/gpu/drm/i915/display/intel_dp.c if (!crtc_state->base.active) base 5053 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5076 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5099 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5118 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5141 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5164 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5174 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5184 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5194 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5204 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5228 drivers/gpu/drm/i915/display/intel_dp.c enum port port = intel_dig_port->base.port; base 5235 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5236 drivers/gpu/drm/i915/display/intel_dp.c struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); base 5262 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5292 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 5315 drivers/gpu/drm/i915/display/intel_dp.c return drm_get_edid(&intel_connector->base, base 5353 drivers/gpu/drm/i915/display/intel_dp.c struct intel_encoder *encoder = &dig_port->base; base 5357 drivers/gpu/drm/i915/display/intel_dp.c connector->base.id, connector->name); base 5457 drivers/gpu/drm/i915/display/intel_dp.c struct intel_encoder *intel_encoder = &dig_port->base; base 5458 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); base 5464 drivers/gpu/drm/i915/display/intel_dp.c connector->base.id, connector->name); base 5575 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); base 5606 drivers/gpu/drm/i915/display/intel_dp.c struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base); base 6203 drivers/gpu/drm/i915/display/intel_dp.c struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; base 6276 drivers/gpu/drm/i915/display/intel_dp.c if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { base 6284 drivers/gpu/drm/i915/display/intel_dp.c port_name(intel_dig_port->base.port)); base 6289 drivers/gpu/drm/i915/display/intel_dp.c port_name(intel_dig_port->base.port), base 6345 drivers/gpu/drm/i915/display/intel_dp.c enum port port = dp_to_dig_port(intel_dp)->base.port; base 6536 drivers/gpu/drm/i915/display/intel_dp.c enum port port = dp_to_dig_port(intel_dp)->base.port; base 6653 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); base 6686 drivers/gpu/drm/i915/display/intel_dp.c if (!crtc_state->base.active) { base 6815 drivers/gpu/drm/i915/display/intel_dp.c struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; base 6852 drivers/gpu/drm/i915/display/intel_dp.c crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; base 6895 drivers/gpu/drm/i915/display/intel_dp.c crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; base 6970 drivers/gpu/drm/i915/display/intel_dp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 7004 drivers/gpu/drm/i915/display/intel_dp.c struct drm_connector *connector = &intel_connector->base; base 7119 drivers/gpu/drm/i915/display/intel_dp.c connector = &intel_connector->base; base 7120 drivers/gpu/drm/i915/display/intel_dp.c DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, base 7139 drivers/gpu/drm/i915/display/intel_dp.c struct drm_connector *connector = &intel_connector->base; base 7141 drivers/gpu/drm/i915/display/intel_dp.c struct intel_encoder *intel_encoder = &intel_dig_port->base; base 7142 drivers/gpu/drm/i915/display/intel_dp.c struct drm_device *dev = intel_encoder->base.dev; base 7222 drivers/gpu/drm/i915/display/intel_dp.c intel_connector->base.base.id); base 7272 drivers/gpu/drm/i915/display/intel_dp.c intel_encoder = &intel_dig_port->base; base 7273 drivers/gpu/drm/i915/display/intel_dp.c encoder = &intel_encoder->base; base 7275 drivers/gpu/drm/i915/display/intel_dp.c if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, base 7352 drivers/gpu/drm/i915/display/intel_dp.c intel_dp = enc_to_intel_dp(&encoder->base); base 7373 drivers/gpu/drm/i915/display/intel_dp.c intel_dp = enc_to_intel_dp(&encoder->base); base 60 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); base 85 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); base 112 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 113 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); base 181 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); base 231 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); base 250 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); base 267 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c struct drm_i915_private *dev_priv = to_i915(intel_connector->base.dev); base 366 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_connector->base.base.id, base 367 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_connector->base.name, base 373 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_connector->base.base.id, base 374 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_connector->base.name, base 45 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_atomic_state *state = crtc_state->base.state; base 46 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); base 51 drivers/gpu/drm/i915/display/intel_dp_mst.c &crtc_state->base.adjusted_mode; base 94 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 95 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); base 102 drivers/gpu/drm/i915/display/intel_dp_mst.c &pipe_config->base.adjusted_mode; base 205 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); base 229 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); base 256 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_dig_port->base.post_disable(&intel_dig_port->base, base 267 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); base 272 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_dig_port->base.pre_pll_enable(&intel_dig_port->base, base 280 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); base 285 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_dig_port->base.post_pll_disable(&intel_dig_port->base, base 294 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); base 297 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 298 drivers/gpu/drm/i915/display/intel_dp_mst.c enum port port = intel_dig_port->base.port; base 318 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_dig_port->base.pre_enable(&intel_dig_port->base, base 341 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); base 344 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 345 drivers/gpu/drm/i915/display/intel_dp_mst.c enum port port = intel_dig_port->base.port; base 363 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); base 373 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); base 376 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_ddi_get_config(&intel_dig_port->base, pipe_config); base 466 drivers/gpu/drm/i915/display/intel_dp_mst.c return &intel_dp->mst_encoders[crtc->pipe]->base.base; base 490 drivers/gpu/drm/i915/display/intel_dp_mst.c if (connector->encoder && connector->base.state->crtc) { base 503 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_device *dev = intel_dig_port->base.base.dev; base 519 drivers/gpu/drm/i915/display/intel_dp_mst.c connector = &intel_connector->base; base 531 drivers/gpu/drm/i915/display/intel_dp_mst.c &intel_dp->mst_encoders[pipe]->base.base; base 533 drivers/gpu/drm/i915/display/intel_dp_mst.c ret = drm_connector_attach_encoder(&intel_connector->base, enc); base 538 drivers/gpu/drm/i915/display/intel_dp_mst.c drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); base 539 drivers/gpu/drm/i915/display/intel_dp_mst.c drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); base 553 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_dp->attached_connector->base.max_bpc_property; base 580 drivers/gpu/drm/i915/display/intel_dp_mst.c DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); base 601 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_device *dev = intel_dig_port->base.base.dev; base 609 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_encoder = &intel_mst->base; base 612 drivers/gpu/drm/i915/display/intel_dp_mst.c drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, base 616 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_encoder->power_domain = intel_dig_port->base.power_domain; base 617 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_encoder->port = intel_dig_port->base.port; base 639 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); base 656 drivers/gpu/drm/i915/display/intel_dp_mst.c struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); base 658 drivers/gpu/drm/i915/display/intel_dp_mst.c enum port port = intel_dig_port->base.port; base 593 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 619 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 644 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 645 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); base 646 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); base 740 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 741 drivers/gpu/drm/i915/display/intel_dpio_phy.c enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); base 742 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 784 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); base 785 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 786 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 864 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 866 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 867 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 943 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); base 944 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 955 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 956 drivers/gpu/drm/i915/display/intel_dpio_phy.c enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe; base 990 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 991 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); base 992 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); base 1017 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); base 1018 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1019 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1046 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 1048 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1049 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1076 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); base 1077 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1078 drivers/gpu/drm/i915/display/intel_dpio_phy.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 139 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 140 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 166 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 167 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 169 drivers/gpu/drm/i915/display/intel_dpll_mgr.c unsigned int crtc_mask = drm_crtc_mask(&crtc->base); base 186 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc->base.base.id); base 211 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 212 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 214 drivers/gpu/drm/i915/display/intel_dpll_mgr.c unsigned int crtc_mask = drm_crtc_mask(&crtc->base); base 229 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc->base.base.id); base 253 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 258 drivers/gpu/drm/i915/display/intel_dpll_mgr.c shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); base 274 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc->base.base.id, crtc->base.name, base 285 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc->base.base.id, crtc->base.name, base 302 drivers/gpu/drm/i915/display/intel_dpll_mgr.c shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); base 319 drivers/gpu/drm/i915/display/intel_dpll_mgr.c shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); base 352 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 452 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 462 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc->base.base.id, crtc->base.name, base 843 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 1752 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1892 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1909 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc->base.base.id, crtc->base.name, pll->info->name); base 2275 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 2541 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 2563 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 2574 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 2700 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 2890 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enc_to_mst(&encoder->base)->primary : base 2891 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enc_to_dig_port(&encoder->base); base 2909 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 2945 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 3003 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 3572 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 3595 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 3624 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 90 drivers/gpu/drm/i915/display/intel_dsi.c host->base.ops = funcs; base 107 drivers/gpu/drm/i915/display/intel_dsi.c device->host = &host->base; base 116 drivers/gpu/drm/i915/display/intel_dsi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 43 drivers/gpu/drm/i915/display/intel_dsi.h struct intel_encoder base; base 126 drivers/gpu/drm/i915/display/intel_dsi.h struct mipi_dsi_host base; base 136 drivers/gpu/drm/i915/display/intel_dsi.h return container_of(h, struct intel_dsi_host, base); base 146 drivers/gpu/drm/i915/display/intel_dsi.h return container_of(encoder, struct intel_dsi, base.base); base 161 drivers/gpu/drm/i915/display/intel_dsi.h return enc_to_intel_dsi(&encoder->base)->ports; base 49 drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 161 drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c struct drm_device *dev = intel_connector->base.dev; base 124 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); base 345 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct drm_device *dev = intel_dsi->base.base.dev; base 459 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); base 524 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); base 573 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct drm_device *dev = intel_dsi->base.base.dev; base 114 drivers/gpu/drm/i915/display/intel_dvo.c struct intel_encoder base; base 125 drivers/gpu/drm/i915/display/intel_dvo.c return container_of(encoder, struct intel_dvo, base); base 135 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_device *dev = connector->base.dev; base 137 drivers/gpu/drm/i915/display/intel_dvo.c struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base); base 151 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 165 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 181 drivers/gpu/drm/i915/display/intel_dvo.c pipe_config->base.adjusted_mode.flags |= flags; base 183 drivers/gpu/drm/i915/display/intel_dvo.c pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; base 190 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 204 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 210 drivers/gpu/drm/i915/display/intel_dvo.c &pipe_config->base.mode, base 211 drivers/gpu/drm/i915/display/intel_dvo.c &pipe_config->base.adjusted_mode); base 256 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 279 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 280 drivers/gpu/drm/i915/display/intel_dvo.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 281 drivers/gpu/drm/i915/display/intel_dvo.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 316 drivers/gpu/drm/i915/display/intel_dvo.c connector->base.id, connector->name); base 429 drivers/gpu/drm/i915/display/intel_dvo.c intel_encoder = &intel_dvo->base; base 441 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_connector *connector = &intel_connector->base; base 501 drivers/gpu/drm/i915/display/intel_dvo.c drm_encoder_init(&dev_priv->drm, &intel_encoder->base, base 425 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 433 drivers/gpu/drm/i915/display/intel_fbc.c if (plane_state->base.visible) base 492 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 631 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 661 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 664 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_framebuffer *fb = plane_state->base.fb; base 669 drivers/gpu/drm/i915/display/intel_fbc.c cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags; base 673 drivers/gpu/drm/i915/display/intel_fbc.c cache->plane.rotation = plane_state->base.rotation; base 679 drivers/gpu/drm/i915/display/intel_fbc.c cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16; base 680 drivers/gpu/drm/i915/display/intel_fbc.c cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16; base 681 drivers/gpu/drm/i915/display/intel_fbc.c cache->plane.visible = plane_state->base.visible; base 684 drivers/gpu/drm/i915/display/intel_fbc.c cache->plane.y = plane_state->base.src.y1 >> 16; base 686 drivers/gpu/drm/i915/display/intel_fbc.c cache->plane.pixel_blend_mode = plane_state->base.pixel_blend_mode; base 702 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 830 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 843 drivers/gpu/drm/i915/display/intel_fbc.c params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane; base 860 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 912 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 944 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 958 drivers/gpu/drm/i915/display/intel_fbc.c return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit; base 1049 drivers/gpu/drm/i915/display/intel_fbc.c struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc); base 1054 drivers/gpu/drm/i915/display/intel_fbc.c if (!plane_state->base.visible) base 1086 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1132 drivers/gpu/drm/i915/display/intel_fbc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1264 drivers/gpu/drm/i915/display/intel_fbc.c crtc->base.primary->state->visible) base 185 drivers/gpu/drm/i915/display/intel_fbdev.c (sizes->fb_width > intel_fb->base.width || base 186 drivers/gpu/drm/i915/display/intel_fbdev.c sizes->fb_height > intel_fb->base.height)) { base 189 drivers/gpu/drm/i915/display/intel_fbdev.c intel_fb->base.width, intel_fb->base.height, base 191 drivers/gpu/drm/i915/display/intel_fbdev.c drm_framebuffer_put(&intel_fb->base); base 194 drivers/gpu/drm/i915/display/intel_fbdev.c if (!intel_fb || WARN_ON(!intel_fb_obj(&intel_fb->base))) { base 203 drivers/gpu/drm/i915/display/intel_fbdev.c sizes->fb_width = intel_fb->base.width; base 204 drivers/gpu/drm/i915/display/intel_fbdev.c sizes->fb_height = intel_fb->base.height; base 214 drivers/gpu/drm/i915/display/intel_fbdev.c vma = intel_pin_and_fence_fb_obj(&ifbdev->fb->base, base 230 drivers/gpu/drm/i915/display/intel_fbdev.c ifbdev->helper.fb = &ifbdev->fb->base; base 235 drivers/gpu/drm/i915/display/intel_fbdev.c info->apertures->ranges[0].base = ggtt->gmadr.start; base 264 drivers/gpu/drm/i915/display/intel_fbdev.c ifbdev->fb->base.width, ifbdev->fb->base.height, base 302 drivers/gpu/drm/i915/display/intel_fbdev.c drm_framebuffer_remove(&ifbdev->fb->base); base 336 drivers/gpu/drm/i915/display/intel_fbdev.c if (obj->base.size > max_size) { base 340 drivers/gpu/drm/i915/display/intel_fbdev.c max_size = obj->base.size; base 370 drivers/gpu/drm/i915/display/intel_fbdev.c cur_size = cur_size * fb->base.format->cpp[0]; base 371 drivers/gpu/drm/i915/display/intel_fbdev.c if (fb->base.pitches[0] < cur_size) { base 374 drivers/gpu/drm/i915/display/intel_fbdev.c cur_size, fb->base.pitches[0]); base 380 drivers/gpu/drm/i915/display/intel_fbdev.c cur_size = intel_fb_align_height(&fb->base, 0, cur_size); base 381 drivers/gpu/drm/i915/display/intel_fbdev.c cur_size *= fb->base.pitches[0]; base 386 drivers/gpu/drm/i915/display/intel_fbdev.c fb->base.format->cpp[0] * 8, base 407 drivers/gpu/drm/i915/display/intel_fbdev.c ifbdev->preferred_bpp = fb->base.format->cpp[0] * 8; base 410 drivers/gpu/drm/i915/display/intel_fbdev.c drm_framebuffer_get(&ifbdev->fb->base); base 421 drivers/gpu/drm/i915/display/intel_fbdev.c crtc->base.id); base 593 drivers/gpu/drm/i915/display/intel_fbdev.c intel_fb_obj(&ifbdev->fb->base)->stolen) base 92 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 144 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 210 drivers/gpu/drm/i915/display/intel_fifo_underrun.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 167 drivers/gpu/drm/i915/display/intel_frontbuffer.c struct drm_i915_private *i915 = to_i915(front->obj->base.dev); base 186 drivers/gpu/drm/i915/display/intel_frontbuffer.c struct drm_i915_private *i915 = to_i915(front->obj->base.dev); base 219 drivers/gpu/drm/i915/display/intel_frontbuffer.c __releases(&to_i915(front->obj->base.dev)->fb_tracking.lock) base 225 drivers/gpu/drm/i915/display/intel_frontbuffer.c spin_unlock(&to_i915(front->obj->base.dev)->fb_tracking.lock); base 234 drivers/gpu/drm/i915/display/intel_frontbuffer.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 273 drivers/gpu/drm/i915/display/intel_frontbuffer.c &to_i915(front->obj->base.dev)->fb_tracking.lock); base 85 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 110 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 120 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 258 drivers/gpu/drm/i915/display/intel_hdcp.c enum port port = intel_dig_port->base.port; base 286 drivers/gpu/drm/i915/display/intel_hdcp.c dev_priv = intel_dig_port->base.base.dev->dev_private; base 497 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_device *dev = connector->base.dev; base 576 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_device *dev = connector->base.dev; base 596 drivers/gpu/drm/i915/display/intel_hdcp.c dev_priv = intel_dig_port->base.base.dev->dev_private; base 598 drivers/gpu/drm/i915/display/intel_hdcp.c port = intel_dig_port->base.port; base 729 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = connector->base.dev->dev_private; base 731 drivers/gpu/drm/i915/display/intel_hdcp.c enum port port = intel_dig_port->base.port; base 735 drivers/gpu/drm/i915/display/intel_hdcp.c connector->base.name, connector->base.base.id); base 758 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = connector->base.dev->dev_private; base 762 drivers/gpu/drm/i915/display/intel_hdcp.c connector->base.name, connector->base.base.id); base 808 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = connector->base.dev->dev_private; base 810 drivers/gpu/drm/i915/display/intel_hdcp.c enum port port = intel_dig_port->base.port; base 824 drivers/gpu/drm/i915/display/intel_hdcp.c connector->base.name, connector->base.base.id, base 841 drivers/gpu/drm/i915/display/intel_hdcp.c connector->base.name, connector->base.base.id); base 869 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_device *dev = connector->base.dev; base 880 drivers/gpu/drm/i915/display/intel_hdcp.c drm_hdcp_update_content_protection(&connector->base, base 898 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 926 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 952 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 977 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1002 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1027 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1051 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1078 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1105 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1128 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1150 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1179 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_device *dev = connector->base.dev; base 1374 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_device *dev = connector->base.dev; base 1493 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1526 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1593 drivers/gpu/drm/i915/display/intel_hdcp.c connector->base.name, connector->base.base.id, base 1604 drivers/gpu/drm/i915/display/intel_hdcp.c connector->base.name, connector->base.base.id, base 1616 drivers/gpu/drm/i915/display/intel_hdcp.c connector->base.name, connector->base.base.id); base 1632 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1676 drivers/gpu/drm/i915/display/intel_hdcp.c connector->base.name, connector->base.base.id, base 1680 drivers/gpu/drm/i915/display/intel_hdcp.c connector->base.name, connector->base.base.id); base 1686 drivers/gpu/drm/i915/display/intel_hdcp.c connector->base.name, connector->base.base.id, ret); base 1695 drivers/gpu/drm/i915/display/intel_hdcp.c connector->base.name, connector->base.base.id, base 1828 drivers/gpu/drm/i915/display/intel_hdcp.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1839 drivers/gpu/drm/i915/display/intel_hdcp.c drm_connector_attach_content_protection_property(&connector->base, base 63 drivers/gpu/drm/i915/display/intel_hdmi.c return hdmi_to_dig_port(intel_hdmi)->base.base.dev; base 91 drivers/gpu/drm/i915/display/intel_hdmi.c container_of(encoder, struct intel_digital_port, base.base); base 97 drivers/gpu/drm/i915/display/intel_hdmi.c return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); base 210 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 244 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 262 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 281 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 282 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); base 317 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 318 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 336 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 337 drivers/gpu/drm/i915/display/intel_hdmi.c enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; base 358 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 359 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); base 397 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 398 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 416 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 417 drivers/gpu/drm/i915/display/intel_hdmi.c enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; base 434 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 435 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); base 470 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 471 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 489 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 490 drivers/gpu/drm/i915/display/intel_hdmi.c enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; base 510 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 542 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 557 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 596 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 597 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); base 641 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); base 670 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); base 703 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->base.adjusted_mode; base 790 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->base.adjusted_mode); base 807 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 840 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 841 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); base 950 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 951 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 975 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 976 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 999 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1013 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->base.adjusted_mode)) base 1022 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1023 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); base 1024 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); base 1081 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1082 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); base 1083 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); base 1130 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1131 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); base 1132 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); base 1188 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1247 drivers/gpu/drm/i915/display/intel_hdmi.c intel_dig_port->base.base.dev->dev_private; base 1277 drivers/gpu/drm/i915/display/intel_hdmi.c intel_dig_port->base.base.dev->dev_private; base 1312 drivers/gpu/drm/i915/display/intel_hdmi.c intel_dig_port->base.base.dev->dev_private; base 1431 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1433 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_crtc *crtc = connector->base.state->crtc; base 1435 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc, base); base 1446 drivers/gpu/drm/i915/display/intel_hdmi.c ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); base 1451 drivers/gpu/drm/i915/display/intel_hdmi.c ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); base 1466 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1472 drivers/gpu/drm/i915/display/intel_hdmi.c ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); base 1493 drivers/gpu/drm/i915/display/intel_hdmi.c intel_dig_port->base.base.dev->dev_private; base 1494 drivers/gpu/drm/i915/display/intel_hdmi.c enum port port = intel_dig_port->base.port; base 1721 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_device *dev = encoder->base.dev; base 1723 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1724 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); base 1725 drivers/gpu/drm/i915/display/intel_hdmi.c const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; base 1760 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1761 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); base 1780 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); base 1781 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_device *dev = encoder->base.dev; base 1816 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->base.adjusted_mode.flags |= flags; base 1826 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->base.adjusted_mode.crtc_clock = dotclock; base 1847 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 1859 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_device *dev = encoder->base.dev; base 1861 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); base 1881 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_device *dev = encoder->base.dev; base 1883 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); base 1931 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_device *dev = encoder->base.dev; base 1933 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 1934 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); base 1992 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_device *dev = encoder->base.dev; base 1994 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); base 1997 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 2075 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2099 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; base 2104 drivers/gpu/drm/i915/display/intel_hdmi.c const struct drm_display_info *info = &connector->base.display_info; base 2195 drivers/gpu/drm/i915/display/intel_hdmi.c to_i915(crtc_state->base.crtc->dev); base 2196 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_atomic_state *state = crtc_state->base.state; base 2200 drivers/gpu/drm/i915/display/intel_hdmi.c &crtc_state->base.adjusted_mode; base 2225 drivers/gpu/drm/i915/display/intel_hdmi.c if (connector_state->crtc != crtc_state->base.crtc) base 2268 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); base 2298 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); base 2299 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2300 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 2305 drivers/gpu/drm/i915/display/intel_hdmi.c int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; base 2457 drivers/gpu/drm/i915/display/intel_hdmi.c enum port port = hdmi_to_dig_port(hdmi)->base.port; base 2545 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; base 2549 drivers/gpu/drm/i915/display/intel_hdmi.c connector->base.id, connector->name); base 2581 drivers/gpu/drm/i915/display/intel_hdmi.c connector->base.id, connector->name); base 2607 drivers/gpu/drm/i915/display/intel_hdmi.c enc_to_dig_port(&encoder->base); base 2620 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); base 2621 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2675 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_device *dev = encoder->base.dev; base 2690 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); base 2691 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_device *dev = encoder->base.dev; base 2819 drivers/gpu/drm/i915/display/intel_hdmi.c drm_object_attach_property(&connector->base, base 2849 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 2850 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); base 2860 drivers/gpu/drm/i915/display/intel_hdmi.c connector->base.id, connector->name, base 3030 drivers/gpu/drm/i915/display/intel_hdmi.c to_i915(intel_dig_port->base.base.dev); base 3070 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_connector *connector = &intel_connector->base; base 3072 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_encoder *intel_encoder = &intel_dig_port->base; base 3073 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_device *dev = intel_encoder->base.dev; base 3177 drivers/gpu/drm/i915/display/intel_hdmi.c intel_encoder = &intel_dig_port->base; base 3179 drivers/gpu/drm/i915/display/intel_hdmi.c drm_encoder_init(&dev_priv->drm, &intel_encoder->base, base 281 drivers/gpu/drm/i915/display/intel_hotplug.c struct drm_device *dev = connector->base.dev; base 285 drivers/gpu/drm/i915/display/intel_hotplug.c old_status = connector->base.status; base 287 drivers/gpu/drm/i915/display/intel_hotplug.c connector->base.status = base 288 drivers/gpu/drm/i915/display/intel_hotplug.c drm_helper_probe_detect(&connector->base, NULL, false); base 290 drivers/gpu/drm/i915/display/intel_hotplug.c if (old_status == connector->base.status) base 294 drivers/gpu/drm/i915/display/intel_hotplug.c connector->base.base.id, base 295 drivers/gpu/drm/i915/display/intel_hotplug.c connector->base.name, base 297 drivers/gpu/drm/i915/display/intel_hotplug.c drm_get_connector_status_name(connector->base.status)); base 305 drivers/gpu/drm/i915/display/intel_hotplug.c enc_to_dig_port(&encoder->base)->hpd_pulse != NULL; base 338 drivers/gpu/drm/i915/display/intel_hotplug.c dig_port = enc_to_dig_port(&encoder->base); base 192 drivers/gpu/drm/i915/display/intel_lspcon.c &crtc_state->base.adjusted_mode; base 253 drivers/gpu/drm/i915/display/intel_lspcon.c if (intel_digital_port_connected(&dig_port->base)) { base 437 drivers/gpu/drm/i915/display/intel_lspcon.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 438 drivers/gpu/drm/i915/display/intel_lspcon.c struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base); base 475 drivers/gpu/drm/i915/display/intel_lspcon.c struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); base 478 drivers/gpu/drm/i915/display/intel_lspcon.c &crtc_state->base.adjusted_mode; base 525 drivers/gpu/drm/i915/display/intel_lspcon.c return enc_to_intel_lspcon(&encoder->base)->active; base 557 drivers/gpu/drm/i915/display/intel_lspcon.c struct drm_device *dev = intel_dig_port->base.base.dev; base 559 drivers/gpu/drm/i915/display/intel_lspcon.c struct drm_connector *connector = &dp->attached_connector->base; base 66 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_encoder base; base 80 drivers/gpu/drm/i915/display/intel_lvds.c return container_of(encoder, struct intel_lvds_encoder, base.base); base 102 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 103 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); base 122 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 123 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); base 138 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->base.adjusted_mode.flags |= flags; base 151 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; base 231 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); base 232 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 233 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 234 drivers/gpu/drm/i915/display/intel_lvds.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 312 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_device *dev = encoder->base.dev; base 313 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); base 331 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); base 332 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 390 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); base 392 drivers/gpu/drm/i915/display/intel_lvds.c to_lvds_encoder(&intel_encoder->base); base 395 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 396 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); base 768 drivers/gpu/drm/i915/display/intel_lvds.c return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; base 773 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_device *dev = lvds_encoder->base.base.dev; base 873 drivers/gpu/drm/i915/display/intel_lvds.c intel_encoder = &lvds_encoder->base; base 874 drivers/gpu/drm/i915/display/intel_lvds.c encoder = &intel_encoder->base; base 875 drivers/gpu/drm/i915/display/intel_lvds.c connector = &intel_connector->base; base 876 drivers/gpu/drm/i915/display/intel_lvds.c drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, base 879 drivers/gpu/drm/i915/display/intel_lvds.c drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, base 367 drivers/gpu/drm/i915/display/intel_opregion.c struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); base 474 drivers/gpu/drm/i915/display/intel_opregion.c intel_panel_set_backlight_acpi(connector->base.state, bclp, 255); base 669 drivers/gpu/drm/i915/display/intel_opregion.c switch (connector->base.connector_type) { base 698 drivers/gpu/drm/i915/display/intel_opregion.c MISSING_CASE(connector->base.connector_type); base 902 drivers/gpu/drm/i915/display/intel_opregion.c void *base; base 921 drivers/gpu/drm/i915/display/intel_opregion.c base = memremap(asls, OPREGION_SIZE, MEMREMAP_WB); base 922 drivers/gpu/drm/i915/display/intel_opregion.c if (!base) base 925 drivers/gpu/drm/i915/display/intel_opregion.c memcpy(buf, base, sizeof(buf)); base 932 drivers/gpu/drm/i915/display/intel_opregion.c opregion->header = base; base 933 drivers/gpu/drm/i915/display/intel_opregion.c opregion->lid_state = base + ACPI_CLID; base 943 drivers/gpu/drm/i915/display/intel_opregion.c opregion->acpi = base + OPREGION_ACPI_OFFSET; base 948 drivers/gpu/drm/i915/display/intel_opregion.c opregion->swsci = base + OPREGION_SWSCI_OFFSET; base 954 drivers/gpu/drm/i915/display/intel_opregion.c opregion->asle = base + OPREGION_ASLE_OFFSET; base 1002 drivers/gpu/drm/i915/display/intel_opregion.c vbt = base + OPREGION_VBT_OFFSET; base 1025 drivers/gpu/drm/i915/display/intel_opregion.c memunmap(base); base 664 drivers/gpu/drm/i915/display/intel_overlay.c to_intel_plane_state(overlay->crtc->base.primary->state); base 672 drivers/gpu/drm/i915/display/intel_overlay.c if (state->base.visible) base 673 drivers/gpu/drm/i915/display/intel_overlay.c format = state->base.fb->format->format; base 1028 drivers/gpu/drm/i915/display/intel_overlay.c if (rec->offset_Y + tmp > new_bo->base.size) base 1039 drivers/gpu/drm/i915/display/intel_overlay.c if (rec->offset_Y + tmp > new_bo->base.size) base 1043 drivers/gpu/drm/i915/display/intel_overlay.c if (rec->offset_U + tmp > new_bo->base.size || base 1044 drivers/gpu/drm/i915/display/intel_overlay.c rec->offset_V + tmp > new_bo->base.size) base 1415 drivers/gpu/drm/i915/display/intel_overlay.c unsigned long base; base 1435 drivers/gpu/drm/i915/display/intel_overlay.c error->base = overlay->flip_addr; base 1449 drivers/gpu/drm/i915/display/intel_overlay.c error->base); base 68 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 73 drivers/gpu/drm/i915/display/intel_panel.c list_for_each_entry(scan, &connector->base.probed_modes, head) { base 100 drivers/gpu/drm/i915/display/intel_panel.c connector->base.base.id, connector->base.name); base 109 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 113 drivers/gpu/drm/i915/display/intel_panel.c if (list_empty(&connector->base.probed_modes)) base 117 drivers/gpu/drm/i915/display/intel_panel.c list_for_each_entry(scan, &connector->base.probed_modes, head) { base 126 drivers/gpu/drm/i915/display/intel_panel.c connector->base.base.id, connector->base.name); base 132 drivers/gpu/drm/i915/display/intel_panel.c scan = list_first_entry(&connector->base.probed_modes, base 142 drivers/gpu/drm/i915/display/intel_panel.c connector->base.base.id, connector->base.name); base 151 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 152 drivers/gpu/drm/i915/display/intel_panel.c struct drm_display_info *info = &connector->base.display_info; base 166 drivers/gpu/drm/i915/display/intel_panel.c connector->base.base.id, connector->base.name); base 181 drivers/gpu/drm/i915/display/intel_panel.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 303 drivers/gpu/drm/i915/display/intel_panel.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 324 drivers/gpu/drm/i915/display/intel_panel.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 381 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); base 383 drivers/gpu/drm/i915/display/intel_panel.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 520 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 538 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 545 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 552 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 580 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 588 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 606 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 615 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 625 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 653 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 664 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 697 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 732 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 758 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 789 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 802 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 822 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 847 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 878 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 928 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 974 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1013 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1048 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1050 drivers/gpu/drm/i915/display/intel_panel.c enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; base 1078 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1080 drivers/gpu/drm/i915/display/intel_panel.c enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; base 1126 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1190 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1192 drivers/gpu/drm/i915/display/intel_panel.c enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; base 1209 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1231 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1255 drivers/gpu/drm/i915/display/intel_panel.c struct drm_device *dev = connector->base.dev; base 1260 drivers/gpu/drm/i915/display/intel_panel.c intel_panel_set_backlight(connector->base.state, bd->props.brightness, base 1286 drivers/gpu/drm/i915/display/intel_panel.c struct drm_device *dev = connector->base.dev; base 1347 drivers/gpu/drm/i915/display/intel_panel.c connector->base.kdev, base 1359 drivers/gpu/drm/i915/display/intel_panel.c connector->base.name); base 1381 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1419 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1442 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1457 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1475 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1493 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1512 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1545 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1570 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1614 drivers/gpu/drm/i915/display/intel_panel.c lpt_set_backlight(connector->base.state, panel->backlight.level); base 1625 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1657 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1696 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1730 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1764 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1804 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1842 drivers/gpu/drm/i915/display/intel_panel.c struct drm_device *dev = connector->base.dev; base 1884 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1953 drivers/gpu/drm/i915/display/intel_panel.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1955 drivers/gpu/drm/i915/display/intel_panel.c if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && base 1959 drivers/gpu/drm/i915/display/intel_panel.c if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI && base 1995 drivers/gpu/drm/i915/display/intel_panel.c if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI) { base 2046 drivers/gpu/drm/i915/display/intel_panel.c drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); base 2049 drivers/gpu/drm/i915/display/intel_panel.c drm_mode_destroy(intel_connector->base.dev, base 87 drivers/gpu/drm/i915/display/intel_pipe_crc.c if (!encoder->base.crtc) base 90 drivers/gpu/drm/i915/display/intel_pipe_crc.c crtc = to_intel_crtc(encoder->base.crtc); base 101 drivers/gpu/drm/i915/display/intel_pipe_crc.c dig_port = enc_to_dig_port(&encoder->base); base 102 drivers/gpu/drm/i915/display/intel_pipe_crc.c switch (dig_port->base.port) { base 114 drivers/gpu/drm/i915/display/intel_pipe_crc.c port_name(dig_port->base.port)); base 289 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 312 drivers/gpu/drm/i915/display/intel_pipe_crc.c pipe_config->base.mode_changed = pipe_config->has_psr; base 316 drivers/gpu/drm/i915/display/intel_pipe_crc.c pipe_config->base.active && crtc->pipe == PIPE_A && base 318 drivers/gpu/drm/i915/display/intel_pipe_crc.c pipe_config->base.mode_changed = true; base 639 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct drm_crtc *crtc = &intel_crtc->base; base 659 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct drm_crtc *crtc = &intel_crtc->base; base 284 drivers/gpu/drm/i915/display/intel_psr.c to_i915(dp_to_dig_port(intel_dp)->base.base.dev); base 369 drivers/gpu/drm/i915/display/intel_psr.c intel_dig_port->write_infoframe(&intel_dig_port->base, base 540 drivers/gpu/drm/i915/display/intel_psr.c int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay; base 541 drivers/gpu/drm/i915/display/intel_psr.c int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; base 598 drivers/gpu/drm/i915/display/intel_psr.c &crtc_state->base.adjusted_mode; base 614 drivers/gpu/drm/i915/display/intel_psr.c if (dig_port->base.port != PORT_A) { base 735 drivers/gpu/drm/i915/display/intel_psr.c dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; base 949 drivers/gpu/drm/i915/display/intel_psr.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 950 drivers/gpu/drm/i915/display/intel_psr.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 79 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_encoder base; base 127 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_connector base; base 169 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_digital_connector_state base; base 180 drivers/gpu/drm/i915/display/intel_sdvo.c return container_of(encoder, struct intel_sdvo, base); base 191 drivers/gpu/drm/i915/display/intel_sdvo.c return container_of(connector, struct intel_sdvo_connector, base.base); base 195 drivers/gpu/drm/i915/display/intel_sdvo.c container_of((conn_state), struct intel_sdvo_connector_state, base.base) base 214 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_device *dev = intel_sdvo->base.base.dev; base 798 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_connector->base.panel.fixed_mode; base 1090 drivers/gpu/drm/i915/display/intel_sdvo.c &crtc_state->base.adjusted_mode; base 1279 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 1280 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_display_mode *mode = &pipe_config->base.mode; base 1286 drivers/gpu/drm/i915/display/intel_sdvo.c if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) base 1306 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_connector->base.panel.fixed_mode)) base 1325 drivers/gpu/drm/i915/display/intel_sdvo.c if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI) base 1328 drivers/gpu/drm/i915/display/intel_sdvo.c if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON || base 1329 drivers/gpu/drm/i915/display/intel_sdvo.c (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio)) base 1332 drivers/gpu/drm/i915/display/intel_sdvo.c if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { base 1344 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED) base 1374 drivers/gpu/drm/i915/display/intel_sdvo.c const struct drm_connector_state *conn_state = &sdvo_state->base.base; base 1431 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); base 1432 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1433 drivers/gpu/drm/i915/display/intel_sdvo.c const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; base 1438 drivers/gpu/drm/i915/display/intel_sdvo.c const struct drm_display_mode *mode = &crtc_state->base.mode; base 1469 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_connector->base.panel.fixed_mode); base 1553 drivers/gpu/drm/i915/display/intel_sdvo.c to_intel_sdvo_connector(&connector->base); base 1554 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); base 1583 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1598 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_device *dev = encoder->base.dev; base 1632 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->base.adjusted_mode.flags |= flags; base 1652 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->base.adjusted_mode.crtc_clock = dotclock; base 1704 drivers/gpu/drm/i915/display/intel_sdvo.c &crtc_state->base.adjusted_mode; base 1724 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1726 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 1785 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_device *dev = encoder->base.dev; base 1788 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); base 1845 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_connector->base.panel.fixed_mode; base 1896 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); base 2036 drivers/gpu/drm/i915/display/intel_sdvo.c connector->base.id, connector->name); base 2086 drivers/gpu/drm/i915/display/intel_sdvo.c connector->base.id, connector->name); base 2185 drivers/gpu/drm/i915/display/intel_sdvo.c connector->base.id, connector->name); base 2223 drivers/gpu/drm/i915/display/intel_sdvo.c connector->base.id, connector->name); base 2413 drivers/gpu/drm/i915/display/intel_sdvo.c __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); base 2414 drivers/gpu/drm/i915/display/intel_sdvo.c return &state->base.base; base 2625 drivers/gpu/drm/i915/display/intel_sdvo.c drm_connector = &connector->base.base; base 2626 drivers/gpu/drm/i915/display/intel_sdvo.c ret = drm_connector_init(encoder->base.base.dev, base 2629 drivers/gpu/drm/i915/display/intel_sdvo.c connector->base.base.connector_type); base 2636 drivers/gpu/drm/i915/display/intel_sdvo.c connector->base.base.interlace_allowed = 1; base 2637 drivers/gpu/drm/i915/display/intel_sdvo.c connector->base.base.doublescan_allowed = 0; base 2638 drivers/gpu/drm/i915/display/intel_sdvo.c connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; base 2639 drivers/gpu/drm/i915/display/intel_sdvo.c connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; base 2641 drivers/gpu/drm/i915/display/intel_sdvo.c intel_connector_attach_encoder(&connector->base, &encoder->base); base 2650 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev); base 2652 drivers/gpu/drm/i915/display/intel_sdvo.c intel_attach_force_audio_property(&connector->base.base); base 2654 drivers/gpu/drm/i915/display/intel_sdvo.c intel_attach_broadcast_rgb_property(&connector->base.base); base 2656 drivers/gpu/drm/i915/display/intel_sdvo.c intel_attach_aspect_ratio_property(&connector->base.base); base 2657 drivers/gpu/drm/i915/display/intel_sdvo.c connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; base 2675 drivers/gpu/drm/i915/display/intel_sdvo.c __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, base 2676 drivers/gpu/drm/i915/display/intel_sdvo.c &conn_state->base.base); base 2684 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_encoder *encoder = &intel_sdvo->base.base; base 2704 drivers/gpu/drm/i915/display/intel_sdvo.c intel_connector = &intel_sdvo_connector->base; base 2705 drivers/gpu/drm/i915/display/intel_sdvo.c connector = &intel_connector->base; base 2740 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_encoder *encoder = &intel_sdvo->base.base; base 2751 drivers/gpu/drm/i915/display/intel_sdvo.c intel_connector = &intel_sdvo_connector->base; base 2752 drivers/gpu/drm/i915/display/intel_sdvo.c connector = &intel_connector->base; base 2780 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_encoder *encoder = &intel_sdvo->base.base; base 2791 drivers/gpu/drm/i915/display/intel_sdvo.c intel_connector = &intel_sdvo_connector->base; base 2792 drivers/gpu/drm/i915/display/intel_sdvo.c connector = &intel_connector->base; base 2816 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_encoder *encoder = &intel_sdvo->base.base; base 2828 drivers/gpu/drm/i915/display/intel_sdvo.c intel_connector = &intel_sdvo_connector->base; base 2829 drivers/gpu/drm/i915/display/intel_sdvo.c connector = &intel_connector->base; base 2924 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); base 2931 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_device *dev = intel_sdvo->base.base.dev; base 2936 drivers/gpu/drm/i915/display/intel_sdvo.c if (intel_attached_encoder(connector) == &intel_sdvo->base) { base 2947 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_device *dev = intel_sdvo->base.base.dev; base 2981 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0]; base 2982 drivers/gpu/drm/i915/display/intel_sdvo.c drm_object_attach_property(&intel_sdvo_connector->base.base.base, base 2997 drivers/gpu/drm/i915/display/intel_sdvo.c drm_object_attach_property(&connector->base, \ base 3011 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_device *dev = intel_sdvo->base.base.dev; base 3012 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_connector *connector = &intel_sdvo_connector->base.base; base 3038 drivers/gpu/drm/i915/display/intel_sdvo.c drm_object_attach_property(&connector->base, base 3046 drivers/gpu/drm/i915/display/intel_sdvo.c drm_object_attach_property(&connector->base, base 3073 drivers/gpu/drm/i915/display/intel_sdvo.c drm_object_attach_property(&connector->base, base 3082 drivers/gpu/drm/i915/display/intel_sdvo.c drm_object_attach_property(&connector->base, base 3112 drivers/gpu/drm/i915/display/intel_sdvo.c drm_object_attach_property(&connector->base, base 3125 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_device *dev = intel_sdvo->base.base.dev; base 3126 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_connector *connector = &intel_sdvo_connector->base.base; base 3260 drivers/gpu/drm/i915/display/intel_sdvo.c intel_encoder = &intel_sdvo->base; base 3264 drivers/gpu/drm/i915/display/intel_sdvo.c drm_encoder_init(&dev_priv->drm, &intel_encoder->base, base 3322 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo->base.cloneable = 0; base 3357 drivers/gpu/drm/i915/display/intel_sdvo.c drm_encoder_cleanup(&intel_encoder->base); base 97 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 98 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 99 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode; base 102 drivers/gpu/drm/i915/display/intel_sprite.c wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); base 120 drivers/gpu/drm/i915/display/intel_sprite.c if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) base 165 drivers/gpu/drm/i915/display/intel_sprite.c drm_crtc_vblank_put(&crtc->base); base 206 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 211 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 219 drivers/gpu/drm/i915/display/intel_sprite.c if (new_crtc_state->base.event) { base 220 drivers/gpu/drm/i915/display/intel_sprite.c WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0); base 222 drivers/gpu/drm/i915/display/intel_sprite.c spin_lock(&crtc->base.dev->event_lock); base 223 drivers/gpu/drm/i915/display/intel_sprite.c drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event); base 224 drivers/gpu/drm/i915/display/intel_sprite.c spin_unlock(&crtc->base.dev->event_lock); base 226 drivers/gpu/drm/i915/display/intel_sprite.c new_crtc_state->base.event = NULL; base 255 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 256 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 257 drivers/gpu/drm/i915/display/intel_sprite.c unsigned int rotation = plane_state->base.rotation; base 267 drivers/gpu/drm/i915/display/intel_sprite.c !plane_state->base.visible) base 277 drivers/gpu/drm/i915/display/intel_sprite.c fb->base.id, stride, base 278 drivers/gpu/drm/i915/display/intel_sprite.c plane->base.base.id, plane->base.name, max_stride); base 287 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 288 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_rect *src = &plane_state->base.src; base 290 drivers/gpu/drm/i915/display/intel_sprite.c bool rotated = drm_rotation_90_or_270(plane_state->base.rotation); base 363 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 368 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_x = plane_state->base.dst.x1; base 369 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_y = plane_state->base.dst.y1; base 370 drivers/gpu/drm/i915/display/intel_sprite.c u32 crtc_w = drm_rect_width(&plane_state->base.dst); base 371 drivers/gpu/drm/i915/display/intel_sprite.c u32 crtc_h = drm_rect_height(&plane_state->base.dst); base 376 drivers/gpu/drm/i915/display/intel_sprite.c hscale = drm_rect_calc_hscale(&plane_state->base.src, base 377 drivers/gpu/drm/i915/display/intel_sprite.c &plane_state->base.dst, base 379 drivers/gpu/drm/i915/display/intel_sprite.c vscale = drm_rect_calc_vscale(&plane_state->base.src, base 380 drivers/gpu/drm/i915/display/intel_sprite.c &plane_state->base.dst, base 384 drivers/gpu/drm/i915/display/intel_sprite.c if (is_planar_yuv_format(plane_state->base.fb->format->format) && base 425 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 509 drivers/gpu/drm/i915/display/intel_sprite.c if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE) base 510 drivers/gpu/drm/i915/display/intel_sprite.c csc = input_csc_matrix[plane_state->base.color_encoding]; base 512 drivers/gpu/drm/i915/display/intel_sprite.c csc = input_csc_matrix_lr[plane_state->base.color_encoding]; base 526 drivers/gpu/drm/i915/display/intel_sprite.c if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE) base 544 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 551 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_x = plane_state->base.dst.x1; base 552 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_y = plane_state->base.dst.y1; base 555 drivers/gpu/drm/i915/display/intel_sprite.c u32 src_w = drm_rect_width(&plane_state->base.src) >> 16; base 556 drivers/gpu/drm/i915/display/intel_sprite.c u32 src_h = drm_rect_height(&plane_state->base.src) >> 16; base 558 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 559 drivers/gpu/drm/i915/display/intel_sprite.c u8 alpha = plane_state->base.alpha >> 8; base 678 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 700 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 733 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 734 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 735 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 761 drivers/gpu/drm/i915/display/intel_sprite.c const s16 *csc = csc_matrix[plane_state->base.color_encoding]; base 792 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 793 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 794 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 800 drivers/gpu/drm/i915/display/intel_sprite.c plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) { base 841 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 842 drivers/gpu/drm/i915/display/intel_sprite.c unsigned int rotation = plane_state->base.rotation; base 887 drivers/gpu/drm/i915/display/intel_sprite.c if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709) base 907 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 908 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 909 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 935 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 941 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_x = plane_state->base.dst.x1; base 942 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_y = plane_state->base.dst.y1; base 943 drivers/gpu/drm/i915/display/intel_sprite.c u32 crtc_w = drm_rect_width(&plane_state->base.dst); base 944 drivers/gpu/drm/i915/display/intel_sprite.c u32 crtc_h = drm_rect_height(&plane_state->base.dst); base 997 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1014 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1051 drivers/gpu/drm/i915/display/intel_sprite.c to_i915(plane_state->base.plane->dev); base 1052 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 1053 drivers/gpu/drm/i915/display/intel_sprite.c unsigned int rotation = plane_state->base.rotation; base 1088 drivers/gpu/drm/i915/display/intel_sprite.c if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709) base 1091 drivers/gpu/drm/i915/display/intel_sprite.c if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE) base 1121 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1122 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1152 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1157 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_x = plane_state->base.dst.x1; base 1158 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_y = plane_state->base.dst.y1; base 1159 drivers/gpu/drm/i915/display/intel_sprite.c u32 crtc_w = drm_rect_width(&plane_state->base.dst); base 1160 drivers/gpu/drm/i915/display/intel_sprite.c u32 crtc_h = drm_rect_height(&plane_state->base.dst); base 1163 drivers/gpu/drm/i915/display/intel_sprite.c u32 src_w = drm_rect_width(&plane_state->base.src) >> 16; base 1164 drivers/gpu/drm/i915/display/intel_sprite.c u32 src_h = drm_rect_height(&plane_state->base.src) >> 16; base 1222 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1241 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1285 drivers/gpu/drm/i915/display/intel_sprite.c to_i915(plane_state->base.plane->dev); base 1286 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 1287 drivers/gpu/drm/i915/display/intel_sprite.c unsigned int rotation = plane_state->base.rotation; base 1320 drivers/gpu/drm/i915/display/intel_sprite.c if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709) base 1323 drivers/gpu/drm/i915/display/intel_sprite.c if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE) base 1342 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1343 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1344 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 1374 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1375 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1376 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 1405 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1410 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_x = plane_state->base.dst.x1; base 1411 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_y = plane_state->base.dst.y1; base 1412 drivers/gpu/drm/i915/display/intel_sprite.c u32 crtc_w = drm_rect_width(&plane_state->base.dst); base 1413 drivers/gpu/drm/i915/display/intel_sprite.c u32 crtc_h = drm_rect_height(&plane_state->base.dst); base 1416 drivers/gpu/drm/i915/display/intel_sprite.c u32 src_w = drm_rect_width(&plane_state->base.src) >> 16; base 1417 drivers/gpu/drm/i915/display/intel_sprite.c u32 src_h = drm_rect_height(&plane_state->base.src) >> 16; base 1471 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1489 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1525 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 1526 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_rect *src = &plane_state->base.src; base 1527 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_rect *dst = &plane_state->base.dst; base 1530 drivers/gpu/drm/i915/display/intel_sprite.c &crtc_state->base.adjusted_mode; base 1586 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1587 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1592 drivers/gpu/drm/i915/display/intel_sprite.c if (intel_fb_scalable(plane_state->base.fb)) { base 1602 drivers/gpu/drm/i915/display/intel_sprite.c ret = drm_atomic_helper_check_plane_state(&plane_state->base, base 1603 drivers/gpu/drm/i915/display/intel_sprite.c &crtc_state->base, base 1613 drivers/gpu/drm/i915/display/intel_sprite.c if (!plane_state->base.visible) base 1634 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1635 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1636 drivers/gpu/drm/i915/display/intel_sprite.c unsigned int rotation = plane_state->base.rotation; base 1659 drivers/gpu/drm/i915/display/intel_sprite.c ret = drm_atomic_helper_check_plane_state(&plane_state->base, base 1660 drivers/gpu/drm/i915/display/intel_sprite.c &crtc_state->base, base 1671 drivers/gpu/drm/i915/display/intel_sprite.c if (!plane_state->base.visible) base 1686 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1687 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1688 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 1689 drivers/gpu/drm/i915/display/intel_sprite.c unsigned int rotation = plane_state->base.rotation; base 1744 drivers/gpu/drm/i915/display/intel_sprite.c if (crtc_state->base.enable && base 1745 drivers/gpu/drm/i915/display/intel_sprite.c crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && base 1761 drivers/gpu/drm/i915/display/intel_sprite.c to_i915(plane_state->base.plane->dev); base 1762 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_x = plane_state->base.dst.x1; base 1763 drivers/gpu/drm/i915/display/intel_sprite.c int crtc_w = drm_rect_width(&plane_state->base.dst); base 1789 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 1790 drivers/gpu/drm/i915/display/intel_sprite.c unsigned int rotation = plane_state->base.rotation; base 1791 drivers/gpu/drm/i915/display/intel_sprite.c int src_w = drm_rect_width(&plane_state->base.src) >> 16; base 1807 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1808 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1809 drivers/gpu/drm/i915/display/intel_sprite.c const struct drm_framebuffer *fb = plane_state->base.fb; base 1824 drivers/gpu/drm/i915/display/intel_sprite.c ret = drm_atomic_helper_check_plane_state(&plane_state->base, base 1825 drivers/gpu/drm/i915/display/intel_sprite.c &crtc_state->base, base 1835 drivers/gpu/drm/i915/display/intel_sprite.c if (!plane_state->base.visible) base 1851 drivers/gpu/drm/i915/display/intel_sprite.c if (!(plane_state->base.alpha >> 8)) base 1852 drivers/gpu/drm/i915/display/intel_sprite.c plane_state->base.visible = false; base 1871 drivers/gpu/drm/i915/display/intel_sprite.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1872 drivers/gpu/drm/i915/display/intel_sprite.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1958 drivers/gpu/drm/i915/display/intel_sprite.c crtc->base.primary); base 2488 drivers/gpu/drm/i915/display/intel_sprite.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, base 2504 drivers/gpu/drm/i915/display/intel_sprite.c drm_plane_create_rotation_property(&plane->base, base 2508 drivers/gpu/drm/i915/display/intel_sprite.c drm_plane_create_color_properties(&plane->base, base 2516 drivers/gpu/drm/i915/display/intel_sprite.c drm_plane_create_alpha_property(&plane->base); base 2517 drivers/gpu/drm/i915/display/intel_sprite.c drm_plane_create_blend_mode_property(&plane->base, base 2522 drivers/gpu/drm/i915/display/intel_sprite.c drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); base 2613 drivers/gpu/drm/i915/display/intel_sprite.c ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, base 2621 drivers/gpu/drm/i915/display/intel_sprite.c drm_plane_create_rotation_property(&plane->base, base 2625 drivers/gpu/drm/i915/display/intel_sprite.c drm_plane_create_color_properties(&plane->base, base 2633 drivers/gpu/drm/i915/display/intel_sprite.c drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); base 50 drivers/gpu/drm/i915/display/intel_tc.c struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); base 51 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); base 66 drivers/gpu/drm/i915/display/intel_tc.c struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); base 97 drivers/gpu/drm/i915/display/intel_tc.c struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); base 98 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); base 152 drivers/gpu/drm/i915/display/intel_tc.c struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); base 153 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); base 184 drivers/gpu/drm/i915/display/intel_tc.c struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); base 185 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); base 203 drivers/gpu/drm/i915/display/intel_tc.c struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); base 204 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); base 234 drivers/gpu/drm/i915/display/intel_tc.c struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); base 235 drivers/gpu/drm/i915/display/intel_tc.c enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); base 389 drivers/gpu/drm/i915/display/intel_tc.c struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); base 415 drivers/gpu/drm/i915/display/intel_tc.c struct intel_encoder *encoder = &dig_port->base; base 423 drivers/gpu/drm/i915/display/intel_tc.c else if (encoder->base.crtc) base 424 drivers/gpu/drm/i915/display/intel_tc.c active_links = to_intel_crtc(encoder->base.crtc)->active; base 476 drivers/gpu/drm/i915/display/intel_tc.c struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); base 498 drivers/gpu/drm/i915/display/intel_tc.c struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); base 530 drivers/gpu/drm/i915/display/intel_tc.c struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); base 531 drivers/gpu/drm/i915/display/intel_tc.c enum port port = dig_port->base.port; base 50 drivers/gpu/drm/i915/display/intel_tv.c struct intel_encoder base; base 868 drivers/gpu/drm/i915/display/intel_tv.c struct drm_connector_state base; base 881 drivers/gpu/drm/i915/display/intel_tv.c #define to_intel_tv_connector_state(x) container_of(x, struct intel_tv_connector_state, base) base 892 drivers/gpu/drm/i915/display/intel_tv.c __drm_atomic_helper_connector_duplicate_state(connector, &state->base); base 893 drivers/gpu/drm/i915/display/intel_tv.c return &state->base; base 898 drivers/gpu/drm/i915/display/intel_tv.c return container_of(encoder, struct intel_tv, base); base 909 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 922 drivers/gpu/drm/i915/display/intel_tv.c struct drm_device *dev = encoder->base.dev; base 927 drivers/gpu/drm/i915/display/intel_tv.c to_intel_crtc(pipe_config->base.crtc)->pipe); base 937 drivers/gpu/drm/i915/display/intel_tv.c struct drm_device *dev = encoder->base.dev; base 1087 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1089 drivers/gpu/drm/i915/display/intel_tv.c &pipe_config->base.adjusted_mode; base 1187 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1192 drivers/gpu/drm/i915/display/intel_tv.c &pipe_config->base.adjusted_mode; base 1420 drivers/gpu/drm/i915/display/intel_tv.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1421 drivers/gpu/drm/i915/display/intel_tv.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); base 1698 drivers/gpu/drm/i915/display/intel_tv.c connector->base.id, connector->name, base 1916 drivers/gpu/drm/i915/display/intel_tv.c intel_encoder = &intel_tv->base; base 1917 drivers/gpu/drm/i915/display/intel_tv.c connector = &intel_connector->base; base 1935 drivers/gpu/drm/i915/display/intel_tv.c drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs, base 1953 drivers/gpu/drm/i915/display/intel_tv.c intel_encoder->base.possible_crtcs = ((1 << 0) | (1 << 1)); base 1979 drivers/gpu/drm/i915/display/intel_tv.c drm_object_attach_property(&connector->base, dev->mode_config.tv_mode_property, base 1981 drivers/gpu/drm/i915/display/intel_tv.c drm_object_attach_property(&connector->base, base 1984 drivers/gpu/drm/i915/display/intel_tv.c drm_object_attach_property(&connector->base, base 1987 drivers/gpu/drm/i915/display/intel_tv.c drm_object_attach_property(&connector->base, base 1990 drivers/gpu/drm/i915/display/intel_tv.c drm_object_attach_property(&connector->base, base 332 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; base 333 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; base 462 drivers/gpu/drm/i915/display/intel_vdsc.c struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev); base 486 drivers/gpu/drm/i915/display/intel_vdsc.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 487 drivers/gpu/drm/i915/display/intel_vdsc.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 886 drivers/gpu/drm/i915/display/intel_vdsc.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 905 drivers/gpu/drm/i915/display/intel_vdsc.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 906 drivers/gpu/drm/i915/display/intel_vdsc.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 941 drivers/gpu/drm/i915/display/intel_vdsc.c struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); base 942 drivers/gpu/drm/i915/display/intel_vdsc.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 79 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_encoder *encoder = &intel_dsi->base.base; base 126 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; base 215 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_encoder *encoder = &intel_dsi->base.base; base 260 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 262 drivers/gpu/drm/i915/display/vlv_dsi.c base); base 264 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 266 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 321 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 322 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 369 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 370 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 440 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 441 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 467 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 468 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 506 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 518 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 519 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 548 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 549 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 581 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 582 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 626 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 627 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 628 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 682 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_device *dev = encoder->base.dev; base 684 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 748 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 749 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_crtc *crtc = pipe_config->base.crtc; base 853 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 876 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 888 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 889 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 958 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 959 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1032 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_device *dev = encoder->base.dev; base 1035 drivers/gpu/drm/i915/display/vlv_dsi.c &pipe_config->base.adjusted_mode; base 1037 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); base 1038 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1048 drivers/gpu/drm/i915/display/vlv_dsi.c adjusted_mode_sw = &crtc->config->base.adjusted_mode; base 1193 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1207 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->base.adjusted_mode.crtc_clock = pclk; base 1315 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_encoder *encoder = &intel_encoder->base; base 1318 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); base 1320 drivers/gpu/drm/i915/display/vlv_dsi.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; base 1508 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 1509 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 1569 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1583 drivers/gpu/drm/i915/display/vlv_dsi.c plane = to_intel_plane(crtc->base.primary); base 1607 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1621 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_i915_private *dev_priv = to_i915(connector->base.dev); base 1630 drivers/gpu/drm/i915/display/vlv_dsi.c drm_connector_attach_scaling_mode_property(&connector->base, base 1633 drivers/gpu/drm/i915/display/vlv_dsi.c connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; base 1635 drivers/gpu/drm/i915/display/vlv_dsi.c connector->base.display_info.panel_orientation = base 1638 drivers/gpu/drm/i915/display/vlv_dsi.c &connector->base, base 1653 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_device *dev = intel_dsi->base.base.dev; base 1844 drivers/gpu/drm/i915/display/vlv_dsi.c intel_encoder = &intel_dsi->base; base 1845 drivers/gpu/drm/i915/display/vlv_dsi.c encoder = &intel_encoder->base; base 1848 drivers/gpu/drm/i915/display/vlv_dsi.c connector = &intel_connector->base; base 1963 drivers/gpu/drm/i915/display/vlv_dsi.c drm_connector_cleanup(&intel_connector->base); base 1965 drivers/gpu/drm/i915/display/vlv_dsi.c drm_encoder_cleanup(&intel_encoder->base); base 119 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 120 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 150 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 182 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 236 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 257 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 258 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 324 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 325 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 343 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 344 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 457 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 458 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 505 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); base 506 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); base 519 drivers/gpu/drm/i915/display/vlv_dsi_pll.c bxt_dsi_program_clocks(encoder->base.dev, port, config); base 521 drivers/gpu/drm/i915/display/vlv_dsi_pll.c glk_dsi_program_esc_clock(encoder->base.dev, config); base 542 drivers/gpu/drm/i915/display/vlv_dsi_pll.c struct drm_device *dev = encoder->base.dev; base 113 drivers/gpu/drm/i915/gem/i915_gem_busy.c seq = raw_read_seqcount(&obj->base.resv->seq); base 117 drivers/gpu/drm/i915/gem/i915_gem_busy.c busy_check_writer(rcu_dereference(obj->base.resv->fence_excl)); base 120 drivers/gpu/drm/i915/gem/i915_gem_busy.c list = rcu_dereference(obj->base.resv->fence); base 132 drivers/gpu/drm/i915/gem/i915_gem_busy.c if (args->busy && read_seqcount_retry(&obj->base.resv->seq, seq)) base 15 drivers/gpu/drm/i915/gem/i915_gem_clflush.c struct dma_fence_work base; base 26 drivers/gpu/drm/i915/gem/i915_gem_clflush.c static int clflush_work(struct dma_fence_work *base) base 28 drivers/gpu/drm/i915/gem/i915_gem_clflush.c struct clflush *clflush = container_of(base, typeof(*clflush), base); base 44 drivers/gpu/drm/i915/gem/i915_gem_clflush.c static void clflush_release(struct dma_fence_work *base) base 46 drivers/gpu/drm/i915/gem/i915_gem_clflush.c struct clflush *clflush = container_of(base, typeof(*clflush), base); base 68 drivers/gpu/drm/i915/gem/i915_gem_clflush.c dma_fence_work_init(&clflush->base, &clflush_ops); base 111 drivers/gpu/drm/i915/gem/i915_gem_clflush.c i915_sw_fence_await_reservation(&clflush->base.chain, base 112 drivers/gpu/drm/i915/gem/i915_gem_clflush.c obj->base.resv, NULL, true, base 115 drivers/gpu/drm/i915/gem/i915_gem_clflush.c dma_resv_add_excl_fence(obj->base.resv, &clflush->base.dma); base 116 drivers/gpu/drm/i915/gem/i915_gem_clflush.c dma_fence_work_commit(&clflush->base); base 297 drivers/gpu/drm/i915/gem/i915_gem_client_blt.c obj->base.resv, NULL, base 303 drivers/gpu/drm/i915/gem/i915_gem_client_blt.c dma_resv_add_excl_fence(obj->base.resv, &work->dma); base 83 drivers/gpu/drm/i915/gem/i915_gem_context.c struct i915_global base; base 110 drivers/gpu/drm/i915/gem/i915_gem_context.c if (!kref_get_unless_zero(&obj->base.refcount)) base 849 drivers/gpu/drm/i915/gem/i915_gem_context.c struct i915_active base; base 854 drivers/gpu/drm/i915/gem/i915_gem_context.c static void cb_retire(struct i915_active *base) base 856 drivers/gpu/drm/i915/gem/i915_gem_context.c struct context_barrier_task *cb = container_of(base, typeof(*cb), base); base 861 drivers/gpu/drm/i915/gem/i915_gem_context.c i915_active_fini(&cb->base); base 886 drivers/gpu/drm/i915/gem/i915_gem_context.c i915_active_init(i915, &cb->base, NULL, cb_retire); base 887 drivers/gpu/drm/i915/gem/i915_gem_context.c err = i915_active_acquire(&cb->base); base 918 drivers/gpu/drm/i915/gem/i915_gem_context.c err = i915_active_ref(&cb->base, rq->timeline, rq); base 929 drivers/gpu/drm/i915/gem/i915_gem_context.c i915_active_release(&cb->base); base 988 drivers/gpu/drm/i915/gem/i915_gem_context.c u32 base = engine->mmio_base; base 1002 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0)); base 1004 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0)); base 1020 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i)); base 1022 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i)); base 1363 drivers/gpu/drm/i915/gem/i915_gem_context.c set_engines__load_balance(struct i915_user_extension __user *base, void *data) base 1366 drivers/gpu/drm/i915/gem/i915_gem_context.c container_of_user(base, typeof(*ext), base); base 1455 drivers/gpu/drm/i915/gem/i915_gem_context.c set_engines__bond(struct i915_user_extension __user *base, void *data) base 1458 drivers/gpu/drm/i915/gem/i915_gem_context.c container_of_user(base, typeof(*ext), base); base 2409 drivers/gpu/drm/i915/gem/i915_gem_context.c i915_global_register(&global.base); base 101 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c if (page_num >= obj->base.size >> PAGE_SHIFT) base 135 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c if (obj->base.size < vma->vm_end - vma->vm_start) base 138 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c if (!obj->base.filp) base 141 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c ret = call_mmap(obj->base.filp, vma); base 146 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c vma->vm_file = get_file(obj->base.filp); base 216 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c exp_info.resv = obj->base.resv; base 232 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c pages = dma_buf_map_attachment(obj->base.import_attach, base 247 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c dma_buf_unmap_attachment(obj->base.import_attach, pages, base 267 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c if (obj->base.dev == dev) { base 272 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c return &i915_gem_object_get(obj)->base; base 289 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drm_gem_private_object_init(dev, &obj->base, dma_buf->size); base 291 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c obj->base.import_attach = attach; base 292 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c obj->base.resv = dma_buf->resv; base 304 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c return &obj->base; base 224 drivers/gpu/drm/i915/gem/i915_gem_domain.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 440 drivers/gpu/drm/i915/gem/i915_gem_domain.c HAS_WT(to_i915(obj->base.dev)) ? base 484 drivers/gpu/drm/i915/gem/i915_gem_domain.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 936 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c GEM_BUG_ON(cache->rq_size >= obj->base.size / sizeof(u32)); base 75 drivers/gpu/drm/i915/gem/i915_gem_fence.c obj->base.resv, NULL, base 80 drivers/gpu/drm/i915/gem/i915_gem_fence.c dma_resv_add_excl_fence(obj->base.resv, &stub->dma); base 37 drivers/gpu/drm/i915/gem/i915_gem_internal.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 71 drivers/gpu/drm/i915/gem/i915_gem_internal.c npages = obj->base.size / PAGE_SIZE; base 181 drivers/gpu/drm/i915/gem/i915_gem_internal.c if (overflows_type(size, obj->base.size)) base 188 drivers/gpu/drm/i915/gem/i915_gem_internal.c drm_gem_private_object_init(&i915->drm, &obj->base, size); base 71 drivers/gpu/drm/i915/gem/i915_gem_mman.c if (!obj->base.filp) { base 76 drivers/gpu/drm/i915/gem/i915_gem_mman.c if (range_overflows(args->offset, args->size, (u64)obj->base.size)) { base 81 drivers/gpu/drm/i915/gem/i915_gem_mman.c addr = vm_mmap(obj->base.filp, 0, args->size, base 96 drivers/gpu/drm/i915/gem/i915_gem_mman.c if (vma && __vma_matches(vma, obj->base.filp, addr, args->size)) base 190 drivers/gpu/drm/i915/gem/i915_gem_mman.c (obj->base.size >> PAGE_SHIFT) - view.partial.offset); base 193 drivers/gpu/drm/i915/gem/i915_gem_mman.c if (chunk >= obj->base.size >> PAGE_SHIFT) base 222 drivers/gpu/drm/i915/gem/i915_gem_mman.c struct drm_device *dev = obj->base.dev; base 383 drivers/gpu/drm/i915/gem/i915_gem_mman.c drm_vma_node_unmap(&obj->base.vma_node, base 384 drivers/gpu/drm/i915/gem/i915_gem_mman.c obj->base.dev->anon_inode->i_mapping); base 406 drivers/gpu/drm/i915/gem/i915_gem_mman.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 441 drivers/gpu/drm/i915/gem/i915_gem_mman.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 444 drivers/gpu/drm/i915/gem/i915_gem_mman.c err = drm_gem_create_mmap_offset(&obj->base); base 457 drivers/gpu/drm/i915/gem/i915_gem_mman.c err = drm_gem_create_mmap_offset(&obj->base); base 486 drivers/gpu/drm/i915/gem/i915_gem_mman.c *offset = drm_vma_node_offset_addr(&obj->base.vma_node); base 35 drivers/gpu/drm/i915/gem/i915_gem_object.c struct i915_global base; base 83 drivers/gpu/drm/i915/gem/i915_gem_object.c else if (HAS_LLC(to_i915(obj->base.dev))) base 141 drivers/gpu/drm/i915/gem/i915_gem_object.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 143 drivers/gpu/drm/i915/gem/i915_gem_object.c dma_resv_fini(&obj->base._resv); base 183 drivers/gpu/drm/i915/gem/i915_gem_object.c if (obj->base.import_attach) base 184 drivers/gpu/drm/i915/gem/i915_gem_object.c drm_prime_gem_destroy(&obj->base, NULL); base 186 drivers/gpu/drm/i915/gem/i915_gem_object.c drm_gem_free_mmap_offset(&obj->base); base 216 drivers/gpu/drm/i915/gem/i915_gem_object.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 328 drivers/gpu/drm/i915/gem/i915_gem_object.c i915_global_register(&global.base); base 76 drivers/gpu/drm/i915/gem/i915_gem_object.h if (obj && !kref_get_unless_zero(&obj->base.refcount)) base 91 drivers/gpu/drm/i915/gem/i915_gem_object.h drm_gem_object_get(&obj->base); base 99 drivers/gpu/drm/i915/gem/i915_gem_object.h __drm_gem_object_put(&obj->base); base 102 drivers/gpu/drm/i915/gem/i915_gem_object.h #define assert_object_held(obj) dma_resv_assert_held((obj)->base.resv) base 106 drivers/gpu/drm/i915/gem/i915_gem_object.h dma_resv_lock(obj->base.resv, NULL); base 112 drivers/gpu/drm/i915/gem/i915_gem_object.h return dma_resv_lock_interruptible(obj->base.resv, NULL); base 117 drivers/gpu/drm/i915/gem/i915_gem_object.h dma_resv_unlock(obj->base.resv); base 128 drivers/gpu/drm/i915/gem/i915_gem_object.h obj->base.vma_node.readonly = true; base 134 drivers/gpu/drm/i915/gem/i915_gem_object.h return obj->base.vma_node.readonly; base 330 drivers/gpu/drm/i915/gem/i915_gem_object.h __i915_gem_object_flush_map(obj, 0, obj->base.size); base 376 drivers/gpu/drm/i915/gem/i915_gem_object.h fence = dma_resv_get_excl_rcu(obj->base.resv); base 317 drivers/gpu/drm/i915/gem/i915_gem_object_blt.c struct drm_gem_object *objs[] = { &src->base, &dst->base }; base 65 drivers/gpu/drm/i915/gem/i915_gem_object_types.h struct drm_gem_object base; base 249 drivers/gpu/drm/i915/gem/i915_gem_object_types.h BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base)); base 251 drivers/gpu/drm/i915/gem/i915_gem_object_types.h return container_of(gem, struct drm_i915_gem_object, base); base 15 drivers/gpu/drm/i915/gem/i915_gem_pages.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 66 drivers/gpu/drm/i915/gem/i915_gem_pages.c i915->mm.shrink_memory += obj->base.size; base 127 drivers/gpu/drm/i915/gem/i915_gem_pages.c drm_gem_free_mmap_offset(&obj->base); base 230 drivers/gpu/drm/i915/gem/i915_gem_pages.c unsigned long n_pages = obj->base.size >> PAGE_SHIFT; base 354 drivers/gpu/drm/i915/gem/i915_gem_pages.c GEM_BUG_ON(range_overflows_t(typeof(obj->base.size), base 355 drivers/gpu/drm/i915/gem/i915_gem_pages.c offset, size, obj->base.size)); base 367 drivers/gpu/drm/i915/gem/i915_gem_pages.c if (size == obj->base.size) { base 383 drivers/gpu/drm/i915/gem/i915_gem_pages.c GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); base 473 drivers/gpu/drm/i915/gem/i915_gem_pages.c unsigned long base = xa_to_value(sg); base 475 drivers/gpu/drm/i915/gem/i915_gem_pages.c sg = radix_tree_lookup(&iter->radix, base); base 478 drivers/gpu/drm/i915/gem/i915_gem_pages.c *offset = n - base; base 23 drivers/gpu/drm/i915/gem/i915_gem_phys.c struct address_space *mapping = obj->base.filp->f_mapping; base 39 drivers/gpu/drm/i915/gem/i915_gem_phys.c vaddr = dma_alloc_coherent(&obj->base.dev->pdev->dev, base 40 drivers/gpu/drm/i915/gem/i915_gem_phys.c roundup_pow_of_two(obj->base.size), base 54 drivers/gpu/drm/i915/gem/i915_gem_phys.c sg->length = obj->base.size; base 58 drivers/gpu/drm/i915/gem/i915_gem_phys.c sg_dma_len(sg) = obj->base.size; base 61 drivers/gpu/drm/i915/gem/i915_gem_phys.c for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { base 78 drivers/gpu/drm/i915/gem/i915_gem_phys.c intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt); base 87 drivers/gpu/drm/i915/gem/i915_gem_phys.c dma_free_coherent(&obj->base.dev->pdev->dev, base 88 drivers/gpu/drm/i915/gem/i915_gem_phys.c roundup_pow_of_two(obj->base.size), base 103 drivers/gpu/drm/i915/gem/i915_gem_phys.c struct address_space *mapping = obj->base.filp->f_mapping; base 107 drivers/gpu/drm/i915/gem/i915_gem_phys.c for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { base 133 drivers/gpu/drm/i915/gem/i915_gem_phys.c dma_free_coherent(&obj->base.dev->pdev->dev, base 134 drivers/gpu/drm/i915/gem/i915_gem_phys.c roundup_pow_of_two(obj->base.size), base 140 drivers/gpu/drm/i915/gem/i915_gem_phys.c fput(obj->base.filp); base 155 drivers/gpu/drm/i915/gem/i915_gem_phys.c if (align > obj->base.size) base 217 drivers/gpu/drm/i915/gem/i915_gem_pm.c if (!kref_get_unless_zero(&obj->base.refcount)) base 28 drivers/gpu/drm/i915/gem/i915_gem_shmem.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 29 drivers/gpu/drm/i915/gem/i915_gem_shmem.c const unsigned long page_count = obj->base.size / PAGE_SIZE; base 74 drivers/gpu/drm/i915/gem/i915_gem_shmem.c mapping = obj->base.filp->f_mapping; base 225 drivers/gpu/drm/i915/gem/i915_gem_shmem.c shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); base 249 drivers/gpu/drm/i915/gem/i915_gem_shmem.c mapping = obj->base.filp->f_mapping; base 252 drivers/gpu/drm/i915/gem/i915_gem_shmem.c for (i = 0; i < obj->base.size >> PAGE_SHIFT; i++) { base 307 drivers/gpu/drm/i915/gem/i915_gem_shmem.c mapping_clear_unevictable(file_inode(obj->base.filp)->i_mapping); base 332 drivers/gpu/drm/i915/gem/i915_gem_shmem.c struct address_space *mapping = obj->base.filp->f_mapping; base 387 drivers/gpu/drm/i915/gem/i915_gem_shmem.c err = pagecache_write_begin(obj->base.filp, mapping, base 399 drivers/gpu/drm/i915/gem/i915_gem_shmem.c err = pagecache_write_end(obj->base.filp, mapping, base 420 drivers/gpu/drm/i915/gem/i915_gem_shmem.c fput(obj->base.filp); base 475 drivers/gpu/drm/i915/gem/i915_gem_shmem.c if (overflows_type(size, obj->base.size)) base 482 drivers/gpu/drm/i915/gem/i915_gem_shmem.c ret = create_shmem(i915, &obj->base, size); base 493 drivers/gpu/drm/i915/gem/i915_gem_shmem.c mapping = obj->base.filp->f_mapping; base 546 drivers/gpu/drm/i915/gem/i915_gem_shmem.c file = obj->base.filp; base 250 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c if (!kref_get_unless_zero(&obj->base.refcount)) base 261 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c count += obj->base.size >> PAGE_SHIFT; base 266 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c scanned += obj->base.size >> PAGE_SHIFT; base 406 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c unevictable += obj->base.size >> PAGE_SHIFT; base 408 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c available += obj->base.size >> PAGE_SHIFT; base 522 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c #define obj_to_i915(obj__) to_i915((obj__)->base.dev) base 541 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c i915->mm.shrink_memory -= obj->base.size; base 558 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c GEM_BUG_ON(!kref_read(&obj->base.refcount)); base 562 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c i915->mm.shrink_memory += obj->base.size; base 162 drivers/gpu/drm/i915/gem/i915_gem_stolen.c resource_size_t *base, base 186 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16; base 187 drivers/gpu/drm/i915/gem/i915_gem_stolen.c WARN_ON((reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base); base 189 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *size = stolen_top - *base; base 193 drivers/gpu/drm/i915/gem/i915_gem_stolen.c resource_size_t *base, base 203 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK; base 225 drivers/gpu/drm/i915/gem/i915_gem_stolen.c resource_size_t *base, base 249 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = stolen_top - *size; base 253 drivers/gpu/drm/i915/gem/i915_gem_stolen.c resource_size_t *base, base 263 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = reg_val & GEN7_STOLEN_RESERVED_ADDR_MASK; base 279 drivers/gpu/drm/i915/gem/i915_gem_stolen.c resource_size_t *base, base 289 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK; base 311 drivers/gpu/drm/i915/gem/i915_gem_stolen.c resource_size_t *base, base 325 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK; base 326 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *size = stolen_top - *base; base 330 drivers/gpu/drm/i915/gem/i915_gem_stolen.c resource_size_t *base, base 337 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK; base 510 drivers/gpu/drm/i915/gem/i915_gem_stolen.c i915_pages_create_for_stolen(obj->base.dev, base 532 drivers/gpu/drm/i915/gem/i915_gem_stolen.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); base 558 drivers/gpu/drm/i915/gem/i915_gem_stolen.c drm_gem_private_object_init(&dev_priv->drm, &obj->base, stolen->size); base 120 drivers/gpu/drm/i915/gem/i915_gem_tiling.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 206 drivers/gpu/drm/i915/gem/i915_gem_tiling.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 287 drivers/gpu/drm/i915/gem/i915_gem_tiling.c obj->bit_17 = bitmap_zalloc(obj->base.size >> PAGE_SHIFT, base 126 drivers/gpu/drm/i915/gem/i915_gem_userptr.c if (!kref_get_unless_zero(&obj->base.refcount)) { base 278 drivers/gpu/drm/i915/gem/i915_gem_userptr.c mo->it.last = obj->userptr.ptr + obj->base.size - 1; base 345 drivers/gpu/drm/i915/gem/i915_gem_userptr.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); base 369 drivers/gpu/drm/i915/gem/i915_gem_userptr.c mm->i915 = to_i915(obj->base.dev); base 418 drivers/gpu/drm/i915/gem/i915_gem_userptr.c &to_i915(obj->base.dev)->mm_lock); base 476 drivers/gpu/drm/i915/gem/i915_gem_userptr.c const unsigned long npages = obj->base.size >> PAGE_SHIFT; base 575 drivers/gpu/drm/i915/gem/i915_gem_userptr.c queue_work(to_i915(obj->base.dev)->mm.userptr_wq, &work->work); base 582 drivers/gpu/drm/i915/gem/i915_gem_userptr.c const unsigned long num_pages = obj->base.size >> PAGE_SHIFT; base 824 drivers/gpu/drm/i915/gem/i915_gem_userptr.c drm_gem_private_object_init(dev, &obj->base, args->user_size); base 842 drivers/gpu/drm/i915/gem/i915_gem_userptr.c ret = drm_gem_handle_create(file, &obj->base, &handle); base 143 drivers/gpu/drm/i915/gem/i915_gem_wait.c ret = dma_resv_get_fences_rcu(obj->base.resv, base 155 drivers/gpu/drm/i915/gem/i915_gem_wait.c excl = dma_resv_get_excl_rcu(obj->base.resv); base 179 drivers/gpu/drm/i915/gem/i915_gem_wait.c timeout = i915_gem_object_wait_reservation(obj->base.resv, base 28 drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c const unsigned long npages = obj->base.size / PAGE_SIZE; base 106 drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c if (overflows_type(dma_size, obj->base.size)) base 113 drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c drm_gem_private_object_init(&i915->drm, &obj->base, dma_size); base 24 drivers/gpu/drm/i915/gem/selftests/huge_gem_object.h return obj->base.size; base 69 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (sg_alloc_table(st, obj->base.size >> PAGE_SHIFT, GFP)) { base 74 drivers/gpu/drm/i915/gem/selftests/huge_pages.c rem = obj->base.size; base 161 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (overflows_type(size, obj->base.size)) base 168 drivers/gpu/drm/i915/gem/selftests/huge_pages.c drm_gem_private_object_init(&i915->drm, &obj->base, size); base 182 drivers/gpu/drm/i915/gem/selftests/huge_pages.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 193 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (sg_alloc_table(st, obj->base.size >> PAGE_SHIFT, GFP)) { base 199 drivers/gpu/drm/i915/gem/selftests/huge_pages.c rem = obj->base.size; base 239 drivers/gpu/drm/i915/gem/selftests/huge_pages.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 256 drivers/gpu/drm/i915/gem/selftests/huge_pages.c page_size = get_largest_page_size(i915, obj->base.size); base 260 drivers/gpu/drm/i915/gem/selftests/huge_pages.c sg->length = obj->base.size; base 261 drivers/gpu/drm/i915/gem/selftests/huge_pages.c sg_dma_len(sg) = obj->base.size; base 310 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (overflows_type(size, obj->base.size)) base 317 drivers/gpu/drm/i915/gem/selftests/huge_pages.c drm_gem_private_object_init(&i915->drm, &obj->base, size); base 403 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (obj->base.size != combination) { base 405 drivers/gpu/drm/i915/gem/selftests/huge_pages.c obj->base.size, combination); base 481 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (obj->base.size != size) { base 483 drivers/gpu/drm/i915/gem/selftests/huge_pages.c obj->base.size, size); base 622 drivers/gpu/drm/i915/gem/selftests/huge_pages.c if (obj->base.size != size) { base 624 drivers/gpu/drm/i915/gem/selftests/huge_pages.c obj->base.size, size); base 698 drivers/gpu/drm/i915/gem/selftests/huge_pages.c obj->base.size, yesno(!!single)); base 705 drivers/gpu/drm/i915/gem/selftests/huge_pages.c __func__, obj->base.size)) base 910 drivers/gpu/drm/i915/gem/selftests/huge_pages.c for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) { base 990 drivers/gpu/drm/i915/gem/selftests/huge_pages.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 1007 drivers/gpu/drm/i915/gem/selftests/huge_pages.c size = obj->base.size; base 183 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 178 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c GEM_BUG_ON(obj->base.size > vm->total); base 217 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c const bool has_llc = HAS_LLC(to_i915(obj->base.dev)); base 295 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c GEM_BUG_ON(obj->base.handle_count); base 298 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c err = idr_alloc(&file->object_idr, &obj->base, 1, 0, GFP_KERNEL); base 303 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c obj->base.handle_count++; base 23 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c dmabuf = i915_gem_prime_export(&obj->base, 0); base 47 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c dmabuf = i915_gem_prime_export(&obj->base, 0); base 63 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c if (import != &obj->base) { base 100 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c if (obj->base.dev != &i915->drm) { base 106 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c if (obj->base.size != PAGE_SIZE) { base 108 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c (long long)obj->base.size, PAGE_SIZE); base 222 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c dmabuf = i915_gem_prime_export(&obj->base, 0); base 269 drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c dmabuf = i915_gem_prime_export(&obj->base, 0); base 82 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c const unsigned long npages = obj->base.size / PAGE_SIZE; base 144 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c if (offset >= obj->base.size) base 147 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c intel_gt_flush_ggtt_writes(&to_i915(obj->base.dev)->gt); base 204 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c nreal, obj->base.size / PAGE_SIZE, err); base 330 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 53 drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c nreal, obj->base.size / PAGE_SIZE, err); base 57 drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c for (n = 0; n < obj->base.size / PAGE_SIZE; n++) { base 11 drivers/gpu/drm/i915/gem/selftests/mock_gem_object.h struct drm_i915_gem_object base; base 18 drivers/gpu/drm/i915/gt/intel_context.c struct i915_global base; base 276 drivers/gpu/drm/i915/gt/intel_context.c i915_global_register(&global.base); base 66 drivers/gpu/drm/i915/gt/intel_engine_cs.c u32 base : 24; base 76 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 1, .base = RENDER_RING_BASE } base 84 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 6, .base = BLT_RING_BASE } base 92 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 11, .base = GEN11_BSD_RING_BASE }, base 93 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 6, .base = GEN6_BSD_RING_BASE }, base 94 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 4, .base = BSD_RING_BASE } base 102 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 11, .base = GEN11_BSD2_RING_BASE }, base 103 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 8, .base = GEN8_BSD2_RING_BASE } base 111 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 11, .base = GEN11_BSD3_RING_BASE } base 119 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 11, .base = GEN11_BSD4_RING_BASE } base 127 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 11, .base = GEN11_VEBOX_RING_BASE }, base 128 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 7, .base = VEBOX_RING_BASE } base 136 drivers/gpu/drm/i915/gt/intel_engine_cs.c { .gen = 11, .base = GEN11_VEBOX2_RING_BASE } base 234 drivers/gpu/drm/i915/gt/intel_engine_cs.c GEM_BUG_ON(!bases[i].base); base 236 drivers/gpu/drm/i915/gt/intel_engine_cs.c return bases[i].base; base 857 drivers/gpu/drm/i915/gt/intel_engine_cs.c const u32 base = engine->mmio_base; base 858 drivers/gpu/drm/i915/gt/intel_engine_cs.c const i915_reg_t mode = RING_MI_MODE(base); base 46 drivers/gpu/drm/i915/gt/intel_engine_pool.c struct dma_resv *resv = node->obj->base.resv; base 69 drivers/gpu/drm/i915/gt/intel_engine_pool.c struct list_head *list = bucket_for_size(pool, node->obj->base.size); base 127 drivers/gpu/drm/i915/gt/intel_engine_pool.c if (node->obj->base.size < size) base 154 drivers/gpu/drm/i915/gt/intel_engine_user.c u8 base, max; base 168 drivers/gpu/drm/i915/gt/intel_engine_user.c return map[ring->class].base + ring->instance; base 182 drivers/gpu/drm/i915/gt/intel_lrc.c struct intel_engine_cs base; base 226 drivers/gpu/drm/i915/gt/intel_lrc.c return container_of(engine, struct virtual_engine, base); base 600 drivers/gpu/drm/i915/gt/intel_lrc.c tasklet_schedule(&ve->base.execlists.tasklet); base 841 drivers/gpu/drm/i915/gt/intel_lrc.c u32 base = engine->mmio_base; base 846 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_CONTEXT_CONTROL(base)); base 847 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_RING_HEAD] = i915_mmio_reg_offset(RING_HEAD(base)); base 848 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_RING_TAIL] = i915_mmio_reg_offset(RING_TAIL(base)); base 849 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_RING_BUFFER_START] = i915_mmio_reg_offset(RING_START(base)); base 850 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_RING_BUFFER_CONTROL] = i915_mmio_reg_offset(RING_CTL(base)); base 852 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_BB_HEAD_U] = i915_mmio_reg_offset(RING_BBADDR_UDW(base)); base 853 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_BB_HEAD_L] = i915_mmio_reg_offset(RING_BBADDR(base)); base 854 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_BB_STATE] = i915_mmio_reg_offset(RING_BBSTATE(base)); base 856 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_SBBADDR_UDW(base)); base 857 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_SECOND_BB_HEAD_L] = i915_mmio_reg_offset(RING_SBBADDR(base)); base 858 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_SECOND_BB_STATE] = i915_mmio_reg_offset(RING_SBBSTATE(base)); base 861 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_CTX_TIMESTAMP(base)); base 862 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP3_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 3)); base 863 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP3_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 3)); base 864 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP2_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 2)); base 865 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP2_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 2)); base 866 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP1_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 1)); base 867 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP1_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 1)); base 868 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP0_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0)); base 869 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP0_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0)); base 873 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_INDIRECT_CTX(base)); base 875 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(base)); base 877 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(base)); base 1172 drivers/gpu/drm/i915/gt/intel_lrc.c spin_lock(&ve->base.active.lock); base 1176 drivers/gpu/drm/i915/gt/intel_lrc.c spin_unlock(&ve->base.active.lock); base 1184 drivers/gpu/drm/i915/gt/intel_lrc.c GEM_BUG_ON(rq->engine != &ve->base); base 1189 drivers/gpu/drm/i915/gt/intel_lrc.c spin_unlock(&ve->base.active.lock); base 1195 drivers/gpu/drm/i915/gt/intel_lrc.c spin_unlock(&ve->base.active.lock); base 1209 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.execlists.queue_priority_hint = INT_MIN; base 1258 drivers/gpu/drm/i915/gt/intel_lrc.c spin_unlock(&ve->base.active.lock); base 1264 drivers/gpu/drm/i915/gt/intel_lrc.c spin_unlock(&ve->base.active.lock); base 1936 drivers/gpu/drm/i915/gt/intel_lrc.c u32 base = engine->mmio_base; base 1938 drivers/gpu/drm/i915/gt/intel_lrc.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i)); base 1940 drivers/gpu/drm/i915/gt/intel_lrc.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i)); base 2620 drivers/gpu/drm/i915/gt/intel_lrc.c spin_lock(&ve->base.active.lock); base 2629 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.execlists.queue_priority_hint = INT_MIN; base 2631 drivers/gpu/drm/i915/gt/intel_lrc.c spin_unlock(&ve->base.active.lock); base 3114 drivers/gpu/drm/i915/gt/intel_lrc.c u32 base = engine->mmio_base; base 3131 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base)); base 3133 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base)); base 3136 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_ELSP(base)); base 3195 drivers/gpu/drm/i915/gt/intel_lrc.c u32 base = engine->mmio_base; base 3210 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base), base 3218 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); base 3219 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); base 3220 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); base 3221 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), base 3223 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); base 3224 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); base 3225 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); base 3226 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); base 3227 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); base 3228 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); base 3232 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); base 3234 drivers/gpu/drm/i915/gt/intel_lrc.c RING_INDIRECT_CTX_OFFSET(base), 0); base 3246 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); base 3257 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); base 3259 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0); base 3260 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0); base 3261 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0); base 3262 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0); base 3263 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0); base 3264 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0); base 3265 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0); base 3266 drivers/gpu/drm/i915/gt/intel_lrc.c CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0); base 3415 drivers/gpu/drm/i915/gt/intel_lrc.c return &ve->base.execlists.default_priolist.requests[0]; base 3443 drivers/gpu/drm/i915/gt/intel_lrc.c GEM_BUG_ON(__tasklet_is_scheduled(&ve->base.execlists.tasklet)); base 3543 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.name, base 3545 drivers/gpu/drm/i915/gt/intel_lrc.c mask, ve->base.execlists.queue_priority_hint); base 3553 drivers/gpu/drm/i915/gt/intel_lrc.c const int prio = ve->base.execlists.queue_priority_hint; base 3637 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.name, base 3641 drivers/gpu/drm/i915/gt/intel_lrc.c GEM_BUG_ON(ve->base.submit_request != virtual_submit_request); base 3643 drivers/gpu/drm/i915/gt/intel_lrc.c spin_lock_irqsave(&ve->base.active.lock, flags); base 3655 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.execlists.queue_priority_hint = INT_MIN; base 3658 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.execlists.queue_priority_hint = rq_prio(rq); base 3664 drivers/gpu/drm/i915/gt/intel_lrc.c tasklet_schedule(&ve->base.execlists.tasklet); base 3667 drivers/gpu/drm/i915/gt/intel_lrc.c spin_unlock_irqrestore(&ve->base.active.lock, flags); base 3725 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.i915 = ctx->i915; base 3726 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.gt = siblings[0]->gt; base 3727 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.id = -1; base 3729 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.class = OTHER_CLASS; base 3730 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.uabi_class = I915_ENGINE_CLASS_INVALID; base 3731 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL; base 3732 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.uabi_instance = I915_ENGINE_CLASS_INVALID_VIRTUAL; base 3747 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.saturated = ALL_ENGINES; base 3749 drivers/gpu/drm/i915/gt/intel_lrc.c snprintf(ve->base.name, sizeof(ve->base.name), "virtual"); base 3751 drivers/gpu/drm/i915/gt/intel_lrc.c intel_engine_init_active(&ve->base, ENGINE_VIRTUAL); base 3753 drivers/gpu/drm/i915/gt/intel_lrc.c intel_engine_init_execlists(&ve->base); base 3755 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.cops = &virtual_context_ops; base 3756 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.request_alloc = execlists_request_alloc; base 3758 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.schedule = i915_schedule; base 3759 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.submit_request = virtual_submit_request; base 3760 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.bond_execute = virtual_bond_execute; base 3763 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.execlists.queue_priority_hint = INT_MIN; base 3764 drivers/gpu/drm/i915/gt/intel_lrc.c tasklet_init(&ve->base.execlists.tasklet, base 3768 drivers/gpu/drm/i915/gt/intel_lrc.c intel_context_init(&ve->context, ctx, &ve->base); base 3774 drivers/gpu/drm/i915/gt/intel_lrc.c if (sibling->mask & ve->base.mask) { base 3798 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.mask |= sibling->mask; base 3807 drivers/gpu/drm/i915/gt/intel_lrc.c if (ve->base.class != OTHER_CLASS) { base 3808 drivers/gpu/drm/i915/gt/intel_lrc.c if (ve->base.class != sibling->class) { base 3810 drivers/gpu/drm/i915/gt/intel_lrc.c sibling->class, ve->base.class); base 3817 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.class = sibling->class; base 3818 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.uabi_class = sibling->uabi_class; base 3819 drivers/gpu/drm/i915/gt/intel_lrc.c snprintf(ve->base.name, sizeof(ve->base.name), base 3820 drivers/gpu/drm/i915/gt/intel_lrc.c "v%dx%d", ve->base.class, count); base 3821 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.context_size = sibling->context_size; base 3823 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.emit_bb_start = sibling->emit_bb_start; base 3824 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.emit_flush = sibling->emit_flush; base 3825 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.emit_init_breadcrumb = sibling->emit_init_breadcrumb; base 3826 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.emit_fini_breadcrumb = sibling->emit_fini_breadcrumb; base 3827 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.emit_fini_breadcrumb_dw = base 3830 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.flags = sibling->flags; base 3833 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.flags |= I915_ENGINE_IS_VIRTUAL; base 38 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_ELSP(base) _MMIO((base) + 0x230) base 39 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) base 40 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) base 41 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) base 46 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) base 47 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) base 48 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) base 640 drivers/gpu/drm/i915/gt/intel_reset.c node = &vma->obj->base.vma_node; base 742 drivers/gpu/drm/i915/gt/intel_ringbuffer.c const u32 base = engine->mmio_base; base 764 drivers/gpu/drm/i915/gt/intel_ringbuffer.c RING_HEAD(base), base 765 drivers/gpu/drm/i915/gt/intel_ringbuffer.c intel_uncore_read_fw(uncore, RING_TAIL(base))); base 766 drivers/gpu/drm/i915/gt/intel_ringbuffer.c intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */ base 768 drivers/gpu/drm/i915/gt/intel_ringbuffer.c intel_uncore_write_fw(uncore, RING_HEAD(base), 0); base 769 drivers/gpu/drm/i915/gt/intel_ringbuffer.c intel_uncore_write_fw(uncore, RING_TAIL(base), 0); base 770 drivers/gpu/drm/i915/gt/intel_ringbuffer.c intel_uncore_posting_read_fw(uncore, RING_TAIL(base)); base 773 drivers/gpu/drm/i915/gt/intel_ringbuffer.c intel_uncore_write_fw(uncore, RING_CTL(base), 0); base 776 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (intel_uncore_read_fw(uncore, RING_HEAD(base))) base 779 drivers/gpu/drm/i915/gt/intel_ringbuffer.c intel_uncore_read_fw(uncore, RING_HEAD(base))); base 1237 drivers/gpu/drm/i915/gt/intel_workarounds.c const u32 base = engine->mmio_base; base 1246 drivers/gpu/drm/i915/gt/intel_workarounds.c RING_FORCE_TO_NONPRIV(base, i), base 1252 drivers/gpu/drm/i915/gt/intel_workarounds.c RING_FORCE_TO_NONPRIV(base, i), base 1253 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(RING_NOPID(base))); base 188 drivers/gpu/drm/i915/gt/mock_engine.c container_of(request->engine, typeof(*engine), base); base 249 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.i915 = i915; base 250 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.gt = &i915->gt; base 251 drivers/gpu/drm/i915/gt/mock_engine.c snprintf(engine->base.name, sizeof(engine->base.name), "%s", name); base 252 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.id = id; base 253 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.mask = BIT(id); base 254 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.instance = id; base 255 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.status_page.addr = (void *)(engine + 1); base 257 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.cops = &mock_context_ops; base 258 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.request_alloc = mock_request_alloc; base 259 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.emit_flush = mock_emit_flush; base 260 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.emit_fini_breadcrumb = mock_emit_breadcrumb; base 261 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.submit_request = mock_submit_request; base 263 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.reset.prepare = mock_reset_prepare; base 264 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.reset.reset = mock_reset; base 265 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.reset.finish = mock_reset_finish; base 266 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.cancel_requests = mock_cancel_requests; base 273 drivers/gpu/drm/i915/gt/mock_engine.c intel_engine_add_user(&engine->base); base 275 drivers/gpu/drm/i915/gt/mock_engine.c return &engine->base; base 303 drivers/gpu/drm/i915/gt/mock_engine.c container_of(engine, typeof(*mock), base); base 321 drivers/gpu/drm/i915/gt/mock_engine.c container_of(engine, typeof(*mock), base); base 35 drivers/gpu/drm/i915/gt/mock_engine.h struct intel_engine_cs base; base 19 drivers/gpu/drm/i915/gt/selftest_engine_cs.c u32 base = info->mmio_bases[j].base; base 33 drivers/gpu/drm/i915/gt/selftest_engine_cs.c if (!base) { base 38 drivers/gpu/drm/i915/gt/selftest_engine_cs.c base, gen, j); base 76 drivers/gpu/drm/i915/gt/selftest_workarounds.c const u32 base = engine->mmio_base; base 135 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); base 28 drivers/gpu/drm/i915/gt/uc/intel_guc.c GEM_BUG_ON(!guc->send_regs.base); base 32 drivers/gpu/drm/i915/gt/uc/intel_guc.c return _MMIO(guc->send_regs.base + 4 * i); base 42 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->send_regs.base = base 46 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); base 140 drivers/gpu/drm/i915/gt/uc/intel_guc.c u32 ctxnum, base; base 142 drivers/gpu/drm/i915/gt/uc/intel_guc.c base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool); base 145 drivers/gpu/drm/i915/gt/uc/intel_guc.c base >>= PAGE_SHIFT; base 146 drivers/gpu/drm/i915/gt/uc/intel_guc.c flags |= (base << GUC_CTL_BASE_ADDR_SHIFT) | base 64 drivers/gpu/drm/i915/gt/uc/intel_guc.h u32 base; base 73 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c u32 base; base 109 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c base = intel_guc_ggtt_offset(guc, guc->ads_vma); base 115 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool); base 119 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c blob->ads.scheduler_policies = base + ptr_offset(blob, policies); base 120 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer); base 121 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state); base 122 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c blob->ads.gt_system_info = base + ptr_offset(blob, system_info); base 123 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c blob->ads.clients_info = base + ptr_offset(blob, clients_info); base 202 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c u32 base; base 211 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c base = intel_guc_ggtt_offset(guc, ctch->vma); base 219 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c base + PAGE_SIZE/4 * i + PAGE_SIZE/2, base 228 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c base + PAGE_SIZE/4 * CTB_RECV, base 234 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c base + PAGE_SIZE/4 * CTB_SEND, base 157 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c relay_reserve(log->relay.channel, log->vma->obj->base.size); base 160 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr; base 162 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c return &base[client->stage_id]; base 354 drivers/gpu/drm/i915/gt/uc/intel_uc.c u32 base = intel_wopcm_guc_base(>->i915->wopcm); base 360 drivers/gpu/drm/i915/gt/uc/intel_uc.c if (unlikely(!base || !size)) { base 366 drivers/gpu/drm/i915/gt/uc/intel_uc.c GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK)); base 367 drivers/gpu/drm/i915/gt/uc/intel_uc.c GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK); base 383 drivers/gpu/drm/i915/gt/uc/intel_uc.c base | huc_agent, mask, base 384 drivers/gpu/drm/i915/gt/uc/intel_uc.c base | huc_agent | base 417 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c .node.size = obj->base.size, base 438 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c ggtt->vm.clear_range(&ggtt->vm, start, obj->base.size); base 1877 drivers/gpu/drm/i915/gvt/cmd_parser.c drm_clflush_virt_range(bb->va, bb->obj->base.size); base 42 drivers/gpu/drm/i915/gvt/dmabuf.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); base 58 drivers/gpu/drm/i915/gvt/dmabuf.c page_num = obj->base.size >> PAGE_SHIFT; base 135 drivers/gpu/drm/i915/gvt/dmabuf.c gem_obj->base.dma_buf = NULL; base 140 drivers/gpu/drm/i915/gvt/dmabuf.c gem_obj->base.dma_buf = NULL; base 162 drivers/gpu/drm/i915/gvt/dmabuf.c drm_gem_private_object_init(dev, &obj->base, base 221 drivers/gpu/drm/i915/gvt/dmabuf.c info->start = p.base; base 251 drivers/gpu/drm/i915/gvt/dmabuf.c info->start = c.base; base 494 drivers/gpu/drm/i915/gvt/dmabuf.c dmabuf = i915_gem_prime_export(&obj->base, DRM_CLOEXEC | DRM_RDWR); base 523 drivers/gpu/drm/i915/gvt/dmabuf.c kref_read(&obj->base.refcount)); base 247 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; base 248 drivers/gpu/drm/i915/gvt/fb_decoder.c if (!vgpu_gmadr_is_valid(vgpu, plane->base)) base 251 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); base 254 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base); base 370 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; base 371 drivers/gpu/drm/i915/gvt/fb_decoder.c if (!vgpu_gmadr_is_valid(vgpu, plane->base)) base 374 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); base 377 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base); base 474 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; base 475 drivers/gpu/drm/i915/gvt/fb_decoder.c if (!vgpu_gmadr_is_valid(vgpu, plane->base)) base 478 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); base 481 drivers/gpu/drm/i915/gvt/fb_decoder.c plane->base); base 108 drivers/gpu/drm/i915/gvt/fb_decoder.h u32 base; /* framebuffer base in graphics memory */ base 123 drivers/gpu/drm/i915/gvt/fb_decoder.h u32 base; /* sprite base in graphics memory */ base 139 drivers/gpu/drm/i915/gvt/fb_decoder.h u32 base; /* cursor base in graphics memory */ base 91 drivers/gpu/drm/i915/gvt/gvt.h u32 base; base 421 drivers/gpu/drm/i915/gvt/gvt.h #define vgpu_fence_base(vgpu) (vgpu->fence.base) base 1189 drivers/gpu/drm/i915/gvt/handlers.c case _vgtif_reg(avail_rs.mappable_gmadr.base) ... base 1881 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x28) base 1885 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x134) base 1889 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x6c) base 1906 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x29c) base 2744 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0xd0) base 2750 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x230) base 2754 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x234) base 2759 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x244) base 2763 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x370) base 2767 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x3a0) base 2786 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x270) base 3097 drivers/gpu/drm/i915/gvt/handlers.c #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) base 37 drivers/gpu/drm/i915/gvt/interrupt.c #define regbase_to_isr(base) (base) base 38 drivers/gpu/drm/i915/gvt/interrupt.c #define regbase_to_imr(base) (base + 0x4) base 39 drivers/gpu/drm/i915/gvt/interrupt.c #define regbase_to_iir(base) (base + 0x8) base 40 drivers/gpu/drm/i915/gvt/interrupt.c #define regbase_to_ier(base) (base + 0xC) base 414 drivers/gpu/drm/i915/gvt/kvmgt.c void *base = vgpu->vdev.region[i].data; base 422 drivers/gpu/drm/i915/gvt/kvmgt.c memcpy(buf, base + pos, count); base 583 drivers/gpu/drm/i915/gvt/kvmgt.c void *base; base 590 drivers/gpu/drm/i915/gvt/kvmgt.c base = vgpu_opregion(vgpu)->va; base 591 drivers/gpu/drm/i915/gvt/kvmgt.c if (!base) base 594 drivers/gpu/drm/i915/gvt/kvmgt.c if (memcmp(base, OPREGION_SIGNATURE, 16)) { base 595 drivers/gpu/drm/i915/gvt/kvmgt.c memunmap(base); base 603 drivers/gpu/drm/i915/gvt/kvmgt.c VFIO_REGION_INFO_FLAG_READ, base); base 612 drivers/gpu/drm/i915/gvt/kvmgt.c struct vfio_edid_region *base; base 615 drivers/gpu/drm/i915/gvt/kvmgt.c base = kzalloc(sizeof(*base), GFP_KERNEL); base 616 drivers/gpu/drm/i915/gvt/kvmgt.c if (!base) base 620 drivers/gpu/drm/i915/gvt/kvmgt.c base->vfio_edid_regs.edid_offset = EDID_BLOB_OFFSET; base 621 drivers/gpu/drm/i915/gvt/kvmgt.c base->vfio_edid_regs.edid_max_size = EDID_SIZE; base 622 drivers/gpu/drm/i915/gvt/kvmgt.c base->vfio_edid_regs.edid_size = EDID_SIZE; base 623 drivers/gpu/drm/i915/gvt/kvmgt.c base->vfio_edid_regs.max_xres = vgpu_edid_xres(port->id); base 624 drivers/gpu/drm/i915/gvt/kvmgt.c base->vfio_edid_regs.max_yres = vgpu_edid_yres(port->id); base 625 drivers/gpu/drm/i915/gvt/kvmgt.c base->edid_blob = port->edid->edid_block; base 633 drivers/gpu/drm/i915/gvt/kvmgt.c VFIO_REGION_INFO_FLAG_CAPS, base); base 127 drivers/gpu/drm/i915/gvt/reg.h #define RING_EXCC(base) _MMIO((base) + 0x28) base 128 drivers/gpu/drm/i915/gvt/reg.h #define RING_GFX_MODE(base) _MMIO((base) + 0x29c) base 483 drivers/gpu/drm/i915/gvt/scheduler.c bb->obj->base.size); base 505 drivers/gpu/drm/i915/gvt/scheduler.c bb->obj->base.size); base 51 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = base 55 drivers/gpu/drm/i915/gvt/vgpu.c vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = base 25 drivers/gpu/drm/i915/i915_active.c struct i915_global base; base 30 drivers/gpu/drm/i915/i915_active.c struct i915_active_request base; base 39 drivers/gpu/drm/i915/i915_active.c return container_of(active, struct active_node, base); base 51 drivers/gpu/drm/i915/i915_active.c GEM_BUG_ON(!is_barrier(&node->base)); base 52 drivers/gpu/drm/i915/i915_active.c return (struct llist_node *)&node->base.link; base 58 drivers/gpu/drm/i915/i915_active.c return (struct intel_engine_cs *)READ_ONCE(node->base.link.prev); base 64 drivers/gpu/drm/i915/i915_active.c GEM_BUG_ON(!is_barrier(&node->base)); base 71 drivers/gpu/drm/i915/i915_active.c struct active_node, base.link); base 147 drivers/gpu/drm/i915/i915_active.c GEM_BUG_ON(i915_active_request_isset(&it->base)); base 170 drivers/gpu/drm/i915/i915_active.c node_retire(struct i915_active_request *base, struct i915_request *rq) base 172 drivers/gpu/drm/i915/i915_active.c active_retire(node_from_active(base)->ref, true); base 176 drivers/gpu/drm/i915/i915_active.c node_retire_nolock(struct i915_active_request *base, struct i915_request *rq) base 178 drivers/gpu/drm/i915/i915_active.c active_retire(node_from_active(base)->ref, false); base 197 drivers/gpu/drm/i915/i915_active.c return &node->base; base 225 drivers/gpu/drm/i915/i915_active.c i915_active_request_init(&node->base, &tl->mutex, NULL, node_retire); base 236 drivers/gpu/drm/i915/i915_active.c BUILD_BUG_ON(offsetof(typeof(*node), base)); base 237 drivers/gpu/drm/i915/i915_active.c return &node->base; base 427 drivers/gpu/drm/i915/i915_active.c if (is_barrier(&it->base)) { /* unconnected idle-barrier */ base 432 drivers/gpu/drm/i915/i915_active.c err = i915_active_request_retire(&it->base, BKL(ref), base 475 drivers/gpu/drm/i915/i915_active.c err = i915_request_await_active_request(rq, &it->base); base 497 drivers/gpu/drm/i915/i915_active.c return node->timeline == idx && !i915_active_request_isset(&node->base); base 567 drivers/gpu/drm/i915/i915_active.c if (is_barrier(&node->base) && base 614 drivers/gpu/drm/i915/i915_active.c node->base.lock = base 617 drivers/gpu/drm/i915/i915_active.c RCU_INIT_POINTER(node->base.request, NULL); base 618 drivers/gpu/drm/i915/i915_active.c node->base.retire = node_retire; base 623 drivers/gpu/drm/i915/i915_active.c if (!i915_active_request_isset(&node->base)) { base 633 drivers/gpu/drm/i915/i915_active.c RCU_INIT_POINTER(node->base.request, ERR_PTR(-EAGAIN)); base 634 drivers/gpu/drm/i915/i915_active.c node->base.link.prev = (void *)engine; base 711 drivers/gpu/drm/i915/i915_active.c RCU_INIT_POINTER(barrier_from_ll(node)->base.request, rq); base 766 drivers/gpu/drm/i915/i915_active.c i915_global_register(&global.base); base 16 drivers/gpu/drm/i915/i915_buddy.c struct i915_global base; base 138 drivers/gpu/drm/i915/i915_debugfs.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); base 144 drivers/gpu/drm/i915/i915_debugfs.c &obj->base, base 149 drivers/gpu/drm/i915/i915_debugfs.c obj->base.size / 1024, base 155 drivers/gpu/drm/i915/i915_debugfs.c if (obj->base.name) base 156 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " (name: %d)", obj->base.name); base 247 drivers/gpu/drm/i915/i915_debugfs.c stats->total += obj->base.size; base 249 drivers/gpu/drm/i915/i915_debugfs.c stats->unbound += obj->base.size; base 1526 drivers/gpu/drm/i915/i915_debugfs.c fbdev_fb->base.width, base 1527 drivers/gpu/drm/i915/i915_debugfs.c fbdev_fb->base.height, base 1528 drivers/gpu/drm/i915/i915_debugfs.c fbdev_fb->base.format->depth, base 1529 drivers/gpu/drm/i915/i915_debugfs.c fbdev_fb->base.format->cpp[0] * 8, base 1530 drivers/gpu/drm/i915/i915_debugfs.c fbdev_fb->base.modifier, base 1531 drivers/gpu/drm/i915/i915_debugfs.c drm_framebuffer_read_refcount(&fbdev_fb->base)); base 1532 drivers/gpu/drm/i915/i915_debugfs.c describe_obj(m, intel_fb_obj(&fbdev_fb->base)); base 1544 drivers/gpu/drm/i915/i915_debugfs.c fb->base.width, base 1545 drivers/gpu/drm/i915/i915_debugfs.c fb->base.height, base 1546 drivers/gpu/drm/i915/i915_debugfs.c fb->base.format->depth, base 1547 drivers/gpu/drm/i915/i915_debugfs.c fb->base.format->cpp[0] * 8, base 1548 drivers/gpu/drm/i915/i915_debugfs.c fb->base.modifier, base 1549 drivers/gpu/drm/i915/i915_debugfs.c drm_framebuffer_read_refcount(&fb->base)); base 1550 drivers/gpu/drm/i915/i915_debugfs.c describe_obj(m, intel_fb_obj(&fb->base)); base 1992 drivers/gpu/drm/i915/i915_debugfs.c for (i = 0; i < obj->base.size / sizeof(u32); i += 4) base 2088 drivers/gpu/drm/i915/i915_debugfs.c enc_to_intel_dp(&intel_attached_encoder(connector)->base); base 2437 drivers/gpu/drm/i915/i915_debugfs.c struct drm_crtc *crtc = &intel_crtc->base; base 2441 drivers/gpu/drm/i915/i915_debugfs.c encoder = &intel_encoder->base; base 2443 drivers/gpu/drm/i915/i915_debugfs.c encoder->base.id, encoder->name); base 2445 drivers/gpu/drm/i915/i915_debugfs.c struct drm_connector *connector = &intel_connector->base; base 2447 drivers/gpu/drm/i915/i915_debugfs.c connector->base.id, base 2464 drivers/gpu/drm/i915/i915_debugfs.c struct drm_crtc *crtc = &intel_crtc->base; base 2471 drivers/gpu/drm/i915/i915_debugfs.c fb->base.id, plane_state->src_x >> 16, base 2510 drivers/gpu/drm/i915/i915_debugfs.c struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); base 2514 drivers/gpu/drm/i915/i915_debugfs.c if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) base 2530 drivers/gpu/drm/i915/i915_debugfs.c enc_to_mst(&intel_encoder->base); base 2543 drivers/gpu/drm/i915/i915_debugfs.c struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); base 2566 drivers/gpu/drm/i915/i915_debugfs.c connector->base.id, connector->name, base 2651 drivers/gpu/drm/i915/i915_debugfs.c struct drm_plane *plane = &intel_plane->base; base 2672 drivers/gpu/drm/i915/i915_debugfs.c plane->base.id, base 2673 drivers/gpu/drm/i915/i915_debugfs.c plane_type(intel_plane->base.type), base 2695 drivers/gpu/drm/i915/i915_debugfs.c pipe_config = to_intel_crtc_state(intel_crtc->base.state); base 2733 drivers/gpu/drm/i915/i915_debugfs.c drm_modeset_lock(&crtc->base.mutex, NULL); base 2734 drivers/gpu/drm/i915/i915_debugfs.c pipe_config = to_intel_crtc_state(crtc->base.state); base 2737 drivers/gpu/drm/i915/i915_debugfs.c crtc->base.base.id, pipe_name(crtc->pipe), base 2738 drivers/gpu/drm/i915/i915_debugfs.c yesno(pipe_config->base.active), base 2742 drivers/gpu/drm/i915/i915_debugfs.c if (pipe_config->base.active) { base 2744 drivers/gpu/drm/i915/i915_debugfs.c to_intel_plane(crtc->base.cursor); base 2749 drivers/gpu/drm/i915/i915_debugfs.c yesno(cursor->base.state->visible), base 2750 drivers/gpu/drm/i915/i915_debugfs.c cursor->base.state->crtc_x, base 2751 drivers/gpu/drm/i915/i915_debugfs.c cursor->base.state->crtc_y, base 2752 drivers/gpu/drm/i915/i915_debugfs.c cursor->base.state->crtc_w, base 2753 drivers/gpu/drm/i915/i915_debugfs.c cursor->base.state->crtc_h, base 2754 drivers/gpu/drm/i915/i915_debugfs.c cursor->cursor.base); base 2762 drivers/gpu/drm/i915/i915_debugfs.c drm_modeset_unlock(&crtc->base.mutex); base 2969 drivers/gpu/drm/i915/i915_debugfs.c to_intel_crtc_state(crtc->base.state); base 3004 drivers/gpu/drm/i915/i915_debugfs.c if (connector->state->crtc != &intel_crtc->base) base 3022 drivers/gpu/drm/i915/i915_debugfs.c if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { base 3076 drivers/gpu/drm/i915/i915_debugfs.c if (intel_crtc->base.state->active) { base 3109 drivers/gpu/drm/i915/i915_debugfs.c intel_dig_port = enc_to_dig_port(&intel_encoder->base); base 3114 drivers/gpu/drm/i915/i915_debugfs.c port_name(intel_dig_port->base.port)); base 3158 drivers/gpu/drm/i915/i915_debugfs.c intel_dp = enc_to_intel_dp(&encoder->base); base 3202 drivers/gpu/drm/i915/i915_debugfs.c intel_dp = enc_to_intel_dp(&encoder->base); base 3252 drivers/gpu/drm/i915/i915_debugfs.c intel_dp = enc_to_intel_dp(&encoder->base); base 3296 drivers/gpu/drm/i915/i915_debugfs.c intel_dp = enc_to_intel_dp(&encoder->base); base 4178 drivers/gpu/drm/i915/i915_debugfs.c ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); base 4182 drivers/gpu/drm/i915/i915_debugfs.c crtc_state = to_intel_crtc_state(crtc->base.state); base 4184 drivers/gpu/drm/i915/i915_debugfs.c if (!crtc_state->base.active || base 4188 drivers/gpu/drm/i915/i915_debugfs.c commit = crtc_state->base.commit; base 4200 drivers/gpu/drm/i915/i915_debugfs.c if (!(crtc_state->base.connector_mask & base 4211 drivers/gpu/drm/i915/i915_debugfs.c intel_dp = enc_to_intel_dp(&encoder->base); base 4222 drivers/gpu/drm/i915/i915_debugfs.c drm_modeset_unlock(&crtc->base.mutex); base 4254 drivers/gpu/drm/i915/i915_debugfs.c ret = drm_modeset_lock_single_interruptible(&intel_crtc->base.mutex); base 4258 drivers/gpu/drm/i915/i915_debugfs.c crtc_state = to_intel_crtc_state(intel_crtc->base.state); base 4259 drivers/gpu/drm/i915/i915_debugfs.c commit = crtc_state->base.commit; base 4266 drivers/gpu/drm/i915/i915_debugfs.c if (!ret && crtc_state->base.active) { base 4273 drivers/gpu/drm/i915/i915_debugfs.c drm_modeset_unlock(&intel_crtc->base.mutex); base 4415 drivers/gpu/drm/i915/i915_debugfs.c enc_to_intel_dp(&intel_attached_encoder(connector)->base); base 4450 drivers/gpu/drm/i915/i915_debugfs.c enc_to_intel_dp(&intel_attached_encoder(connector)->base); base 4481 drivers/gpu/drm/i915/i915_debugfs.c connector->base.id); base 4528 drivers/gpu/drm/i915/i915_debugfs.c intel_dp = enc_to_intel_dp(&intel_attached_encoder(connector)->base); base 4556 drivers/gpu/drm/i915/i915_debugfs.c struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); base 434 drivers/gpu/drm/i915/i915_drv.c ap->ranges[0].base = ggtt->gmadr.start; base 2398 drivers/gpu/drm/i915/i915_drv.h struct drm_i915_private *dev_priv = to_i915(obj->base.dev); base 112 drivers/gpu/drm/i915/i915_gem.c lockdep_assert_held(&obj->base.dev->struct_mutex); base 152 drivers/gpu/drm/i915/i915_gem.c intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt); base 178 drivers/gpu/drm/i915/i915_gem.c ret = drm_gem_handle_create(file, &obj->base, &handle); base 305 drivers/gpu/drm/i915/i915_gem.c loff_t base, int offset, base 312 drivers/gpu/drm/i915/i915_gem.c vaddr = io_mapping_map_atomic_wc(mapping, base); base 318 drivers/gpu/drm/i915/i915_gem.c vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); base 331 drivers/gpu/drm/i915/i915_gem.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 459 drivers/gpu/drm/i915/i915_gem.c if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { base 492 drivers/gpu/drm/i915/i915_gem.c loff_t base, int offset, base 499 drivers/gpu/drm/i915/i915_gem.c vaddr = io_mapping_map_atomic_wc(mapping, base); base 504 drivers/gpu/drm/i915/i915_gem.c vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); base 523 drivers/gpu/drm/i915/i915_gem.c struct drm_i915_private *i915 = to_i915(obj->base.dev); base 759 drivers/gpu/drm/i915/i915_gem.c if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { base 965 drivers/gpu/drm/i915/i915_gem.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); base 980 drivers/gpu/drm/i915/i915_gem.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); base 984 drivers/gpu/drm/i915/i915_gem.c lockdep_assert_held(&obj->base.dev->struct_mutex); base 998 drivers/gpu/drm/i915/i915_gem.c if (obj->base.size > dev_priv->ggtt.mappable_end) base 1017 drivers/gpu/drm/i915/i915_gem.c obj->base.size > dev_priv->ggtt.mappable_end / 2) base 1168 drivers/gpu/drm/i915/i915_gem.c static void init_unused_ring(struct intel_gt *gt, u32 base) base 1172 drivers/gpu/drm/i915/i915_gem.c intel_uncore_write(uncore, RING_CTL(base), 0); base 1173 drivers/gpu/drm/i915/i915_gem.c intel_uncore_write(uncore, RING_HEAD(base), 0); base 1174 drivers/gpu/drm/i915/i915_gem.c intel_uncore_write(uncore, RING_TAIL(base), 0); base 1175 drivers/gpu/drm/i915/i915_gem.c intel_uncore_write(uncore, RING_START(base), 0); base 794 drivers/gpu/drm/i915/i915_gem_fence_reg.c const unsigned int page_count = obj->base.size >> PAGE_SHIFT; base 661 drivers/gpu/drm/i915/i915_gem_gtt.c vm->scratch[0].base.page = page; base 662 drivers/gpu/drm/i915/i915_gem_gtt.c vm->scratch[0].base.daddr = addr; base 713 drivers/gpu/drm/i915/i915_gem_gtt.c if (unlikely(setup_page_dma(vm, &pt->base))) { base 1616 drivers/gpu/drm/i915/i915_gem_gtt.c i915_pt_entry(ppgtt->base.pd, pde++); base 1689 drivers/gpu/drm/i915/i915_gem_gtt.c struct i915_page_directory * const pd = ppgtt->base.pd; base 1735 drivers/gpu/drm/i915/i915_gem_gtt.c mark_tlbs_dirty(&ppgtt->base); base 1752 drivers/gpu/drm/i915/i915_gem_gtt.c struct i915_address_space * const vm = &ppgtt->base.vm; base 1753 drivers/gpu/drm/i915/i915_gem_gtt.c struct i915_page_directory * const pd = ppgtt->base.pd; base 1777 drivers/gpu/drm/i915/i915_gem_gtt.c struct i915_page_directory * const pd = ppgtt->base.pd; base 1779 drivers/gpu/drm/i915/i915_gem_gtt.c px_base(&ppgtt->base.vm.scratch[1]); base 1785 drivers/gpu/drm/i915/i915_gem_gtt.c free_px(&ppgtt->base.vm, pt); base 1800 drivers/gpu/drm/i915/i915_gem_gtt.c kfree(ppgtt->base.pd); base 1826 drivers/gpu/drm/i915/i915_gem_gtt.c px_base(ppgtt->base.pd)->ggtt_offset = ggtt_offset * sizeof(gen6_pte_t); base 1829 drivers/gpu/drm/i915/i915_gem_gtt.c gen6_for_all_pdes(pt, ppgtt->base.pd, pde) base 1832 drivers/gpu/drm/i915/i915_gem_gtt.c mark_tlbs_dirty(&ppgtt->base); base 1841 drivers/gpu/drm/i915/i915_gem_gtt.c struct i915_page_directory * const pd = ppgtt->base.pd; base 1843 drivers/gpu/drm/i915/i915_gem_gtt.c px_base(&ppgtt->base.vm.scratch[1]); base 1851 drivers/gpu/drm/i915/i915_gem_gtt.c gen6_for_all_pdes(pt, ppgtt->base.pd, pde) { base 1855 drivers/gpu/drm/i915/i915_gem_gtt.c free_px(&ppgtt->base.vm, pt); base 1871 drivers/gpu/drm/i915/i915_gem_gtt.c struct drm_i915_private *i915 = ppgtt->base.vm.i915; base 1872 drivers/gpu/drm/i915/i915_gem_gtt.c struct i915_ggtt *ggtt = ppgtt->base.vm.gt->ggtt; base 1903 drivers/gpu/drm/i915/i915_gem_gtt.c int gen6_ppgtt_pin(struct i915_ppgtt *base) base 1905 drivers/gpu/drm/i915/i915_gem_gtt.c struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base); base 1908 drivers/gpu/drm/i915/i915_gem_gtt.c GEM_BUG_ON(ppgtt->base.vm.closed); base 1937 drivers/gpu/drm/i915/i915_gem_gtt.c void gen6_ppgtt_unpin(struct i915_ppgtt *base) base 1939 drivers/gpu/drm/i915/i915_gem_gtt.c struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base); base 1948 drivers/gpu/drm/i915/i915_gem_gtt.c void gen6_ppgtt_unpin_all(struct i915_ppgtt *base) base 1950 drivers/gpu/drm/i915/i915_gem_gtt.c struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base); base 1969 drivers/gpu/drm/i915/i915_gem_gtt.c ppgtt_init(&ppgtt->base, &i915->gt); base 1970 drivers/gpu/drm/i915/i915_gem_gtt.c ppgtt->base.vm.top = 1; base 1972 drivers/gpu/drm/i915/i915_gem_gtt.c ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range; base 1973 drivers/gpu/drm/i915/i915_gem_gtt.c ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range; base 1974 drivers/gpu/drm/i915/i915_gem_gtt.c ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries; base 1975 drivers/gpu/drm/i915/i915_gem_gtt.c ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup; base 1977 drivers/gpu/drm/i915/i915_gem_gtt.c ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode; base 1979 drivers/gpu/drm/i915/i915_gem_gtt.c ppgtt->base.pd = __alloc_pd(sizeof(*ppgtt->base.pd)); base 1980 drivers/gpu/drm/i915/i915_gem_gtt.c if (!ppgtt->base.pd) { base 1995 drivers/gpu/drm/i915/i915_gem_gtt.c return &ppgtt->base; base 1998 drivers/gpu/drm/i915/i915_gem_gtt.c free_scratch(&ppgtt->base.vm); base 2000 drivers/gpu/drm/i915/i915_gem_gtt.c kfree(ppgtt->base.pd); base 2147 drivers/gpu/drm/i915/i915_gem_gtt.c if (dma_map_sg_attrs(&obj->base.dev->pdev->dev, base 2161 drivers/gpu/drm/i915/i915_gem_gtt.c } while (i915_gem_shrink(to_i915(obj->base.dev), base 2162 drivers/gpu/drm/i915/i915_gem_gtt.c obj->base.size >> PAGE_SHIFT, NULL, base 2530 drivers/gpu/drm/i915/i915_gem_gtt.c struct drm_i915_private *dev_priv = to_i915(obj->base.dev); base 3420 drivers/gpu/drm/i915/i915_gem_gtt.c obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); base 3503 drivers/gpu/drm/i915/i915_gem_gtt.c obj->base.size, rem_info->plane[0].width, rem_info->plane[0].height, size); base 232 drivers/gpu/drm/i915/i915_gem_gtt.h struct i915_page_dma base; base 237 drivers/gpu/drm/i915/i915_gem_gtt.h struct i915_page_dma base; base 256 drivers/gpu/drm/i915/i915_gem_gtt.h __px_choose_expr(px, struct i915_page_scratch *, &__x->base, \ base 257 drivers/gpu/drm/i915/i915_gem_gtt.h __px_choose_expr(px, struct i915_page_table *, &__x->base, \ base 258 drivers/gpu/drm/i915/i915_gem_gtt.h __px_choose_expr(px, struct i915_page_directory *, &__x->pt.base, \ base 430 drivers/gpu/drm/i915/i915_gem_gtt.h struct i915_ppgtt base; base 439 drivers/gpu/drm/i915/i915_gem_gtt.h #define __to_gen6_ppgtt(base) container_of(base, struct gen6_ppgtt, base) base 441 drivers/gpu/drm/i915/i915_gem_gtt.h static inline struct gen6_ppgtt *to_gen6_ppgtt(struct i915_ppgtt *base) base 443 drivers/gpu/drm/i915/i915_gem_gtt.h BUILD_BUG_ON(offsetof(struct gen6_ppgtt, base)); base 444 drivers/gpu/drm/i915/i915_gem_gtt.h return __to_gen6_ppgtt(base); base 580 drivers/gpu/drm/i915/i915_gem_gtt.h int gen6_ppgtt_pin(struct i915_ppgtt *base); base 581 drivers/gpu/drm/i915/i915_gem_gtt.h void gen6_ppgtt_unpin(struct i915_ppgtt *base); base 582 drivers/gpu/drm/i915/i915_gem_gtt.h void gen6_ppgtt_unpin_all(struct i915_ppgtt *base); base 974 drivers/gpu/drm/i915/i915_gpu_error.c num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; base 1156 drivers/gpu/drm/i915/i915_gpu_error.c u32 base = engine->mmio_base; base 1160 drivers/gpu/drm/i915/i915_gpu_error.c I915_READ(GEN8_RING_PDP_UDW(base, i)); base 1163 drivers/gpu/drm/i915/i915_gpu_error.c I915_READ(GEN8_RING_PDP_LDW(base, i)); base 1350 drivers/gpu/drm/i915/i915_gpu_error.c .node = { .start = U64_MAX, .size = obj->base.size }, base 1351 drivers/gpu/drm/i915/i915_gpu_error.c .size = obj->base.size, base 844 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 846 drivers/gpu/drm/i915/i915_irq.c &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; base 888 drivers/gpu/drm/i915/i915_irq.c struct drm_device *dev = crtc->base.dev; base 898 drivers/gpu/drm/i915/i915_irq.c vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; base 1064 drivers/gpu/drm/i915/i915_irq.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1600 drivers/gpu/drm/i915/i915_irq.c drm_crtc_add_crc_entry(&crtc->base, true, base 1601 drivers/gpu/drm/i915/i915_irq.c drm_crtc_accurate_vblank_count(&crtc->base), base 123 drivers/gpu/drm/i915/i915_pmu.c if (!pmu->base.event_init) base 150 drivers/gpu/drm/i915/i915_pmu.c if (!pmu->base.event_init) base 302 drivers/gpu/drm/i915/i915_pmu.c container_of(event->pmu, typeof(*i915), pmu.base); base 372 drivers/gpu/drm/i915/i915_pmu.c container_of(event->pmu, typeof(*i915), pmu.base); base 396 drivers/gpu/drm/i915/i915_pmu.c container_of(event->pmu, typeof(*i915), pmu.base); base 530 drivers/gpu/drm/i915/i915_pmu.c container_of(event->pmu, typeof(*i915), pmu.base); base 592 drivers/gpu/drm/i915/i915_pmu.c container_of(event->pmu, typeof(*i915), pmu.base); base 651 drivers/gpu/drm/i915/i915_pmu.c container_of(event->pmu, typeof(*i915), pmu.base); base 990 drivers/gpu/drm/i915/i915_pmu.c GEM_BUG_ON(!pmu->base.event_init); base 1004 drivers/gpu/drm/i915/i915_pmu.c GEM_BUG_ON(!pmu->base.event_init); base 1011 drivers/gpu/drm/i915/i915_pmu.c perf_pmu_migrate_context(&pmu->base, cpu, target); base 1066 drivers/gpu/drm/i915/i915_pmu.c pmu->base.attr_groups = i915_pmu_attr_groups; base 1067 drivers/gpu/drm/i915/i915_pmu.c pmu->base.task_ctx_nr = perf_invalid_context; base 1068 drivers/gpu/drm/i915/i915_pmu.c pmu->base.event_init = i915_pmu_event_init; base 1069 drivers/gpu/drm/i915/i915_pmu.c pmu->base.add = i915_pmu_event_add; base 1070 drivers/gpu/drm/i915/i915_pmu.c pmu->base.del = i915_pmu_event_del; base 1071 drivers/gpu/drm/i915/i915_pmu.c pmu->base.start = i915_pmu_event_start; base 1072 drivers/gpu/drm/i915/i915_pmu.c pmu->base.stop = i915_pmu_event_stop; base 1073 drivers/gpu/drm/i915/i915_pmu.c pmu->base.read = i915_pmu_event_read; base 1074 drivers/gpu/drm/i915/i915_pmu.c pmu->base.event_idx = i915_pmu_event_event_idx; base 1080 drivers/gpu/drm/i915/i915_pmu.c ret = perf_pmu_register(&pmu->base, "i915", -1); base 1091 drivers/gpu/drm/i915/i915_pmu.c perf_pmu_unregister(&pmu->base); base 1093 drivers/gpu/drm/i915/i915_pmu.c pmu->base.event_init = NULL; base 1102 drivers/gpu/drm/i915/i915_pmu.c if (!pmu->base.event_init) base 1111 drivers/gpu/drm/i915/i915_pmu.c perf_pmu_unregister(&pmu->base); base 1112 drivers/gpu/drm/i915/i915_pmu.c pmu->base.event_init = NULL; base 48 drivers/gpu/drm/i915/i915_pmu.h struct pmu base; base 77 drivers/gpu/drm/i915/i915_pvinfo.h u32 base; base 82 drivers/gpu/drm/i915/i915_pvinfo.h u32 base; base 416 drivers/gpu/drm/i915/i915_reg.h #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228) base 417 drivers/gpu/drm/i915/i915_reg.h #define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518) base 418 drivers/gpu/drm/i915/i915_reg.h #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220) base 421 drivers/gpu/drm/i915/i915_reg.h #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4) base 422 drivers/gpu/drm/i915/i915_reg.h #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8) base 2402 drivers/gpu/drm/i915/i915_reg.h #define RING_TAIL(base) _MMIO((base) + 0x30) base 2403 drivers/gpu/drm/i915/i915_reg.h #define RING_HEAD(base) _MMIO((base) + 0x34) base 2404 drivers/gpu/drm/i915/i915_reg.h #define RING_START(base) _MMIO((base) + 0x38) base 2405 drivers/gpu/drm/i915/i915_reg.h #define RING_CTL(base) _MMIO((base) + 0x3c) base 2407 drivers/gpu/drm/i915/i915_reg.h #define RING_SYNC_0(base) _MMIO((base) + 0x40) base 2408 drivers/gpu/drm/i915/i915_reg.h #define RING_SYNC_1(base) _MMIO((base) + 0x44) base 2409 drivers/gpu/drm/i915/i915_reg.h #define RING_SYNC_2(base) _MMIO((base) + 0x48) base 2423 drivers/gpu/drm/i915/i915_reg.h #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) base 2424 drivers/gpu/drm/i915/i915_reg.h #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) base 2425 drivers/gpu/drm/i915/i915_reg.h #define RING_HWS_PGA(base) _MMIO((base) + 0x80) base 2426 drivers/gpu/drm/i915/i915_reg.h #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) base 2427 drivers/gpu/drm/i915/i915_reg.h #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) base 2432 drivers/gpu/drm/i915/i915_reg.h #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) base 2469 drivers/gpu/drm/i915/i915_reg.h #define RING_ACTHD(base) _MMIO((base) + 0x74) base 2470 drivers/gpu/drm/i915/i915_reg.h #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) base 2471 drivers/gpu/drm/i915/i915_reg.h #define RING_NOPID(base) _MMIO((base) + 0x94) base 2472 drivers/gpu/drm/i915/i915_reg.h #define RING_IMR(base) _MMIO((base) + 0xa8) base 2473 drivers/gpu/drm/i915/i915_reg.h #define RING_HWSTAM(base) _MMIO((base) + 0x98) base 2474 drivers/gpu/drm/i915/i915_reg.h #define RING_TIMESTAMP(base) _MMIO((base) + 0x358) base 2475 drivers/gpu/drm/i915/i915_reg.h #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) base 2492 drivers/gpu/drm/i915/i915_reg.h #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) base 2546 drivers/gpu/drm/i915/i915_reg.h #define RING_IPEIR(base) _MMIO((base) + 0x64) base 2547 drivers/gpu/drm/i915/i915_reg.h #define RING_IPEHR(base) _MMIO((base) + 0x68) base 2553 drivers/gpu/drm/i915/i915_reg.h #define RING_INSTDONE(base) _MMIO((base) + 0x6c) base 2554 drivers/gpu/drm/i915/i915_reg.h #define RING_INSTPS(base) _MMIO((base) + 0x70) base 2555 drivers/gpu/drm/i915/i915_reg.h #define RING_DMA_FADD(base) _MMIO((base) + 0x78) base 2556 drivers/gpu/drm/i915/i915_reg.h #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ base 2557 drivers/gpu/drm/i915/i915_reg.h #define RING_INSTPM(base) _MMIO((base) + 0xc0) base 2558 drivers/gpu/drm/i915/i915_reg.h #define RING_MI_MODE(base) _MMIO((base) + 0x9c) base 2567 drivers/gpu/drm/i915/i915_reg.h #define IPEIR(base) _MMIO((base) + 0x88) base 2568 drivers/gpu/drm/i915/i915_reg.h #define IPEHR(base) _MMIO((base) + 0x8c) base 2572 drivers/gpu/drm/i915/i915_reg.h #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0) base 2573 drivers/gpu/drm/i915/i915_reg.h #define RING_BBSTATE(base) _MMIO((base) + 0x110) base 2575 drivers/gpu/drm/i915/i915_reg.h #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ base 2576 drivers/gpu/drm/i915/i915_reg.h #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */ base 2577 drivers/gpu/drm/i915/i915_reg.h #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */ base 2578 drivers/gpu/drm/i915/i915_reg.h #define RING_BBADDR(base) _MMIO((base) + 0x140) base 2579 drivers/gpu/drm/i915/i915_reg.h #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */ base 2580 drivers/gpu/drm/i915/i915_reg.h #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ base 2581 drivers/gpu/drm/i915/i915_reg.h #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ base 2582 drivers/gpu/drm/i915/i915_reg.h #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ base 2583 drivers/gpu/drm/i915/i915_reg.h #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ base 2694 drivers/gpu/drm/i915/i915_reg.h #define RING_MODE_GEN7(base) _MMIO((base) + 0x29c) base 2748 drivers/gpu/drm/i915/i915_reg.h #define ACTHD(base) _MMIO((base) + 0xc8) base 3932 drivers/gpu/drm/i915/i915_reg.h #define CCID(base) _MMIO((base) + 0x180) base 50 drivers/gpu/drm/i915/i915_request.c struct i915_global base; base 1070 drivers/gpu/drm/i915/i915_request.c ret = dma_resv_get_fences_rcu(obj->base.resv, base 1087 drivers/gpu/drm/i915/i915_request.c excl = dma_resv_get_excl_rcu(obj->base.resv); base 1605 drivers/gpu/drm/i915/i915_request.c i915_global_register(&global.base); base 15 drivers/gpu/drm/i915/i915_scheduler.c struct i915_global base; base 532 drivers/gpu/drm/i915/i915_scheduler.c i915_global_register(&global.base); base 373 drivers/gpu/drm/i915/i915_sw_fence.c struct i915_sw_dma_fence_cb base; base 383 drivers/gpu/drm/i915/i915_sw_fence.c struct i915_sw_dma_fence_cb *cb = container_of(data, typeof(*cb), base); base 395 drivers/gpu/drm/i915/i915_sw_fence.c fence = xchg(&cb->base.fence, NULL); base 413 drivers/gpu/drm/i915/i915_sw_fence.c container_of(data, typeof(*cb), base.base); base 416 drivers/gpu/drm/i915/i915_sw_fence.c fence = xchg(&cb->base.fence, NULL); base 466 drivers/gpu/drm/i915/i915_sw_fence.c container_of(cb, typeof(*timer), base); base 478 drivers/gpu/drm/i915/i915_sw_fence.c ret = dma_fence_add_callback(dma, &cb->base, func); base 482 drivers/gpu/drm/i915/i915_sw_fence.c func(dma, &cb->base); base 493 drivers/gpu/drm/i915/i915_sw_fence.c struct i915_sw_dma_fence_cb *cb = container_of(data, typeof(*cb), base); base 513 drivers/gpu/drm/i915/i915_sw_fence.c ret = dma_fence_add_callback(dma, &cb->base, __dma_i915_sw_fence_wake); base 517 drivers/gpu/drm/i915/i915_sw_fence.c __dma_i915_sw_fence_wake(dma, &cb->base); base 73 drivers/gpu/drm/i915/i915_sw_fence.h struct dma_fence_cb base; base 33 drivers/gpu/drm/i915/i915_trace.h struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 60 drivers/gpu/drm/i915/i915_trace.h struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 428 drivers/gpu/drm/i915/i915_trace.h __entry->size = obj->base.size; base 113 drivers/gpu/drm/i915/i915_utils.h __check_struct_size(size_t base, size_t arr, size_t count, size_t *size) base 120 drivers/gpu/drm/i915/i915_utils.h if (check_add_overflow(sz, base, &sz)) base 342 drivers/gpu/drm/i915/i915_utils.h u64 base; \ base 348 drivers/gpu/drm/i915/i915_utils.h base = local_clock(); \ base 359 drivers/gpu/drm/i915/i915_utils.h if (now - base >= timeout) { \ base 367 drivers/gpu/drm/i915/i915_utils.h timeout -= now - base; \ base 369 drivers/gpu/drm/i915/i915_utils.h base = local_clock(); \ base 233 drivers/gpu/drm/i915/i915_vgpu.c intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base)); base 237 drivers/gpu/drm/i915/i915_vgpu.c intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base)); base 39 drivers/gpu/drm/i915/i915_vma.c struct i915_global base; base 116 drivers/gpu/drm/i915/i915_vma.c vma->resv = obj->base.resv; base 117 drivers/gpu/drm/i915/i915_vma.c vma->size = obj->base.size; base 138 drivers/gpu/drm/i915/i915_vma.c obj->base.size >> PAGE_SHIFT)); base 141 drivers/gpu/drm/i915/i915_vma.c GEM_BUG_ON(vma->size > obj->base.size); base 864 drivers/gpu/drm/i915/i915_vma.c struct drm_vma_offset_node *node = &vma->obj->base.vma_node; base 1054 drivers/gpu/drm/i915/i915_vma.c i915_global_register(&global.base); base 236 drivers/gpu/drm/i915/i915_vma.h if (likely(kref_get_unless_zero(&vma->obj->base.refcount))) base 180 drivers/gpu/drm/i915/intel_csr.c struct intel_dmc_header_base base; base 198 drivers/gpu/drm/i915/intel_csr.c struct intel_dmc_header_base base; base 495 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 496 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 826 drivers/gpu/drm/i915/intel_pm.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 829 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.active) base 841 drivers/gpu/drm/i915/intel_pm.c return plane_state->base.fb != NULL; base 843 drivers/gpu/drm/i915/intel_pm.c return plane_state->base.visible; base 863 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); base 882 drivers/gpu/drm/i915/intel_pm.c &crtc->config->base.adjusted_mode; base 884 drivers/gpu/drm/i915/intel_pm.c crtc->base.primary->state->fb; base 1115 drivers/gpu/drm/i915/intel_pm.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1116 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1118 drivers/gpu/drm/i915/intel_pm.c &crtc_state->base.adjusted_mode; base 1128 drivers/gpu/drm/i915/intel_pm.c cpp = plane_state->base.fb->format->cpp[0]; base 1149 drivers/gpu/drm/i915/intel_pm.c width = plane_state->base.crtc_w; base 1151 drivers/gpu/drm/i915/intel_pm.c width = drm_rect_width(&plane_state->base.dst); base 1178 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 1194 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 1217 drivers/gpu/drm/i915/intel_pm.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1218 drivers/gpu/drm/i915/intel_pm.c int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); base 1271 drivers/gpu/drm/i915/intel_pm.c plane->base.name, base 1296 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 1334 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1336 drivers/gpu/drm/i915/intel_pm.c to_intel_atomic_state(crtc_state->base.state); base 1351 drivers/gpu/drm/i915/intel_pm.c if (new_plane_state->base.crtc != &crtc->base && base 1352 drivers/gpu/drm/i915/intel_pm.c old_plane_state->base.crtc != &crtc->base) base 1423 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 1427 drivers/gpu/drm/i915/intel_pm.c to_intel_atomic_state(new_crtc_state->base.state); base 1433 drivers/gpu/drm/i915/intel_pm.c if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) { base 1565 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 1566 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1577 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 1578 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1624 drivers/gpu/drm/i915/intel_pm.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1625 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 1627 drivers/gpu/drm/i915/intel_pm.c &crtc_state->base.adjusted_mode; base 1636 drivers/gpu/drm/i915/intel_pm.c cpp = plane_state->base.fb->format->cpp[0]; base 1665 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1749 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1777 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 1794 drivers/gpu/drm/i915/intel_pm.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 1796 drivers/gpu/drm/i915/intel_pm.c int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); base 1823 drivers/gpu/drm/i915/intel_pm.c plane->base.name, base 1852 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1853 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 1855 drivers/gpu/drm/i915/intel_pm.c to_intel_atomic_state(crtc_state->base.state); base 1861 drivers/gpu/drm/i915/intel_pm.c bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base); base 1872 drivers/gpu/drm/i915/intel_pm.c if (new_plane_state->base.crtc != &crtc->base && base 1873 drivers/gpu/drm/i915/intel_pm.c old_plane_state->base.crtc != &crtc->base) base 1960 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 1961 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 2056 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 2060 drivers/gpu/drm/i915/intel_pm.c to_intel_atomic_state(new_crtc_state->base.state); base 2066 drivers/gpu/drm/i915/intel_pm.c if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) { base 2184 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 2185 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 2196 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 2197 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 2210 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); base 2222 drivers/gpu/drm/i915/intel_pm.c &crtc->config->base.adjusted_mode; base 2224 drivers/gpu/drm/i915/intel_pm.c crtc->base.primary->state->fb; base 2242 drivers/gpu/drm/i915/intel_pm.c crtc->base.cursor->state->crtc_w, 4, base 2283 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); base 2303 drivers/gpu/drm/i915/intel_pm.c &crtc->config->base.adjusted_mode; base 2305 drivers/gpu/drm/i915/intel_pm.c crtc->base.primary->state->fb; base 2330 drivers/gpu/drm/i915/intel_pm.c &crtc->config->base.adjusted_mode; base 2332 drivers/gpu/drm/i915/intel_pm.c crtc->base.primary->state->fb; base 2358 drivers/gpu/drm/i915/intel_pm.c obj = intel_fb_obj(enabled->base.primary->state->fb); base 2378 drivers/gpu/drm/i915/intel_pm.c &enabled->config->base.adjusted_mode; base 2380 drivers/gpu/drm/i915/intel_pm.c enabled->base.primary->state->fb; base 2426 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); base 2436 drivers/gpu/drm/i915/intel_pm.c adjusted_mode = &crtc->config->base.adjusted_mode; base 2518 drivers/gpu/drm/i915/intel_pm.c cpp = plane_state->base.fb->format->cpp[0]; base 2526 drivers/gpu/drm/i915/intel_pm.c crtc_state->base.adjusted_mode.crtc_htotal, base 2527 drivers/gpu/drm/i915/intel_pm.c drm_rect_width(&plane_state->base.dst), base 2550 drivers/gpu/drm/i915/intel_pm.c cpp = plane_state->base.fb->format->cpp[0]; base 2554 drivers/gpu/drm/i915/intel_pm.c crtc_state->base.adjusted_mode.crtc_htotal, base 2555 drivers/gpu/drm/i915/intel_pm.c drm_rect_width(&plane_state->base.dst), base 2576 drivers/gpu/drm/i915/intel_pm.c cpp = plane_state->base.fb->format->cpp[0]; base 2579 drivers/gpu/drm/i915/intel_pm.c crtc_state->base.adjusted_mode.crtc_htotal, base 2580 drivers/gpu/drm/i915/intel_pm.c plane_state->base.crtc_w, cpp, mem_value); base 2593 drivers/gpu/drm/i915/intel_pm.c cpp = plane_state->base.fb->format->cpp[0]; base 2595 drivers/gpu/drm/i915/intel_pm.c return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->base.dst), cpp); base 2800 drivers/gpu/drm/i915/intel_pm.c to_intel_atomic_state(crtc_state->base.state); base 2802 drivers/gpu/drm/i915/intel_pm.c &crtc_state->base.adjusted_mode; base 2805 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.active) base 3115 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; base 3116 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); base 3130 drivers/gpu/drm/i915/intel_pm.c drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &crtc_state->base) { base 3141 drivers/gpu/drm/i915/intel_pm.c pipe_wm->pipe_enabled = crtc_state->base.active; base 3143 drivers/gpu/drm/i915/intel_pm.c pipe_wm->sprites_enabled = sprstate->base.visible; base 3144 drivers/gpu/drm/i915/intel_pm.c pipe_wm->sprites_scaled = sprstate->base.visible && base 3145 drivers/gpu/drm/i915/intel_pm.c (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 || base 3146 drivers/gpu/drm/i915/intel_pm.c drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16); base 3198 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *intel_crtc = to_intel_crtc(newstate->base.crtc); base 3199 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); base 3202 drivers/gpu/drm/i915/intel_pm.c to_intel_atomic_state(newstate->base.state); base 3214 drivers/gpu/drm/i915/intel_pm.c if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base) || base 3750 drivers/gpu/drm/i915/intel_pm.c struct drm_device *dev = state->base.dev; base 3785 drivers/gpu/drm/i915/intel_pm.c crtc_state = to_intel_crtc_state(crtc->base.state); base 3787 drivers/gpu/drm/i915/intel_pm.c if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) base 3806 drivers/gpu/drm/i915/intel_pm.c plane->base.state->fb->modifier == base 3837 drivers/gpu/drm/i915/intel_pm.c adjusted_mode = &crtc_state->base.adjusted_mode; base 3866 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; base 3868 drivers/gpu/drm/i915/intel_pm.c struct drm_crtc *for_crtc = crtc_state->base.crtc; base 3875 drivers/gpu/drm/i915/intel_pm.c if (WARN_ON(!state) || !crtc_state->base.active) { base 3914 drivers/gpu/drm/i915/intel_pm.c &crtc_state->base.adjusted_mode; base 3918 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.enable) base 3949 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 4028 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 4074 drivers/gpu/drm/i915/intel_pm.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 4088 drivers/gpu/drm/i915/intel_pm.c src_w = plane_state->base.src_w >> 16; base 4089 drivers/gpu/drm/i915/intel_pm.c src_h = plane_state->base.src_h >> 16; base 4090 drivers/gpu/drm/i915/intel_pm.c dst_w = plane_state->base.crtc_w; base 4091 drivers/gpu/drm/i915/intel_pm.c dst_h = plane_state->base.crtc_h; base 4098 drivers/gpu/drm/i915/intel_pm.c src_w = drm_rect_width(&plane_state->base.src) >> 16; base 4099 drivers/gpu/drm/i915/intel_pm.c src_h = drm_rect_height(&plane_state->base.src) >> 16; base 4100 drivers/gpu/drm/i915/intel_pm.c dst_w = drm_rect_width(&plane_state->base.dst); base 4101 drivers/gpu/drm/i915/intel_pm.c dst_h = drm_rect_height(&plane_state->base.dst); base 4117 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.enable) base 4148 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); base 4149 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; base 4157 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.enable) base 4160 drivers/gpu/drm/i915/intel_pm.c drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) { base 4170 drivers/gpu/drm/i915/intel_pm.c if (WARN_ON(!plane_state->base.fb)) base 4174 drivers/gpu/drm/i915/intel_pm.c bpp = plane_state->base.fb->format->cpp[0] * 8; base 4185 drivers/gpu/drm/i915/intel_pm.c crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; base 4206 drivers/gpu/drm/i915/intel_pm.c struct intel_plane *intel_plane = to_intel_plane(plane_state->base.plane); base 4214 drivers/gpu/drm/i915/intel_pm.c if (!plane_state->base.visible) base 4217 drivers/gpu/drm/i915/intel_pm.c fb = plane_state->base.fb; base 4230 drivers/gpu/drm/i915/intel_pm.c width = drm_rect_width(&plane_state->base.src) >> 16; base 4231 drivers/gpu/drm/i915/intel_pm.c height = drm_rect_height(&plane_state->base.src) >> 16; base 4254 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; base 4263 drivers/gpu/drm/i915/intel_pm.c drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) { base 4291 drivers/gpu/drm/i915/intel_pm.c if (WARN_ON(!crtc_state->base.state)) base 4295 drivers/gpu/drm/i915/intel_pm.c drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) { base 4337 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; base 4338 drivers/gpu/drm/i915/intel_pm.c struct drm_crtc *crtc = crtc_state->base.crtc; base 4360 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.active) { base 4602 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->base.active) base 4610 drivers/gpu/drm/i915/intel_pm.c crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal; base 4645 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 4646 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 4734 drivers/gpu/drm/i915/intel_pm.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 4735 drivers/gpu/drm/i915/intel_pm.c const struct drm_framebuffer *fb = plane_state->base.fb; base 4739 drivers/gpu/drm/i915/intel_pm.c width = plane_state->base.crtc_w; base 4746 drivers/gpu/drm/i915/intel_pm.c width = drm_rect_width(&plane_state->base.src) >> 16; base 4751 drivers/gpu/drm/i915/intel_pm.c plane_state->base.rotation, base 4771 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 4797 drivers/gpu/drm/i915/intel_pm.c crtc_state->base.adjusted_mode.crtc_htotal, base 4804 drivers/gpu/drm/i915/intel_pm.c if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal / base 4895 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 4912 drivers/gpu/drm/i915/intel_pm.c struct drm_atomic_state *state = crtc_state->base.state; base 4931 drivers/gpu/drm/i915/intel_pm.c struct drm_device *dev = crtc_state->base.crtc->dev; base 5029 drivers/gpu/drm/i915/intel_pm.c struct intel_plane *plane = to_intel_plane(plane_state->base.plane); base 5030 drivers/gpu/drm/i915/intel_pm.c const struct drm_framebuffer *fb = plane_state->base.fb; base 5055 drivers/gpu/drm/i915/intel_pm.c enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id; base 5063 drivers/gpu/drm/i915/intel_pm.c const struct drm_framebuffer *fb = plane_state->base.fb; base 5091 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 5104 drivers/gpu/drm/i915/intel_pm.c &crtc_state->base) { base 5150 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 5186 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(plane->base.dev); base 5232 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 5274 drivers/gpu/drm/i915/intel_pm.c ret |= drm_crtc_mask(&crtc->base); base 5283 drivers/gpu/drm/i915/intel_pm.c struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state); base 5284 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); base 5285 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 5311 drivers/gpu/drm/i915/intel_pm.c const struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 5343 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 5371 drivers/gpu/drm/i915/intel_pm.c plane->base.base.id, plane->base.name, base 5388 drivers/gpu/drm/i915/intel_pm.c plane->base.base.id, plane->base.name, base 5402 drivers/gpu/drm/i915/intel_pm.c plane->base.base.id, plane->base.name, base 5425 drivers/gpu/drm/i915/intel_pm.c plane->base.base.id, plane->base.name, base 5439 drivers/gpu/drm/i915/intel_pm.c plane->base.base.id, plane->base.name, base 5457 drivers/gpu/drm/i915/intel_pm.c struct drm_device *dev = state->base.dev; base 5493 drivers/gpu/drm/i915/intel_pm.c state->base.acquire_ctx); base 5532 drivers/gpu/drm/i915/intel_pm.c crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); base 5565 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 5584 drivers/gpu/drm/i915/intel_pm.c if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) && base 5636 drivers/gpu/drm/i915/intel_pm.c results->dirty_pipes |= drm_crtc_mask(&crtc->base); base 5651 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5652 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(state->base.dev); base 5656 drivers/gpu/drm/i915/intel_pm.c if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base))) base 5665 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); base 5666 drivers/gpu/drm/i915/intel_pm.c struct drm_device *dev = intel_crtc->base.dev; base 5670 drivers/gpu/drm/i915/intel_pm.c if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0) base 5675 drivers/gpu/drm/i915/intel_pm.c if (crtc_state->base.active_changed) base 5734 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 5735 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5746 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); base 5747 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); base 5771 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 5814 drivers/gpu/drm/i915/intel_pm.c crtc_state = to_intel_crtc_state(crtc->base.state); base 5819 drivers/gpu/drm/i915/intel_pm.c hw->dirty_pipes |= drm_crtc_mask(&crtc->base); base 5830 drivers/gpu/drm/i915/intel_pm.c struct drm_device *dev = crtc->base.dev; base 5833 drivers/gpu/drm/i915/intel_pm.c struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); base 5997 drivers/gpu/drm/i915/intel_pm.c to_intel_crtc_state(crtc->base.state); base 6081 drivers/gpu/drm/i915/intel_pm.c to_intel_crtc_state(crtc->base.state); base 6083 drivers/gpu/drm/i915/intel_pm.c to_intel_plane_state(plane->base.state); base 6088 drivers/gpu/drm/i915/intel_pm.c if (plane_state->base.visible) base 6114 drivers/gpu/drm/i915/intel_pm.c to_intel_crtc_state(crtc->base.state); base 6173 drivers/gpu/drm/i915/intel_pm.c to_intel_crtc_state(crtc->base.state); base 6234 drivers/gpu/drm/i915/intel_pm.c to_intel_crtc_state(crtc->base.state); base 6236 drivers/gpu/drm/i915/intel_pm.c to_intel_plane_state(plane->base.state); base 6243 drivers/gpu/drm/i915/intel_pm.c if (plane_state->base.visible) base 6260 drivers/gpu/drm/i915/intel_pm.c to_intel_crtc_state(crtc->base.state); base 6354 drivers/gpu/drm/i915/intel_pm.c struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); base 832 drivers/gpu/drm/i915/intel_uncore.c #define BSEARCH(key, base, num, cmp) ({ \ base 834 drivers/gpu/drm/i915/intel_uncore.c typeof(base) result__ = NULL; \ base 837 drivers/gpu/drm/i915/intel_uncore.c int ret__ = (cmp)((key), (base) + mid__); \ base 843 drivers/gpu/drm/i915/intel_uncore.c result__ = (base) + mid__; \ base 412 drivers/gpu/drm/i915/intel_uncore.h #define raw_reg_read(base, reg) \ base 413 drivers/gpu/drm/i915/intel_uncore.h readl(base + i915_mmio_reg_offset(reg)) base 414 drivers/gpu/drm/i915/intel_uncore.h #define raw_reg_write(base, reg, value) \ base 415 drivers/gpu/drm/i915/intel_uncore.h writel(value, base + i915_mmio_reg_offset(reg)) base 235 drivers/gpu/drm/i915/intel_wopcm.c GEM_BUG_ON(wopcm->guc.base); base 275 drivers/gpu/drm/i915/intel_wopcm.c wopcm->guc.base = guc_wopcm_base; base 277 drivers/gpu/drm/i915/intel_wopcm.c GEM_BUG_ON(!wopcm->guc.base); base 22 drivers/gpu/drm/i915/intel_wopcm.h u32 base; base 39 drivers/gpu/drm/i915/intel_wopcm.h return wopcm->guc.base; base 18 drivers/gpu/drm/i915/selftests/i915_active.c struct i915_active base; base 30 drivers/gpu/drm/i915/selftests/i915_active.c i915_active_fini(&active->base); base 46 drivers/gpu/drm/i915/selftests/i915_active.c static int __live_active(struct i915_active *base) base 48 drivers/gpu/drm/i915/selftests/i915_active.c struct live_active *active = container_of(base, typeof(*active), base); base 54 drivers/gpu/drm/i915/selftests/i915_active.c static void __live_retire(struct i915_active *base) base 56 drivers/gpu/drm/i915/selftests/i915_active.c struct live_active *active = container_of(base, typeof(*active), base); base 71 drivers/gpu/drm/i915/selftests/i915_active.c i915_active_init(i915, &active->base, __live_active, __live_retire); base 96 drivers/gpu/drm/i915/selftests/i915_active.c err = i915_active_acquire(&active->base); base 113 drivers/gpu/drm/i915/selftests/i915_active.c err = i915_active_ref(&active->base, rq->timeline, rq); base 123 drivers/gpu/drm/i915/selftests/i915_active.c i915_active_release(&active->base); base 128 drivers/gpu/drm/i915/selftests/i915_active.c if (atomic_read(&active->base.count) != count) { base 130 drivers/gpu/drm/i915/selftests/i915_active.c atomic_read(&active->base.count), count); base 163 drivers/gpu/drm/i915/selftests/i915_active.c i915_active_wait(&active->base); base 64 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c typeof(obj->base.size) rem; base 70 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c rem = round_up(obj->base.size, BIT(31)) >> 31; base 77 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c rem = obj->base.size; base 121 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (overflows_type(size, obj->base.size)) base 128 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c drm_gem_private_object_init(&i915->drm, &obj->base, size); base 267 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c GEM_BUG_ON(obj->base.size != BIT_ULL(size)); base 396 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (offset < hole_start + obj->base.size) base 398 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c offset -= obj->base.size; base 420 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (offset + obj->base.size > hole_end) base 422 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c offset += obj->base.size; base 433 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (offset < hole_start + obj->base.size) base 435 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c offset -= obj->base.size; base 456 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (offset + obj->base.size > hole_end) base 458 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c offset += obj->base.size; base 469 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (offset < hole_start + obj->base.size) base 471 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c offset -= obj->base.size; base 493 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (offset + obj->base.size > hole_end) base 495 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c offset += obj->base.size; base 506 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (offset < hole_start + obj->base.size) base 508 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c offset -= obj->base.size; base 529 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c if (offset + obj->base.size > hole_end) base 531 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c offset += obj->base.size; base 588 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c addr + obj->base.size < hole_end; base 589 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c addr += obj->base.size) { base 1334 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c obj->base.size, base 1384 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c obj->base.size, base 1428 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c obj->base.size, base 1541 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c obj->base.size, 0, obj->cache_level, base 1599 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c obj->base.size, 0, obj->cache_level, base 1646 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c obj->base.size, 0, obj->cache_level, base 46 drivers/gpu/drm/i915/selftests/i915_vma.c if (vma->size != obj->base.size) { base 48 drivers/gpu/drm/i915/selftests/i915_vma.c vma->size, obj->base.size); base 787 drivers/gpu/drm/i915/selftests/i915_vma.c if (!assert_pin(vma, NULL, obj->base.size, p->name)) { base 47 drivers/gpu/drm/i915/selftests/mock_request.c container_of(request->engine, typeof(*engine), base); base 16 drivers/gpu/drm/imx/imx-drm.h struct drm_crtc_state base; base 25 drivers/gpu/drm/imx/imx-drm.h return container_of(s, struct imx_crtc_state, base); base 445 drivers/gpu/drm/imx/imx-tve.c static int tve_clk_init(struct imx_tve *tve, void __iomem *base) base 544 drivers/gpu/drm/imx/imx-tve.c void __iomem *base; base 587 drivers/gpu/drm/imx/imx-tve.c base = devm_ioremap_resource(dev, res); base 588 drivers/gpu/drm/imx/imx-tve.c if (IS_ERR(base)) base 589 drivers/gpu/drm/imx/imx-tve.c return PTR_ERR(base); base 592 drivers/gpu/drm/imx/imx-tve.c tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base, base 638 drivers/gpu/drm/imx/imx-tve.c ret = tve_clk_init(tve, base); base 33 drivers/gpu/drm/imx/ipuv3-crtc.c struct drm_crtc base; base 46 drivers/gpu/drm/imx/ipuv3-crtc.c return container_of(crtc, struct ipu_crtc, base); base 69 drivers/gpu/drm/imx/ipuv3-crtc.c if (plane == &ipu_crtc->plane[0]->base) base 71 drivers/gpu/drm/imx/ipuv3-crtc.c if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base) base 122 drivers/gpu/drm/imx/ipuv3-crtc.c crtc->state = &state->base; base 125 drivers/gpu/drm/imx/ipuv3-crtc.c state->base.crtc = crtc; base 136 drivers/gpu/drm/imx/ipuv3-crtc.c __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); base 138 drivers/gpu/drm/imx/ipuv3-crtc.c WARN_ON(state->base.crtc != crtc); base 139 drivers/gpu/drm/imx/ipuv3-crtc.c state->base.crtc = crtc; base 141 drivers/gpu/drm/imx/ipuv3-crtc.c return &state->base; base 181 drivers/gpu/drm/imx/ipuv3-crtc.c struct drm_crtc *crtc = &ipu_crtc->base; base 194 drivers/gpu/drm/imx/ipuv3-crtc.c if (ipu_plane_atomic_update_pending(&plane->base)) base 363 drivers/gpu/drm/imx/ipuv3-crtc.c struct drm_crtc *crtc = &ipu_crtc->base; base 385 drivers/gpu/drm/imx/ipuv3-crtc.c drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL, base 399 drivers/gpu/drm/imx/ipuv3-crtc.c drm_crtc_mask(&ipu_crtc->base), base 22 drivers/gpu/drm/imx/ipuv3-plane.c struct drm_plane_state base; base 29 drivers/gpu/drm/imx/ipuv3-plane.c return container_of(p, struct ipu_plane_state, base); base 34 drivers/gpu/drm/imx/ipuv3-plane.c return container_of(p, struct ipu_plane, base); base 205 drivers/gpu/drm/imx/ipuv3-plane.c switch (ipu_plane->base.state->fb->format->format) { base 239 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->base.base.id); base 290 drivers/gpu/drm/imx/ipuv3-plane.c __drm_atomic_helper_plane_reset(plane, &ipu_state->base); base 291 drivers/gpu/drm/imx/ipuv3-plane.c ipu_state->base.zpos = zpos; base 292 drivers/gpu/drm/imx/ipuv3-plane.c ipu_state->base.normalized_zpos = zpos; base 306 drivers/gpu/drm/imx/ipuv3-plane.c __drm_atomic_helper_plane_duplicate_state(plane, &state->base); base 308 drivers/gpu/drm/imx/ipuv3-plane.c return &state->base; base 661 drivers/gpu/drm/imx/ipuv3-plane.c dev_dbg(ipu_plane->base.dev->dev, base 672 drivers/gpu/drm/imx/ipuv3-plane.c dev_dbg(ipu_plane->base.dev->dev, base 685 drivers/gpu/drm/imx/ipuv3-plane.c dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d", base 703 drivers/gpu/drm/imx/ipuv3-plane.c dev_dbg(ipu_plane->base.dev->dev, "phys = %lu, x = %d, y = %d", base 850 drivers/gpu/drm/imx/ipuv3-plane.c ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs, base 860 drivers/gpu/drm/imx/ipuv3-plane.c drm_plane_helper_add(&ipu_plane->base, &ipu_plane_helper_funcs); base 863 drivers/gpu/drm/imx/ipuv3-plane.c drm_plane_create_zpos_property(&ipu_plane->base, zpos, 0, 1); base 865 drivers/gpu/drm/imx/ipuv3-plane.c drm_plane_create_zpos_immutable_property(&ipu_plane->base, 0); base 18 drivers/gpu/drm/imx/ipuv3-plane.h struct drm_plane base; base 609 drivers/gpu/drm/ingenic/ingenic-drm.c void __iomem *base; base 642 drivers/gpu/drm/ingenic/ingenic-drm.c base = devm_platform_ioremap_resource(pdev, 0); base 643 drivers/gpu/drm/ingenic/ingenic-drm.c if (IS_ERR(base)) { base 645 drivers/gpu/drm/ingenic/ingenic-drm.c return PTR_ERR(base); base 648 drivers/gpu/drm/ingenic/ingenic-drm.c priv->map = devm_regmap_init_mmio(dev, base, base 16 drivers/gpu/drm/lima/lima_sched.c struct dma_fence base; base 47 drivers/gpu/drm/lima/lima_sched.c return container_of(fence, struct lima_fence, base); base 59 drivers/gpu/drm/lima/lima_sched.c return f->pipe->base.name; base 74 drivers/gpu/drm/lima/lima_sched.c call_rcu(&f->base.rcu, lima_fence_release_rcu); base 92 drivers/gpu/drm/lima/lima_sched.c dma_fence_init(&fence->base, &lima_fence_ops, &pipe->fence_lock, base 100 drivers/gpu/drm/lima/lima_sched.c return container_of(job, struct lima_sched_task, base); base 105 drivers/gpu/drm/lima/lima_sched.c return container_of(sched, struct lima_sched_pipe, base); base 122 drivers/gpu/drm/lima/lima_sched.c err = drm_sched_job_init(&task->base, &context->base, vm); base 142 drivers/gpu/drm/lima/lima_sched.c drm_sched_job_cleanup(&task->base); base 162 drivers/gpu/drm/lima/lima_sched.c struct drm_sched_rq *rq = pipe->base.sched_rq + DRM_SCHED_PRIORITY_NORMAL; base 164 drivers/gpu/drm/lima/lima_sched.c return drm_sched_entity_init(&context->base, &rq, 1, guilty); base 170 drivers/gpu/drm/lima/lima_sched.c drm_sched_entity_fini(&context->base); base 176 drivers/gpu/drm/lima/lima_sched.c struct dma_fence *fence = dma_fence_get(&task->base.s_fence->finished); base 178 drivers/gpu/drm/lima/lima_sched.c drm_sched_entity_push_job(&task->base, &context->base); base 209 drivers/gpu/drm/lima/lima_sched.c task->fence = &fence->base; base 261 drivers/gpu/drm/lima/lima_sched.c drm_sched_stop(&pipe->base, &task->base); base 264 drivers/gpu/drm/lima/lima_sched.c drm_sched_increase_karma(&task->base); base 283 drivers/gpu/drm/lima/lima_sched.c drm_sched_resubmit_jobs(&pipe->base); base 284 drivers/gpu/drm/lima/lima_sched.c drm_sched_start(&pipe->base, true); base 340 drivers/gpu/drm/lima/lima_sched.c return drm_sched_init(&pipe->base, &lima_sched_ops, 1, 0, base 346 drivers/gpu/drm/lima/lima_sched.c drm_sched_fini(&pipe->base); base 12 drivers/gpu/drm/lima/lima_sched.h struct drm_sched_job base; base 28 drivers/gpu/drm/lima/lima_sched.h struct drm_sched_entity base; base 38 drivers/gpu/drm/lima/lima_sched.h struct drm_gpu_scheduler base; base 36 drivers/gpu/drm/mediatek/mtk_drm_crtc.c struct drm_crtc base; base 53 drivers/gpu/drm/mediatek/mtk_drm_crtc.c struct drm_crtc_state base; base 63 drivers/gpu/drm/mediatek/mtk_drm_crtc.c return container_of(c, struct mtk_drm_crtc, base); base 68 drivers/gpu/drm/mediatek/mtk_drm_crtc.c return container_of(s, struct mtk_crtc_state, base); base 73 drivers/gpu/drm/mediatek/mtk_drm_crtc.c struct drm_crtc *crtc = &mtk_crtc->base; base 85 drivers/gpu/drm/mediatek/mtk_drm_crtc.c drm_crtc_handle_vblank(&mtk_crtc->base); base 114 drivers/gpu/drm/mediatek/mtk_drm_crtc.c crtc->state = &state->base; base 117 drivers/gpu/drm/mediatek/mtk_drm_crtc.c state->base.crtc = crtc; base 128 drivers/gpu/drm/mediatek/mtk_drm_crtc.c __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); base 130 drivers/gpu/drm/mediatek/mtk_drm_crtc.c WARN_ON(state->base.crtc != crtc); base 131 drivers/gpu/drm/mediatek/mtk_drm_crtc.c state->base.crtc = crtc; base 133 drivers/gpu/drm/mediatek/mtk_drm_crtc.c return &state->base; base 167 drivers/gpu/drm/mediatek/mtk_drm_crtc.c mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); base 212 drivers/gpu/drm/mediatek/mtk_drm_crtc.c struct drm_crtc *crtc = &mtk_crtc->base; base 300 drivers/gpu/drm/mediatek/mtk_drm_crtc.c struct drm_device *drm = mtk_crtc->base.dev; base 301 drivers/gpu/drm/mediatek/mtk_drm_crtc.c struct drm_crtc *crtc = &mtk_crtc->base; base 335 drivers/gpu/drm/mediatek/mtk_drm_crtc.c struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); base 375 drivers/gpu/drm/mediatek/mtk_drm_crtc.c DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); base 400 drivers/gpu/drm/mediatek/mtk_drm_crtc.c DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); base 431 drivers/gpu/drm/mediatek/mtk_drm_crtc.c if (mtk_crtc->event && state->base.event) base 434 drivers/gpu/drm/mediatek/mtk_drm_crtc.c if (state->base.event) { base 435 drivers/gpu/drm/mediatek/mtk_drm_crtc.c state->base.event->pipe = drm_crtc_index(crtc); base 437 drivers/gpu/drm/mediatek/mtk_drm_crtc.c mtk_crtc->event = state->base.event; base 438 drivers/gpu/drm/mediatek/mtk_drm_crtc.c state->base.event = NULL; base 512 drivers/gpu/drm/mediatek/mtk_drm_crtc.c ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, base 517 drivers/gpu/drm/mediatek/mtk_drm_crtc.c drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); base 522 drivers/gpu/drm/mediatek/mtk_drm_crtc.c drm_crtc_cleanup(&mtk_crtc->base); base 624 drivers/gpu/drm/mediatek/mtk_drm_crtc.c drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); base 625 drivers/gpu/drm/mediatek/mtk_drm_crtc.c drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size); base 28 drivers/gpu/drm/mediatek/mtk_drm_gem.c ret = drm_gem_object_init(dev, &mtk_gem_obj->base, size); base 50 drivers/gpu/drm/mediatek/mtk_drm_gem.c obj = &mtk_gem->base; base 115 drivers/gpu/drm/mediatek/mtk_drm_gem.c ret = drm_gem_handle_create(file_priv, &mtk_gem->base, &args->handle); base 120 drivers/gpu/drm/mediatek/mtk_drm_gem.c drm_gem_object_put_unlocked(&mtk_gem->base); base 125 drivers/gpu/drm/mediatek/mtk_drm_gem.c mtk_drm_gem_free_object(&mtk_gem->base); base 238 drivers/gpu/drm/mediatek/mtk_drm_gem.c return &mtk_gem->base; base 26 drivers/gpu/drm/mediatek/mtk_drm_gem.h struct drm_gem_object base; base 35 drivers/gpu/drm/mediatek/mtk_drm_gem.h #define to_mtk_gem_obj(x) container_of(x, struct mtk_drm_gem_obj, base) base 41 drivers/gpu/drm/mediatek/mtk_drm_plane.c plane->state = &state->base; base 44 drivers/gpu/drm/mediatek/mtk_drm_plane.c state->base.plane = plane; base 57 drivers/gpu/drm/mediatek/mtk_drm_plane.c __drm_atomic_helper_plane_duplicate_state(plane, &state->base); base 59 drivers/gpu/drm/mediatek/mtk_drm_plane.c WARN_ON(state->base.plane != plane); base 63 drivers/gpu/drm/mediatek/mtk_drm_plane.c return &state->base; base 27 drivers/gpu/drm/mediatek/mtk_drm_plane.h struct drm_plane_state base; base 34 drivers/gpu/drm/mediatek/mtk_drm_plane.h return container_of(state, struct mtk_plane_state, base); base 33 drivers/gpu/drm/meson/meson_crtc.c struct drm_crtc base; base 40 drivers/gpu/drm/meson/meson_crtc.c #define to_meson_crtc(x) container_of(x, struct meson_crtc, base) base 569 drivers/gpu/drm/meson/meson_crtc.c crtc = &meson_crtc->base; base 176 drivers/gpu/drm/meson/meson_drv.c ap->ranges[0].base = 0; base 80 drivers/gpu/drm/meson/meson_overlay.c struct drm_plane base; base 83 drivers/gpu/drm/meson/meson_overlay.c #define to_meson_overlay(x) container_of(x, struct meson_overlay, base) base 567 drivers/gpu/drm/meson/meson_overlay.c plane = &meson_overlay->base; base 64 drivers/gpu/drm/meson/meson_plane.c struct drm_plane base; base 68 drivers/gpu/drm/meson/meson_plane.c #define to_meson_plane(x) container_of(x, struct meson_plane, base) base 377 drivers/gpu/drm/meson/meson_plane.c plane = &meson_plane->base; base 98 drivers/gpu/drm/mgag200/mgag200_drv.h #define to_mga_crtc(x) container_of(x, struct mga_crtc, base) base 99 drivers/gpu/drm/mgag200/mgag200_drv.h #define to_mga_encoder(x) container_of(x, struct mga_encoder, base) base 100 drivers/gpu/drm/mgag200/mgag200_drv.h #define to_mga_connector(x) container_of(x, struct mga_connector, base) base 103 drivers/gpu/drm/mgag200/mgag200_drv.h struct drm_crtc base; base 115 drivers/gpu/drm/mgag200/mgag200_drv.h struct drm_encoder base; base 128 drivers/gpu/drm/mgag200/mgag200_drv.h struct drm_connector base; base 1444 drivers/gpu/drm/mgag200/mgag200_mode.c drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs); base 1446 drivers/gpu/drm/mgag200/mgag200_mode.c drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE); base 1449 drivers/gpu/drm/mgag200/mgag200_mode.c drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs); base 1511 drivers/gpu/drm/mgag200/mgag200_mode.c encoder = &mga_encoder->base; base 1680 drivers/gpu/drm/mgag200/mgag200_mode.c connector = &mga_connector->base; base 416 drivers/gpu/drm/msm/adreno/a2xx_gpu.c .base = { base 460 drivers/gpu/drm/msm/adreno/a2xx_gpu.c adreno_gpu = &a2xx_gpu->base; base 461 drivers/gpu/drm/msm/adreno/a2xx_gpu.c gpu = &adreno_gpu->base; base 489 drivers/gpu/drm/msm/adreno/a2xx_gpu.c a2xx_destroy(&a2xx_gpu->base.base); base 16 drivers/gpu/drm/msm/adreno/a2xx_gpu.h struct adreno_gpu base; base 19 drivers/gpu/drm/msm/adreno/a2xx_gpu.h #define to_a2xx_gpu(x) container_of(x, struct a2xx_gpu, base) base 435 drivers/gpu/drm/msm/adreno/a3xx_gpu.c .base = { base 482 drivers/gpu/drm/msm/adreno/a3xx_gpu.c adreno_gpu = &a3xx_gpu->base; base 483 drivers/gpu/drm/msm/adreno/a3xx_gpu.c gpu = &adreno_gpu->base; base 527 drivers/gpu/drm/msm/adreno/a3xx_gpu.c a3xx_destroy(&a3xx_gpu->base.base); base 19 drivers/gpu/drm/msm/adreno/a3xx_gpu.h struct adreno_gpu base; base 25 drivers/gpu/drm/msm/adreno/a3xx_gpu.h #define to_a3xx_gpu(x) container_of(x, struct a3xx_gpu, base) base 525 drivers/gpu/drm/msm/adreno/a4xx_gpu.c .base = { base 566 drivers/gpu/drm/msm/adreno/a4xx_gpu.c adreno_gpu = &a4xx_gpu->base; base 567 drivers/gpu/drm/msm/adreno/a4xx_gpu.c gpu = &adreno_gpu->base; base 611 drivers/gpu/drm/msm/adreno/a4xx_gpu.c a4xx_destroy(&a4xx_gpu->base.base); base 16 drivers/gpu/drm/msm/adreno/a4xx_gpu.h struct adreno_gpu base; base 22 drivers/gpu/drm/msm/adreno/a4xx_gpu.h #define to_a4xx_gpu(x) container_of(x, struct a4xx_gpu, base) base 68 drivers/gpu/drm/msm/adreno/a5xx_gpu.c ptr = msm_gem_get_vaddr(&obj->base); base 88 drivers/gpu/drm/msm/adreno/a5xx_gpu.c msm_gem_put_vaddr(&obj->base); base 1142 drivers/gpu/drm/msm/adreno/a5xx_gpu.c struct msm_gpu_state base; base 1274 drivers/gpu/drm/msm/adreno/a5xx_gpu.c adreno_gpu_state_get(gpu, &(a5xx_state->base)); base 1276 drivers/gpu/drm/msm/adreno/a5xx_gpu.c a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS); base 1283 drivers/gpu/drm/msm/adreno/a5xx_gpu.c return &a5xx_state->base; base 1291 drivers/gpu/drm/msm/adreno/a5xx_gpu.c struct a5xx_gpu_state, base); base 1315 drivers/gpu/drm/msm/adreno/a5xx_gpu.c struct a5xx_gpu_state, base); base 1377 drivers/gpu/drm/msm/adreno/a5xx_gpu.c .base = { base 1438 drivers/gpu/drm/msm/adreno/a5xx_gpu.c adreno_gpu = &a5xx_gpu->base; base 1439 drivers/gpu/drm/msm/adreno/a5xx_gpu.c gpu = &adreno_gpu->base; base 1450 drivers/gpu/drm/msm/adreno/a5xx_gpu.c a5xx_destroy(&(a5xx_gpu->base.base)); base 16 drivers/gpu/drm/msm/adreno/a5xx_gpu.h struct adreno_gpu base; base 41 drivers/gpu/drm/msm/adreno/a5xx_gpu.h #define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base) base 79 drivers/gpu/drm/msm/adreno/a5xx_preempt.c struct msm_gpu *gpu = &a5xx_gpu->base.base; base 226 drivers/gpu/drm/msm/adreno/a5xx_preempt.c struct adreno_gpu *adreno_gpu = &a5xx_gpu->base; base 227 drivers/gpu/drm/msm/adreno/a5xx_preempt.c struct msm_gpu *gpu = &adreno_gpu->base; base 16 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; base 17 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct msm_gpu *gpu = &adreno_gpu->base; base 106 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; base 107 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct msm_gpu *gpu = &adreno_gpu->base; base 559 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; base 695 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; base 696 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct msm_gpu *gpu = &adreno_gpu->base; base 785 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; base 786 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct msm_gpu *gpu = &adreno_gpu->base; base 846 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct msm_gpu *gpu = &a6xx_gpu->base.base; base 1094 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; base 1095 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct msm_gpu *gpu = &adreno_gpu->base; base 1144 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; base 1145 drivers/gpu/drm/msm/adreno/a6xx_gmu.c struct msm_gpu *gpu = &adreno_gpu->base; base 822 drivers/gpu/drm/msm/adreno/a6xx_gpu.c .base = { base 861 drivers/gpu/drm/msm/adreno/a6xx_gpu.c adreno_gpu = &a6xx_gpu->base; base 862 drivers/gpu/drm/msm/adreno/a6xx_gpu.c gpu = &adreno_gpu->base; base 869 drivers/gpu/drm/msm/adreno/a6xx_gpu.c a6xx_destroy(&(a6xx_gpu->base.base)); base 881 drivers/gpu/drm/msm/adreno/a6xx_gpu.c a6xx_destroy(&(a6xx_gpu->base.base)); base 16 drivers/gpu/drm/msm/adreno/a6xx_gpu.h struct adreno_gpu base; base 26 drivers/gpu/drm/msm/adreno/a6xx_gpu.h #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) base 17 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c struct msm_gpu_state base; base 447 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c dbgahb->registers[j] - (dbgahb->base >> 2); base 879 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c adreno_gpu_state_get(gpu, &a6xx_state->base); base 885 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c return &a6xx_state->base; base 902 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c return &a6xx_state->base; base 911 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c struct a6xx_gpu_state, base); base 1118 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c struct a6xx_gpu_state, base); base 124 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h { .name = #_id, .statetype = _type, .base = _base, \ base 130 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h u32 base; base 180 drivers/gpu/drm/msm/adreno/adreno_gpu.c *value = adreno_gpu->base.fast_rate; base 211 drivers/gpu/drm/msm/adreno/adreno_gpu.c struct drm_device *drm = adreno_gpu->base.dev; base 902 drivers/gpu/drm/msm/adreno/adreno_gpu.c struct msm_gpu *gpu = &adreno_gpu->base; base 927 drivers/gpu/drm/msm/adreno/adreno_gpu.c return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, base 933 drivers/gpu/drm/msm/adreno/adreno_gpu.c struct msm_gpu *gpu = &adreno_gpu->base; base 941 drivers/gpu/drm/msm/adreno/adreno_gpu.c msm_gpu_cleanup(&adreno_gpu->base); base 67 drivers/gpu/drm/msm/adreno/adreno_gpu.h struct msm_gpu_funcs base; base 86 drivers/gpu/drm/msm/adreno/adreno_gpu.h struct msm_gpu base; base 127 drivers/gpu/drm/msm/adreno/adreno_gpu.h #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) base 341 drivers/gpu/drm/msm/adreno/adreno_gpu.h val = gpu_read(&gpu->base, reg - 1); base 350 drivers/gpu/drm/msm/adreno/adreno_gpu.h gpu_write(&gpu->base, reg - 1, data); base 58 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c tmp_crtc->base.id); base 98 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c crtc->base.id, perf->core_clk_rate, base 144 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl, base 200 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c DPU_DEBUG("crtc=%d bw=%llu\n", tmp_crtc->base.id, base 240 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c trace_dpu_cmd_release_bw(crtc->base.id); base 241 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id); base 310 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c crtc->base.id, stop_req, kms->perf.core_clk_rate); base 328 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c crtc->base.id, params_changed, base 343 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c DPU_DEBUG("crtc=%d disable\n", crtc->base.id); base 350 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c trace_dpu_perf_crtc_update(crtc->base.id, new->bw_ctl, base 357 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c crtc->base.id); base 85 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c drm_get_format_name(format->base.pixel_format, &format_name), base 143 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c crtc->base.id, base 145 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c plane->base.id, base 147 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c state->fb ? state->fb->base.id : -1); base 149 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); base 163 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c format->base.pixel_format, base 308 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, base 337 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c crtc->base.id, ktime_to_ns(fevent->ts)); base 384 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c DRM_ERROR("crtc%d event %d overflow\n", crtc->base.id, event); base 437 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c crtc->base.id, crtc->state->enable); base 441 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c DPU_DEBUG("crtc%d\n", crtc->base.id); base 495 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c crtc->base.id, crtc->state->enable); base 499 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c DPU_DEBUG("crtc%d\n", crtc->base.id); base 576 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c DPU_DEBUG("crtc%d\n", crtc->base.id); base 632 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c DPU_DEBUG("crtc%d first commit\n", crtc->base.id); base 634 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c DPU_DEBUG("crtc%d commit\n", crtc->base.id); base 654 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c __drm_atomic_helper_crtc_reset(crtc, &cstate->base); base 681 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); base 683 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c return &cstate->base; base 703 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c mode = &cstate->base.adjusted_mode; base 706 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); base 725 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c crtc->base.id, base 777 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); base 842 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c crtc->base.id, state->enable, state->active); base 869 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c dpu_crtc->name, plane->base.id, rc); base 911 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c pipe_staged[i]->plane->base.id); base 960 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c multirect_plane[i].r0->plane->base.id, base 961 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c multirect_plane[i].r1->plane->base.id); base 972 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c crtc->base.id, rc); base 994 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c left_pid = prv_pstate->dpu_pstate->base.plane->base.id; base 997 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c right_pid = cur_pstate->dpu_pstate->base.plane->base.id; base 1048 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc); base 1092 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c crtc = &dpu_crtc->base; base 1100 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id, base 1126 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id, base 1133 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c fb->base.id, (char *) &fb->format->format, base 1242 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c &dpu_crtc->base, base 1302 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c crtc = &dpu_crtc->base; base 1326 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); base 142 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h struct drm_crtc base; base 176 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h #define to_dpu_crtc(x) container_of(x, struct dpu_crtc, base) base 195 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h struct drm_crtc_state base; base 214 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h container_of(x, struct dpu_crtc_state, base) base 30 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) base 33 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) base 36 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c (p) ? (p)->parent->base.id : -1, \ base 42 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c (p) ? (p)->parent->base.id : -1, \ base 171 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct drm_encoder base; base 210 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) base 643 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c drm_enc = &dpu_enc->base; base 1003 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG); base 1011 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_CTL); base 1019 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, DPU_HW_BLK_LM); base 1057 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, base 1155 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; base 1228 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); base 1412 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_encoder_resource_control(&dpu_enc->base, base 1415 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, base 1586 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); base 1594 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c &dpu_enc->base, base 1733 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct drm_encoder *drm_enc = &dpu_enc->base; base 1770 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time)) base 1773 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time); base 1938 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id); base 2055 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_params.parent = &dpu_enc->base; base 2135 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct drm_encoder *drm_enc = &dpu_enc->base; base 2237 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs, base 2244 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); base 2249 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c return &dpu_enc->base; base 259 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h struct dpu_encoder_phys base; base 14 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c (e) && (e)->base.parent ? \ base 15 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c (e)->base.parent->base.id : -1, \ base 16 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__) base 19 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c (e) && (e)->base.parent ? \ base 20 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c (e)->base.parent->base.id : -1, \ base 21 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__) base 24 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c container_of(x, struct dpu_encoder_phys_cmd, base) base 779 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc = &cmd_enc->base; base 14 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c (e)->parent->base.id : -1, \ base 20 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c (e)->parent->base.id : -1, \ base 25 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c container_of(x, struct dpu_encoder_phys_vid, base) base 36 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c .base.pixel_format = DRM_FORMAT_ ## fmt, \ base 55 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c .base.pixel_format = DRM_FORMAT_ ## fmt, \ base 75 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c .base.pixel_format = DRM_FORMAT_ ## fmt, \ base 93 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c .base.pixel_format = DRM_FORMAT_ ## fmt, \ base 112 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c .base.pixel_format = DRM_FORMAT_ ## fmt, \ base 130 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c .base.pixel_format = DRM_FORMAT_ ## fmt, \ base 149 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c .base.pixel_format = DRM_FORMAT_ ## fmt, \ base 169 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c .base.pixel_format = DRM_FORMAT_ ## fmt, \ base 561 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c if (fmt->base.pixel_format == DRM_FORMAT_NV12) { base 573 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c if (fmt->base.pixel_format == dpu_media_ubwc_map[i].format) { base 599 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c (char *)&fmt->base.pixel_format); base 693 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c if ((fmt->base.pixel_format == DRM_FORMAT_NV12) && base 937 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c info = drm_format_info(fmt->base.pixel_format); base 996 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c if (format == map[i].base.pixel_format) { base 1022 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c return &fmt->base; base 66 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = 0x0, .len = 0x45C, base 94 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = 0x1000, .len = 0xE4, base 99 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = 0x1200, .len = 0xE4, base 104 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = 0x1400, .len = 0xE4, base 109 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = 0x1600, .len = 0xE4, base 114 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = 0x1800, .len = 0xE4, base 138 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ base 141 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = 0xa00, .len = 0xa0,}, \ base 144 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = 0x1a00, .len = 0x100,}, \ base 158 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ base 179 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = _base, .len = 0x1c8, \ base 221 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = _base, .len = 0x320, \ base 241 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, base 243 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, base 248 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, base 255 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = _base, .len = 0xd4, \ base 262 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = _base, .len = 0xd4, \ base 280 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = _base, .len = 0x280, \ base 303 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = 0, .len = 0x1040, base 320 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c base 195 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h u32 base; \ base 210 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h u32 base; \ base 41 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b->blk_off = m->ctl[i].base; base 501 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops); base 509 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c dpu_hw_blk_destroy(&ctx->base); base 165 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h struct dpu_hw_blk base; base 186 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h return container_of(hw, struct dpu_hw_ctl, base); base 1082 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c hw->blk_off = m->mdp[0].base; base 70 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b->blk_off = m->intf[i].base; base 287 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops); base 295 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c dpu_hw_blk_destroy(&intf->base); base 74 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h struct dpu_hw_blk base; base 37 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b->blk_off = m->mixer[i].base; base 187 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); base 195 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c dpu_hw_blk_destroy(&lm->base); base 59 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h struct dpu_hw_blk base; base 82 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h return container_of(hw, struct dpu_hw_mixer, base); base 352 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h struct msm_format base; base 368 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h #define to_dpu_format(x) container_of(x, struct dpu_format, base) base 41 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b->blk_off = m->pingpong[i].base; base 217 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops); base 225 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c dpu_hw_blk_destroy(&pp->base); base 88 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h struct dpu_hw_blk base; base 147 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c *idx = sblk->src_blk.base; base 152 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c *idx = sblk->scaler_blk.base; base 156 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c *idx = sblk->csc_blk.base; base 680 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b->blk_off = catalog->sspp[i].base; base 721 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops); base 729 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c dpu_hw_blk_destroy(&ctx->base); base 373 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h struct dpu_hw_blk base; base 305 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b->blk_off = m->mdp[i].base; base 345 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops); base 353 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c dpu_hw_blk_destroy(&mdp->base); base 144 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h struct dpu_hw_blk base; base 223 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b->blk_off = m->vbif[i].base; base 149 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c void __iomem *base; base 163 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c base = dpu_kms->mmio + regset->offset; base 179 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c seq_printf(s, " %08x", readl_relaxed(base + i)); base 373 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); base 378 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); base 671 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c encoder->base.id, rc); base 723 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c if (!dpu_kms->base.aspace) base 726 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c mmu = dpu_kms->base.aspace->mmu; base 730 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c msm_gem_address_space_put(dpu_kms->base.aspace); base 732 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c dpu_kms->base.aspace = NULL; base 763 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c dpu_kms->base.aspace = aspace; base 990 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c dpu_kms->base.irq = irq; base 992 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c return &dpu_kms->base; base 1017 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c msm_kms_init(&dpu_kms->base, &kms_funcs); base 1024 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c priv->kms = &dpu_kms->base; base 26 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h #define DRMID(x) ((x) ? (x)->base.id : -1) base 96 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h struct msm_kms base; base 140 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h #define to_dpu_kms(x) container_of(x, struct dpu_kms, base) base 13 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c #define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base) base 26 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c struct msm_mdss base; base 150 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c dev = dpu_mdss->base.dev->dev; base 273 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c dpu_mdss->base.dev = dev; base 274 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c dpu_mdss->base.funcs = &mdss_funcs; base 287 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c priv->mdss = &dpu_mdss->base; base 29 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) base 32 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) base 84 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c struct drm_plane base; base 120 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) base 154 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c if (!tmp->base.state->visible) base 157 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c pdpu->base.base.id, tmp->base.base.id, base 185 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c plane->base.id, pdpu->pipe - SSPP_VIG0, base 186 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c (char *)&fmt->base.pixel_format, base 251 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c (fmt) ? fmt->base.pixel_format : 0, base 255 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c plane->base.id, base 257 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c fmt ? (char *)&fmt->base.pixel_format : NULL, base 302 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c (fmt) ? fmt->base.pixel_format : 0, base 308 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c plane->base.id, base 310 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c fmt ? (char *)&fmt->base.pixel_format : NULL, base 352 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c plane->base.id, base 408 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c plane->base.id, qos_params.num, base 422 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); base 423 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c struct msm_gem_address_space *aspace = kms->base.aspace; base 552 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); base 576 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c const struct drm_plane *plane = &pdpu->base; base 668 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c drm_state[i]->plane->base.id); base 729 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c drm_state[R0]->plane->base.id, base 730 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c drm_state[R1]->plane->base.id); base 769 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); base 775 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); base 778 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c pstate->aspace = kms->base.aspace; base 818 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); base 989 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), base 990 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c crtc->base.id, DRM_RECT_ARG(&state->dst), base 991 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); base 1199 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); base 1201 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c return &pstate->base; base 1229 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c pstate->base.plane = plane; base 1231 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c plane->state = &pstate->base; base 1268 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c plane->base.id, plane->fb->width, base 1278 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c DPU_DEBUG("Inactive plane:%d\n", plane->base.id); base 1333 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c sblk->src_blk.base + cfg->base, base 1342 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c sblk->scaler_blk.base + cfg->base, base 1357 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c sblk->csc_blk.base + cfg->base, base 1476 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c plane = &pdpu->base; base 1548 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id); base 1553 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c pipe, plane->base.id, master_plane_id); base 30 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h struct drm_plane_state base; base 55 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h container_of(x, struct dpu_plane_state, base) base 543 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c ret = _dpu_rm_reserve_lms(rm, enc->base.id, reqs); base 549 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c ret = _dpu_rm_reserve_ctls(rm, enc->base.id, &reqs->topology); base 555 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id, &reqs->hw_res); base 600 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c _dpu_rm_release_reservation(rm, enc->base.id); base 620 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c enc->base.id, crtc_state->crtc->base.id, test_only); base 634 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c _dpu_rm_release_reservation(rm, enc->base.id); base 638 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c enc->base.id); base 639 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c _dpu_rm_release_reservation(rm, enc->base.id); base 666 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __entry->fb_id = state ? state->fb->base.id : 0; base 16 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct drm_crtc base; base 59 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base) base 72 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank); base 118 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base); base 119 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct msm_kms *kms = &mdp4_kms->base.base; base 280 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err); base 302 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err); base 358 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct msm_kms *kms = &mdp4_kms->base.base; base 408 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct msm_kms *kms = &mdp4_kms->base.base; base 498 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct drm_crtc *crtc = &mdp4_crtc->base; base 502 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank); base 519 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c struct drm_crtc *crtc = &mdp4_crtc->base; base 628 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c crtc = &mdp4_crtc->base; base 15 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c struct drm_encoder base; base 19 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c #define to_mdp4_dsi_encoder(x) container_of(x, struct mdp4_dsi_encoder, base) base 111 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_PRIMARY_VSYNC); base 159 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c encoder = &mdp4_dsi_encoder->base; base 13 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c struct drm_encoder base; base 20 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c #define to_mdp4_dtv_encoder(x) container_of(x, struct mdp4_dtv_encoder, base) base 33 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c struct drm_device *dev = mdp4_dtv_encoder->base.dev; base 160 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC); base 235 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c encoder = &mdp4_dtv_encoder->base; base 187 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c .base = { base 435 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c mdp_kms_init(&mdp4_kms->base, &kms_funcs); base 437 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c kms = &mdp4_kms->base.base; base 20 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h struct mdp_kms base; base 43 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base) base 16 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c struct drm_encoder base; base 25 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c #define to_mdp4_lcdc_encoder(x) container_of(x, struct mdp4_lcdc_encoder, base) base 37 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c struct drm_device *dev = mdp4_lcdc_encoder->base.dev; base 341 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_PRIMARY_VSYNC); base 444 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c encoder = &mdp4_lcdc_encoder->base; base 11 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_connector.c struct drm_connector base; base 16 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_connector.c #define to_mdp4_lvds_connector(x) container_of(x, struct mdp4_lvds_connector, base) base 111 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_connector.c connector = &mdp4_lvds_connector->base; base 16 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c struct drm_plane base; base 27 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c #define to_mdp4_plane(x) container_of(x, struct mdp4_plane, base) base 97 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c struct msm_kms *kms = &mdp4_kms->base.base; base 103 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c DBG("%s: cleanup: FB[%u]", mdp4_plane->name, fb->base.id); base 142 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c struct msm_kms *kms = &mdp4_kms->base.base; base 223 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c fb->base.id, src_x, src_y, src_w, src_h, base 224 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); base 365 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c plane = &mdp4_plane->base; base 384 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c mdp4_plane_install_properties(plane, &plane->base); base 352 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 0: return (mdp5_cfg->ctl.base[0]); base 353 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 1: return (mdp5_cfg->ctl.base[1]); base 354 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 2: return (mdp5_cfg->ctl.base[2]); base 355 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 3: return (mdp5_cfg->ctl.base[3]); base 356 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 4: return (mdp5_cfg->ctl.base[4]); base 539 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]); base 540 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]); base 541 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]); base 542 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]); base 543 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]); base 544 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]); base 545 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]); base 546 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]); base 547 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]); base 548 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]); base 549 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_CURSOR0: return (mdp5_cfg->pipe_cursor.base[0]); base 550 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case SSPP_CURSOR1: return (mdp5_cfg->pipe_cursor.base[1]); base 1066 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 0: return (mdp5_cfg->lm.base[0]); base 1067 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 1: return (mdp5_cfg->lm.base[1]); base 1068 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 2: return (mdp5_cfg->lm.base[2]); base 1069 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 3: return (mdp5_cfg->lm.base[3]); base 1070 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 4: return (mdp5_cfg->lm.base[4]); base 1071 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 5: return (mdp5_cfg->lm.base[5]); base 1261 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 0: return (mdp5_cfg->dspp.base[0]); base 1262 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 1: return (mdp5_cfg->dspp.base[1]); base 1263 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 2: return (mdp5_cfg->dspp.base[2]); base 1264 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 3: return (mdp5_cfg->dspp.base[3]); base 1306 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 0: return (mdp5_cfg->pp.base[0]); base 1307 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 1: return (mdp5_cfg->pp.base[1]); base 1308 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 2: return (mdp5_cfg->pp.base[2]); base 1309 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 3: return (mdp5_cfg->pp.base[3]); base 1395 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 0: return (mdp5_cfg->wb.base[0]); base 1396 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 1: return (mdp5_cfg->wb.base[1]); base 1397 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 2: return (mdp5_cfg->wb.base[2]); base 1398 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 3: return (mdp5_cfg->wb.base[3]); base 1399 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 4: return (mdp5_cfg->wb.base[4]); base 1746 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 0: return (mdp5_cfg->intf.base[0]); base 1747 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 1: return (mdp5_cfg->intf.base[1]); base 1748 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 2: return (mdp5_cfg->intf.base[2]); base 1749 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 3: return (mdp5_cfg->intf.base[3]); base 1750 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 4: return (mdp5_cfg->intf.base[4]); base 1892 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 0: return (mdp5_cfg->ad.base[0]); base 1893 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h case 1: return (mdp5_cfg->ad.base[1]); base 35 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 }, base 40 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x01100, 0x01500, 0x01900 }, base 49 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x01d00, 0x02100, 0x02500 }, base 57 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x02900, 0x02d00 }, base 64 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 }, base 83 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x04500, 0x04900, 0x04d00 }, base 87 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x21a00, 0x21b00, 0x21c00 }, base 90 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x21000, 0x21200, 0x21400, 0x21600 }, base 119 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 }, base 124 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x01100, 0x01500, 0x01900 }, base 131 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x01d00, 0x02100, 0x02500 }, base 137 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x02900, 0x02d00 }, base 142 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 }, base 161 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x04500, 0x04900, 0x04d00 }, base 165 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x13000, 0x13200 }, base 169 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x12c00, 0x12d00, 0x12e00 }, base 172 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x12400, 0x12600, 0x12800, 0x12a00 }, base 209 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 }, base 214 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x01100, 0x01500, 0x01900, 0x01d00 }, base 221 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x02100, 0x02500, 0x02900, 0x02d00 }, base 227 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x03100, 0x03500 }, base 232 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 }, base 255 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x05100, 0x05500, 0x05900, 0x05d00 }, base 260 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x13400, 0x13600, 0x13800 }, base 264 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 }, base 267 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 }, base 282 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x0 }, base 296 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, base 301 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x04000 }, base 308 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x14000, 0x16000 }, base 314 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x24000 }, base 319 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x44000, 0x47000 }, base 332 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x54000 }, base 336 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x00000, 0x6a800 }, base 371 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, base 376 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x04000, 0x06000, 0x08000, 0x0a000 }, base 383 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, base 389 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x24000, 0x26000 }, base 394 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 }, base 417 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x54000, 0x56000, 0x58000, 0x5a000 }, base 422 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x78000, 0x78800, 0x79000 }, base 426 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x70000, 0x70800, 0x71000, 0x71800 }, base 429 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 }, base 451 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, base 456 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x04000, 0x06000, 0x08000, 0x0a000 }, base 467 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, base 477 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x24000, 0x26000 }, base 485 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x34000, 0x36000 }, base 495 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 }, base 518 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x54000, 0x56000 }, base 522 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x78000, 0x78800, 0x79000 }, base 526 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x70000, 0x70800, 0x71000, 0x71800 }, base 530 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x79200 }, base 534 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x80000, 0x80400 }, base 537 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 }, base 556 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x01000, 0x01200, 0x01400 }, base 561 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x04000 }, base 572 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x14000, 0x16000 }, base 581 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x24000 }, base 589 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x34000 }, base 599 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x44000, 0x45000 }, base 612 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x54000 }, base 617 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x70000 }, base 621 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x79200 }, base 624 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x6a000, 0x6a800 }, base 644 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, base 649 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x04000, 0x06000, 0x08000, 0x0a000 }, base 660 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, base 670 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x24000, 0x26000, 0x28000, 0x2a000 }, base 678 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x34000, 0x36000 }, base 688 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 }, base 711 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x54000, 0x56000 }, base 715 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x78000, 0x78800, 0x79000 }, base 719 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x70000, 0x70800, 0x71000, 0x71800 }, base 723 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x79200 }, base 727 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x80000, 0x80400 }, base 730 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 }, base 28 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t base[MAX_BASES] base 75 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h uint32_t base[MAX_BASES]; base 23 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct drm_crtc base; base 63 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base) base 78 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank); base 165 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base); base 166 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct msm_kms *kms = &mdp5_kms->base.base; base 279 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb)); base 291 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c msm_framebuffer_format(pstates[i]->base.fb)); base 292 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c plane = pstates[i]->base.plane; base 429 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done); base 431 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); base 497 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err); base 500 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done); base 673 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c start = get_start_stage(crtc, state, &pstates[0].state->base); base 865 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct msm_kms *kms = &mdp5_kms->base.base; base 1023 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c __drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base); base 1025 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c return &mdp5_cstate->base; base 1045 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); base 1074 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct drm_crtc *crtc = &mdp5_crtc->base; base 1078 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank); base 1094 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus); base 1159 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp_irq_update(&mdp5_kms->base); base 1218 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c crtc = &mdp5_crtc->base; base 717 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c if (WARN_ON(!ctl_cfg->base[c])) { base 725 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c ctl->reg_offset = ctl_cfg->base[c]; base 223 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp_irq_wait(&mdp5_kms->base, intf2vblank(mixer, intf)); base 419 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c encoder = &mdp5_encoder->base; base 113 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); base 115 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c return &state->base; base 144 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c &state->base, base 284 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c .base = { base 696 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c mdp_kms_init(&mdp5_kms->base, &kms_funcs); base 718 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c !config->hw->intf.base[i]) base 846 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); base 852 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); base 858 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); base 864 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c cursor_planes, hw_cfg->pipe_cursor.base, base 1036 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c priv->kms = &mdp5_kms->base.base; base 21 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h struct mdp_kms base; base 70 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base) base 75 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h #define to_mdp5_global_state(x) container_of(x, struct mdp5_global_state, base) base 77 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h struct drm_private_state base; base 94 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h struct drm_plane_state base; base 108 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h container_of(x, struct mdp5_plane_state, base) base 117 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h struct drm_crtc_state base; base 138 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h container_of(x, struct mdp5_crtc_state, base) base 160 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h struct drm_encoder base; base 168 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h #define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base) base 12 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c #define to_mdp5_mdss(x) container_of(x, struct mdp5_mdss, base) base 15 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c struct msm_mdss base; base 118 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c struct device *dev = mdp5_mdss->base.dev->dev; base 165 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c to_platform_device(mdp5_mdss->base.dev->dev); base 222 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c mdp5_mdss->base.dev = dev; base 269 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c mdp5_mdss->base.funcs = &mdss_funcs; base 270 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c priv->mdss = &mdp5_mdss->base; base 15 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct drm_plane base; base 20 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base) base 78 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c drm_object_attach_property(&plane->base, prop, init_val); \ base 193 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_state->base.plane = plane; base 195 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c plane->state = &mdp5_state->base; base 211 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base); base 213 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c return &mdp5_state->base; base 243 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct msm_kms *kms = &mdp5_kms->base.base; base 249 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id); base 538 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct msm_kms *kms = &mdp5_kms->base.base; base 694 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c const struct drm_format_info *info = drm_format_info(format->base.pixel_format); base 749 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c const struct drm_format_info *info = drm_format_info(format->base.pixel_format); base 944 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c pix_format = format->base.pixel_format; base 966 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c fb->base.id, src_x, src_y, src_w, src_h, base 967 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); base 1079 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c plane = &mdp5_plane->base; base 1092 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_plane_install_properties(plane, &plane->base); base 120 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c const struct drm_format_info *info = drm_format_info(format->base.pixel_format); base 124 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c u32 fmt = format->base.pixel_format; base 64 drivers/gpu/drm/msm/disp/mdp_format.c .base = { .pixel_format = DRM_FORMAT_ ## name }, \ base 157 drivers/gpu/drm/msm/disp/mdp_format.c pixel_formats[i] = f->base.pixel_format; base 169 drivers/gpu/drm/msm/disp/mdp_format.c if (f->base.pixel_format == format) base 170 drivers/gpu/drm/msm/disp/mdp_format.c return &f->base; base 21 drivers/gpu/drm/msm/disp/mdp_kms.h struct msm_kms_funcs base; base 27 drivers/gpu/drm/msm/disp/mdp_kms.h struct msm_kms base; base 37 drivers/gpu/drm/msm/disp/mdp_kms.h #define to_mdp_kms(x) container_of(x, struct mdp_kms, base) base 44 drivers/gpu/drm/msm/disp/mdp_kms.h msm_kms_init(&mdp_kms->base, &funcs->base); base 76 drivers/gpu/drm/msm/disp/mdp_kms.h struct msm_format base; base 86 drivers/gpu/drm/msm/disp/mdp_kms.h #define to_mdp_format(x) container_of(x, struct mdp_format, base) base 31 drivers/gpu/drm/msm/dsi/dsi_host.c static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) base 49 drivers/gpu/drm/msm/dsi/dsi_host.c ver = msm_readl(base + REG_DSI_VERSION); base 67 drivers/gpu/drm/msm/dsi/dsi_host.c ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); base 72 drivers/gpu/drm/msm/dsi/dsi_host.c *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); base 95 drivers/gpu/drm/msm/dsi/dsi_host.c struct mipi_dsi_host base; base 257 drivers/gpu/drm/msm/dsi/dsi_host.c return container_of(host, struct msm_dsi_host, base); base 1813 drivers/gpu/drm/msm/dsi/dsi_host.c msm_dsi->host = &msm_host->base; base 204 drivers/gpu/drm/msm/dsi/dsi_manager.c struct drm_connector base; base 209 drivers/gpu/drm/msm/dsi/dsi_manager.c struct drm_bridge base; base 213 drivers/gpu/drm/msm/dsi/dsi_manager.c #define to_dsi_connector(x) container_of(x, struct dsi_connector, base) base 214 drivers/gpu/drm/msm/dsi/dsi_manager.c #define to_dsi_bridge(x) container_of(x, struct dsi_bridge, base) base 278 drivers/gpu/drm/msm/dsi/dsi_manager.c drm_object_attach_property(&conn->base, base 599 drivers/gpu/drm/msm/dsi/dsi_manager.c connector = &dsi_connector->base; base 669 drivers/gpu/drm/msm/dsi/dsi_manager.c bridge = &dsi_bridge->base; base 378 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c val = dsi_phy_read(phy->base + reg); base 381 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c dsi_phy_write(phy->base + reg, val | bit_mask); base 383 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c dsi_phy_write(phy->base + reg, val & (~bit_mask)); base 583 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); base 584 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c if (IS_ERR(phy->base)) { base 77 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h void __iomem *base; base 13 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c void __iomem *base = phy->base; base 16 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL); base 95 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c void __iomem *base = phy->base; base 110 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c ret = readl_poll_timeout_atomic(base + REG_DSI_10nm_PHY_CMN_PHY_STATUS, base 120 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data); base 123 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0x00); base 126 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x00); base 129 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_GLBL_CTRL, 0x10); base 132 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_VREG_CTRL, 0x59); base 135 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG0, 0x21); base 136 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG1, 0x84); base 139 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0, base 141 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1, base 143 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2, base 145 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3, base 147 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4, base 149 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5, base 151 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6, base 153 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7, base 155 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8, base 157 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9, base 159 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10, base 161 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11, base 165 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, 0x7f); base 168 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_CTRL_0); base 172 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data); base 173 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0, 0x1F); base 176 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40); base 17 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c void __iomem *base = phy->lane_base; base 27 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx), base 29 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx), base 31 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx), base 33 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx), base 35 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx), base 37 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx), base 39 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx), base 41 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx), base 44 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx), base 46 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx), base 57 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c void __iomem *base = phy->base; base 69 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); base 71 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0x1); base 96 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0x00); base 101 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x80); base 104 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00); base 118 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0xff); base 125 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0); base 126 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0); base 12 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c void __iomem *base = phy->base; base 14 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, base 16 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, base 18 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, base 21 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, base 23 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, base 25 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, base 27 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, base 29 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, base 31 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, base 33 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9, base 36 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10, base 38 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11, base 44 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c void __iomem *base = phy->reg_base; base 47 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0); base 52 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d); base 57 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03); base 58 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03); base 59 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00); base 60 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20); base 61 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01); base 62 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00); base 63 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03); base 71 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c void __iomem *base = phy->base; base 84 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff); base 91 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i), base 93 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01); base 94 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46); base 95 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02); base 96 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0); base 97 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]); base 100 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80); base 101 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01); base 102 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46); base 103 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00); base 104 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0); base 105 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00); base 106 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00); base 110 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00); base 112 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06); base 116 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f); base 123 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0); base 12 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c void __iomem *base = phy->base; base 14 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, base 16 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, base 18 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, base 21 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3, base 23 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, base 25 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, base 27 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, base 29 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7, base 31 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8, base 33 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_9, base 36 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_10, base 38 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_11, base 44 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c void __iomem *base = phy->reg_base; base 47 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); base 51 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); base 52 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1); base 53 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0); base 54 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); base 55 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3); base 56 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9); base 57 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7); base 58 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); base 66 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c void __iomem *base = phy->base; base 76 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff); base 80 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00); base 84 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00); base 85 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); base 87 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_1, 0x6); base 90 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_0(i), 0); base 91 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0); base 92 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0); base 93 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0); base 94 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0); base 95 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0); base 96 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0); base 97 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1); base 98 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97); base 101 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0); base 102 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0); base 103 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1); base 104 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb); base 106 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f); base 117 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0); base 14 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c void __iomem *base = phy->base; base 16 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0, base 18 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1, base 20 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2, base 22 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0); base 23 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4, base 25 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5, base 27 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6, base 29 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7, base 31 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8, base 33 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_9, base 36 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_10, base 38 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_11, base 44 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c void __iomem *base = phy->reg_base; base 46 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0, 0x3); base 47 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1, 1); base 48 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2, 1); base 49 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3, 0); base 50 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4, base 56 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c void __iomem *base = phy->reg_base; base 58 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0, 0x3); base 59 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1, 0xa); base 60 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2, 0x4); base 61 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3, 0x0); base 62 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4, 0x20); base 67 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c void __iomem *base = phy->reg_base; base 71 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG, base 74 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2, 0x0); base 75 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1, 0x5a); base 76 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3, 0x10); base 77 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4, 0x1); base 78 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0, 0x1); base 80 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER, 0x1); base 82 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER, 0x0); base 85 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c status = dsi_phy_read(base + base 97 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c void __iomem *base = phy->base; base 101 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_0(i), 0x80); base 102 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_1(i), 0x45); base 103 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_CFG_2(i), 0x00); base 104 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(i), base 106 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(i), base 108 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(i), base 112 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_0, 0x40); base 113 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_1, 0x67); base 114 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_CFG_2, 0x0); base 115 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH, 0x0); base 116 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0, 0x1); base 117 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1, 0x88); base 124 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c void __iomem *base = phy->base; base 136 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LDO_CTRL, 0x04); base 139 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_0, 0xff); base 140 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_1, 0x00); base 141 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_STRENGTH_2, 0x06); base 144 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_0, 0x5f); base 145 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_1, 0x00); base 146 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_2, 0x00); base 147 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_CTRL_3, 0x10); base 155 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4, 0x0f); base 156 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_1, 0x03); base 157 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_0, 0x03); base 158 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4, 0x0); base 167 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c dsi_phy_write(phy->base + REG_DSI_28nm_8960_PHY_CTRL_0, 0x0); base 88 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct msm_dsi_pll base; base 124 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c #define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, base) base 246 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *base = pll->mmio; base 252 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1, base 254 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, base 256 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1, base 258 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1, base 260 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1, base 262 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1, base 264 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, base 271 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *base = pll->mmio; base 273 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80); base 274 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); base 275 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); base 276 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00); base 277 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); base 278 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); base 279 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, base 281 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); base 282 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00); base 283 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00); base 284 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); base 285 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08); base 286 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0); base 287 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa); base 288 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, base 290 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); base 291 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29); base 292 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f); base 297 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *base = pll->mmio; base 300 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); base 301 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1, base 303 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1, base 305 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1, base 307 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1, base 309 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40); base 310 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); base 311 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10); base 312 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS, base 486 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *base = pll_10nm->mmio; base 494 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dec = pll_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1); base 497 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c frac = pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1); base 498 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) & base 500 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & base 585 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *base = pll_10nm->phy_cmn_mmio; base 604 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2)); base 643 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister(&pll_10nm->base.clk_hw); base 677 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->base.clk_hw.init = &vco_init; base 679 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c ret = clk_hw_register(dev, &pll_10nm->base.clk_hw); base 816 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c clk_hw_unregister(&pll_10nm->base.clk_hw); base 851 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll = &pll_10nm->base; base 118 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct msm_dsi_pll base; base 150 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c #define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, base) base 180 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll_14nm->mmio; base 185 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + base 198 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + base 393 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll->mmio; base 400 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); base 403 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); base 407 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); base 410 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); base 414 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); base 417 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data); base 422 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data); base 431 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll->mmio; base 436 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data); base 439 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data); base 442 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data); base 444 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data); base 446 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data); base 449 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data); base 451 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data); base 454 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data); base 456 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data); base 459 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data); base 462 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data); base 465 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data); base 468 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data); base 471 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data); base 474 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data); base 477 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data); base 480 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data); base 483 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data); base 486 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data); base 510 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll->mmio; base 531 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data); base 534 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data); base 536 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data); base 538 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data); base 541 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data); base 544 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data); base 547 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data); base 550 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data); base 553 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data); base 555 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data); base 558 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data); base 560 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data); base 563 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data); base 629 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll_14nm->mmio; base 635 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c dec_start = pll_read(base + REG_DSI_14nm_PHY_PLL_DEC_START); base 640 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c div_frac_start = (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) base 642 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c div_frac_start |= (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) base 644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c div_frac_start |= pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) base 682 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll_14nm->phy_cmn_mmio; base 689 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; base 715 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll_14nm->phy_cmn_mmio; base 731 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); base 735 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); base 765 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll_14nm->mmio; base 771 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); base 851 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll_14nm->mmio; base 870 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en); base 872 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap); base 968 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_14nm->base.clk_hw.init = &vco_init; base 970 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c ret = clk_hw_register(dev, &pll_14nm->base.clk_hw); base 974 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c hws[num++] = &pll_14nm->base.clk_hw; base 1074 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll = &pll_14nm->base; base 70 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct msm_dsi_pll base; base 89 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c #define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base) base 113 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; base 119 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, base 121 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); base 133 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; base 144 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); base 155 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); base 158 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); base 159 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); base 184 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); base 211 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); base 212 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); base 213 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); base 214 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); base 216 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); base 217 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, base 219 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3, base 221 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); base 227 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); base 228 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); base 229 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31); base 230 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); base 231 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12); base 232 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30); base 233 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00); base 234 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60); base 235 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00); base 236 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff); base 237 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff); base 238 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20); base 257 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; base 266 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & base 271 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); base 275 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), base 281 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), base 284 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), base 286 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), base 317 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; base 332 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); base 335 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); base 338 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); base 341 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); base 345 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, base 347 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); base 362 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); base 365 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); base 368 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); base 371 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); base 374 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); base 377 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); base 392 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; base 405 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500); base 408 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); base 411 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); base 415 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); base 418 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500); base 419 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512); base 443 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; base 446 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); base 448 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); base 449 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); base 457 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c void __iomem *base = pll_28nm->mmio; base 468 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, base 470 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, base 472 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG, base 528 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_28nm->base.clk_hw.init = &vco_init; base 529 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); base 606 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll = &pll_28nm->base; base 64 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct msm_dsi_pll base; base 84 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c #define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base) base 114 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c void __iomem *base = pll_28nm->mmio; base 123 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, base 126 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); base 130 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2, base 133 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); base 137 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3, base 140 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6, base 143 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); base 145 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, base 165 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c void __iomem *base = pll_28nm->mmio; base 171 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c status = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); base 174 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c fb_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); base 176 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c temp = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07; base 180 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c ref_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); base 291 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c void __iomem *base = pll_28nm->mmio; base 306 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); base 310 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); base 313 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); base 316 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, base 341 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c void __iomem *base = pll_28nm->mmio; base 344 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10); base 346 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); base 348 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); base 357 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c void __iomem *base = pll_28nm->mmio; base 368 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, base 370 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9, base 372 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, base 440 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_28nm->base.clk_hw.init = &vco_init; base 442 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); base 507 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll = &pll_28nm->base; base 21 drivers/gpu/drm/msm/edp/edp_aux.c void __iomem *base; base 67 drivers/gpu/drm/msm/edp/edp_aux.c edp_write(aux->base + REG_EDP_AUX_DATA, reg); base 75 drivers/gpu/drm/msm/edp/edp_aux.c edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, reg); base 87 drivers/gpu/drm/msm/edp/edp_aux.c edp_write(aux->base + REG_EDP_AUX_DATA, base 93 drivers/gpu/drm/msm/edp/edp_aux.c data = edp_read(aux->base + REG_EDP_AUX_DATA); base 95 drivers/gpu/drm/msm/edp/edp_aux.c data = edp_read(aux->base + REG_EDP_AUX_DATA); base 151 drivers/gpu/drm/msm/edp/edp_aux.c edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0); base 198 drivers/gpu/drm/msm/edp/edp_aux.c aux->base = regbase; base 229 drivers/gpu/drm/msm/edp/edp_aux.c edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0); base 247 drivers/gpu/drm/msm/edp/edp_aux.c data = edp_read(aux->base + REG_EDP_AUX_CTRL); base 251 drivers/gpu/drm/msm/edp/edp_aux.c edp_write(aux->base + REG_EDP_AUX_CTRL, data); base 258 drivers/gpu/drm/msm/edp/edp_aux.c edp_write(aux->base + REG_EDP_AUX_CTRL, data); base 261 drivers/gpu/drm/msm/edp/edp_aux.c edp_write(aux->base + REG_EDP_AUX_CTRL, data); base 9 drivers/gpu/drm/msm/edp/edp_bridge.c struct drm_bridge base; base 12 drivers/gpu/drm/msm/edp/edp_bridge.c #define to_edp_bridge(x) container_of(x, struct edp_bridge, base) base 91 drivers/gpu/drm/msm/edp/edp_bridge.c bridge = &edp_bridge->base; base 11 drivers/gpu/drm/msm/edp/edp_connector.c struct drm_connector base; base 14 drivers/gpu/drm/msm/edp/edp_connector.c #define to_edp_connector(x) container_of(x, struct edp_connector, base) base 113 drivers/gpu/drm/msm/edp/edp_connector.c connector = &edp_connector->base; base 57 drivers/gpu/drm/msm/edp/edp_ctrl.c void __iomem *base; base 391 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, EDP_INTR_MASK1); base 392 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, EDP_INTR_MASK2); base 394 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, 0x0); base 395 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, 0x0); base 457 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_CONFIGURATION_CTRL, data); base 462 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_STATE_CTRL, state); base 547 drivers/gpu/drm/msm/edp/edp_ctrl.c data = edp_read(ctrl->base + REG_EDP_MAINLINK_READY); base 819 drivers/gpu/drm/msm/edp/edp_ctrl.c data = edp_read(ctrl->base + REG_EDP_MISC1_MISC0); base 839 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_MISC1_MISC0, data); base 856 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_SOFTWARE_MVID, m * m_multi); base 857 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_SOFTWARE_NVID, n * n_multi); base 866 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_MAINLINK_CTRL, EDP_MAINLINK_CTRL_RESET); base 874 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_MAINLINK_CTRL, data); base 1035 drivers/gpu/drm/msm/edp/edp_ctrl.c isr1 = edp_read(ctrl->base + REG_EDP_INTERRUPT_REG_1); base 1036 drivers/gpu/drm/msm/edp/edp_ctrl.c isr2 = edp_read(ctrl->base + REG_EDP_INTERRUPT_REG_2); base 1050 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, ack); base 1055 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, ack); base 1100 drivers/gpu/drm/msm/edp/edp_ctrl.c ctrl->base = msm_ioremap(ctrl->pdev, "edp", "eDP"); base 1101 drivers/gpu/drm/msm/edp/edp_ctrl.c if (IS_ERR(ctrl->base)) base 1102 drivers/gpu/drm/msm/edp/edp_ctrl.c return PTR_ERR(ctrl->base); base 1122 drivers/gpu/drm/msm/edp/edp_ctrl.c ctrl->aux = msm_edp_aux_init(dev, ctrl->base, &ctrl->drm_aux); base 1128 drivers/gpu/drm/msm/edp/edp_ctrl.c ctrl->phy = msm_edp_phy_init(dev, ctrl->base); base 1284 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_TOTAL_HOR_VER, base 1290 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_START_HOR_VER_FROM_SYNC, base 1302 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_HSYNC_VSYNC_WIDTH_POLARITY, data); base 1304 drivers/gpu/drm/msm/edp/edp_ctrl.c edp_write(ctrl->base + REG_EDP_ACTIVE_HOR_VER, base 12 drivers/gpu/drm/msm/edp/edp_phy.c void __iomem *base; base 21 drivers/gpu/drm/msm/edp/edp_phy.c status = edp_read(phy->base + base 41 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_CTRL, base 46 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_CTRL, 0x000); base 47 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0x3f); base 48 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_GLB_CFG, 0x1); base 50 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0xc0); base 57 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, 0x3); base 58 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, 0x64); base 59 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_GLB_MISC9, 0x6c); base 64 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, v0); base 65 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, v1); base 79 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_LN_PD_CTL(i) , data); base 84 drivers/gpu/drm/msm/edp/edp_phy.c edp_write(phy->base + REG_EDP_PHY_LN_PD_CTL(i) , data); base 95 drivers/gpu/drm/msm/edp/edp_phy.c phy->base = regbase; base 12 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c struct drm_bridge base; base 15 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c #define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base) base 287 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c bridge = &hdmi_bridge->base; base 15 drivers/gpu/drm/msm/hdmi/hdmi_connector.c struct drm_connector base; base 19 drivers/gpu/drm/msm/hdmi/hdmi_connector.c #define to_hdmi_connector(x) container_of(x, struct hdmi_connector, base) base 241 drivers/gpu/drm/msm/hdmi/hdmi_connector.c struct drm_connector *connector = &hdmi_connector->base; base 434 drivers/gpu/drm/msm/hdmi/hdmi_connector.c connector = &hdmi_connector->base; base 10 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c struct i2c_adapter base; base 15 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c #define to_hdmi_i2c_adapter(x) container_of(x, struct hdmi_i2c_adapter, base) base 245 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c i2c = &hdmi_i2c->base; base 132 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c u64 base; base 135 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c base = (64 * ref_clk) / HDMI_DEFAULT_REF_CLOCK; base 137 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c base = (1022 * ref_clk) / 100; base 139 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c base <<= digclk_divsel; base 141 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c return (base <= 2046 ? base : 2046); base 503 drivers/gpu/drm/msm/msm_drv.c priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id; base 19 drivers/gpu/drm/msm/msm_fb.c struct drm_framebuffer base; base 22 drivers/gpu/drm/msm/msm_fb.c #define to_msm_framebuffer(x) container_of(x, struct msm_framebuffer, base) base 40 drivers/gpu/drm/msm/msm_fb.c drm_framebuffer_read_refcount(fb), fb->base.id); base 63 drivers/gpu/drm/msm/msm_fb.c DBG("FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret); base 162 drivers/gpu/drm/msm/msm_fb.c fb = &msm_fb->base; base 185 drivers/gpu/drm/msm/msm_fb.c msm_fb->base.obj[i] = bos[i]; base 196 drivers/gpu/drm/msm/msm_fb.c DBG("create: FB ID: %d (%p)", fb->base.id, fb); base 22 drivers/gpu/drm/msm/msm_fbdev.c #define to_msm_fbdev(x) container_of(x, struct msm_fbdev, base) base 25 drivers/gpu/drm/msm/msm_fbdev.c struct drm_fb_helper base; base 159 drivers/gpu/drm/msm/msm_fbdev.c helper = &fbdev->base; base 91 drivers/gpu/drm/msm/msm_fence.c struct dma_fence base; base 97 drivers/gpu/drm/msm/msm_fence.c return container_of(fence, struct msm_fence, base); base 114 drivers/gpu/drm/msm/msm_fence.c return fence_completed(f->fctx, f->base.seqno); base 134 drivers/gpu/drm/msm/msm_fence.c dma_fence_init(&f->base, &msm_fence_ops, &fctx->spinlock, base 137 drivers/gpu/drm/msm/msm_fence.c return &f->base; base 53 drivers/gpu/drm/msm/msm_gem.c struct device *dev = msm_obj->base.dev->dev; base 66 drivers/gpu/drm/msm/msm_gem.c struct device *dev = msm_obj->base.dev->dev; base 871 drivers/gpu/drm/msm/msm_gem.c struct drm_gem_object *obj = &msm_obj->base; base 895 drivers/gpu/drm/msm/msm_gem.c struct drm_gem_object *obj = &msm_obj->base; base 1018 drivers/gpu/drm/msm/msm_gem.c *obj = &msm_obj->base; base 38 drivers/gpu/drm/msm/msm_gem.h struct drm_gem_object base; base 86 drivers/gpu/drm/msm/msm_gem.h #define to_msm_bo(x) container_of(x, struct msm_gem_object, base) base 95 drivers/gpu/drm/msm/msm_gem.h WARN_ON(!mutex_is_locked(&msm_obj->base.dev->struct_mutex)); base 97 drivers/gpu/drm/msm/msm_gem.h !msm_obj->base.dma_buf && !msm_obj->base.import_attach; base 55 drivers/gpu/drm/msm/msm_gem_shrinker.c count += msm_obj->base.size >> PAGE_SHIFT; base 81 drivers/gpu/drm/msm/msm_gem_shrinker.c msm_gem_purge(&msm_obj->base, OBJ_LOCK_SHRINKER); base 82 drivers/gpu/drm/msm/msm_gem_shrinker.c freed += msm_obj->base.size >> PAGE_SHIFT; base 110 drivers/gpu/drm/msm/msm_gem_shrinker.c msm_gem_vunmap(&msm_obj->base, OBJ_LOCK_SHRINKER); base 158 drivers/gpu/drm/msm/msm_gem_submit.c msm_gem_unpin_iova(&msm_obj->base, submit->aspace); base 161 drivers/gpu/drm/msm/msm_gem_submit.c ww_mutex_unlock(&msm_obj->base.resv->lock); base 184 drivers/gpu/drm/msm/msm_gem_submit.c ret = ww_mutex_lock_interruptible(&msm_obj->base.resv->lock, base 206 drivers/gpu/drm/msm/msm_gem_submit.c ret = ww_mutex_lock_slow_interruptible(&msm_obj->base.resv->lock, base 232 drivers/gpu/drm/msm/msm_gem_submit.c ret = dma_resv_reserve_shared(msm_obj->base.resv, base 241 drivers/gpu/drm/msm/msm_gem_submit.c ret = msm_gem_sync_object(&msm_obj->base, submit->ring->fctx, base 261 drivers/gpu/drm/msm/msm_gem_submit.c ret = msm_gem_get_and_pin_iova(&msm_obj->base, base 320 drivers/gpu/drm/msm/msm_gem_submit.c ptr = msm_gem_get_vaddr(&obj->base); base 351 drivers/gpu/drm/msm/msm_gem_submit.c if ((off >= (obj->base.size / 4)) || base 378 drivers/gpu/drm/msm/msm_gem_submit.c msm_gem_put_vaddr(&obj->base); base 391 drivers/gpu/drm/msm/msm_gem_submit.c drm_gem_object_put(&msm_obj->base); base 543 drivers/gpu/drm/msm/msm_gem_submit.c msm_obj->base.size)) { base 311 drivers/gpu/drm/msm/msm_gpu.c state_bo->size = obj->base.size; base 315 drivers/gpu/drm/msm/msm_gpu.c if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) { base 318 drivers/gpu/drm/msm/msm_gpu.c state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL); base 322 drivers/gpu/drm/msm/msm_gpu.c ptr = msm_gem_get_vaddr_active(&obj->base); base 329 drivers/gpu/drm/msm/msm_gpu.c memcpy(state_bo->data, ptr, obj->base.size); base 330 drivers/gpu/drm/msm/msm_gpu.c msm_gem_put_vaddr(&obj->base); base 677 drivers/gpu/drm/msm/msm_gpu.c msm_gem_move_to_inactive(&msm_obj->base); base 678 drivers/gpu/drm/msm/msm_gpu.c msm_gem_unpin_iova(&msm_obj->base, submit->aspace); base 679 drivers/gpu/drm/msm/msm_gpu.c drm_gem_object_put(&msm_obj->base); base 761 drivers/gpu/drm/msm/msm_gpu.c drm_gem_object_get(&msm_obj->base); base 762 drivers/gpu/drm/msm/msm_gpu.c msm_gem_get_and_pin_iova(&msm_obj->base, submit->aspace, &iova); base 765 drivers/gpu/drm/msm/msm_gpu.c msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence); base 767 drivers/gpu/drm/msm/msm_gpu.c msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence); base 12 drivers/gpu/drm/msm/msm_gpummu.c struct msm_mmu base; base 17 drivers/gpu/drm/msm/msm_gpummu.c #define to_msm_gpummu(x) container_of(x, struct msm_gpummu, base) base 113 drivers/gpu/drm/msm/msm_gpummu.c msm_mmu_init(&gpummu->base, dev, &funcs); base 115 drivers/gpu/drm/msm/msm_gpummu.c return &gpummu->base; base 121 drivers/gpu/drm/msm/msm_gpummu.c dma_addr_t base = to_msm_gpummu(mmu)->pt_base; base 123 drivers/gpu/drm/msm/msm_gpummu.c *pt_base = base; base 124 drivers/gpu/drm/msm/msm_gpummu.c *tran_error = base + TABLE_SIZE; /* 32-byte aligned */ base 11 drivers/gpu/drm/msm/msm_iommu.c struct msm_mmu base; base 14 drivers/gpu/drm/msm/msm_iommu.c #define to_msm_iommu(x) container_of(x, struct msm_iommu, base) base 20 drivers/gpu/drm/msm/msm_iommu.c if (iommu->base.handler) base 21 drivers/gpu/drm/msm/msm_iommu.c return iommu->base.handler(iommu->base.arg, iova, flags); base 87 drivers/gpu/drm/msm/msm_iommu.c msm_mmu_init(&iommu->base, dev, &funcs); base 90 drivers/gpu/drm/msm/msm_iommu.c return &iommu->base; base 311 drivers/gpu/drm/msm/msm_rd.c size = obj->base.size; base 325 drivers/gpu/drm/msm/msm_rd.c buf = msm_gem_get_vaddr_active(&obj->base); base 333 drivers/gpu/drm/msm/msm_rd.c msm_gem_put_vaddr(&obj->base); base 63 drivers/gpu/drm/mxsfb/mxsfb_crtc.c ctrl1 = readl(mxsfb->base + LCDC_CTRL1); base 83 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(ctrl1, mxsfb->base + LCDC_CTRL1); base 84 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(ctrl, mxsfb->base + LCDC_CTRL); base 96 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg = readl(mxsfb->base + LCDC_CTRL); base 116 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(reg, mxsfb->base + LCDC_CTRL); base 128 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET); base 131 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg = readl(mxsfb->base + LCDC_VDCTRL4); base 133 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(reg, mxsfb->base + LCDC_VDCTRL4); base 135 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); base 146 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR); base 148 drivers/gpu/drm/mxsfb/mxsfb_crtc.c readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, !(reg & CTRL_RUN), base 151 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg = readl(mxsfb->base + LCDC_VDCTRL4); base 153 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(reg, mxsfb->base + LCDC_VDCTRL4); base 219 drivers/gpu/drm/mxsfb/mxsfb_crtc.c err = mxsfb_reset_block(mxsfb->base); base 224 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET); base 234 drivers/gpu/drm/mxsfb/mxsfb_crtc.c mxsfb->base + mxsfb->devdata->transfer_count); base 258 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0); base 263 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1); base 269 drivers/gpu/drm/mxsfb/mxsfb_crtc.c mxsfb->base + LCDC_VDCTRL2); base 273 drivers/gpu/drm/mxsfb/mxsfb_crtc.c mxsfb->base + LCDC_VDCTRL3); base 276 drivers/gpu/drm/mxsfb/mxsfb_crtc.c mxsfb->base + LCDC_VDCTRL4); base 289 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(paddr, mxsfb->base + mxsfb->devdata->cur_buf); base 290 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); base 326 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); base 148 drivers/gpu/drm/mxsfb/mxsfb_drv.c writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); base 149 drivers/gpu/drm/mxsfb/mxsfb_drv.c writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET); base 161 drivers/gpu/drm/mxsfb/mxsfb_drv.c writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); base 162 drivers/gpu/drm/mxsfb/mxsfb_drv.c writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); base 190 drivers/gpu/drm/mxsfb/mxsfb_drv.c mxsfb->base = devm_ioremap_resource(drm->dev, res); base 191 drivers/gpu/drm/mxsfb/mxsfb_drv.c if (IS_ERR(mxsfb->base)) base 192 drivers/gpu/drm/mxsfb/mxsfb_drv.c return PTR_ERR(mxsfb->base); base 304 drivers/gpu/drm/mxsfb/mxsfb_drv.c reg = readl(mxsfb->base + LCDC_CTRL1); base 309 drivers/gpu/drm/mxsfb/mxsfb_drv.c writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); base 24 drivers/gpu/drm/mxsfb/mxsfb_drv.h void __iomem *base; /* registers */ base 765 drivers/gpu/drm/nouveau/dispnv04/crtc.c struct drm_device *dev = nv_crtc->base.dev; base 806 drivers/gpu/drm/nouveau/dispnv04/crtc.c if (!nv_crtc->base.primary->fb) { base 1313 drivers/gpu/drm/nouveau/dispnv04/crtc.c drm_crtc_init_with_planes(dev, &nv_crtc->base, base 1316 drivers/gpu/drm/nouveau/dispnv04/crtc.c drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); base 1317 drivers/gpu/drm/nouveau/dispnv04/crtc.c drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); base 11 drivers/gpu/drm/nouveau/dispnv04/cursor.c nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true); base 17 drivers/gpu/drm/nouveau/dispnv04/cursor.c nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false); base 24 drivers/gpu/drm/nouveau/dispnv04/cursor.c NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index, base 40 drivers/gpu/drm/nouveau/dispnv04/cursor.c struct drm_device *dev = nv_crtc->base.dev; base 43 drivers/gpu/drm/nouveau/dispnv04/cursor.c struct drm_crtc *crtc = &nv_crtc->base; base 421 drivers/gpu/drm/nouveau/dispnv04/dac.c nouveau_encoder_connector_get(nv_encoder)->base.name, base 292 drivers/gpu/drm/nouveau/dispnv04/dfp.c struct drm_connector *connector = &nv_connector->base; base 481 drivers/gpu/drm/nouveau/dispnv04/dfp.c nouveau_encoder_connector_get(nv_encoder)->base.name, base 93 drivers/gpu/drm/nouveau/dispnv04/disp.c nv_crtc->save(&nv_crtc->base); base 96 drivers/gpu/drm/nouveau/dispnv04/disp.c list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.base.head) base 97 drivers/gpu/drm/nouveau/dispnv04/disp.c encoder->enc_save(&encoder->base.base); base 171 drivers/gpu/drm/nouveau/dispnv04/disp.c list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.base.head) base 172 drivers/gpu/drm/nouveau/dispnv04/disp.c encoder->enc_restore(&encoder->base.base); base 174 drivers/gpu/drm/nouveau/dispnv04/disp.c list_for_each_entry(nv_crtc, &dev->mode_config.crtc_list, base.head) base 175 drivers/gpu/drm/nouveau/dispnv04/disp.c nv_crtc->restore(&nv_crtc->base); base 274 drivers/gpu/drm/nouveau/dispnv04/disp.c list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) base 275 drivers/gpu/drm/nouveau/dispnv04/disp.c crtc->save(&crtc->base); base 277 drivers/gpu/drm/nouveau/dispnv04/disp.c list_for_each_entry(nv_encoder, &dev->mode_config.encoder_list, base.base.head) base 278 drivers/gpu/drm/nouveau/dispnv04/disp.c nv_encoder->enc_save(&nv_encoder->base.base); base 38 drivers/gpu/drm/nouveau/dispnv04/overlay.c struct drm_plane base; base 122 drivers/gpu/drm/nouveau/dispnv04/overlay.c container_of(plane, struct nouveau_plane, base); base 195 drivers/gpu/drm/nouveau/dispnv04/overlay.c container_of(plane, struct nouveau_plane, base); base 217 drivers/gpu/drm/nouveau/dispnv04/overlay.c struct nvif_object *dev = &nouveau_drm(plane->base.dev)->client.device.object; base 247 drivers/gpu/drm/nouveau/dispnv04/overlay.c container_of(plane, struct nouveau_plane, base); base 259 drivers/gpu/drm/nouveau/dispnv04/overlay.c else if (property == nv_plane->base.color_encoding_property) base 297 drivers/gpu/drm/nouveau/dispnv04/overlay.c ret = drm_plane_init(device, &plane->base, 3 /* both crtc's */, base 322 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_object_attach_property(&plane->base.base, base 326 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_object_attach_property(&plane->base.base, base 330 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_object_attach_property(&plane->base.base, base 334 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_object_attach_property(&plane->base.base, base 338 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_object_attach_property(&plane->base.base, base 342 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_plane_create_color_properties(&plane->base, base 351 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_plane_force_disable(&plane->base); base 354 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_plane_cleanup(&plane->base); base 370 drivers/gpu/drm/nouveau/dispnv04/overlay.c container_of(plane, struct nouveau_plane, base); base 444 drivers/gpu/drm/nouveau/dispnv04/overlay.c container_of(plane, struct nouveau_plane, base); base 475 drivers/gpu/drm/nouveau/dispnv04/overlay.c ret = drm_plane_init(device, &plane->base, 1 /* single crtc */, base 491 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_object_attach_property(&plane->base.base, base 495 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_object_attach_property(&plane->base.base, base 498 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_plane_force_disable(&plane->base); base 501 drivers/gpu/drm/nouveau/dispnv04/overlay.c drm_plane_cleanup(&plane->base); base 356 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c static void tv_save_filter(struct drm_device *dev, uint32_t base, base 360 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c uint32_t offsets[] = { base, base + 0x1c, base + 0x40, base + 0x5c }; base 368 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c static void tv_load_filter(struct drm_device *dev, uint32_t base, base 372 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c uint32_t offsets[] = { base, base + 0x1c, base + 0x40, base + 0x5c }; base 175 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c nouveau_encoder_connector_get(nv_encoder)->base.name, base 150 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c struct dcb_output *dcb = tv_enc->base.dcb; base 185 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c drm_object_property_set_value(&connector->base, base 602 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c nouveau_encoder_connector_get(nv_encoder)->base.name, base 661 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c drm_object_attach_property(&connector->base, base 664 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c drm_object_attach_property(&connector->base, base 667 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c drm_object_attach_property(&connector->base, base 670 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c drm_object_attach_property(&connector->base, base 673 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c drm_object_attach_property(&connector->base, base 676 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c drm_object_attach_property(&connector->base, base 679 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c drm_object_attach_property(&connector->base, base 809 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c encoder = to_drm_encoder(&tv_enc->base); base 811 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->base.dcb = entry; base 812 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->base.or = ffs(entry->or) - 1; base 819 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->base.enc_save = nv17_tv_save; base 820 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->base.enc_restore = nv17_tv_restore; base 71 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h struct nouveau_encoder base; base 86 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h struct nv17_tv_encoder, base) base 94 drivers/gpu/drm/nouveau/dispnv50/atom.h } base; base 133 drivers/gpu/drm/nouveau/dispnv50/atom.h bool base:1; base 183 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.cpp = 0; base 201 drivers/gpu/drm/nouveau/dispnv50/base507c.c if ((asyh->base.cpp != 1) ^ (fb->format->cpp[0] != 1)) base 205 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.depth = fb->format->depth; base 206 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.cpp = fb->format->cpp[0]; base 207 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.x = asyw->state.src.x1 >> 16; base 208 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.y = asyw->state.src.y1 >> 16; base 209 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.w = asyw->state.fb->width; base 210 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.h = asyw->state.fb->height; base 216 drivers/gpu/drm/nouveau/dispnv50/base507c.c if (!asyh->base.depth) base 217 drivers/gpu/drm/nouveau/dispnv50/base507c.c asyh->base.depth = asyh->base.cpp * 8; base 283 drivers/gpu/drm/nouveau/dispnv50/base507c.c ret = nvif_notify_init(&wndw->wndw.base.user, wndw->notify.func, base 34 drivers/gpu/drm/nouveau/dispnv50/curs507a.c nvif_wr32(&wndw->wimm.base.user, 0x0080, 0x00000000); base 40 drivers/gpu/drm/nouveau/dispnv50/curs507a.c nvif_wr32(&wndw->wimm.base.user, 0x0084, asyw->point.y << 16 | base 127 drivers/gpu/drm/nouveau/dispnv50/curs507a.c sizeof(args), &wndw->wimm.base.user); base 133 drivers/gpu/drm/nouveau/dispnv50/curs507a.c nvif_object_map(&wndw->wimm.base.user, NULL, 0); base 28 drivers/gpu/drm/nouveau/dispnv50/cursc37a.c nvif_wr32(&wndw->wimm.base.user, 0x0200, 0x00000001); base 34 drivers/gpu/drm/nouveau/dispnv50/cursc37a.c nvif_wr32(&wndw->wimm.base.user, 0x0208, asyw->point.y << 16 | base 128 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_chan_destroy(&dmac->base); base 166 drivers/gpu/drm/nouveau/dispnv50/disp.c &dmac->base); base 173 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, base 184 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, base 208 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nvif_device *device = dmac->base.device; base 221 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nvif_device *device = dmac->base.device; base 222 drivers/gpu/drm/nouveau/dispnv50/disp.c u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; base 229 drivers/gpu/drm/nouveau/dispnv50/disp.c nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); base 231 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!nvif_rd32(&dmac->base.user, 0x0004)) base 252 drivers/gpu/drm/nouveau/dispnv50/disp.c nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); base 262 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); base 264 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp_mthd_v1 base; base 266 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.version = 1, base 267 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.method = NV50_DISP_MTHD_V1_RELEASE, base 268 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hasht = nv_encoder->dcb->hasht, base 269 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hashm = nv_encoder->dcb->hashm, base 280 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); base 283 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp_mthd_v1 base; base 286 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.version = 1, base 287 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.method = NV50_DISP_MTHD_V1_ACQUIRE, base 288 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hasht = nv_encoder->dcb->hasht, base 289 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hashm = nv_encoder->dcb->hashm, base 391 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); base 408 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp_mthd_v1 base; base 411 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.version = 1, base 412 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, base 413 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hasht = nv_encoder->dcb->hasht, base 414 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hashm = nv_encoder->dcb->hashm, base 488 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp_mthd_v1 base; base 491 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.version = 1, base 492 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, base 493 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hasht = nv_encoder->dcb->hasht, base 494 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | base 512 drivers/gpu/drm/nouveau/dispnv50/disp.c } base; base 513 drivers/gpu/drm/nouveau/dispnv50/disp.c u8 data[sizeof(nv_connector->base.eld)]; base 515 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.mthd.version = 1, base 516 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, base 517 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.mthd.hasht = nv_encoder->dcb->hasht, base 518 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | base 526 drivers/gpu/drm/nouveau/dispnv50/disp.c memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); base 529 drivers/gpu/drm/nouveau/dispnv50/disp.c sizeof(args.base) + drm_eld_size(args.data)); base 541 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp_mthd_v1 base; base 544 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.version = 1, base 545 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, base 546 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hasht = nv_encoder->dcb->hasht, base 547 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | base 562 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp_mthd_v1 base; base 566 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.version = 1, base 567 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, base 568 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hasht = nv_encoder->dcb->hasht, base 569 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | base 588 drivers/gpu/drm/nouveau/dispnv50/disp.c hdmi = &nv_connector->base.display_info.hdmi; base 591 drivers/gpu/drm/nouveau/dispnv50/disp.c &nv_connector->base, mode); base 599 drivers/gpu/drm/nouveau/dispnv50/disp.c &nv_connector->base, mode); base 624 drivers/gpu/drm/nouveau/dispnv50/disp.c size = sizeof(args.base) base 701 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->outp->base.base.name, i, payload->vcpi, base 740 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp_mthd_v1 base; base 743 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.version = 1, base 744 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, base 745 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hasht = mstm->outp->dcb->hasht, base 746 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | base 747 drivers/gpu/drm/nouveau/dispnv50/disp.c (0x0100 << msto->head->base.index), base 764 drivers/gpu/drm/nouveau/dispnv50/disp.c msto->encoder.name, msto->head->base.base.name, base 837 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state); base 872 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->outp->update(mstm->outp, head->base.index, armh, proto, base 889 drivers/gpu/drm/nouveau/dispnv50/disp.c mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); base 946 drivers/gpu/drm/nouveau/dispnv50/disp.c return &mstc->mstm->msto[head->base.index]->encoder; base 1073 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_device *dev = mstm->outp->base.base.dev; base 1098 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); base 1099 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); base 1108 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); base 1112 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); base 1117 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { base 1132 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); base 1136 drivers/gpu/drm/nouveau/dispnv50/disp.c NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); base 1139 drivers/gpu/drm/nouveau/dispnv50/disp.c drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { base 1239 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp_mthd_v1 base; base 1242 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.version = 1, base 1243 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, base 1244 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hasht = outp->dcb->hasht, base 1245 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hashm = outp->dcb->hashm, base 1248 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); base 1368 drivers/gpu/drm/nouveau/dispnv50/disp.c struct drm_device *dev = outp->base.base.dev; base 1394 drivers/gpu/drm/nouveau/dispnv50/disp.c ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name, base 1410 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); base 1449 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); base 1459 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); base 1462 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp_mthd_v1 base; base 1465 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.version = 1, base 1466 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, base 1467 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hasht = nv_encoder->dcb->hasht, base 1468 drivers/gpu/drm/nouveau/dispnv50/disp.c .base.hashm = nv_encoder->dcb->hashm, base 1500 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_hdmi_enable(&nv_encoder->base.base, mode); base 1630 drivers/gpu/drm/nouveau/dispnv50/disp.c nv_connector->base.base.id, base 1677 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); base 1796 drivers/gpu/drm/nouveau/dispnv50/disp.c disp->core->chan.base.device)) base 57 drivers/gpu/drm/nouveau/dispnv50/disp.h struct nv50_chan base; base 59 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->set.base ) head->func->base (head, asyh); base 87 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->base.depth > asyh->or.bpc * 3) base 214 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_disp *disp = nv50_disp(head->base.base.dev); base 318 drivers/gpu/drm/nouveau/dispnv50/head.c if (armh->base.depth != asyh->base.depth) base 355 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.base = armh->base.cpp != asyh->base.cpp; base 361 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->base.cpp = 0; base 431 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->base = armh->base; base 482 drivers/gpu/drm/nouveau/dispnv50/head.c struct nv50_wndw *base, *ovly, *curs; base 491 drivers/gpu/drm/nouveau/dispnv50/head.c head->base.index = index; base 494 drivers/gpu/drm/nouveau/dispnv50/head.c ret = nv50_base_new(drm, head->base.index, &base); base 495 drivers/gpu/drm/nouveau/dispnv50/head.c ret = nv50_ovly_new(drm, head->base.index, &ovly); base 498 drivers/gpu/drm/nouveau/dispnv50/head.c head->base.index * 2 + 0, &base); base 500 drivers/gpu/drm/nouveau/dispnv50/head.c head->base.index * 2 + 1, &ovly); base 503 drivers/gpu/drm/nouveau/dispnv50/head.c ret = nv50_curs_new(drm, head->base.index, &curs); base 509 drivers/gpu/drm/nouveau/dispnv50/head.c crtc = &head->base.base; base 510 drivers/gpu/drm/nouveau/dispnv50/head.c drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane, base 511 drivers/gpu/drm/nouveau/dispnv50/head.c &nv50_head_func, "head-%d", head->base.index); base 3 drivers/gpu/drm/nouveau/dispnv50/head.h #define nv50_head(c) container_of((c), struct nv50_head, base.base) base 12 drivers/gpu/drm/nouveau/dispnv50/head.h struct nouveau_crtc base; base 36 drivers/gpu/drm/nouveau/dispnv50/head.h void (*base)(struct nv50_head *, struct nv50_head_atom *); base 28 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 31 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1); base 41 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 44 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1); base 55 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 73 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x0904 + head->base.index * 0x400, 1); base 82 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 86 drivers/gpu/drm/nouveau/dispnv50/head507d.c if (asyh->base.cpp) { base 87 drivers/gpu/drm/nouveau/dispnv50/head507d.c switch (asyh->base.cpp) { base 100 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x0900 + head->base.index * 0x400, 1); base 109 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 112 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x0880 + head->base.index * 0x400, 1); base 121 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 124 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x0880 + head->base.index * 0x400, 2); base 161 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 164 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x0874 + head->base.index * 0x400, 1); base 173 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 176 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x0860 + head->base.index * 0x400, 1); base 178 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x0868 + head->base.index * 0x400, 4); base 187 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1); base 203 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_disp *disp = nv50_disp(head->base.base.dev); base 204 drivers/gpu/drm/nouveau/dispnv50/head507d.c if ((asyh->core.visible = (asyh->base.cpp != 0))) { base 205 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.x = asyh->base.x; base 206 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.y = asyh->base.y; base 207 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.w = asyh->base.w; base 208 drivers/gpu/drm/nouveau/dispnv50/head507d.c asyh->core.h = asyh->base.h; base 235 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 238 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1); base 247 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 250 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); base 277 drivers/gpu/drm/nouveau/dispnv50/head507d.c if (asyh->base.cpp == 1) base 288 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 292 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2); base 295 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7); base 303 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x082c + (head->base.index * 0x400), 1); base 312 drivers/gpu/drm/nouveau/dispnv50/head507d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 315 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1); base 317 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1); base 319 drivers/gpu/drm/nouveau/dispnv50/head507d.c evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2); base 340 drivers/gpu/drm/nouveau/dispnv50/head507d.c .base = head507d_base, base 28 drivers/gpu/drm/nouveau/dispnv50/head827d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 31 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_mthd(push, 0x0880 + head->base.index * 0x400, 1); base 33 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_mthd(push, 0x089c + head->base.index * 0x400, 1); base 42 drivers/gpu/drm/nouveau/dispnv50/head827d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 45 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_mthd(push, 0x0880 + head->base.index * 0x400, 2); base 49 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_mthd(push, 0x089c + head->base.index * 0x400, 1); base 58 drivers/gpu/drm/nouveau/dispnv50/head827d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 61 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_mthd(push, 0x0860 + head->base.index * 0x400, 1); base 63 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_mthd(push, 0x0868 + head->base.index * 0x400, 4); base 71 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1); base 80 drivers/gpu/drm/nouveau/dispnv50/head827d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 83 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1); base 85 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_mthd(push, 0x085c + (head->base.index * 0x400), 1); base 94 drivers/gpu/drm/nouveau/dispnv50/head827d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 97 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); base 100 drivers/gpu/drm/nouveau/dispnv50/head827d.c evo_mthd(push, 0x085c + (head->base.index * 0x400), 1); base 120 drivers/gpu/drm/nouveau/dispnv50/head827d.c .base = head507d_base, base 28 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 31 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0404 + (head->base.index * 0x300), 2); base 35 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_data(push, 0x31ec6000 | head->base.index << 25 | base 44 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 47 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1); base 57 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 60 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1); base 71 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 90 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1); base 99 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 103 drivers/gpu/drm/nouveau/dispnv50/head907d.c if (asyh->base.cpp) { base 104 drivers/gpu/drm/nouveau/dispnv50/head907d.c switch (asyh->base.cpp) { base 117 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1); base 126 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 129 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0480 + head->base.index * 0x300, 1); base 131 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x048c + head->base.index * 0x300, 1); base 140 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 143 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0480 + head->base.index * 0x300, 2); base 147 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x048c + head->base.index * 0x300, 1); base 156 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 159 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0474 + head->base.index * 0x300, 1); base 168 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 171 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0460 + head->base.index * 0x300, 1); base 173 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0468 + head->base.index * 0x300, 4); base 181 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1); base 190 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 193 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0448 + (head->base.index * 0x300), 1); base 195 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x045c + (head->base.index * 0x300), 1); base 204 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 207 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0448 + (head->base.index * 0x300), 2); base 210 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x045c + (head->base.index * 0x300), 1); base 243 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 247 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6); base 254 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x042c + (head->base.index * 0x300), 2); base 257 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3); base 268 drivers/gpu/drm/nouveau/dispnv50/head907d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 271 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1); base 273 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1); base 275 drivers/gpu/drm/nouveau/dispnv50/head907d.c evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3); base 297 drivers/gpu/drm/nouveau/dispnv50/head907d.c .base = head907d_base, base 28 drivers/gpu/drm/nouveau/dispnv50/head917d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 31 drivers/gpu/drm/nouveau/dispnv50/head917d.c evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1); base 42 drivers/gpu/drm/nouveau/dispnv50/head917d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 46 drivers/gpu/drm/nouveau/dispnv50/head917d.c if (asyh->base.cpp) { base 47 drivers/gpu/drm/nouveau/dispnv50/head917d.c switch (asyh->base.cpp) { base 60 drivers/gpu/drm/nouveau/dispnv50/head917d.c evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1); base 95 drivers/gpu/drm/nouveau/dispnv50/head917d.c .base = head917d_base, base 29 drivers/gpu/drm/nouveau/dispnv50/headc37d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 45 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x2004 + (head->base.index * 0x400), 1); base 57 drivers/gpu/drm/nouveau/dispnv50/headc37d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 60 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x2000 + (head->base.index * 0x400), 1); base 71 drivers/gpu/drm/nouveau/dispnv50/headc37d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 74 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x2018 + (head->base.index * 0x0400), 1); base 85 drivers/gpu/drm/nouveau/dispnv50/headc37d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 88 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x209c + head->base.index * 0x400, 1); base 90 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x2088 + head->base.index * 0x400, 1); base 99 drivers/gpu/drm/nouveau/dispnv50/headc37d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 102 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x209c + head->base.index * 0x400, 2); base 107 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x2088 + head->base.index * 0x400, 1); base 109 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x2090 + head->base.index * 0x400, 1); base 126 drivers/gpu/drm/nouveau/dispnv50/headc37d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 129 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x20ac + (head->base.index * 0x400), 1); base 138 drivers/gpu/drm/nouveau/dispnv50/headc37d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 141 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x20a4 + (head->base.index * 0x400), 3); base 164 drivers/gpu/drm/nouveau/dispnv50/headc37d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 168 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x2064 + (head->base.index * 0x400), 5); base 174 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x200c + (head->base.index * 0x400), 1); base 176 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x2028 + (head->base.index * 0x400), 1); base 179 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x2030 + (head->base.index * 0x400), 1); base 188 drivers/gpu/drm/nouveau/dispnv50/headc37d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 191 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x204c + (head->base.index * 0x400), 1); base 193 drivers/gpu/drm/nouveau/dispnv50/headc37d.c evo_mthd(push, 0x2058 + (head->base.index * 0x400), 1); base 29 drivers/gpu/drm/nouveau/dispnv50/headc57d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 45 drivers/gpu/drm/nouveau/dispnv50/headc57d.c evo_mthd(push, 0x2004 + (head->base.index * 0x400), 1); base 57 drivers/gpu/drm/nouveau/dispnv50/headc57d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 60 drivers/gpu/drm/nouveau/dispnv50/headc57d.c evo_mthd(push, 0x2000 + (head->base.index * 0x400), 1); base 75 drivers/gpu/drm/nouveau/dispnv50/headc57d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 78 drivers/gpu/drm/nouveau/dispnv50/headc57d.c evo_mthd(push, 0x2288 + (head->base.index * 0x400), 1); base 87 drivers/gpu/drm/nouveau/dispnv50/headc57d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 90 drivers/gpu/drm/nouveau/dispnv50/headc57d.c evo_mthd(push, 0x2280 + (head->base.index * 0x400), 4); base 170 drivers/gpu/drm/nouveau/dispnv50/headc57d.c struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; base 174 drivers/gpu/drm/nouveau/dispnv50/headc57d.c evo_mthd(push, 0x2064 + (head->base.index * 0x400), 5); base 180 drivers/gpu/drm/nouveau/dispnv50/headc57d.c evo_mthd(push, 0x200c + (head->base.index * 0x400), 1); base 182 drivers/gpu/drm/nouveau/dispnv50/headc57d.c evo_mthd(push, 0x2028 + (head->base.index * 0x400), 1); base 185 drivers/gpu/drm/nouveau/dispnv50/headc57d.c evo_mthd(push, 0x2030 + (head->base.index * 0x400), 1); base 37 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c sizeof(args), &wndw->wimm.base.user); base 43 drivers/gpu/drm/nouveau/dispnv50/oimm507b.c nvif_object_map(&wndw->wimm.base.user, NULL, 0); base 195 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c ret = nvif_notify_init(&wndw->wndw.base.user, wndw->notify.func, false, base 44 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nouveau_drm *drm = nouveau_drm(fb->base.dev); base 49 drivers/gpu/drm/nouveau/dispnv50/wndw.c struct nv_dma_v0 base; base 56 drivers/gpu/drm/nouveau/dispnv50/wndw.c u32 argc = sizeof(args.base); base 68 drivers/gpu/drm/nouveau/dispnv50/wndw.c args.base.target = NV_DMA_V0_TARGET_VRAM; base 69 drivers/gpu/drm/nouveau/dispnv50/wndw.c args.base.access = NV_DMA_V0_ACCESS_RDWR; base 70 drivers/gpu/drm/nouveau/dispnv50/wndw.c args.base.start = 0; base 71 drivers/gpu/drm/nouveau/dispnv50/wndw.c args.base.limit = drm->client.device.info.ram_user - 1; base 108 drivers/gpu/drm/nouveau/dispnv50/wndw.c wndw->wndw.base.device); base 244 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->image.w = fb->base.width; base 245 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->image.h = fb->base.height; base 261 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->image.blocks[0] = fb->base.pitches[0] / 64; base 267 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->image.pitch[0] = fb->base.pitches[0]; base 506 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->state.fence = dma_resv_get_excl_rcu(fb->nvbo->bo.base.resv); base 648 drivers/gpu/drm/nouveau/dispnv50/wndw.c wndw->ctxdma.parent = &wndw->wndw.base.user; base 277 drivers/gpu/drm/nouveau/include/nvkm/core/device.h struct nvkm_sclass base; base 31 drivers/gpu/drm/nouveau/include/nvkm/core/engine.h } base; base 20 drivers/gpu/drm/nouveau/include/nvkm/core/oclass.h struct nvkm_sclass base; base 4 drivers/gpu/drm/nouveau/include/nvkm/core/oproxy.h #define nvkm_oproxy(p) container_of((p), struct nvkm_oproxy, base) base 9 drivers/gpu/drm/nouveau/include/nvkm/core/oproxy.h struct nvkm_object base; base 5 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h u32 base; base 14 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h u32 base; base 66 drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h struct nvkm_cstate base; base 21 drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h u64 base; base 14 drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h u32 base; base 19 drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h u32 base; base 58 drivers/gpu/drm/nouveau/nouveau_abi16.c if (nvif_device_init(&cli->base.object, 0, NV_DEVICE, base 142 drivers/gpu/drm/nouveau/nouveau_abi16.c drm_gem_object_put_unlocked(&chan->ntfy->bo.base); base 342 drivers/gpu/drm/nouveau/nouveau_abi16.c ret = drm_gem_handle_create(file_priv, &chan->ntfy->bo.base, base 561 drivers/gpu/drm/nouveau/nouveau_abi16.c args.start += drm->agp.base + chan->ntfy->bo.offset; base 562 drivers/gpu/drm/nouveau/nouveau_abi16.c args.limit += drm->agp.base + chan->ntfy->bo.offset; base 69 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); base 81 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); base 103 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(encoder->base.base.dev); base 119 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); base 134 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); base 155 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); base 173 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); base 202 drivers/gpu/drm/nouveau/nouveau_backlight.c struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); base 146 drivers/gpu/drm/nouveau/nouveau_bo.c if (bo->base.dev) base 147 drivers/gpu/drm/nouveau/nouveau_bo.c drm_gem_object_release(&bo->base); base 1151 drivers/gpu/drm/nouveau/nouveau_bo.c &fence->base, base 1356 drivers/gpu/drm/nouveau/nouveau_bo.c struct dma_fence *fence = dma_resv_get_excl(bo->base.resv); base 1433 drivers/gpu/drm/nouveau/nouveau_bo.c return drm_vma_node_verify_access(&nvbo->bo.base.vma_node, base 1448 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.base = 0; base 1460 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.base = drm->agp.base; base 1470 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.base = device->func->resource_addr(device, 1); base 1506 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.base = 0; base 1687 drivers/gpu/drm/nouveau/nouveau_bo.c struct dma_resv *resv = nvbo->bo.base.resv; base 1690 drivers/gpu/drm/nouveau/nouveau_bo.c dma_resv_add_excl_fence(resv, &fence->base); base 1692 drivers/gpu/drm/nouveau/nouveau_bo.c dma_resv_add_shared_fence(resv, &fence->base); base 77 drivers/gpu/drm/nouveau/nouveau_chan.c chan->chid, nvxx_client(&cli->base)->name); base 93 drivers/gpu/drm/nouveau/nouveau_chan.c super = cli->base.super; base 94 drivers/gpu/drm/nouveau/nouveau_chan.c cli->base.super = true; base 117 drivers/gpu/drm/nouveau/nouveau_chan.c cli->base.super = super; base 204 drivers/gpu/drm/nouveau/nouveau_chan.c args.start = chan->drm->agp.base; base 205 drivers/gpu/drm/nouveau/nouveau_chan.c args.limit = chan->drm->agp.base + base 405 drivers/gpu/drm/nouveau/nouveau_chan.c args.start = chan->drm->agp.base; base 406 drivers/gpu/drm/nouveau/nouveau_chan.c args.limit = chan->drm->agp.base + base 483 drivers/gpu/drm/nouveau/nouveau_chan.c super = cli->base.super; base 484 drivers/gpu/drm/nouveau/nouveau_chan.c cli->base.super = true; base 507 drivers/gpu/drm/nouveau/nouveau_chan.c cli->base.super = super; base 298 drivers/gpu/drm/nouveau/nouveau_connector.c drm_object_attach_property(&connector->base, dev->mode_config. base 307 drivers/gpu/drm/nouveau/nouveau_connector.c drm_object_attach_property(&connector->base, base 310 drivers/gpu/drm/nouveau/nouveau_connector.c drm_object_attach_property(&connector->base, base 312 drivers/gpu/drm/nouveau/nouveau_connector.c drm_object_attach_property(&connector->base, base 318 drivers/gpu/drm/nouveau/nouveau_connector.c drm_object_attach_property(&connector->base, base 322 drivers/gpu/drm/nouveau/nouveau_connector.c drm_object_attach_property(&connector->base, base 335 drivers/gpu/drm/nouveau/nouveau_connector.c drm_object_attach_property(&connector->base, dev->mode_config. base 348 drivers/gpu/drm/nouveau/nouveau_connector.c drm_object_attach_property(&connector->base, base 353 drivers/gpu/drm/nouveau/nouveau_connector.c drm_object_attach_property(&connector->base, base 533 drivers/gpu/drm/nouveau/nouveau_connector.c drm_object_property_set_value(&connector->base, base 772 drivers/gpu/drm/nouveau/nouveau_connector.c ret = connector->funcs->atomic_set_property(&nv_connector->base, base 998 drivers/gpu/drm/nouveau/nouveau_connector.c info = &nv_connector->base.display_info; base 1142 drivers/gpu/drm/nouveau/nouveau_connector.c struct drm_connector *connector = &nv_connector->base; base 1203 drivers/gpu/drm/nouveau/nouveau_connector.c nv_encoder = find_encoder(&nv_connector->base, DCB_OUTPUT_DP); base 1283 drivers/gpu/drm/nouveau/nouveau_connector.c connector = &nv_connector->base; base 103 drivers/gpu/drm/nouveau/nouveau_connector.h struct drm_connector base; base 132 drivers/gpu/drm/nouveau/nouveau_connector.h return container_of(con, struct nouveau_connector, base); base 148 drivers/gpu/drm/nouveau/nouveau_connector.h encoder = &nv_encoder->base.base; base 159 drivers/gpu/drm/nouveau/nouveau_connector.h struct drm_device *dev = nv_crtc->base.dev; base 35 drivers/gpu/drm/nouveau/nouveau_crtc.h struct drm_crtc base; base 74 drivers/gpu/drm/nouveau/nouveau_crtc.h return crtc ? container_of(crtc, struct nouveau_crtc, base) : NULL; base 79 drivers/gpu/drm/nouveau/nouveau_crtc.h return &crtc->base; base 52 drivers/gpu/drm/nouveau/nouveau_display.c drm_crtc_handle_vblank(&nv_crtc->base); base 105 drivers/gpu/drm/nouveau/nouveau_display.c struct nv04_disp_mthd_v0 base; base 108 drivers/gpu/drm/nouveau/nouveau_display.c .base.method = NV04_DISP_SCANOUTPOS, base 109 drivers/gpu/drm/nouveau/nouveau_display.c .base.head = nouveau_crtc(crtc)->index, base 206 drivers/gpu/drm/nouveau/nouveau_display.c drm_gem_object_put_unlocked(&fb->nvbo->bo.base); base 219 drivers/gpu/drm/nouveau/nouveau_display.c return drm_gem_handle_create(file_priv, &fb->nvbo->bo.base, handle); base 260 drivers/gpu/drm/nouveau/nouveau_display.c drm_helper_mode_fill_fb_struct(dev, &fb->base, mode_cmd); base 263 drivers/gpu/drm/nouveau/nouveau_display.c ret = drm_framebuffer_init(dev, &fb->base, &nouveau_framebuffer_funcs); base 286 drivers/gpu/drm/nouveau/nouveau_display.c return &fb->base; base 665 drivers/gpu/drm/nouveau/nouveau_display.c ret = drm_gem_handle_create(file_priv, &bo->bo.base, &args->handle); base 666 drivers/gpu/drm/nouveau/nouveau_display.c drm_gem_object_put_unlocked(&bo->bo.base); base 680 drivers/gpu/drm/nouveau/nouveau_display.c *poffset = drm_vma_node_offset_addr(&bo->bo.base.vma_node); base 12 drivers/gpu/drm/nouveau/nouveau_display.h struct drm_framebuffer base; base 25 drivers/gpu/drm/nouveau/nouveau_display.h return container_of(fb, struct nouveau_framebuffer, base); base 61 drivers/gpu/drm/nouveau/nouveau_dp.c struct drm_device *dev = nv_encoder->base.base.dev; base 184 drivers/gpu/drm/nouveau/nouveau_drm.c nvif_client_fini(&cli->base); base 229 drivers/gpu/drm/nouveau/nouveau_drm.c cli->name, device, &cli->base); base 232 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nvif_client_init(&drm->master.base, cli->name, device, base 233 drivers/gpu/drm/nouveau/nouveau_drm.c &cli->base); base 241 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE, base 519 drivers/gpu/drm/nouveau/nouveau_drm.c nvxx_client(&drm->client.base)->debug = base 706 drivers/gpu/drm/nouveau/nouveau_drm.c aper->ranges[0].base = pci_resource_start(pdev, 1); base 711 drivers/gpu/drm/nouveau/nouveau_drm.c aper->ranges[aper->count].base = pci_resource_start(pdev, 2); base 717 drivers/gpu/drm/nouveau/nouveau_drm.c aper->ranges[aper->count].base = pci_resource_start(pdev, 3); base 785 drivers/gpu/drm/nouveau/nouveau_drm.c client = nvxx_client(&drm->client.base); base 850 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nvif_client_suspend(&drm->master.base); base 875 drivers/gpu/drm/nouveau/nouveau_drm.c ret = nvif_client_resume(&drm->master.base); base 1070 drivers/gpu/drm/nouveau/nouveau_drm.c cli->base.super = false; base 93 drivers/gpu/drm/nouveau/nouveau_drv.h struct nvif_client base; base 145 drivers/gpu/drm/nouveau/nouveau_drv.h u32 base; base 42 drivers/gpu/drm/nouveau/nouveau_encoder.h struct drm_encoder_slave base; base 82 drivers/gpu/drm/nouveau/nouveau_encoder.h return container_of(slave, struct nouveau_encoder, base); base 87 drivers/gpu/drm/nouveau/nouveau_encoder.h return &enc->base.base; base 370 drivers/gpu/drm/nouveau/nouveau_fbcon.c fbcon->helper.fb = &fb->base; base 379 drivers/gpu/drm/nouveau/nouveau_fbcon.c info->fix.smem_start = fb->nvbo->bo.mem.bus.base + base 396 drivers/gpu/drm/nouveau/nouveau_fbcon.c fb->base.width, fb->base.height, fb->nvbo->bo.offset, nvbo); base 425 drivers/gpu/drm/nouveau/nouveau_fbcon.c drm_framebuffer_put(&nouveau_fb->base); base 46 drivers/gpu/drm/nouveau/nouveau_fence.c return container_of(fence, struct nouveau_fence, base); base 52 drivers/gpu/drm/nouveau/nouveau_fence.c return container_of(fence->base.lock, struct nouveau_fence_chan, lock); base 60 drivers/gpu/drm/nouveau/nouveau_fence.c dma_fence_signal_locked(&fence->base); base 64 drivers/gpu/drm/nouveau/nouveau_fence.c if (test_bit(DMA_FENCE_FLAG_USER_BITS, &fence->base.flags)) { base 71 drivers/gpu/drm/nouveau/nouveau_fence.c dma_fence_put(&fence->base); base 135 drivers/gpu/drm/nouveau/nouveau_fence.c if ((int)(seq - fence->base.seqno) < 0) base 184 drivers/gpu/drm/nouveau/nouveau_fence.c strcpy(fctx->name, nvxx_client(&cli->base)->name); base 211 drivers/gpu/drm/nouveau/nouveau_fence.c dma_fence_init(&fence->base, &nouveau_fence_ops_uevent, base 214 drivers/gpu/drm/nouveau/nouveau_fence.c dma_fence_init(&fence->base, &nouveau_fence_ops_legacy, base 218 drivers/gpu/drm/nouveau/nouveau_fence.c trace_dma_fence_emit(&fence->base); base 221 drivers/gpu/drm/nouveau/nouveau_fence.c dma_fence_get(&fence->base); base 237 drivers/gpu/drm/nouveau/nouveau_fence.c if (fence->base.ops == &nouveau_fence_ops_legacy || base 238 drivers/gpu/drm/nouveau/nouveau_fence.c fence->base.ops == &nouveau_fence_ops_uevent) { base 243 drivers/gpu/drm/nouveau/nouveau_fence.c if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->base.flags)) base 252 drivers/gpu/drm/nouveau/nouveau_fence.c return dma_fence_is_signaled(&fence->base); base 323 drivers/gpu/drm/nouveau/nouveau_fence.c ret = dma_fence_wait_timeout(&fence->base, intr, 15 * HZ); base 337 drivers/gpu/drm/nouveau/nouveau_fence.c struct dma_resv *resv = nvbo->bo.base.resv; base 401 drivers/gpu/drm/nouveau/nouveau_fence.c dma_fence_put(&(*pfence)->base); base 456 drivers/gpu/drm/nouveau/nouveau_fence.c ret = (int)(fctx->read(chan) - fence->base.seqno) >= 0; base 470 drivers/gpu/drm/nouveau/nouveau_fence.c WARN_ON(kref_read(&fence->base.refcount) <= 1); base 480 drivers/gpu/drm/nouveau/nouveau_fence.c dma_fence_put(&fence->base); base 493 drivers/gpu/drm/nouveau/nouveau_fence.c dma_fence_free(&fence->base); base 516 drivers/gpu/drm/nouveau/nouveau_fence.c set_bit(DMA_FENCE_FLAG_USER_BITS, &fence->base.flags); base 12 drivers/gpu/drm/nouveau/nouveau_fence.h struct dma_fence base; base 86 drivers/gpu/drm/nouveau/nouveau_fence.h struct nouveau_fence_chan base; base 91 drivers/gpu/drm/nouveau/nouveau_fence.h struct nouveau_fence_priv base; base 114 drivers/gpu/drm/nouveau/nouveau_gem.c struct dma_fence *fence = vma->fence ? &vma->fence->base : NULL; base 194 drivers/gpu/drm/nouveau/nouveau_gem.c ret = drm_gem_object_init(drm->dev, &nvbo->bo.base, size); base 215 drivers/gpu/drm/nouveau/nouveau_gem.c nvbo->bo.persistent_swap_storage = nvbo->bo.base.filp; base 245 drivers/gpu/drm/nouveau/nouveau_gem.c rep->map_handle = drm_vma_node_offset_addr(&nvbo->bo.base.vma_node); base 273 drivers/gpu/drm/nouveau/nouveau_gem.c ret = drm_gem_handle_create(file_priv, &nvbo->bo.base, base 276 drivers/gpu/drm/nouveau/nouveau_gem.c ret = nouveau_gem_info(file_priv, &nvbo->bo.base, &req->info); base 282 drivers/gpu/drm/nouveau/nouveau_gem.c drm_gem_object_put_unlocked(&nvbo->bo.base); base 348 drivers/gpu/drm/nouveau/nouveau_gem.c dma_fence_get(&fence->base); base 361 drivers/gpu/drm/nouveau/nouveau_gem.c drm_gem_object_put_unlocked(&nvbo->bo.base); base 499 drivers/gpu/drm/nouveau/nouveau_gem.c ret = nouveau_gem_set_domain(&nvbo->bo.base, b->read_domains, base 892 drivers/gpu/drm/nouveau/nouveau_gem.c lret = dma_resv_wait_timeout_rcu(nvbo->bo.base.resv, write, true, base 11 drivers/gpu/drm/nouveau/nouveau_gem.h return gem ? container_of(gem, struct nouveau_bo, bo.base) : NULL; base 102 drivers/gpu/drm/nouveau/nouveau_mem.c bool super = cli->base.super; base 123 drivers/gpu/drm/nouveau/nouveau_mem.c cli->base.super = true; base 127 drivers/gpu/drm/nouveau/nouveau_mem.c cli->base.super = super; base 139 drivers/gpu/drm/nouveau/nouveau_mem.c bool super = cli->base.super; base 144 drivers/gpu/drm/nouveau/nouveau_mem.c cli->base.super = true; base 168 drivers/gpu/drm/nouveau/nouveau_mem.c cli->base.super = super; base 84 drivers/gpu/drm/nouveau/nouveau_prime.c ret = drm_gem_object_init(dev, &nvbo->bo.base, size); base 98 drivers/gpu/drm/nouveau/nouveau_prime.c obj = &nvbo->bo.base; base 227 drivers/gpu/drm/nouveau/nouveau_ttm.c drm->agp.base = pci->agp.base; base 36 drivers/gpu/drm/nouveau/nouveau_usif.c struct drm_pending_event base; base 38 drivers/gpu/drm/nouveau/nouveau_usif.c struct drm_event base; base 93 drivers/gpu/drm/nouveau/nouveau_usif.c filp = ntfy->p->base.file_priv; base 111 drivers/gpu/drm/nouveau/nouveau_usif.c if (!WARN_ON(filp->event_space < ntfy->p->e.base.length)) { base 112 drivers/gpu/drm/nouveau/nouveau_usif.c list_add_tail(&ntfy->p->base.link, &filp->event_list); base 113 drivers/gpu/drm/nouveau/nouveau_usif.c filp->event_space -= ntfy->p->e.base.length; base 125 drivers/gpu/drm/nouveau/nouveau_usif.c struct nvif_client *client = &cli->base; base 170 drivers/gpu/drm/nouveau/nouveau_usif.c struct nvif_client *client = &cli->base; base 193 drivers/gpu/drm/nouveau/nouveau_usif.c struct nvif_client *client = &cli->base; base 212 drivers/gpu/drm/nouveau/nouveau_usif.c ntfy->p->base.event = &ntfy->p->e.base; base 213 drivers/gpu/drm/nouveau/nouveau_usif.c ntfy->p->base.file_priv = f; base 214 drivers/gpu/drm/nouveau/nouveau_usif.c ntfy->p->e.base.type = DRM_NOUVEAU_EVENT_NVIF; base 215 drivers/gpu/drm/nouveau/nouveau_usif.c ntfy->p->e.base.length = sizeof(ntfy->p->e.base) + ntfy->reply; base 230 drivers/gpu/drm/nouveau/nouveau_usif.c struct nvif_client *client = &cli->base; base 267 drivers/gpu/drm/nouveau/nouveau_usif.c struct nvif_client *client = &cli->base; base 297 drivers/gpu/drm/nouveau/nouveau_usif.c struct nvif_client *client = &cli->base; base 32 drivers/gpu/drm/nouveau/nv04_fence.c struct nouveau_fence_chan base; base 36 drivers/gpu/drm/nouveau/nv04_fence.c struct nouveau_fence_priv base; base 46 drivers/gpu/drm/nouveau/nv04_fence.c OUT_RING (chan, fence->base.seqno); base 72 drivers/gpu/drm/nouveau/nv04_fence.c nouveau_fence_context_del(&fctx->base); base 74 drivers/gpu/drm/nouveau/nv04_fence.c nouveau_fence_context_free(&fctx->base); base 82 drivers/gpu/drm/nouveau/nv04_fence.c nouveau_fence_context_new(chan, &fctx->base); base 83 drivers/gpu/drm/nouveau/nv04_fence.c fctx->base.emit = nv04_fence_emit; base 84 drivers/gpu/drm/nouveau/nv04_fence.c fctx->base.sync = nv04_fence_sync; base 85 drivers/gpu/drm/nouveau/nv04_fence.c fctx->base.read = nv04_fence_read; base 109 drivers/gpu/drm/nouveau/nv04_fence.c priv->base.dtor = nv04_fence_destroy; base 110 drivers/gpu/drm/nouveau/nv04_fence.c priv->base.context_new = nv04_fence_context_new; base 111 drivers/gpu/drm/nouveau/nv04_fence.c priv->base.context_del = nv04_fence_context_del; base 36 drivers/gpu/drm/nouveau/nv10_fence.c OUT_RING (chan, fence->base.seqno); base 60 drivers/gpu/drm/nouveau/nv10_fence.c nouveau_fence_context_del(&fctx->base); base 63 drivers/gpu/drm/nouveau/nv10_fence.c nouveau_fence_context_free(&fctx->base); base 75 drivers/gpu/drm/nouveau/nv10_fence.c nouveau_fence_context_new(chan, &fctx->base); base 76 drivers/gpu/drm/nouveau/nv10_fence.c fctx->base.emit = nv10_fence_emit; base 77 drivers/gpu/drm/nouveau/nv10_fence.c fctx->base.read = nv10_fence_read; base 78 drivers/gpu/drm/nouveau/nv10_fence.c fctx->base.sync = nv10_fence_sync; base 103 drivers/gpu/drm/nouveau/nv10_fence.c priv->base.dtor = nv10_fence_destroy; base 104 drivers/gpu/drm/nouveau/nv10_fence.c priv->base.context_new = nv10_fence_context_new; base 105 drivers/gpu/drm/nouveau/nv10_fence.c priv->base.context_del = nv10_fence_context_del; base 9 drivers/gpu/drm/nouveau/nv10_fence.h struct nouveau_fence_chan base; base 14 drivers/gpu/drm/nouveau/nv10_fence.h struct nouveau_fence_priv base; base 88 drivers/gpu/drm/nouveau/nv17_fence.c nouveau_fence_context_new(chan, &fctx->base); base 89 drivers/gpu/drm/nouveau/nv17_fence.c fctx->base.emit = nv10_fence_emit; base 90 drivers/gpu/drm/nouveau/nv17_fence.c fctx->base.read = nv10_fence_read; base 91 drivers/gpu/drm/nouveau/nv17_fence.c fctx->base.sync = nv17_fence_sync; base 124 drivers/gpu/drm/nouveau/nv17_fence.c priv->base.dtor = nv10_fence_destroy; base 125 drivers/gpu/drm/nouveau/nv17_fence.c priv->base.resume = nv17_fence_resume; base 126 drivers/gpu/drm/nouveau/nv17_fence.c priv->base.context_new = nv17_fence_context_new; base 127 drivers/gpu/drm/nouveau/nv17_fence.c priv->base.context_del = nv10_fence_context_del; base 49 drivers/gpu/drm/nouveau/nv50_fence.c nouveau_fence_context_new(chan, &fctx->base); base 50 drivers/gpu/drm/nouveau/nv50_fence.c fctx->base.emit = nv10_fence_emit; base 51 drivers/gpu/drm/nouveau/nv50_fence.c fctx->base.read = nv10_fence_read; base 52 drivers/gpu/drm/nouveau/nv50_fence.c fctx->base.sync = nv17_fence_sync; base 77 drivers/gpu/drm/nouveau/nv50_fence.c priv->base.dtor = nv10_fence_destroy; base 78 drivers/gpu/drm/nouveau/nv50_fence.c priv->base.resume = nv17_fence_resume; base 79 drivers/gpu/drm/nouveau/nv50_fence.c priv->base.context_new = nv50_fence_context_new; base 80 drivers/gpu/drm/nouveau/nv50_fence.c priv->base.context_del = nv10_fence_context_del; base 74 drivers/gpu/drm/nouveau/nv84_fence.c return fctx->base.emit32(chan, addr, fence->base.seqno); base 84 drivers/gpu/drm/nouveau/nv84_fence.c return fctx->base.sync32(chan, addr, fence->base.seqno); base 100 drivers/gpu/drm/nouveau/nv84_fence.c nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); base 104 drivers/gpu/drm/nouveau/nv84_fence.c nouveau_fence_context_del(&fctx->base); base 106 drivers/gpu/drm/nouveau/nv84_fence.c nouveau_fence_context_free(&fctx->base); base 120 drivers/gpu/drm/nouveau/nv84_fence.c nouveau_fence_context_new(chan, &fctx->base); base 121 drivers/gpu/drm/nouveau/nv84_fence.c fctx->base.emit = nv84_fence_emit; base 122 drivers/gpu/drm/nouveau/nv84_fence.c fctx->base.sync = nv84_fence_sync; base 123 drivers/gpu/drm/nouveau/nv84_fence.c fctx->base.read = nv84_fence_read; base 124 drivers/gpu/drm/nouveau/nv84_fence.c fctx->base.emit32 = nv84_fence_emit32; base 125 drivers/gpu/drm/nouveau/nv84_fence.c fctx->base.sync32 = nv84_fence_sync32; base 126 drivers/gpu/drm/nouveau/nv84_fence.c fctx->base.sequence = nv84_fence_read(chan); base 189 drivers/gpu/drm/nouveau/nv84_fence.c priv->base.dtor = nv84_fence_destroy; base 190 drivers/gpu/drm/nouveau/nv84_fence.c priv->base.suspend = nv84_fence_suspend; base 191 drivers/gpu/drm/nouveau/nv84_fence.c priv->base.resume = nv84_fence_resume; base 192 drivers/gpu/drm/nouveau/nv84_fence.c priv->base.context_new = nv84_fence_context_new; base 193 drivers/gpu/drm/nouveau/nv84_fence.c priv->base.context_del = nv84_fence_context_del; base 195 drivers/gpu/drm/nouveau/nv84_fence.c priv->base.uevent = true; base 69 drivers/gpu/drm/nouveau/nvc0_fence.c fctx->base.emit32 = nvc0_fence_emit32; base 70 drivers/gpu/drm/nouveau/nvc0_fence.c fctx->base.sync32 = nvc0_fence_sync32; base 81 drivers/gpu/drm/nouveau/nvc0_fence.c priv->base.context_new = nvc0_fence_context_new; base 234 drivers/gpu/drm/nouveau/nvkm/core/client.c return oclass->base.ctor(oclass, data, size, pobject); base 251 drivers/gpu/drm/nouveau/nvkm/core/client.c oclass->base = *sclass; base 291 drivers/gpu/drm/nouveau/nvkm/core/client.c struct nvkm_oclass oclass = { .base = nvkm_uclient_sclass }; base 69 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c args->v0.oclass[i].oclass = oclass.base.oclass; base 70 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c args->v0.oclass[i].minver = oclass.base.minver; base 71 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c args->v0.oclass[i].maxver = oclass.base.maxver; base 118 drivers/gpu/drm/nouveau/nvkm/core/ioctl.c } while (oclass.base.oclass != args->v0.oclass); base 300 drivers/gpu/drm/nouveau/nvkm/core/object.c object->oclass = oclass->base.oclass; base 334 drivers/gpu/drm/nouveau/nvkm/core/object.c oclass->base.func ? oclass->base.func : &nvkm_object_func; base 197 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c nvkm_object_ctor(&nvkm_oproxy_func, oclass, &oproxy->base); base 47 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c gk104_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base) base 51 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c u32 stat = nvkm_rd32(device, 0x104f14 + base); base 55 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c nvkm_wr32(device, 0x104f14 + base, 0x00000000); base 61 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x1000; base 64 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c u32 mask = nvkm_rd32(device, 0x104904 + base); base 65 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c u32 intr = nvkm_rd32(device, 0x104908 + base) & mask; base 68 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c nvkm_wr32(device, 0x104908 + base, 0x00000001); base 73 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c nvkm_wr32(device, 0x104908 + base, 0x00000002); base 77 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c gk104_ce_intr_launcherr(ce, base); base 78 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c nvkm_wr32(device, 0x104908 + base, 0x00000004); base 83 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c nvkm_wr32(device, 0x104908 + base, intr); base 49 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c gp100_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base) base 53 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c u32 stat = nvkm_rd32(device, 0x104418 + base); base 62 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x80; base 65 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c u32 mask = nvkm_rd32(device, 0x10440c + base); base 66 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c u32 intr = nvkm_rd32(device, 0x104410 + base) & mask; base 69 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c nvkm_wr32(device, 0x104410 + base, 0x00000001); base 74 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c nvkm_wr32(device, 0x104410 + base, 0x00000002); base 78 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c gp100_ce_intr_launcherr(ce, base); base 79 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c nvkm_wr32(device, 0x104410 + base, 0x00000004); base 84 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c nvkm_wr32(device, 0x104410 + base, intr); base 47 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c const u32 base = (subdev->index - NVKM_ENGINE_CE0) * 0x1000; base 48 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff; base 49 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16; base 52 drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c u32 data = nvkm_rd32(device, 0x104044 + base); base 111 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c lo = pstate->base.domain[domain->name]; base 208 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c .base.oclass = NVIF_CLASS_CONTROL, base 209 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c .base.minver = -1, base 210 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c .base.maxver = -1, base 360 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c !(engine->func->base.sclass)) base 364 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index -= engine->func->base.sclass(oclass, index, &sclass); base 377 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c oclass->base = sclass->base; base 151 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c struct nvkm_disp *disp = nvkm_disp(oproxy->base.engine); base 176 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c *pobject = &oproxy->base; base 201 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c oclass->base = root->base; base 471 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c .base.sclass = nvkm_disp_class_get, base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c if (!nvkm_head_find(&disp->base, args->v0.head)) base 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c struct nvkm_device *device = disp->base.engine.subdev.device; base 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c struct nvkm_device *device = disp->base.engine.subdev.device; base 54 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nv50_disp_mthd_list(struct nv50_disp *disp, int debug, u32 base, int c, base 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c u32 next = nvkm_rd32(device, list->data[i].addr + base + 0); base 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c u32 prev = nvkm_rd32(device, list->data[i].addr + base + c); base 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 81 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c u32 base = chan->head * mthd->addr; base 82 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c for (j = 0; j < mthd->data[i].nr; j++, base += list->addr) { base 100 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nv50_disp_mthd_list(disp, debug, base, mthd->prev, base 110 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = disp->base.engine.subdev.device; base 119 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = disp->base.engine.subdev.device; base 170 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 180 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 181 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c u64 size, base = chan->func->user(chan, &size); base 182 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c *data = nvkm_rd32(device, base + addr); base 190 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 191 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c u64 size, base = chan->func->user(chan, &size); base 192 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nvkm_wr32(device, base + addr, data); base 217 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 218 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c const u64 base = device->func->resource_addr(device, 0); base 220 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c *addr = base + chan->func->user(chan, size); base 231 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nv50_disp_chan_child_del_(struct nvkm_oproxy *base) base 234 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c container_of(base, typeof(*object), oproxy); base 249 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = disp->base.engine.subdev.device; base 258 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c *pobject = &object->oproxy.base; base 277 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 285 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c if (sclass->engine && sclass->engine->func->base.sclass) { base 286 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c sclass->engine->func->base.sclass(sclass, index, &oclass); base 172 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 190 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 138 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 157 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 166 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 175 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 169 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 187 drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 29 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c if (!nvkm_head_find(&disp->base, args->v0.head)) base 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 82 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 102 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; base 13 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h struct nvkm_outp base; base 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { base 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { base 64 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nvkm_outp_route(&disp->base); base 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { base 70 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { base 77 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { base 84 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) base 92 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 124 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 164 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { base 170 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c nvkm_disp_vblank(&disp->base, head->id); base 180 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c struct nvkm_device *device = disp->base.engine.subdev.device; base 188 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c struct nvkm_device *device = disp->base.engine.subdev.device; base 199 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { base 246 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c list_for_each_entry(head, &disp->base.head, head) { base 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { base 59 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { base 66 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { base 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_outp_route(&disp->base); base 72 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { base 77 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { base 84 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { base 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) base 99 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 130 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 172 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 201 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 221 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 241 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 252 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_disp_vblank(&disp->base, head); base 266 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 306 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_device *device = disp->base.engine.subdev.device; base 313 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c struct nvkm_device *device = disp->base.engine.subdev.device; base 340 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { base 400 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c list_for_each_entry(head, &disp->base.head, head) { base 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_root_(struct nvkm_disp *base) base 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c return nv50_disp(base)->func->root; base 46 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_intr_(struct nvkm_disp *base) base 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp = nv50_disp(base); base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_fini_(struct nvkm_disp *base) base 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp = nv50_disp(base); base 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_init_(struct nvkm_disp *base) base 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp = nv50_disp(base); base 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_dtor_(struct nvkm_disp *base) base 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp = nv50_disp(base); base 82 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nv50_disp_oneinit_(struct nvkm_disp *base) base 84 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nv50_disp *disp = nv50_disp(base); base 86 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->wndw.nr = func->wndw.cnt(&disp->base, &disp->wndw.mask); base 96 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->head.nr = func->head.cnt(&disp->base, &disp->head.mask); base 100 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = func->head.new(&disp->base, i); base 106 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->dac.nr = func->dac.cnt(&disp->base, &disp->dac.mask); base 110 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = func->dac.new(&disp->base, i); base 117 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->pior.nr = func->pior.cnt(&disp->base, &disp->pior.mask); base 121 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = func->pior.new(&disp->base, i); base 127 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->sor.nr = func->sor.cnt(&disp->base, &disp->sor.mask); base 131 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = func->sor.new(&disp->base, i); base 165 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c *pdisp = &disp->base; base 167 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = nvkm_disp_ctor(&nv50_disp_, device, index, &disp->base); base 480 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_devinit *devinit = disp->base.engine.subdev.device->devinit; base 532 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { base 537 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(ior, &disp->base.ior, head) { base 548 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 558 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { base 567 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { base 572 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_outp_route(&disp->base); base 573 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { base 578 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { base 585 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { base 616 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 650 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_device *device = disp->base.engine.subdev.device; base 667 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_disp_vblank(&disp->base, 0); base 672 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_disp_vblank(&disp->base, 1); base 686 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_device *device = disp->base.engine.subdev.device; base 695 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c struct nvkm_device *device = disp->base.engine.subdev.device; base 708 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c list_for_each_entry(head, &disp->base.head, head) { base 4 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h #define nv50_disp(p) container_of((p), struct nv50_disp, base) base 12 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h struct nvkm_disp base; base 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c if (!nvkm_head_find(&disp->base, args->v0.head)) base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/ovlynv50.c if (!nvkm_head_find(&disp->base, args->v0.head)) base 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocgf119.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c struct nvkm_subdev *subdev = &disp->base.engine.subdev; base 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h struct nvkm_sclass base; base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c .base.oclass = G82_DISP, base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c .base.minver = -1, base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c .base.maxver = -1, base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c .base.oclass = GT206_DISP, base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c .base.minver = -1, base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c .base.maxver = -1, base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c .base.oclass = GF110_DISP, base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c .base.minver = -1, base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c .base.maxver = -1, base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c .base.oclass = GK104_DISP, base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c .base.minver = -1, base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c .base.maxver = -1, base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c .base.oclass = GK110_DISP, base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c .base.minver = -1, base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c .base.maxver = -1, base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c .base.oclass = GM107_DISP, base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c .base.minver = -1, base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c .base.maxver = -1, base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c .base.oclass = GM200_DISP, base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c .base.minver = -1, base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c .base.maxver = -1, base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c .base.oclass = GP100_DISP, base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c .base.minver = -1, base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c .base.maxver = -1, base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c .base.oclass = GP102_DISP, base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c .base.minver = -1, base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c .base.maxver = -1, base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c .base.oclass = GT200_DISP, base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c .base.minver = -1, base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c .base.maxver = -1, base 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c .base.oclass = GT214_DISP, base 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c .base.minver = -1, base 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c .base.maxver = -1, base 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c .base.oclass = GV100_DISP, base 49 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c .base.minver = -1, base 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgv100.c .base.maxver = -1, base 94 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c .base.oclass = NV04_DISP, base 95 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c .base.minver = -1, base 96 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c .base.maxver = -1, base 72 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c if (!(head = nvkm_head_find(&disp->base, hidx))) base 76 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c list_for_each_entry(temp, &disp->base.outp, head) { base 293 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c sclass->base = root->func->user[index].base; base 319 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c struct nvkm_disp *base, const struct nvkm_oclass *oclass, base 322 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c struct nv50_disp *disp = nv50_disp(base); base 357 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c .base.oclass = NV50_DISP, base 358 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c .base.minver = -1, base 359 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c .base.maxver = -1, base 17 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h struct nvkm_sclass base; base 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c .base.oclass = TU102_DISP, base 49 drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c .base.minver = -1, base 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c .base.maxver = -1, base 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c struct nvkm_device *device = disp->base.engine.subdev.device; base 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c list_for_each_entry(head, &disp->base.head, head) { base 122 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c list_for_each_entry(head, &disp->base.head, head) { base 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 133 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c struct nvkm_device *device = chan->disp->base.engine.subdev.device; base 73 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c sclass->base = oclass[0]; base 86 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c oclass->base = nvkm_dma_sclass[index]; base 101 drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c .base.sclass = nvkm_dma_oclass_base_get, base 48 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c nvkm_dmaobj_bind(struct nvkm_object *base, struct nvkm_gpuobj *gpuobj, base 51 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c struct nvkm_dmaobj *dmaobj = nvkm_dmaobj(base); base 56 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c nvkm_dmaobj_dtor(struct nvkm_object *base) base 58 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c return nvkm_dmaobj(base); base 24 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c #define gf100_dmaobj(p) container_of((p), struct gf100_dmaobj, base) base 35 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c struct nvkm_dmaobj base; base 41 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c gf100_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, base 44 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c struct gf100_dmaobj *dmaobj = gf100_dmaobj(base); base 45 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device; base 52 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); base 53 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); base 54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | base 55 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c upper_32_bits(dmaobj->base.start)); base 83 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c *pdmaobj = &dmaobj->base; base 86 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c &data, &size, &dmaobj->base); base 103 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c if (dmaobj->base.target != NV_MEM_TARGET_VM) { base 117 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c dmaobj->flags0 |= (kind << 22) | (user << 20) | oclass->base.oclass; base 120 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c switch (dmaobj->base.target) { base 137 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c switch (dmaobj->base.access) { base 24 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c #define gf119_dmaobj(p) container_of((p), struct gf119_dmaobj, base) base 35 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c struct nvkm_dmaobj base; base 40 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c gf119_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, base 43 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c struct gf119_dmaobj *dmaobj = gf119_dmaobj(base); base 44 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device; base 51 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8); base 52 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8); base 81 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c *pdmaobj = &dmaobj->base; base 84 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c &data, &size, &dmaobj->base); base 100 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c if (dmaobj->base.target != NV_MEM_TARGET_VM) { base 114 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c switch (dmaobj->base.target) { base 22 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c #define gv100_dmaobj(p) container_of((p), struct gv100_dmaobj, base) base 33 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c struct nvkm_dmaobj base; base 38 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c gv100_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, base 41 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c struct gv100_dmaobj *dmaobj = gv100_dmaobj(base); base 42 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device; base 43 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c u64 start = dmaobj->base.start >> 8; base 44 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c u64 limit = dmaobj->base.limit >> 8; base 80 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c *pdmaobj = &dmaobj->base; base 83 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c &data, &size, &dmaobj->base); base 110 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c switch (dmaobj->base.target) { base 24 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c #define nv04_dmaobj(p) container_of((p), struct nv04_dmaobj, base) base 34 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c struct nvkm_dmaobj base; base 41 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c nv04_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, base 44 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c struct nv04_dmaobj *dmaobj = nv04_dmaobj(base); base 45 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device; base 46 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c u64 offset = dmaobj->base.start & 0xfffff000; base 47 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c u64 adjust = dmaobj->base.start & 0x00000fff; base 48 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c u32 length = dmaobj->base.limit - dmaobj->base.start; base 54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c if (!dmaobj->base.start) base 90 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c *pdmaobj = &dmaobj->base; base 93 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c &data, &size, &dmaobj->base); base 97 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c if (dmaobj->base.target == NV_MEM_TARGET_VM) { base 100 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c dmaobj->base.target = NV_MEM_TARGET_PCI; base 101 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c dmaobj->base.access = NV_MEM_ACCESS_RW; base 104 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c dmaobj->flags0 = oclass->base.oclass; base 105 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c switch (dmaobj->base.target) { base 119 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c switch (dmaobj->base.access) { base 24 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c #define nv50_dmaobj(p) container_of((p), struct nv50_dmaobj, base) base 35 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c struct nvkm_dmaobj base; base 41 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c nv50_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, base 44 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c struct nv50_dmaobj *dmaobj = nv50_dmaobj(base); base 45 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device; base 52 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); base 53 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); base 54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | base 55 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c upper_32_bits(dmaobj->base.start)); base 83 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c *pdmaobj = &dmaobj->base; base 86 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c &data, &size, &dmaobj->base); base 105 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c if (dmaobj->base.target != NV_MEM_TARGET_VM) { base 122 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c oclass->base.oclass; base 125 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c switch (dmaobj->base.target) { base 142 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c switch (dmaobj->base.access) { base 37 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c oclass->base = falcon->func->sclass[index]; base 64 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c const u32 base = falcon->addr; base 65 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c u32 dest = nvkm_rd32(device, base + 0x01c); base 66 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); base 67 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c u32 inst = nvkm_rd32(device, base + 0x050) & 0x3fffffff; base 76 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x004, 0x00000040); base 83 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x004, 0x00000010); base 89 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x004, intr); base 100 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c const u32 base = falcon->addr; base 112 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000); base 113 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x014, 0xffffffff); base 134 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c const u32 base = falcon->addr; base 143 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c caps = nvkm_rd32(device, base + 0x12c); base 148 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c caps = nvkm_rd32(device, base + 0x108); base 167 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c const u32 base = falcon->addr; base 174 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (nvkm_rd32(device, base + 0x008) & 0x00000010) base 179 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (!(nvkm_rd32(device, base + 0x180) & 0x80000000)) base 183 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x004, 0x00000010); base 187 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x014, 0xffffffff); base 266 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x618, 0x04000000); base 268 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x618, 0x00000114); base 269 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x11c, 0); base 270 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x110, addr >> 8); base 271 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x114, 0); base 272 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x118, 0x00006610); base 281 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0xff8, 0x00100000); base 283 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0xff4, falcon->code.data[i]); base 285 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x180, 0x01000000); base 288 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x188, i >> 6); base 289 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x184, falcon->code.data[i]); base 296 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0xff8, 0x00000000); base 298 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0xff4, falcon->data.data[i]); base 300 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0xff4, 0x00000000); base 302 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x1c0, 0x01000000); base 304 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x1c4, falcon->data.data[i]); base 306 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x1c4, 0x00000000); base 310 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x10c, 0x00000001); /* BLOCK_ON_FIFO */ base 311 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x104, 0x00000000); /* ENTRY */ base 312 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x100, 0x00000002); /* TRIGGER */ base 313 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x048, 0x00000003); /* FIFO | CHSW */ base 264 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c oclass->base = sclass->base; base 349 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c .base.sclass = nvkm_fifo_class_get, base 39 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c nvkm_fifo_chan_child_fini(struct nvkm_oproxy *base, bool suspend) base 42 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c container_of(base, typeof(*object), oproxy); base 72 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c nvkm_fifo_chan_child_init(struct nvkm_oproxy *base) base 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c container_of(base, typeof(*object), oproxy); base 105 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c nvkm_fifo_chan_child_del(struct nvkm_oproxy *base) base 108 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c container_of(base, typeof(*object), oproxy); base 109 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c struct nvkm_engine *engine = object->oproxy.base.engine; base 146 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c *pobject = &object->oproxy.base; base 176 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c ret = oclass->base.ctor(&(const struct nvkm_oclass) { base 177 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c .base = oclass->base, base 215 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->base.oclass = 0; base 219 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (oclass->base.oclass) { base 220 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (!oclass->base.ctor) base 221 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->base.ctor = nvkm_object_new; base 232 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->base = engine->func->sclass[index]; base 233 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c if (!oclass->base.ctor) base 234 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c oclass->base.ctor = nvkm_object_new; base 355 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c u64 hvmm, u64 push, u64 engines, int bar, u32 base, base 417 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c base + user * chan->chid; base 25 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h u64 engines, int bar, u32 base, u32 user, base 31 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h struct nvkm_sclass base; base 90 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c g84_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, base 93 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 95 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 107 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); base 115 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c chan->base.chid, chan->base.object.client->name); base 133 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c g84_fifo_chan_engine_init(struct nvkm_fifo_chan *base, base 136 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 160 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c g84_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, base 164 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 174 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c g84_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, base 177 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 205 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c g84_fifo_chan_init(struct nvkm_fifo_chan *base) base 207 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 209 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 211 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c u32 chid = chan->base.chid; base 236 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 242 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c ret = nvkm_fifo_chan_ctor(&g84_fifo_chan_func, &fifo->base, base 258 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c 0, 0xc00000, 0x2000, oclass, &chan->base); base 263 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c ret = nvkm_gpuobj_new(device, 0x0200, 0, true, chan->base.inst, base 268 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->base.inst, base 273 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, chan->base.inst, base 278 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, chan->base.inst, base 283 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c return nvkm_ramht_new(device, 0x8000, 16, chan->base.inst, &chan->ramht); base 4 drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h #define gf100_fifo_chan(p) container_of((p), struct gf100_fifo_chan, base) base 9 drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h struct nvkm_fifo_chan base; base 4 drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h #define gk104_fifo_chan(p) container_of((p), struct gk104_fifo_chan, base) base 9 drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h struct nvkm_fifo_chan base; base 4 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h #define nv04_fifo_chan(p) container_of((p), struct nv04_fifo_chan, base) base 9 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h struct nvkm_fifo_chan base; base 46 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nv50_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, base 49 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 51 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); base 81 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c chan->base.chid, chan->base.object.client->name); base 102 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nv50_fifo_chan_engine_init(struct nvkm_fifo_chan *base, base 105 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 129 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *base, base 132 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 137 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nv50_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, base 141 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 151 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *base, int cookie) base 153 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 158 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nv50_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, base 161 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 179 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nv50_fifo_chan_fini(struct nvkm_fifo_chan *base) base 181 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 183 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 184 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c u32 chid = chan->base.chid; base 193 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nv50_fifo_chan_init(struct nvkm_fifo_chan *base) base 195 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 197 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 199 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c u32 chid = chan->base.chid; base 206 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nv50_fifo_chan_dtor(struct nvkm_fifo_chan *base) base 208 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nv50_fifo_chan *chan = nv50_fifo_chan(base); base 235 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 241 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c ret = nvkm_fifo_chan_ctor(&nv50_fifo_chan_func, &fifo->base, base 247 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c 0, 0xc00000, 0x2000, oclass, &chan->base); base 252 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c ret = nvkm_gpuobj_new(device, 0x0200, 0x1000, true, chan->base.inst, base 257 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c ret = nvkm_gpuobj_new(device, 0x1200, 0, true, chan->base.inst, base 262 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->base.inst, base 267 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c return nvkm_ramht_new(device, 0x8000, 16, chan->base.inst, &chan->ramht); base 4 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h #define nv50_fifo_chan(p) container_of((p), struct nv50_fifo_chan, base) base 10 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h struct nvkm_fifo_chan base; base 34 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, base 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c struct nv50_fifo *fifo = nv50_fifo(base); base 58 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c *pobject = &chan->base.object; base 65 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c args->v0.chid = chan->base.chid; base 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); base 83 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12); base 90 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c .base.oclass = G82_CHANNEL_DMA, base 91 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c .base.minver = 0, base 92 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c .base.maxver = 0, base 36 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie) base 38 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nv04_fifo_chan *chan = nv04_fifo_chan(base); base 39 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; base 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c mutex_lock(&chan->fifo->base.engine.subdev.mutex); base 43 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c mutex_unlock(&chan->fifo->base.engine.subdev.mutex); base 47 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, base 50 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nv04_fifo_chan *chan = nv04_fifo_chan(base); base 51 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; base 52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c u32 context = 0x80000000 | chan->base.chid << 24; base 66 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c mutex_lock(&chan->fifo->base.engine.subdev.mutex); base 67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, base 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c mutex_unlock(&chan->fifo->base.engine.subdev.mutex); base 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nv04_fifo_dma_fini(struct nvkm_fifo_chan *base) base 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nv04_fifo_chan *chan = nv04_fifo_chan(base); base 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 82 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c u32 mask = fifo->base.nr - 1; base 87 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c spin_lock_irqsave(&fifo->base.lock, flags); base 92 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c if (chid == chan->base.chid) { base 121 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); base 123 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c spin_unlock_irqrestore(&fifo->base.lock, flags); base 127 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nv04_fifo_dma_init(struct nvkm_fifo_chan *base) base 129 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nv04_fifo_chan *chan = nv04_fifo_chan(base); base 131 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 132 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c u32 mask = 1 << chan->base.chid; base 134 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c spin_lock_irqsave(&fifo->base.lock, flags); base 136 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c spin_unlock_irqrestore(&fifo->base.lock, flags); base 140 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base) base 142 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nv04_fifo_chan *chan = nv04_fifo_chan(base); base 144 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; base 165 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, base 172 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nv04_fifo *fifo = nv04_fifo(base); base 174 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 190 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c *pobject = &chan->base.object; base 192 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, base 197 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c 0, 0x800000, 0x10000, oclass, &chan->base); base 202 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c args->v0.chid = chan->base.chid; base 203 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c chan->ramfc = chan->base.chid * 32; base 208 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4); base 222 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c .base.oclass = NV03_CHANNEL_DMA, base 223 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c .base.minver = 0, base 224 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c .base.maxver = 0, base 36 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, base 43 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c struct nv04_fifo *fifo = nv04_fifo(base); base 45 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 61 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c *pobject = &chan->base.object; base 63 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, base 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c 0, 0x800000, 0x10000, oclass, &chan->base); base 73 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c args->v0.chid = chan->base.chid; base 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c chan->ramfc = chan->base.chid * 32; base 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); base 93 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c .base.oclass = NV10_CHANNEL_DMA, base 94 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c .base.minver = 0, base 95 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c .base.maxver = 0, base 36 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c nv17_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, base 43 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c struct nv04_fifo *fifo = nv04_fifo(base); base 45 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 61 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c *pobject = &chan->base.object; base 63 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, base 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c 0, 0x800000, 0x10000, oclass, &chan->base); base 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c args->v0.chid = chan->base.chid; base 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c chan->ramfc = chan->base.chid * 64; base 80 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); base 94 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c .base.oclass = NV17_CHANNEL_DMA, base 95 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c .base.minver = 0, base 96 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c .base.maxver = 0, base 59 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nv40_fifo_dma_engine_fini(struct nvkm_fifo_chan *base, base 62 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c struct nv04_fifo_chan *chan = nv04_fifo_chan(base); base 64 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 73 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c spin_lock_irqsave(&fifo->base.lock, flags); base 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); base 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c if (chid == chan->base.chid) base 84 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c spin_unlock_irqrestore(&fifo->base.lock, flags); base 89 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nv40_fifo_dma_engine_init(struct nvkm_fifo_chan *base, base 92 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c struct nv04_fifo_chan *chan = nv04_fifo_chan(base); base 94 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 104 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c spin_lock_irqsave(&fifo->base.lock, flags); base 107 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); base 108 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c if (chid == chan->base.chid) base 115 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c spin_unlock_irqrestore(&fifo->base.lock, flags); base 120 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nv40_fifo_dma_engine_dtor(struct nvkm_fifo_chan *base, base 123 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c struct nv04_fifo_chan *chan = nv04_fifo_chan(base); base 128 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nv40_fifo_dma_engine_ctor(struct nvkm_fifo_chan *base, base 132 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c struct nv04_fifo_chan *chan = nv04_fifo_chan(base); base 143 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, base 146 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c struct nv04_fifo_chan *chan = nv04_fifo_chan(base); base 147 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; base 148 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c u32 context = chan->base.chid << 23; base 162 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c mutex_lock(&chan->fifo->base.engine.subdev.mutex); base 163 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, base 165 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c mutex_unlock(&chan->fifo->base.engine.subdev.mutex); base 183 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, base 190 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c struct nv04_fifo *fifo = nv04_fifo(base); base 192 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 208 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c *pobject = &chan->base.object; base 210 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c ret = nvkm_fifo_chan_ctor(&nv40_fifo_dma_func, &fifo->base, base 216 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c 0, 0xc00000, 0x1000, oclass, &chan->base); base 221 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c args->v0.chid = chan->base.chid; base 222 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c chan->ramfc = chan->base.chid * 128; base 227 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); base 242 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c .base.oclass = NV40_CHANNEL_DMA, base 243 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c .base.minver = 0, base 244 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c .base.maxver = 0, base 34 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, base 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c struct nv50_fifo *fifo = nv50_fifo(base); base 58 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c *pobject = &chan->base.object; base 65 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c args->v0.chid = chan->base.chid; base 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); base 88 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c .base.oclass = NV50_CHANNEL_DMA, base 89 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c .base.minver = 0, base 90 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c .base.maxver = 0, base 54 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 66 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid); base 95 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c mutex_lock(&fifo->base.engine.subdev.mutex); base 97 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c mutex_unlock(&fifo->base.engine.subdev.mutex); base 103 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c mutex_lock(&fifo->base.engine.subdev.mutex); base 105 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c mutex_unlock(&fifo->base.engine.subdev.mutex); base 128 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 148 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 154 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c spin_lock_irqsave(&fifo->base.lock, flags); base 157 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c spin_unlock_irqrestore(&fifo->base.lock, flags); base 179 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 181 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 chid = chan->base.chid; base 185 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c assert_spin_locked(&fifo->base.lock); base 191 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c if (engine != &fifo->base.engine) base 194 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c nvkm_fifo_kevent(&fifo->base, chid); base 257 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c gf100_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) base 259 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct gf100_fifo *fifo = gf100_fifo(base); base 260 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 294 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c chan = nvkm_fifo_chan_inst(&fifo->base, info->inst, &flags); base 307 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c nvkm_fifo_chan_put(&fifo->base, flags, &chan); base 319 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 325 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c spin_lock_irqsave(&fifo->base.lock, flags); base 337 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c if (chan->base.chid == chid) { base 347 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c spin_unlock_irqrestore(&fifo->base.lock, flags); base 353 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 407 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 429 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); base 435 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c nvkm_fifo_chan_put(&fifo->base, flags, &chan); base 445 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 464 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 475 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c nvkm_fifo_uevent(&fifo->base); base 489 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 499 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c gf100_fifo_intr(struct nvkm_fifo *base) base 501 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct gf100_fifo *fifo = gf100_fifo(base); base 502 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 538 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c gf100_fifo_intr_fault(&fifo->base, unit); base 574 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c gf100_fifo_oneinit(struct nvkm_fifo *base) base 576 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct gf100_fifo *fifo = gf100_fifo(base); base 577 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 614 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c gf100_fifo_fini(struct nvkm_fifo *base) base 616 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct gf100_fifo *fifo = gf100_fifo(base); base 621 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c gf100_fifo_init(struct nvkm_fifo *base) base 623 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct gf100_fifo *fifo = gf100_fifo(base); base 624 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 657 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c gf100_fifo_dtor(struct nvkm_fifo *base) base 659 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct gf100_fifo *fifo = gf100_fifo(base); base 660 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 693 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c *pfifo = &fifo->base; base 695 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c return nvkm_fifo_ctor(&gf100_fifo, device, index, 128, &fifo->base); base 4 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h #define gf100_fifo(p) container_of((p), struct gf100_fifo, base) base 11 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h struct nvkm_fifo base; base 56 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 99 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_class_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, base 102 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct gk104_fifo *fifo = gk104_fifo(base); base 116 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_class_get(struct nvkm_fifo *base, int index, base 119 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct gk104_fifo *fifo = gk104_fifo(base); base 123 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c oclass->base = fifo->func->user.user; base 129 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c oclass->base = fifo->func->chan.user; base 155 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 183 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 213 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c mutex_lock(&fifo->base.engine.subdev.mutex); base 219 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c mutex_unlock(&fifo->base.engine.subdev.mutex); base 226 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c mutex_lock(&fifo->base.engine.subdev.mutex); base 234 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c mutex_unlock(&fifo->base.engine.subdev.mutex); base 241 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_wo32(memory, offset + 0, chan->base.chid); base 255 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 262 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 278 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 284 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c spin_lock_irqsave(&fifo->base.lock, flags); base 289 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c spin_unlock_irqrestore(&fifo->base.lock, flags); base 312 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 316 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c assert_spin_locked(&fifo->base.lock); base 336 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c if (chan->base.chid == chid) { base 356 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_recover_chan(struct nvkm_fifo *base, int chid) base 358 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct gk104_fifo *fifo = gk104_fifo(base); base 359 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 367 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c assert_spin_locked(&fifo->base.lock); base 375 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_fifo_kevent(&fifo->base, chid); base 399 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 406 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c assert_spin_locked(&fifo->base.lock); base 418 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_recover_chan(&fifo->base, status.chan->id); base 465 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) base 467 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct gk104_fifo *fifo = gk104_fifo(base); base 468 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 518 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c spin_lock_irqsave(&fifo->base.lock, flags); base 519 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c chan = nvkm_fifo_chan_inst_locked(&fifo->base, info->inst); base 532 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_recover_chan(&fifo->base, chan->chid); base 545 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c spin_unlock_irqrestore(&fifo->base.lock, flags); base 562 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 581 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 588 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c spin_lock_irqsave(&fifo->base.lock, flags); base 606 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c spin_unlock_irqrestore(&fifo->base.lock, flags); base 612 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 633 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 643 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 686 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 711 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); base 717 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_fifo_chan_put(&fifo->base, flags, &chan); base 735 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 756 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 769 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c nvkm_fifo_uevent(&fifo->base); base 773 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_intr(struct nvkm_fifo *base) base 775 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct gk104_fifo *fifo = gk104_fifo(base); base 776 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 827 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->func->intr.fault(&fifo->base, unit); base 865 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_fini(struct nvkm_fifo *base) base 867 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct gk104_fifo *fifo = gk104_fifo(base); base 868 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 875 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_info(struct nvkm_fifo *base, u64 mthd, u64 *data) base 877 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct gk104_fifo *fifo = gk104_fifo(base); base 903 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_oneinit(struct nvkm_fifo *base) base 905 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct gk104_fifo *fifo = gk104_fifo(base); base 906 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 950 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->base.nr * 2/* TSG+chan */ * base 964 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c fifo->base.nr * 0x200, 0x1000, true, base 978 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_init(struct nvkm_fifo *base) base 980 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct gk104_fifo *fifo = gk104_fifo(base); base 981 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 1010 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c gk104_fifo_dtor(struct nvkm_fifo *base) base 1012 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct gk104_fifo *fifo = gk104_fifo(base); base 1013 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 1053 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c *pfifo = &fifo->base; base 1055 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c return nvkm_fifo_ctor(&gk104_fifo_, device, index, nr, &fifo->base); base 4 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h #define gk104_fifo(p) container_of((p), struct gk104_fifo, base) base 14 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h struct nvkm_fifo base; base 32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 36 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c nvkm_wo32(memory, offset + 0, chan->base.chid); base 37 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c nvkm_wo32(memory, offset + 4, chan->base.inst->addr >> 12); base 32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 34 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c g84_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, base 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c struct nv50_fifo *fifo = nv50_fifo(base); base 60 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c *pobject = &chan->base.object; base 67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c args->v0.chid = chan->base.chid; base 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); base 84 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12); base 91 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c .base.oclass = G82_CHANNEL_GPFIFO, base 92 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c .base.minver = 0, base 93 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c .base.maxver = 0, base 70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, base 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct gf100_fifo_chan *chan = gf100_fifo_chan(base); base 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct nvkm_subdev *subdev = &chan->fifo->base.engine.subdev; base 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct nvkm_gpuobj *inst = chan->base.inst; base 81 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wr32(device, 0x002634, chan->base.chid); base 83 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c if (nvkm_rd32(device, 0x002634) == chan->base.chid) base 87 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c chan->base.chid, chan->base.object.client->name); base 106 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c gf100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, base 110 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct gf100_fifo_chan *chan = gf100_fifo_chan(base); base 111 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct nvkm_gpuobj *inst = chan->base.inst; base 125 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c gf100_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base, base 128 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct gf100_fifo_chan *chan = gf100_fifo_chan(base); base 129 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma); base 134 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c gf100_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, base 138 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct gf100_fifo_chan *chan = gf100_fifo_chan(base); base 149 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size, base 154 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm, base 159 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c gf100_fifo_gpfifo_fini(struct nvkm_fifo_chan *base) base 161 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct gf100_fifo_chan *chan = gf100_fifo_chan(base); base 163 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 164 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c u32 coff = chan->base.chid * 8; base 178 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c gf100_fifo_gpfifo_init(struct nvkm_fifo_chan *base) base 180 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct gf100_fifo_chan *chan = gf100_fifo_chan(base); base 182 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 183 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c u32 addr = chan->base.inst->addr >> 12; base 184 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c u32 coff = chan->base.chid * 8; base 196 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c gf100_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base) base 198 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c return gf100_fifo_chan(base); base 214 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, base 220 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c struct gf100_fifo *fifo = gf100_fifo(base); base 240 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c *pobject = &chan->base.object; base 244 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base, base 254 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c oclass, &chan->base); base 258 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c args->v0.chid = chan->base.chid; base 262 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c usermem = chan->base.chid * 0x1000; base 273 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_kmap(chan->base.inst); base 274 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem)); base 275 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem)); base 276 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x10, 0x0000face); base 277 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x30, 0xfffff902); base 278 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset)); base 279 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) | base 281 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x54, 0x00000002); base 282 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x84, 0x20400000); base 283 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x94, 0x30000001); base 284 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x9c, 0x00000100); base 285 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0xa4, 0x1f1f1f1f); base 286 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0xa8, 0x1f1f1f1f); base 287 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0xac, 0x0000001f); base 288 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000); base 289 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */ base 290 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */ base 291 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_done(chan->base.inst); base 297 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c .base.oclass = FERMI_CHANNEL_GPFIFO, base 298 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c .base.minver = 0, base 299 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c .base.maxver = 0, base 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 43 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct nvkm_client *client = chan->base.object.client; base 50 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wr32(device, 0x002634, chan->base.chid); base 57 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c cgrp ? cgrp->id : chan->base.chid, client->name); base 58 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_fifo_recover_chan(&fifo->base, chan->base.chid); base 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c mutex_lock(&chan->base.fifo->engine.subdev.mutex); base 70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c mutex_unlock(&chan->base.fifo->engine.subdev.mutex); base 98 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, base 101 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct gk104_fifo_chan *chan = gk104_fifo_chan(base); base 102 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct nvkm_gpuobj *inst = chan->base.inst; base 125 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, base 128 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct gk104_fifo_chan *chan = gk104_fifo_chan(base); base 129 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct nvkm_gpuobj *inst = chan->base.inst; base 150 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base, base 153 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct gk104_fifo_chan *chan = gk104_fifo_chan(base); base 154 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma); base 159 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, base 163 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct gk104_fifo_chan *chan = gk104_fifo_chan(base); base 174 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size, base 179 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm, base 184 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base) base 186 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct gk104_fifo_chan *chan = gk104_fifo_chan(base); base 188 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 189 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c u32 coff = chan->base.chid * 8; base 202 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base) base 204 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct gk104_fifo_chan *chan = gk104_fifo_chan(base); base 206 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 207 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c u32 addr = chan->base.inst->addr >> 12; base 208 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c u32 coff = chan->base.chid * 8; base 222 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base) base 224 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c struct gk104_fifo_chan *chan = gk104_fifo_chan(base); base 270 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c *pobject = &chan->base.object; base 275 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base, base 278 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c oclass, &chan->base); base 282 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c *chid = chan->base.chid; base 283 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c *inst = chan->base.inst->addr; base 291 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c chan->cgrp->id = chan->base.chid; base 298 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c usermem = chan->base.chid * 0x200; base 308 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_kmap(chan->base.inst); base 309 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem)); base 310 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem)); base 311 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x10, 0x0000face); base 312 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x30, 0xfffff902); base 313 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset)); base 314 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) | base 316 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x84, 0x20400000); base 317 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x94, 0x30000001); base 318 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x9c, 0x00000100); base 319 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0xac, 0x0000001f); base 320 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0xe4, priv ? 0x00000020 : 0x00000000); base 321 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0xe8, chan->base.chid); base 322 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000); base 323 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */ base 324 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */ base 325 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_done(chan->base.inst); base 40 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c struct nvkm_subdev *subdev = &chan->base.fifo->engine.subdev; base 54 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_kmap(chan->base.inst); base 55 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_mo32(chan->base.inst, 0x0ac, mask, data); base 56 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_done(chan->base.inst); base 66 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c gv100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, base 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c struct gk104_fifo_chan *chan = gk104_fifo_chan(base); base 70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c struct nvkm_gpuobj *inst = chan->base.inst; base 89 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c gv100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, base 92 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c struct gk104_fifo_chan *chan = gk104_fifo_chan(base); base 93 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c struct nvkm_gpuobj *inst = chan->base.inst; base 129 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 150 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c *pobject = &chan->base.object; base 155 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c ret = nvkm_fifo_chan_ctor(func, &fifo->base, 0x1000, 0x1000, true, vmm, base 157 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c oclass, &chan->base); base 161 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c *chid = chan->base.chid; base 162 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c *inst = chan->base.inst->addr; base 163 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c *token = chan->base.func->submit_token(&chan->base); base 171 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c chan->cgrp->id = chan->base.chid; base 178 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c usermem = chan->base.chid * 0x200; base 202 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_kmap(chan->base.inst); base 203 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem)); base 204 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x00c, upper_32_bits(usermem)); base 205 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x010, 0x0000face); base 206 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x030, 0x7ffff902); base 207 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x048, lower_32_bits(ioffset)); base 208 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x04c, upper_32_bits(ioffset) | base 210 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x084, 0x20400000); base 211 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x094, 0x30000001); base 212 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x0e4, priv ? 0x00000020 : 0x00000000); base 213 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x0e8, chan->base.chid); base 214 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x0f4, 0x00001000); base 215 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x0f8, 0x10003080); base 216 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_mo32(chan->base.inst, 0x218, 0x00000000, 0x00000000); base 217 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x220, lower_32_bits(mthd)); base 218 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x224, upper_32_bits(mthd)); base 219 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_done(chan->base.inst); base 34 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nv50_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, base 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c struct nv50_fifo *fifo = nv50_fifo(base); base 60 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c *pobject = &chan->base.object; base 67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c args->v0.chid = chan->base.chid; base 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); base 89 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c .base.oclass = NV50_CHANNEL_GPFIFO, base 90 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c .base.minver = 0, base 91 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c .base.maxver = 0, base 32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c tu102_fifo_gpfifo_submit_token(struct nvkm_fifo_chan *base) base 34 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c struct gk104_fifo_chan *chan = gk104_fifo_chan(base); base 35 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c return (chan->runl << 16) | chan->base.chid; base 36 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c const u64 user = nvkm_memory_addr(usermem) + (chan->base.chid * 0x200); base 37 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c const u64 inst = chan->base.inst->addr; base 41 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->base.chid); base 48 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nv04_fifo_pause(struct nvkm_fifo *base, unsigned long *pflags) base 49 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c __acquires(fifo->base.lock) base 51 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nv04_fifo *fifo = nv04_fifo(base); base 52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 55 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c spin_lock_irqsave(&fifo->base.lock, flags); base 84 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nv04_fifo_start(struct nvkm_fifo *base, unsigned long *pflags) base 85 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c __releases(fifo->base.lock) base 87 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nv04_fifo *fifo = nv04_fifo(base); base 88 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 94 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c spin_unlock_irqrestore(&fifo->base.lock, flags); base 139 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 164 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); base 169 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nvkm_fifo_chan_put(&fifo->base, flags, &chan); base 190 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 200 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); base 232 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nvkm_fifo_chan_put(&fifo->base, flags, &chan); base 240 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nv04_fifo_intr(struct nvkm_fifo *base) base 242 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nv04_fifo *fifo = nv04_fifo(base); base 243 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nvkm_subdev *subdev = &fifo->base.engine.subdev; base 252 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & (fifo->base.nr - 1); base 284 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nvkm_fifo_uevent(&fifo->base); base 299 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nv04_fifo_init(struct nvkm_fifo *base) base 301 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nv04_fifo *fifo = nv04_fifo(base); base 302 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 317 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); base 338 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c *pfifo = &fifo->base; base 340 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c ret = nvkm_fifo_ctor(func, device, index, nr, &fifo->base); base 344 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c set_bit(nr - 1, fifo->base.mask); /* inactive channel */ base 4 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h #define nv04_fifo(p) container_of((p), struct nv04_fifo, base) base 16 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h struct nvkm_fifo base; base 51 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c nv17_fifo_init(struct nvkm_fifo *base) base 53 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c struct nv04_fifo *fifo = nv04_fifo(base); base 54 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); base 60 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c nv40_fifo_init(struct nvkm_fifo *base) base 62 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c struct nv04_fifo *fifo = nv04_fifo(base); base 63 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 101 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); base 32 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 40 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c for (i = 0, p = 0; i < fifo->base.nr; i++) { base 54 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c mutex_lock(&fifo->base.engine.subdev.mutex); base 56 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c mutex_unlock(&fifo->base.engine.subdev.mutex); base 60 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c nv50_fifo_oneinit(struct nvkm_fifo *base) base 62 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c struct nv50_fifo *fifo = nv50_fifo(base); base 63 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c nv50_fifo_init(struct nvkm_fifo *base) base 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c struct nv50_fifo *fifo = nv50_fifo(base); base 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 100 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c nv50_fifo_dtor(struct nvkm_fifo *base) base 102 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c struct nv50_fifo *fifo = nv50_fifo(base); base 117 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c *pfifo = &fifo->base; base 119 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c ret = nvkm_fifo_ctor(func, device, index, 128, &fifo->base); base 123 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c set_bit(0, fifo->base.mask); /* PIO channel */ base 124 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c set_bit(127, fifo->base.mask); /* inactive channel */ base 4 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h #define nv50_fifo(p) container_of((p), struct nv50_fifo, base) base 8 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h struct nvkm_fifo base; base 35 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 85 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c struct nvkm_device *device = fifo->base.engine.subdev.device; base 95 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c int ret = gr->func->object_get(gr, index, &oclass->base); base 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (oclass->base.oclass) base 103 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c oclass->base = gr->func->sclass[index]; base 1012 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = info->gr->base.engine.subdev.device; base 1035 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1097 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1117 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1163 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1273 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1309 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1317 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1327 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1371 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1442 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 774 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c struct nvkm_device *device = gr->base.engine.subdev.device; base 190 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c struct nvkm_device *device = gr->base.engine.subdev.device; base 200 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c struct nvkm_device *device = gr->base.engine.subdev.device; base 851 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = gr->base.engine.subdev.device; base 866 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = info->gr->base.engine.subdev.device; base 906 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = gr->base.engine.subdev.device; base 918 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = gr->base.engine.subdev.device; base 925 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = gr->base.engine.subdev.device; base 932 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = gr->base.engine.subdev.device; base 819 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c struct nvkm_device *device = gr->base.engine.subdev.device; base 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c struct nvkm_device *device = gr->base.engine.subdev.device; base 871 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c struct nvkm_device *device = gr->base.engine.subdev.device; base 951 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c nvkm_wr32(gr->base.engine.subdev.device, 0x406500, 0x00000001); base 957 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c struct nvkm_device *device = gr->base.engine.subdev.device; base 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c struct nvkm_device *device = gr->base.engine.subdev.device; base 40 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c struct nvkm_device *device = gr->base.engine.subdev.device; base 48 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c struct nvkm_device *device = gr->base.engine.subdev.device; base 73 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c nvkm_wr32(gr->base.engine.subdev.device, 0x4041c4, tmp); base 79 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c nvkm_wr32(gr->base.engine.subdev.device, 0x406500, 0x00000000); base 85 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c struct nvkm_device *device = gr->base.engine.subdev.device; base 27 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c struct nvkm_device *device = gr->base.engine.subdev.device; base 98 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c struct nvkm_device *device = gr->base.engine.subdev.device; base 116 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 153 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 160 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 169 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 180 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 301 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c int offset, base; base 585 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c base = 0x408000 + (i<<12); base 587 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c base = 0x408000 + (i<<11); base 589 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0xc00; base 591 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0x80; base 600 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0x200 + (j<<7); base 602 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0x100 + (j<<7); base 654 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x300, 0x4); base 656 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x300, 0x5); base 658 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x304, 0x00007070); base 660 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x304, 0x00027070); base 662 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x304, 0x01127070); base 664 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x304, 0x05127070); base 667 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x318, 1); base 669 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x320, 1); base 671 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x318, 0x0003ffff); base 673 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x318, 0x03ffffff); base 675 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x320, 0x07ffffff); base 678 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x324, 5); base 680 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x328, 4); base 683 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x340, 9); base 684 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0x340; base 686 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x33c, 0xb); base 687 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0x344; base 689 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x33c, 0xd); base 690 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0x344; base 700 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x36c, 1); base 702 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x400, 2); base 703 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x404, 0x00000040); base 704 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x40c, 2); base 705 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x40c, 0x0d0c0b0a); base 706 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x410, 0x00141210); base 709 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0x800; base 711 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0x500; base 727 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c cp_ctx(ctx, base + 0x54c, 2); base 729 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x54c, 0x003fe006); base 731 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x54c, 0x003fe007); base 732 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c gr_def(ctx, base + 0x550, 0x003fe000); base 736 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0xa00; base 738 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0x680; base 743 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0xe00; base 745 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c offset = base + 0x700; base 798 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c int base, num; base 799 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c base = ctx->ctxvals_pos; base 1107 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c num = ctx->ctxvals_pos - base; base 1108 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c ctx->ctxvals_pos = base; base 98 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 115 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c g84_gr_tlb_flush(struct nvkm_gr *base) base 117 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c struct nv50_gr *gr = nv50_gr(base); base 118 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 51 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 67 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; base 102 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 114 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; base 292 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_object_ctor(oclass->base.func ? oclass->base.func : base 299 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) base 301 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); base 327 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, base 378 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, base 382 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); base 387 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 727 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 745 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_start_ctxsw(struct nvkm_gr *base) base 747 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); base 760 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_stop_ctxsw(struct nvkm_gr *base) base 762 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); base 777 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 796 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 813 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 830 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 868 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 884 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 900 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 916 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 924 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_chsw_load(struct nvkm_gr *base) base 926 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); base 928 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c); base 932 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808); base 942 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 957 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; base 993 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1022 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1039 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1077 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1100 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_units(struct nvkm_gr *base) base 1102 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); base 1176 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1237 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1258 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1303 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1351 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1475 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) base 1477 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1479 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "%06x - done %08x\n", base, base 1480 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x400)); base 1481 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, base 1482 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x800), base 1483 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x804), base 1484 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x808), base 1485 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x80c)); base 1486 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, base 1487 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x810), base 1488 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x814), base 1489 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x818), base 1490 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_rd32(device, base + 0x81c)); base 1496 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1508 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1546 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_intr(struct nvkm_gr *base) base 1548 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); base 1549 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1648 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 falcon, u32 starstar, u32 base) base 1650 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1664 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 head = init->addr - base; base 1691 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1778 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1938 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_oneinit(struct nvkm_gr *base) base 1940 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); base 1941 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1987 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_(struct nvkm_gr *base) base 1989 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); base 1990 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &base->engine.subdev; base 2019 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); base 2033 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fini_(struct nvkm_gr *base, bool suspend) base 2035 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); base 2036 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 2056 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_dtor(struct nvkm_gr *base) base 2058 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); base 2100 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 2147 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_firmware_get(&gr->base.engine.subdev, fwname, &fw); base 2171 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c &gr->base); base 2183 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c *pgr = &gr->base; base 2203 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464); base 2209 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 2217 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 2224 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 2231 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 2245 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000); base 2252 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data); base 2258 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 2274 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 2281 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 2309 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 2316 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 26 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h #define gf100_gr(p) container_of((p), struct gf100_gr, base) base 83 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h struct nvkm_gr base; base 109 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c nvkm_wr32(gr->base.engine.subdev.device, 0x405a14, 0x80000000); base 126 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c struct nvkm_device *device = gr->base.engine.subdev.device; base 393 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c nvkm_wr32(gr->base.engine.subdev.device, 0x407020, 0x40000000); base 399 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c struct nvkm_device *device = gr->base.engine.subdev.device; base 408 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c struct nvkm_device *device = gr->base.engine.subdev.device; base 417 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c struct nvkm_device *device = gr->base.engine.subdev.device; base 432 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c struct nvkm_device *device = gr->base.engine.subdev.device; base 341 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c struct nvkm_device *device = gr->base.engine.subdev.device; base 189 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 214 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c struct nvkm_device *device = gr->base.engine.subdev.device; base 222 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c struct nvkm_device *device = gr->base.engine.subdev.device; base 314 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c *pgr = &gr->base; base 290 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x2c350f63); base 296 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c struct nvkm_device *device = gr->base.engine.subdev.device; base 304 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c struct nvkm_device *device = gr->base.engine.subdev.device; base 311 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 346 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c struct nvkm_device *device = gr->base.engine.subdev.device; base 365 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c struct nvkm_device *device = gr->base.engine.subdev.device; base 38 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c); base 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c struct nvkm_device *device = gr->base.engine.subdev.device; base 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c struct nvkm_device *device = gr->base.engine.subdev.device; base 60 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c struct nvkm_device *device = gr->base.engine.subdev.device; base 74 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c struct nvkm_device *device = gr->base.engine.subdev.device; base 136 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c *pgr = &gr->base; base 32 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c struct nvkm_device *device = gr->base.engine.subdev.device; base 60 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c struct nvkm_device *device = gr->base.engine.subdev.device; base 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 74 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 82 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 90 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x000f0002); base 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 32 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c struct nvkm_device *device = gr->base.engine.subdev.device; base 47 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; base 88 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c struct nvkm_device *device = gr->base.engine.subdev.device; base 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 65 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 77 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 84 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c struct nvkm_device *device = gr->base.engine.subdev.device; base 349 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c #define nv04_gr(p) container_of((p), struct nv04_gr, base) base 352 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_gr base; base 1074 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1087 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = chan->gr->base.engine.subdev.device; base 1102 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = chan->gr->base.engine.subdev.device; base 1116 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1121 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_idle(&gr->base); base 1165 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1184 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, base 1187 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nv04_gr *gr = nv04_gr(base); base 1272 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_intr(struct nvkm_gr *base) base 1274 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nv04_gr *gr = nv04_gr(base); base 1275 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1328 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_init(struct nvkm_gr *base) base 1330 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nv04_gr *gr = nv04_gr(base); base 1331 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1423 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c *pgr = &gr->base; base 1425 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c return nvkm_gr_ctor(&nv04_gr, device, index, true, &gr->base); base 389 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c #define nv10_gr(p) container_of((p), struct nv10_gr, base) base 392 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_gr base; base 434 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_gr *gr = &chan->gr->base; base 507 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_gr *gr = &chan->gr->base; base 549 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; base 564 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; base 583 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; base 587 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(&gr->base); base 612 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(&gr->base); base 626 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(&gr->base); base 633 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 788 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 801 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 815 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; base 886 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; base 913 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; base 934 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; base 939 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(&gr->base); base 958 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1002 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, base 1005 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); base 1007 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1049 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) base 1051 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); base 1052 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1057 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(&gr->base); base 1081 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_intr(struct nvkm_gr *base) base 1083 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); base 1084 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 1136 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_init(struct nvkm_gr *base) base 1138 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); base 1139 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; base 1183 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c *pgr = &gr->base; base 1185 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c return nvkm_gr_ctor(func, device, index, true, &gr->base); base 34 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nvkm_device *device = gr->base.engine.subdev.device; base 75 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nv20_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, base 78 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); base 89 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c ret = nvkm_memory_new(gr->base.engine.subdev.device, base 149 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) base 151 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); base 152 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nvkm_device *device = gr->base.engine.subdev.device; base 157 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nv04_gr_idle(&gr->base); base 180 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nv20_gr_intr(struct nvkm_gr *base) base 182 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); base 183 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 220 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nv20_gr_oneinit(struct nvkm_gr *base) base 222 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); base 223 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c return nvkm_memory_new(gr->base.engine.subdev.device, base 229 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nv20_gr_init(struct nvkm_gr *base) base 231 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); base 232 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nvkm_device *device = gr->base.engine.subdev.device; base 324 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nv20_gr_dtor(struct nvkm_gr *base) base 326 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); base 339 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c *pgr = &gr->base; base 341 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c return nvkm_gr_ctor(func, device, index, true, &gr->base); base 4 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h #define nv20_gr(p) container_of((p), struct nv20_gr, base) base 8 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h struct nvkm_gr base; base 21 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c nv25_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, base 24 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c struct nv20_gr *gr = nv20_gr(base); base 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c ret = nvkm_memory_new(gr->base.engine.subdev.device, base 21 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c nv2a_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, base 24 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c struct nv20_gr *gr = nv20_gr(base); base 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c ret = nvkm_memory_new(gr->base.engine.subdev.device, base 22 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c nv30_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, base 25 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c struct nv20_gr *gr = nv20_gr(base); base 36 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c ret = nvkm_memory_new(gr->base.engine.subdev.device, base 104 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c nv30_gr_init(struct nvkm_gr *base) base 106 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c struct nv20_gr *gr = nv20_gr(base); base 107 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c struct nvkm_device *device = gr->base.engine.subdev.device; base 21 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c nv34_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, base 24 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c struct nv20_gr *gr = nv20_gr(base); base 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c ret = nvkm_memory_new(gr->base.engine.subdev.device, base 21 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c nv35_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, base 24 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c struct nv20_gr *gr = nv20_gr(base); base 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c ret = nvkm_memory_new(gr->base.engine.subdev.device, base 79 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, base 84 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); base 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 134 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_lock_irqsave(&chan->gr->base.engine.lock, flags); base 136 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags); base 148 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nv40_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, base 151 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nv40_gr *gr = nv40_gr(base); base 162 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_lock_irqsave(&chan->gr->base.engine.lock, flags); base 164 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags); base 173 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) base 175 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nv40_gr *gr = nv40_gr(base); base 176 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nvkm_device *device = gr->base.engine.subdev.device; base 181 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nv04_gr_idle(&gr->base); base 232 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nv40_gr_intr(struct nvkm_gr *base) base 234 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nv40_gr *gr = nv40_gr(base); base 236 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 251 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_lock_irqsave(&gr->base.engine.lock, flags); base 283 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_unlock_irqrestore(&gr->base.engine.lock, flags); base 287 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nv40_gr_init(struct nvkm_gr *base) base 289 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nv40_gr *gr = nv40_gr(base); base 290 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nvkm_device *device = gr->base.engine.subdev.device; base 438 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c *pgr = &gr->base; base 441 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c return nvkm_gr_ctor(func, device, index, true, &gr->base); base 4 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h #define nv40_gr(p) container_of((p), struct nv40_gr, base) base 8 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h struct nvkm_gr base; base 31 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) base 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c struct nv40_gr *gr = nv40_gr(base); base 34 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c struct nvkm_device *device = gr->base.engine.subdev.device; base 39 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nv04_gr_idle(&gr->base); base 73 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, base 77 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); base 89 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, base 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nv50_gr *gr = nv50_gr(base); base 242 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 284 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 328 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 398 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 620 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_intr(struct nvkm_gr *base) base 622 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nv50_gr *gr = nv50_gr(base); base 623 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; base 679 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_init(struct nvkm_gr *base) base 681 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nv50_gr *gr = nv50_gr(base); base 682 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_device *device = gr->base.engine.subdev.device; base 771 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c *pgr = &gr->base; base 773 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c return nvkm_gr_ctor(func, device, index, true, &gr->base); base 4 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h #define nv50_gr(p) container_of((p), struct nv50_gr, base) base 8 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h struct nvkm_gr base; base 133 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); base 147 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nvkm_wr32(device, 0x00b334, base); base 154 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nvkm_wr32(device, 0x00b360, base); base 161 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c nvkm_wr32(device, 0x00b370, base); base 40 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); base 53 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c nvkm_wr32(device, 0x00b334, base); base 59 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c nvkm_wr32(device, 0x00b360, base); base 66 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c nvkm_wr32(device, 0x00b370, base); base 617 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c oclass->base.oclass = NVIF_CLASS_PERFDOM; base 618 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c oclass->base.minver = 0; base 619 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c oclass->base.maxver = 0; base 684 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c .base.oclass = NVIF_CLASS_PERFMON, base 685 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c .base.minver = -1, base 686 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c .base.maxver = -1, base 695 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c oclass->base = nvkm_pm_oclass.base; base 767 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c u32 base, u32 size_unit, u32 size_domain, base 776 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c u32 addr = base + (i * size_unit); base 856 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c .base.sclass = nvkm_pm_oclass_get, base 62 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c struct nv40_pm *nv40pm = container_of(pm, struct nv40_pm, base); base 90 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c *ppm = &pm->base; base 92 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c ret = nvkm_pm_ctor(&nv40_pm_, device, index, &pm->base); base 96 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c return nvkm_perfdom_new(&pm->base, "pc", 0, 0, 0, 4, doms); base 4 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h #define nv40_pm(p) container_of((p), struct nv40_pm, base) base 8 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h struct nvkm_pm base; base 67 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c oclass->base = sw->func->sclass[index].base; base 68 drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c oclass->base.ctor = nvkm_sw_oclass_new; base 43 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c struct nvkm_sw *sw = chan->base.sw; base 45 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c u32 inst = chan->base.fifo->inst->addr >> 12; base 57 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c gf100_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) base 59 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c struct nv50_sw_chan *chan = nv50_sw_chan(base); base 60 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c struct nvkm_engine *engine = chan->base.object.engine; base 115 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c *pobject = &chan->base.object; base 118 drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c &chan->base); base 24 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c #define nv04_sw_chan(p) container_of((p), struct nv04_sw_chan, base) base 35 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c struct nvkm_sw_chan base; base 88 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c nv04_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) base 90 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c struct nv04_sw_chan *chan = nv04_sw_chan(base); base 117 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c *pobject = &chan->base.object; base 119 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c return nvkm_sw_chan_ctor(&nv04_sw_chan, sw, fifo, oclass, &chan->base); base 43 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c struct nvkm_sw *sw = chan->base.sw; base 46 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c nvkm_wr32(device, 0x001704, chan->base.fifo->inst->addr >> 12); base 62 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c nv50_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) base 64 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c struct nv50_sw_chan *chan = nv50_sw_chan(base); base 65 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c struct nvkm_engine *engine = chan->base.object.engine; base 84 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c nv50_sw_chan_dtor(struct nvkm_sw_chan *base) base 86 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c struct nv50_sw_chan *chan = nv50_sw_chan(base); base 109 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c *pobject = &chan->base.object; base 111 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c ret = nvkm_sw_chan_ctor(&nv50_sw_chan, sw, fifoch, oclass, &chan->base); base 4 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h #define nv50_sw_chan(p) container_of((p), struct nv50_sw_chan, base) base 11 drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h struct nvkm_sw_chan base; base 14 drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h struct nvkm_sclass base; base 35 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c oclass->base = xtensa->func->sclass[index]; base 62 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c const u32 base = xtensa->addr; base 63 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c u32 unk104 = nvkm_rd32(device, base + 0xd04); base 64 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c u32 intr = nvkm_rd32(device, base + 0xc20); base 65 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c u32 chan = nvkm_rd32(device, base + 0xc28); base 66 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c u32 unk10c = nvkm_rd32(device, base + 0xd0c); base 70 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xc20, intr); base 71 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c intr = nvkm_rd32(device, base + 0xc20); base 83 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c const u32 base = xtensa->addr; base 85 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */ base 86 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */ base 99 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c const u32 base = xtensa->addr; base 140 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xd10, 0x1fffffff); /* ?? */ base 141 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xd08, 0x0fffffff); /* ?? */ base 143 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xd28, xtensa->func->unkd28); /* ?? */ base 144 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */ base 145 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */ base 147 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xcc0, addr >> 8); /* XT_REGION_BASE */ base 148 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xcc4, 0x1c); /* XT_REGION_SETUP */ base 149 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xcc8, size >> 8); /* XT_REGION_LIMIT */ base 152 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xde0, tmp); /* SCRATCH_H2X */ base 154 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xce8, 0xf); /* XT_REGION_SETUP */ base 156 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */ base 157 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */ base 39 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c struct nvkm_msgqueue base; base 44 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c container_of(q, struct msgqueue_0137c63d, base) base 47 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c struct msgqueue_0137c63d base; base 52 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c container_of(container_of(q, struct msgqueue_0137c63d, base), \ base 53 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c struct msgqueue_0137bca5, base); base 60 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c const struct nvkm_subdev *subdev = priv->base.falcon->owner; base 80 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c nvkm_msgqueue_process_msgs(&priv->base, q_queue); base 124 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c struct nvkm_msgqueue_msg base; base 142 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c if (init->base.hdr.unit_id != MSGQUEUE_0137C63D_UNIT_INIT) { base 147 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c if (init->base.msg_type != INIT_MSG_INIT) { base 175 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c return acr_init_wpr(&priv->base); base 200 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c struct nvkm_msgqueue_msg base; base 248 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c struct nvkm_msgqueue_msg base; base 304 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c struct nvkm_msgqueue_msg base; base 399 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c *queue = &ret->base; base 401 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c nvkm_msgqueue_ctor(&msgqueue_0137c63d_func, falcon, &ret->base); base 425 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c *queue = &ret->base.base; base 433 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c nvkm_msgqueue_ctor(&msgqueue_0137bca5_func, falcon, &ret->base.base); base 40 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c struct nvkm_msgqueue base; base 45 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c container_of(q, struct msgqueue_0148cdec, base) base 63 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c nvkm_msgqueue_process_msgs(&priv->base, q_queue); base 93 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c struct nvkm_msgqueue_msg base; base 111 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c if (init->base.hdr.unit_id != MSGQUEUE_0148CDEC_UNIT_INIT) { base 116 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c if (init->base.msg_type != INIT_MSG_INIT) { base 169 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c struct nvkm_msgqueue_msg base; base 259 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c *queue = &ret->base; base 261 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c nvkm_msgqueue_ctor(&msgqueue_0148cdec_func, falcon, &ret->base); base 32 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c gf100_bar_bar1_vmm(struct nvkm_bar *base) base 34 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c return gf100_bar(base)->bar[1].vmm; base 38 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c gf100_bar_bar1_wait(struct nvkm_bar *base) base 41 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c nvkm_bar_flush(base); base 42 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c nvkm_bar_flush(base); base 52 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c gf100_bar_bar1_init(struct nvkm_bar *base) base 54 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c struct nvkm_device *device = base->subdev.device; base 55 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c struct gf100_bar *bar = gf100_bar(base); base 61 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c gf100_bar_bar2_vmm(struct nvkm_bar *base) base 63 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c return gf100_bar(base)->bar[0].vmm; base 73 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c gf100_bar_bar2_init(struct nvkm_bar *base) base 75 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c struct nvkm_device *device = base->subdev.device; base 76 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c struct gf100_bar *bar = gf100_bar(base); base 87 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c struct nvkm_device *device = bar->base.subdev.device; base 108 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c bar_vm->vmm->debug = bar->base.subdev.debug; base 123 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c gf100_bar_oneinit(struct nvkm_bar *base) base 127 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c struct gf100_bar *bar = gf100_bar(base); base 131 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c if (bar->base.func->bar2.init) { base 136 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c bar->base.subdev.oneinit = true; base 137 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c nvkm_bar_bar2_init(bar->base.subdev.device); base 149 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c gf100_bar_dtor(struct nvkm_bar *base) base 151 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c struct gf100_bar *bar = gf100_bar(base); base 170 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c nvkm_bar_ctor(func, device, index, &bar->base); base 172 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c *pbar = &bar->base; base 4 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h #define gf100_bar(p) container_of((p), struct gf100_bar, base) base 13 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h struct nvkm_bar base; base 32 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nv50_bar_flush(struct nvkm_bar *base) base 34 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c struct nv50_bar *bar = nv50_bar(base); base 35 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c struct nvkm_device *device = bar->base.subdev.device; base 37 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c spin_lock_irqsave(&bar->base.lock, flags); base 43 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c spin_unlock_irqrestore(&bar->base.lock, flags); base 47 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nv50_bar_bar1_vmm(struct nvkm_bar *base) base 49 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c return nv50_bar(base)->bar1_vmm; base 53 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nv50_bar_bar1_wait(struct nvkm_bar *base) base 55 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_bar_flush(base); base 65 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nv50_bar_bar1_init(struct nvkm_bar *base) base 67 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c struct nvkm_device *device = base->subdev.device; base 68 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c struct nv50_bar *bar = nv50_bar(base); base 73 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nv50_bar_bar2_vmm(struct nvkm_bar *base) base 75 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c return nv50_bar(base)->bar2_vmm; base 85 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nv50_bar_bar2_init(struct nvkm_bar *base) base 87 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c struct nvkm_device *device = base->subdev.device; base 88 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c struct nv50_bar *bar = nv50_bar(base); base 95 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nv50_bar_init(struct nvkm_bar *base) base 97 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c struct nv50_bar *bar = nv50_bar(base); base 98 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c struct nvkm_device *device = bar->base.subdev.device; base 106 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nv50_bar_oneinit(struct nvkm_bar *base) base 108 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c struct nv50_bar *bar = nv50_bar(base); base 109 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c struct nvkm_device *device = bar->base.subdev.device; base 141 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c bar->bar2_vmm->debug = bar->base.subdev.debug; base 165 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c bar->base.subdev.oneinit = true; base 181 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c bar->bar1_vmm->debug = bar->base.subdev.debug; base 204 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nv50_bar_dtor(struct nvkm_bar *base) base 206 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c struct nv50_bar *bar = nv50_bar(base); base 228 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c nvkm_bar_ctor(func, device, index, &bar->base); base 230 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c *pbar = &bar->base; base 4 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h #define nv50_bar(p) container_of((p), struct nv50_bar, base) base 8 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h struct nvkm_bar base; base 44 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c tu102_bar_bar2_init(struct nvkm_bar *base) base 46 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c struct nvkm_device *device = base->subdev.device; base 47 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c struct gf100_bar *bar = gf100_bar(base); base 71 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c tu102_bar_bar1_init(struct nvkm_bar *base) base 73 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c struct nvkm_device *device = base->subdev.device; base 74 drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.c struct gf100_bar *bar = gf100_bar(base); base 165 drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c bios->imaged_addr = image.base; base 39 drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c switch ((data = nvbios_rd16(bios, image->base + 0x00))) { base 46 drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c image->base, data); base 50 drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c if (!(data = nvbios_pcirTp(bios, image->base, &ver, &hdr, &pcir))) base 57 drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c if (!(data = nvbios_npdeTp(bios, image->base, &npde))) base 75 drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.c image->base += image->size; base 1151 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 base = nvbios_rd08(bios, init->offset + 3); base 1162 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("\t\t[0x%02x] = 0x%02x\n", base, data); base 1165 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wrvgai(init, 0x03d4, addr0, base++); base 1284 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 base = nvbios_rd32(bios, init->offset + 1); base 1293 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("\t\tR[0x%06x] = 0x%08x\n", base, data); base 1296 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(init, base, data); base 1297 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c base += 4; base 29 drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c nvbios_npdeTe(struct nvkm_bios *bios, u32 base) base 33 drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c u32 data = nvbios_pcirTp(bios, base, &ver, &hdr, &pcir); base 50 drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c nvbios_npdeTp(struct nvkm_bios *bios, u32 base, struct nvbios_npdeT *info) base 52 drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.c u32 data = nvbios_npdeTe(bios, base); base 28 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c nvbios_pcirTe(struct nvkm_bios *bios, u32 base, u8 *ver, u16 *hdr) base 30 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c u32 data = nvbios_rd16(bios, base + 0x18); base 32 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c data += base; base 52 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c nvbios_pcirTp(struct nvkm_bios *bios, u32 base, u8 *ver, u16 *hdr, base 55 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.c u32 data = nvbios_pcirTe(bios, base, ver, hdr); base 59 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c image.base = 0; base 76 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c image.base, image.type, image.size); base 79 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c nvkm_debug(subdev, "%08x: fetch failed\n", image.base); base 86 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c nvbios_checksum(&bios->data[image.base], image.size)) { base 88 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c image.base); base 92 drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c info->base = nvbios_rd32(bios, volt + 0x04); base 96 drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c info->min = min(info->base, base 97 drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c info->base + info->step * info->vidmask); base 100 drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c info->max = max(info->base, info->base + info->step * info->vidmask); base 105 drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c info->base = nvbios_rd32(bios, volt + 0x12) & 0x00ffffff; base 173 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c cstate = &pstate->base; base 186 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c pstate->base.voltage, clk->temp, +1); base 201 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c pstate->base.voltage, clk->temp, -1); base 244 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c *cstate = pstate->base; base 285 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c int khz = pstate->base.domain[nv_clk_src_mem]; base 358 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c u32 lo = pstate->base.domain[clock->name]; base 419 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c cstate = &pstate->base; base 607 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c clk->bstate.base.domain[clock->name] = ret; base 663 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c struct nvbios_vpstate_entry base, boost; base 666 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c if (!nvbios_vpstate_entry(bios, &h, h.base_id, &base)) base 667 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c clk->base_khz = base.clock_mhz * 1000; base 24 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c #define gf100_clk(p) container_of((p), struct gf100_clk, base) base 42 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_clk base; base 51 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_device *device = clk->base.subdev.device; base 54 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); base 55 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); base 61 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_device *device = clk->base.subdev.device; base 79 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); base 82 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); base 100 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_device *device = clk->base.subdev.device; base 135 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_device *device = clk->base.subdev.device; base 158 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c gf100_clk_read(struct nvkm_clk *base, enum nv_clk_src src) base 160 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct gf100_clk *clk = gf100_clk(base); base 161 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_subdev *subdev = &clk->base.subdev; base 184 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return nvkm_clk_read(&clk->base, nv_clk_src_mpll); base 185 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return nvkm_clk_read(&clk->base, nv_clk_src_mdiv); base 252 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_subdev *subdev = &clk->base.subdev; base 325 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c gf100_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) base 327 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct gf100_clk *clk = gf100_clk(base); base 347 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_device *device = clk->base.subdev.device; base 357 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_device *device = clk->base.subdev.device; base 369 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_device *device = clk->base.subdev.device; base 396 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_device *device = clk->base.subdev.device; base 411 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct nvkm_device *device = clk->base.subdev.device; base 416 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c gf100_clk_prog(struct nvkm_clk *base) base 418 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct gf100_clk *clk = gf100_clk(base); base 442 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c gf100_clk_tidy(struct nvkm_clk *base) base 444 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c struct gf100_clk *clk = gf100_clk(base); base 477 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c *pclk = &clk->base; base 479 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return nvkm_clk_ctor(&gf100_clk, device, index, false, &clk->base); base 24 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c #define gk104_clk(p) container_of((p), struct gk104_clk, base) base 42 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_clk base; base 52 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 62 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 108 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 135 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 147 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 189 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c gk104_clk_read(struct nvkm_clk *base, enum nv_clk_src src) base 191 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct gk104_clk *clk = gk104_clk(base); base 192 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_subdev *subdev = &clk->base.subdev; base 265 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_subdev *subdev = &clk->base.subdev; base 339 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c gk104_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) base 341 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct gk104_clk *clk = gk104_clk(base); base 360 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 370 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 381 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 389 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 414 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 425 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 440 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct nvkm_device *device = clk->base.subdev.device; base 448 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c gk104_clk_prog(struct nvkm_clk *base) base 450 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct gk104_clk *clk = gk104_clk(base); base 479 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c gk104_clk_tidy(struct nvkm_clk *base) base 481 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c struct gk104_clk *clk = gk104_clk(base); base 513 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c *pclk = &clk->base; base 515 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c return nvkm_clk_ctor(&gk104_clk, device, index, true, &clk->base); base 67 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct nvkm_device *device = clk->base.subdev.device; base 79 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct nvkm_device *device = clk->base.subdev.device; base 104 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct nvkm_subdev *subdev = &clk->base.subdev; base 213 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct nvkm_subdev *subdev = &clk->base.subdev; base 258 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct nvkm_device *device = clk->base.subdev.device; base 286 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct nvkm_device *device = clk->base.subdev.device; base 298 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct nvkm_subdev *subdev = &clk->base.subdev; base 368 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 374 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 380 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 386 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 392 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 398 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 404 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 410 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 416 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 422 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 428 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 434 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 440 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 446 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 452 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c .base = { base 460 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src) base 462 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct gk20a_clk *clk = gk20a_clk(base); base 463 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct nvkm_subdev *subdev = &clk->base.subdev; base 480 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) base 482 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct gk20a_clk *clk = gk20a_clk(base); base 489 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_clk_prog(struct nvkm_clk *base) base 491 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct gk20a_clk *clk = gk20a_clk(base); base 502 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_clk_tidy(struct nvkm_clk *base) base 509 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct nvkm_subdev *subdev = &clk->base.subdev; base 543 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_clk_fini(struct nvkm_clk *base) base 545 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct nvkm_device *device = base->subdev.device; base 546 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct gk20a_clk *clk = gk20a_clk(base); base 565 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_clk_init(struct nvkm_clk *base) base 567 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct gk20a_clk *clk = gk20a_clk(base); base 568 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct nvkm_subdev *subdev = &clk->base.subdev; base 585 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c base->func->calc(base, &base->func->pstates[0].base); base 586 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c ret = base->func->prog(&clk->base); base 631 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c ret = nvkm_clk_ctor(func, device, index, true, &clk->base); base 635 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c nvkm_debug(&clk->base.subdev, "parent clock rate: %d Khz\n", base 650 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c *pclk = &clk->base; base 117 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h struct nvkm_clk base; base 125 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define gk20a_clk(p) container_of((p), struct gk20a_clk, base) base 135 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h struct nvkm_device *device = clk->base.subdev.device; base 109 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct gk20a_pll base; base 121 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct gk20a_clk base; base 139 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c #define gm20b_clk(p) container_of((gk20a_clk(p)), struct gm20b_clk, base) base 162 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_subdev *subdev = &clk->base.base.subdev; base 166 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gk20a_pllg_read_mnp(&clk->base, &pll->base); base 175 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_device *device = clk->base.base.subdev.device; base 179 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gk20a_pllg_write_mnp(&clk->base, &pll->base); base 192 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_subdev *subdev = &clk->base.base.subdev; base 227 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_subdev *subdev = &clk->base.base.subdev; base 228 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c const struct gk20a_clk_pllg_params *p = clk->base.params; base 268 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_subdev *subdev = &clk->base.base.subdev; base 280 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c if (n_int == pll.base.n && sdm_din == pll.sdm_din) base 292 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c pll.base.n = n_int; base 294 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gk20a_pllg_write_mnp(&clk->base, &pll.base); base 324 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_device *device = clk->base.base.subdev.device; base 347 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_device *device = clk->base.base.subdev.device; base 362 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_subdev *subdev = &clk->base.base.subdev; base 372 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c pdiv_only = cur_pll.base.n == n_int && cur_pll.sdm_din == sdm_din && base 373 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_pll.base.m == pll->m; base 376 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c if (!gk20a_pllg_is_enabled(&clk->base)) base 389 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c u32 old = cur_pll.base.pl; base 399 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_pll.base.pl = min(old | BIT(ffs(new) - 1), base 401 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gk20a_pllg_write_mnp(&clk->base, &cur_pll.base); base 404 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_pll.base.pl = new; base 405 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gk20a_pllg_write_mnp(&clk->base, &cur_pll.base); base 410 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_pll.base = *pll; base 411 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_pll.base.n = n_int; base 438 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c if (gk20a_pllg_is_enabled(&clk->base)) { base 439 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gk20a_pllg_read_mnp(&clk->base, &cur_pll); base 446 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_pll.n = gk20a_pllg_n_lo(&clk->base, &cur_pll); base 454 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_pll.n = gk20a_pllg_n_lo(&clk->base, &cur_pll); base 464 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) base 466 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct gm20b_clk *clk = gm20b_clk(base); base 467 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_subdev *subdev = &base->subdev; base 468 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_volt *volt = base->subdev.device->volt; base 471 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c ret = gk20a_pllg_calc_mnp(&clk->base, cstate->domain[nv_clk_src_gpc] * base 490 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c u32 rate = gk20a_pllg_calc_rate(&clk->base, pll) / KHZ; base 491 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c u32 parent_rate = clk->base.parent_rate / KHZ; base 501 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nmin = DIV_ROUND_UP(pll->m * clk->base.params->min_vco, parent_rate); base 502 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nsafe = pll->m * rate / (clk->base.parent_rate); base 515 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_device *device = clk->base.base.subdev.device; base 533 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_device *device = clk->base.base.subdev.device; base 552 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_device *device = clk->base.base.subdev.device; base 572 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_clk_prog(struct nvkm_clk *base) base 574 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct gm20b_clk *clk = gm20b_clk(base); base 601 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_freq = nvkm_clk_read(&clk->base.base, nv_clk_src_gpc); base 607 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c pll_safe = clk->base.pll; base 632 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c clk->base.pll = clk->new_pll; base 634 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c return gm20b_pllg_program_mnp_slide(clk, &clk->base.pll); base 640 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 646 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 652 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 658 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 664 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 670 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 676 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 682 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 688 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 694 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 700 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 706 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 712 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c .base = { base 720 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_clk_fini(struct nvkm_clk *base) base 722 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_device *device = base->subdev.device; base 723 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct gm20b_clk *clk = gm20b_clk(base); base 726 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c if (gk20a_pllg_is_enabled(&clk->base)) { base 730 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gk20a_pllg_read_mnp(&clk->base, &pll); base 731 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c n_lo = gk20a_pllg_n_lo(&clk->base, &pll); base 744 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_subdev *subdev = &clk->base.base.subdev; base 811 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_clk_init(struct nvkm_clk *base) base 813 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct gk20a_clk *clk = gk20a_clk(base); base 814 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_subdev *subdev = &clk->base.subdev; base 851 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c if (clk->base.func == &gm20b_clk) { base 852 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct gm20b_clk *_clk = gm20b_clk(base); base 865 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c base->func->calc(base, &base->func->pstates[0].base); base 866 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c ret = base->func->prog(base); base 920 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c *pclk = &clk->base; base 947 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_subdev *subdev = &clk->base.base.subdev; base 981 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_subdev *subdev = &clk->base.base.subdev; base 983 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct nvkm_pstate *pstates = clk->base.base.func->pstates; base 984 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c int nr_pstates = clk->base.base.func->nr_pstates; base 1000 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c if (pstates[i].base.voltage == id) base 1002 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c pstates[i].base.domain[nv_clk_src_gpc]); base 1033 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c *pclk = &clk->base.base; base 1034 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c subdev = &clk->base.base.subdev; base 1040 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c &clk->base); base 1049 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c (clk->base.parent_rate / KHZ)); base 1056 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c clk->base.pl_to_div = pl_to_div; base 1057 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c clk->base.div_to_pl = div_to_pl; base 25 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c #define gt215_clk(p) container_of((p), struct gt215_clk, base) base 35 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct nvkm_clk base; base 45 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct nvkm_device *device = clk->base.subdev.device; base 63 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct nvkm_device *device = clk->base.subdev.device; base 110 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct nvkm_device *device = clk->base.subdev.device; base 143 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c gt215_clk_read(struct nvkm_clk *base, enum nv_clk_src src) base 145 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct gt215_clk *clk = gt215_clk(base); base 146 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct nvkm_subdev *subdev = &clk->base.subdev; base 187 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c gt215_clk_info(struct nvkm_clk *base, int idx, u32 khz, base 190 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct gt215_clk *clk = gt215_clk(base); base 235 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz, base 238 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct gt215_clk *clk = gt215_clk(base); base 239 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct nvkm_subdev *subdev = &clk->base.subdev; base 248 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c ret = gt215_clk_info(&clk->base, idx, khz, info); base 259 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c ret = gt215_clk_info(&clk->base, idx - 0x10, limits.refclk, info); base 277 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c int ret = gt215_pll_info(&clk->base, idx, pll, cstate->domain[dom], base 299 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c ret = gt215_clk_info(&clk->base, 0x1d, kHz, info); base 357 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct nvkm_device *device = clk->base.subdev.device; base 366 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct nvkm_device *device = clk->base.subdev.device; base 410 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct nvkm_device *device = clk->base.subdev.device; base 418 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct nvkm_device *device = clk->base.subdev.device; base 446 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct nvkm_device *device = clk->base.subdev.device; base 459 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c gt215_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) base 461 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct gt215_clk *clk = gt215_clk(base); base 475 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c ret = gt215_clk_info(&clk->base, 0x10, base 486 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c gt215_clk_prog(struct nvkm_clk *base) base 488 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c struct gt215_clk *clk = gt215_clk(base); base 494 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c ret = gt215_clk_pre(&clk->base, f); base 511 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c gt215_clk_post(&clk->base, f); base 516 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c gt215_clk_tidy(struct nvkm_clk *base) base 546 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c *pclk = &clk->base; base 548 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c return nvkm_clk_ctor(>215_clk, device, index, true, &clk->base); base 24 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c #define mcp77_clk(p) container_of((p), struct mcp77_clk, base) base 33 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c struct nvkm_clk base; base 44 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c struct nvkm_device *device = clk->base.subdev.device; base 49 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c read_pll(struct mcp77_clk *clk, u32 base) base 51 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c struct nvkm_device *device = clk->base.subdev.device; base 52 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c u32 ctrl = nvkm_rd32(device, base + 0); base 53 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c u32 coef = nvkm_rd32(device, base + 4); base 54 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); base 59 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c switch (base){ base 81 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src) base 83 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c struct mcp77_clk *clk = mcp77_clk(base); base 84 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c struct nvkm_subdev *subdev = &clk->base.subdev; base 95 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; base 97 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3; base 100 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); base 102 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00080000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); base 103 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x000c0000: return nvkm_clk_read(&clk->base, nv_clk_src_cclk); base 110 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; base 112 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000002: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4) >> P; base 118 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_core); base 121 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_core); base 124 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); base 125 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000400: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); base 126 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c case 0x00000800: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); base 134 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P; base 135 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; base 149 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; base 168 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c struct nvkm_subdev *subdev = &clk->base.subdev; base 177 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c pll.refclk = nvkm_clk_read(&clk->base, nv_clk_src_href); base 203 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c mcp77_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) base 205 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c struct mcp77_clk *clk = mcp77_clk(base); base 209 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c struct nvkm_subdev *subdev = &clk->base.subdev; base 215 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c if (core < nvkm_clk_read(&clk->base, nv_clk_src_hclkm4)) base 216 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs); base 242 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c if (shader == nvkm_clk_read(&clk->base, nv_clk_src_href)) { base 299 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c mcp77_clk_prog(struct nvkm_clk *base) base 301 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c struct mcp77_clk *clk = mcp77_clk(base); base 302 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c struct nvkm_subdev *subdev = &clk->base.subdev; base 309 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c ret = gt215_clk_pre(&clk->base, f); base 389 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c gt215_clk_post(&clk->base, f); base 394 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c mcp77_clk_tidy(struct nvkm_clk *base) base 421 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c *pclk = &clk->base; base 423 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nvkm_clk_ctor(&mcp77_clk, device, index, true, &clk->base); base 24 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c #define nv40_clk(p) container_of((p), struct nv40_clk, base) base 32 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nvkm_clk base; base 42 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nvkm_device *device = clk->base.subdev.device; base 58 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nvkm_device *device = clk->base.subdev.device; base 97 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c nv40_clk_read(struct nvkm_clk *base, enum nv_clk_src src) base 99 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nv40_clk *clk = nv40_clk(base); base 100 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nvkm_subdev *subdev = &clk->base.subdev; base 127 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nvkm_subdev *subdev = &clk->base.subdev; base 146 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c nv40_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) base 148 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nv40_clk *clk = nv40_clk(base); base 186 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c nv40_clk_prog(struct nvkm_clk *base) base 188 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nv40_clk *clk = nv40_clk(base); base 189 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nvkm_device *device = clk->base.subdev.device; base 227 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c clk->base.pll_calc = nv04_clk_pll_calc; base 228 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c clk->base.pll_prog = nv04_clk_pll_prog; base 229 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c *pclk = &clk->base; base 231 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c return nvkm_clk_ctor(&nv40_clk, device, index, true, &clk->base); base 34 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nvkm_device *device = clk->base.subdev.device; base 52 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c read_pll_src(struct nv50_clk *clk, u32 base) base 54 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nvkm_subdev *subdev = &clk->base.subdev; base 56 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); base 63 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c switch (base) { base 69 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c nvkm_error(subdev, "ref: bad pll %06x\n", base); base 91 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c switch (base) { base 97 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c nvkm_error(subdev, "ref: bad pll %06x\n", base); base 103 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); base 104 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href); base 125 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c read_pll_ref(struct nv50_clk *clk, u32 base) base 127 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nvkm_subdev *subdev = &clk->base.subdev; base 131 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c switch (base) { base 145 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_crystal); base 147 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c nvkm_error(subdev, "bad pll %06x\n", base); base 152 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_href); base 154 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return read_pll_src(clk, base); base 158 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c read_pll(struct nv50_clk *clk, u32 base) base 160 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nvkm_device *device = clk->base.subdev.device; base 162 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c u32 ctrl = nvkm_rd32(device, base + 0); base 163 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c u32 coef = nvkm_rd32(device, base + 4); base 164 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c u32 ref = read_pll_ref(clk, base); base 168 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c if (base == 0x004028 && (mast & 0x00100000)) { base 171 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_dom6); base 192 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c nv50_clk_read(struct nvkm_clk *base, enum nv_clk_src src) base 194 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nv50_clk *clk = nv50_clk(base); base 195 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nvkm_subdev *subdev = &clk->base.subdev; base 206 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return div_u64((u64)nvkm_clk_read(&clk->base, nv_clk_src_href) * 27778, 10000); base 208 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3; base 210 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3 / 2; base 213 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); base 216 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk); base 223 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; base 224 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6); base 234 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_host) >> P; base 235 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; base 246 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; base 249 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P; base 267 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; base 268 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; base 276 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; base 282 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; base 286 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2) >> P; base 288 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_mem) >> P; base 306 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); base 308 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk); base 310 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3) >> P; base 327 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nvkm_subdev *subdev = &clk->base.subdev; base 368 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c nv50_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) base 370 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nv50_clk *clk = nv50_clk(base); base 372 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nvkm_subdev *subdev = &clk->base.subdev; base 405 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c out = nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2); base 426 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_href))) { base 429 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_hclk))) { base 432 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c freq = nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3; base 495 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c nv50_clk_prog(struct nvkm_clk *base) base 497 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nv50_clk *clk = nv50_clk(base); base 502 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c nv50_clk_tidy(struct nvkm_clk *base) base 504 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nv50_clk *clk = nv50_clk(base); base 517 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c ret = nvkm_clk_ctor(func, device, index, allow_reclock, &clk->base); base 518 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c *pclk = &clk->base; base 4 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h #define nv50_clk(p) container_of((p), struct nv50_clk, base) base 10 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h struct hwsq base; base 19 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h struct nvkm_clk base; base 6 drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h #define clk_init(s,p) hwsq_init(&(s)->base, (p)) base 7 drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h #define clk_exec(s,e) hwsq_exec(&(s)->base, (e)) base 9 drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h #define clk_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r) base 10 drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h #define clk_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d)) base 11 drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h #define clk_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) base 12 drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h #define clk_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) base 13 drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h #define clk_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) base 14 drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h #define clk_nsec(s,n) hwsq_nsec(&(s)->base, (n)) base 94 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c gf100_devinit_preinit(struct nvkm_devinit *base) base 96 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c struct nv50_devinit *init = nv50_devinit(base); base 97 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c struct nvkm_subdev *subdev = &init->base.subdev; base 104 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c base->post = ((nvkm_rd32(device, 0x2240c) & BIT(1)) == 0); base 34 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c struct nvkm_device *device = init->base.subdev.device; base 54 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c struct nvkm_device *device = init->base.subdev.device; base 66 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c struct nvkm_device *device = init->base.subdev.device; base 75 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c struct nvkm_device *device = init->base.subdev.device; base 85 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c struct nvkm_subdev *subdev = &init->base.subdev; base 118 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c gm200_devinit_post(struct nvkm_devinit *base, bool post) base 120 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c struct nv50_devinit *init = nv50_devinit(base); base 121 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c struct nvkm_subdev *subdev = &init->base.subdev; base 102 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c gt215_devinit_mmio(struct nvkm_devinit *base, u32 addr) base 104 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c struct nv50_devinit *init = nv50_devinit(base); base 105 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c struct nvkm_device *device = init->base.subdev.device; base 400 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nv04_devinit_preinit(struct nvkm_devinit *base) base 402 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c struct nv04_devinit *init = nv04_devinit(base); base 403 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c struct nvkm_subdev *subdev = &init->base.subdev; base 414 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c if (!init->base.post) { base 422 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c init->base.post = true; base 428 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nv04_devinit_dtor(struct nvkm_devinit *base) base 430 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c struct nv04_devinit *init = nv04_devinit(base); base 432 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_wrvgaowner(init->base.subdev.device, init->owner); base 445 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c *pinit = &init->base; base 447 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_devinit_ctor(func, device, index, &init->base); base 4 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h #define nv04_devinit(p) container_of((p), struct nv04_devinit, base) base 9 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h struct nvkm_devinit base; base 94 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c nv50_devinit_preinit(struct nvkm_devinit *base) base 96 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c struct nvkm_subdev *subdev = &base->subdev; base 103 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c if (!base->post) { base 104 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c u64 disable = nvkm_devinit_disable(base); base 106 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c base->post = true; base 112 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c if (!base->post) { base 116 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c base->post = true; base 122 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c nv50_devinit_init(struct nvkm_devinit *base) base 124 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c struct nv50_devinit *init = nv50_devinit(base); base 125 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c struct nvkm_subdev *subdev = &init->base.subdev; base 137 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c while (init->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) { base 159 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c *pinit = &init->base; base 161 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c nvkm_devinit_ctor(func, device, index, &init->base); base 4 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h #define nv50_devinit(p) container_of((p), struct nv50_devinit, base) base 8 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h struct nvkm_devinit base; base 69 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c tu102_devinit_post(struct nvkm_devinit *base, bool post) base 71 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c struct nv50_devinit *init = nv50_devinit(base); base 181 drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c fault->user.base = func->user.base; base 42 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 base = get * buffer->fault->func->buffer.entry_size; base 43 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 instlo = nvkm_ro32(mem, base + 0x00); base 44 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 insthi = nvkm_ro32(mem, base + 0x04); base 45 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 addrlo = nvkm_ro32(mem, base + 0x08); base 46 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 addrhi = nvkm_ro32(mem, base + 0x0c); base 47 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 timelo = nvkm_ro32(mem, base + 0x10); base 48 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 timehi = nvkm_ro32(mem, base + 0x14); base 49 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 info0 = nvkm_ro32(mem, base + 0x18); base 50 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 info1 = nvkm_ro32(mem, base + 0x1c); base 38 drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h struct nvkm_sclass base; base 32 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c gf100_fb_intr(struct nvkm_fb *base) base 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c struct gf100_fb *fb = gf100_fb(base); base 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c struct nvkm_subdev *subdev = &fb->base.subdev; base 45 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c gf100_fb_oneinit(struct nvkm_fb *base) base 47 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c struct gf100_fb *fb = gf100_fb(base); base 48 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c struct nvkm_device *device = fb->base.subdev.device; base 49 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c int ret, size = 1 << (fb->base.page ? fb->base.page : 17); base 55 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c true, &fb->base.mmu_rd); base 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c true, &fb->base.mmu_wr); base 89 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c gf100_fb_init(struct nvkm_fb *base) base 91 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c struct gf100_fb *fb = gf100_fb(base); base 92 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c struct nvkm_device *device = fb->base.subdev.device; base 97 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c if (base->func->clkgate_pack) { base 99 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c base->func->clkgate_pack); base 104 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c gf100_fb_dtor(struct nvkm_fb *base) base 106 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c struct gf100_fb *fb = gf100_fb(base); base 107 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c struct nvkm_device *device = fb->base.subdev.device; base 126 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c nvkm_fb_ctor(func, device, index, &fb->base); base 127 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c *pfb = &fb->base; base 4 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h #define gf100_fb(p) container_of((p), struct gf100_fb, base) base 8 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h struct nvkm_fb base; base 21 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h void gm200_fb_init(struct nvkm_fb *base); base 44 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c gm200_fb_init(struct nvkm_fb *base) base 46 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c struct gf100_fb *fb = gf100_fb(base); base 47 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c struct nvkm_device *device = fb->base.subdev.device; base 52 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(fb->base.mmu_wr) >> 8); base 53 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(fb->base.mmu_rd) >> 8); base 55 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.c min(nvkm_memory_size(fb->base.mmu_rd) >> 16, (u64)2) << 17); base 30 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c gp100_fb_init_unkn(struct nvkm_fb *base) base 32 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c struct nvkm_device *device = gf100_fb(base)->base.subdev.device; base 48 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c gp100_fb_init(struct nvkm_fb *base) base 50 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c struct gf100_fb *fb = gf100_fb(base); base 51 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c struct nvkm_device *device = fb->base.subdev.device; base 56 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(fb->base.mmu_wr) >> 8); base 57 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(fb->base.mmu_rd) >> 8); base 59 drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.c min(nvkm_memory_size(fb->base.mmu_rd) >> 16, (u64)2) << 17); base 32 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c nv50_fb_ram_new(struct nvkm_fb *base, struct nvkm_ram **pram) base 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c struct nv50_fb *fb = nv50_fb(base); base 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c return fb->func->ram_new(&fb->base, pram); base 135 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c nv50_fb_intr(struct nvkm_fb *base) base 137 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c struct nv50_fb *fb = nv50_fb(base); base 138 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c struct nvkm_subdev *subdev = &fb->base.subdev; base 196 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c nv50_fb_oneinit(struct nvkm_fb *base) base 198 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c struct nv50_fb *fb = nv50_fb(base); base 199 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c struct nvkm_device *device = fb->base.subdev.device; base 213 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c nv50_fb_init(struct nvkm_fb *base) base 215 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c struct nv50_fb *fb = nv50_fb(base); base 216 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c struct nvkm_device *device = fb->base.subdev.device; base 230 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c nv50_fb_tags(struct nvkm_fb *base) base 232 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c struct nv50_fb *fb = nv50_fb(base); base 234 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c return fb->func->tags(&fb->base); base 239 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c nv50_fb_dtor(struct nvkm_fb *base) base 241 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c struct nv50_fb *fb = nv50_fb(base); base 242 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c struct nvkm_device *device = fb->base.subdev.device; base 271 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c nvkm_fb_ctor(&nv50_fb_, device, index, &fb->base); base 273 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c *pfb = &fb->base; base 4 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h #define nv50_fb(p) container_of((p), struct nv50_fb, base) base 9 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h struct nvkm_fb base; base 164 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_init(s,p) ramfuc_init(&(s)->base, (p)) base 165 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_exec(s,e) ramfuc_exec(&(s)->base, (e)) base 167 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_rd32(s,r) ramfuc_rd32(&(s)->base, &(s)->r_##r) base 168 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_wr32(s,r,d) ramfuc_wr32(&(s)->base, &(s)->r_##r, (d)) base 169 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_nuke(s,r) ramfuc_nuke(&(s)->base, &(s)->r_##r) base 170 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_mask(s,r,m,d) ramfuc_mask(&(s)->base, &(s)->r_##r, (m), (d)) base 171 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n)) base 172 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_nsec(s,n) ramfuc_nsec(&(s)->base, (n)) base 173 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_wait_vblank(s) ramfuc_wait_vblank(&(s)->base) base 174 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_train(s) ramfuc_train(&(s)->base) base 176 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_block(s) ramfuc_block(&(s)->base) base 177 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h #define ram_unblock(s) ramfuc_unblock(&(s)->base) base 24 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c #define gf100_ram(p) container_of((p), struct gf100_ram, base) base 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c struct ramfuc base; base 100 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c struct nvkm_ram base; base 110 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c struct nvkm_fb *fb = ram->base.fb; base 127 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c gf100_ram_calc(struct nvkm_ram *base, u32 freq) base 129 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c struct gf100_ram *ram = gf100_ram(base); base 131 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c struct nvkm_subdev *subdev = &ram->base.fb->subdev; base 180 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c ret = ram_init(fuc, ram->base.fb); base 407 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c gf100_ram_prog(struct nvkm_ram *base) base 409 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c struct gf100_ram *ram = gf100_ram(base); base 410 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c struct nvkm_device *device = ram->base.fb->subdev.device; base 416 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c gf100_ram_tidy(struct nvkm_ram *base) base 418 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c struct gf100_ram *ram = gf100_ram(base); base 423 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c gf100_ram_init(struct nvkm_ram *base) base 437 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c struct gf100_ram *ram = gf100_ram(base); base 438 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c struct nvkm_device *device = ram->base.fb->subdev.device; base 441 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c switch (ram->base.type) { base 577 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c *pram = &ram->base; base 579 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c ret = gf100_ram_ctor(func, fb, &ram->base); base 24 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c #define gk104_ram(p) container_of((p), struct gk104_ram, base) base 41 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct ramfuc base; base 122 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_ram base; base 210 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_ram_data *next = ram->base.next; base 232 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_fb *fb = ram->base.fb; base 233 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct ramfuc *fuc = &ram->fuc.base; base 255 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_ram_data *next = ram->base.next; base 263 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) base 267 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if ((ram->base.mr[1] & 0x03c) != 0x030) { base 268 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c); base 269 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000); base 592 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]); base 593 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_wr32(fuc, mr[0], ram->base.mr[0]); base 594 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]); base 596 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]); base 597 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */ base 598 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]); base 599 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]); base 651 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5]) base 664 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) base 706 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_ram_data *next = ram->base.next; base 714 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) base 916 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, mr[2], 0x00000fff, ram->base.mr[2]); base 917 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, mr[1], 0xffffffff, ram->base.mr[1]); base 918 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_wr32(fuc, mr[0], ram->base.mr[0]); base 946 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP)) base 964 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_subdev *subdev = &ram->base.fb->subdev; base 1044 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_subdev *subdev = &ram->base.fb->subdev; base 1048 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ret = ram_init(fuc, ram->base.fb); base 1088 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram->base.mr[i] = ram_rd32(fuc, mr[i]); base 1090 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram->base.freq = next->freq; base 1092 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c switch (ram->base.type) { base 1094 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ret = nvkm_sddr3_calc(&ram->base); base 1099 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0); base 1112 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c gk104_ram_calc(struct nvkm_ram *base, u32 freq) base 1114 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct gk104_ram *ram = gk104_ram(base); base 1115 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_clk *clk = ram->base.fb->subdev.device->clk; base 1116 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_ram_data *xits = &ram->base.xition; base 1120 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (ram->base.next == NULL) { base 1123 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c &ram->base.former); base 1127 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ret = gk104_ram_calc_data(ram, freq, &ram->base.target); base 1131 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (ram->base.target.freq < ram->base.former.freq) { base 1132 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c *xits = ram->base.target; base 1133 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c copy = &ram->base.former; base 1135 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c *xits = ram->base.former; base 1136 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c copy = &ram->base.target; base 1143 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram->base.next = &ram->base.target; base 1144 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (memcmp(xits, &ram->base.former, sizeof(xits->bios))) base 1145 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram->base.next = &ram->base.xition; base 1147 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c BUG_ON(ram->base.next != &ram->base.xition); base 1148 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram->base.next = &ram->base.target; base 1151 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c return gk104_ram_calc_xits(ram, ram->base.next); base 1157 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_device *device = ram->base.fb->subdev.device; base 1231 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c gk104_ram_prog(struct nvkm_ram *base) base 1233 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct gk104_ram *ram = gk104_ram(base); base 1235 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_device *device = ram->base.fb->subdev.device; base 1236 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_ram_data *next = ram->base.next; base 1240 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c return (ram->base.next == &ram->base.xition); base 1247 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c return (ram->base.next == &ram->base.xition); base 1251 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c gk104_ram_tidy(struct nvkm_ram *base) base 1253 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct gk104_ram *ram = gk104_ram(base); base 1254 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram->base.next = NULL; base 1441 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct nvkm_bios *bios = ram->base.fb->subdev.device->bios; base 1508 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c gk104_ram_dtor(struct nvkm_ram *base) base 1510 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c struct gk104_ram *ram = gk104_ram(base); base 1535 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c *pram = &ram->base; base 1537 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ret = gf100_ram_ctor(func, fb, &ram->base); base 1658 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c switch (ram->base.type) { base 25 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c #define gt215_ram(p) container_of((p), struct gt215_ram, base) base 39 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct ramfuc base; base 94 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct nvkm_ram base; base 158 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct nvkm_subdev *subdev = &ram->base.fb->subdev; base 194 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ret = ram->base.func->calc(&ram->base, (u32) M0205T.freq * 1000); base 237 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram->base.func->calc(&ram->base, clk_current); base 246 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_train_result(ram->base.fb, result, 64); base 281 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct nvkm_device *device = ram->base.fb->subdev.device; base 350 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct nvbios_ramcfg *cfg = &ram->base.target.bios; base 351 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct nvkm_subdev *subdev = &ram->base.fb->subdev; base 362 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c switch ((!T(CWL)) * ram->base.type) { base 403 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c switch (ram->base.type) { base 468 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct nvkm_gpio *gpio = fuc->base.fb->subdev.device->gpio; base 492 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c gt215_ram_calc(struct nvkm_ram *base, u32 freq) base 494 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct gt215_ram *ram = gt215_ram(base); base 497 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct nvkm_subdev *subdev = &ram->base.fb->subdev; base 511 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c next = &ram->base.target; base 513 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram->base.next = next; base 559 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ret = ram_init(fuc, ram->base.fb); base 564 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram->base.mr[0] = ram_rd32(fuc, mr[0]); base 565 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram->base.mr[1] = ram_rd32(fuc, mr[1]); base 566 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram->base.mr[2] = ram_rd32(fuc, mr[2]); base 568 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c switch (ram->base.type) { base 570 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ret = nvkm_sddr2_calc(&ram->base); base 573 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ret = nvkm_sddr3_calc(&ram->base); base 576 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ret = nvkm_gddr3_calc(&ram->base); base 630 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c if (ram->base.type == NVKM_RAM_TYPE_GDDR3) base 637 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c switch (next->bios.ramcfg_DLLoff * ram->base.type) { base 639 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c nvkm_sddr3_dll_disable(fuc, ram->base.mr); base 642 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c nvkm_gddr3_dll_disable(fuc, ram->base.mr); base 749 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c if (ram_rd32(fuc, mr[i]) != ram->base.mr[i]) { base 750 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_wr32(fuc, mr[i], ram->base.mr[i]); base 781 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c switch (ram->base.type) { base 794 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c switch (ram->base.type) { base 841 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c if (ram->base.type == NVKM_RAM_TYPE_GDDR3) { base 847 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c if (ram->base.type == NVKM_RAM_TYPE_DDR3) { base 883 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c gt215_ram_prog(struct nvkm_ram *base) base 885 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct gt215_ram *ram = gt215_ram(base); base 887 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct nvkm_device *device = ram->base.fb->subdev.device; base 908 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c gt215_ram_tidy(struct nvkm_ram *base) base 910 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct gt215_ram *ram = gt215_ram(base); base 915 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c gt215_ram_init(struct nvkm_ram *base) base 917 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct gt215_ram *ram = gt215_ram(base); base 923 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c gt215_ram_dtor(struct nvkm_ram *base) base 925 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c struct gt215_ram *ram = gt215_ram(base); base 947 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c *pram = &ram->base; base 949 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ret = nv50_ram_ctor(>215_ram_func, fb, &ram->base); base 978 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram->fuc.r_0x100760 = ramfuc_stride(0x100760, 4, ram->base.part_mask); base 979 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram->fuc.r_0x1007a0 = ramfuc_stride(0x1007a0, 4, ram->base.part_mask); base 980 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram->fuc.r_0x1007e0 = ramfuc_stride(0x1007e0, 4, ram->base.part_mask); base 981 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram->fuc.r_0x100da0 = ramfuc_stride(0x100da0, 4, ram->base.part_mask); base 983 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram->fuc.r_0x1110e0 = ramfuc_stride(0x1110e0, 4, ram->base.part_mask); base 990 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c if (ram->base.ranks > 1) { base 24 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c #define mcp77_ram(p) container_of((p), struct mcp77_ram, base) base 28 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c struct nvkm_ram base; base 33 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c mcp77_ram_init(struct nvkm_ram *base) base 35 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c struct mcp77_ram *ram = mcp77_ram(base); base 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c struct nvkm_device *device = ram->base.fb->subdev.device; base 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c u32 dniso = ((ram->base.size - (ram->poller_base + 0x00)) >> 5) - 1; base 38 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c u32 hostnb = ((ram->base.size - (ram->poller_base + 0x20)) >> 5) - 1; base 39 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c u32 flush = ((ram->base.size - (ram->poller_base + 0x40)) >> 5) - 1; base 64 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c u64 base = (u64)nvkm_rd32(device, 0x100e10) << 12; base 71 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c *pram = &ram->base; base 74 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c size, &ram->base); base 79 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c ram->base.stolen = base; base 80 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c nvkm_mm_fini(&ram->base.vram); base 82 drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c return nvkm_mm_init(&ram->base.vram, NVKM_RAM_MM_NORMAL, base 34 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c nv40_ram_calc(struct nvkm_ram *base, u32 freq) base 36 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c struct nv40_ram *ram = nv40_ram(base); base 37 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c struct nvkm_subdev *subdev = &ram->base.fb->subdev; base 67 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c nv40_ram_prog(struct nvkm_ram *base) base 69 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c struct nv40_ram *ram = nv40_ram(base); base 70 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c struct nvkm_subdev *subdev = &ram->base.fb->subdev; base 179 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c nv40_ram_tidy(struct nvkm_ram *base) base 197 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c *pram = &ram->base; base 198 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c return nvkm_ram_ctor(&nv40_ram_func, fb, type, size, &ram->base); base 4 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h #define nv40_ram(p) container_of((p), struct nv40_ram, base) base 8 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h struct nvkm_ram base; base 24 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c #define nv50_ram(p) container_of((p), struct nv50_ram, base) base 39 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq base; base 67 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nvkm_ram base; base 75 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nvbios_ramcfg *cfg = &ram->base.target.bios; base 76 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nvkm_subdev *subdev = &ram->base.fb->subdev; base 86 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c switch ((!T(CWL)) * ram->base.type) { base 97 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; base 99 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->base.next->bios.rammap_00_16_40) << 16 | base 133 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c if (ram->base.type == NVKM_RAM_TYPE_DDR2) { base 137 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c if (ram->base.type == NVKM_RAM_TYPE_GDDR3) { base 154 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nvbios_ramcfg *cfg = &ram->base.target.bios; base 155 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nvkm_subdev *subdev = &ram->base.fb->subdev; base 165 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c switch (ram->base.type) { base 194 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nvkm_gpio *gpio = hwsq->base.subdev->device->gpio; base 219 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c nv50_ram_calc(struct nvkm_ram *base, u32 freq) base 221 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nv50_ram *ram = nv50_ram(base); base 223 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nvkm_subdev *subdev = &ram->base.fb->subdev; base 235 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c next = &ram->base.target; base 237 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->base.next = next; base 287 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->base.mr[0] = ram_rd32(hwsq, mr[0]); base 288 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->base.mr[1] = ram_rd32(hwsq, mr[1]); base 289 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->base.mr[2] = ram_rd32(hwsq, mr[2]); base 291 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c switch (ram->base.type) { base 293 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ret = nvkm_gddr3_calc(&ram->base); base 375 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c switch (ram->base.type) { base 382 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_wr32(hwsq, mr[1], ram->base.mr[1]); base 384 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_wr32(hwsq, mr[0], ram->base.mr[0]); base 454 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]); base 481 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c nv50_ram_prog(struct nvkm_ram *base) base 483 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nv50_ram *ram = nv50_ram(base); base 484 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nvkm_device *device = ram->base.fb->subdev.device; base 490 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c nv50_ram_tidy(struct nvkm_ram *base) base 492 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct nv50_ram *ram = nv50_ram(base); base 593 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c *pram = &ram->base; base 595 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ret = nv50_ram_ctor(&nv50_ram_func, fb, &ram->base); base 616 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x100da0 = hwsq_stride(0x100da0, 4, ram->base.part_mask); base 624 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c if (ram->base.ranks > 1) { base 6 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h #define ram_init(s,p) hwsq_init(&(s)->base, (p)) base 7 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h #define ram_exec(s,e) hwsq_exec(&(s)->base, (e)) base 9 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h #define ram_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r) base 10 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h #define ram_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d)) base 11 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h #define ram_nuke(s,r) hwsq_nuke(&(s)->base, &(s)->r_##r) base 12 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h #define ram_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) base 13 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h #define ram_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) base 14 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h #define ram_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) base 15 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h #define ram_wait_vblank(s) hwsq_wait_vblank(&(s)->base) base 16 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h #define ram_nsec(s,n) hwsq_nsec(&(s)->base, (n)) base 24 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c #define anx9805_pad(p) container_of((p), struct anx9805_pad, base) base 25 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c #define anx9805_bus(p) container_of((p), struct anx9805_bus, base) base 26 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c #define anx9805_aux(p) container_of((p), struct anx9805_aux, base) base 31 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c struct nvkm_i2c_pad base; base 37 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c struct nvkm_i2c_bus base; base 43 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c anx9805_bus_xfer(struct nvkm_i2c_bus *base, struct i2c_msg *msgs, int num) base 45 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c struct anx9805_bus *bus = anx9805_bus(base); base 103 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c anx9805_bus_new(struct nvkm_i2c_pad *base, int id, u8 drive, base 106 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c struct anx9805_pad *pad = anx9805_pad(base); base 112 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c *pbus = &bus->base; base 115 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c ret = nvkm_i2c_bus_ctor(&anx9805_bus_func, &pad->base, id, &bus->base); base 130 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c struct nvkm_i2c_aux base; base 136 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c anx9805_aux_xfer(struct nvkm_i2c_aux *base, bool retry, base 139 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c struct anx9805_aux *aux = anx9805_aux(base); base 146 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c AUX_DBG(&aux->base, "%02x %05x %d", type, addr, *size); base 156 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c AUX_DBG(&aux->base, "%16ph", buf); base 181 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c AUX_DBG(&aux->base, "%16ph", buf); base 192 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c anx9805_aux_lnk_ctl(struct nvkm_i2c_aux *base, base 195 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c struct anx9805_aux *aux = anx9805_aux(base); base 200 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c AUX_DBG(&aux->base, "ANX9805 train %d %02x %d", base 212 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c AUX_ERR(&aux->base, "link training timeout"); base 218 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c AUX_ERR(&aux->base, "link training failed"); base 232 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c anx9805_aux_new(struct nvkm_i2c_pad *base, int id, u8 drive, base 235 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c struct anx9805_pad *pad = anx9805_pad(base); base 241 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c *pbus = &aux->base; base 244 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c ret = nvkm_i2c_aux_ctor(&anx9805_aux_func, &pad->base, id, &aux->base); base 272 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c *ppad = &pad->base; base 274 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c nvkm_i2c_pad_ctor(&anx9805_pad_func, bus->pad->i2c, id, &pad->base); base 24 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c #define g94_i2c_aux(p) container_of((p), struct g94_i2c_aux, base) base 28 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c struct nvkm_i2c_aux base; base 35 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c struct nvkm_device *device = aux->base.pad->i2c->subdev.device; base 42 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c struct nvkm_device *device = aux->base.pad->i2c->subdev.device; base 54 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl); base 66 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c AUX_ERR(&aux->base, "magic wait %08x", ctrl); base 80 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c struct nvkm_device *device = aux->base.pad->i2c->subdev.device; base 81 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c const u32 base = aux->ch * 0x50; base 86 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c AUX_TRACE(&aux->base, "%d: %08x %d", type, addr, *size); base 92 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c stat = nvkm_rd32(device, 0x00e4e8 + base); base 94 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c AUX_TRACE(&aux->base, "sink not detected"); base 102 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c AUX_TRACE(&aux->base, "wr %08x", xbuf[i / 4]); base 103 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c nvkm_wr32(device, 0x00e4c0 + base + i, xbuf[i / 4]); base 107 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c ctrl = nvkm_rd32(device, 0x00e4e4 + base); base 111 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c nvkm_wr32(device, 0x00e4e0 + base, addr); base 116 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c nvkm_wr32(device, 0x00e4e4 + base, 0x80000000 | ctrl); base 117 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c nvkm_wr32(device, 0x00e4e4 + base, 0x00000000 | ctrl); base 122 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c nvkm_wr32(device, 0x00e4e4 + base, 0x00010000 | ctrl); base 126 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c ctrl = nvkm_rd32(device, 0x00e4e4 + base); base 129 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c AUX_ERR(&aux->base, "timeout %08x", ctrl); base 137 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c stat = nvkm_mask(device, 0x00e4e8 + base, 0, 0); base 146 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c AUX_TRACE(&aux->base, "%02d %08x %08x", retries, ctrl, stat); base 151 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c xbuf[i / 4] = nvkm_rd32(device, 0x00e4d0 + base + i); base 152 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c AUX_TRACE(&aux->base, "rd %08x", xbuf[i / 4]); base 172 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c *paux = &aux->base; base 174 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c nvkm_i2c_aux_ctor(func, pad, index, &aux->base); base 176 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c aux->base.intr = 1 << aux->ch; base 24 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c #define gm200_i2c_aux(p) container_of((p), struct gm200_i2c_aux, base) base 28 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c struct nvkm_i2c_aux base; base 35 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c struct nvkm_device *device = aux->base.pad->i2c->subdev.device; base 42 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c struct nvkm_device *device = aux->base.pad->i2c->subdev.device; base 54 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl); base 66 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c AUX_ERR(&aux->base, "magic wait %08x", ctrl); base 80 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c struct nvkm_device *device = aux->base.pad->i2c->subdev.device; base 81 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c const u32 base = aux->ch * 0x50; base 86 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c AUX_TRACE(&aux->base, "%d: %08x %d", type, addr, *size); base 92 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c stat = nvkm_rd32(device, 0x00d958 + base); base 94 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c AUX_TRACE(&aux->base, "sink not detected"); base 102 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c AUX_TRACE(&aux->base, "wr %08x", xbuf[i / 4]); base 103 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c nvkm_wr32(device, 0x00d930 + base + i, xbuf[i / 4]); base 107 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c ctrl = nvkm_rd32(device, 0x00d954 + base); base 111 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c nvkm_wr32(device, 0x00d950 + base, addr); base 116 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c nvkm_wr32(device, 0x00d954 + base, 0x80000000 | ctrl); base 117 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c nvkm_wr32(device, 0x00d954 + base, 0x00000000 | ctrl); base 122 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c nvkm_wr32(device, 0x00d954 + base, 0x00010000 | ctrl); base 126 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c ctrl = nvkm_rd32(device, 0x00d954 + base); base 129 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c AUX_ERR(&aux->base, "timeout %08x", ctrl); base 137 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c stat = nvkm_mask(device, 0x00d958 + base, 0, 0); base 146 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c AUX_TRACE(&aux->base, "%02d %08x %08x", retries, ctrl, stat); base 151 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c xbuf[i / 4] = nvkm_rd32(device, 0x00d940 + base + i); base 152 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c AUX_TRACE(&aux->base, "rd %08x", xbuf[i / 4]); base 177 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c *paux = &aux->base; base 179 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c nvkm_i2c_aux_ctor(&gm200_i2c_aux_func, pad, index, &aux->base); base 181 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c aux->base.intr = 1 << aux->ch; base 24 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c #define gf119_i2c_bus(p) container_of((p), struct gf119_i2c_bus, base) base 28 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c struct nvkm_i2c_bus base; base 33 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c gf119_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) base 35 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c struct gf119_i2c_bus *bus = gf119_i2c_bus(base); base 36 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 41 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c gf119_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) base 43 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c struct gf119_i2c_bus *bus = gf119_i2c_bus(base); base 44 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 49 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c gf119_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) base 51 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c struct gf119_i2c_bus *bus = gf119_i2c_bus(base); base 52 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 57 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c gf119_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) base 59 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c struct gf119_i2c_bus *bus = gf119_i2c_bus(base); base 60 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 65 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c gf119_i2c_bus_init(struct nvkm_i2c_bus *base) base 67 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c struct gf119_i2c_bus *bus = gf119_i2c_bus(base); base 68 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 90 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c *pbus = &bus->base; base 92 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.c nvkm_i2c_bus_ctor(&gf119_i2c_bus_func, pad, id, &bus->base); base 24 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c #define nv04_i2c_bus(p) container_of((p), struct nv04_i2c_bus, base) base 30 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c struct nvkm_i2c_bus base; base 36 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c nv04_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) base 38 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c struct nv04_i2c_bus *bus = nv04_i2c_bus(base); base 39 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 47 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c nv04_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) base 49 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c struct nv04_i2c_bus *bus = nv04_i2c_bus(base); base 50 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 58 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c nv04_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) base 60 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c struct nv04_i2c_bus *bus = nv04_i2c_bus(base); base 61 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 66 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c nv04_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) base 68 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c struct nv04_i2c_bus *bus = nv04_i2c_bus(base); base 69 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 90 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c *pbus = &bus->base; base 92 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.c nvkm_i2c_bus_ctor(&nv04_i2c_bus_func, pad, id, &bus->base); base 24 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c #define nv4e_i2c_bus(p) container_of((p), struct nv4e_i2c_bus, base) base 28 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c struct nvkm_i2c_bus base; base 33 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c nv4e_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) base 35 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); base 36 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 41 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c nv4e_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) base 43 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); base 44 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 49 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c nv4e_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) base 51 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); base 52 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 57 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c nv4e_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) base 59 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); base 60 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 81 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c *pbus = &bus->base; base 83 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.c nvkm_i2c_bus_ctor(&nv4e_i2c_bus_func, pad, id, &bus->base); base 24 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c #define nv50_i2c_bus(p) container_of((p), struct nv50_i2c_bus, base) base 30 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c struct nvkm_i2c_bus base; base 36 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c nv50_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) base 38 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c struct nv50_i2c_bus *bus = nv50_i2c_bus(base); base 39 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 46 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c nv50_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) base 48 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c struct nv50_i2c_bus *bus = nv50_i2c_bus(base); base 49 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 56 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c nv50_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) base 58 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c struct nv50_i2c_bus *bus = nv50_i2c_bus(base); base 59 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 64 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c nv50_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) base 66 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c struct nv50_i2c_bus *bus = nv50_i2c_bus(base); base 67 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 72 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c nv50_i2c_bus_init(struct nvkm_i2c_bus *base) base 74 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c struct nv50_i2c_bus *bus = nv50_i2c_bus(base); base 75 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c struct nvkm_device *device = bus->base.pad->i2c->subdev.device; base 107 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c *pbus = &bus->base; base 109 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.c nvkm_i2c_bus_ctor(&nv50_i2c_bus_func, pad, id, &bus->base); base 33 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c const u32 base = (pad->id - NVKM_I2C_PAD_HYBRID(0)) * 0x50; base 37 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c nvkm_mask(device, 0x00e50c + base, 0x00000001, 0x00000001); base 40 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c nvkm_mask(device, 0x00e500 + base, 0x0000c003, 0x0000c001); base 41 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c nvkm_mask(device, 0x00e50c + base, 0x00000001, 0x00000000); base 44 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c nvkm_mask(device, 0x00e500 + base, 0x0000c003, 0x00000002); base 45 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.c nvkm_mask(device, 0x00e50c + base, 0x00000001, 0x00000000); base 33 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.c const u32 base = (pad->id - NVKM_I2C_PAD_HYBRID(0)) * 0x50; base 37 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.c nvkm_mask(device, 0x00d97c + base, 0x00000001, 0x00000001); base 40 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.c nvkm_mask(device, 0x00d970 + base, 0x0000c003, 0x0000c001); base 41 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.c nvkm_mask(device, 0x00d97c + base, 0x00000001, 0x00000000); base 44 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.c nvkm_mask(device, 0x00d970 + base, 0x0000c003, 0x00000002); base 45 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.c nvkm_mask(device, 0x00d97c + base, 0x00000001, 0x00000000); base 65 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct gk20a_instobj base; base 71 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c container_of(gk20a_instobj(p), struct gk20a_instobj_dma, base) base 77 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct gk20a_instobj base; base 90 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c container_of(gk20a_instobj(p), struct gk20a_instobj_iommu, base) base 93 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct nvkm_instmem base; base 113 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c #define gk20a_instmem(p) container_of((p), struct gk20a_instmem, base) base 145 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct gk20a_instmem *imem = obj->base.imem; base 149 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c vunmap(obj->base.vaddr); base 150 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c obj->base.vaddr = NULL; base 151 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c imem->vaddr_use -= nvkm_memory_size(&obj->base.memory); base 152 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", imem->vaddr_use, base 178 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; base 189 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct gk20a_instmem *imem = node->base.imem; base 190 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; base 197 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c if (node->base.vaddr) { base 209 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c node->base.vaddr = vmap(node->pages, size >> PAGE_SHIFT, VM_MAP, base 211 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c if (!node->base.vaddr) { base 212 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c nvkm_error(&imem->base.subdev, "cannot map instobj - " base 218 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", base 225 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c return node->base.vaddr; base 233 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; base 244 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct gk20a_instmem *imem = node->base.imem; base 245 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; base 298 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct gk20a_instmem *imem = node->base.imem; base 299 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct device *dev = imem->base.subdev.device->dev; base 301 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c if (unlikely(!node->base.vaddr)) base 304 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c dma_free_attrs(dev, (u64)node->base.mn->length << PAGE_SHIFT, base 305 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c node->base.vaddr, node->handle, imem->attrs); base 315 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct gk20a_instmem *imem = node->base.imem; base 316 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct device *dev = imem->base.subdev.device->dev; base 317 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct nvkm_mm_node *r = node->base.mn; base 326 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c if (node->base.vaddr) base 335 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c for (i = 0; i < node->base.mn->length; i++) { base 387 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct nvkm_subdev *subdev = &imem->base.subdev; base 392 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c *_node = &node->base; base 394 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c nvkm_memory_ctor(&gk20a_instobj_func_dma, &node->base.memory); base 395 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c node->base.memory.ptrs = &gk20a_instobj_ptrs; base 397 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c node->base.vaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, base 400 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c if (!node->base.vaddr) { base 416 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c node->base.mn = &node->r; base 425 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct nvkm_subdev *subdev = &imem->base.subdev; base 438 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c *_node = &node->base; base 441 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c nvkm_memory_ctor(&gk20a_instobj_func_iommu, &node->base.memory); base 442 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c node->base.memory.ptrs = &gk20a_instobj_ptrs; base 493 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c node->base.mn = r; base 514 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, base 517 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct gk20a_instmem *imem = gk20a_instmem(base); base 518 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct nvkm_subdev *subdev = &imem->base.subdev; base 548 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c gk20a_instmem_dtor(struct nvkm_instmem *base) base 550 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c struct gk20a_instmem *imem = gk20a_instmem(base); base 554 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c nvkm_warn(&base->subdev, "instobj LRU not empty!\n"); base 557 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c nvkm_warn(&base->subdev, "instobj vmap area not empty! " base 579 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c nvkm_instmem_ctor(&gk20a_instmem, device, index, &imem->base); base 581 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c *pimem = &imem->base; base 595 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c nvkm_info(&imem->base.subdev, "using IOMMU\n"); base 601 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c nvkm_info(&imem->base.subdev, "using DMA API\n"); base 24 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c #define nv04_instmem(p) container_of((p), struct nv04_instmem, base) base 30 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c struct nvkm_instmem base; base 37 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c #define nv04_instobj(p) container_of((p), struct nv04_instobj, base.memory) base 40 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c struct nvkm_instobj base; base 49 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c struct nvkm_device *device = iobj->imem->base.subdev.device; base 57 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c struct nvkm_device *device = iobj->imem->base.subdev.device; base 76 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c struct nvkm_device *device = iobj->imem->base.subdev.device; base 102 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c mutex_lock(&iobj->imem->base.subdev.mutex); base 104 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c mutex_unlock(&iobj->imem->base.subdev.mutex); base 105 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nvkm_instobj_dtor(&iobj->imem->base, &iobj->base); base 120 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nv04_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, base 123 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c struct nv04_instmem *imem = nv04_instmem(base); base 129 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c *pmemory = &iobj->base.memory; base 131 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nvkm_instobj_ctor(&nv04_instobj_func, &imem->base, &iobj->base); base 132 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c iobj->base.memory.ptrs = &nv04_instobj_ptrs; base 135 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c mutex_lock(&imem->base.subdev.mutex); base 138 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c mutex_unlock(&imem->base.subdev.mutex); base 159 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nv04_instmem_oneinit(struct nvkm_instmem *base) base 161 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c struct nv04_instmem *imem = nv04_instmem(base); base 162 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c struct nvkm_device *device = imem->base.subdev.device; base 166 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c imem->base.reserved = 512 * 1024; base 168 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c ret = nvkm_mm_init(&imem->heap, 0, 0, imem->base.reserved, 1); base 174 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c &imem->base.vbios); base 179 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c ret = nvkm_ramht_new(device, 0x08000, 0, NULL, &imem->base.ramht); base 185 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c &imem->base.ramfc); base 191 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c &imem->base.ramro); base 199 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nv04_instmem_dtor(struct nvkm_instmem *base) base 201 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c struct nv04_instmem *imem = nv04_instmem(base); base 202 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nvkm_memory_unref(&imem->base.ramfc); base 203 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nvkm_memory_unref(&imem->base.ramro); base 204 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nvkm_ramht_del(&imem->base.ramht); base 205 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nvkm_memory_unref(&imem->base.vbios); base 228 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nvkm_instmem_ctor(&nv04_instmem, device, index, &imem->base); base 229 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c *pimem = &imem->base; base 24 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c #define nv40_instmem(p) container_of((p), struct nv40_instmem, base) base 31 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c struct nvkm_instmem base; base 39 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c #define nv40_instobj(p) container_of((p), struct nv40_instobj, base.memory) base 42 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c struct nvkm_instobj base; base 102 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c mutex_lock(&iobj->imem->base.subdev.mutex); base 104 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c mutex_unlock(&iobj->imem->base.subdev.mutex); base 105 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nvkm_instobj_dtor(&iobj->imem->base, &iobj->base); base 120 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nv40_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, base 123 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c struct nv40_instmem *imem = nv40_instmem(base); base 129 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c *pmemory = &iobj->base.memory; base 131 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nvkm_instobj_ctor(&nv40_instobj_func, &imem->base, &iobj->base); base 132 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c iobj->base.memory.ptrs = &nv40_instobj_ptrs; base 135 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c mutex_lock(&imem->base.subdev.mutex); base 138 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c mutex_unlock(&imem->base.subdev.mutex); base 147 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nv40_instmem_rd32(struct nvkm_instmem *base, u32 addr) base 149 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c return ioread32_native(nv40_instmem(base)->iomem + addr); base 153 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nv40_instmem_wr32(struct nvkm_instmem *base, u32 addr, u32 data) base 155 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c iowrite32_native(data, nv40_instmem(base)->iomem + addr); base 159 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nv40_instmem_oneinit(struct nvkm_instmem *base) base 161 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c struct nv40_instmem *imem = nv40_instmem(base); base 162 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c struct nvkm_device *device = imem->base.subdev.device; base 170 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c if (device->chipset == 0x40) imem->base.reserved = 0x6aa0 * vs; base 171 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c else if (device->chipset < 0x43) imem->base.reserved = 0x4f00 * vs; base 172 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c else if (nv44_gr_class(device)) imem->base.reserved = 0x4980 * vs; base 173 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c else imem->base.reserved = 0x4a40 * vs; base 174 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c imem->base.reserved += 16 * 1024; base 175 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c imem->base.reserved *= 32; /* per-channel */ base 176 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c imem->base.reserved += 512 * 1024; /* pci(e)gart table */ base 177 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c imem->base.reserved += 512 * 1024; /* object storage */ base 178 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c imem->base.reserved = round_up(imem->base.reserved, 4096); base 180 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c ret = nvkm_mm_init(&imem->heap, 0, 0, imem->base.reserved, 1); base 186 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c &imem->base.vbios); base 191 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c ret = nvkm_ramht_new(device, 0x08000, 0, NULL, &imem->base.ramht); base 199 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c &imem->base.ramro); base 207 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c &imem->base.ramfc); base 215 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nv40_instmem_dtor(struct nvkm_instmem *base) base 217 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c struct nv40_instmem *imem = nv40_instmem(base); base 218 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nvkm_memory_unref(&imem->base.ramfc); base 219 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nvkm_memory_unref(&imem->base.ramro); base 220 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nvkm_ramht_del(&imem->base.ramht); base 221 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nvkm_memory_unref(&imem->base.vbios); base 247 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nvkm_instmem_ctor(&nv40_instmem, device, index, &imem->base); base 248 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c *pimem = &imem->base; base 259 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nvkm_error(&imem->base.subdev, "unable to map PRAMIN BAR\n"); base 24 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c #define nv50_instmem(p) container_of((p), struct nv50_instmem, base) base 33 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nvkm_instmem base; base 43 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c #define nv50_instobj(p) container_of((p), struct nv50_instobj, base.memory) base 46 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nvkm_instobj base; base 60 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nvkm_device *device = imem->base.subdev.device; base 61 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL; base 65 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c spin_lock_irqsave(&imem->base.lock, flags); base 66 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c if (unlikely(imem->addr != base)) { base 67 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c nvkm_wr32(device, 0x001700, base >> 16); base 68 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c imem->addr = base; base 71 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c spin_unlock_irqrestore(&imem->base.lock, flags); base 79 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nvkm_device *device = imem->base.subdev.device; base 80 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL; base 85 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c spin_lock_irqsave(&imem->base.lock, flags); base 86 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c if (unlikely(imem->addr != base)) { base 87 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c nvkm_wr32(device, 0x001700, base >> 16); base 88 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c imem->addr = base; base 91 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c spin_unlock_irqrestore(&imem->base.lock, flags); base 124 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nvkm_memory *memory = &iobj->base.memory; base 125 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nvkm_subdev *subdev = &imem->base.subdev; base 145 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c nvkm_memory_addr(&eobj->base.memory), base 146 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c nvkm_memory_size(&eobj->base.memory), base 195 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nvkm_subdev *subdev = &imem->base.subdev; base 210 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c iobj->base.memory.ptrs = NULL; base 219 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nvkm_instmem *imem = &iobj->imem->base; base 249 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c iobj->base.memory.ptrs = &nv50_instobj_fast; base 251 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c iobj->base.memory.ptrs = &nv50_instobj_slow; base 263 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nvkm_instmem *imem = &iobj->imem->base; base 296 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c if (nv50_instobj_acquire(&iobj->base.memory)) { base 300 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c nv50_instobj_release(&iobj->base.memory); base 314 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nvkm_instmem *imem = &iobj->imem->base; base 333 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c nvkm_instobj_dtor(imem, &iobj->base); base 351 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c nv50_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, base 354 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nv50_instmem *imem = nv50_instmem(base); base 356 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c struct nvkm_device *device = imem->base.subdev.device; base 361 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c *pmemory = &iobj->base.memory; base 363 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c nvkm_instobj_ctor(&nv50_instobj_func, &imem->base, &iobj->base); base 376 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c nv50_instmem_fini(struct nvkm_instmem *base) base 378 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c nv50_instmem(base)->addr = ~0ULL; base 396 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c nvkm_instmem_ctor(&nv50_instmem, device, index, &imem->base); base 398 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c *pimem = &imem->base; base 97 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c u32 base = 0x141000 + (c * 0x2000) + (s * 0x400); base 98 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c u32 intr = nvkm_rd32(device, base + 0x020); base 107 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c nvkm_wr32(device, base + 0x020, intr); base 76 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c u32 base = 0x140400 + (c * 0x2000) + (s * 0x200); base 77 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c u32 intr = nvkm_rd32(device, base + 0x00c); base 86 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c nvkm_wr32(device, base + 0x00c, intr); base 24 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c #define gp100_mc(p) container_of((p), struct gp100_mc, base) base 28 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c struct nvkm_mc base; base 37 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c struct nvkm_device *device = mc->base.subdev.device; base 46 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c gp100_mc_intr_unarm(struct nvkm_mc *base) base 48 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c struct gp100_mc *mc = gp100_mc(base); base 57 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c gp100_mc_intr_rearm(struct nvkm_mc *base) base 59 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c struct gp100_mc *mc = gp100_mc(base); base 68 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr) base 70 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c struct gp100_mc *mc = gp100_mc(base); base 115 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c nvkm_mc_ctor(func, device, index, &mc->base); base 116 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c *pmc = &mc->base; base 44 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c const int slot = pt->base >> pt->ptp->shift; base 107 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c pt->base = slot << ptp->shift; base 108 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c pt->addr = pt->ptp->pt->addr + pt->base; base 214 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c pt->base = 0; base 424 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c mmu->user.base = func->mmu.user; base 30 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c nv50_mmu_kind(struct nvkm_mmu *base, int *count) base 57 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h u16 base; base 39 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c oclass->base = mmu->func->mem.user; base 47 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c oclass->base = mmu->func->vmm.user; base 376 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c const bool more = oclass->base.maxver >= 0; base 206 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h int gf100_vmm_join_(struct nvkm_vmm *, struct nvkm_memory *, u64 base); base 220 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h int gm200_vmm_join_(struct nvkm_vmm *, struct nvkm_memory *, u64 base); base 329 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h VMM_##fn((m), (m)->base + _pteo, _data, (c), b); \ base 345 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h nvkm_wo64((m)->memory, (m)->base + _pteo + 0, (lo)); \ base 346 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h nvkm_wo64((m)->memory, (m)->base + _pteo + 8, (hi)); \ base 35 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c u64 base = (addr >> 8) | map->type; base 36 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c u64 data = base; base 40 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c data = base | ((map->ctag >> 1) << 44); base 45 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c base += map->next; base 341 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c gf100_vmm_join_(struct nvkm_vmm *vmm, struct nvkm_memory *inst, u64 base) base 346 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c case NVKM_MEM_TARGET_VRAM: base |= 0ULL << 0; break; base 347 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c case NVKM_MEM_TARGET_HOST: base |= 2ULL << 0; base 348 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c base |= BIT_ULL(2) /* VOL. */; base 350 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c case NVKM_MEM_TARGET_NCOH: base |= 3ULL << 0; break; base 355 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c base |= pd->addr; base 358 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c nvkm_wo64(inst, 0x0200, base); base 96 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c gm200_vmm_join_(struct nvkm_vmm *vmm, struct nvkm_memory *inst, u64 base) base 99 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c base |= BIT_ULL(11); base 100 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c return gf100_vmm_join_(vmm, inst, base); base 42 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 0); base 43 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 4); base 61 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 0); base 62 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 4); base 479 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c u64 base = BIT_ULL(10) /* VER2 */ | BIT_ULL(11) /* 64KiB */; base 481 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c base |= BIT_ULL(4); /* FAULT_REPLAY_TEX */ base 482 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c base |= BIT_ULL(5); /* FAULT_REPLAY_GCC */ base 484 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c return gf100_vmm_join_(vmm, inst, base); base 133 drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c pci->agp.base = info.aper_base; base 173 drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c pci->agp.mtrr = arch_phys_wc_add(pci->agp.base, pci->agp.size); base 22 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c #define gk20a_pmu(p) container_of((p), struct gk20a_pmu, base) base 40 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c struct nvkm_pmu base; base 53 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c struct nvkm_clk *clk = pmu->base.subdev.device->clk; base 61 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c struct nvkm_clk *clk = pmu->base.subdev.device->clk; base 71 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c struct nvkm_clk *clk = pmu->base.subdev.device->clk; base 86 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c nvkm_trace(&pmu->base.subdev, "cur level = %d, new level = %d\n", base 98 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c struct nvkm_falcon *falcon = pmu->base.falcon; base 107 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c struct nvkm_falcon *falcon = pmu->base.falcon; base 120 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c struct nvkm_subdev *subdev = &pmu->base.subdev; base 212 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c *ppmu = &pmu->base; base 214 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c nvkm_pmu_ctor(&gk20a_pmu, device, index, &pmu->base); base 65 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c pmu->send.base)); base 105 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c pmu->recv.base)); base 228 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c pmu->send.base = nvkm_rd32(device, 0x10a4d0) & 0x0000ffff; base 237 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c pmu->recv.base = nvkm_rd32(device, 0x10a4dc) & 0x0000ffff; base 8 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c u32 base; base 60 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c memx->base = reply[0]; base 67 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c nvkm_wr32(device, 0x10a1c0, 0x01000000 | memx->base); base 90 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c memx->base, finish); base 169 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c u32 reply[2], base, size, i; base 177 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c base = reply[0]; base 183 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c nvkm_wr32(device, 0x10a1c0, 0x02000000 | base); base 82 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c u64 base, addr_code, addr_data; base 84 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c base = wpr_addr + img->ucode_off + pdesc->app_start_offset; base 85 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c addr_code = (base + pdesc->app_resident_code_offset) >> 8; base 86 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c addr_data = (base + pdesc->app_resident_data_offset) >> 8; base 230 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c struct ls_ucode_img base; base 237 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c #define ls_ucode_img_r352(i) container_of(i, struct ls_ucode_img_r352, base) base 247 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c const struct nvkm_subdev *subdev = acr->base.subdev; base 256 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c img->base.falcon_id = falcon_id; base 258 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = func->load(sb, func->version_max, &img->base); base 260 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c kfree(img->base.ucode_data); base 261 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c kfree(img->base.sig); base 269 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (img->base.sig_size != sizeof(img->lsb_header.signature)) { base 276 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c memcpy(&img->lsb_header.signature, img->base.sig, img->base.sig_size); base 281 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c return &img->base; base 305 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c struct ls_ucode_img *_img = &img->base; base 313 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c whdr->bootstrap_owner = acr->base.boot_falcon; base 361 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (_img->falcon_id == acr->base.boot_falcon) base 404 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c list_for_each_entry(img, imgs, base.node) { base 449 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc); base 483 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c const struct nvkm_subdev *subdev = acr->base.subdev; base 486 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c unsigned long managed_falcons = acr->base.managed_falcons; base 502 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->base.optional_falcons & BIT(falcon_id)) { base 517 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->base.managed_falcons = managed_falcons; base 523 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->func->ls_func[acr->base.boot_falcon] && base 524 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c (managed_falcons & BIT(acr->base.boot_falcon))) { base 527 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (falcon_id == acr->base.boot_falcon) base 756 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c if (acr->base.boot_falcon != NVKM_SECBOOT_FALCON_PMU) { base 907 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c unsigned long managed_falcons = acr->base.managed_falcons; base 943 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c ret = func->post_run(&acr->base, sb); base 1145 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c u64 base; base 1150 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c base = wpr_addr + img->ucode_off + pdesc->app_start_offset; base 1151 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c addr_code = (base + pdesc->app_resident_code_offset) >> 8; base 1152 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c addr_data = (base + pdesc->app_resident_data_offset) >> 8; base 1228 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->base.boot_falcon = boot_falcon; base 1229 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->base.managed_falcons = managed_falcons; base 1230 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->base.func = &acr_r352_base_func; base 1233 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c return &acr->base; base 108 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h struct nvkm_acr base; base 153 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h #define acr_r352(acr) container_of(acr, struct acr_r352, base) base 37 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c u64 base, addr_code, addr_data; base 39 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c base = wpr_addr + img->ucode_off + pdesc->app_start_offset; base 40 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c addr_code = base + pdesc->app_resident_code_offset; base 41 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c addr_data = base + pdesc->app_resident_data_offset; base 123 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c u64 base, addr_code, addr_data; base 126 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c base = wpr_addr + img->ucode_off + pdesc->app_start_offset; base 127 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c addr_code = base + pdesc->app_resident_code_offset; base 128 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c addr_data = base + pdesc->app_resident_data_offset; base 168 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c u64 base, addr_code, addr_data; base 171 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c base = wpr_addr + img->ucode_off + pdesc->app_start_offset; base 173 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c addr_code = base; base 174 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c addr_data = base + pdesc->app_resident_data_offset; base 102 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c struct ls_ucode_img base; base 109 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c #define ls_ucode_img_r367(i) container_of(i, struct ls_ucode_img_r367, base) base 116 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c const struct nvkm_subdev *subdev = acr->base.subdev; base 125 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c img->base.falcon_id = falcon_id; base 127 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c ret = func->load(sb, func->version_max, &img->base); base 129 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c kfree(img->base.ucode_data); base 130 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c kfree(img->base.sig); base 138 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c if (img->base.sig_size != sizeof(img->lsb_header.signature)) { base 145 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c memcpy(&img->lsb_header.signature, img->base.sig, img->base.sig_size); base 150 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c return &img->base; base 163 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c struct ls_ucode_img *_img = &img->base; base 171 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c whdr->bootstrap_owner = acr->base.boot_falcon; base 220 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c if (_img->falcon_id == acr->base.boot_falcon) base 260 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c list_for_each_entry(img, imgs, base.node) { base 301 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc); base 37 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c u64 base, addr_code, addr_data; base 39 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c base = wpr_addr + img->ucode_off + pdesc->app_start_offset; base 40 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c addr_code = base + pdesc->app_resident_code_offset; base 41 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c addr_data = base + pdesc->app_resident_data_offset; base 92 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c u64 base, addr_code, addr_data; base 95 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c base = wpr_addr + img->ucode_off + pdesc->app_start_offset; base 97 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c addr_code = base; base 98 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c addr_data = base + pdesc->app_resident_data_offset; base 37 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c u64 base, addr_code, addr_data; base 40 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c base = wpr_addr + img->ucode_off + pdesc->app_start_offset; base 41 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c addr_code = base + pdesc->app_resident_code_offset; base 42 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c addr_data = base + pdesc->app_resident_data_offset; base 41 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c struct nvkm_subdev *subdev = &gsb->base.subdev; base 123 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c gsb->vmm->debug = gsb->base.subdev.debug; base 190 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c *psb = &gsb->base; base 192 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c ret = nvkm_secboot_ctor(&gm200_secboot, acr, device, index, &gsb->base); base 29 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h struct nvkm_secboot base; base 35 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h #define gm200_secboot(sb) container_of(sb, struct gm200_secboot, base) base 44 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c struct nvkm_secboot *sb = &gsb->base; base 77 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c nvkm_error(&gsb->base.subdev, "Tegra support not compiled in\n"); base 122 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c *psb = &gsb->base; base 124 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c ret = nvkm_secboot_ctor(&gm20b_secboot, acr, device, index, &gsb->base); base 164 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c *psb = &gsb->base; base 166 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c ret = nvkm_secboot_ctor(&gp102_secboot, acr, device, index, &gsb->base); base 43 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c *psb = &gsb->base; base 45 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp108.c return nvkm_secboot_ctor(&gp102_secboot, acr, device, index, &gsb->base); base 68 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c *psb = &gsb->base; base 70 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c ret = nvkm_secboot_ctor(&gp10b_secboot, acr, device, index, &gsb->base); base 33 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c struct nvkm_fan base; base 66 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c divs = fan->base.perf.pwm_divisor; base 67 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c if (fan->base.bios.pwm_freq) { base 71 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c divs /= fan->base.bios.pwm_freq; base 101 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c therm->fan = &fan->base; base 105 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c fan->base.type = "PWM"; base 106 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c fan->base.get = nvkm_fanpwm_get; base 107 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c fan->base.set = nvkm_fanpwm_set; base 30 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c struct nvkm_fan base; base 41 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c struct nvkm_therm *therm = fan->base.parent; base 103 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c therm->fan = &fan->base; base 107 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c fan->base.type = "toggle"; base 108 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c fan->base.get = nvkm_fantog_get; base 109 drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c fan->base.set = nvkm_fantog_set; base 30 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c gk104_clkgate_enable(struct nvkm_therm *base) base 32 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c struct gk104_therm *therm = gk104_therm(base); base 33 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c struct nvkm_device *dev = therm->base.subdev.device; base 59 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c gk104_clkgate_fini(struct nvkm_therm *base, bool suspend) base 61 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c struct gk104_therm *therm = gk104_therm(base); base 62 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c struct nvkm_device *dev = therm->base.subdev.device; base 121 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c nvkm_therm_ctor(&therm->base, device, index, func); base 122 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c *ptherm = &therm->base; base 27 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h #define gk104_therm(p) (container_of((p), struct gk104_therm, base)) base 39 drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h struct nvkm_therm base; base 196 drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c if (data && info.vidmask && info.base && info.step && info.ranged) { base 201 drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c if (info.base >= info.min && base 202 drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c info.base <= info.max) { base 203 drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c volt->vid[volt->vid_nr].uv = info.base; base 207 drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c info.base += info.step; base 227 drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c volt->min_uv = info.base; base 228 drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c volt->max_uv = info.base + info.pwm_range; base 32 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c #define gk104_volt(p) container_of((p), struct gk104_volt, base) base 34 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c struct nvkm_volt base; base 39 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c gk104_volt_get(struct nvkm_volt *base) base 41 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c struct nvbios_volt *bios = &gk104_volt(base)->bios; base 42 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c struct nvkm_device *device = base->subdev.device; base 48 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c return bios->base + bios->pwm_range * duty / div; base 52 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c gk104_volt_set(struct nvkm_volt *base, u32 uv) base 54 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c struct nvbios_volt *bios = &gk104_volt(base)->bios; base 55 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c struct nvkm_device *device = base->subdev.device; base 60 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c duty = DIV_ROUND_UP((uv - bios->base) * div, bios->pwm_range); base 117 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c nvkm_volt_ctor(volt_func, device, index, &volt->base); base 118 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c *pvolt = &volt->base; base 126 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c nvkm_error(&volt->base.subdev, base 132 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c nvkm_voltgpio_init(&volt->base); base 137 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c nvkm_debug(&volt->base.subdev, "Using %s mode\n", mode); base 22 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c #define gk20a_volt(p) container_of((p), struct gk20a_volt, base) base 93 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c gk20a_volt_vid_get(struct nvkm_volt *base) base 95 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c struct gk20a_volt *volt = gk20a_volt(base); base 100 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c for (i = 0; i < volt->base.vid_nr; i++) base 101 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c if (volt->base.vid[i].uv >= uv) base 108 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c gk20a_volt_vid_set(struct nvkm_volt *base, u8 vid) base 110 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c struct gk20a_volt *volt = gk20a_volt(base); base 111 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c struct nvkm_subdev *subdev = &volt->base.subdev; base 113 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c nvkm_debug(subdev, "set voltage as %duv\n", volt->base.vid[vid].uv); base 114 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c return regulator_set_voltage(volt->vdd, volt->base.vid[vid].uv, 1200000); base 118 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c gk20a_volt_set_id(struct nvkm_volt *base, u8 id, int condition) base 120 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c struct gk20a_volt *volt = gk20a_volt(base); base 121 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c struct nvkm_subdev *subdev = &volt->base.subdev; base 123 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c int target_uv = volt->base.vid[id].uv; base 131 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c ret = gk20a_volt_vid_set(&volt->base, volt->base.vid[id].vid); base 154 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c nvkm_volt_ctor(&gk20a_volt, device, index, &volt->base); base 157 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c nvkm_debug(&volt->base.subdev, "the default voltage is %duV\n", uv); base 161 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c volt->base.vid_nr = nb_coefs; base 162 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c for (i = 0; i < volt->base.vid_nr; i++) { base 163 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c volt->base.vid[i].vid = i; base 164 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c volt->base.vid[i].uv = max( base 167 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c nvkm_debug(&volt->base.subdev, "%2d: vid=%d, uv=%d\n", i, base 168 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c volt->base.vid[i].vid, volt->base.vid[i].uv); base 182 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c *pvolt = &volt->base; base 36 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.h struct nvkm_volt base; base 82 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c *pvolt = &volt->base; base 160 drivers/gpu/drm/omapdrm/dss/dispc.c void __iomem *base; base 360 drivers/gpu/drm/omapdrm/dss/dispc.c __raw_writel(val, dispc->base + idx); base 365 drivers/gpu/drm/omapdrm/dss/dispc.c return __raw_readl(dispc->base + idx); base 4788 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->base = devm_ioremap_resource(&pdev->dev, dispc_mem); base 4789 drivers/gpu/drm/omapdrm/dss/dispc.c if (IS_ERR(dispc->base)) { base 4790 drivers/gpu/drm/omapdrm/dss/dispc.c r = PTR_ERR(dispc->base); base 438 drivers/gpu/drm/omapdrm/dss/dsi.c void __iomem *base; base 441 drivers/gpu/drm/omapdrm/dss/dsi.c case DSI_PROTO: base = dsi->proto_base; break; base 442 drivers/gpu/drm/omapdrm/dss/dsi.c case DSI_PHY: base = dsi->phy_base; break; base 443 drivers/gpu/drm/omapdrm/dss/dsi.c case DSI_PLL: base = dsi->pll_base; break; base 447 drivers/gpu/drm/omapdrm/dss/dsi.c __raw_writel(val, base + idx.idx); base 452 drivers/gpu/drm/omapdrm/dss/dsi.c void __iomem *base; base 455 drivers/gpu/drm/omapdrm/dss/dsi.c case DSI_PROTO: base = dsi->proto_base; break; base 456 drivers/gpu/drm/omapdrm/dss/dsi.c case DSI_PHY: base = dsi->phy_base; break; base 457 drivers/gpu/drm/omapdrm/dss/dsi.c case DSI_PLL: base = dsi->pll_base; break; base 461 drivers/gpu/drm/omapdrm/dss/dsi.c return __raw_readl(base + idx.idx); base 5030 drivers/gpu/drm/omapdrm/dss/dsi.c pll->base = dsi->pll_base; base 97 drivers/gpu/drm/omapdrm/dss/dss.c __raw_writel(val, dss->base + idx.idx); base 102 drivers/gpu/drm/omapdrm/dss/dss.c return __raw_readl(dss->base + idx.idx); base 1428 drivers/gpu/drm/omapdrm/dss/dss.c dss->base = devm_ioremap_resource(&pdev->dev, dss_mem); base 1429 drivers/gpu/drm/omapdrm/dss/dss.c if (IS_ERR(dss->base)) { base 1430 drivers/gpu/drm/omapdrm/dss/dss.c r = PTR_ERR(dss->base); base 185 drivers/gpu/drm/omapdrm/dss/dss.h void __iomem *base; base 226 drivers/gpu/drm/omapdrm/dss/dss.h void __iomem *base; base 227 drivers/gpu/drm/omapdrm/dss/hdmi.h void __iomem *base; base 235 drivers/gpu/drm/omapdrm/dss/hdmi.h void __iomem *base; base 248 drivers/gpu/drm/omapdrm/dss/hdmi.h void __iomem *base; base 256 drivers/gpu/drm/omapdrm/dss/hdmi.h void __iomem *base; base 276 drivers/gpu/drm/omapdrm/dss/hdmi.h #define REG_FLD_MOD(base, idx, val, start, end) \ base 277 drivers/gpu/drm/omapdrm/dss/hdmi.h hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ base 279 drivers/gpu/drm/omapdrm/dss/hdmi.h #define REG_GET(base, idx, start, end) \ base 280 drivers/gpu/drm/omapdrm/dss/hdmi.h FLD_GET(hdmi_read_reg(base, idx), start, end) base 90 drivers/gpu/drm/omapdrm/dss/hdmi4.c u32 intr4 = hdmi_read_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4); base 92 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_write_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4, intr4); base 70 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff; base 83 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c msg.msg[0] = hdmi_read_reg(core->base, base 85 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c msg.msg[1] = hdmi_read_reg(core->base, base 91 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_read_reg(core->base, reg); base 97 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1); base 99 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1) base 105 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff; base 111 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0); base 112 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1); base 114 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0); base 115 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1); base 120 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); base 122 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3); base 128 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); base 140 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); base 142 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3); base 156 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 0x3); base 159 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c temp = hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL); base 173 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0); base 174 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0); base 175 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3); base 178 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); base 190 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); base 207 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, base 208 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1)); base 209 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, base 210 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0)); base 215 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3); base 221 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x22); base 226 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x02); base 229 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03); base 231 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x04); base 233 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c temp = hdmi_read_reg(core->base, HDMI_CEC_SETUP); base 236 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_SETUP, temp); base 243 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c temp = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1); base 245 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp); base 250 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); base 262 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, 0); base 263 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, 0); base 267 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0); base 269 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, v); base 271 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8); base 273 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, v); base 293 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, base 296 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, base 300 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4); base 303 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_TX_INIT, cec_msg_initiator(msg)); base 309 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_TX_DEST, temp); base 314 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_TX_COMMAND, msg->msg[1]); base 317 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_TX_OPERAND + i * 4, base 321 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_write_reg(core->base, HDMI_CEC_TRANSMIT_DATA, base 352 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); base 32 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c return core->base + HDMI_CORE_AV; base 37 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c void __iomem *base = core->base; base 40 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); base 43 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { base 45 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); base 47 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, base 55 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); base 58 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, base 65 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); base 68 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, base 80 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c void __iomem *base = core->base; base 86 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, base 96 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); base 99 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); base 102 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); base 105 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); base 106 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); base 110 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); base 112 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); base 115 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { base 120 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { base 129 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { base 136 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { base 144 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); base 202 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x1, 0, 0); base 208 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); base 214 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); base 222 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c void __iomem *core_sys_base = core->base; base 354 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c hdmi_read_reg(core->base, r)) base 925 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c core->base = devm_ioremap_resource(&pdev->dev, res); base 926 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (IS_ERR(core->base)) base 927 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c return PTR_ERR(core->base); base 88 drivers/gpu/drm/omapdrm/dss/hdmi5.c v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL); base 91 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_write_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); base 98 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); base 284 drivers/gpu/drm/omapdrm/dss/hdmi5.c idlemode = REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2); base 286 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); base 290 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); base 300 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); base 309 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); base 589 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2); base 40 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 55 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); base 56 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, base 61 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); base 65 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, base 67 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, base 72 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, base 74 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, base 79 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, base 81 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, base 86 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, base 88 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, base 93 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0); base 95 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0); base 96 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0); base 99 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7); base 102 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6); base 105 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3); base 108 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2); base 111 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3); base 114 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2); base 119 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 122 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); base 123 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); base 124 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); base 129 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 136 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0); base 146 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); base 148 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS, base 152 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1); base 154 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0); base 159 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0); base 179 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0); base 222 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_read_reg(core->base, r)) base 319 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 328 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); base 334 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r); base 337 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, vm->hactive >> 8, 4, 0); base 338 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, vm->hactive & 0xFF, 7, 0); base 341 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, vm->vactive >> 8, 4, 0); base 342 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, vm->vactive & 0xFF, 7, 0); base 345 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0); base 346 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0); base 349 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0); base 352 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, vm->hfront_porch >> 8, base 354 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, vm->hfront_porch & 0xFF, base 358 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, vm->vfront_porch, 7, 0); base 361 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (vm->hsync_len >> 8), base 363 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, vm->hsync_len & 0xFF, base 367 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, vm->vsync_len, 5, 0); base 370 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, base 374 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4); base 376 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4); base 381 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 385 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4); base 387 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6); base 389 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5); base 391 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3); base 393 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1); base 395 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2); base 397 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0); base 405 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4); base 413 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0); base 419 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 455 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0, base 458 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1, base 461 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2, base 464 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic); base 466 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3, base 469 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0); base 475 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 477 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0); base 478 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0); base 479 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0); base 480 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0); base 481 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0); base 482 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0); base 483 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0); base 484 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0); base 485 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0); base 486 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0); base 487 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0); base 488 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0); base 489 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0); base 490 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0); base 491 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0); base 492 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0); base 493 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0); base 494 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0); base 495 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0); base 496 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0); base 497 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0); base 498 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0); base 499 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0); base 500 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0); base 502 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0); base 517 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 521 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0); base 522 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0); base 523 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0); base 524 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0); base 525 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0); base 526 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0); base 527 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0); base 528 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1); base 533 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 536 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0); base 540 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0); base 541 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0); base 542 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0); base 543 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0); base 545 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2); base 546 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0); base 548 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0); base 550 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); base 551 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); base 552 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); base 554 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0); base 556 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); base 560 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); base 561 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0); base 562 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0); base 563 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0); base 565 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0); base 567 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0); base 569 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); base 571 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); base 577 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0); base 582 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 584 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0); base 585 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0); base 586 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0); base 587 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0); base 588 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); base 589 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0); base 590 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0); base 591 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); base 592 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0); base 645 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 649 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4); base 652 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0); base 653 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0); base 654 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0); base 660 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4); base 661 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0); base 662 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0); base 663 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0); base 667 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0); base 669 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0); base 673 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0); base 674 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4); base 682 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1); base 683 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5); base 684 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2); base 685 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6); base 689 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3); base 690 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7); base 694 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0); base 699 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4); base 704 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0); base 707 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1), base 712 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4); base 716 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0); base 719 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0); base 721 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4); base 723 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0); base 725 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4); base 727 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0); base 729 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4); base 731 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0); base 733 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4); base 736 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7), base 740 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8), base 744 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2); base 750 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); base 752 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0); base 755 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); base 757 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0); base 760 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); base 762 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0); base 766 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0); base 768 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1); base 770 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0); base 772 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0); base 775 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4); base 781 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c void __iomem *base = core->base; base 784 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0, base 788 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss); base 789 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca); base 790 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, base 901 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c core->base = devm_ioremap_resource(&pdev->dev, res); base 902 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c if (IS_ERR(core->base)) base 903 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c return PTR_ERR(core->base); base 22 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c hdmi_read_reg(phy->base, r)) base 119 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); base 120 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); base 132 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL); base 139 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); base 156 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); base 159 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); base 163 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); base 193 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c phy->base = devm_ioremap_resource(&pdev->dev, res); base 194 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c if (IS_ERR(phy->base)) base 195 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c return PTR_ERR(phy->base); base 26 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c hdmi_read_reg(pll->base, r)) base 144 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->base = hpll->base; base 171 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->base = devm_ioremap_resource(&pdev->dev, res); base 172 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c if (IS_ERR(pll->base)) base 173 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c return PTR_ERR(pll->base); base 22 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) base 46 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); base 51 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); base 53 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); base 58 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); base 63 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); base 70 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) base 74 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); base 77 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) base 90 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); base 93 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) base 104 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); base 113 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE); base 115 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); base 122 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW); base 135 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, base 140 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l); base 153 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); base 160 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r); base 184 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); base 189 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v); base 232 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG); base 243 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r); base 253 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2); base 256 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r); base 258 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL); base 261 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r); base 266 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); base 273 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); base 284 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c wp->base = devm_ioremap_resource(&pdev->dev, res); base 285 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (IS_ERR(wp->base)) base 286 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c return PTR_ERR(wp->base); base 352 drivers/gpu/drm/omapdrm/dss/pll.c void __iomem *base = pll->base; base 354 drivers/gpu/drm/omapdrm/dss/pll.c if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1) base 365 drivers/gpu/drm/omapdrm/dss/pll.c u32 v = readl_relaxed(pll->base + PLL_STATUS); base 394 drivers/gpu/drm/omapdrm/dss/pll.c void __iomem *base = pll->base; base 409 drivers/gpu/drm/omapdrm/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION1); base 418 drivers/gpu/drm/omapdrm/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION3); base 420 drivers/gpu/drm/omapdrm/dss/pll.c l = readl_relaxed(base + PLL_CONFIGURATION2); base 443 drivers/gpu/drm/omapdrm/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION2); base 457 drivers/gpu/drm/omapdrm/dss/pll.c writel_relaxed(1, base + PLL_GO); /* PLL_GO */ base 463 drivers/gpu/drm/omapdrm/dss/pll.c readl_relaxed(base + PLL_GO); base 466 drivers/gpu/drm/omapdrm/dss/pll.c l = readl_relaxed(base + PLL_STATUS); base 469 drivers/gpu/drm/omapdrm/dss/pll.c !(readl_relaxed(base + PLL_GO) & 0x1)) base 480 drivers/gpu/drm/omapdrm/dss/pll.c writel_relaxed(1, base + PLL_GO); /* PLL_GO */ base 482 drivers/gpu/drm/omapdrm/dss/pll.c if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) { base 488 drivers/gpu/drm/omapdrm/dss/pll.c if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { base 495 drivers/gpu/drm/omapdrm/dss/pll.c l = readl_relaxed(base + PLL_CONFIGURATION2); base 502 drivers/gpu/drm/omapdrm/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION2); base 522 drivers/gpu/drm/omapdrm/dss/pll.c void __iomem *base = pll->base; base 528 drivers/gpu/drm/omapdrm/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION1); base 530 drivers/gpu/drm/omapdrm/dss/pll.c l = readl_relaxed(base + PLL_CONFIGURATION2); base 542 drivers/gpu/drm/omapdrm/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION2); base 544 drivers/gpu/drm/omapdrm/dss/pll.c l = readl_relaxed(base + PLL_CONFIGURATION3); base 546 drivers/gpu/drm/omapdrm/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION3); base 548 drivers/gpu/drm/omapdrm/dss/pll.c l = readl_relaxed(base + PLL_CONFIGURATION4); base 551 drivers/gpu/drm/omapdrm/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION4); base 553 drivers/gpu/drm/omapdrm/dss/pll.c writel_relaxed(1, base + PLL_GO); /* PLL_GO */ base 555 drivers/gpu/drm/omapdrm/dss/pll.c if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) { base 560 drivers/gpu/drm/omapdrm/dss/pll.c if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { base 291 drivers/gpu/drm/omapdrm/dss/venc.c void __iomem *base; base 312 drivers/gpu/drm/omapdrm/dss/venc.c __raw_writel(val, venc->base + idx); base 317 drivers/gpu/drm/omapdrm/dss/venc.c u32 l = __raw_readl(venc->base + idx); base 847 drivers/gpu/drm/omapdrm/dss/venc.c venc->base = devm_ioremap_resource(&pdev->dev, venc_mem); base 848 drivers/gpu/drm/omapdrm/dss/venc.c if (IS_ERR(venc->base)) { base 849 drivers/gpu/drm/omapdrm/dss/venc.c r = PTR_ERR(venc->base); base 183 drivers/gpu/drm/omapdrm/dss/video-pll.c pll->base = pll_base; base 18 drivers/gpu/drm/omapdrm/omap_connector.c #define to_omap_connector(x) container_of(x, struct omap_connector, base) base 21 drivers/gpu/drm/omapdrm/omap_connector.c struct drm_connector base; base 51 drivers/gpu/drm/omapdrm/omap_connector.c struct drm_connector *connector = &omap_connector->base; base 346 drivers/gpu/drm/omapdrm/omap_connector.c connector = &omap_connector->base; base 18 drivers/gpu/drm/omapdrm/omap_crtc.c #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base) base 22 drivers/gpu/drm/omapdrm/omap_crtc.c struct drm_crtc_state base; base 29 drivers/gpu/drm/omapdrm/omap_crtc.c #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) base 32 drivers/gpu/drm/omapdrm/omap_crtc.c struct drm_crtc base; base 191 drivers/gpu/drm/omapdrm/omap_crtc.c omap_crtc_set_enabled(&omap_crtc->base, true); base 202 drivers/gpu/drm/omapdrm/omap_crtc.c omap_crtc_set_enabled(&omap_crtc->base, false); base 234 drivers/gpu/drm/omapdrm/omap_crtc.c struct drm_device *dev = omap_crtc->base.dev; base 253 drivers/gpu/drm/omapdrm/omap_crtc.c struct drm_device *dev = omap_crtc->base.dev; base 294 drivers/gpu/drm/omapdrm/omap_crtc.c struct drm_device *dev = omap_crtc->base.dev; base 367 drivers/gpu/drm/omapdrm/omap_crtc.c struct drm_device *dev = omap_crtc->base.dev; base 724 drivers/gpu/drm/omapdrm/omap_crtc.c __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); base 730 drivers/gpu/drm/omapdrm/omap_crtc.c return &state->base; base 797 drivers/gpu/drm/omapdrm/omap_crtc.c crtc = &omap_crtc->base; base 843 drivers/gpu/drm/omapdrm/omap_crtc.c omap_plane_install_properties(crtc->primary, &crtc->base); base 163 drivers/gpu/drm/omapdrm/omap_dmm_priv.h void __iomem *base; base 122 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c return readl(dmm->base + reg); base 154 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c writel(val, dmm->base + reg); base 170 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c return readl(dmm->base + reg); base 183 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c writel(val, dmm->base + reg); base 771 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c iounmap(omap_dmm->base); base 817 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c omap_dmm->base = ioremap(mem->start, SZ_2K); base 819 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c if (!omap_dmm->base) { base 20 drivers/gpu/drm/omapdrm/omap_encoder.c #define to_omap_encoder(x) container_of(x, struct omap_encoder, base) base 28 drivers/gpu/drm/omapdrm/omap_encoder.c struct drm_encoder base; base 261 drivers/gpu/drm/omapdrm/omap_encoder.c encoder = &omap_encoder->base; base 47 drivers/gpu/drm/omapdrm/omap_fb.c #define to_omap_framebuffer(x) container_of(x, struct omap_framebuffer, base) base 50 drivers/gpu/drm/omapdrm/omap_fb.c struct drm_framebuffer base; base 370 drivers/gpu/drm/omapdrm/omap_fb.c fb = &omap_fb->base; base 420 drivers/gpu/drm/omapdrm/omap_fb.c DBG("create: FB ID: %d (%p)", fb->base.id, fb); base 23 drivers/gpu/drm/omapdrm/omap_fbdev.c #define to_omap_fbdev(x) container_of(x, struct omap_fbdev, base) base 26 drivers/gpu/drm/omapdrm/omap_fbdev.c struct drm_fb_helper base; base 40 drivers/gpu/drm/omapdrm/omap_fbdev.c struct fb_info *fbi = fbdev->base.fbdev; base 241 drivers/gpu/drm/omapdrm/omap_fbdev.c helper = &fbdev->base; base 29 drivers/gpu/drm/omapdrm/omap_gem.c struct drm_gem_object base; base 98 drivers/gpu/drm/omapdrm/omap_gem.c #define to_omap_bo(x) container_of(x, struct omap_gem_object, base) base 997 drivers/gpu/drm/omapdrm/omap_gem.c struct drm_gem_object *obj = &omap_obj->base; base 1060 drivers/gpu/drm/omapdrm/omap_gem.c struct drm_gem_object *obj = &omap_obj->base; base 1173 drivers/gpu/drm/omapdrm/omap_gem.c obj = &omap_obj->base; base 18 drivers/gpu/drm/omapdrm/omap_plane.c #define to_omap_plane(x) container_of(x, struct omap_plane, base) base 21 drivers/gpu/drm/omapdrm/omap_plane.c struct drm_plane base; base 170 drivers/gpu/drm/omapdrm/omap_plane.c if (plane->rotation_property && obj != &plane->base) base 280 drivers/gpu/drm/omapdrm/omap_plane.c plane = &omap_plane->base; base 290 drivers/gpu/drm/omapdrm/omap_plane.c omap_plane_install_properties(plane, &plane->base); base 51 drivers/gpu/drm/panel/panel-innolux-p079zca.c struct drm_panel base; base 65 drivers/gpu/drm/panel/panel-innolux-p079zca.c return container_of(panel, struct innolux_panel, base); base 490 drivers/gpu/drm/panel/panel-innolux-p079zca.c drm_panel_init(&innolux->base); base 491 drivers/gpu/drm/panel/panel-innolux-p079zca.c innolux->base.funcs = &innolux_panel_funcs; base 492 drivers/gpu/drm/panel/panel-innolux-p079zca.c innolux->base.dev = dev; base 494 drivers/gpu/drm/panel/panel-innolux-p079zca.c err = drm_panel_add(&innolux->base); base 506 drivers/gpu/drm/panel/panel-innolux-p079zca.c drm_panel_remove(&innolux->base); base 531 drivers/gpu/drm/panel/panel-innolux-p079zca.c err = innolux_panel_unprepare(&innolux->base); base 536 drivers/gpu/drm/panel/panel-innolux-p079zca.c err = innolux_panel_disable(&innolux->base); base 554 drivers/gpu/drm/panel/panel-innolux-p079zca.c innolux_panel_unprepare(&innolux->base); base 555 drivers/gpu/drm/panel/panel-innolux-p079zca.c innolux_panel_disable(&innolux->base); base 34 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c struct drm_panel base; base 52 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c return container_of(panel, struct jdi_panel, base); base 440 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c drm_panel_init(&jdi->base); base 441 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c jdi->base.funcs = &jdi_panel_funcs; base 442 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c jdi->base.dev = &jdi->dsi->dev; base 444 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c ret = drm_panel_add(&jdi->base); base 451 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c if (jdi->base.dev) base 452 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c drm_panel_remove(&jdi->base); base 485 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c ret = jdi_panel_disable(&jdi->base); base 503 drivers/gpu/drm/panel/panel-jdi-lt070me05000.c jdi_panel_disable(&jdi->base); base 23 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c struct drm_panel base; base 183 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c return container_of(panel, struct kingdisplay_panel, base); base 394 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c drm_panel_init(&kingdisplay->base); base 395 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c kingdisplay->base.funcs = &kingdisplay_panel_funcs; base 396 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c kingdisplay->base.dev = &kingdisplay->link->dev; base 398 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c return drm_panel_add(&kingdisplay->base); base 403 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c drm_panel_remove(&kingdisplay->base); base 435 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c err = kingdisplay_panel_unprepare(&kingdisplay->base); base 440 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c err = kingdisplay_panel_disable(&kingdisplay->base); base 458 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c kingdisplay_panel_unprepare(&kingdisplay->base); base 459 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c kingdisplay_panel_disable(&kingdisplay->base); base 20 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c struct drm_panel base; base 34 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c return container_of(panel, struct osd101t2587_panel, base); base 169 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c drm_panel_init(&osd101t2587->base); base 170 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c osd101t2587->base.funcs = &osd101t2587_panel_funcs; base 171 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c osd101t2587->base.dev = &osd101t2587->dsi->dev; base 173 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c return drm_panel_add(&osd101t2587->base); base 208 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c drm_panel_remove(&osd101t2587->base); base 218 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c ret = osd101t2587_panel_disable(&osd101t2587->base); base 222 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c osd101t2587_panel_unprepare(&osd101t2587->base); base 224 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c drm_panel_remove(&osd101t2587->base); base 237 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c osd101t2587_panel_disable(&osd101t2587->base); base 238 drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c osd101t2587_panel_unprepare(&osd101t2587->base); base 31 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c struct drm_panel base; base 47 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c return container_of(panel, struct wuxga_nt_panel, base); base 226 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c drm_panel_init(&wuxga_nt->base); base 227 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c wuxga_nt->base.funcs = &wuxga_nt_panel_funcs; base 228 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c wuxga_nt->base.dev = &wuxga_nt->dsi->dev; base 230 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c ret = drm_panel_add(&wuxga_nt->base); base 245 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c if (wuxga_nt->base.dev) base 246 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c drm_panel_remove(&wuxga_nt->base); base 284 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c ret = wuxga_nt_panel_disable(&wuxga_nt->base); base 301 drivers/gpu/drm/panel/panel-panasonic-vvx10f034n00.c wuxga_nt_panel_disable(&wuxga_nt->base); base 195 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c struct drm_panel base; base 220 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c return container_of(panel, struct rpi_touchscreen, base); base 429 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c drm_panel_init(&ts->base); base 430 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c ts->base.dev = dev; base 431 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c ts->base.funcs = &rpi_touchscreen_funcs; base 436 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c ret = drm_panel_add(&ts->base); base 453 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c drm_panel_remove(&ts->base); base 45 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c struct drm_panel base; base 56 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c return container_of(panel, struct seiko_panel, base); base 61 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c struct drm_connector *connector = panel->base.connector; base 62 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c struct drm_device *drm = panel->base.drm; base 277 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c drm_panel_init(&panel->base); base 278 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c panel->base.dev = dev; base 279 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c panel->base.funcs = &seiko_panel_funcs; base 281 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c err = drm_panel_add(&panel->base); base 294 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c drm_panel_remove(&panel->base); base 296 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c seiko_panel_disable(&panel->base); base 308 drivers/gpu/drm/panel/panel-seiko-43wvf1g.c seiko_panel_disable(&panel->base); base 21 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c struct drm_panel base; base 37 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c return container_of(panel, struct sharp_panel, base); base 332 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c drm_panel_init(&sharp->base); base 333 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c sharp->base.funcs = &sharp_panel_funcs; base 334 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c sharp->base.dev = &sharp->link1->dev; base 336 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c return drm_panel_add(&sharp->base); base 341 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c if (sharp->base.dev) base 342 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c drm_panel_remove(&sharp->base); base 411 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c err = sharp_panel_disable(&sharp->base); base 432 drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c sharp_panel_disable(&sharp->base); base 25 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c struct drm_panel base; base 40 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c return container_of(panel, struct sharp_nt_panel, base); base 267 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c drm_panel_init(&sharp_nt->base); base 268 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c sharp_nt->base.funcs = &sharp_nt_panel_funcs; base 269 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c sharp_nt->base.dev = &sharp_nt->dsi->dev; base 271 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c return drm_panel_add(&sharp_nt->base); base 276 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c if (sharp_nt->base.dev) base 277 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c drm_panel_remove(&sharp_nt->base); base 312 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c ret = sharp_nt_panel_disable(&sharp_nt->base); base 329 drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c sharp_nt_panel_disable(&sharp_nt->base); base 100 drivers/gpu/drm/panel/panel-simple.c struct drm_panel base; base 118 drivers/gpu/drm/panel/panel-simple.c return container_of(panel, struct panel_simple, base); base 123 drivers/gpu/drm/panel/panel-simple.c struct drm_connector *connector = panel->base.connector; base 124 drivers/gpu/drm/panel/panel-simple.c struct drm_device *drm = panel->base.drm; base 156 drivers/gpu/drm/panel/panel-simple.c struct drm_connector *connector = panel->base.connector; base 157 drivers/gpu/drm/panel/panel-simple.c struct drm_device *drm = panel->base.drm; base 187 drivers/gpu/drm/panel/panel-simple.c struct drm_connector *connector = panel->base.connector; base 188 drivers/gpu/drm/panel/panel-simple.c struct drm_device *drm = panel->base.drm; base 467 drivers/gpu/drm/panel/panel-simple.c drm_panel_init(&panel->base); base 468 drivers/gpu/drm/panel/panel-simple.c panel->base.dev = dev; base 469 drivers/gpu/drm/panel/panel-simple.c panel->base.funcs = &panel_simple_funcs; base 471 drivers/gpu/drm/panel/panel-simple.c err = drm_panel_add(&panel->base); base 493 drivers/gpu/drm/panel/panel-simple.c drm_panel_remove(&panel->base); base 495 drivers/gpu/drm/panel/panel-simple.c panel_simple_disable(&panel->base); base 496 drivers/gpu/drm/panel/panel-simple.c panel_simple_unprepare(&panel->base); base 511 drivers/gpu/drm/panel/panel-simple.c panel_simple_disable(&panel->base); base 512 drivers/gpu/drm/panel/panel-simple.c panel_simple_unprepare(&panel->base); base 3738 drivers/gpu/drm/panel/panel-simple.c drm_panel_remove(&panel->base); base 102 drivers/gpu/drm/panfrost/panfrost_drv.c drm_gem_object_put_unlocked(&bo->base.base); base 431 drivers/gpu/drm/panfrost/panfrost_drv.c list_add_tail(&bo->base.madv_list, base 434 drivers/gpu/drm/panfrost/panfrost_drv.c list_del_init(&bo->base.madv_list); base 29 drivers/gpu/drm/panfrost/panfrost_gem.c list_del_init(&bo->base.madv_list); base 40 drivers/gpu/drm/panfrost/panfrost_gem.c int n_sgt = bo->base.base.size / SZ_2M; base 96 drivers/gpu/drm/panfrost/panfrost_gem.c drm_gem_object_put_unlocked(&mapping->obj->base.base); base 163 drivers/gpu/drm/panfrost/panfrost_gem.c WARN_ON(bo->base.madv != PANFROST_MADV_WILLNEED); base 231 drivers/gpu/drm/panfrost/panfrost_gem.c obj->base.base.funcs = &panfrost_gem_funcs; base 233 drivers/gpu/drm/panfrost/panfrost_gem.c return &obj->base.base; base 254 drivers/gpu/drm/panfrost/panfrost_gem.c bo = to_panfrost_bo(&shmem->base); base 262 drivers/gpu/drm/panfrost/panfrost_gem.c ret = drm_gem_handle_create(file_priv, &shmem->base, handle); base 264 drivers/gpu/drm/panfrost/panfrost_gem.c drm_gem_object_put_unlocked(&shmem->base); base 13 drivers/gpu/drm/panfrost/panfrost_gem.h struct drm_gem_shmem_object base; base 55 drivers/gpu/drm/panfrost/panfrost_gem.h return container_of(to_drm_gem_shmem_obj(obj), struct panfrost_gem_object, base); base 31 drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c count += shmem->base.size >> PAGE_SHIFT; base 72 drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c panfrost_gem_purge(&shmem->base)) { base 73 drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c freed += shmem->base.size >> PAGE_SHIFT; base 41 drivers/gpu/drm/panfrost/panfrost_job.c return container_of(sched_job, struct panfrost_job, base); base 45 drivers/gpu/drm/panfrost/panfrost_job.c struct dma_fence base; base 96 drivers/gpu/drm/panfrost/panfrost_job.c dma_fence_init(&fence->base, &panfrost_fence_ops, &js->job_lock, base 99 drivers/gpu/drm/panfrost/panfrost_job.c return &fence->base; base 227 drivers/gpu/drm/panfrost/panfrost_job.c ret = drm_sched_job_init(&job->base, entity, NULL); base 233 drivers/gpu/drm/panfrost/panfrost_job.c job->render_done_fence = dma_fence_get(&job->base.s_fence->finished); base 240 drivers/gpu/drm/panfrost/panfrost_job.c drm_sched_entity_push_job(&job->base, entity); base 346 drivers/gpu/drm/panfrost/panfrost_job.c if (unlikely(job->base.s_fence->finished.error)) base 15 drivers/gpu/drm/panfrost/panfrost_job.h struct drm_sched_job base; base 280 drivers/gpu/drm/panfrost/panfrost_mmu.c struct drm_gem_object *obj = &bo->base.base; base 305 drivers/gpu/drm/panfrost/panfrost_mmu.c struct drm_gem_object *obj = &bo->base.base; base 475 drivers/gpu/drm/panfrost/panfrost_mmu.c mutex_lock(&bo->base.pages_lock); base 477 drivers/gpu/drm/panfrost/panfrost_mmu.c if (!bo->base.pages) { base 478 drivers/gpu/drm/panfrost/panfrost_mmu.c bo->sgts = kvmalloc_array(bo->base.base.size / SZ_2M, base 481 drivers/gpu/drm/panfrost/panfrost_mmu.c mutex_unlock(&bo->base.pages_lock); base 486 drivers/gpu/drm/panfrost/panfrost_mmu.c pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT, base 491 drivers/gpu/drm/panfrost/panfrost_mmu.c mutex_unlock(&bo->base.pages_lock); base 495 drivers/gpu/drm/panfrost/panfrost_mmu.c bo->base.pages = pages; base 496 drivers/gpu/drm/panfrost/panfrost_mmu.c bo->base.pages_use_count = 1; base 498 drivers/gpu/drm/panfrost/panfrost_mmu.c pages = bo->base.pages; base 500 drivers/gpu/drm/panfrost/panfrost_mmu.c mapping = bo->base.base.filp->f_mapping; base 506 drivers/gpu/drm/panfrost/panfrost_mmu.c mutex_unlock(&bo->base.pages_lock); base 512 drivers/gpu/drm/panfrost/panfrost_mmu.c mutex_unlock(&bo->base.pages_lock); base 539 drivers/gpu/drm/panfrost/panfrost_mmu.c drm_gem_shmem_put_pages(&bo->base); base 541 drivers/gpu/drm/panfrost/panfrost_mmu.c drm_gem_object_put_unlocked(&bo->base.base); base 93 drivers/gpu/drm/panfrost/panfrost_perfcnt.c ret = panfrost_gem_open(&bo->base, file_priv); base 97 drivers/gpu/drm/panfrost/panfrost_perfcnt.c perfcnt->mapping = panfrost_gem_mapping_get(to_panfrost_bo(&bo->base), base 104 drivers/gpu/drm/panfrost/panfrost_perfcnt.c perfcnt->buf = drm_gem_shmem_vmap(&bo->base); base 159 drivers/gpu/drm/panfrost/panfrost_perfcnt.c drm_gem_object_put_unlocked(&bo->base); base 164 drivers/gpu/drm/panfrost/panfrost_perfcnt.c drm_gem_shmem_vunmap(&bo->base, perfcnt->buf); base 168 drivers/gpu/drm/panfrost/panfrost_perfcnt.c panfrost_gem_close(&bo->base, file_priv); base 170 drivers/gpu/drm/panfrost/panfrost_perfcnt.c drm_gem_object_put_unlocked(&bo->base); base 191 drivers/gpu/drm/panfrost/panfrost_perfcnt.c drm_gem_shmem_vunmap(&perfcnt->mapping->obj->base.base, perfcnt->buf); base 193 drivers/gpu/drm/panfrost/panfrost_perfcnt.c panfrost_gem_close(&perfcnt->mapping->obj->base.base, file_priv); base 380 drivers/gpu/drm/qxl/qxl_cmd.c drm_gem_object_put_unlocked(&qdev->primary_bo->tbo.base); base 407 drivers/gpu/drm/qxl/qxl_cmd.c drm_gem_object_get(&qdev->primary_bo->tbo.base); base 64 drivers/gpu/drm/qxl/qxl_debugfs.c fobj = rcu_dereference(bo->tbo.base.resv->fence); base 69 drivers/gpu/drm/qxl/qxl_debugfs.c (unsigned long)bo->tbo.base.size, base 155 drivers/gpu/drm/qxl/qxl_display.c drm_object_property_set_value(&connector->base, base 157 drivers/gpu/drm/qxl/qxl_display.c drm_object_property_set_value(&connector->base, base 800 drivers/gpu/drm/qxl/qxl_display.c (&qdev->dumb_shadow_bo->tbo.base); base 810 drivers/gpu/drm/qxl/qxl_display.c (&user_bo->shadow->tbo.base); base 813 drivers/gpu/drm/qxl/qxl_display.c drm_gem_object_get(&qdev->dumb_shadow_bo->tbo.base); base 844 drivers/gpu/drm/qxl/qxl_display.c drm_gem_object_put_unlocked(&user_bo->shadow->tbo.base); base 958 drivers/gpu/drm/qxl/qxl_display.c r = drm_crtc_init_with_planes(dev, &qxl_crtc->base, primary, cursor, base 964 drivers/gpu/drm/qxl/qxl_display.c drm_crtc_helper_add(&qxl_crtc->base, &qxl_crtc_helper_funcs); base 1110 drivers/gpu/drm/qxl/qxl_display.c connector = &qxl_output->base; base 1112 drivers/gpu/drm/qxl/qxl_display.c drm_connector_init(dev, &qxl_output->base, base 1121 drivers/gpu/drm/qxl/qxl_display.c drm_connector_attach_encoder(&qxl_output->base, base 1126 drivers/gpu/drm/qxl/qxl_display.c drm_object_attach_property(&connector->base, base 1128 drivers/gpu/drm/qxl/qxl_display.c drm_object_attach_property(&connector->base, base 1130 drivers/gpu/drm/qxl/qxl_display.c drm_object_attach_property(&connector->base, base 96 drivers/gpu/drm/qxl/qxl_drv.h #define gem_to_qxl_bo(gobj) container_of((gobj), struct qxl_bo, tbo.base) base 109 drivers/gpu/drm/qxl/qxl_drv.h struct drm_crtc base; base 117 drivers/gpu/drm/qxl/qxl_drv.h struct drm_connector base; base 121 drivers/gpu/drm/qxl/qxl_drv.h #define to_qxl_crtc(x) container_of(x, struct qxl_crtc, base) base 122 drivers/gpu/drm/qxl/qxl_drv.h #define drm_connector_to_qxl_output(x) container_of(x, struct qxl_output, base) base 149 drivers/gpu/drm/qxl/qxl_drv.h struct dma_fence base; base 66 drivers/gpu/drm/qxl/qxl_gem.c *obj = &qbo->tbo.base; base 36 drivers/gpu/drm/qxl/qxl_object.c qdev = (struct qxl_device *)bo->tbo.base.dev->dev_private; base 43 drivers/gpu/drm/qxl/qxl_object.c drm_gem_object_release(&bo->tbo.base); base 98 drivers/gpu/drm/qxl/qxl_object.c r = drm_gem_object_init(&qdev->ddev, &bo->tbo.base, size); base 217 drivers/gpu/drm/qxl/qxl_object.c drm_gem_object_put_unlocked(&(*bo)->tbo.base); base 223 drivers/gpu/drm/qxl/qxl_object.c drm_gem_object_get(&bo->tbo.base); base 230 drivers/gpu/drm/qxl/qxl_object.c struct drm_device *ddev = bo->tbo.base.dev; base 250 drivers/gpu/drm/qxl/qxl_object.c struct drm_device *ddev = bo->tbo.base.dev; base 313 drivers/gpu/drm/qxl/qxl_object.c &bo->tbo.base, bo, (unsigned long)bo->tbo.base.size, base 314 drivers/gpu/drm/qxl/qxl_object.c *((unsigned long *)&bo->tbo.base.refcount)); base 319 drivers/gpu/drm/qxl/qxl_object.c drm_gem_object_put_unlocked(&bo->tbo.base); base 37 drivers/gpu/drm/qxl/qxl_object.h struct drm_device *ddev = bo->tbo.base.dev; base 63 drivers/gpu/drm/qxl/qxl_object.h return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); base 74 drivers/gpu/drm/qxl/qxl_object.h struct drm_device *ddev = bo->tbo.base.dev; base 67 drivers/gpu/drm/qxl/qxl_release.c release = container_of(fence, struct qxl_release, base); base 136 drivers/gpu/drm/qxl/qxl_release.c release->base.ops = NULL; base 145 drivers/gpu/drm/qxl/qxl_release.c release->base.seqno = ++qdev->release_seqno; base 189 drivers/gpu/drm/qxl/qxl_release.c if (release->base.ops) { base 193 drivers/gpu/drm/qxl/qxl_release.c dma_fence_signal(&release->base); base 194 drivers/gpu/drm/qxl/qxl_release.c dma_fence_put(&release->base); base 241 drivers/gpu/drm/qxl/qxl_release.c ret = dma_resv_reserve_shared(bo->tbo.base.resv, 1); base 246 drivers/gpu/drm/qxl/qxl_release.c ret = qxl_bo_check_id(bo->tbo.base.dev->dev_private, bo); base 450 drivers/gpu/drm/qxl/qxl_release.c dma_fence_init(&release->base, &qxl_fence_ops, &qdev->release_lock, base 451 drivers/gpu/drm/qxl/qxl_release.c release->id | 0xf0000000, release->base.seqno); base 452 drivers/gpu/drm/qxl/qxl_release.c trace_dma_fence_emit(&release->base); base 461 drivers/gpu/drm/qxl/qxl_release.c dma_resv_add_shared_fence(bo->base.resv, &release->base); base 463 drivers/gpu/drm/qxl/qxl_release.c dma_resv_unlock(bo->base.resv); base 158 drivers/gpu/drm/qxl/qxl_ttm.c return drm_vma_node_verify_access(&qbo->tbo.base.vma_node, base 171 drivers/gpu/drm/qxl/qxl_ttm.c mem->bus.base = 0; base 181 drivers/gpu/drm/qxl/qxl_ttm.c mem->bus.base = qdev->vram_base; base 186 drivers/gpu/drm/qxl/qxl_ttm.c mem->bus.base = qdev->surfaceram_base; base 300 drivers/gpu/drm/qxl/qxl_ttm.c qdev = qbo->tbo.base.dev->dev_private; base 323 drivers/gpu/drm/r128/r128_cce.c ring_start = dev_priv->cce_ring->offset - dev->agp->base; base 541 drivers/gpu/drm/r128/r128_cce.c dev_priv->cce_buffers_offset = dev->agp->base; base 107 drivers/gpu/drm/radeon/atom.c static uint32_t atom_iio_execute(struct atom_context *ctx, int base, base 114 drivers/gpu/drm/radeon/atom.c switch (CU8(base)) { base 116 drivers/gpu/drm/radeon/atom.c base++; base 119 drivers/gpu/drm/radeon/atom.c temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1)); base 120 drivers/gpu/drm/radeon/atom.c base += 3; base 124 drivers/gpu/drm/radeon/atom.c (void)ctx->card->ioreg_read(ctx->card, CU16(base + 1)); base 125 drivers/gpu/drm/radeon/atom.c ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); base 126 drivers/gpu/drm/radeon/atom.c base += 3; base 130 drivers/gpu/drm/radeon/atom.c ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << base 131 drivers/gpu/drm/radeon/atom.c CU8(base + 2)); base 132 drivers/gpu/drm/radeon/atom.c base += 3; base 136 drivers/gpu/drm/radeon/atom.c (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + base 138 drivers/gpu/drm/radeon/atom.c base += 3; base 142 drivers/gpu/drm/radeon/atom.c ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << base 143 drivers/gpu/drm/radeon/atom.c CU8(base + 3)); base 145 drivers/gpu/drm/radeon/atom.c ((index >> CU8(base + 2)) & base 146 drivers/gpu/drm/radeon/atom.c (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + base 148 drivers/gpu/drm/radeon/atom.c base += 4; base 152 drivers/gpu/drm/radeon/atom.c ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << base 153 drivers/gpu/drm/radeon/atom.c CU8(base + 3)); base 155 drivers/gpu/drm/radeon/atom.c ((data >> CU8(base + 2)) & base 156 drivers/gpu/drm/radeon/atom.c (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + base 158 drivers/gpu/drm/radeon/atom.c base += 4; base 162 drivers/gpu/drm/radeon/atom.c ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << base 163 drivers/gpu/drm/radeon/atom.c CU8(base + 3)); base 166 drivers/gpu/drm/radeon/atom.c io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - base 168 drivers/gpu/drm/radeon/atom.c (base base 171 drivers/gpu/drm/radeon/atom.c << CU8(base + 3); base 172 drivers/gpu/drm/radeon/atom.c base += 4; base 1160 drivers/gpu/drm/radeon/atom.c int base = CU16(ctx->cmd_table + 4 + 2 * index); base 1166 drivers/gpu/drm/radeon/atom.c if (!base) base 1169 drivers/gpu/drm/radeon/atom.c len = CU16(base + ATOM_CT_SIZE_PTR); base 1170 drivers/gpu/drm/radeon/atom.c ws = CU8(base + ATOM_CT_WS_PTR); base 1171 drivers/gpu/drm/radeon/atom.c ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; base 1172 drivers/gpu/drm/radeon/atom.c ptr = base + ATOM_CT_CODE_PTR; base 1174 drivers/gpu/drm/radeon/atom.c SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); base 1178 drivers/gpu/drm/radeon/atom.c ectx.start = base; base 1196 drivers/gpu/drm/radeon/atom.c base, len, ws, ps, ptr - 1); base 1251 drivers/gpu/drm/radeon/atom.c static void atom_index_iio(struct atom_context *ctx, int base) base 1256 drivers/gpu/drm/radeon/atom.c while (CU8(base) == ATOM_IIO_START) { base 1257 drivers/gpu/drm/radeon/atom.c ctx->iio[CU8(base + 1)] = base + 2; base 1258 drivers/gpu/drm/radeon/atom.c base += 2; base 1259 drivers/gpu/drm/radeon/atom.c while (CU8(base) != ATOM_IIO_END) base 1260 drivers/gpu/drm/radeon/atom.c base += atom_iio_len[CU8(base)]; base 1261 drivers/gpu/drm/radeon/atom.c base += 3; base 1267 drivers/gpu/drm/radeon/atom.c int base; base 1293 drivers/gpu/drm/radeon/atom.c base = CU16(ATOM_ROM_TABLE_PTR); base 1295 drivers/gpu/drm/radeon/atom.c (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, base 1302 drivers/gpu/drm/radeon/atom.c ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); base 1303 drivers/gpu/drm/radeon/atom.c ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); base 1310 drivers/gpu/drm/radeon/atom.c str = CSTR(CU16(base + ATOM_ROM_MSG_PTR)); base 763 drivers/gpu/drm/radeon/atombios_crtc.c SET_PIXEL_CLOCK_PS_ALLOCATION base; base 2275 drivers/gpu/drm/radeon/atombios_crtc.c drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); base 94 drivers/gpu/drm/radeon/atombios_dp.c unsigned char *base; base 103 drivers/gpu/drm/radeon/atombios_dp.c base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); base 105 drivers/gpu/drm/radeon/atombios_dp.c radeon_atom_copy_swap(base, send, send_bytes, true); base 145 drivers/gpu/drm/radeon/atombios_dp.c radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); base 229 drivers/gpu/drm/radeon/atombios_dp.c struct drm_device *dev = radeon_connector->base.dev; base 234 drivers/gpu/drm/radeon/atombios_dp.c radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; base 362 drivers/gpu/drm/radeon/atombios_dp.c struct drm_device *dev = radeon_connector->base.dev; base 83 drivers/gpu/drm/radeon/atombios_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 95 drivers/gpu/drm/radeon/atombios_encoders.c struct drm_encoder *encoder = &radeon_encoder->base; base 96 drivers/gpu/drm/radeon/atombios_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 174 drivers/gpu/drm/radeon/atombios_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 188 drivers/gpu/drm/radeon/atombios_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 258 drivers/gpu/drm/radeon/atombios_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 1392 drivers/gpu/drm/radeon/atombios_encoders.c struct drm_device *dev = radeon_connector->base.dev; base 2692 drivers/gpu/drm/radeon/atombios_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 2749 drivers/gpu/drm/radeon/atombios_encoders.c encoder = &radeon_encoder->base; base 44 drivers/gpu/drm/radeon/atombios_i2c.c unsigned char *base; base 53 drivers/gpu/drm/radeon/atombios_i2c.c base = (unsigned char *)rdev->mode_info.atom_context->scratch; base 96 drivers/gpu/drm/radeon/atombios_i2c.c radeon_atom_copy_swap(buf, base, num, false); base 8835 drivers/gpu/drm/radeon/cik.c if (radeon_crtc->base.enabled && mode) { base 8867 drivers/gpu/drm/radeon/cik.c if (radeon_crtc->base.enabled && mode) { base 9254 drivers/gpu/drm/radeon/cik.c struct drm_display_mode *mode = &radeon_crtc->base.mode; base 9261 drivers/gpu/drm/radeon/cik.c if (radeon_crtc->base.enabled && num_heads && mode) { base 9398 drivers/gpu/drm/radeon/cik.c if (rdev->mode_info.crtcs[i]->base.enabled) base 9402 drivers/gpu/drm/radeon/cik.c mode = &rdev->mode_info.crtcs[i]->base.mode; base 1851 drivers/gpu/drm/radeon/evergreen.c if (radeon_crtc->base.enabled && mode) { base 1880 drivers/gpu/drm/radeon/evergreen.c if (radeon_crtc->base.enabled && mode) { base 2156 drivers/gpu/drm/radeon/evergreen.c struct drm_display_mode *mode = &radeon_crtc->base.mode; base 2169 drivers/gpu/drm/radeon/evergreen.c if (radeon_crtc->base.enabled && num_heads && mode) { base 2334 drivers/gpu/drm/radeon/evergreen.c if (rdev->mode_info.crtcs[i]->base.enabled) base 2338 drivers/gpu/drm/radeon/evergreen.c mode0 = &rdev->mode_info.crtcs[i]->base.mode; base 2339 drivers/gpu/drm/radeon/evergreen.c mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; base 2829 drivers/gpu/drm/radeon/r100.c u64 base; base 2833 drivers/gpu/drm/radeon/r100.c base = rdev->mc.aper_base; base 2835 drivers/gpu/drm/radeon/r100.c base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; base 2836 drivers/gpu/drm/radeon/r100.c radeon_vram_location(rdev, &rdev->mc, base); base 3227 drivers/gpu/drm/radeon/r100.c if (rdev->mode_info.crtcs[0]->base.enabled) { base 3229 drivers/gpu/drm/radeon/r100.c rdev->mode_info.crtcs[0]->base.primary->fb; base 3231 drivers/gpu/drm/radeon/r100.c mode1 = &rdev->mode_info.crtcs[0]->base.mode; base 3235 drivers/gpu/drm/radeon/r100.c if (rdev->mode_info.crtcs[1]->base.enabled) { base 3237 drivers/gpu/drm/radeon/r100.c rdev->mode_info.crtcs[1]->base.primary->fb; base 3239 drivers/gpu/drm/radeon/r100.c mode2 = &rdev->mode_info.crtcs[1]->base.mode; base 478 drivers/gpu/drm/radeon/r300.c u64 base; base 492 drivers/gpu/drm/radeon/r300.c base = rdev->mc.aper_base; base 494 drivers/gpu/drm/radeon/r300.c base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; base 495 drivers/gpu/drm/radeon/r300.c radeon_vram_location(rdev, &rdev->mc, base); base 1423 drivers/gpu/drm/radeon/r600.c u64 base = 0; base 1425 drivers/gpu/drm/radeon/r600.c base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; base 1426 drivers/gpu/drm/radeon/r600.c base <<= 24; base 1428 drivers/gpu/drm/radeon/r600.c radeon_vram_location(rdev, &rdev->mc, base); base 372 drivers/gpu/drm/radeon/radeon.h struct dma_fence base; base 515 drivers/gpu/drm/radeon/radeon.h #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base) base 721 drivers/gpu/drm/radeon/radeon.h resource_size_t base; base 741 drivers/gpu/drm/radeon/radeon.h uint64_t base; base 2497 drivers/gpu/drm/radeon/radeon.h struct radeon_fence *__f = container_of(f, struct radeon_fence, base); base 2499 drivers/gpu/drm/radeon/radeon.h if (__f->base.ops == &radeon_fence_ops) base 2763 drivers/gpu/drm/radeon/radeon.h #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) base 2817 drivers/gpu/drm/radeon/radeon.h extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); base 1344 drivers/gpu/drm/radeon/radeon_atombios.c struct drm_device *dev = encoder->base.dev; base 1633 drivers/gpu/drm/radeon/radeon_atombios.c struct drm_device *dev = encoder->base.dev; base 1773 drivers/gpu/drm/radeon/radeon_atombios.c struct drm_device *dev = encoder->base.dev; base 1959 drivers/gpu/drm/radeon/radeon_atombios.c struct drm_device *dev = encoder->base.dev; base 125 drivers/gpu/drm/radeon/radeon_benchmark.c dobj->tbo.base.resv); base 136 drivers/gpu/drm/radeon/radeon_benchmark.c dobj->tbo.base.resv); base 865 drivers/gpu/drm/radeon/radeon_combios.c struct drm_device *dev = encoder->base.dev; base 1016 drivers/gpu/drm/radeon/radeon_combios.c struct drm_device *dev = encoder->base.dev; base 1175 drivers/gpu/drm/radeon/radeon_combios.c struct drm_device *dev = encoder->base.dev; base 1320 drivers/gpu/drm/radeon/radeon_combios.c struct drm_device *dev = encoder->base.dev; base 1336 drivers/gpu/drm/radeon/radeon_combios.c struct drm_device *dev = encoder->base.dev; base 1389 drivers/gpu/drm/radeon/radeon_combios.c struct drm_device *dev = encoder->base.dev; base 1413 drivers/gpu/drm/radeon/radeon_combios.c struct drm_device *dev = encoder->base.dev; base 322 drivers/gpu/drm/radeon/radeon_connectors.c radeon_connector->edid = drm_get_edid(&radeon_connector->base, base 325 drivers/gpu/drm/radeon/radeon_connectors.c radeon_connector->edid = drm_get_edid(&radeon_connector->base, base 330 drivers/gpu/drm/radeon/radeon_connectors.c radeon_connector->edid = drm_get_edid_switcheroo(&radeon_connector->base, base 333 drivers/gpu/drm/radeon/radeon_connectors.c radeon_connector->edid = drm_get_edid(&radeon_connector->base, base 577 drivers/gpu/drm/radeon/radeon_connectors.c radeon_property_change_mode(&radeon_encoder->base); base 592 drivers/gpu/drm/radeon/radeon_connectors.c radeon_property_change_mode(&radeon_encoder->base); base 607 drivers/gpu/drm/radeon/radeon_connectors.c radeon_property_change_mode(&radeon_encoder->base); base 621 drivers/gpu/drm/radeon/radeon_connectors.c radeon_property_change_mode(&radeon_encoder->base); base 635 drivers/gpu/drm/radeon/radeon_connectors.c radeon_property_change_mode(&radeon_encoder->base); base 649 drivers/gpu/drm/radeon/radeon_connectors.c radeon_property_change_mode(&radeon_encoder->base); base 674 drivers/gpu/drm/radeon/radeon_connectors.c radeon_property_change_mode(&radeon_encoder->base); base 710 drivers/gpu/drm/radeon/radeon_connectors.c radeon_property_change_mode(&radeon_encoder->base); base 739 drivers/gpu/drm/radeon/radeon_connectors.c radeon_property_change_mode(&radeon_encoder->base); base 972 drivers/gpu/drm/radeon/radeon_connectors.c radeon_property_change_mode(&radeon_encoder->base); base 1295 drivers/gpu/drm/radeon/radeon_connectors.c radeon_connector->base.null_edid_counter) { base 1927 drivers/gpu/drm/radeon/radeon_connectors.c connector = &radeon_connector->base; base 1959 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, base 1961 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, base 1966 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 1969 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 1973 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 1982 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, base 1984 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, base 1986 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 1989 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 1992 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 1996 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2000 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2005 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2011 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2023 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2030 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, base 2032 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, base 2034 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2045 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); base 2046 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); base 2053 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2057 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2061 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2070 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); base 2071 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); base 2078 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2082 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2086 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2101 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); base 2102 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); base 2109 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2113 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2116 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2119 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2122 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2125 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2130 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2137 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2142 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2158 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); base 2159 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); base 2165 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2169 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2172 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2175 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2178 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2181 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2186 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2192 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2208 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type); base 2209 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs); base 2218 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2222 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2225 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2228 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2231 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2234 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2239 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2245 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2258 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_edp_connector_funcs, connector_type); base 2259 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs); base 2267 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2277 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); base 2278 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); base 2280 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2283 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2297 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); base 2298 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); base 2304 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2372 drivers/gpu/drm/radeon/radeon_connectors.c connector = &radeon_connector->base; base 2381 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); base 2382 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); base 2389 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2398 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); base 2399 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); base 2406 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2416 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); base 2417 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); base 2425 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2439 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); base 2440 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); base 2449 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2452 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 2461 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); base 2462 drivers/gpu/drm/radeon/radeon_connectors.c drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); base 2468 drivers/gpu/drm/radeon/radeon_connectors.c drm_object_attach_property(&radeon_connector->base.base, base 260 drivers/gpu/drm/radeon/radeon_cs.c resv = reloc->robj->tbo.base.resv; base 434 drivers/gpu/drm/radeon/radeon_cs.c &parser->ib.fence->base); base 446 drivers/gpu/drm/radeon/radeon_cs.c drm_gem_object_put_unlocked(&bo->tbo.base); base 340 drivers/gpu/drm/radeon/radeon_device.c rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); base 347 drivers/gpu/drm/radeon/radeon_device.c rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); base 351 drivers/gpu/drm/radeon/radeon_device.c DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); base 566 drivers/gpu/drm/radeon/radeon_device.c void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) base 570 drivers/gpu/drm/radeon/radeon_device.c mc->vram_start = base; base 571 drivers/gpu/drm/radeon/radeon_device.c if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { base 280 drivers/gpu/drm/radeon/radeon_display.c drm_gem_object_put_unlocked(&work->old_rbo->tbo.base); base 342 drivers/gpu/drm/radeon/radeon_display.c &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && base 392 drivers/gpu/drm/radeon/radeon_display.c drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); base 396 drivers/gpu/drm/radeon/radeon_display.c drm_crtc_vblank_put(&radeon_crtc->base); base 416 drivers/gpu/drm/radeon/radeon_display.c struct drm_crtc *crtc = &radeon_crtc->base; base 473 drivers/gpu/drm/radeon/radeon_display.c radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); base 494 drivers/gpu/drm/radeon/radeon_display.c uint64_t base; base 531 drivers/gpu/drm/radeon/radeon_display.c ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); base 538 drivers/gpu/drm/radeon/radeon_display.c work->fence = dma_fence_get(dma_resv_get_excl(new_rbo->tbo.base.resv)); base 544 drivers/gpu/drm/radeon/radeon_display.c base -= radeon_crtc->legacy_display_base_addr; base 549 drivers/gpu/drm/radeon/radeon_display.c base &= ~0x7ff; base 553 drivers/gpu/drm/radeon/radeon_display.c base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); base 573 drivers/gpu/drm/radeon/radeon_display.c base += offset; base 575 drivers/gpu/drm/radeon/radeon_display.c base &= ~7; base 577 drivers/gpu/drm/radeon/radeon_display.c work->base = base; base 612 drivers/gpu/drm/radeon/radeon_display.c drm_gem_object_put_unlocked(&work->old_rbo->tbo.base); base 683 drivers/gpu/drm/radeon/radeon_display.c drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); base 685 drivers/gpu/drm/radeon/radeon_display.c drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); base 701 drivers/gpu/drm/radeon/radeon_display.c radeon_crtc->mode_set.crtc = &radeon_crtc->base; base 32 drivers/gpu/drm/radeon/radeon_dp_mst.c struct drm_device *dev = primary->base.dev; base 70 drivers/gpu/drm/radeon/radeon_dp_mst.c struct drm_device *dev = primary->base.dev; base 116 drivers/gpu/drm/radeon/radeon_dp_mst.c struct drm_device *dev = mst_conn->base.dev; base 166 drivers/gpu/drm/radeon/radeon_dp_mst.c struct drm_device *dev = mst->base.dev; base 200 drivers/gpu/drm/radeon/radeon_dp_mst.c drm_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); base 201 drivers/gpu/drm/radeon/radeon_dp_mst.c ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); base 204 drivers/gpu/drm/radeon/radeon_dp_mst.c drm_connector_update_edid_property(&radeon_connector->base, NULL); base 233 drivers/gpu/drm/radeon/radeon_dp_mst.c return &radeon_connector->mst_encoder->base; base 257 drivers/gpu/drm/radeon/radeon_dp_mst.c drm_encoder_cleanup(&radeon_encoder->base); base 275 drivers/gpu/drm/radeon/radeon_dp_mst.c struct drm_device *dev = master->base.dev; base 284 drivers/gpu/drm/radeon/radeon_dp_mst.c connector = &radeon_connector->base; base 293 drivers/gpu/drm/radeon/radeon_dp_mst.c drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); base 294 drivers/gpu/drm/radeon/radeon_dp_mst.c drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); base 314 drivers/gpu/drm/radeon/radeon_dp_mst.c struct drm_device *dev = master->base.dev; base 358 drivers/gpu/drm/radeon/radeon_dp_mst.c struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base); base 364 drivers/gpu/drm/radeon/radeon_dp_mst.c if (radeon_connector->base.display_info.bpc) base 365 drivers/gpu/drm/radeon/radeon_dp_mst.c radeon_crtc->bpc = radeon_connector->base.display_info.bpc; base 422 drivers/gpu/drm/radeon/radeon_dp_mst.c atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0); base 423 drivers/gpu/drm/radeon/radeon_dp_mst.c atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE, base 428 drivers/gpu/drm/radeon/radeon_dp_mst.c radeon_dp_link_train(&primary->base, &mst_enc->connector->base); base 460 drivers/gpu/drm/radeon/radeon_dp_mst.c atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0, base 489 drivers/gpu/drm/radeon/radeon_dp_mst.c atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0, base 522 drivers/gpu/drm/radeon/radeon_dp_mst.c mst_enc->connector->devices, mst_enc->primary->base.encoder_type); base 559 drivers/gpu/drm/radeon/radeon_dp_mst.c dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1); base 603 drivers/gpu/drm/radeon/radeon_dp_mst.c struct drm_device *dev = connector->base.dev; base 608 drivers/gpu/drm/radeon/radeon_dp_mst.c const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private; base 609 drivers/gpu/drm/radeon/radeon_dp_mst.c struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base); base 621 drivers/gpu/drm/radeon/radeon_dp_mst.c encoder = &radeon_encoder->base; base 638 drivers/gpu/drm/radeon/radeon_dp_mst.c drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs, base 652 drivers/gpu/drm/radeon/radeon_dp_mst.c struct drm_device *dev = radeon_connector->base.dev; base 660 drivers/gpu/drm/radeon/radeon_dp_mst.c radeon_connector->base.base.id); base 667 drivers/gpu/drm/radeon/radeon_dp_mst.c struct drm_device *dev = radeon_connector->base.dev; base 167 drivers/gpu/drm/radeon/radeon_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 277 drivers/gpu/drm/radeon/radeon_fb.c info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base; base 150 drivers/gpu/drm/radeon/radeon_fence.c dma_fence_init(&(*fence)->base, &radeon_fence_ops, base 180 drivers/gpu/drm/radeon/radeon_fence.c int ret = dma_fence_signal_locked(&fence->base); base 183 drivers/gpu/drm/radeon/radeon_fence.c DMA_FENCE_TRACE(&fence->base, "signaled from irq context\n"); base 185 drivers/gpu/drm/radeon/radeon_fence.c DMA_FENCE_TRACE(&fence->base, "was already signaled\n"); base 189 drivers/gpu/drm/radeon/radeon_fence.c dma_fence_put(&fence->base); base 191 drivers/gpu/drm/radeon/radeon_fence.c DMA_FENCE_TRACE(&fence->base, "pending\n"); base 427 drivers/gpu/drm/radeon/radeon_fence.c DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", fence->ring); base 447 drivers/gpu/drm/radeon/radeon_fence.c ret = dma_fence_signal(&fence->base); base 449 drivers/gpu/drm/radeon/radeon_fence.c DMA_FENCE_TRACE(&fence->base, "signaled from radeon_fence_signaled\n"); base 562 drivers/gpu/drm/radeon/radeon_fence.c if (WARN_ON_ONCE(!to_radeon_fence(&fence->base))) base 563 drivers/gpu/drm/radeon/radeon_fence.c return dma_fence_wait(&fence->base, intr); base 571 drivers/gpu/drm/radeon/radeon_fence.c r_sig = dma_fence_signal(&fence->base); base 573 drivers/gpu/drm/radeon/radeon_fence.c DMA_FENCE_TRACE(&fence->base, "signaled from fence_wait\n"); base 708 drivers/gpu/drm/radeon/radeon_fence.c dma_fence_get(&fence->base); base 725 drivers/gpu/drm/radeon/radeon_fence.c dma_fence_put(&tmp->base); base 1062 drivers/gpu/drm/radeon/radeon_fence.c return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->base.flags); base 1066 drivers/gpu/drm/radeon/radeon_fence.c struct dma_fence_cb base; base 1074 drivers/gpu/drm/radeon/radeon_fence.c container_of(cb, struct radeon_wait_cb, base); base 1088 drivers/gpu/drm/radeon/radeon_fence.c if (dma_fence_add_callback(f, &cb.base, radeon_fence_wait_cb)) base 1116 drivers/gpu/drm/radeon/radeon_fence.c dma_fence_remove_callback(f, &cb.base); base 86 drivers/gpu/drm/radeon/radeon_gem.c *obj = &robj->tbo.base; base 117 drivers/gpu/drm/radeon/radeon_gem.c r = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, 30 * HZ); base 454 drivers/gpu/drm/radeon/radeon_gem.c r = dma_resv_test_signaled_rcu(robj->tbo.base.resv, true); base 483 drivers/gpu/drm/radeon/radeon_gem.c ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, 30 * HZ); base 262 drivers/gpu/drm/radeon/radeon_kms.c if (crtc && crtc->base.id == *value) { base 786 drivers/gpu/drm/radeon/radeon_kms.c &rdev->mode_info.crtcs[pipe]->base.hwmode); base 383 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint64_t base; base 432 drivers/gpu/drm/radeon/radeon_legacy_crtc.c &base); base 473 drivers/gpu/drm/radeon/radeon_legacy_crtc.c base -= radeon_crtc->legacy_display_base_addr; base 502 drivers/gpu/drm/radeon/radeon_legacy_crtc.c base &= ~0x7ff; base 506 drivers/gpu/drm/radeon/radeon_legacy_crtc.c base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); base 528 drivers/gpu/drm/radeon/radeon_legacy_crtc.c base += offset; base 531 drivers/gpu/drm/radeon/radeon_legacy_crtc.c base &= ~7; base 544 drivers/gpu/drm/radeon/radeon_legacy_crtc.c crtc_offset = (u32)base; base 1123 drivers/gpu/drm/radeon/radeon_legacy_crtc.c drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); base 282 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 295 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 317 drivers/gpu/drm/radeon/radeon_legacy_encoders.c radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode); base 356 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 374 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 462 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct drm_device *dev = radeon_encoder->base.dev; base 1700 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct drm_device *dev = encoder->base.dev; base 1723 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct drm_device *dev = encoder->base.dev; base 1766 drivers/gpu/drm/radeon/radeon_legacy_encoders.c encoder = &radeon_encoder->base; base 240 drivers/gpu/drm/radeon/radeon_legacy_tv.c struct drm_device *dev = radeon_encoder->base.dev; base 247 drivers/gpu/drm/radeon/radeon_legacy_tv.c radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); base 304 drivers/gpu/drm/radeon/radeon_legacy_tv.c struct drm_device *dev = radeon_encoder->base.dev; base 326 drivers/gpu/drm/radeon/radeon_legacy_tv.c struct drm_device *dev = radeon_encoder->base.dev; base 389 drivers/gpu/drm/radeon/radeon_legacy_tv.c struct drm_device *dev = radeon_encoder->base.dev; base 416 drivers/gpu/drm/radeon/radeon_legacy_tv.c struct drm_device *dev = radeon_encoder->base.dev; base 108 drivers/gpu/drm/radeon/radeon_mn.c r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, base 46 drivers/gpu/drm/radeon/radeon_mode.h #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) base 47 drivers/gpu/drm/radeon/radeon_mode.h #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) base 48 drivers/gpu/drm/radeon/radeon_mode.h #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) base 328 drivers/gpu/drm/radeon/radeon_mode.h struct drm_crtc base; base 463 drivers/gpu/drm/radeon/radeon_mode.h struct drm_encoder base; base 545 drivers/gpu/drm/radeon/radeon_mode.h struct drm_connector base; base 88 drivers/gpu/drm/radeon/radeon_object.c if (bo->tbo.base.import_attach) base 89 drivers/gpu/drm/radeon/radeon_object.c drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); base 90 drivers/gpu/drm/radeon/radeon_object.c drm_gem_object_release(&bo->tbo.base); base 212 drivers/gpu/drm/radeon/radeon_object.c drm_gem_private_object_init(rdev->ddev, &bo->tbo.base, size); base 445 drivers/gpu/drm/radeon/radeon_object.c &bo->tbo.base, bo, (unsigned long)bo->tbo.base.size, base 446 drivers/gpu/drm/radeon/radeon_object.c *((unsigned long *)&bo->tbo.base.refcount)); base 451 drivers/gpu/drm/radeon/radeon_object.c drm_gem_object_put_unlocked(&bo->tbo.base); base 613 drivers/gpu/drm/radeon/radeon_object.c dma_resv_assert_held(bo->tbo.base.resv); base 739 drivers/gpu/drm/radeon/radeon_object.c dma_resv_assert_held(bo->tbo.base.resv); base 751 drivers/gpu/drm/radeon/radeon_object.c dma_resv_assert_held(bo->tbo.base.resv); base 873 drivers/gpu/drm/radeon/radeon_object.c struct dma_resv *resv = bo->tbo.base.resv; base 876 drivers/gpu/drm/radeon/radeon_object.c dma_resv_add_shared_fence(resv, &fence->base); base 878 drivers/gpu/drm/radeon/radeon_object.c dma_resv_add_excl_fence(resv, &fence->base); base 119 drivers/gpu/drm/radeon/radeon_object.h return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); base 1777 drivers/gpu/drm/radeon/radeon_pm.c &rdev->mode_info.crtcs[crtc]->base.hwmode); base 83 drivers/gpu/drm/radeon/radeon_prime.c return &bo->tbo.base; base 123 drivers/gpu/drm/radeon/radeon_test.c vram_obj->tbo.base.resv); base 127 drivers/gpu/drm/radeon/radeon_test.c vram_obj->tbo.base.resv); base 174 drivers/gpu/drm/radeon/radeon_test.c vram_obj->tbo.base.resv); base 178 drivers/gpu/drm/radeon/radeon_test.c vram_obj->tbo.base.resv); base 187 drivers/gpu/drm/radeon/radeon_ttm.c return drm_vma_node_verify_access(&rbo->tbo.base.vma_node, base 247 drivers/gpu/drm/radeon/radeon_ttm.c fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv); base 251 drivers/gpu/drm/radeon/radeon_ttm.c r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem); base 410 drivers/gpu/drm/radeon/radeon_ttm.c mem->bus.base = 0; base 423 drivers/gpu/drm/radeon/radeon_ttm.c mem->bus.base = rdev->mc.agp_base; base 433 drivers/gpu/drm/radeon/radeon_ttm.c mem->bus.base = rdev->mc.aper_base; base 442 drivers/gpu/drm/radeon/radeon_ttm.c ioremap_wc(mem->bus.base + mem->bus.offset, base 446 drivers/gpu/drm/radeon/radeon_ttm.c ioremap_nocache(mem->bus.base + mem->bus.offset, base 457 drivers/gpu/drm/radeon/radeon_ttm.c mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + base 480 drivers/gpu/drm/radeon/radeon_uvd.c f = dma_resv_get_excl(bo->tbo.base.resv); base 705 drivers/gpu/drm/radeon/radeon_vm.c radeon_sync_resv(rdev, &ib.sync, pd->tbo.base.resv, true); base 833 drivers/gpu/drm/radeon/radeon_vm.c radeon_sync_resv(rdev, &ib->sync, pt->tbo.base.resv, true); base 834 drivers/gpu/drm/radeon/radeon_vm.c r = dma_resv_reserve_shared(pt->tbo.base.resv, 1); base 270 drivers/gpu/drm/radeon/rs400.c u64 base; base 278 drivers/gpu/drm/radeon/rs400.c base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; base 279 drivers/gpu/drm/radeon/rs400.c radeon_vram_location(rdev, &rdev->mc, base); base 875 drivers/gpu/drm/radeon/rs600.c u64 base; base 885 drivers/gpu/drm/radeon/rs600.c base = RREG32_MC(R_000004_MC_FB_LOCATION); base 886 drivers/gpu/drm/radeon/rs600.c base = G_000004_MC_FB_START(base) << 16; base 887 drivers/gpu/drm/radeon/rs600.c radeon_vram_location(rdev, &rdev->mc, base); base 905 drivers/gpu/drm/radeon/rs600.c if (rdev->mode_info.crtcs[0]->base.enabled) base 906 drivers/gpu/drm/radeon/rs600.c mode0 = &rdev->mode_info.crtcs[0]->base.mode; base 907 drivers/gpu/drm/radeon/rs600.c if (rdev->mode_info.crtcs[1]->base.enabled) base 908 drivers/gpu/drm/radeon/rs600.c mode1 = &rdev->mode_info.crtcs[1]->base.mode; base 152 drivers/gpu/drm/radeon/rs690.c u64 base; base 164 drivers/gpu/drm/radeon/rs690.c base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); base 165 drivers/gpu/drm/radeon/rs690.c base = G_000100_MC_FB_START(base) << 16; base 173 drivers/gpu/drm/radeon/rs690.c base += 128 * 1024 * 1024; base 199 drivers/gpu/drm/radeon/rs690.c radeon_vram_location(rdev, &rdev->mc, base); base 277 drivers/gpu/drm/radeon/rs690.c struct drm_display_mode *mode = &crtc->base.mode; base 284 drivers/gpu/drm/radeon/rs690.c if (!crtc->base.enabled) { base 351 drivers/gpu/drm/radeon/rs690.c a.full = dfixed_const(crtc->base.mode.crtc_htotal); base 359 drivers/gpu/drm/radeon/rs690.c a.full = dfixed_const(crtc->base.mode.crtc_htotal); base 360 drivers/gpu/drm/radeon/rs690.c b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); base 443 drivers/gpu/drm/radeon/rs690.c wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); base 450 drivers/gpu/drm/radeon/rs690.c if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { base 599 drivers/gpu/drm/radeon/rs690.c if (rdev->mode_info.crtcs[0]->base.enabled) base 600 drivers/gpu/drm/radeon/rs690.c mode0 = &rdev->mode_info.crtcs[0]->base.mode; base 601 drivers/gpu/drm/radeon/rs690.c if (rdev->mode_info.crtcs[1]->base.enabled) base 602 drivers/gpu/drm/radeon/rs690.c mode1 = &rdev->mode_info.crtcs[1]->base.mode; base 960 drivers/gpu/drm/radeon/rv515.c struct drm_display_mode *mode = &crtc->base.mode; base 967 drivers/gpu/drm/radeon/rv515.c if (!crtc->base.enabled) { base 1031 drivers/gpu/drm/radeon/rv515.c a.full = dfixed_const(crtc->base.mode.crtc_htotal); base 1039 drivers/gpu/drm/radeon/rv515.c a.full = dfixed_const(crtc->base.mode.crtc_htotal); base 1040 drivers/gpu/drm/radeon/rv515.c b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); base 1094 drivers/gpu/drm/radeon/rv515.c wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); base 1101 drivers/gpu/drm/radeon/rv515.c if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { base 1245 drivers/gpu/drm/radeon/rv515.c if (rdev->mode_info.crtcs[0]->base.enabled) base 1246 drivers/gpu/drm/radeon/rv515.c mode0 = &rdev->mode_info.crtcs[0]->base.mode; base 1247 drivers/gpu/drm/radeon/rv515.c if (rdev->mode_info.crtcs[1]->base.enabled) base 1248 drivers/gpu/drm/radeon/rv515.c mode1 = &rdev->mode_info.crtcs[1]->base.mode; base 1287 drivers/gpu/drm/radeon/rv515.c if (rdev->mode_info.crtcs[0]->base.enabled) base 1288 drivers/gpu/drm/radeon/rv515.c mode0 = &rdev->mode_info.crtcs[0]->base.mode; base 1289 drivers/gpu/drm/radeon/rv515.c if (rdev->mode_info.crtcs[1]->base.enabled) base 1290 drivers/gpu/drm/radeon/rv515.c mode1 = &rdev->mode_info.crtcs[1]->base.mode; base 1991 drivers/gpu/drm/radeon/si.c if (radeon_crtc->base.enabled && mode) { base 2016 drivers/gpu/drm/radeon/si.c if (radeon_crtc->base.enabled && mode) { base 2302 drivers/gpu/drm/radeon/si.c struct drm_display_mode *mode = &radeon_crtc->base.mode; base 2314 drivers/gpu/drm/radeon/si.c if (radeon_crtc->base.enabled && num_heads && mode) { base 2477 drivers/gpu/drm/radeon/si.c if (rdev->mode_info.crtcs[i]->base.enabled) base 2481 drivers/gpu/drm/radeon/si.c mode0 = &rdev->mode_info.crtcs[i]->base.mode; base 2482 drivers/gpu/drm/radeon/si.c mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; base 684 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rcar_lvds_clk_enable(encoder->base.bridge, base 710 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rcar_lvds_clk_disable(encoder->base.bridge); base 829 drivers/gpu/drm/rcar-du/rcar_du_crtc.c sprintf(name, "plane%u", plane->base.id); base 965 drivers/gpu/drm/rcar-du/rcar_du_crtc.c if (index == rcrtc->vsp->planes[i].plane.base.id) base 18 drivers/gpu/drm/rcar-du/rcar_du_encoder.h struct drm_encoder base; base 23 drivers/gpu/drm/rcar-du/rcar_du_encoder.h container_of(e, struct rcar_du_encoder, base) base 25 drivers/gpu/drm/rcar-du/rcar_du_encoder.h #define rcar_encoder_to_drm_encoder(e) (&(e)->base) base 791 drivers/gpu/drm/rcar-du/rcar_du_plane.c drm_object_attach_property(&plane->plane.base, base 195 drivers/gpu/drm/rcar-du/rcar_du_vsp.c gem->base.size); base 204 drivers/gpu/drm/rcar-du/rcar_du_writeback.c drm_connector_helper_add(&wb_conn->base, base 223 drivers/gpu/drm/rcar-du/rcar_du_writeback.c state = rcrtc->writeback.base.state; base 215 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c void __iomem *base; base 300 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c writel(val, dsi->base + reg); base 305 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c return readl(dsi->base + reg); base 902 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c dsi->base = devm_ioremap_resource(dev, res); base 903 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c if (IS_ERR(dsi->base)) { base 905 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c return PTR_ERR(dsi->base); base 957 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c dsi->pdata.base = dsi->base; base 28 drivers/gpu/drm/rockchip/rockchip_drm_drv.h struct drm_crtc_state base; base 35 drivers/gpu/drm/rockchip/rockchip_drm_drv.h container_of(s, struct rockchip_crtc_state, base) base 67 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c private->fbdev_bo = &rk_obj->base; base 95 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c fbi->screen_size = rk_obj->base.size; base 96 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c fbi->fix.smem_len = rk_obj->base.size; base 106 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c rockchip_gem_free_object(&rk_obj->base); base 20 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = rk_obj->base.dev; base 27 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rk_obj->base.size, PAGE_SIZE, base 40 drivers/gpu/drm/rockchip/rockchip_drm_gem.c if (ret < rk_obj->base.size) { base 42 drivers/gpu/drm/rockchip/rockchip_drm_gem.c ret, rk_obj->base.size); base 61 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = rk_obj->base.dev; base 77 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_device *drm = rk_obj->base.dev; base 81 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rk_obj->pages = drm_gem_get_pages(&rk_obj->base); base 85 drivers/gpu/drm/rockchip/rockchip_drm_gem.c rk_obj->num_pages = rk_obj->base.size >> PAGE_SHIFT; base 109 drivers/gpu/drm/rockchip/rockchip_drm_gem.c drm_gem_put_pages(&rk_obj->base, rk_obj->pages, false, false); base 117 drivers/gpu/drm/rockchip/rockchip_drm_gem.c drm_gem_put_pages(&rk_obj->base, rk_obj->pages, true, true); base 156 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_gem_object *obj = &rk_obj->base; base 178 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_gem_object *obj = &rk_obj->base; base 197 drivers/gpu/drm/rockchip/rockchip_drm_gem.c struct drm_gem_object *obj = &rk_obj->base; base 293 drivers/gpu/drm/rockchip/rockchip_drm_gem.c drm_gem_object_release(&rk_obj->base); base 309 drivers/gpu/drm/rockchip/rockchip_drm_gem.c obj = &rk_obj->base; base 383 drivers/gpu/drm/rockchip/rockchip_drm_gem.c obj = &rk_obj->base; base 535 drivers/gpu/drm/rockchip/rockchip_drm_gem.c return &rk_obj->base; base 10 drivers/gpu/drm/rockchip/rockchip_drm_gem.h #define to_rockchip_obj(x) container_of(x, struct rockchip_gem_object, base) base 13 drivers/gpu/drm/rockchip/rockchip_drm_gem.h struct drm_gem_object base; base 43 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) base 45 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) base 48 drivers/gpu/drm/rockchip/rockchip_drm_vop.c win->base, ~0, v, #name) base 59 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ base 83 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_read_reg(vop, win->base, &win->phy->name) base 89 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_readl(vop, win->base + win->phy->yrgb_mst.offset) base 95 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define to_vop_win(x) container_of(x, struct vop_win, base) base 114 drivers/gpu/drm/rockchip/rockchip_drm_vop.c struct drm_plane base; base 182 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, base 185 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; base 1295 drivers/gpu/drm/rockchip/rockchip_drm_vop.c __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); base 1296 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return &rockchip_state->base; base 1304 drivers/gpu/drm/rockchip/rockchip_drm_vop.c __drm_atomic_helper_crtc_destroy_state(&s->base); base 1316 drivers/gpu/drm/rockchip/rockchip_drm_vop.c __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); base 1526 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, base 1537 drivers/gpu/drm/rockchip/rockchip_drm_vop.c plane = &vop_win->base; base 1565 drivers/gpu/drm/rockchip/rockchip_drm_vop.c ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, base 1576 drivers/gpu/drm/rockchip/rockchip_drm_vop.c drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); base 1577 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_plane_add_properties(&vop_win->base, win_data); base 152 drivers/gpu/drm/rockchip/rockchip_drm_vop.h uint32_t base; base 158 drivers/gpu/drm/rockchip/rockchip_drm_vop.h uint32_t base; base 100 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3036_win0_data, base 102 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3036_win1_data, base 165 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3036_win0_data, base 167 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3126_win1_data, base 272 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &px30_win0_data, base 274 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &px30_win1_data, base 276 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &px30_win2_data, base 291 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &px30_win1_data, base 377 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3066_win0_data, base 379 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3066_win1_data, base 381 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3066_win2_data, base 473 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3188_win0_data, base 475 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3188_win1_data, base 614 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3288_win01_data, base 616 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x40, .phy = &rk3288_win01_data, base 618 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3288_win23_data, base 620 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x50, .phy = &rk3288_win23_data, base 709 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3368_win01_data, base 711 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x40, .phy = &rk3368_win01_data, base 713 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3368_win23_data, base 715 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x50, .phy = &rk3368_win23_data, base 800 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data, base 802 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x60, .phy = &rk3399_yuv2yuv_win01_data, base 804 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0xC0, .phy = &rk3399_yuv2yuv_win23_data }, base 805 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x120, .phy = &rk3399_yuv2yuv_win23_data }, base 822 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3368_win01_data, base 824 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3368_win23_data, base 829 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data, base 831 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x60, .phy = &rk3399_yuv2yuv_win23_data }, base 847 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x00, .phy = &rk3288_win01_data, base 849 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x40, .phy = &rk3288_win01_data, base 912 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0xd0, .phy = &rk3368_win01_data, base 914 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x1d0, .phy = &rk3368_win01_data, base 916 drivers/gpu/drm/rockchip/rockchip_vop_reg.c { .base = 0x2d0, .phy = &rk3368_win01_data, base 681 drivers/gpu/drm/shmobile/shmob_drm_crtc.c drm_object_property_set_value(&connector->base, base 59 drivers/gpu/drm/sti/sti_crtc.c crtc->base.id, sti_mixer_to_str(mixer), mode->name); base 110 drivers/gpu/drm/sti/sti_crtc.c DRM_DEBUG_KMS("CRTC:%d (%s)\n", crtc->base.id, sti_mixer_to_str(mixer)); base 361 drivers/gpu/drm/sti/sti_crtc.c crtc->base.id, sti_mixer_to_str(mixer)); base 47 drivers/gpu/drm/sti/sti_cursor.c void *base; base 96 drivers/gpu/drm/sti/sti_cursor.c seq_printf(s, "\tVirt @: %p", cursor->pixmap.base); base 149 drivers/gpu/drm/sti/sti_cursor.c u8 *dst = cursor->pixmap.base; base 169 drivers/gpu/drm/sti/sti_cursor.c unsigned short *base = cursor->clut; base 177 drivers/gpu/drm/sti/sti_cursor.c *base++ = (a * 5) << 12 | base 219 drivers/gpu/drm/sti/sti_cursor.c if (!cursor->pixmap.base || base 225 drivers/gpu/drm/sti/sti_cursor.c if (cursor->pixmap.base) base 227 drivers/gpu/drm/sti/sti_cursor.c cursor->pixmap.base, cursor->pixmap.paddr); base 231 drivers/gpu/drm/sti/sti_cursor.c cursor->pixmap.base = dma_alloc_wc(cursor->dev, base 235 drivers/gpu/drm/sti/sti_cursor.c if (!cursor->pixmap.base) { base 247 drivers/gpu/drm/sti/sti_cursor.c crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)), base 248 drivers/gpu/drm/sti/sti_cursor.c drm_plane->base.id, sti_plane_to_str(plane)); base 315 drivers/gpu/drm/sti/sti_cursor.c drm_plane->base.id); base 320 drivers/gpu/drm/sti/sti_cursor.c oldstate->crtc->base.id, base 322 drivers/gpu/drm/sti/sti_cursor.c drm_plane->base.id, sti_plane_to_str(plane)); base 183 drivers/gpu/drm/sti/sti_gdp.c void *base = NULL; base 188 drivers/gpu/drm/sti/sti_gdp.c base = gdp->node_list[i].top_field; base 192 drivers/gpu/drm/sti/sti_gdp.c base = gdp->node_list[i].btm_field; base 197 drivers/gpu/drm/sti/sti_gdp.c if (base) base 198 drivers/gpu/drm/sti/sti_gdp.c seq_printf(s, "\tVirt @: %p", base); base 253 drivers/gpu/drm/sti/sti_gdp.c crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc))); base 518 drivers/gpu/drm/sti/sti_gdp.c void *base; base 524 drivers/gpu/drm/sti/sti_gdp.c base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL); base 526 drivers/gpu/drm/sti/sti_gdp.c if (!base) { base 530 drivers/gpu/drm/sti/sti_gdp.c memset(base, 0, size); base 537 drivers/gpu/drm/sti/sti_gdp.c gdp->node_list[i].top_field = base; base 540 drivers/gpu/drm/sti/sti_gdp.c DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); base 541 drivers/gpu/drm/sti/sti_gdp.c base += sizeof(struct sti_gdp_node); base 548 drivers/gpu/drm/sti/sti_gdp.c gdp->node_list[i].btm_field = base; base 550 drivers/gpu/drm/sti/sti_gdp.c DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); base 551 drivers/gpu/drm/sti/sti_gdp.c base += sizeof(struct sti_gdp_node); base 686 drivers/gpu/drm/sti/sti_gdp.c crtc->base.id, sti_mixer_to_str(mixer), base 687 drivers/gpu/drm/sti/sti_gdp.c drm_plane->base.id, sti_plane_to_str(plane)); base 773 drivers/gpu/drm/sti/sti_gdp.c DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, base 868 drivers/gpu/drm/sti/sti_gdp.c drm_plane->base.id); base 873 drivers/gpu/drm/sti/sti_gdp.c oldstate->crtc->base.id, base 875 drivers/gpu/drm/sti/sti_gdp.c drm_plane->base.id, sti_plane_to_str(plane)); base 1068 drivers/gpu/drm/sti/sti_hdmi.c drm_object_attach_property(&connector->base, prop, hdmi->colorspace); base 1099 drivers/gpu/drm/sti/sti_hqvdp.c crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)), base 1100 drivers/gpu/drm/sti/sti_hqvdp.c drm_plane->base.id, sti_plane_to_str(plane)); base 1176 drivers/gpu/drm/sti/sti_hqvdp.c DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, base 1247 drivers/gpu/drm/sti/sti_hqvdp.c drm_plane->base.id); base 1252 drivers/gpu/drm/sti/sti_hqvdp.c oldstate->crtc->base.id, base 1254 drivers/gpu/drm/sti/sti_hqvdp.c drm_plane->base.id, sti_plane_to_str(plane)); base 143 drivers/gpu/drm/sti/sti_plane.c plane->drm_plane.base.id, sti_plane_to_str(plane)); base 78 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c void __iomem *base; base 89 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c writel(val, dsi->base + reg); base 94 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c return readl(dsi->base + reg); base 205 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS, base 212 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS, base 340 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c dsi->base = devm_ioremap_resource(dev, res); base 341 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c if (IS_ERR(dsi->base)) { base 342 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c ret = PTR_ERR(dsi->base); base 396 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c dw_mipi_dsi_stm_plat_data.base = dsi->base; base 242 drivers/gpu/drm/stm/ltdc.c static inline u32 reg_read(void __iomem *base, u32 reg) base 244 drivers/gpu/drm/stm/ltdc.c return readl_relaxed(base + reg); base 247 drivers/gpu/drm/stm/ltdc.c static inline void reg_write(void __iomem *base, u32 reg, u32 val) base 249 drivers/gpu/drm/stm/ltdc.c writel_relaxed(val, base + reg); base 252 drivers/gpu/drm/stm/ltdc.c static inline void reg_set(void __iomem *base, u32 reg, u32 mask) base 254 drivers/gpu/drm/stm/ltdc.c reg_write(base, reg, reg_read(base, reg) | mask); base 257 drivers/gpu/drm/stm/ltdc.c static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) base 259 drivers/gpu/drm/stm/ltdc.c reg_write(base, reg, reg_read(base, reg) & ~mask); base 262 drivers/gpu/drm/stm/ltdc.c static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, base 265 drivers/gpu/drm/stm/ltdc.c reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); base 565 drivers/gpu/drm/stm/ltdc.c DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); base 785 drivers/gpu/drm/stm/ltdc.c plane->base.id, fb->base.id, base 882 drivers/gpu/drm/stm/ltdc.c oldstate->crtc->base.id, plane->base.id); base 977 drivers/gpu/drm/stm/ltdc.c DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); base 1016 drivers/gpu/drm/stm/ltdc.c DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); base 1064 drivers/gpu/drm/stm/ltdc.c DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); base 250 drivers/gpu/drm/sun4i/sun4i_hdmi.h void __iomem *base; base 66 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); base 90 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); base 92 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); base 110 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); base 116 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); base 132 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c hdmi->base + SUN4I_HDMI_UNKNOWN_REG); base 144 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); base 147 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); base 148 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); base 153 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG); base 158 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG); base 163 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG); base 168 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG); base 177 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); base 265 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg, base 289 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; base 297 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); base 308 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(0, hdmi->base + SUN4I_HDMI_CEC); base 511 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c hdmi->base = devm_ioremap_resource(dev, res); base 512 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c if (IS_ERR(hdmi->base)) { base 514 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c return PTR_ERR(hdmi->base); base 561 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base, base 586 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG); base 589 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG); base 591 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); base 594 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); base 637 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, base 638 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c hdmi->base + SUN4I_HDMI_CEC); base 59 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); base 61 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); base 77 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); base 82 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); base 131 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); base 135 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); base 154 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); base 158 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c writel(reg, tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); base 160 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); base 163 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); base 173 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG); base 186 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG); base 189 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG); base 1085 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c void __iomem *base; base 1097 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c base = devm_ioremap_resource(dev, res); base 1098 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c if (IS_ERR(base)) { base 1100 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c return PTR_ERR(base); base 1103 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base, base 153 drivers/gpu/drm/sun4i/sun8i_csc.c static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, base 173 drivers/gpu/drm/sun4i/sun8i_csc.c base_reg = SUN8I_CSC_COEFF(base, 0); base 201 drivers/gpu/drm/sun4i/sun8i_csc.c static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable) base 210 drivers/gpu/drm/sun4i/sun8i_csc.c regmap_update_bits(map, SUN8I_CSC_CTRL(base), SUN8I_CSC_CTRL_EN, val); base 233 drivers/gpu/drm/sun4i/sun8i_csc.c u32 base; base 241 drivers/gpu/drm/sun4i/sun8i_csc.c base = ccsc_base[mixer->cfg->ccsc][layer]; base 243 drivers/gpu/drm/sun4i/sun8i_csc.c sun8i_csc_set_coefficients(mixer->engine.regs, base, base 249 drivers/gpu/drm/sun4i/sun8i_csc.c u32 base; base 256 drivers/gpu/drm/sun4i/sun8i_csc.c base = ccsc_base[mixer->cfg->ccsc][layer]; base 258 drivers/gpu/drm/sun4i/sun8i_csc.c sun8i_csc_enable(mixer->engine.regs, base, enable); base 19 drivers/gpu/drm/sun4i/sun8i_csc.h #define SUN8I_CSC_CTRL(base) (base + 0x0) base 20 drivers/gpu/drm/sun4i/sun8i_csc.h #define SUN8I_CSC_COEFF(base, i) (base + 0x10 + 4 * i) base 431 drivers/gpu/drm/sun4i/sun8i_mixer.c unsigned int base; base 520 drivers/gpu/drm/sun4i/sun8i_mixer.c base = sun8i_blender_base(mixer); base 555 drivers/gpu/drm/sun4i/sun8i_mixer.c regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base), base 562 drivers/gpu/drm/sun4i/sun8i_mixer.c regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), base 564 drivers/gpu/drm/sun4i/sun8i_mixer.c regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), base 570 drivers/gpu/drm/sun4i/sun8i_mixer.c SUN8I_MIXER_BLEND_MODE(base, i), base 573 drivers/gpu/drm/sun4i/sun8i_mixer.c regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), base 39 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0) base 40 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x)) base 41 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x)) base 42 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x)) base 43 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80) base 44 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84) base 45 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88) base 46 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c) base 47 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x)) base 48 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0) base 49 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_CK_CFG(base) ((base) + 0xb4) base 50 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_CK_MAX(base, x) ((base) + 0xc0 + 0x04 * (x)) base 51 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x)) base 52 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc) base 53 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN50I_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100) base 54 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \ base 55 drivers/gpu/drm/sun4i/sun8i_mixer.h ((base) + 0x110 + (layer) * 0x30 + (x) * 0x10 + 4 * (y)) base 56 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN50I_MIXER_BLEND_CSC_CONST(base, layer, i) \ base 57 drivers/gpu/drm/sun4i/sun8i_mixer.h ((base) + 0x110 + (layer) * 0x30 + (i) * 0x10 + 0x0c) base 17 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ base 18 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x0) base 19 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ base 20 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x4) base 21 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ base 22 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x8) base 23 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ base 24 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0xc) base 25 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \ base 26 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x10) base 27 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_BOT_LADDR(base, layer) \ base 28 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x14) base 29 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_FCOLOR(base, layer) \ base 30 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x18) base 31 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_TOP_HADDR(base) \ base 32 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x80) base 33 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_BOT_HADDR(base) \ base 34 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x84) base 35 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_OVL_SIZE(base) \ base 36 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x88) base 132 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c u32 val, base; base 137 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c base = sun8i_ui_scaler_base(mixer, layer); base 145 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c regmap_write(mixer->engine.regs, SUN8I_SCALER_GSU_CTRL(base), val); base 154 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c u32 base; base 159 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c base = sun8i_ui_scaler_base(mixer, layer); base 170 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c SUN8I_SCALER_GSU_OUTSIZE(base), outsize); base 172 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c SUN8I_SCALER_GSU_INSIZE(base), insize); base 174 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c SUN8I_SCALER_GSU_HSTEP(base), hscale); base 176 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c SUN8I_SCALER_GSU_VSTEP(base), vscale); base 178 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c SUN8I_SCALER_GSU_HPHASE(base), hphase); base 180 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c SUN8I_SCALER_GSU_VPHASE(base), vphase); base 185 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c SUN8I_SCALER_GSU_HCOEFF(base, i), base 26 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h #define SUN8I_SCALER_GSU_CTRL(base) ((base) + 0x0) base 27 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h #define SUN8I_SCALER_GSU_OUTSIZE(base) ((base) + 0x40) base 28 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h #define SUN8I_SCALER_GSU_INSIZE(base) ((base) + 0x80) base 29 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h #define SUN8I_SCALER_GSU_HSTEP(base) ((base) + 0x88) base 30 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h #define SUN8I_SCALER_GSU_VSTEP(base) ((base) + 0x8c) base 31 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h #define SUN8I_SCALER_GSU_HPHASE(base) ((base) + 0x90) base 32 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h #define SUN8I_SCALER_GSU_VPHASE(base) ((base) + 0x98) base 33 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h #define SUN8I_SCALER_GSU_HCOEFF(base, index) ((base) + 0x200 + 0x4 * (index)) base 11 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \ base 12 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0x30 * (layer) + 0x0) base 13 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \ base 14 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0x30 * (layer) + 0x4) base 15 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \ base 16 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0x30 * (layer) + 0x8) base 17 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \ base 18 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0x30 * (layer) + 0xc + 4 * (plane)) base 19 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \ base 20 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0x30 * (layer) + 0x18 + 4 * (plane)) base 21 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_OVL_SIZE(base) \ base 22 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0xe8) base 23 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_HDS_Y(base) \ base 24 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0xf0) base 25 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_HDS_UV(base) \ base 26 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0xf4) base 27 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_VDS_Y(base) \ base 28 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0xf8) base 29 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_VDS_UV(base) \ base 30 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0xfc) base 870 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base, base 890 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, i), base 892 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF1(base, i), base 894 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, i), base 896 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF1(base, i), base 903 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c regmap_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, i), base 905 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c regmap_write(map, SUN8I_SCALER_VSU_CVCOEFF(base, i), base 912 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c u32 val, base; base 914 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c base = sun8i_vi_scaler_base(mixer, layer); base 923 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_CTRL(base), val); base 933 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c u32 base; base 935 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c base = sun8i_vi_scaler_base(mixer, layer); base 968 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN50I_SCALER_VSU_SCALE_MODE(base), val); base 972 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_OUTSIZE(base), outsize); base 974 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_YINSIZE(base), insize); base 976 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_YHSTEP(base), hscale); base 978 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_YVSTEP(base), vscale); base 980 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_YHPHASE(base), hphase); base 982 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_YVPHASE(base), vphase); base 984 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_CINSIZE(base), base 988 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_CHSTEP(base), base 991 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_CVSTEP(base), base 994 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_CHPHASE(base), chphase); base 996 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c SUN8I_SCALER_VSU_CVPHASE(base), cvphase); base 997 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c sun8i_vi_scaler_set_coeff(mixer->engine.regs, base, base 30 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0) base 31 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN50I_SCALER_VSU_SCALE_MODE(base) ((base) + 0x10) base 32 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN50I_SCALER_VSU_DIR_THR(base) ((base) + 0x20) base 33 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN50I_SCALER_VSU_EDGE_THR(base) ((base) + 0x24) base 34 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN50I_SCALER_VSU_EDSCL_CTRL(base) ((base) + 0x28) base 35 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN50I_SCALER_VSU_ANGLE_THR(base) ((base) + 0x2c) base 36 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_OUTSIZE(base) ((base) + 0x40) base 37 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_YINSIZE(base) ((base) + 0x80) base 38 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_YHSTEP(base) ((base) + 0x88) base 39 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_YVSTEP(base) ((base) + 0x8c) base 40 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_YHPHASE(base) ((base) + 0x90) base 41 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_YVPHASE(base) ((base) + 0x98) base 42 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_CINSIZE(base) ((base) + 0xc0) base 43 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_CHSTEP(base) ((base) + 0xc8) base 44 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_CVSTEP(base) ((base) + 0xcc) base 45 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_CHPHASE(base) ((base) + 0xd0) base 46 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_CVPHASE(base) ((base) + 0xd8) base 47 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_YHCOEFF0(base, i) ((base) + 0x200 + 0x4 * (i)) base 48 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_YHCOEFF1(base, i) ((base) + 0x300 + 0x4 * (i)) base 49 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_YVCOEFF(base, i) ((base) + 0x400 + 0x4 * (i)) base 50 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_CHCOEFF0(base, i) ((base) + 0x600 + 0x4 * (i)) base 51 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_CHCOEFF1(base, i) ((base) + 0x700 + 0x4 * (i)) base 52 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h #define SUN8I_SCALER_VSU_CVCOEFF(base, i) ((base) + 0x800 + 0x4 * (i)) base 178 drivers/gpu/drm/tegra/dc.c state = to_tegra_plane_state(plane->base.state); base 199 drivers/gpu/drm/tegra/dc.c switch (state->base.normalized_zpos) { base 229 drivers/gpu/drm/tegra/dc.c switch (state->base.normalized_zpos) { base 253 drivers/gpu/drm/tegra/dc.c switch (state->base.normalized_zpos) { base 396 drivers/gpu/drm/tegra/dc.c tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); base 399 drivers/gpu/drm/tegra/dc.c tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); base 400 drivers/gpu/drm/tegra/dc.c tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); base 720 drivers/gpu/drm/tegra/dc.c window.base[i] = bo->paddr + fb->offsets[i]; base 781 drivers/gpu/drm/tegra/dc.c err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, base 789 drivers/gpu/drm/tegra/dc.c drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); base 790 drivers/gpu/drm/tegra/dc.c drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); base 792 drivers/gpu/drm/tegra/dc.c err = drm_plane_create_rotation_property(&plane->base, base 800 drivers/gpu/drm/tegra/dc.c return &plane->base; base 948 drivers/gpu/drm/tegra/dc.c err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, base 957 drivers/gpu/drm/tegra/dc.c drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); base 959 drivers/gpu/drm/tegra/dc.c return &plane->base; base 1066 drivers/gpu/drm/tegra/dc.c err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, base 1074 drivers/gpu/drm/tegra/dc.c drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); base 1075 drivers/gpu/drm/tegra/dc.c drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); base 1077 drivers/gpu/drm/tegra/dc.c err = drm_plane_create_rotation_property(&plane->base, base 1085 drivers/gpu/drm/tegra/dc.c return &plane->base; base 1168 drivers/gpu/drm/tegra/dc.c __drm_atomic_helper_crtc_reset(crtc, &state->base); base 1182 drivers/gpu/drm/tegra/dc.c __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); base 1188 drivers/gpu/drm/tegra/dc.c return ©->base; base 1422 drivers/gpu/drm/tegra/dc.c drm_modeset_lock(&dc->base.mutex, NULL); base 1424 drivers/gpu/drm/tegra/dc.c if (!dc->base.state->active) { base 1437 drivers/gpu/drm/tegra/dc.c drm_modeset_unlock(&dc->base.mutex); base 1448 drivers/gpu/drm/tegra/dc.c drm_modeset_lock(&dc->base.mutex, NULL); base 1450 drivers/gpu/drm/tegra/dc.c if (!dc->base.state->active) { base 1459 drivers/gpu/drm/tegra/dc.c drm_crtc_wait_one_vblank(&dc->base); base 1460 drivers/gpu/drm/tegra/dc.c drm_crtc_wait_one_vblank(&dc->base); base 1468 drivers/gpu/drm/tegra/dc.c drm_modeset_unlock(&dc->base.mutex); base 1546 drivers/gpu/drm/tegra/dc.c return (u32)drm_crtc_vblank_count(&dc->base); base 1952 drivers/gpu/drm/tegra/dc.c drm_crtc_handle_vblank(&dc->base); base 2049 drivers/gpu/drm/tegra/dc.c err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, base 2054 drivers/gpu/drm/tegra/dc.c drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); base 19 drivers/gpu/drm/tegra/dc.h struct drm_crtc_state base; base 31 drivers/gpu/drm/tegra/dc.h return container_of(state, struct tegra_dc_state, base); base 76 drivers/gpu/drm/tegra/dc.h struct drm_crtc base; base 105 drivers/gpu/drm/tegra/dc.h return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; base 139 drivers/gpu/drm/tegra/dc.h unsigned long base[3]; base 283 drivers/gpu/drm/tegra/drm.c return &bo->base; base 329 drivers/gpu/drm/tegra/drm.c struct host1x_client *client = &context->client->base; base 481 drivers/gpu/drm/tegra/drm.c err = host1x_job_pin(job, context->client->base.dev); base 624 drivers/gpu/drm/tegra/drm.c if (client->base.class == args->client) { base 681 drivers/gpu/drm/tegra/drm.c if (args->index >= context->client->base.num_syncpts) { base 686 drivers/gpu/drm/tegra/drm.c syncpt = context->client->base.syncpts[args->index]; base 723 drivers/gpu/drm/tegra/drm.c struct host1x_syncpt_base *base; base 735 drivers/gpu/drm/tegra/drm.c if (args->syncpt >= context->client->base.num_syncpts) { base 740 drivers/gpu/drm/tegra/drm.c syncpt = context->client->base.syncpts[args->syncpt]; base 742 drivers/gpu/drm/tegra/drm.c base = host1x_syncpt_get_base(syncpt); base 743 drivers/gpu/drm/tegra/drm.c if (!base) { base 748 drivers/gpu/drm/tegra/drm.c args->id = host1x_syncpt_base_id(base); base 974 drivers/gpu/drm/tegra/drm.c fb->base.id, fb->width, fb->height, base 30 drivers/gpu/drm/tegra/drm.h struct drm_fb_helper base; base 85 drivers/gpu/drm/tegra/drm.h struct host1x_client base; base 96 drivers/gpu/drm/tegra/drm.h return container_of(client, struct tegra_drm_client, base); base 33 drivers/gpu/drm/tegra/dsi.c struct drm_connector_state base; base 51 drivers/gpu/drm/tegra/dsi.c return container_of(state, struct tegra_dsi_state, base); base 785 drivers/gpu/drm/tegra/dsi.c __drm_atomic_helper_connector_reset(connector, &state->base); base 799 drivers/gpu/drm/tegra/dsi.c ©->base); base 801 drivers/gpu/drm/tegra/dsi.c return ©->base; base 42 drivers/gpu/drm/tegra/falcon.c phys_addr_t base, base 52 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, base, FALCON_DMATRFFBOFFS); base 22 drivers/gpu/drm/tegra/fb.c return container_of(helper, struct tegra_fbdev, base); base 299 drivers/gpu/drm/tegra/fb.c drm_fb_helper_prepare(drm, &fbdev->base, &tegra_fb_helper_funcs); base 314 drivers/gpu/drm/tegra/fb.c struct drm_device *drm = fbdev->base.dev; base 317 drivers/gpu/drm/tegra/fb.c err = drm_fb_helper_init(drm, &fbdev->base, max_connectors); base 324 drivers/gpu/drm/tegra/fb.c err = drm_fb_helper_single_add_all_connectors(&fbdev->base); base 330 drivers/gpu/drm/tegra/fb.c err = drm_fb_helper_initial_config(&fbdev->base, preferred_bpp); base 340 drivers/gpu/drm/tegra/fb.c drm_fb_helper_fini(&fbdev->base); base 346 drivers/gpu/drm/tegra/fb.c drm_fb_helper_unregister_fbi(&fbdev->base); base 360 drivers/gpu/drm/tegra/fb.c drm_fb_helper_fini(&fbdev->base); base 183 drivers/gpu/drm/tegra/gem.c host1x_bo_init(&bo->base, &tegra_bo_ops); base 31 drivers/gpu/drm/tegra/gem.h struct host1x_bo base; base 53 drivers/gpu/drm/tegra/gem.h return container_of(bo, struct tegra_bo, base); base 219 drivers/gpu/drm/tegra/gr2d.c INIT_LIST_HEAD(&gr2d->client.base.list); base 220 drivers/gpu/drm/tegra/gr2d.c gr2d->client.base.ops = &gr2d_client_ops; base 221 drivers/gpu/drm/tegra/gr2d.c gr2d->client.base.dev = dev; base 222 drivers/gpu/drm/tegra/gr2d.c gr2d->client.base.class = HOST1X_CLASS_GR2D; base 223 drivers/gpu/drm/tegra/gr2d.c gr2d->client.base.syncpts = syncpts; base 224 drivers/gpu/drm/tegra/gr2d.c gr2d->client.base.num_syncpts = 1; base 230 drivers/gpu/drm/tegra/gr2d.c err = host1x_client_register(&gr2d->client.base); base 251 drivers/gpu/drm/tegra/gr2d.c err = host1x_client_unregister(&gr2d->client.base); base 346 drivers/gpu/drm/tegra/gr3d.c INIT_LIST_HEAD(&gr3d->client.base.list); base 347 drivers/gpu/drm/tegra/gr3d.c gr3d->client.base.ops = &gr3d_client_ops; base 348 drivers/gpu/drm/tegra/gr3d.c gr3d->client.base.dev = &pdev->dev; base 349 drivers/gpu/drm/tegra/gr3d.c gr3d->client.base.class = HOST1X_CLASS_GR3D; base 350 drivers/gpu/drm/tegra/gr3d.c gr3d->client.base.syncpts = syncpts; base 351 drivers/gpu/drm/tegra/gr3d.c gr3d->client.base.num_syncpts = 1; base 357 drivers/gpu/drm/tegra/gr3d.c err = host1x_client_register(&gr3d->client.base); base 378 drivers/gpu/drm/tegra/gr3d.c err = host1x_client_unregister(&gr3d->client.base); base 171 drivers/gpu/drm/tegra/hub.c mask = COMMON_UPDATE | WIN_A_UPDATE << plane->base.index; base 191 drivers/gpu/drm/tegra/hub.c mask = COMMON_ACTREQ | WIN_A_ACT_REQ << plane->base.index; base 312 drivers/gpu/drm/tegra/hub.c value |= THREAD_NUM(plane->base.index); base 369 drivers/gpu/drm/tegra/hub.c err = tegra_plane_state_add(&tegra->base, state); base 417 drivers/gpu/drm/tegra/hub.c dma_addr_t base; base 460 drivers/gpu/drm/tegra/hub.c base = bo->paddr; base 478 drivers/gpu/drm/tegra/hub.c tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI); base 479 drivers/gpu/drm/tegra/hub.c tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR); base 550 drivers/gpu/drm/tegra/hub.c plane->base.offset = 0x0a00 + 0x0300 * index; base 551 drivers/gpu/drm/tegra/hub.c plane->base.index = index; base 556 drivers/gpu/drm/tegra/hub.c p = &plane->base.base; base 585 drivers/gpu/drm/tegra/hub.c __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); base 587 drivers/gpu/drm/tegra/hub.c return &state->base; base 613 drivers/gpu/drm/tegra/hub.c priv = drm_atomic_get_private_obj_state(state, &hub->base); base 649 drivers/gpu/drm/tegra/hub.c hub_state->dc = to_tegra_dc(dc->base.crtc); base 690 drivers/gpu/drm/tegra/hub.c hub_state = to_tegra_display_hub_state(hub->base.state); base 719 drivers/gpu/drm/tegra/hub.c drm_atomic_private_obj_init(drm, &hub->base, &state->base, base 732 drivers/gpu/drm/tegra/hub.c drm_atomic_private_obj_fini(&tegra->hub->base); base 25 drivers/gpu/drm/tegra/hub.h struct tegra_plane base; base 32 drivers/gpu/drm/tegra/hub.h return container_of(plane, struct tegra_shared_plane, base.base); base 41 drivers/gpu/drm/tegra/hub.h struct drm_private_obj base; base 62 drivers/gpu/drm/tegra/hub.h struct drm_private_state base; base 72 drivers/gpu/drm/tegra/hub.h return container_of(priv, struct tegra_display_hub_state, base); base 35 drivers/gpu/drm/tegra/plane.c plane->state = &state->base; base 53 drivers/gpu/drm/tegra/plane.c __drm_atomic_helper_plane_duplicate_state(plane, ©->base); base 63 drivers/gpu/drm/tegra/plane.c return ©->base; base 342 drivers/gpu/drm/tegra/plane.c old = drm_atomic_get_old_plane_state(state->base.state, &tegra->base); base 345 drivers/gpu/drm/tegra/plane.c if (old->normalized_zpos == state->base.normalized_zpos && base 350 drivers/gpu/drm/tegra/plane.c drm_for_each_plane(plane, tegra->base.dev) { base 357 drivers/gpu/drm/tegra/plane.c plane_state = drm_atomic_get_plane_state(state->base.state, base 393 drivers/gpu/drm/tegra/plane.c for_each_new_plane_in_state(state->base.state, plane, new, i) { base 408 drivers/gpu/drm/tegra/plane.c if (new->normalized_zpos > state->base.normalized_zpos) base 445 drivers/gpu/drm/tegra/plane.c drm_for_each_plane(plane, tegra->base.dev) { base 452 drivers/gpu/drm/tegra/plane.c new = drm_atomic_get_new_plane_state(state->base.state, plane); base 15 drivers/gpu/drm/tegra/plane.h struct drm_plane base; base 22 drivers/gpu/drm/tegra/plane.h struct tegra_plane base; base 31 drivers/gpu/drm/tegra/plane.h return container_of(plane, struct tegra_plane, base); base 40 drivers/gpu/drm/tegra/plane.h struct drm_plane_state base; base 57 drivers/gpu/drm/tegra/plane.h return container_of(state, struct tegra_plane_state, base); base 304 drivers/gpu/drm/tegra/rgb.c output->encoder.possible_crtcs = drm_crtc_mask(&dc->base); base 437 drivers/gpu/drm/tegra/sor.c struct drm_connector_state base; base 447 drivers/gpu/drm/tegra/sor.c return container_of(state, struct tegra_sor_state, base); base 1513 drivers/gpu/drm/tegra/sor.c __drm_atomic_helper_connector_reset(connector, &state->base); base 1538 drivers/gpu/drm/tegra/sor.c __drm_atomic_helper_connector_duplicate_state(connector, ©->base); base 1540 drivers/gpu/drm/tegra/sor.c return ©->base; base 421 drivers/gpu/drm/tegra/vic.c INIT_LIST_HEAD(&vic->client.base.list); base 422 drivers/gpu/drm/tegra/vic.c vic->client.base.ops = &vic_client_ops; base 423 drivers/gpu/drm/tegra/vic.c vic->client.base.dev = dev; base 424 drivers/gpu/drm/tegra/vic.c vic->client.base.class = HOST1X_CLASS_VIC; base 425 drivers/gpu/drm/tegra/vic.c vic->client.base.syncpts = syncpts; base 426 drivers/gpu/drm/tegra/vic.c vic->client.base.num_syncpts = 1; base 433 drivers/gpu/drm/tegra/vic.c err = host1x_client_register(&vic->client.base); base 449 drivers/gpu/drm/tegra/vic.c host1x_client_unregister(&vic->client.base); base 461 drivers/gpu/drm/tegra/vic.c err = host1x_client_unregister(&vic->client.base); base 30 drivers/gpu/drm/tilcdc/tilcdc_crtc.c struct drm_crtc base; base 60 drivers/gpu/drm/tilcdc/tilcdc_crtc.c #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) base 554 drivers/gpu/drm/tilcdc/tilcdc_crtc.c struct drm_crtc *crtc = &tilcdc_crtc->base; base 996 drivers/gpu/drm/tilcdc/tilcdc_crtc.c crtc = &tilcdc_crtc->base; base 53 drivers/gpu/drm/tilcdc/tilcdc_external.c encoder->name, encoder->base.id); base 24 drivers/gpu/drm/tilcdc/tilcdc_panel.c struct tilcdc_module base; base 30 drivers/gpu/drm/tilcdc/tilcdc_panel.c #define to_panel_module(x) container_of(x, struct panel_module, base) base 38 drivers/gpu/drm/tilcdc/tilcdc_panel.c struct drm_encoder base; base 41 drivers/gpu/drm/tilcdc/tilcdc_panel.c #define to_panel_encoder(x) container_of(x, struct panel_encoder, base) base 102 drivers/gpu/drm/tilcdc/tilcdc_panel.c encoder = &panel_encoder->base; base 124 drivers/gpu/drm/tilcdc/tilcdc_panel.c struct drm_connector base; base 129 drivers/gpu/drm/tilcdc/tilcdc_panel.c #define to_panel_connector(x) container_of(x, struct panel_connector, base) base 201 drivers/gpu/drm/tilcdc/tilcdc_panel.c connector = &panel_connector->base; base 344 drivers/gpu/drm/tilcdc/tilcdc_panel.c mod = &panel_mod->base; base 22 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c struct tilcdc_module base; base 26 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c #define to_tfp410_module(x) container_of(x, struct tfp410_module, base) base 46 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c struct drm_encoder base; base 50 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c #define to_tfp410_encoder(x) container_of(x, struct tfp410_encoder, base) base 113 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c encoder = &tfp410_encoder->base; base 135 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c struct drm_connector base; base 140 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c #define to_tfp410_connector(x) container_of(x, struct tfp410_connector, base) base 215 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c connector = &tfp410_connector->base; base 292 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c mod = &tfp410_mod->base; base 100 drivers/gpu/drm/tiny/ili9225.c DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect)); base 534 drivers/gpu/drm/tiny/repaper.c struct dma_buf_attachment *import_attach = cma_obj->base.import_attach; base 554 drivers/gpu/drm/tiny/repaper.c DRM_DEBUG("Flushing [FB:%d] st=%ums\n", fb->base.id, base 95 drivers/gpu/drm/tiny/st7586.c struct dma_buf_attachment *import_attach = cma_obj->base.import_attach; base 131 drivers/gpu/drm/tiny/st7586.c DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect)); base 164 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_fini(&bo->base._resv); base 176 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(bo->base.resv); base 248 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(bo->base.resv); base 281 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(pos->first->base.resv); base 282 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(pos->last->base.resv); base 296 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(pos->first->base.resv); base 297 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(pos->last->base.resv); base 311 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(pos->first->base.resv); base 312 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(pos->last->base.resv); base 443 drivers/gpu/drm/ttm/ttm_bo.c if (bo->base.resv == &bo->base._resv) base 446 drivers/gpu/drm/ttm/ttm_bo.c BUG_ON(!dma_resv_trylock(&bo->base._resv)); base 448 drivers/gpu/drm/ttm/ttm_bo.c r = dma_resv_copy_fences(&bo->base._resv, bo->base.resv); base 450 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(&bo->base._resv); base 461 drivers/gpu/drm/ttm/ttm_bo.c fobj = dma_resv_get_list(&bo->base._resv); base 462 drivers/gpu/drm/ttm/ttm_bo.c fence = dma_resv_get_excl(&bo->base._resv); base 468 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_held(bo->base.resv)); base 486 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_wait_timeout_rcu(bo->base.resv, true, false, base 493 drivers/gpu/drm/ttm/ttm_bo.c ret = dma_resv_trylock(bo->base.resv) ? 0 : -EBUSY; base 495 drivers/gpu/drm/ttm/ttm_bo.c if (dma_resv_test_signaled_rcu(&bo->base._resv, true)) { base 498 drivers/gpu/drm/ttm/ttm_bo.c if (bo->base.resv != &bo->base._resv) base 499 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(&bo->base._resv); base 502 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(bo->base.resv); base 518 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(bo->base.resv); base 520 drivers/gpu/drm/ttm/ttm_bo.c if (bo->base.resv != &bo->base._resv) { base 522 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(&bo->base._resv); base 556 drivers/gpu/drm/ttm/ttm_bo.c resv = bo->base.resv; base 558 drivers/gpu/drm/ttm/ttm_bo.c resv = &bo->base._resv; base 569 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(bo->base.resv); base 582 drivers/gpu/drm/ttm/ttm_bo.c if (unlock_resv && !dma_resv_trylock(bo->base.resv)) { base 599 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(bo->base.resv); base 612 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(bo->base.resv); base 638 drivers/gpu/drm/ttm/ttm_bo.c if (remove_all || bo->base.resv != &bo->base._resv) { base 640 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_lock(bo->base.resv, NULL); base 645 drivers/gpu/drm/ttm/ttm_bo.c } else if (dma_resv_trylock(bo->base.resv)) { base 681 drivers/gpu/drm/ttm/ttm_bo.c drm_vma_offset_remove(&bdev->vma_manager, &bo->base.vma_node); base 717 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(bo->base.resv); base 787 drivers/gpu/drm/ttm/ttm_bo.c if (bo->base.resv == ctx->resv) { base 788 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(bo->base.resv); base 796 drivers/gpu/drm/ttm/ttm_bo.c ret = dma_resv_trylock(bo->base.resv); base 824 drivers/gpu/drm/ttm/ttm_bo.c r = dma_resv_lock_interruptible(busy_bo->base.resv, base 827 drivers/gpu/drm/ttm/ttm_bo.c r = dma_resv_lock(busy_bo->base.resv, ticket); base 835 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(busy_bo->base.resv); base 861 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_locking_ctx(bo->base.resv)) base 869 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(bo->base.resv); base 947 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_add_shared_fence(bo->base.resv, fence); base 949 drivers/gpu/drm/ttm/ttm_bo.c ret = dma_resv_reserve_shared(bo->base.resv, 1); base 974 drivers/gpu/drm/ttm/ttm_bo.c ticket = dma_resv_locking_ctx(bo->base.resv); base 1104 drivers/gpu/drm/ttm/ttm_bo.c ret = dma_resv_reserve_shared(bo->base.resv, 1); base 1189 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(bo->base.resv); base 1259 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(bo->base.resv); base 1349 drivers/gpu/drm/ttm/ttm_bo.c bo->base.resv = resv; base 1350 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_assert_held(bo->base.resv); base 1352 drivers/gpu/drm/ttm/ttm_bo.c bo->base.resv = &bo->base._resv; base 1359 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_init(&bo->base._resv); base 1360 drivers/gpu/drm/ttm/ttm_bo.c drm_vma_node_reset(&bo->base.vma_node); base 1370 drivers/gpu/drm/ttm/ttm_bo.c ret = drm_vma_offset_add(&bdev->vma_manager, &bo->base.vma_node, base 1377 drivers/gpu/drm/ttm/ttm_bo.c locked = dma_resv_trylock(bo->base.resv); base 1798 drivers/gpu/drm/ttm/ttm_bo.c drm_vma_node_unmap(&bo->base.vma_node, bdev->dev_mapping); base 1821 drivers/gpu/drm/ttm/ttm_bo.c if (dma_resv_test_signaled_rcu(bo->base.resv, true)) base 1827 drivers/gpu/drm/ttm/ttm_bo.c timeout = dma_resv_wait_timeout_rcu(bo->base.resv, true, base 1835 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_add_excl_fence(bo->base.resv, NULL); base 1951 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(bo->base.resv); base 1989 drivers/gpu/drm/ttm/ttm_bo.c if (!dma_resv_is_locked(bo->base.resv)) base 1991 drivers/gpu/drm/ttm/ttm_bo.c ret = dma_resv_lock_interruptible(bo->base.resv, NULL); base 1996 drivers/gpu/drm/ttm/ttm_bo.c dma_resv_unlock(bo->base.resv); base 44 drivers/gpu/drm/ttm/ttm_bo_util.c struct ttm_buffer_object base; base 223 drivers/gpu/drm/ttm/ttm_bo_util.c addr = ioremap_wc(mem->bus.base + mem->bus.offset, mem->bus.size); base 225 drivers/gpu/drm/ttm/ttm_bo_util.c addr = ioremap_nocache(mem->bus.base + mem->bus.offset, mem->bus.size); base 465 drivers/gpu/drm/ttm/ttm_bo_util.c fbo = container_of(bo, struct ttm_transfer_obj, base); base 495 drivers/gpu/drm/ttm/ttm_bo_util.c fbo->base = *bo; base 496 drivers/gpu/drm/ttm/ttm_bo_util.c fbo->base.mem.placement |= TTM_PL_FLAG_NO_EVICT; base 507 drivers/gpu/drm/ttm/ttm_bo_util.c INIT_LIST_HEAD(&fbo->base.ddestroy); base 508 drivers/gpu/drm/ttm/ttm_bo_util.c INIT_LIST_HEAD(&fbo->base.lru); base 509 drivers/gpu/drm/ttm/ttm_bo_util.c INIT_LIST_HEAD(&fbo->base.swap); base 510 drivers/gpu/drm/ttm/ttm_bo_util.c INIT_LIST_HEAD(&fbo->base.io_reserve_lru); base 511 drivers/gpu/drm/ttm/ttm_bo_util.c mutex_init(&fbo->base.wu_mutex); base 512 drivers/gpu/drm/ttm/ttm_bo_util.c fbo->base.moving = NULL; base 513 drivers/gpu/drm/ttm/ttm_bo_util.c drm_vma_node_reset(&fbo->base.base.vma_node); base 514 drivers/gpu/drm/ttm/ttm_bo_util.c atomic_set(&fbo->base.cpu_writers, 0); base 516 drivers/gpu/drm/ttm/ttm_bo_util.c kref_init(&fbo->base.list_kref); base 517 drivers/gpu/drm/ttm/ttm_bo_util.c kref_init(&fbo->base.kref); base 518 drivers/gpu/drm/ttm/ttm_bo_util.c fbo->base.destroy = &ttm_transfered_destroy; base 519 drivers/gpu/drm/ttm/ttm_bo_util.c fbo->base.acc_size = 0; base 520 drivers/gpu/drm/ttm/ttm_bo_util.c fbo->base.base.resv = &fbo->base.base._resv; base 521 drivers/gpu/drm/ttm/ttm_bo_util.c dma_resv_init(fbo->base.base.resv); base 522 drivers/gpu/drm/ttm/ttm_bo_util.c ret = dma_resv_trylock(fbo->base.base.resv); base 525 drivers/gpu/drm/ttm/ttm_bo_util.c *new_obj = &fbo->base; base 568 drivers/gpu/drm/ttm/ttm_bo_util.c map->virtual = ioremap_wc(bo->mem.bus.base + bo->mem.bus.offset + offset, base 571 drivers/gpu/drm/ttm/ttm_bo_util.c map->virtual = ioremap_nocache(bo->mem.bus.base + bo->mem.bus.offset + offset, base 692 drivers/gpu/drm/ttm/ttm_bo_util.c dma_resv_add_excl_fence(bo->base.resv, fence); base 719 drivers/gpu/drm/ttm/ttm_bo_util.c dma_resv_add_excl_fence(ghost_obj->base.resv, fence); base 755 drivers/gpu/drm/ttm/ttm_bo_util.c dma_resv_add_excl_fence(bo->base.resv, fence); base 775 drivers/gpu/drm/ttm/ttm_bo_util.c dma_resv_add_excl_fence(ghost_obj->base.resv, fence); base 844 drivers/gpu/drm/ttm/ttm_bo_util.c ret = dma_resv_copy_fences(ghost->base.resv, bo->base.resv); base 74 drivers/gpu/drm/ttm/ttm_bo_vm.c dma_resv_unlock(bo->base.resv); base 105 drivers/gpu/drm/ttm/ttm_bo_vm.c return ((bo->mem.bus.base + bo->mem.bus.offset) >> PAGE_SHIFT) base 134 drivers/gpu/drm/ttm/ttm_bo_vm.c if (unlikely(!dma_resv_trylock(bo->base.resv))) { base 214 drivers/gpu/drm/ttm/ttm_bo_vm.c vma->vm_pgoff - drm_vma_node_start(&bo->base.vma_node); base 216 drivers/gpu/drm/ttm/ttm_bo_vm.c drm_vma_node_start(&bo->base.vma_node); base 270 drivers/gpu/drm/ttm/ttm_bo_vm.c page->index = drm_vma_node_start(&bo->base.vma_node) + base 297 drivers/gpu/drm/ttm/ttm_bo_vm.c dma_resv_unlock(bo->base.resv); base 415 drivers/gpu/drm/ttm/ttm_bo_vm.c base.vma_node); base 42 drivers/gpu/drm/ttm/ttm_execbuf_util.c dma_resv_unlock(bo->base.resv); base 74 drivers/gpu/drm/ttm/ttm_execbuf_util.c dma_resv_unlock(bo->base.resv); base 117 drivers/gpu/drm/ttm/ttm_execbuf_util.c dma_resv_unlock(bo->base.resv); base 133 drivers/gpu/drm/ttm/ttm_execbuf_util.c ret = dma_resv_reserve_shared(bo->base.resv, base 147 drivers/gpu/drm/ttm/ttm_execbuf_util.c ret = dma_resv_lock_slow_interruptible(bo->base.resv, base 150 drivers/gpu/drm/ttm/ttm_execbuf_util.c dma_resv_lock_slow(bo->base.resv, ticket); base 156 drivers/gpu/drm/ttm/ttm_execbuf_util.c ret = dma_resv_reserve_shared(bo->base.resv, base 204 drivers/gpu/drm/ttm/ttm_execbuf_util.c dma_resv_add_shared_fence(bo->base.resv, fence); base 206 drivers/gpu/drm/ttm/ttm_execbuf_util.c dma_resv_add_excl_fence(bo->base.resv, fence); base 211 drivers/gpu/drm/ttm/ttm_execbuf_util.c dma_resv_unlock(bo->base.resv); base 51 drivers/gpu/drm/ttm/ttm_tt.c dma_resv_assert_held(bo->base.resv); base 67 drivers/gpu/drm/udl/udl_dmabuf.c struct drm_device *dev = obj->base.dev; base 90 drivers/gpu/drm/udl/udl_dmabuf.c page_count = obj->base.size / PAGE_SIZE; base 243 drivers/gpu/drm/udl/udl_dmabuf.c uobj->base.import_attach = attach; base 246 drivers/gpu/drm/udl/udl_dmabuf.c return &uobj->base; base 80 drivers/gpu/drm/udl/udl_drv.h struct drm_gem_object base; base 87 drivers/gpu/drm/udl/udl_drv.h #define to_udl_bo(x) container_of(x, struct udl_gem_object, base) base 90 drivers/gpu/drm/udl/udl_drv.h struct drm_framebuffer base; base 95 drivers/gpu/drm/udl/udl_drv.h #define to_udl_fb(x) container_of(x, struct udl_framebuffer, base) base 80 drivers/gpu/drm/udl/udl_fb.c struct drm_device *dev = fb->base.dev; base 91 drivers/gpu/drm/udl/udl_fb.c BUG_ON(!is_power_of_2(fb->base.format->cpp[0])); base 92 drivers/gpu/drm/udl/udl_fb.c log_bpp = __ffs(fb->base.format->cpp[0]); base 114 drivers/gpu/drm/udl/udl_fb.c (x + width > fb->base.width) || base 115 drivers/gpu/drm/udl/udl_fb.c (y + height > fb->base.height)) base 126 drivers/gpu/drm/udl/udl_fb.c const int line_offset = fb->base.pitches[0] * i; base 128 drivers/gpu/drm/udl/udl_fb.c const int dev_byte_offset = (fb->base.width * i + x) << log_bpp; base 208 drivers/gpu/drm/udl/udl_fb.c struct drm_device *dev = ufbdev->ufb.base.dev; base 292 drivers/gpu/drm/udl/udl_fb.c if (ufb->obj->base.import_attach) { base 293 drivers/gpu/drm/udl/udl_fb.c ret = dma_buf_begin_cpu_access(ufb->obj->base.import_attach->dmabuf, base 307 drivers/gpu/drm/udl/udl_fb.c if (ufb->obj->base.import_attach) { base 308 drivers/gpu/drm/udl/udl_fb.c ret = dma_buf_end_cpu_access(ufb->obj->base.import_attach->dmabuf, base 323 drivers/gpu/drm/udl/udl_fb.c drm_gem_object_put_unlocked(&ufb->obj->base); base 344 drivers/gpu/drm/udl/udl_fb.c drm_helper_mode_fill_fb_struct(dev, &ufb->base, mode_cmd); base 345 drivers/gpu/drm/udl/udl_fb.c ret = drm_framebuffer_init(dev, &ufb->base, &udlfb_funcs); base 396 drivers/gpu/drm/udl/udl_fb.c fb = &ufbdev->ufb.base; base 413 drivers/gpu/drm/udl/udl_fb.c drm_gem_object_put_unlocked(&ufbdev->ufb.obj->base); base 428 drivers/gpu/drm/udl/udl_fb.c drm_framebuffer_unregister_private(&ufbdev->ufb.base); base 429 drivers/gpu/drm/udl/udl_fb.c drm_framebuffer_cleanup(&ufbdev->ufb.base); base 430 drivers/gpu/drm/udl/udl_fb.c drm_gem_object_put_unlocked(&ufbdev->ufb.obj->base); base 526 drivers/gpu/drm/udl/udl_fb.c return &ufb->base; base 23 drivers/gpu/drm/udl/udl_gem.c if (drm_gem_object_init(dev, &obj->base, size) != 0) { base 48 drivers/gpu/drm/udl/udl_gem.c ret = drm_gem_handle_create(file, &obj->base, &handle); base 50 drivers/gpu/drm/udl/udl_gem.c drm_gem_object_release(&obj->base); base 55 drivers/gpu/drm/udl/udl_gem.c drm_gem_object_put_unlocked(&obj->base); base 126 drivers/gpu/drm/udl/udl_gem.c pages = drm_gem_get_pages(&obj->base); base 137 drivers/gpu/drm/udl/udl_gem.c if (obj->base.import_attach) { base 143 drivers/gpu/drm/udl/udl_gem.c drm_gem_put_pages(&obj->base, obj->pages, false, false); base 149 drivers/gpu/drm/udl/udl_gem.c int page_count = obj->base.size / PAGE_SIZE; base 152 drivers/gpu/drm/udl/udl_gem.c if (obj->base.import_attach) { base 153 drivers/gpu/drm/udl/udl_gem.c obj->vmapping = dma_buf_vmap(obj->base.import_attach->dmabuf); base 171 drivers/gpu/drm/udl/udl_gem.c if (obj->base.import_attach) { base 172 drivers/gpu/drm/udl/udl_gem.c dma_buf_vunmap(obj->base.import_attach->dmabuf, obj->vmapping); base 224 drivers/gpu/drm/udl/udl_gem.c *offset = drm_vma_node_offset_addr(&gobj->base.vma_node); base 227 drivers/gpu/drm/udl/udl_gem.c drm_gem_object_put_unlocked(&gobj->base); base 73 drivers/gpu/drm/udl/udl_modeset.c static char *udl_set_base16bpp(char *wrptr, u32 base) base 76 drivers/gpu/drm/udl/udl_modeset.c wrptr = udl_set_register(wrptr, 0x20, base >> 16); base 77 drivers/gpu/drm/udl/udl_modeset.c wrptr = udl_set_register(wrptr, 0x21, base >> 8); base 78 drivers/gpu/drm/udl/udl_modeset.c return udl_set_register(wrptr, 0x22, base); base 85 drivers/gpu/drm/udl/udl_modeset.c static char *udl_set_base8bpp(char *wrptr, u32 base) base 87 drivers/gpu/drm/udl/udl_modeset.c wrptr = udl_set_register(wrptr, 0x26, base >> 16); base 88 drivers/gpu/drm/udl/udl_modeset.c wrptr = udl_set_register(wrptr, 0x27, base >> 8); base 89 drivers/gpu/drm/udl/udl_modeset.c return udl_set_register(wrptr, 0x28, base); base 343 drivers/gpu/drm/udl/udl_modeset.c udl_handle_damage(ufb, 0, 0, ufb->base.width, ufb->base.height); base 462 drivers/gpu/drm/udl/udl_modeset.c udl_handle_damage(ufb, 0, 0, ufb->base.width, ufb->base.height); base 48 drivers/gpu/drm/v3d/v3d_bo.c bo->base.pages_mark_dirty_on_put = true; base 78 drivers/gpu/drm/v3d/v3d_bo.c obj = &bo->base.base; base 84 drivers/gpu/drm/v3d/v3d_bo.c return &bo->base.base; base 98 drivers/gpu/drm/v3d/v3d_bo.c sgt = drm_gem_shmem_get_pages_sgt(&bo->base.base); base 135 drivers/gpu/drm/v3d/v3d_bo.c bo = to_v3d_bo(&shmem_obj->base); base 137 drivers/gpu/drm/v3d/v3d_bo.c ret = v3d_bo_create_finish(&shmem_obj->base); base 144 drivers/gpu/drm/v3d/v3d_bo.c drm_gem_shmem_free_object(&shmem_obj->base); base 187 drivers/gpu/drm/v3d/v3d_bo.c ret = drm_gem_handle_create(file_priv, &bo->base.base, &args->handle); base 188 drivers/gpu/drm/v3d/v3d_bo.c drm_gem_object_put_unlocked(&bo->base.base); base 141 drivers/gpu/drm/v3d/v3d_drv.h struct drm_gem_shmem_object base; base 158 drivers/gpu/drm/v3d/v3d_drv.h struct dma_fence base; base 184 drivers/gpu/drm/v3d/v3d_drv.h struct drm_sched_job base; base 214 drivers/gpu/drm/v3d/v3d_drv.h struct v3d_job base; base 229 drivers/gpu/drm/v3d/v3d_drv.h struct v3d_job base; base 243 drivers/gpu/drm/v3d/v3d_drv.h struct v3d_job base; base 249 drivers/gpu/drm/v3d/v3d_drv.h struct v3d_job base; base 17 drivers/gpu/drm/v3d/v3d_fence.c dma_fence_init(&fence->base, &v3d_fence_ops, &v3d->job_lock, base 20 drivers/gpu/drm/v3d/v3d_fence.c return &fence->base; base 383 drivers/gpu/drm/v3d/v3d_gem.c base.refcount); base 387 drivers/gpu/drm/v3d/v3d_gem.c drm_gem_object_put_unlocked(&bo->base.base); base 471 drivers/gpu/drm/v3d/v3d_gem.c ret = drm_sched_job_init(&job->base, &v3d_priv->sched_entity[queue], base 476 drivers/gpu/drm/v3d/v3d_gem.c job->done_fence = dma_fence_get(&job->base.s_fence->finished); base 481 drivers/gpu/drm/v3d/v3d_gem.c drm_sched_entity_push_job(&job->base, &v3d_priv->sched_entity[queue]); base 551 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_job_init(v3d, file_priv, &render->base, base 561 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&render->base); base 565 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_job_init(v3d, file_priv, &bin->base, base 568 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&render->base); base 581 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_lookup_bos(dev, file_priv, &render->base, base 586 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_lock_bo_reservations(&render->base, &acquire_ctx); base 592 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_push_job(v3d_priv, &bin->base, V3D_BIN); base 596 drivers/gpu/drm/v3d/v3d_gem.c ret = drm_gem_fence_array_add(&render->base.deps, base 597 drivers/gpu/drm/v3d/v3d_gem.c dma_fence_get(bin->base.done_fence)); base 602 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_push_job(v3d_priv, &render->base, V3D_RENDER); base 608 drivers/gpu/drm/v3d/v3d_gem.c &render->base, base 611 drivers/gpu/drm/v3d/v3d_gem.c render->base.done_fence); base 614 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&bin->base); base 615 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&render->base); base 621 drivers/gpu/drm/v3d/v3d_gem.c drm_gem_unlock_reservations(render->base.bo, base 622 drivers/gpu/drm/v3d/v3d_gem.c render->base.bo_count, &acquire_ctx); base 625 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&bin->base); base 626 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&render->base); base 657 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_job_init(v3d, file_priv, &job->base, base 664 drivers/gpu/drm/v3d/v3d_gem.c job->base.bo = kcalloc(ARRAY_SIZE(args->bo_handles), base 665 drivers/gpu/drm/v3d/v3d_gem.c sizeof(*job->base.bo), GFP_KERNEL); base 666 drivers/gpu/drm/v3d/v3d_gem.c if (!job->base.bo) { base 667 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&job->base); base 674 drivers/gpu/drm/v3d/v3d_gem.c for (job->base.bo_count = 0; base 675 drivers/gpu/drm/v3d/v3d_gem.c job->base.bo_count < ARRAY_SIZE(args->bo_handles); base 676 drivers/gpu/drm/v3d/v3d_gem.c job->base.bo_count++) { base 679 drivers/gpu/drm/v3d/v3d_gem.c if (!args->bo_handles[job->base.bo_count]) base 683 drivers/gpu/drm/v3d/v3d_gem.c args->bo_handles[job->base.bo_count]); base 686 drivers/gpu/drm/v3d/v3d_gem.c job->base.bo_count, base 687 drivers/gpu/drm/v3d/v3d_gem.c args->bo_handles[job->base.bo_count]); base 693 drivers/gpu/drm/v3d/v3d_gem.c job->base.bo[job->base.bo_count] = bo; base 697 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_lock_bo_reservations(&job->base, &acquire_ctx); base 702 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_push_job(v3d_priv, &job->base, V3D_TFU); base 708 drivers/gpu/drm/v3d/v3d_gem.c &job->base, &acquire_ctx, base 710 drivers/gpu/drm/v3d/v3d_gem.c job->base.done_fence); base 712 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&job->base); base 718 drivers/gpu/drm/v3d/v3d_gem.c drm_gem_unlock_reservations(job->base.bo, job->base.bo_count, base 721 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&job->base); base 758 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_job_init(v3d, file_priv, &job->base, base 767 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&job->base); base 774 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&job->base); base 791 drivers/gpu/drm/v3d/v3d_gem.c ret = v3d_push_job(v3d_priv, &job->base, V3D_CSD); base 796 drivers/gpu/drm/v3d/v3d_gem.c dma_fence_get(job->base.done_fence)); base 811 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&job->base); base 821 drivers/gpu/drm/v3d/v3d_gem.c v3d_job_put(&job->base); base 50 drivers/gpu/drm/v3d/v3d_irq.c obj = &bo->base.base; base 102 drivers/gpu/drm/v3d/v3d_irq.c to_v3d_fence(v3d->bin_job->base.irq_fence); base 105 drivers/gpu/drm/v3d/v3d_irq.c dma_fence_signal(&fence->base); base 111 drivers/gpu/drm/v3d/v3d_irq.c to_v3d_fence(v3d->render_job->base.irq_fence); base 114 drivers/gpu/drm/v3d/v3d_irq.c dma_fence_signal(&fence->base); base 120 drivers/gpu/drm/v3d/v3d_irq.c to_v3d_fence(v3d->csd_job->base.irq_fence); base 123 drivers/gpu/drm/v3d/v3d_irq.c dma_fence_signal(&fence->base); base 156 drivers/gpu/drm/v3d/v3d_irq.c to_v3d_fence(v3d->tfu_job->base.irq_fence); base 159 drivers/gpu/drm/v3d/v3d_irq.c dma_fence_signal(&fence->base); base 89 drivers/gpu/drm/v3d/v3d_mmu.c struct drm_gem_shmem_object *shmem_obj = &bo->base; base 90 drivers/gpu/drm/v3d/v3d_mmu.c struct v3d_dev *v3d = to_v3d_dev(shmem_obj->base.dev); base 109 drivers/gpu/drm/v3d/v3d_mmu.c shmem_obj->base.size >> V3D_MMU_PAGE_SHIFT); base 117 drivers/gpu/drm/v3d/v3d_mmu.c struct v3d_dev *v3d = to_v3d_dev(bo->base.base.dev); base 118 drivers/gpu/drm/v3d/v3d_mmu.c u32 npages = bo->base.base.size >> V3D_MMU_PAGE_SHIFT; base 30 drivers/gpu/drm/v3d/v3d_sched.c return container_of(sched_job, struct v3d_job, base); base 36 drivers/gpu/drm/v3d/v3d_sched.c return container_of(sched_job, struct v3d_bin_job, base.base); base 42 drivers/gpu/drm/v3d/v3d_sched.c return container_of(sched_job, struct v3d_render_job, base.base); base 48 drivers/gpu/drm/v3d/v3d_sched.c return container_of(sched_job, struct v3d_tfu_job, base.base); base 54 drivers/gpu/drm/v3d/v3d_sched.c return container_of(sched_job, struct v3d_csd_job, base.base); base 91 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->base.v3d; base 96 drivers/gpu/drm/v3d/v3d_sched.c if (unlikely(job->base.base.s_fence->finished.error)) base 116 drivers/gpu/drm/v3d/v3d_sched.c if (job->base.irq_fence) base 117 drivers/gpu/drm/v3d/v3d_sched.c dma_fence_put(job->base.irq_fence); base 118 drivers/gpu/drm/v3d/v3d_sched.c job->base.irq_fence = dma_fence_get(fence); base 144 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->base.v3d; base 148 drivers/gpu/drm/v3d/v3d_sched.c if (unlikely(job->base.base.s_fence->finished.error)) base 165 drivers/gpu/drm/v3d/v3d_sched.c if (job->base.irq_fence) base 166 drivers/gpu/drm/v3d/v3d_sched.c dma_fence_put(job->base.irq_fence); base 167 drivers/gpu/drm/v3d/v3d_sched.c job->base.irq_fence = dma_fence_get(fence); base 187 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->base.v3d; base 196 drivers/gpu/drm/v3d/v3d_sched.c if (job->base.irq_fence) base 197 drivers/gpu/drm/v3d/v3d_sched.c dma_fence_put(job->base.irq_fence); base 198 drivers/gpu/drm/v3d/v3d_sched.c job->base.irq_fence = dma_fence_get(fence); base 224 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->base.v3d; base 237 drivers/gpu/drm/v3d/v3d_sched.c if (job->base.irq_fence) base 238 drivers/gpu/drm/v3d/v3d_sched.c dma_fence_put(job->base.irq_fence); base 239 drivers/gpu/drm/v3d/v3d_sched.c job->base.irq_fence = dma_fence_get(fence); base 343 drivers/gpu/drm/v3d/v3d_sched.c struct v3d_dev *v3d = job->base.v3d; base 52 drivers/gpu/drm/vboxvideo/vbox_drv.h struct drm_framebuffer base; base 93 drivers/gpu/drm/vboxvideo/vbox_drv.h struct drm_connector base; base 104 drivers/gpu/drm/vboxvideo/vbox_drv.h struct drm_crtc base; base 134 drivers/gpu/drm/vboxvideo/vbox_drv.h struct drm_encoder base; base 137 drivers/gpu/drm/vboxvideo/vbox_drv.h #define to_vbox_crtc(x) container_of(x, struct vbox_crtc, base) base 138 drivers/gpu/drm/vboxvideo/vbox_drv.h #define to_vbox_connector(x) container_of(x, struct vbox_connector, base) base 139 drivers/gpu/drm/vboxvideo/vbox_drv.h #define to_vbox_encoder(x) container_of(x, struct vbox_encoder, base) base 140 drivers/gpu/drm/vboxvideo/vbox_drv.h #define to_vbox_framebuffer(x) container_of(x, struct vbox_framebuffer, base) base 93 drivers/gpu/drm/vboxvideo/vbox_fb.c fb = &vbox->afb.base; base 102 drivers/gpu/drm/vboxvideo/vbox_fb.c info->apertures->ranges[0].base = pci_resource_start(pdev, 0); base 110 drivers/gpu/drm/vboxvideo/vbox_fb.c info->fix.smem_start = info->apertures->ranges[0].base + gpu_addr; base 147 drivers/gpu/drm/vboxvideo/vbox_fb.c drm_framebuffer_unregister_private(&afb->base); base 148 drivers/gpu/drm/vboxvideo/vbox_fb.c drm_framebuffer_cleanup(&afb->base); base 111 drivers/gpu/drm/vboxvideo/vbox_main.c drm_helper_mode_fill_fb_struct(&vbox->ddev, &vbox_fb->base, mode_cmd); base 113 drivers/gpu/drm/vboxvideo/vbox_main.c ret = drm_framebuffer_init(&vbox->ddev, &vbox_fb->base, &vbox_fb_funcs); base 295 drivers/gpu/drm/vboxvideo/vbox_main.c *obj = &gbo->bo.base; base 610 drivers/gpu/drm/vboxvideo/vbox_mode.c ret = drm_crtc_init_with_planes(dev, &vbox_crtc->base, primary, cursor, base 615 drivers/gpu/drm/vboxvideo/vbox_mode.c drm_mode_crtc_set_gamma_size(&vbox_crtc->base, 256); base 616 drivers/gpu/drm/vboxvideo/vbox_mode.c drm_crtc_helper_add(&vbox_crtc->base, &vbox_crtc_helper_funcs); base 652 drivers/gpu/drm/vboxvideo/vbox_mode.c drm_encoder_init(dev, &vbox_encoder->base, &vbox_enc_funcs, base 655 drivers/gpu/drm/vboxvideo/vbox_mode.c vbox_encoder->base.possible_crtcs = 1 << i; base 656 drivers/gpu/drm/vboxvideo/vbox_mode.c return &vbox_encoder->base; base 761 drivers/gpu/drm/vboxvideo/vbox_mode.c drm_object_property_set_value(&connector->base, base 765 drivers/gpu/drm/vboxvideo/vbox_mode.c drm_object_property_set_value(&connector->base, base 769 drivers/gpu/drm/vboxvideo/vbox_mode.c drm_object_property_set_value(&connector->base, base 773 drivers/gpu/drm/vboxvideo/vbox_mode.c drm_object_property_set_value(&connector->base, base 805 drivers/gpu/drm/vboxvideo/vbox_mode.c dev = vbox_connector->base.dev; base 838 drivers/gpu/drm/vboxvideo/vbox_mode.c connector = &vbox_connector->base; base 849 drivers/gpu/drm/vboxvideo/vbox_mode.c drm_object_attach_property(&connector->base, base 851 drivers/gpu/drm/vboxvideo/vbox_mode.c drm_object_attach_property(&connector->base, base 882 drivers/gpu/drm/vboxvideo/vbox_mode.c return &vbox_fb->base; base 308 drivers/gpu/drm/vboxvideo/vboxvideo.h struct vbva_enable base; base 117 drivers/gpu/drm/vboxvideo/vbva_base.c p->base.flags = enable ? VBVA_F_ENABLE : VBVA_F_DISABLE; base 118 drivers/gpu/drm/vboxvideo/vbva_base.c p->base.offset = vbva_ctx->buffer_offset; base 119 drivers/gpu/drm/vboxvideo/vbva_base.c p->base.result = VERR_NOT_SUPPORTED; base 121 drivers/gpu/drm/vboxvideo/vbva_base.c p->base.flags |= VBVA_F_EXTENDED | VBVA_F_ABSOFFSET; base 128 drivers/gpu/drm/vboxvideo/vbva_base.c ret = p->base.result >= 0; base 164 drivers/gpu/drm/vc4/vc4_bo.c struct drm_gem_object *obj = &bo->base.base; base 183 drivers/gpu/drm/vc4/vc4_bo.c struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev); base 247 drivers/gpu/drm/vc4/vc4_bo.c struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev); base 252 drivers/gpu/drm/vc4/vc4_bo.c vc4->purgeable.size += bo->base.base.size; base 258 drivers/gpu/drm/vc4/vc4_bo.c struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev); base 274 drivers/gpu/drm/vc4/vc4_bo.c vc4->purgeable.size -= bo->base.base.size; base 279 drivers/gpu/drm/vc4/vc4_bo.c struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev); base 296 drivers/gpu/drm/vc4/vc4_bo.c dma_free_wc(dev->dev, obj->size, bo->base.vaddr, bo->base.paddr); base 297 drivers/gpu/drm/vc4/vc4_bo.c bo->base.vaddr = NULL; base 309 drivers/gpu/drm/vc4/vc4_bo.c struct drm_gem_object *obj = &bo->base.base; base 334 drivers/gpu/drm/vc4/vc4_bo.c purged_size = bo->base.base.size; base 368 drivers/gpu/drm/vc4/vc4_bo.c kref_init(&bo->base.base.refcount); base 372 drivers/gpu/drm/vc4/vc4_bo.c vc4_bo_set_label(&bo->base.base, type); base 403 drivers/gpu/drm/vc4/vc4_bo.c return &bo->base.base; base 421 drivers/gpu/drm/vc4/vc4_bo.c memset(bo->base.vaddr, 0, bo->base.base.size); base 457 drivers/gpu/drm/vc4/vc4_bo.c bo = to_vc4_bo(&cma_obj->base); base 466 drivers/gpu/drm/vc4/vc4_bo.c vc4_bo_set_label(&cma_obj->base, type); base 492 drivers/gpu/drm/vc4/vc4_bo.c ret = drm_gem_handle_create(file_priv, &bo->base.base, &args->handle); base 493 drivers/gpu/drm/vc4/vc4_bo.c drm_gem_object_put_unlocked(&bo->base.base); base 554 drivers/gpu/drm/vc4/vc4_bo.c if (!bo->base.vaddr) { base 581 drivers/gpu/drm/vc4/vc4_bo.c vc4_bo_set_label(&bo->base.base, VC4_BO_TYPE_KERNEL_CACHE); base 748 drivers/gpu/drm/vc4/vc4_bo.c ret = dma_mmap_wc(bo->base.base.dev->dev, vma, bo->base.vaddr, base 749 drivers/gpu/drm/vc4/vc4_bo.c bo->base.paddr, vma->vm_end - vma->vm_start); base 836 drivers/gpu/drm/vc4/vc4_bo.c ret = drm_gem_handle_create(file_priv, &bo->base.base, &args->handle); base 837 drivers/gpu/drm/vc4/vc4_bo.c drm_gem_object_put_unlocked(&bo->base.base); base 897 drivers/gpu/drm/vc4/vc4_bo.c if (copy_from_user(bo->base.vaddr, base 906 drivers/gpu/drm/vc4/vc4_bo.c memset(bo->base.vaddr + args->size, 0, base 907 drivers/gpu/drm/vc4/vc4_bo.c bo->base.base.size - args->size); base 909 drivers/gpu/drm/vc4/vc4_bo.c bo->validated_shader = vc4_validate_shader(&bo->base); base 918 drivers/gpu/drm/vc4/vc4_bo.c ret = drm_gem_handle_create(file_priv, &bo->base.base, &args->handle); base 921 drivers/gpu/drm/vc4/vc4_bo.c drm_gem_object_put_unlocked(&bo->base.base); base 48 drivers/gpu/drm/vc4/vc4_crtc.c struct drm_crtc_state base; base 587 drivers/gpu/drm/vc4/vc4_crtc.c crtc->base.id); base 783 drivers/gpu/drm/vc4/vc4_crtc.c struct drm_crtc *crtc = &vc4_crtc->base; base 812 drivers/gpu/drm/vc4/vc4_crtc.c drm_crtc_handle_vblank(&crtc->base); base 876 drivers/gpu/drm/vc4/vc4_crtc.c bo = to_vc4_bo(&cma_bo->base); base 903 drivers/gpu/drm/vc4/vc4_crtc.c struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); base 987 drivers/gpu/drm/vc4/vc4_crtc.c __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); base 988 drivers/gpu/drm/vc4/vc4_crtc.c return &vc4_state->base; base 1111 drivers/gpu/drm/vc4/vc4_crtc.c struct drm_device *drm = vc4_crtc->base.dev; base 1119 drivers/gpu/drm/vc4/vc4_crtc.c u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3; base 1121 drivers/gpu/drm/vc4/vc4_crtc.c vc4_crtc->cob_size = top - base + 4; base 1137 drivers/gpu/drm/vc4/vc4_crtc.c crtc = &vc4_crtc->base; base 1149 drivers/gpu/drm/vc4/vc4_crtc.c vc4_crtc->regset.base = vc4_crtc->regs; base 1247 drivers/gpu/drm/vc4/vc4_crtc.c vc4_crtc_destroy(&vc4_crtc->base); base 102 drivers/gpu/drm/vc4/vc4_dpi.c struct vc4_encoder base; base 109 drivers/gpu/drm/vc4/vc4_dpi.c return container_of(encoder, struct vc4_dpi_encoder, base.base); base 274 drivers/gpu/drm/vc4/vc4_dpi.c vc4_dpi_encoder->base.type = VC4_ENCODER_TYPE_DPI; base 276 drivers/gpu/drm/vc4/vc4_dpi.c dpi->encoder = &vc4_dpi_encoder->base.base; base 282 drivers/gpu/drm/vc4/vc4_dpi.c dpi->regset.base = dpi->regs; base 237 drivers/gpu/drm/vc4/vc4_drv.h struct drm_gem_cma_object base; base 290 drivers/gpu/drm/vc4/vc4_drv.h struct dma_fence base; base 334 drivers/gpu/drm/vc4/vc4_drv.h struct drm_plane base; base 350 drivers/gpu/drm/vc4/vc4_drv.h struct drm_plane_state base; base 430 drivers/gpu/drm/vc4/vc4_drv.h struct drm_encoder base; base 438 drivers/gpu/drm/vc4/vc4_drv.h return container_of(encoder, struct vc4_encoder, base); base 450 drivers/gpu/drm/vc4/vc4_drv.h struct drm_crtc base; base 593 drivers/gpu/drm/vc4/vc4_dsi.c struct vc4_encoder base; base 600 drivers/gpu/drm/vc4/vc4_dsi.c return container_of(encoder, struct vc4_dsi_encoder, base.base); base 1462 drivers/gpu/drm/vc4/vc4_dsi.c vc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1; base 1464 drivers/gpu/drm/vc4/vc4_dsi.c dsi->encoder = &vc4_dsi_encoder->base.base; base 1470 drivers/gpu/drm/vc4/vc4_dsi.c dsi->regset.base = dsi->regs; base 126 drivers/gpu/drm/vc4/vc4_gem.c bo_state[i].paddr = vc4_bo->base.paddr; base 127 drivers/gpu/drm/vc4/vc4_gem.c bo_state[i].size = vc4_bo->base.base.size; base 199 drivers/gpu/drm/vc4/vc4_gem.c bo = to_vc4_bo(&exec[i]->bo[j]->base); base 207 drivers/gpu/drm/vc4/vc4_gem.c drm_gem_object_get(&exec[i]->bo[j]->base); base 208 drivers/gpu/drm/vc4/vc4_gem.c kernel_state->bo[k++] = &exec[i]->bo[j]->base; base 215 drivers/gpu/drm/vc4/vc4_gem.c drm_gem_object_get(&bo->base.base); base 216 drivers/gpu/drm/vc4/vc4_gem.c kernel_state->bo[k++] = &bo->base.base; base 543 drivers/gpu/drm/vc4/vc4_gem.c bo = to_vc4_bo(&exec->bo[i]->base); base 546 drivers/gpu/drm/vc4/vc4_gem.c dma_resv_add_shared_fence(bo->base.base.resv, exec->fence); base 554 drivers/gpu/drm/vc4/vc4_gem.c bo = to_vc4_bo(&exec->rcl_write_bo[i]->base); base 557 drivers/gpu/drm/vc4/vc4_gem.c dma_resv_add_excl_fence(bo->base.base.resv, exec->fence); base 569 drivers/gpu/drm/vc4/vc4_gem.c struct drm_gem_object *bo = &exec->bo[i]->base; base 597 drivers/gpu/drm/vc4/vc4_gem.c bo = &exec->bo[contended_lock]->base; base 610 drivers/gpu/drm/vc4/vc4_gem.c bo = &exec->bo[i]->base; base 617 drivers/gpu/drm/vc4/vc4_gem.c bo = &exec->bo[j]->base; base 622 drivers/gpu/drm/vc4/vc4_gem.c bo = &exec->bo[contended_lock]->base; base 643 drivers/gpu/drm/vc4/vc4_gem.c bo = &exec->bo[i]->base; base 685 drivers/gpu/drm/vc4/vc4_gem.c dma_fence_init(&fence->base, &vc4_fence_ops, &vc4->job_lock, base 688 drivers/gpu/drm/vc4/vc4_gem.c exec->fence = &fence->base; base 789 drivers/gpu/drm/vc4/vc4_gem.c ret = vc4_bo_inc_usecnt(to_vc4_bo(&exec->bo[i]->base)); base 807 drivers/gpu/drm/vc4/vc4_gem.c vc4_bo_dec_usecnt(to_vc4_bo(&exec->bo[i]->base)); base 812 drivers/gpu/drm/vc4/vc4_gem.c drm_gem_object_put_unlocked(&exec->bo[i]->base); base 896 drivers/gpu/drm/vc4/vc4_gem.c exec->exec_bo = &bo->base; base 898 drivers/gpu/drm/vc4/vc4_gem.c list_add_tail(&to_vc4_bo(&exec->exec_bo->base)->unref_head, base 958 drivers/gpu/drm/vc4/vc4_gem.c struct vc4_bo *bo = to_vc4_bo(&exec->bo[i]->base); base 961 drivers/gpu/drm/vc4/vc4_gem.c drm_gem_object_put_unlocked(&exec->bo[i]->base); base 970 drivers/gpu/drm/vc4/vc4_gem.c drm_gem_object_put_unlocked(&bo->base.base); base 1305 drivers/gpu/drm/vc4/vc4_gem.c drm_gem_object_put_unlocked(&vc4->bin_bo->base.base); base 104 drivers/gpu/drm/vc4/vc4_hdmi.c struct vc4_encoder base; base 112 drivers/gpu/drm/vc4/vc4_hdmi.c return container_of(encoder, struct vc4_hdmi_encoder, base.base); base 117 drivers/gpu/drm/vc4/vc4_hdmi.c struct drm_connector base; base 129 drivers/gpu/drm/vc4/vc4_hdmi.c return container_of(connector, struct vc4_hdmi_connector, base); base 280 drivers/gpu/drm/vc4/vc4_hdmi.c connector = &hdmi_connector->base; base 1320 drivers/gpu/drm/vc4/vc4_hdmi.c vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; base 1321 drivers/gpu/drm/vc4/vc4_hdmi.c hdmi->encoder = &vc4_hdmi_encoder->base.base; base 1332 drivers/gpu/drm/vc4/vc4_hdmi.c hdmi->hdmi_regset.base = hdmi->hdmicore_regs; base 1335 drivers/gpu/drm/vc4/vc4_hdmi.c hdmi->hd_regset.base = hdmi->hd_regs; base 237 drivers/gpu/drm/vc4/vc4_hvs.c hvs->regset.base = hvs->regs; base 103 drivers/gpu/drm/vc4/vc4_irq.c V3D_WRITE(V3D_BPOA, bo->base.paddr + bin_bo_slot * vc4->bin_alloc_size); base 104 drivers/gpu/drm/vc4/vc4_irq.c V3D_WRITE(V3D_BPOS, bo->base.base.size); base 26 drivers/gpu/drm/vc4/vc4_kms.c struct drm_private_state base; base 33 drivers/gpu/drm/vc4/vc4_kms.c return container_of(priv, struct vc4_ctm_state, base); base 37 drivers/gpu/drm/vc4/vc4_kms.c struct drm_private_state base; base 45 drivers/gpu/drm/vc4/vc4_kms.c return container_of(priv, struct vc4_load_tracker_state, base); base 76 drivers/gpu/drm/vc4/vc4_kms.c __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); base 78 drivers/gpu/drm/vc4/vc4_kms.c return &state->base; base 469 drivers/gpu/drm/vc4/vc4_kms.c __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); base 471 drivers/gpu/drm/vc4/vc4_kms.c return &state->base; base 547 drivers/gpu/drm/vc4/vc4_kms.c drm_atomic_private_obj_init(dev, &vc4->ctm_manager, &ctm_state->base, base 556 drivers/gpu/drm/vc4/vc4_kms.c drm_atomic_private_obj_init(dev, &vc4->load_tracker, &load_state->base, base 159 drivers/gpu/drm/vc4/vc4_plane.c __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base); base 172 drivers/gpu/drm/vc4/vc4_plane.c return &vc4_state->base; base 190 drivers/gpu/drm/vc4/vc4_plane.c __drm_atomic_helper_plane_destroy_state(&vc4_state->base); base 205 drivers/gpu/drm/vc4/vc4_plane.c __drm_atomic_helper_plane_reset(plane, &vc4_state->base); base 985 drivers/gpu/drm/vc4/vc4_plane.c container_of(state, typeof(*vc4_state), base); base 1134 drivers/gpu/drm/vc4/vc4_plane.c bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base); base 1156 drivers/gpu/drm/vc4/vc4_plane.c bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base); base 1253 drivers/gpu/drm/vc4/vc4_plane.c plane = &vc4_plane->base; base 331 drivers/gpu/drm/vc4/vc4_render_cl.c setup->rcl = &vc4_bo_create(dev, size, true, VC4_BO_TYPE_RCL)->base; base 334 drivers/gpu/drm/vc4/vc4_render_cl.c list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head, base 390 drivers/gpu/drm/vc4/vc4_render_cl.c if (surf->offset > obj->base.size) { base 392 drivers/gpu/drm/vc4/vc4_render_cl.c surf->offset, obj->base.size); base 396 drivers/gpu/drm/vc4/vc4_render_cl.c if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE < base 401 drivers/gpu/drm/vc4/vc4_render_cl.c obj->base.size, base 163 drivers/gpu/drm/vc4/vc4_txp.c return container_of(conn, struct vc4_txp, connector.base); base 363 drivers/gpu/drm/vc4/vc4_txp.c vc4_crtc_handle_vblank(to_vc4_crtc(txp->connector.base.state->crtc)); base 390 drivers/gpu/drm/vc4/vc4_txp.c txp->regset.base = txp->regs; base 394 drivers/gpu/drm/vc4/vc4_txp.c drm_connector_helper_add(&txp->connector.base, base 423 drivers/gpu/drm/vc4/vc4_txp.c vc4_txp_connector_destroy(&txp->connector.base); base 264 drivers/gpu/drm/vc4/vc4_v3d.c if ((bo->base.paddr & 0xf0000000) == base 265 drivers/gpu/drm/vc4/vc4_v3d.c ((bo->base.paddr + bo->base.base.size - 1) & 0xf0000000)) { base 288 drivers/gpu/drm/vc4/vc4_v3d.c bo->base.base.size / vc4->bin_alloc_size); base 311 drivers/gpu/drm/vc4/vc4_v3d.c drm_gem_object_put_unlocked(&bo->base.base); base 347 drivers/gpu/drm/vc4/vc4_v3d.c drm_gem_object_put_unlocked(&vc4->bin_bo->base.base); base 410 drivers/gpu/drm/vc4/vc4_v3d.c v3d->regset.base = v3d->regs; base 117 drivers/gpu/drm/vc4/vc4_validate.c bo = to_vc4_bo(&obj->base); base 202 drivers/gpu/drm/vc4/vc4_validate.c size + offset > fbo->base.size) { base 206 drivers/gpu/drm/vc4/vc4_validate.c size, offset, fbo->base.size); base 280 drivers/gpu/drm/vc4/vc4_validate.c to_vc4_bo(&ib->base)->write_seqno); base 282 drivers/gpu/drm/vc4/vc4_validate.c if (offset > ib->base.size || base 283 drivers/gpu/drm/vc4/vc4_validate.c (ib->base.size - offset) / index_size < length) { base 285 drivers/gpu/drm/vc4/vc4_validate.c offset, length, index_size, ib->base.size); base 351 drivers/gpu/drm/vc4/vc4_validate.c struct drm_device *dev = exec->exec_bo->base.dev; base 395 drivers/gpu/drm/vc4/vc4_validate.c bin_addr = vc4->bin_bo->base.paddr + bin_slot * vc4->bin_alloc_size; base 588 drivers/gpu/drm/vc4/vc4_validate.c uint32_t remaining_size = tex->base.size - p0; base 590 drivers/gpu/drm/vc4/vc4_validate.c if (p0 > tex->base.size - 4) { base 731 drivers/gpu/drm/vc4/vc4_validate.c to_vc4_bo(&tex->base)->write_seqno); base 812 drivers/gpu/drm/vc4/vc4_validate.c to_vc4_bo(&bo[0]->base)->validated_shader->is_threaded) { base 817 drivers/gpu/drm/vc4/vc4_validate.c if (to_vc4_bo(&bo[1]->base)->validated_shader->is_threaded || base 818 drivers/gpu/drm/vc4/vc4_validate.c to_vc4_bo(&bo[2]->base)->validated_shader->is_threaded) { base 839 drivers/gpu/drm/vc4/vc4_validate.c validated_shader = to_vc4_bo(&bo[i]->base)->validated_shader; base 896 drivers/gpu/drm/vc4/vc4_validate.c to_vc4_bo(&vbo->base)->write_seqno); base 901 drivers/gpu/drm/vc4/vc4_validate.c if (vbo->base.size < offset || base 902 drivers/gpu/drm/vc4/vc4_validate.c vbo->base.size - offset < attr_size) { base 904 drivers/gpu/drm/vc4/vc4_validate.c offset, attr_size, vbo->base.size); base 909 drivers/gpu/drm/vc4/vc4_validate.c max_index = ((vbo->base.size - offset - attr_size) / base 790 drivers/gpu/drm/vc4/vc4_validate_shaders.c validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t); base 903 drivers/gpu/drm/vc4/vc4_validate_shaders.c shader_obj->base.size); base 177 drivers/gpu/drm/vc4/vc4_vec.c struct vc4_encoder base; base 184 drivers/gpu/drm/vc4/vc4_vec.c return container_of(encoder, struct vc4_vec_encoder, base.base); base 189 drivers/gpu/drm/vc4/vc4_vec.c struct drm_connector base; base 202 drivers/gpu/drm/vc4/vc4_vec.c return container_of(connector, struct vc4_vec_connector, base); base 357 drivers/gpu/drm/vc4/vc4_vec.c connector = &vec_connector->base; base 367 drivers/gpu/drm/vc4/vc4_vec.c drm_object_attach_property(&connector->base, base 547 drivers/gpu/drm/vc4/vc4_vec.c vc4_vec_encoder->base.type = VC4_ENCODER_TYPE_VEC; base 549 drivers/gpu/drm/vc4/vc4_vec.c vec->encoder = &vc4_vec_encoder->base.base; base 555 drivers/gpu/drm/vc4/vc4_vec.c vec->regset.base = vec->regs; base 82 drivers/gpu/drm/vgem/vgem_drv.c num_pages = DIV_ROUND_UP(obj->base.size, PAGE_SIZE); base 98 drivers/gpu/drm/vgem/vgem_drv.c file_inode(obj->base.filp)->i_mapping, base 169 drivers/gpu/drm/vgem/vgem_drv.c ret = drm_gem_object_init(dev, &obj->base, roundup(size, PAGE_SIZE)); base 182 drivers/gpu/drm/vgem/vgem_drv.c drm_gem_object_release(&obj->base); base 198 drivers/gpu/drm/vgem/vgem_drv.c ret = drm_gem_handle_create(file, &obj->base, handle); base 200 drivers/gpu/drm/vgem/vgem_drv.c drm_gem_object_put_unlocked(&obj->base); base 204 drivers/gpu/drm/vgem/vgem_drv.c return &obj->base; base 296 drivers/gpu/drm/vgem/vgem_drv.c pages = drm_gem_get_pages(&bo->base); base 314 drivers/gpu/drm/vgem/vgem_drv.c drm_gem_put_pages(&bo->base, bo->pages, true, true); base 349 drivers/gpu/drm/vgem/vgem_drv.c return drm_prime_pages_to_sg(bo->pages, bo->base.size >> PAGE_SHIFT); base 382 drivers/gpu/drm/vgem/vgem_drv.c return &obj->base; base 42 drivers/gpu/drm/vgem/vgem_drv.h #define to_vgem_bo(x) container_of(x, struct drm_vgem_gem_object, base) base 44 drivers/gpu/drm/vgem/vgem_drv.h struct drm_gem_object base; base 33 drivers/gpu/drm/vgem/vgem_fence.c struct dma_fence base; base 48 drivers/gpu/drm/vgem/vgem_fence.c static void vgem_fence_release(struct dma_fence *base) base 50 drivers/gpu/drm/vgem/vgem_fence.c struct vgem_fence *fence = container_of(base, typeof(*fence), base); base 53 drivers/gpu/drm/vgem/vgem_fence.c dma_fence_free(&fence->base); base 81 drivers/gpu/drm/vgem/vgem_fence.c dma_fence_signal(&fence->base); base 94 drivers/gpu/drm/vgem/vgem_fence.c dma_fence_init(&fence->base, &vgem_fence_ops, &fence->lock, base 102 drivers/gpu/drm/vgem/vgem_fence.c return &fence->base; base 194 drivers/gpu/drm/via/via_dma.c if (!dev->agp || !dev->agp->base) { base 204 drivers/gpu/drm/via/via_dma.c dev_priv->ring.map.offset = dev->agp->base + init->offset; base 70 drivers/gpu/drm/virtio/virtgpu_display.c vgfb->base.obj[0] = obj; base 72 drivers/gpu/drm/virtio/virtgpu_display.c drm_helper_mode_fill_fb_struct(dev, &vgfb->base, mode_cmd); base 74 drivers/gpu/drm/virtio/virtgpu_display.c ret = drm_framebuffer_init(dev, &vgfb->base, &virtio_gpu_fb_funcs); base 76 drivers/gpu/drm/virtio/virtgpu_display.c vgfb->base.obj[0] = NULL; base 321 drivers/gpu/drm/virtio/virtgpu_display.c return &virtio_gpu_fb->base; base 144 drivers/gpu/drm/virtio/virtgpu_drv.h struct drm_framebuffer base; base 148 drivers/gpu/drm/virtio/virtgpu_drv.h container_of(x, struct virtio_gpu_framebuffer, base) base 399 drivers/gpu/drm/virtio/virtgpu_drv.h return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); base 399 drivers/gpu/drm/virtio/virtgpu_ioctl.c dma_resv_add_excl_fence(qobj->tbo.base.resv, base 453 drivers/gpu/drm/virtio/virtgpu_ioctl.c dma_resv_add_excl_fence(qobj->tbo.base.resv, base 109 drivers/gpu/drm/virtio/virtgpu_plane.c bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]); base 155 drivers/gpu/drm/virtio/virtgpu_plane.c bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]); base 200 drivers/gpu/drm/virtio/virtgpu_plane.c bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]); base 215 drivers/gpu/drm/virtio/virtgpu_plane.c dma_resv_add_excl_fence(bo->tbo.base.resv, base 167 drivers/gpu/drm/virtio/virtgpu_ttm.c mem->bus.base = 0; base 156 drivers/gpu/drm/vkms/vkms_composer.c struct drm_crtc *crtc = crtc_state->base.crtc; base 117 drivers/gpu/drm/vkms/vkms_crtc.c __drm_atomic_helper_crtc_duplicate_state(crtc, &vkms_state->base); base 121 drivers/gpu/drm/vkms/vkms_crtc.c return &vkms_state->base; base 144 drivers/gpu/drm/vkms/vkms_crtc.c __drm_atomic_helper_crtc_reset(crtc, &vkms_state->base); base 37 drivers/gpu/drm/vkms/vkms_drv.h struct drm_plane_state base; base 49 drivers/gpu/drm/vkms/vkms_drv.h struct drm_crtc_state base; base 105 drivers/gpu/drm/vkms/vkms_drv.h container_of(target, struct vkms_crtc_state, base) base 108 drivers/gpu/drm/vkms/vkms_drv.h container_of(target, struct vkms_plane_state, base) base 39 drivers/gpu/drm/vkms/vkms_plane.c &vkms_state->base); base 41 drivers/gpu/drm/vkms/vkms_plane.c return &vkms_state->base; base 48 drivers/gpu/drm/vkms/vkms_plane.c struct drm_crtc *crtc = vkms_state->base.crtc; base 78 drivers/gpu/drm/vkms/vkms_plane.c plane->state = &vkms_state->base; base 1347 drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h PPN64 base; base 1602 drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h PPN base; base 1631 drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h PPN64 base; base 1646 drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h PPN64 base; base 1608 drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h uint8 base; /* SVGA3dFogBase */ base 69 drivers/gpu/drm/vmwgfx/ttm_lock.h struct ttm_base_object base; base 159 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base, base 169 drivers/gpu/drm/vmwgfx/ttm_object.c base->shareable = shareable; base 170 drivers/gpu/drm/vmwgfx/ttm_object.c base->tfile = ttm_object_file_ref(tfile); base 171 drivers/gpu/drm/vmwgfx/ttm_object.c base->refcount_release = refcount_release; base 172 drivers/gpu/drm/vmwgfx/ttm_object.c base->ref_obj_release = ref_obj_release; base 173 drivers/gpu/drm/vmwgfx/ttm_object.c base->object_type = object_type; base 174 drivers/gpu/drm/vmwgfx/ttm_object.c kref_init(&base->refcount); base 177 drivers/gpu/drm/vmwgfx/ttm_object.c ret = idr_alloc(&tdev->idr, base, 1, 0, GFP_NOWAIT); base 183 drivers/gpu/drm/vmwgfx/ttm_object.c base->handle = ret; base 184 drivers/gpu/drm/vmwgfx/ttm_object.c ret = ttm_ref_object_add(tfile, base, TTM_REF_USAGE, NULL, false); base 188 drivers/gpu/drm/vmwgfx/ttm_object.c ttm_base_object_unref(&base); base 193 drivers/gpu/drm/vmwgfx/ttm_object.c idr_remove(&tdev->idr, base->handle); base 200 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base = base 202 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_object_device *tdev = base->tfile->tdev; base 205 drivers/gpu/drm/vmwgfx/ttm_object.c idr_remove(&tdev->idr, base->handle); base 214 drivers/gpu/drm/vmwgfx/ttm_object.c ttm_object_file_unref(&base->tfile); base 215 drivers/gpu/drm/vmwgfx/ttm_object.c if (base->refcount_release) base 216 drivers/gpu/drm/vmwgfx/ttm_object.c base->refcount_release(&base); base 221 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base = *p_base; base 225 drivers/gpu/drm/vmwgfx/ttm_object.c kref_put(&base->refcount, ttm_release_base); base 266 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base = NULL; base 275 drivers/gpu/drm/vmwgfx/ttm_object.c base = drm_hash_entry(hash, struct ttm_ref_object, hash)->obj; base 276 drivers/gpu/drm/vmwgfx/ttm_object.c if (!kref_get_unless_zero(&base->refcount)) base 277 drivers/gpu/drm/vmwgfx/ttm_object.c base = NULL; base 281 drivers/gpu/drm/vmwgfx/ttm_object.c return base; base 287 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base; base 290 drivers/gpu/drm/vmwgfx/ttm_object.c base = idr_find(&tdev->idr, key); base 292 drivers/gpu/drm/vmwgfx/ttm_object.c if (base && !kref_get_unless_zero(&base->refcount)) base 293 drivers/gpu/drm/vmwgfx/ttm_object.c base = NULL; base 296 drivers/gpu/drm/vmwgfx/ttm_object.c return base; base 310 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base) base 317 drivers/gpu/drm/vmwgfx/ttm_object.c if (unlikely(drm_ht_find_item_rcu(ht, base->handle, &hash) != 0)) base 326 drivers/gpu/drm/vmwgfx/ttm_object.c if (unlikely(base != ref->obj)) base 345 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base, base 359 drivers/gpu/drm/vmwgfx/ttm_object.c if (base->tfile != tfile && !base->shareable) base 367 drivers/gpu/drm/vmwgfx/ttm_object.c ret = drm_ht_find_item_rcu(ht, base->handle, &hash); base 391 drivers/gpu/drm/vmwgfx/ttm_object.c ref->hash.key = base->handle; base 392 drivers/gpu/drm/vmwgfx/ttm_object.c ref->obj = base; base 402 drivers/gpu/drm/vmwgfx/ttm_object.c kref_get(&base->refcount); base 424 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base = ref->obj; base 434 drivers/gpu/drm/vmwgfx/ttm_object.c if (ref->ref_type != TTM_REF_USAGE && base->ref_obj_release) base 435 drivers/gpu/drm/vmwgfx/ttm_object.c base->ref_obj_release(base, ref->ref_type); base 599 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base = *p_base; base 603 drivers/gpu/drm/vmwgfx/ttm_object.c prime = container_of(base, struct ttm_prime_object, base); base 607 drivers/gpu/drm/vmwgfx/ttm_object.c prime->refcount_release(&base); base 624 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base = &prime->base; base 625 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_object_device *tdev = base->tfile->tdev; base 634 drivers/gpu/drm/vmwgfx/ttm_object.c ttm_base_object_unref(&base); base 654 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base; base 665 drivers/gpu/drm/vmwgfx/ttm_object.c base = &prime->base; base 666 drivers/gpu/drm/vmwgfx/ttm_object.c *handle = base->handle; base 667 drivers/gpu/drm/vmwgfx/ttm_object.c ret = ttm_ref_object_add(tfile, base, TTM_REF_USAGE, NULL, false); base 688 drivers/gpu/drm/vmwgfx/ttm_object.c struct ttm_base_object *base; base 693 drivers/gpu/drm/vmwgfx/ttm_object.c base = ttm_base_object_lookup(tfile, handle); base 694 drivers/gpu/drm/vmwgfx/ttm_object.c if (unlikely(base == NULL || base 695 drivers/gpu/drm/vmwgfx/ttm_object.c base->object_type != ttm_prime_type)) { base 700 drivers/gpu/drm/vmwgfx/ttm_object.c prime = container_of(base, struct ttm_prime_object, base); base 701 drivers/gpu/drm/vmwgfx/ttm_object.c if (unlikely(!base->shareable)) { base 746 drivers/gpu/drm/vmwgfx/ttm_object.c base = NULL; base 759 drivers/gpu/drm/vmwgfx/ttm_object.c if (base) base 760 drivers/gpu/drm/vmwgfx/ttm_object.c ttm_base_object_unref(&base); base 790 drivers/gpu/drm/vmwgfx/ttm_object.c return ttm_base_object_init(tfile, &prime->base, shareable, base 130 drivers/gpu/drm/vmwgfx/ttm_object.h void (*refcount_release) (struct ttm_base_object **base); base 131 drivers/gpu/drm/vmwgfx/ttm_object.h void (*ref_obj_release) (struct ttm_base_object *base, base 154 drivers/gpu/drm/vmwgfx/ttm_object.h struct ttm_base_object base; base 177 drivers/gpu/drm/vmwgfx/ttm_object.h struct ttm_base_object *base, base 248 drivers/gpu/drm/vmwgfx/ttm_object.h struct ttm_base_object *base, base 253 drivers/gpu/drm/vmwgfx/ttm_object.h struct ttm_base_object *base); base 340 drivers/gpu/drm/vmwgfx/ttm_object.h ttm_base_object_type(struct ttm_base_object *base) base 342 drivers/gpu/drm/vmwgfx/ttm_object.h return (base->object_type == ttm_prime_type) ? base 343 drivers/gpu/drm/vmwgfx/ttm_object.h container_of(base, struct ttm_prime_object, base)->real_type : base 344 drivers/gpu/drm/vmwgfx/ttm_object.h base->object_type; base 353 drivers/gpu/drm/vmwgfx/ttm_object.h kfree_rcu(__obj, __prime.base.rhead) base 462 drivers/gpu/drm/vmwgfx/vmwgfx_blit.c dma_resv_assert_held(dst->base.resv); base 464 drivers/gpu/drm/vmwgfx/vmwgfx_blit.c dma_resv_assert_held(src->base.resv); base 58 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c return container_of(bo, struct vmw_buffer_object, base); base 95 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct ttm_buffer_object *bo = &buf->base; base 144 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct ttm_buffer_object *bo = &buf->base; base 219 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct ttm_buffer_object *bo = &buf->base; base 288 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct ttm_buffer_object *bo = &buf->base; base 340 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct ttm_buffer_object *bo = &vbo->base; base 344 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c dma_resv_assert_held(bo->base.resv); base 389 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct ttm_buffer_object *bo = &vbo->base; base 513 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c vmw_bo->base.priority = 3; base 517 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ret = ttm_bo_init(bdev, &vmw_bo->base, size, base 537 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct ttm_base_object *base = *p_base; base 541 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c if (unlikely(base == NULL)) base 544 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c vmw_user_bo = container_of(base, struct vmw_user_buffer_object, base 545 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c prime.base); base 546 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_bo_put(&vmw_user_bo->vbo.base); base 560 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c static void vmw_user_bo_ref_obj_release(struct ttm_base_object *base, base 565 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c user_bo = container_of(base, struct vmw_user_buffer_object, prime.base); base 569 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_bo_synccpu_write_release(&user_bo->vbo.base); base 615 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_bo_get(&user_bo->vbo.base); base 624 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_bo_put(&user_bo->vbo.base); base 630 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c *p_base = &user_bo->prime.base; base 633 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c *handle = user_bo->prime.base.handle; base 658 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c if (likely(ttm_ref_object_exists(tfile, &vmw_user_bo->prime.base))) base 685 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct ttm_buffer_object *bo = &user_bo->vbo.base; base 694 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c (bo->base.resv, true, true, base 708 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ret = ttm_ref_object_add(tfile, &user_bo->prime.base, base 711 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_bo_synccpu_write_release(&user_bo->vbo.base); base 839 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c rep->map_handle = drm_vma_node_offset_addr(&vbo->base.base.vma_node); base 894 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct ttm_base_object *base; base 896 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c base = ttm_base_object_lookup(tfile, handle); base 897 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c if (unlikely(base == NULL)) { base 903 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c if (unlikely(ttm_base_object_type(base) != ttm_buffer_type)) { base 904 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_base_object_unref(&base); base 910 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c vmw_user_bo = container_of(base, struct vmw_user_buffer_object, base 911 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c prime.base); base 912 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_bo_get(&vmw_user_bo->vbo.base); base 914 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c *p_base = base; base 916 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c ttm_base_object_unref(&base); base 943 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c struct ttm_base_object *base; base 945 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c base = ttm_base_object_noref_lookup(tfile, handle); base 946 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c if (!base) { base 952 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c if (unlikely(ttm_base_object_type(base) != ttm_buffer_type)) { base 959 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c vmw_user_bo = container_of(base, struct vmw_user_buffer_object, base 960 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c prime.base); base 978 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c if (vbo->base.destroy != vmw_user_bo_destroy) base 983 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c *handle = user_bo->prime.base.handle; base 984 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c return ttm_ref_object_add(tfile, &user_bo->prime.base, base 1011 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c dma_resv_add_excl_fence(bo->base.resv, &fence->base); base 1012 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c dma_fence_put(&fence->base); base 1014 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c dma_resv_add_excl_fence(bo->base.resv, &fence->base); base 1081 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c *offset = drm_vma_node_offset_addr(&out_buf->base.base.vma_node); base 1146 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c vbo = container_of(bo, struct vmw_buffer_object, base); base 35 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct ttm_base_object base; base 46 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_user_context_base_to_res(struct ttm_base_object *base); base 673 drivers/gpu/drm/vmwgfx/vmwgfx_context.c vmw_user_context_base_to_res(struct ttm_base_object *base) base 675 drivers/gpu/drm/vmwgfx/vmwgfx_context.c return &(container_of(base, struct vmw_user_context, base)->res); base 689 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ttm_base_object_kfree(ctx, base); base 701 drivers/gpu/drm/vmwgfx/vmwgfx_context.c struct ttm_base_object *base = *p_base; base 703 drivers/gpu/drm/vmwgfx/vmwgfx_context.c container_of(base, struct vmw_user_context, base); base 767 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ctx->base.shareable = false; base 768 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ctx->base.tfile = NULL; base 779 drivers/gpu/drm/vmwgfx/vmwgfx_context.c ret = ttm_base_object_init(tfile, &ctx->base, false, VMW_RES_CONTEXT, base 787 drivers/gpu/drm/vmwgfx/vmwgfx_context.c arg->cid = ctx->base.handle; base 167 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c struct ttm_buffer_object *bo = &res->backup->base; base 174 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c dma_resv_assert_held(bo->base.resv); base 215 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c val_buf->bo = &res->backup->base; base 316 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c dma_resv_assert_held(bo->base.resv); base 363 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c vmw_bo_fence_single(&res->backup->base, fence); base 387 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c struct ttm_buffer_object *bo, *old_bo = &res->backup->base; base 418 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c bo = &buf->base; base 371 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = ttm_bo_reserve(&vbo->base, false, true, NULL); base 375 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); base 384 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ttm_bo_unreserve(&vbo->base); base 110 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h struct ttm_buffer_object base; base 130 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h struct ttm_validate_buffer base; base 788 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h struct ttm_base_object **base); base 819 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h vbo->base.priority = i; base 824 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h vbo->base.priority = 3; base 1439 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h ttm_bo_put(&tmp_buf->base); base 1446 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h ttm_bo_get(&buf->base); base 730 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c cmd->body.mobid = dx_query_mob->base.mem.start; base 1041 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c if (unlikely(new_query_bo->base.num_pages > 4)) { base 1540 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c bo_size = vmw_bo->base.num_pages * PAGE_SIZE; base 1563 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c vmw_kms_cursor_snoop(srf, sw_context->fp->tfile, &vmw_bo->base, header); base 3305 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c bo = &reloc->vbo->base; base 3436 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c fence_rep.seqno = fence->base.seqno; base 3801 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c sync_file = sync_file_create(&fence->base); base 199 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c (void) ttm_bo_reserve(&vbo->base, false, false, NULL); base 256 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c ttm_bo_unreserve(&vbo->base); base 551 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c par->set_fb = &vfb->base; base 739 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c info->apertures->ranges[0].base = vmw_priv->vram_start; base 54 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct ttm_base_object base; base 87 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c return container_of(fence->base.lock, struct vmw_fence_manager, lock); base 115 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c container_of(f, struct vmw_fence_obj, base); base 139 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c container_of(f, struct vmw_fence_obj, base); base 146 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c if (seqno - fence->base.seqno < VMW_FENCE_WRAP) base 155 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct dma_fence_cb base; base 163 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c container_of(cb, struct vmwgfx_wait_cb, base); base 173 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c container_of(f, struct vmw_fence_obj, base); base 196 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c cb.base.func = vmwgfx_wait_cb; base 198 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c list_add(&cb.base.node, &f->cb_list); base 234 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c if (!list_empty(&cb.base.node)) base 235 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c list_del(&cb.base.node); base 345 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c dma_fence_init(&fence->base, &vmw_fence_ops, &fman->lock, base 419 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c vmw_mmio_write(fence->base.seqno, base 450 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c if (dma_fence_is_signaled_locked(&fence->base)) base 456 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c goal_seqno - fence->base.seqno < VMW_FENCE_WRAP)) base 459 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c vmw_mmio_write(fence->base.seqno, fifo_mem + SVGA_FIFO_FENCE_GOAL); base 476 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c if (seqno - fence->base.seqno < VMW_FENCE_WRAP) { base 478 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c dma_fence_signal_locked(&fence->base); base 517 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->base.flags)) base 522 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c return dma_fence_is_signaled(&fence->base); base 528 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c long ret = dma_fence_wait_timeout(&fence->base, interruptible, timeout); base 547 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c dma_fence_free(&fence->base); base 581 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c ttm_base_object_kfree(ufence, base); base 591 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct ttm_base_object *base = *p_base; base 593 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c container_of(base, struct vmw_user_fence, base); base 644 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c ret = ttm_base_object_init(tfile, &ufence->base, false, base 658 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c *p_handle = ufence->base.handle; base 735 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c dma_fence_get(&fence->base); base 743 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c dma_fence_signal(&fence->base); base 751 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c dma_fence_put(&fence->base); base 781 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct ttm_base_object *base = ttm_base_object_lookup(tfile, handle); base 783 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c if (!base) { base 789 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c if (base->refcount_release != vmw_user_fence_base_release) { base 792 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c ttm_base_object_unref(&base); base 796 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c return base; base 806 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct ttm_base_object *base; base 825 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c base = vmw_fence_obj_lookup(tfile, arg->handle); base 826 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c if (IS_ERR(base)) base 827 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c return PTR_ERR(base); base 829 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c fence = &(container_of(base, struct vmw_user_fence, base)->fence); base 843 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c ttm_base_object_unref(&base); base 860 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct ttm_base_object *base; base 866 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c base = vmw_fence_obj_lookup(tfile, arg->handle); base 867 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c if (IS_ERR(base)) base 868 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c return PTR_ERR(base); base 870 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c fence = &(container_of(base, struct vmw_user_fence, base)->fence); base 880 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c ttm_base_object_unref(&base); base 971 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c if (dma_fence_is_signaled_locked(&fence->base)) { base 1046 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct drm_pending_event base; base 1068 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c event->event.base.type = DRM_VMW_EVENT_FENCE_SIGNALED; base 1069 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c event->event.base.length = sizeof(*event); base 1072 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c ret = drm_event_reserve_init(dev, file_priv, &event->base, &event->event.base); base 1082 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c &event->base, base 1088 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c &event->base, base 1098 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c drm_event_cancel_free(dev, &event->base); base 1124 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c struct ttm_base_object *base = base 1127 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c if (IS_ERR(base)) base 1128 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c return PTR_ERR(base); base 1130 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c fence = &(container_of(base, struct vmw_user_fence, base 1131 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c base)->fence); base 1135 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c ret = ttm_ref_object_add(vmw_fp->tfile, base, base 1142 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c handle = base->handle; base 1144 drivers/gpu/drm/vmwgfx/vmwgfx_fence.c ttm_base_object_unref(&base); base 59 drivers/gpu/drm/vmwgfx/vmwgfx_fence.h struct dma_fence base; base 78 drivers/gpu/drm/vmwgfx/vmwgfx_fence.h dma_fence_put(&fence->base); base 85 drivers/gpu/drm/vmwgfx/vmwgfx_fence.h dma_fence_get(&fence->base); base 598 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; base 644 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base; base 106 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = ttm_bo_reserve(&bo->base, true, false, NULL); base 112 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = ttm_bo_kmap(&bo->base, kmap_offset, kmap_num, &map); base 122 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ttm_bo_unreserve(&bo->base); base 598 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c state = &vcs->base; base 632 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c crtc->state = &vcs->base; base 683 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c state = &vps->base; base 713 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c __drm_atomic_helper_plane_reset(plane, &vps->base); base 766 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c state = &vcs->base; base 800 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c __drm_atomic_helper_connector_reset(connector, &vcs->base); base 833 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (vfbs->base.user_obj) base 834 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ttm_base_object_unref(&vfbs->base.user_obj); base 955 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_helper_mode_fill_fb_struct(dev, &vfbs->base.base, mode_cmd); base 957 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vfbs->base.user_handle = mode_cmd->handles[0]; base 960 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c *out = &vfbs->base; base 962 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = drm_framebuffer_init(dev, &vfbs->base.base, base 987 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (vfbd->base.user_obj) base 988 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ttm_base_object_unref(&vfbd->base.user_obj); base 1026 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = vmw_kms_ldu_do_bo_dirty(dev_priv, &vfbd->base, 0, 0, base 1070 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(vfb->base.dev); base 1075 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c buf = vfb->bo ? vmw_framebuffer_to_vfbd(&vfb->base)->buffer : base 1076 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_framebuffer_to_vfbs(&vfb->base)->surface->res.backup; base 1115 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_private *dev_priv = vmw_priv(vfb->base.dev); base 1118 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c buf = vfb->bo ? vmw_framebuffer_to_vfbd(&vfb->base)->buffer : base 1119 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vmw_framebuffer_to_vfbs(&vfb->base)->surface->res.backup; base 1229 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (unlikely(requested_size > bo->base.num_pages * PAGE_SIZE)) { base 1257 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c drm_helper_mode_fill_fb_struct(dev, &vfbd->base.base, mode_cmd); base 1258 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vfbd->base.bo = true; base 1260 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c vfbd->base.user_handle = mode_cmd->handles[0]; base 1261 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c *out = &vfbd->base; base 1263 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c ret = drm_framebuffer_init(dev, &vfbd->base.base, base 1438 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c return &vfb->base; base 1531 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c lockdep_assert_held(&crtc->mutex.mutex.base); base 2070 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c (&con->base, dev->mode_config.suggested_x_property, base 2073 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c (&con->base, dev->mode_config.suggested_y_property, base 2077 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c (&con->base, dev->mode_config.suggested_x_property, base 2080 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c (&con->base, dev->mode_config.suggested_y_property, base 2462 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c if (plane->state->fb == &framebuffer->base) base 2823 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c container_of(update->vfb, typeof(*vfbbo), base); base 2829 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c container_of(update->vfb, typeof(*vfbs), base); base 138 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct vmw_du_update_plane base; base 150 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct vmw_du_update_plane base; base 205 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h container_of(x, struct vmw_framebuffer, base) base 207 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h container_of(x, struct vmw_framebuffer_surface, base.base) base 209 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h container_of(x, struct vmw_framebuffer_bo, base.base) base 218 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct drm_framebuffer base; base 234 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct vmw_framebuffer base; base 243 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct vmw_framebuffer base; base 261 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h #define vmw_crtc_state_to_vcs(x) container_of(x, struct vmw_crtc_state, base) base 262 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h #define vmw_plane_state_to_vps(x) container_of(x, struct vmw_plane_state, base) base 264 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h container_of(x, struct vmw_connector_state, base) base 272 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct drm_crtc_state base; base 286 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct drm_plane_state base; base 308 drivers/gpu/drm/vmwgfx/vmwgfx_kms.h struct drm_connector_state base; base 37 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c container_of(x, struct vmw_legacy_display_unit, base.crtc) base 39 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c container_of(x, struct vmw_legacy_display_unit, base.encoder) base 41 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c container_of(x, struct vmw_legacy_display_unit, base.connector) base 56 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c struct vmw_display_unit base; base 64 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c vmw_du_cleanup(&ldu->base); base 92 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c crtc = &entry->base.crtc; base 100 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c fb = entry->base.crtc.primary->state->fb; base 109 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c fb = entry->base.crtc.primary->state->fb; base 121 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c crtc = &entry->base.crtc; base 183 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c if (entry->base.unit > ldu->base.unit) base 367 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c ldu->base.unit = unit; base 368 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c crtc = &ldu->base.crtc; base 369 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c encoder = &ldu->base.encoder; base 370 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c connector = &ldu->base.connector; base 371 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c primary = &ldu->base.primary; base 372 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c cursor = &ldu->base.cursor; base 376 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c ldu->base.pref_active = (unit == 0); base 377 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c ldu->base.pref_width = dev_priv->initial_width; base 378 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c ldu->base.pref_height = dev_priv->initial_height; base 379 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c ldu->base.pref_mode = NULL; base 385 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c ldu->base.is_implicit = true; base 390 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c ret = drm_universal_plane_init(dev, &ldu->base.primary, base 405 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c ret = drm_universal_plane_init(dev, &ldu->base.cursor, base 412 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c drm_plane_cleanup(&ldu->base.primary); base 447 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c ret = drm_crtc_init_with_planes(dev, crtc, &ldu->base.primary, base 448 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c &ldu->base.cursor, base 459 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c drm_object_attach_property(&connector->base, base 461 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c drm_object_attach_property(&connector->base, base 463 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c drm_object_attach_property(&connector->base, base 467 drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c (&connector->base, base 690 drivers/gpu/drm/vmwgfx/vmwgfx_mob.c cmd->body.base = mob->pt_root_page >> PAGE_SHIFT; base 143 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c vmw_bo_get_guest_ptr(&buf->base, &ptr); base 44 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c dma_resv_assert_held(res->backup->base.base.resv); base 59 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c dma_resv_assert_held(backup->base.base.resv); base 109 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct ttm_buffer_object *bo = &res->backup->base; base 240 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct ttm_base_object *base; base 244 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c base = ttm_base_object_lookup(tfile, handle); base 245 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c if (unlikely(base == NULL)) base 248 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c if (unlikely(ttm_base_object_type(base) != converter->object_type)) base 251 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c res = converter->base_obj_to_res(base); base 258 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ttm_base_object_unref(&base); base 284 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c struct ttm_base_object *base; base 286 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c base = ttm_base_object_noref_lookup(tfile, handle); base 287 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c if (!base) base 290 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c if (unlikely(ttm_base_object_type(base) != converter->object_type)) { base 295 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c return converter->base_obj_to_res(base); base 343 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c BUG_ON(res->backup->base.num_pages * PAGE_SIZE < size); base 491 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ttm_bo_get(&res->backup->base); base 492 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c val_buf->bo = &res->backup->base; base 504 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ret = ttm_bo_validate(&res->backup->base, base 650 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c val_buf.bo = &res->backup->base; base 718 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c .bo = &vbo->base, base 722 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c dma_resv_assert_held(vbo->base.base.resv); base 733 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c (void) ttm_bo_wait(&vbo->base, false, false); base 801 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c dx_query_mob = container_of(bo, struct vmw_buffer_object, base); base 936 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ttm_bo_reserve(&vbo->base, interruptible, false, NULL); base 939 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c (&vbo->base, base 943 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ttm_bo_unreserve(&vbo->base); base 953 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ttm_bo_unreserve(&vbo->base); base 991 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c (void) ttm_bo_reserve(&vbo->base, false, false, NULL); base 993 drivers/gpu/drm/vmwgfx/vmwgfx_resource.c ttm_bo_unreserve(&vbo->base); base 53 drivers/gpu/drm/vmwgfx/vmwgfx_resource_priv.h struct vmw_resource *(*base_obj_to_res)(struct ttm_base_object *base); base 38 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c container_of(x, struct vmw_screen_object_unit, base.crtc) base 40 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c container_of(x, struct vmw_screen_object_unit, base.encoder) base 42 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c container_of(x, struct vmw_screen_object_unit, base.connector) base 57 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c struct vmw_kms_dirty base; base 91 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c struct vmw_display_unit base; base 101 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_du_cleanup(&sou->base); base 142 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c cmd->obj.id = sou->base.unit; base 144 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c (sou->base.unit == 0 ? SVGA_SCREEN_IS_PRIMARY : 0); base 149 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sou->base.set_gui_x = cmd->obj.root.x; base 150 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sou->base.set_gui_y = cmd->obj.root.y; base 153 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_bo_get_guest_ptr(&sou->buffer->base, &cmd->obj.backingStore.ptr); base 190 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c cmd->body.screenId = sou->base.unit; base 246 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c conn_state = sou->base.connector.state; base 479 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c container_of(update->vfb, typeof(*vfbbo), base); base 481 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c int depth = update->vfb->base.format->depth; base 492 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c gmr->body.format.bitsPerPixel = update->vfb->base.format->cpp[0] * 8; base 495 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c gmr->body.bytesPerLine = update->vfb->base.pitches[0]; base 496 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_bo_get_guest_ptr(&vfbbo->buffer->base, &gmr->body.ptr); base 546 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.plane = plane; base 547 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.old_state = old_state; base 548 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.dev_priv = dev_priv; base 549 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.du = vmw_crtc_to_du(plane->state->crtc); base 550 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.vfb = vfb; base 551 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.out_fence = out_fence; base 552 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.mutex = NULL; base 553 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.cpu_blit = false; base 554 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.intr = true; base 556 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.calc_fifo_size = vmw_sou_bo_fifo_size; base 557 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.post_prepare = vmw_sou_bo_define_gmrfb; base 558 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.clip = vmw_sou_bo_populate_clip; base 559 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c bo_update.base.post_clip = vmw_stud_bo_post_clip; base 561 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c return vmw_du_helper_plane_update(&bo_update.base); base 576 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update = container_of(update, typeof(*srf_update), base); base 594 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vfbs = container_of(update->vfb, typeof(*vfbs), base); base 648 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update = container_of(update, typeof(*srf_update), base); base 707 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.plane = plane; base 708 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.old_state = old_state; base 709 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.dev_priv = dev_priv; base 710 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.du = vmw_crtc_to_du(plane->state->crtc); base 711 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.vfb = vfb; base 712 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.out_fence = out_fence; base 713 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.mutex = &dev_priv->cmdbuf_mutex; base 714 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.cpu_blit = false; base 715 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.intr = true; base 717 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.calc_fifo_size = vmw_sou_surface_fifo_size; base 718 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.post_prepare = vmw_sou_surface_post_prepare; base 719 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.pre_clip = vmw_sou_surface_pre_clip; base 720 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.clip = vmw_sou_surface_clip_rect; base 721 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c srf_update.base.post_clip = vmw_sou_surface_post_clip; base 723 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c return vmw_du_helper_plane_update(&srf_update.base); base 758 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c struct drm_file *file_priv = event->base.file_priv; base 762 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c &event->base, base 840 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sou->base.unit = unit; base 841 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c crtc = &sou->base.crtc; base 842 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c encoder = &sou->base.encoder; base 843 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c connector = &sou->base.connector; base 844 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c primary = &sou->base.primary; base 845 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c cursor = &sou->base.cursor; base 847 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sou->base.pref_active = (unit == 0); base 848 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sou->base.pref_width = dev_priv->initial_width; base 849 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sou->base.pref_height = dev_priv->initial_height; base 850 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sou->base.pref_mode = NULL; base 856 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sou->base.is_implicit = false; base 861 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = drm_universal_plane_init(dev, &sou->base.primary, base 877 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = drm_universal_plane_init(dev, &sou->base.cursor, base 884 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c drm_plane_cleanup(&sou->base.primary); base 920 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c ret = drm_crtc_init_with_planes(dev, crtc, &sou->base.primary, base 921 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c &sou->base.cursor, base 932 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c drm_object_attach_property(&connector->base, base 934 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c drm_object_attach_property(&connector->base, base 936 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c drm_object_attach_property(&connector->base, base 983 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c base)->buffer; base 984 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c int depth = framebuffer->base.format->depth; base 1002 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c cmd->body.format.bitsPerPixel = framebuffer->base.format->cpp[0] * 8; base 1005 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c cmd->body.bytesPerLine = framebuffer->base.pitches[0]; base 1007 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c vmw_bo_get_guest_ptr(&buf->base, &cmd->body.ptr); base 1025 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c container_of(dirty, typeof(*sdirty), base); base 1083 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c container_of(dirty, typeof(*sdirty), base); base 1137 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c container_of(framebuffer, typeof(*vfbs), base); base 1154 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sdirty.base.fifo_commit = vmw_sou_surface_fifo_commit; base 1155 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sdirty.base.clip = vmw_sou_surface_clip; base 1156 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sdirty.base.dev_priv = dev_priv; base 1157 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sdirty.base.fifo_reserve_size = sizeof(struct vmw_kms_sou_dirty_cmd) + base 1159 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c sdirty.base.crtc = crtc; base 1169 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c &sdirty.base); base 1252 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c base)->buffer; base 1358 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c container_of(vfb, struct vmw_framebuffer_bo, base)->buffer; base 43 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct ttm_base_object base; base 62 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c vmw_user_shader_base_to_res(struct ttm_base_object *base); base 285 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c BUG_ON(res->backup->base.mem.mem_type != VMW_PL_MOB); base 405 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c cmd->body.mobid = res->backup->base.mem.start; base 516 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c BUG_ON(res->backup->base.mem.mem_type != VMW_PL_MOB); base 662 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c vmw_user_shader_base_to_res(struct ttm_base_object *base) base 664 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c return &(container_of(base, struct vmw_user_shader, base)-> base 674 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ttm_base_object_kfree(ushader, base); base 696 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct ttm_base_object *base = *p_base; base 697 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c struct vmw_resource *res = vmw_user_shader_base_to_res(base); base 755 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ushader->base.shareable = false; base 756 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ushader->base.tfile = NULL; base 770 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = ttm_base_object_init(tfile, &ushader->base, false, base 780 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c *handle = ushader->base.handle; base 859 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c if ((u64)buffer->base.num_pages * PAGE_SIZE < base 986 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = ttm_bo_reserve(&buf->base, false, true, NULL); base 991 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = ttm_bo_kmap(&buf->base, 0, PAGE_ALIGN(size) >> PAGE_SHIFT, base 994 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ttm_bo_unreserve(&buf->base); base 1002 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ret = ttm_bo_validate(&buf->base, &vmw_sys_placement, &ctx); base 1004 drivers/gpu/drm/vmwgfx/vmwgfx_shader.c ttm_bo_unreserve(&buf->base); base 39 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c struct ttm_base_object base; base 104 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c ttm_base_object_kfree(usimple, base); base 119 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c struct ttm_base_object *base = *p_base; base 121 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c container_of(base, struct vmw_user_simple_resource, base); base 191 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c usimple->base.shareable = false; base 192 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c usimple->base.tfile = NULL; base 203 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c ret = ttm_base_object_init(tfile, &usimple->base, false, base 212 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c func->set_arg_handle(data, usimple->base.handle); base 237 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c struct ttm_base_object *base; base 240 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c base = ttm_base_object_lookup(tfile, handle); base 241 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c if (!base) { base 248 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c if (ttm_base_object_type(base) != func->ttm_res_type) { base 249 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c ttm_base_object_unref(&base); base 256 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c usimple = container_of(base, typeof(*usimple), base); base 258 drivers/gpu/drm/vmwgfx/vmwgfx_simple_resource.c ttm_base_object_unref(&base); base 39 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(x, struct vmw_screen_target_display_unit, base.crtc) base 41 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(x, struct vmw_screen_target_display_unit, base.encoder) base 43 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(x, struct vmw_screen_target_display_unit, base.connector) base 68 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct vmw_kms_dirty base; base 116 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct vmw_display_unit base; base 180 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c cmd->body.stid = stdu->base.unit; base 188 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu->base.set_gui_x = cmd->body.xRoot; base 189 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu->base.set_gui_y = cmd->body.yRoot; base 239 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c cmd->body.stid = stdu->base.unit; base 300 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_stdu_populate_update(cmd, stdu->base.unit, base 339 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c cmd->body.stid = stdu->base.unit; base 374 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c conn_state = stdu->base.connector.state; base 457 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(dirty, struct vmw_stdu_dirty, base); base 492 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(dirty, struct vmw_stdu_dirty, base); base 494 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(dirty->unit, typeof(*stdu), base); base 508 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_bo_get_guest_ptr(&ddirty->buf->base, &cmd->body.guest.ptr); base 515 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c suffix->maximumOffset = ddirty->buf->base.num_pages * PAGE_SIZE; base 520 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_stdu_populate_update(&suffix[1], stdu->base.unit, base 543 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(dirty, struct vmw_stdu_dirty, base); base 574 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(dirty, struct vmw_stdu_dirty, base); base 576 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(dirty->unit, typeof(*stdu), base); base 594 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c dst_bo = &stdu->display_srf->res.backup->base; base 598 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c src_bo = &ddirty->buf->base; base 630 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c dev_priv = vmw_priv(stdu->base.crtc.dev); base 635 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_stdu_populate_update(cmd, stdu->base.unit, base 684 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(vfb, struct vmw_framebuffer_bo, base)->buffer; base 708 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ddirty.pitch = vfb->base.pitches[0]; base 710 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ddirty.base.fifo_commit = vmw_stdu_bo_fifo_commit; base 711 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ddirty.base.clip = vmw_stdu_bo_clip; base 712 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ddirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_dma) + base 716 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ddirty.base.fifo_reserve_size += sizeof(struct vmw_stdu_update); base 720 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ddirty.base.fifo_commit = vmw_stdu_bo_cpu_commit; base 721 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ddirty.base.clip = vmw_stdu_bo_cpu_clip; base 722 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ddirty.base.fifo_reserve_size = 0; base 725 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ddirty.base.crtc = crtc; base 728 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c 0, 0, num_clips, increment, &ddirty.base); base 750 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(dirty, struct vmw_stdu_dirty, base); base 753 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(dirty->unit, typeof(*stdu), base); base 789 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(dirty, struct vmw_stdu_dirty, base); base 791 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(dirty->unit, typeof(*stdu), base); base 817 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_stdu_populate_update(update, stdu->base.unit, sdirty->left, base 860 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(framebuffer, typeof(*vfbs), base); base 883 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c sdirty.base.fifo_commit = vmw_kms_stdu_surface_fifo_commit; base 884 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c sdirty.base.clip = vmw_kms_stdu_surface_clip; base 885 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c sdirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_surface_copy) + base 888 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c sdirty.base.crtc = crtc; base 895 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c &sdirty.base); base 1206 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu = container_of(update->du, typeof(*stdu), base); base 1207 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vfbbo = container_of(update->vfb, typeof(*vfbbo), base); base 1213 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_bo_get_guest_ptr(&vfbbo->buffer->base, &cmd_dma->body.guest.ptr); base 1214 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c cmd_dma->body.guest.pitch = update->vfb->base.pitches[0]; base 1249 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu = container_of(update->du, typeof(*stdu), base); base 1250 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vfbbo = container_of(update->vfb, typeof(*vfbbo), base); base 1253 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c suffix->maximumOffset = vfbbo->buffer->base.num_pages * PAGE_SIZE; base 1255 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_stdu_populate_update(&suffix[1], stdu->base.unit, bb->x1, bb->x2, base 1265 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(update, typeof(*bo_update), base); base 1278 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c container_of(update, typeof(*bo_update), base); base 1301 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update = container_of(update, typeof(*bo_update), base); base 1302 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu = container_of(update->du, typeof(*stdu), base); base 1303 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vfbbo = container_of(update->vfb, typeof(*vfbbo), base); base 1310 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c dst_bo = &stdu->display_srf->res.backup->base; base 1314 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c src_bo = &vfbbo->buffer->base; base 1315 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c src_pitch = update->vfb->base.pitches[0]; base 1340 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_stdu_populate_update(cmd_update, stdu->base.unit, base 1371 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.plane = plane; base 1372 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.old_state = old_state; base 1373 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.dev_priv = dev_priv; base 1374 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.du = vmw_crtc_to_du(plane->state->crtc); base 1375 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.vfb = vfb; base 1376 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.out_fence = out_fence; base 1377 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.mutex = NULL; base 1378 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.cpu_blit = !(dev_priv->capabilities & SVGA_CAP_3D); base 1379 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.intr = false; base 1385 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c if (bo_update.base.cpu_blit) { base 1386 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.calc_fifo_size = vmw_stdu_bo_fifo_size_cpu; base 1387 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.pre_clip = vmw_stdu_bo_pre_clip_cpu; base 1388 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.clip = vmw_stdu_bo_clip_cpu; base 1389 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.post_clip = vmw_stdu_bo_populate_update_cpu; base 1391 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.calc_fifo_size = vmw_stdu_bo_fifo_size; base 1392 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.pre_clip = vmw_stdu_bo_populate_dma; base 1393 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.clip = vmw_stdu_bo_populate_clip; base 1394 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c bo_update.base.post_clip = vmw_stdu_bo_populate_update; base 1397 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c return vmw_du_helper_plane_update(&bo_update.base); base 1407 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vfbs = container_of(update->vfb, typeof(*vfbs), base); base 1423 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vfbs = container_of(update->vfb, typeof(*vfbs), base); base 1445 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vfbs = container_of(update->vfb, typeof(*vfbs), base); base 1483 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu = container_of(update->du, typeof(*stdu), base); base 1484 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vfbs = container_of(update->vfb, typeof(*vfbs), base); base 1548 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vfbs = container_of(vfb, typeof(*vfbs), base); base 1647 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c struct drm_file *file_priv = event->base.file_priv; base 1651 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c &event->base, base 1740 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu->base.unit = unit; base 1741 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c crtc = &stdu->base.crtc; base 1742 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c encoder = &stdu->base.encoder; base 1743 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c connector = &stdu->base.connector; base 1744 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c primary = &stdu->base.primary; base 1745 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c cursor = &stdu->base.cursor; base 1747 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu->base.pref_active = (unit == 0); base 1748 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu->base.pref_width = dev_priv->initial_width; base 1749 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu->base.pref_height = dev_priv->initial_height; base 1750 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c stdu->base.is_implicit = false; base 1778 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c drm_plane_cleanup(&stdu->base.primary); base 1814 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c ret = drm_crtc_init_with_planes(dev, crtc, &stdu->base.primary, base 1815 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c &stdu->base.cursor, base 1826 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c drm_object_attach_property(&connector->base, base 1828 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c drm_object_attach_property(&connector->base, base 1830 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c drm_object_attach_property(&connector->base, base 1856 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c vmw_du_cleanup(&stdu->base); base 73 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_user_surface_base_to_res(struct ttm_base_object *base); base 625 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c vmw_user_surface_base_to_res(struct ttm_base_object *base) base 627 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c return &(container_of(base, struct vmw_user_surface, base 628 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c prime.base)->srf.res); base 664 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct ttm_base_object *base = *p_base; base 666 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c container_of(base, struct vmw_user_surface, prime.base); base 837 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c user_srf->prime.base.shareable = false; base 838 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c user_srf->prime.base.tfile = NULL; base 881 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->sid = user_srf->prime.base.handle; base 910 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct ttm_base_object *base; base 926 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c base = ttm_base_object_lookup_for_ref(dev_priv->tdev, handle); base 927 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (unlikely(!base)) { base 932 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (unlikely(ttm_base_object_type(base) != VMW_RES_SURFACE)) { base 938 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c user_srf = container_of(base, struct vmw_user_surface, base 939 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c prime.base); base 949 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = ttm_ref_object_add(tfile, base, TTM_REF_USAGE, NULL, base 957 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c *base_p = base; base 961 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_base_object_unref(&base); base 989 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct ttm_base_object *base; base 993 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->handle_type, &base); base 997 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c user_srf = container_of(base, struct vmw_user_surface, prime.base); base 1013 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_ref_object_base_unref(tfile, base->handle, TTM_REF_USAGE); base 1017 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_base_object_unref(&base); base 1295 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req_ext.base = arg->req; base 1328 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->creq = rep_ext.creq.base; base 1433 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c user_srf->prime.base.shareable = false; base 1434 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c user_srf->prime.base.tfile = NULL; base 1563 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->base.svga3d_flags); base 1573 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (req->base.multisample_count != 0) base 1584 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->base.multisample_count == 0) base 1587 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (req->base.mip_levels > DRM_VMW_MAX_MIP_LEVELS) base 1600 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->base.format, base 1601 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->base.drm_surface_flags & base 1603 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->base.mip_levels, base 1604 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->base.multisample_count, base 1605 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->base.array_size, base 1606 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->base.base_size, base 1623 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (req->base.buffer_handle != SVGA3D_INVALID_ID) { base 1624 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ret = vmw_user_bo_lookup(tfile, req->base.buffer_handle, base 1628 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c if (res->backup->base.num_pages * PAGE_SIZE < base 1635 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c backup_handle = req->base.buffer_handle; base 1638 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c } else if (req->base.drm_surface_flags & base 1642 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->base.drm_surface_flags & base 1655 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->base.drm_surface_flags & base 1666 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->handle = user_srf->prime.base.handle; base 1670 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c drm_vma_node_offset_addr(&res->backup->base.base.vma_node); base 1671 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->buffer_size = res->backup->base.num_pages * PAGE_SIZE; base 1705 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c struct ttm_base_object *base; base 1710 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c req->handle_type, &base); base 1714 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c user_srf = container_of(base, struct vmw_user_surface, prime.base); base 1728 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c (void) ttm_ref_object_base_unref(tfile, base->handle, base 1733 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->creq.base.svga3d_flags = SVGA3D_FLAGS_LOWER_32(srf->flags); base 1734 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->creq.base.format = srf->format; base 1735 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->creq.base.mip_levels = srf->mip_levels[0]; base 1736 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->creq.base.drm_surface_flags = 0; base 1737 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->creq.base.multisample_count = srf->multisample_count; base 1738 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->creq.base.autogen_filter = srf->autogen_filter; base 1739 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->creq.base.array_size = srf->array_size; base 1740 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->creq.base.buffer_handle = backup_handle; base 1741 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->creq.base.base_size = srf->base_size; base 1742 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->crep.handle = user_srf->prime.base.handle; base 1746 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c drm_vma_node_offset_addr(&srf->res.backup->base.base.vma_node); base 1747 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c rep->crep.buffer_size = srf->res.backup->base.num_pages * PAGE_SIZE; base 1757 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c ttm_base_object_unref(&base); base 345 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c __sg_page_iter_start(&viter->iter.base, vsgt->sgt->sgl, base 806 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c mem->bus.base = 0; base 816 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c mem->bus.base = dev_priv->vram_start; base 43 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c struct ttm_validate_buffer base; base 190 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c list_for_each_entry(entry, &ctx->bo_list, base.head) { base 191 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c if (entry->base.bo == &vbo->base) { base 286 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val_buf = &bo_node->base; base 287 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c val_buf->bo = ttm_bo_get_unless_zero(&vbo->base); base 517 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c container_of(bo, struct vmw_buffer_object, base); base 564 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c list_for_each_entry(entry, &ctx->bo_list, base.head) { base 571 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c ret = ttm_bo_validate(entry->base.bo, base 575 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c (entry->base.bo, intr, entry->as_mob); base 645 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c list_for_each_entry(entry, &ctx->bo_list, base.head) base 670 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c list_for_each_entry(entry, &ctx->bo_list, base.head) { base 671 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c ttm_bo_put(entry->base.bo); base 672 drivers/gpu/drm/vmwgfx/vmwgfx_validation.c entry->base.bo = NULL; base 26 drivers/gpu/drm/xen/xen_drm_front_gem.c struct drm_gem_object base; base 41 drivers/gpu/drm/xen/xen_drm_front_gem.c return container_of(gem_obj, struct xen_gem_object, base); base 69 drivers/gpu/drm/xen/xen_drm_front_gem.c ret = drm_gem_object_init(dev, &xen_obj->base, size); base 119 drivers/gpu/drm/xen/xen_drm_front_gem.c xen_obj->pages = drm_gem_get_pages(&xen_obj->base); base 142 drivers/gpu/drm/xen/xen_drm_front_gem.c return &xen_obj->base; base 149 drivers/gpu/drm/xen/xen_drm_front_gem.c if (xen_obj->base.import_attach) { base 150 drivers/gpu/drm/xen/xen_drm_front_gem.c drm_prime_gem_destroy(&xen_obj->base, xen_obj->sgt_imported); base 159 drivers/gpu/drm/xen/xen_drm_front_gem.c drm_gem_put_pages(&xen_obj->base, base 212 drivers/gpu/drm/xen/xen_drm_front_gem.c xen_drm_front_dbuf_to_cookie(&xen_obj->base), base 220 drivers/gpu/drm/xen/xen_drm_front_gem.c return &xen_obj->base; base 115 drivers/gpu/host1x/dev.c .base = 0x1af0, base 137 drivers/gpu/host1x/dev.c .base = 0x1af0, base 176 drivers/gpu/host1x/dev.c host1x_hypervisor_writel(host, entry->offset, entry->base); base 177 drivers/gpu/host1x/dev.c host1x_hypervisor_writel(host, entry->limit, entry->base + 4); base 87 drivers/gpu/host1x/dev.h unsigned int base; base 60 drivers/gpu/host1x/hw/channel_hw.c dma_addr_t addr = g->base + g->offset; base 95 drivers/gpu/host1x/hw/channel_hw.c id = sp->base->id; base 171 drivers/gpu/host1x/hw/channel_hw.c if (sp->base) base 220 drivers/gpu/host1x/hw/debug_hw.c &g->base, g->offset, g->words); base 222 drivers/gpu/host1x/hw/debug_hw.c show_gather(o, g->base + g->offset, g->words, cdma, base 223 drivers/gpu/host1x/hw/debug_hw.c g->base, mapped); base 21 drivers/gpu/host1x/hw/debug_hw_1x01.c u32 val, base, baseval; base 46 drivers/gpu/host1x/hw/debug_hw_1x01.c base = (cbread >> 16) & 0xff; base 48 drivers/gpu/host1x/hw/debug_hw_1x01.c host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(base)); base 51 drivers/gpu/host1x/hw/debug_hw_1x01.c cbread >> 24, baseval + val, base, base 487 drivers/gpu/host1x/job.c g->base = job->gather_copy; base 531 drivers/gpu/host1x/job.c g->base = job->gather_addr_phys[i]; base 536 drivers/gpu/host1x/job.c job->gathers[j].base = g->base; base 13 drivers/gpu/host1x/job.h dma_addr_t base; base 39 drivers/gpu/host1x/syncpt.c static void host1x_syncpt_base_free(struct host1x_syncpt_base *base) base 41 drivers/gpu/host1x/syncpt.c if (base) base 42 drivers/gpu/host1x/syncpt.c base->requested = false; base 62 drivers/gpu/host1x/syncpt.c sp->base = host1x_syncpt_base_request(host); base 63 drivers/gpu/host1x/syncpt.c if (!sp->base) base 84 drivers/gpu/host1x/syncpt.c host1x_syncpt_base_free(sp->base); base 85 drivers/gpu/host1x/syncpt.c sp->base = NULL; base 447 drivers/gpu/host1x/syncpt.c host1x_syncpt_base_free(sp->base); base 449 drivers/gpu/host1x/syncpt.c sp->base = NULL; base 542 drivers/gpu/host1x/syncpt.c return sp ? sp->base : NULL; base 550 drivers/gpu/host1x/syncpt.c u32 host1x_syncpt_base_id(struct host1x_syncpt_base *base) base 552 drivers/gpu/host1x/syncpt.c return base->id; base 37 drivers/gpu/host1x/syncpt.h struct host1x_syncpt_base *base; base 23 drivers/gpu/ipu-v3/ipu-cpmem.c struct ipu_ch_param __iomem *base; base 97 drivers/gpu/ipu-v3/ipu-cpmem.c return cpmem->base + ch->num; base 102 drivers/gpu/ipu-v3/ipu-cpmem.c struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); base 113 drivers/gpu/ipu-v3/ipu-cpmem.c val = readl(&base->word[word].data[i]); base 116 drivers/gpu/ipu-v3/ipu-cpmem.c writel(val, &base->word[word].data[i]); base 119 drivers/gpu/ipu-v3/ipu-cpmem.c val = readl(&base->word[word].data[i + 1]); base 122 drivers/gpu/ipu-v3/ipu-cpmem.c writel(val, &base->word[word].data[i + 1]); base 128 drivers/gpu/ipu-v3/ipu-cpmem.c struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); base 139 drivers/gpu/ipu-v3/ipu-cpmem.c val = (readl(&base->word[word].data[i]) >> ofs) & mask; base 144 drivers/gpu/ipu-v3/ipu-cpmem.c tmp = readl(&base->word[word].data[i + 1]); base 231 drivers/gpu/ipu-v3/ipu-cpmem.c void __iomem *base = p; base 235 drivers/gpu/ipu-v3/ipu-cpmem.c writel(0, base + i * sizeof(u32)); base 952 drivers/gpu/ipu-v3/ipu-cpmem.c int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base) base 963 drivers/gpu/ipu-v3/ipu-cpmem.c cpmem->base = devm_ioremap(dev, base, SZ_128K); base 964 drivers/gpu/ipu-v3/ipu-cpmem.c if (!cpmem->base) base 968 drivers/gpu/ipu-v3/ipu-cpmem.c base, cpmem->base); base 23 drivers/gpu/ipu-v3/ipu-csi.c void __iomem *base; base 179 drivers/gpu/ipu-v3/ipu-csi.c return readl(csi->base + offset); base 185 drivers/gpu/ipu-v3/ipu-csi.c writel(value, csi->base + offset); base 766 drivers/gpu/ipu-v3/ipu-csi.c unsigned long base, u32 module, struct clk *clk_ipu) base 783 drivers/gpu/ipu-v3/ipu-csi.c csi->base = devm_ioremap(dev, base, PAGE_SIZE); base 784 drivers/gpu/ipu-v3/ipu-csi.c if (!csi->base) base 788 drivers/gpu/ipu-v3/ipu-csi.c id, base, csi->base); base 92 drivers/gpu/ipu-v3/ipu-dc.c void __iomem *base; base 113 drivers/gpu/ipu-v3/ipu-dc.c reg = readl(dc->base + DC_RL_CH(event)); base 116 drivers/gpu/ipu-v3/ipu-dc.c writel(reg, dc->base + DC_RL_CH(event)); base 212 drivers/gpu/ipu-v3/ipu-dc.c reg = readl(dc->base + DC_WR_CH_CONF); base 217 drivers/gpu/ipu-v3/ipu-dc.c writel(reg, dc->base + DC_WR_CH_CONF); base 219 drivers/gpu/ipu-v3/ipu-dc.c writel(0x0, dc->base + DC_WR_CH_ADDR); base 245 drivers/gpu/ipu-v3/ipu-dc.c reg = readl(dc->base + DC_WR_CH_CONF); base 247 drivers/gpu/ipu-v3/ipu-dc.c writel(reg, dc->base + DC_WR_CH_CONF); base 255 drivers/gpu/ipu-v3/ipu-dc.c val = readl(dc->base + DC_WR_CH_CONF); base 257 drivers/gpu/ipu-v3/ipu-dc.c writel(val, dc->base + DC_WR_CH_CONF); base 339 drivers/gpu/ipu-v3/ipu-dc.c unsigned long base, unsigned long template_base) base 354 drivers/gpu/ipu-v3/ipu-dc.c priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE); base 362 drivers/gpu/ipu-v3/ipu-dc.c priv->channels[i].base = priv->dc_reg + channel_offsets[i]; base 367 drivers/gpu/ipu-v3/ipu-dc.c priv->channels[1].base + DC_WR_CH_CONF); base 369 drivers/gpu/ipu-v3/ipu-dc.c priv->channels[5].base + DC_WR_CH_CONF); base 377 drivers/gpu/ipu-v3/ipu-dc.c base, template_base); base 18 drivers/gpu/ipu-v3/ipu-di.c void __iomem *base; base 125 drivers/gpu/ipu-v3/ipu-di.c return readl(di->base + offset); base 130 drivers/gpu/ipu-v3/ipu-di.c writel(value, di->base + offset); base 708 drivers/gpu/ipu-v3/ipu-di.c unsigned long base, base 729 drivers/gpu/ipu-v3/ipu-di.c di->base = devm_ioremap(dev, base, PAGE_SIZE); base 730 drivers/gpu/ipu-v3/ipu-di.c if (!di->base) base 736 drivers/gpu/ipu-v3/ipu-di.c id, base, di->base); base 97 drivers/gpu/ipu-v3/ipu-dmfc.c void __iomem *base; base 142 drivers/gpu/ipu-v3/ipu-dmfc.c dmfc_gen1 = readl(priv->base + DMFC_GENERAL1); base 149 drivers/gpu/ipu-v3/ipu-dmfc.c writel(dmfc_gen1, priv->base + DMFC_GENERAL1); base 172 drivers/gpu/ipu-v3/ipu-dmfc.c int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, base 182 drivers/gpu/ipu-v3/ipu-dmfc.c priv->base = devm_ioremap(dev, base, PAGE_SIZE); base 183 drivers/gpu/ipu-v3/ipu-dmfc.c if (!priv->base) base 203 drivers/gpu/ipu-v3/ipu-dmfc.c writel(0x00000050, priv->base + DMFC_WR_CHAN); base 204 drivers/gpu/ipu-v3/ipu-dmfc.c writel(0x00005654, priv->base + DMFC_DP_CHAN); base 205 drivers/gpu/ipu-v3/ipu-dmfc.c writel(0x202020f6, priv->base + DMFC_WR_CHAN_DEF); base 206 drivers/gpu/ipu-v3/ipu-dmfc.c writel(0x2020f6f6, priv->base + DMFC_DP_CHAN_DEF); base 207 drivers/gpu/ipu-v3/ipu-dmfc.c writel(0x00000003, priv->base + DMFC_GENERAL1); base 55 drivers/gpu/ipu-v3/ipu-dp.c void __iomem *base; base 62 drivers/gpu/ipu-v3/ipu-dp.c void __iomem *base; base 87 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); base 92 drivers/gpu/ipu-v3/ipu-dp.c writel(reg, flow->base + DP_COM_CONF); base 95 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_GRAPH_WIND_CTRL) & 0x00FFFFFFL; base 97 drivers/gpu/ipu-v3/ipu-dp.c flow->base + DP_GRAPH_WIND_CTRL); base 99 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); base 100 drivers/gpu/ipu-v3/ipu-dp.c writel(reg | DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); base 102 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); base 103 drivers/gpu/ipu-v3/ipu-dp.c writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); base 119 drivers/gpu/ipu-v3/ipu-dp.c writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS); base 134 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); base 138 drivers/gpu/ipu-v3/ipu-dp.c writel(reg, flow->base + DP_COM_CONF); base 143 drivers/gpu/ipu-v3/ipu-dp.c writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0); base 144 drivers/gpu/ipu-v3/ipu-dp.c writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1); base 145 drivers/gpu/ipu-v3/ipu-dp.c writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2); base 146 drivers/gpu/ipu-v3/ipu-dp.c writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3); base 148 drivers/gpu/ipu-v3/ipu-dp.c flow->base + DP_CSC_0); base 150 drivers/gpu/ipu-v3/ipu-dp.c flow->base + DP_CSC_1); base 152 drivers/gpu/ipu-v3/ipu-dp.c writel(0x095 | (0x000 << 16), flow->base + DP_CSC_A_0); base 153 drivers/gpu/ipu-v3/ipu-dp.c writel(0x0cc | (0x095 << 16), flow->base + DP_CSC_A_1); base 154 drivers/gpu/ipu-v3/ipu-dp.c writel(0x3ce | (0x398 << 16), flow->base + DP_CSC_A_2); base 155 drivers/gpu/ipu-v3/ipu-dp.c writel(0x095 | (0x0ff << 16), flow->base + DP_CSC_A_3); base 157 drivers/gpu/ipu-v3/ipu-dp.c flow->base + DP_CSC_0); base 159 drivers/gpu/ipu-v3/ipu-dp.c flow->base + DP_CSC_1); base 164 drivers/gpu/ipu-v3/ipu-dp.c writel(reg, flow->base + DP_COM_CONF); base 238 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); base 240 drivers/gpu/ipu-v3/ipu-dp.c writel(reg, flow->base + DP_COM_CONF); base 263 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); base 270 drivers/gpu/ipu-v3/ipu-dp.c writel(reg, flow->base + DP_COM_CONF); base 272 drivers/gpu/ipu-v3/ipu-dp.c writel(0, flow->base + DP_FG_POS); base 325 drivers/gpu/ipu-v3/ipu-dp.c int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base) base 338 drivers/gpu/ipu-v3/ipu-dp.c priv->base = devm_ioremap(dev, base, PAGE_SIZE); base 339 drivers/gpu/ipu-v3/ipu-dp.c if (!priv->base) base 348 drivers/gpu/ipu-v3/ipu-dp.c priv->flow[i].base = priv->base + ipu_dp_flow_base[i]; base 155 drivers/gpu/ipu-v3/ipu-ic.c void __iomem *base; base 166 drivers/gpu/ipu-v3/ipu-ic.c return readl(ic->priv->base + offset); base 171 drivers/gpu/ipu-v3/ipu-ic.c writel(value, ic->priv->base + offset); base 179 drivers/gpu/ipu-v3/ipu-ic.c u32 __iomem *base; base 184 drivers/gpu/ipu-v3/ipu-ic.c base = (u32 __iomem *) base 193 drivers/gpu/ipu-v3/ipu-ic.c writel(param, base++); base 197 drivers/gpu/ipu-v3/ipu-ic.c writel(param, base++); base 201 drivers/gpu/ipu-v3/ipu-ic.c writel(param, base++); base 204 drivers/gpu/ipu-v3/ipu-ic.c writel(param, base++); base 208 drivers/gpu/ipu-v3/ipu-ic.c writel(param, base++); base 211 drivers/gpu/ipu-v3/ipu-ic.c writel(param, base++); base 698 drivers/gpu/ipu-v3/ipu-ic.c unsigned long base, unsigned long tpmem_base) base 710 drivers/gpu/ipu-v3/ipu-ic.c priv->base = devm_ioremap(dev, base, PAGE_SIZE); base 711 drivers/gpu/ipu-v3/ipu-ic.c if (!priv->base) base 717 drivers/gpu/ipu-v3/ipu-ic.c dev_dbg(dev, "IC base: 0x%08lx remapped to %p\n", base, priv->base); base 112 drivers/gpu/ipu-v3/ipu-image-convert.c struct ipu_image base; base 331 drivers/gpu/ipu-v3/ipu-image-convert.c ic_image->base.pix.width, ic_image->base.pix.height, base 720 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int resized_width = out->base.rect.width; base 721 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int resized_height = out->base.rect.height; base 732 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int in_right = in->base.rect.width; base 733 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int in_bottom = in->base.rect.height; base 734 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int out_right = out->base.rect.width; base 735 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int out_bottom = out->base.rect.height; base 741 drivers/gpu/ipu-v3/ipu-image-convert.c resized_width = out->base.rect.height; base 742 drivers/gpu/ipu-v3/ipu-image-convert.c resized_height = out->base.rect.width; base 747 drivers/gpu/ipu-v3/ipu-image-convert.c out_right = out->base.rect.height; base 748 drivers/gpu/ipu-v3/ipu-image-convert.c out_bottom = out->base.rect.width; base 982 drivers/gpu/ipu-v3/ipu-image-convert.c H = image->base.pix.height; base 1310 drivers/gpu/ipu-v3/ipu-image-convert.c addr0 = image->base.phys0 + base 1313 drivers/gpu/ipu-v3/ipu-image-convert.c addr1 = image->base.phys0 + base 1486 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->in.base.phys0 = run->in_phys; base 1487 drivers/gpu/ipu-v3/ipu-image-convert.c ctx->out.base.phys0 = run->out_phys; base 1669 drivers/gpu/ipu-v3/ipu-image-convert.c s_image->base.phys0 + base 1672 drivers/gpu/ipu-v3/ipu-image-convert.c d_image->base.phys0 + base 1693 drivers/gpu/ipu-v3/ipu-image-convert.c s_image->base.phys0 + src_tile->offset); base 1695 drivers/gpu/ipu-v3/ipu-image-convert.c d_image->base.phys0 + dst_tile->offset); base 1897 drivers/gpu/ipu-v3/ipu-image-convert.c ic_image->base = *image; base 1908 drivers/gpu/ipu-v3/ipu-image-convert.c ic_image->stride = ic_image->base.pix.width; base 1910 drivers/gpu/ipu-v3/ipu-image-convert.c ic_image->stride = ic_image->base.pix.bytesperline; base 2126 drivers/gpu/ipu-v3/ipu-image-convert.c s_image->base.pix.ycbcr_enc, base 2127 drivers/gpu/ipu-v3/ipu-image-convert.c s_image->base.pix.quantization, base 2129 drivers/gpu/ipu-v3/ipu-image-convert.c d_image->base.pix.ycbcr_enc, base 2130 drivers/gpu/ipu-v3/ipu-image-convert.c d_image->base.pix.quantization, base 221 drivers/gpu/ipu-v3/ipu-prv.h unsigned long base, u32 module, struct clk *clk_ipu); base 225 drivers/gpu/ipu-v3/ipu-prv.h unsigned long base, unsigned long tpmem_base); base 229 drivers/gpu/ipu-v3/ipu-prv.h unsigned long base, u32 module); base 236 drivers/gpu/ipu-v3/ipu-prv.h unsigned long base, u32 module, struct clk *ipu_clk); base 239 drivers/gpu/ipu-v3/ipu-prv.h int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, base 243 drivers/gpu/ipu-v3/ipu-prv.h int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); base 246 drivers/gpu/ipu-v3/ipu-prv.h int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, base 250 drivers/gpu/ipu-v3/ipu-prv.h int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); base 253 drivers/gpu/ipu-v3/ipu-prv.h int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); base 24 drivers/gpu/ipu-v3/ipu-smfc.c void __iomem *base; base 45 drivers/gpu/ipu-v3/ipu-smfc.c val = readl(priv->base + SMFC_BS); base 48 drivers/gpu/ipu-v3/ipu-smfc.c writel(val, priv->base + SMFC_BS); base 65 drivers/gpu/ipu-v3/ipu-smfc.c val = readl(priv->base + SMFC_MAP); base 68 drivers/gpu/ipu-v3/ipu-smfc.c writel(val, priv->base + SMFC_MAP); base 85 drivers/gpu/ipu-v3/ipu-smfc.c val = readl(priv->base + SMFC_WMC); base 88 drivers/gpu/ipu-v3/ipu-smfc.c writel(val, priv->base + SMFC_WMC); base 173 drivers/gpu/ipu-v3/ipu-smfc.c unsigned long base) base 186 drivers/gpu/ipu-v3/ipu-smfc.c priv->base = devm_ioremap(dev, base, PAGE_SIZE); base 187 drivers/gpu/ipu-v3/ipu-smfc.c if (!priv->base) base 195 drivers/gpu/ipu-v3/ipu-smfc.c pr_debug("%s: ioremap 0x%08lx -> %p\n", __func__, base, priv->base); base 10 drivers/gpu/ipu-v3/ipu-vdi.c void __iomem *base; base 47 drivers/gpu/ipu-v3/ipu-vdi.c return readl(vdi->base + offset); base 53 drivers/gpu/ipu-v3/ipu-vdi.c writel(value, vdi->base + offset); base 210 drivers/gpu/ipu-v3/ipu-vdi.c unsigned long base, u32 module) base 222 drivers/gpu/ipu-v3/ipu-vdi.c vdi->base = devm_ioremap(dev, base, PAGE_SIZE); base 223 drivers/gpu/ipu-v3/ipu-vdi.c if (!vdi->base) base 226 drivers/gpu/ipu-v3/ipu-vdi.c dev_dbg(dev, "VDI base: 0x%08lx remapped to %p\n", base, vdi->base); base 1460 drivers/gpu/vga/vgaarb.c u64 base = screen_info.lfb_base; base 1468 drivers/gpu/vga/vgaarb.c base |= (u64)screen_info.ext_lfb_base << 32; base 1470 drivers/gpu/vga/vgaarb.c limit = base + size; base 1496 drivers/gpu/vga/vgaarb.c if (base < start || limit >= end) base 1336 drivers/hid/hid-cp2112.c dev->gc.base = -1; base 330 drivers/hsi/controllers/omap_ssi_core.c void __iomem *base; base 334 drivers/hsi/controllers/omap_ssi_core.c base = devm_ioremap_resource(&ssi->device, mem); base 335 drivers/hsi/controllers/omap_ssi_core.c if (IS_ERR(base)) base 336 drivers/hsi/controllers/omap_ssi_core.c return PTR_ERR(base); base 338 drivers/hsi/controllers/omap_ssi_core.c *pbase = base; base 53 drivers/hsi/controllers/omap_ssi_port.c void __iomem *base = omap_ssi->sys; base 60 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_WAKE_REG(port->num))); base 62 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_MPU_ENABLE_REG(port->num, 0))); base 64 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_MPU_STATUS_REG(port->num, 0))); base 66 drivers/hsi/controllers/omap_ssi_port.c base = omap_port->sst_base; base 69 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SST_ID_REG)); base 71 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SST_MODE_REG)); base 73 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SST_FRAMESIZE_REG)); base 75 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SST_DIVISOR_REG)); base 77 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SST_CHANNELS_REG)); base 79 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SST_ARBMODE_REG)); base 81 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SST_TXSTATE_REG)); base 83 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SST_BUFSTATE_REG)); base 85 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SST_BREAK_REG)); base 88 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SST_BUFFER_CH_REG(ch))); base 91 drivers/hsi/controllers/omap_ssi_port.c base = omap_port->ssr_base; base 94 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SSR_ID_REG)); base 96 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SSR_MODE_REG)); base 98 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SSR_FRAMESIZE_REG)); base 100 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SSR_CHANNELS_REG)); base 102 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SSR_TIMEOUT_REG)); base 104 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SSR_RXSTATE_REG)); base 106 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SSR_BUFSTATE_REG)); base 108 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SSR_BREAK_REG)); base 110 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SSR_ERROR_REG)); base 112 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SSR_ERRORACK_REG)); base 115 drivers/hsi/controllers/omap_ssi_port.c readl(base + SSI_SSR_BUFFER_CH_REG(ch))); base 1098 drivers/hsi/controllers/omap_ssi_port.c void __iomem *base; base 1112 drivers/hsi/controllers/omap_ssi_port.c base = devm_ioremap(&port->device, mem->start, resource_size(mem)); base 1113 drivers/hsi/controllers/omap_ssi_port.c if (!base) { base 1117 drivers/hsi/controllers/omap_ssi_port.c *pbase = base; base 1303 drivers/hsi/controllers/omap_ssi_port.c void __iomem *base; base 1309 drivers/hsi/controllers/omap_ssi_port.c base = omap_port->sst_base; base 1310 drivers/hsi/controllers/omap_ssi_port.c writel_relaxed(omap_port->sst.frame_size, base + SSI_SST_FRAMESIZE_REG); base 1311 drivers/hsi/controllers/omap_ssi_port.c writel_relaxed(omap_port->sst.channels, base + SSI_SST_CHANNELS_REG); base 1312 drivers/hsi/controllers/omap_ssi_port.c writel_relaxed(omap_port->sst.arb_mode, base + SSI_SST_ARBMODE_REG); base 1315 drivers/hsi/controllers/omap_ssi_port.c base = omap_port->ssr_base; base 1316 drivers/hsi/controllers/omap_ssi_port.c writel_relaxed(omap_port->ssr.frame_size, base + SSI_SSR_FRAMESIZE_REG); base 1317 drivers/hsi/controllers/omap_ssi_port.c writel_relaxed(omap_port->ssr.channels, base + SSI_SSR_CHANNELS_REG); base 1318 drivers/hsi/controllers/omap_ssi_port.c writel_relaxed(omap_port->ssr.timeout, base + SSI_SSR_TIMEOUT_REG); base 28 drivers/hwmon/as370-hwmon.c void __iomem *base; base 34 drivers/hwmon/as370-hwmon.c void __iomem *addr = hwmon->base + CTRL; base 54 drivers/hwmon/as370-hwmon.c val = readl_relaxed(hwmon->base + STS) & BN_MASK; base 114 drivers/hwmon/as370-hwmon.c hwmon->base = devm_platform_ioremap_resource(pdev, 0); base 115 drivers/hwmon/as370-hwmon.c if (IS_ERR(hwmon->base)) base 116 drivers/hwmon/as370-hwmon.c return PTR_ERR(hwmon->base); base 62 drivers/hwmon/f71805f.c superio_inb(int base, int reg) base 64 drivers/hwmon/f71805f.c outb(reg, base); base 65 drivers/hwmon/f71805f.c return inb(base + 1); base 69 drivers/hwmon/f71805f.c superio_inw(int base, int reg) base 72 drivers/hwmon/f71805f.c outb(reg++, base); base 73 drivers/hwmon/f71805f.c val = inb(base + 1) << 8; base 74 drivers/hwmon/f71805f.c outb(reg, base); base 75 drivers/hwmon/f71805f.c val |= inb(base + 1); base 80 drivers/hwmon/f71805f.c superio_select(int base, int ld) base 82 drivers/hwmon/f71805f.c outb(SIO_REG_LDSEL, base); base 83 drivers/hwmon/f71805f.c outb(ld, base + 1); base 87 drivers/hwmon/f71805f.c superio_enter(int base) base 89 drivers/hwmon/f71805f.c if (!request_muxed_region(base, 2, DRVNAME)) base 92 drivers/hwmon/f71805f.c outb(0x87, base); base 93 drivers/hwmon/f71805f.c outb(0x87, base); base 99 drivers/hwmon/f71805f.c superio_exit(int base) base 101 drivers/hwmon/f71805f.c outb(0xaa, base); base 102 drivers/hwmon/f71805f.c release_region(base, 2); base 239 drivers/hwmon/f71882fg.c static inline int superio_inb(int base, int reg); base 240 drivers/hwmon/f71882fg.c static inline int superio_inw(int base, int reg); base 241 drivers/hwmon/f71882fg.c static inline int superio_enter(int base); base 242 drivers/hwmon/f71882fg.c static inline void superio_select(int base, int ld); base 243 drivers/hwmon/f71882fg.c static inline void superio_exit(int base); base 1104 drivers/hwmon/f71882fg.c static inline int superio_inb(int base, int reg) base 1106 drivers/hwmon/f71882fg.c outb(reg, base); base 1107 drivers/hwmon/f71882fg.c return inb(base + 1); base 1110 drivers/hwmon/f71882fg.c static int superio_inw(int base, int reg) base 1113 drivers/hwmon/f71882fg.c val = superio_inb(base, reg) << 8; base 1114 drivers/hwmon/f71882fg.c val |= superio_inb(base, reg + 1); base 1118 drivers/hwmon/f71882fg.c static inline int superio_enter(int base) base 1121 drivers/hwmon/f71882fg.c if (!request_muxed_region(base, 2, DRVNAME)) { base 1122 drivers/hwmon/f71882fg.c pr_err("I/O address 0x%04x already in use\n", base); base 1127 drivers/hwmon/f71882fg.c outb(SIO_UNLOCK_KEY, base); base 1128 drivers/hwmon/f71882fg.c outb(SIO_UNLOCK_KEY, base); base 1133 drivers/hwmon/f71882fg.c static inline void superio_select(int base, int ld) base 1135 drivers/hwmon/f71882fg.c outb(SIO_REG_LDSEL, base); base 1136 drivers/hwmon/f71882fg.c outb(ld, base + 1); base 1139 drivers/hwmon/f71882fg.c static inline void superio_exit(int base) base 1141 drivers/hwmon/f71882fg.c outb(SIO_LOCK_KEY, base); base 1142 drivers/hwmon/f71882fg.c release_region(base, 2); base 891 drivers/hwmon/hwmon.c u16 base; base 900 drivers/hwmon/hwmon.c pci_read_config_word(sb, 0x64, &base); base 902 drivers/hwmon/hwmon.c if (base == 0 && !(enable & BIT(2))) { base 98 drivers/hwmon/k10temp.c unsigned int base, int offset, u32 *val) base 102 drivers/hwmon/k10temp.c base, offset); base 104 drivers/hwmon/k10temp.c base + 4, val); base 248 drivers/hwmon/lm93.c u8 base[4]; base 1087 drivers/hwmon/lm93.c data->block10.base[i] = base 1340 drivers/hwmon/lm93.c return sprintf(buf, "%d\n", LM93_TEMP_FROM_REG(data->block10.base[nr])); base 1358 drivers/hwmon/lm93.c data->block10.base[nr] = LM93_TEMP_TO_REG(val); base 1359 drivers/hwmon/lm93.c lm93_write_byte(client, LM93_REG_TEMP_BASE(nr), data->block10.base[nr]); base 390 drivers/hwmon/nct6683.c int base; base 437 drivers/hwmon/nct6683.c (*t)->dev_attr.attr.name, tg->base + i); base 779 drivers/hwmon/nct6683.c .base = 1, base 907 drivers/hwmon/nct6683.c .base = 1, base 969 drivers/hwmon/nct6683.c .base = 1, base 1277 drivers/hwmon/nct6775.c int base; base 1324 drivers/hwmon/nct6775.c (*t)->dev_attr.attr.name, tg->base + i); base 2307 drivers/hwmon/nct6775.c .base = 1, base 2519 drivers/hwmon/nct6775.c .base = 1, base 3393 drivers/hwmon/nct6775.c .base = 1, base 19 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) base 21 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00) base 22 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04) base 23 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08) base 24 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \ base 25 drivers/hwmon/npcm750-pwm-fan.c (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch))) base 26 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_REG_CMRx(base, n, ch) \ base 27 drivers/hwmon/npcm750-pwm-fan.c (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch))) base 28 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_REG_PDRx(base, n, ch) \ base 29 drivers/hwmon/npcm750-pwm-fan.c (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch))) base 30 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_REG_PIER(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C) base 31 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_PWM_REG_PIIR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x40) base 80 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) base 82 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TCNT1(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x00) base 83 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TCRA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x02) base 84 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TCRB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x04) base 85 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TCNT2(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x06) base 86 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TPRSC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x08) base 87 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TCKC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A) base 88 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TMCTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C) base 89 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TICTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E) base 90 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TICLR(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x10) base 91 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TIEN(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x12) base 92 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TCPA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x14) base 93 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TCPB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x16) base 94 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TCPCFG(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x18) base 95 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TINASEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A) base 96 drivers/hwmon/npcm750-pwm-fan.c #define NPCM7XX_FAN_REG_TINBSEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C) base 547 drivers/hwmon/pmbus/pmbus_core.c u16 base; base 577 drivers/hwmon/pmbus/pmbus_core.c data->status[s->base + i] base 1180 drivers/hwmon/pmbus/pmbus_core.c struct pmbus_sensor *base, base 1200 drivers/hwmon/pmbus/pmbus_core.c attr->compare ? l->low ? curr : base base 1202 drivers/hwmon/pmbus/pmbus_core.c attr->compare ? l->low ? base : curr base 1223 drivers/hwmon/pmbus/pmbus_core.c struct pmbus_sensor *base; base 1233 drivers/hwmon/pmbus/pmbus_core.c base = pmbus_add_sensor(data, name, "input", index, page, attr->reg, base 1235 drivers/hwmon/pmbus/pmbus_core.c if (!base) base 1239 drivers/hwmon/pmbus/pmbus_core.c index, page, base, attr); base 1894 drivers/hwmon/pmbus/pmbus_core.c int base; base 1897 drivers/hwmon/pmbus/pmbus_core.c base = PB_STATUS_FAN34_BASE + page; base 1899 drivers/hwmon/pmbus/pmbus_core.c base = PB_STATUS_FAN_BASE + page; base 1901 drivers/hwmon/pmbus/pmbus_core.c "alarm", index, NULL, NULL, base, base 1906 drivers/hwmon/pmbus/pmbus_core.c "fault", index, NULL, NULL, base, base 344 drivers/hwmon/pmbus/ucd9000.c data->gpio.base = -1; base 65 drivers/hwmon/sch56xx-common.c static inline int superio_inb(int base, int reg) base 67 drivers/hwmon/sch56xx-common.c outb(reg, base); base 68 drivers/hwmon/sch56xx-common.c return inb(base + 1); base 71 drivers/hwmon/sch56xx-common.c static inline int superio_enter(int base) base 74 drivers/hwmon/sch56xx-common.c if (!request_muxed_region(base, 2, "sch56xx")) { base 75 drivers/hwmon/sch56xx-common.c pr_err("I/O address 0x%04x already in use\n", base); base 79 drivers/hwmon/sch56xx-common.c outb(SIO_UNLOCK_KEY, base); base 84 drivers/hwmon/sch56xx-common.c static inline void superio_select(int base, int ld) base 86 drivers/hwmon/sch56xx-common.c outb(SIO_REG_LDSEL, base); base 87 drivers/hwmon/sch56xx-common.c outb(ld, base + 1); base 90 drivers/hwmon/sch56xx-common.c static inline void superio_exit(int base) base 92 drivers/hwmon/sch56xx-common.c outb(SIO_LOCK_KEY, base); base 93 drivers/hwmon/sch56xx-common.c release_region(base, 2); base 82 drivers/hwspinlock/qcom_hwspinlock.c u32 base; base 97 drivers/hwspinlock/qcom_hwspinlock.c ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, &base); base 117 drivers/hwspinlock/qcom_hwspinlock.c field.reg = base + i * stride; base 37 drivers/hwspinlock/sprd_hwspinlock.c void __iomem *base; base 55 drivers/hwspinlock/sprd_hwspinlock.c user_id = readl(sprd_hwlock->base + HWSPINLOCK_MASTERID(lock_id)); base 100 drivers/hwspinlock/sprd_hwspinlock.c sprd_hwlock->base = devm_ioremap_resource(&pdev->dev, res); base 101 drivers/hwspinlock/sprd_hwspinlock.c if (IS_ERR(sprd_hwlock->base)) base 102 drivers/hwspinlock/sprd_hwspinlock.c return PTR_ERR(sprd_hwlock->base); base 113 drivers/hwspinlock/sprd_hwspinlock.c writel(HWSPINLOCK_USER_BITS, sprd_hwlock->base + HWSPINLOCK_RECCTRL); base 117 drivers/hwspinlock/sprd_hwspinlock.c lock->priv = sprd_hwlock->base + HWSPINLOCK_TOKEN(i); base 404 drivers/hwtracing/coresight/coresight-catu.c return coresight_timeout(drvdata->base, base 424 drivers/hwtracing/coresight/coresight-catu.c rc = coresight_claim_device_unlocked(drvdata->base); base 458 drivers/hwtracing/coresight/coresight-catu.c CS_UNLOCK(catu_drvdata->base); base 460 drivers/hwtracing/coresight/coresight-catu.c CS_LOCK(catu_drvdata->base); base 470 drivers/hwtracing/coresight/coresight-catu.c coresight_disclaim_device_unlocked(drvdata->base); base 485 drivers/hwtracing/coresight/coresight-catu.c CS_UNLOCK(catu_drvdata->base); base 487 drivers/hwtracing/coresight/coresight-catu.c CS_LOCK(catu_drvdata->base); base 508 drivers/hwtracing/coresight/coresight-catu.c void __iomem *base; base 521 drivers/hwtracing/coresight/coresight-catu.c base = devm_ioremap_resource(dev, &adev->res); base 522 drivers/hwtracing/coresight/coresight-catu.c if (IS_ERR(base)) { base 523 drivers/hwtracing/coresight/coresight-catu.c ret = PTR_ERR(base); base 528 drivers/hwtracing/coresight/coresight-catu.c dma_mask = readl_relaxed(base + CORESIGHT_DEVID) & 0x3f; base 553 drivers/hwtracing/coresight/coresight-catu.c drvdata->base = base; base 64 drivers/hwtracing/coresight/coresight-catu.h void __iomem *base; base 73 drivers/hwtracing/coresight/coresight-catu.h return coresight_read_reg_pair(drvdata->base, offset, -1); \ base 78 drivers/hwtracing/coresight/coresight-catu.h coresight_write_reg_pair(drvdata->base, val, offset, -1); \ base 85 drivers/hwtracing/coresight/coresight-catu.h return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \ base 90 drivers/hwtracing/coresight/coresight-catu.h coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \ base 86 drivers/hwtracing/coresight/coresight-cpu-debug.c void __iomem *base; base 114 drivers/hwtracing/coresight/coresight-cpu-debug.c writel_relaxed(0x0, drvdata->base + EDOSLAR); base 156 drivers/hwtracing/coresight/coresight-cpu-debug.c edprcr = readl_relaxed(drvdata->base + EDPRCR); base 158 drivers/hwtracing/coresight/coresight-cpu-debug.c writel_relaxed(edprcr, drvdata->base + EDPRCR); base 161 drivers/hwtracing/coresight/coresight-cpu-debug.c if (readx_poll_timeout_atomic(readl_relaxed, drvdata->base + EDPRSR, base 179 drivers/hwtracing/coresight/coresight-cpu-debug.c edprcr = readl_relaxed(drvdata->base + EDPRCR); base 181 drivers/hwtracing/coresight/coresight-cpu-debug.c writel_relaxed(edprcr, drvdata->base + EDPRCR); base 183 drivers/hwtracing/coresight/coresight-cpu-debug.c drvdata->edprsr = readl_relaxed(drvdata->base + EDPRSR); base 194 drivers/hwtracing/coresight/coresight-cpu-debug.c CS_UNLOCK(drvdata->base); base 200 drivers/hwtracing/coresight/coresight-cpu-debug.c save_edprcr = readl_relaxed(drvdata->base + EDPRCR); base 211 drivers/hwtracing/coresight/coresight-cpu-debug.c drvdata->edpcsr = readl_relaxed(drvdata->base + EDPCSR); base 229 drivers/hwtracing/coresight/coresight-cpu-debug.c drvdata->edpcsr_hi = readl_relaxed(drvdata->base + EDPCSR_HI); base 232 drivers/hwtracing/coresight/coresight-cpu-debug.c drvdata->edcidsr = readl_relaxed(drvdata->base + EDCIDSR); base 235 drivers/hwtracing/coresight/coresight-cpu-debug.c drvdata->edvidsr = readl_relaxed(drvdata->base + EDVIDSR); base 239 drivers/hwtracing/coresight/coresight-cpu-debug.c writel_relaxed(save_edprcr, drvdata->base + EDPRCR); base 241 drivers/hwtracing/coresight/coresight-cpu-debug.c CS_LOCK(drvdata->base); base 329 drivers/hwtracing/coresight/coresight-cpu-debug.c CS_UNLOCK(drvdata->base); base 332 drivers/hwtracing/coresight/coresight-cpu-debug.c eddevid = readl_relaxed(drvdata->base + EDDEVID); base 333 drivers/hwtracing/coresight/coresight-cpu-debug.c eddevid1 = readl_relaxed(drvdata->base + EDDEVID1); base 335 drivers/hwtracing/coresight/coresight-cpu-debug.c CS_LOCK(drvdata->base); base 560 drivers/hwtracing/coresight/coresight-cpu-debug.c void __iomem *base; base 584 drivers/hwtracing/coresight/coresight-cpu-debug.c base = devm_ioremap_resource(dev, res); base 585 drivers/hwtracing/coresight/coresight-cpu-debug.c if (IS_ERR(base)) base 586 drivers/hwtracing/coresight/coresight-cpu-debug.c return PTR_ERR(base); base 588 drivers/hwtracing/coresight/coresight-cpu-debug.c drvdata->base = base; base 84 drivers/hwtracing/coresight/coresight-etb10.c void __iomem *base; base 102 drivers/hwtracing/coresight/coresight-etb10.c return readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); base 110 drivers/hwtracing/coresight/coresight-etb10.c CS_UNLOCK(drvdata->base); base 114 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); base 117 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(0x0, drvdata->base + ETB_RWD_REG); base 120 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); base 122 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); base 124 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG); base 126 drivers/hwtracing/coresight/coresight-etb10.c drvdata->base + ETB_FFCR); base 128 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG); base 130 drivers/hwtracing/coresight/coresight-etb10.c CS_LOCK(drvdata->base); base 135 drivers/hwtracing/coresight/coresight-etb10.c int rc = coresight_claim_device(drvdata->base); base 255 drivers/hwtracing/coresight/coresight-etb10.c CS_UNLOCK(drvdata->base); base 257 drivers/hwtracing/coresight/coresight-etb10.c ffcr = readl_relaxed(drvdata->base + ETB_FFCR); base 260 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(ffcr, drvdata->base + ETB_FFCR); base 263 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(ffcr, drvdata->base + ETB_FFCR); base 265 drivers/hwtracing/coresight/coresight-etb10.c if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) { base 271 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(0x0, drvdata->base + ETB_CTL_REG); base 273 drivers/hwtracing/coresight/coresight-etb10.c if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) { base 278 drivers/hwtracing/coresight/coresight-etb10.c CS_LOCK(drvdata->base); base 291 drivers/hwtracing/coresight/coresight-etb10.c CS_UNLOCK(drvdata->base); base 293 drivers/hwtracing/coresight/coresight-etb10.c read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); base 294 drivers/hwtracing/coresight/coresight-etb10.c write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); base 307 drivers/hwtracing/coresight/coresight-etb10.c if ((readl_relaxed(drvdata->base + ETB_STATUS_REG) base 309 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); base 311 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER); base 318 drivers/hwtracing/coresight/coresight-etb10.c read_data = readl_relaxed(drvdata->base + base 337 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); base 339 drivers/hwtracing/coresight/coresight-etb10.c CS_LOCK(drvdata->base); base 346 drivers/hwtracing/coresight/coresight-etb10.c coresight_disclaim_device(drvdata->base); base 450 drivers/hwtracing/coresight/coresight-etb10.c CS_UNLOCK(drvdata->base); base 453 drivers/hwtracing/coresight/coresight-etb10.c read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); base 454 drivers/hwtracing/coresight/coresight-etb10.c write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); base 476 drivers/hwtracing/coresight/coresight-etb10.c status = readl_relaxed(drvdata->base + ETB_STATUS_REG); base 524 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); base 532 drivers/hwtracing/coresight/coresight-etb10.c read_data = readl_relaxed(drvdata->base + base 552 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); base 553 drivers/hwtracing/coresight/coresight-etb10.c writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); base 565 drivers/hwtracing/coresight/coresight-etb10.c CS_LOCK(drvdata->base); base 729 drivers/hwtracing/coresight/coresight-etb10.c void __iomem *base; base 753 drivers/hwtracing/coresight/coresight-etb10.c base = devm_ioremap_resource(dev, res); base 754 drivers/hwtracing/coresight/coresight-etb10.c if (IS_ERR(base)) base 755 drivers/hwtracing/coresight/coresight-etb10.c return PTR_ERR(base); base 757 drivers/hwtracing/coresight/coresight-etb10.c drvdata->base = base; base 233 drivers/hwtracing/coresight/coresight-etm.h void __iomem *base; base 265 drivers/hwtracing/coresight/coresight-etm.h writel_relaxed(val, drvdata->base + off); base 279 drivers/hwtracing/coresight/coresight-etm.h val = readl_relaxed(drvdata->base + off); base 53 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c CS_UNLOCK(drvdata->base); base 57 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c CS_LOCK(drvdata->base); base 951 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c CS_UNLOCK(drvdata->base); base 953 drivers/hwtracing/coresight/coresight-etm3x-sysfs.c CS_LOCK(drvdata->base); base 90 drivers/hwtracing/coresight/coresight-etm3x.c etmpdcr = readl_relaxed(drvdata->base + ETMPDCR); base 92 drivers/hwtracing/coresight/coresight-etm3x.c writel_relaxed(etmpdcr, drvdata->base + ETMPDCR); base 105 drivers/hwtracing/coresight/coresight-etm3x.c etmpdcr = readl_relaxed(drvdata->base + ETMPDCR); base 107 drivers/hwtracing/coresight/coresight-etm3x.c writel_relaxed(etmpdcr, drvdata->base + ETMPDCR); base 364 drivers/hwtracing/coresight/coresight-etm3x.c CS_UNLOCK(drvdata->base); base 366 drivers/hwtracing/coresight/coresight-etm3x.c rc = coresight_claim_device_unlocked(drvdata->base); base 426 drivers/hwtracing/coresight/coresight-etm3x.c CS_LOCK(drvdata->base); base 471 drivers/hwtracing/coresight/coresight-etm3x.c CS_UNLOCK(drvdata->base); base 473 drivers/hwtracing/coresight/coresight-etm3x.c CS_LOCK(drvdata->base); base 572 drivers/hwtracing/coresight/coresight-etm3x.c CS_UNLOCK(drvdata->base); base 582 drivers/hwtracing/coresight/coresight-etm3x.c coresight_disclaim_device_unlocked(drvdata->base); base 584 drivers/hwtracing/coresight/coresight-etm3x.c CS_LOCK(drvdata->base); base 597 drivers/hwtracing/coresight/coresight-etm3x.c CS_UNLOCK(drvdata->base); base 607 drivers/hwtracing/coresight/coresight-etm3x.c coresight_disclaim_device_unlocked(drvdata->base); base 609 drivers/hwtracing/coresight/coresight-etm3x.c CS_LOCK(drvdata->base); base 744 drivers/hwtracing/coresight/coresight-etm3x.c CS_UNLOCK(drvdata->base); base 777 drivers/hwtracing/coresight/coresight-etm3x.c CS_LOCK(drvdata->base); base 788 drivers/hwtracing/coresight/coresight-etm3x.c void __iomem *base; base 803 drivers/hwtracing/coresight/coresight-etm3x.c base = devm_ioremap_resource(dev, res); base 804 drivers/hwtracing/coresight/coresight-etm3x.c if (IS_ERR(base)) base 805 drivers/hwtracing/coresight/coresight-etm3x.c return PTR_ERR(base); base 807 drivers/hwtracing/coresight/coresight-etm3x.c drvdata->base = base; base 2078 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c reg.addr = drvdata->base + offset; base 52 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(0x0, drvdata->base + TRCOSLAR); base 94 drivers/hwtracing/coresight/coresight-etm4x.c CS_UNLOCK(drvdata->base); base 98 drivers/hwtracing/coresight/coresight-etm4x.c rc = coresight_claim_device_unlocked(drvdata->base); base 103 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(0, drvdata->base + TRCPRGCTLR); base 106 drivers/hwtracing/coresight/coresight-etm4x.c if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) base 110 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR); base 111 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR); base 113 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(0x0, drvdata->base + TRCAUXCTLR); base 114 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R); base 115 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R); base 116 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR); base 117 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR); base 118 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR); base 119 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR); base 120 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR); base 121 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR); base 122 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR); base 123 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR); base 125 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCVISSCTLR); base 127 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCVIPCSSCTLR); base 130 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCSEQEVRn(i)); base 131 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR); base 132 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR); base 133 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR); base 136 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCCNTRLDVRn(i)); base 138 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCCNTCTLRn(i)); base 140 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCCNTVRn(i)); base 149 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCRSCTLRn(i)); base 153 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCSSCCRn(i)); base 155 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCSSCSRn(i)); base 157 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCSSPCICRn(i)); base 161 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCACVRn(i)); base 163 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCACATRn(i)); base 167 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCCIDCVRn(i)); base 168 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0); base 169 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1); base 173 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCVMIDCVRn(i)); base 174 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); base 175 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); base 181 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU, base 182 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base + TRCPDCR); base 185 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(1, drvdata->base + TRCPRGCTLR); base 188 drivers/hwtracing/coresight/coresight-etm4x.c if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) base 200 drivers/hwtracing/coresight/coresight-etm4x.c CS_LOCK(drvdata->base); base 452 drivers/hwtracing/coresight/coresight-etm4x.c CS_UNLOCK(drvdata->base); base 455 drivers/hwtracing/coresight/coresight-etm4x.c control = readl_relaxed(drvdata->base + TRCPDCR); base 457 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(control, drvdata->base + TRCPDCR); base 459 drivers/hwtracing/coresight/coresight-etm4x.c control = readl_relaxed(drvdata->base + TRCPRGCTLR); base 471 drivers/hwtracing/coresight/coresight-etm4x.c writel_relaxed(control, drvdata->base + TRCPRGCTLR); base 473 drivers/hwtracing/coresight/coresight-etm4x.c coresight_disclaim_device_unlocked(drvdata->base); base 475 drivers/hwtracing/coresight/coresight-etm4x.c CS_LOCK(drvdata->base); base 499 drivers/hwtracing/coresight/coresight-etm4x.c control = readl_relaxed(drvdata->base + TRCVICTLR); base 583 drivers/hwtracing/coresight/coresight-etm4x.c CS_UNLOCK(drvdata->base); base 586 drivers/hwtracing/coresight/coresight-etm4x.c etmidr0 = readl_relaxed(drvdata->base + TRCIDR0); base 626 drivers/hwtracing/coresight/coresight-etm4x.c etmidr1 = readl_relaxed(drvdata->base + TRCIDR1); base 634 drivers/hwtracing/coresight/coresight-etm4x.c etmidr2 = readl_relaxed(drvdata->base + TRCIDR2); base 642 drivers/hwtracing/coresight/coresight-etm4x.c etmidr3 = readl_relaxed(drvdata->base + TRCIDR3); base 687 drivers/hwtracing/coresight/coresight-etm4x.c etmidr4 = readl_relaxed(drvdata->base + TRCIDR4); base 709 drivers/hwtracing/coresight/coresight-etm4x.c etmidr5 = readl_relaxed(drvdata->base + TRCIDR5); base 731 drivers/hwtracing/coresight/coresight-etm4x.c CS_LOCK(drvdata->base); base 1091 drivers/hwtracing/coresight/coresight-etm4x.c void __iomem *base; base 1105 drivers/hwtracing/coresight/coresight-etm4x.c base = devm_ioremap_resource(dev, res); base 1106 drivers/hwtracing/coresight/coresight-etm4x.c if (IS_ERR(base)) base 1107 drivers/hwtracing/coresight/coresight-etm4x.c return PTR_ERR(base); base 1109 drivers/hwtracing/coresight/coresight-etm4x.c drvdata->base = base; base 341 drivers/hwtracing/coresight/coresight-etm4x.h void __iomem *base; base 44 drivers/hwtracing/coresight/coresight-funnel.c void __iomem *base; base 56 drivers/hwtracing/coresight/coresight-funnel.c CS_UNLOCK(drvdata->base); base 58 drivers/hwtracing/coresight/coresight-funnel.c functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL); base 61 drivers/hwtracing/coresight/coresight-funnel.c rc = coresight_claim_device_unlocked(drvdata->base); base 69 drivers/hwtracing/coresight/coresight-funnel.c writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL); base 70 drivers/hwtracing/coresight/coresight-funnel.c writel_relaxed(drvdata->priority, drvdata->base + FUNNEL_PRICTL); base 72 drivers/hwtracing/coresight/coresight-funnel.c CS_LOCK(drvdata->base); base 86 drivers/hwtracing/coresight/coresight-funnel.c if (drvdata->base) base 105 drivers/hwtracing/coresight/coresight-funnel.c CS_UNLOCK(drvdata->base); base 107 drivers/hwtracing/coresight/coresight-funnel.c functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL); base 109 drivers/hwtracing/coresight/coresight-funnel.c writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL); base 113 drivers/hwtracing/coresight/coresight-funnel.c coresight_disclaim_device_unlocked(drvdata->base); base 115 drivers/hwtracing/coresight/coresight-funnel.c CS_LOCK(drvdata->base); base 127 drivers/hwtracing/coresight/coresight-funnel.c if (drvdata->base) base 176 drivers/hwtracing/coresight/coresight-funnel.c CS_UNLOCK(drvdata->base); base 177 drivers/hwtracing/coresight/coresight-funnel.c functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL); base 178 drivers/hwtracing/coresight/coresight-funnel.c CS_LOCK(drvdata->base); base 209 drivers/hwtracing/coresight/coresight-funnel.c void __iomem *base; base 238 drivers/hwtracing/coresight/coresight-funnel.c base = devm_ioremap_resource(dev, res); base 239 drivers/hwtracing/coresight/coresight-funnel.c if (IS_ERR(base)) { base 240 drivers/hwtracing/coresight/coresight-funnel.c ret = PTR_ERR(base); base 243 drivers/hwtracing/coresight/coresight-funnel.c drvdata->base = base; base 54 drivers/hwtracing/coresight/coresight-priv.h val = coresight_read_reg_pair(drvdata->base, \ base 37 drivers/hwtracing/coresight/coresight-replicator.c void __iomem *base; base 45 drivers/hwtracing/coresight/coresight-replicator.c CS_UNLOCK(drvdata->base); base 47 drivers/hwtracing/coresight/coresight-replicator.c if (!coresight_claim_device_unlocked(drvdata->base)) { base 48 drivers/hwtracing/coresight/coresight-replicator.c writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); base 49 drivers/hwtracing/coresight/coresight-replicator.c writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); base 50 drivers/hwtracing/coresight/coresight-replicator.c coresight_disclaim_device_unlocked(drvdata->base); base 53 drivers/hwtracing/coresight/coresight-replicator.c CS_LOCK(drvdata->base); base 61 drivers/hwtracing/coresight/coresight-replicator.c if (drvdata->base) base 83 drivers/hwtracing/coresight/coresight-replicator.c CS_UNLOCK(drvdata->base); base 85 drivers/hwtracing/coresight/coresight-replicator.c if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) && base 86 drivers/hwtracing/coresight/coresight-replicator.c (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff)) base 87 drivers/hwtracing/coresight/coresight-replicator.c rc = coresight_claim_device_unlocked(drvdata->base); base 91 drivers/hwtracing/coresight/coresight-replicator.c writel_relaxed(0x00, drvdata->base + reg); base 92 drivers/hwtracing/coresight/coresight-replicator.c CS_LOCK(drvdata->base); base 107 drivers/hwtracing/coresight/coresight-replicator.c if (drvdata->base) base 139 drivers/hwtracing/coresight/coresight-replicator.c CS_UNLOCK(drvdata->base); base 142 drivers/hwtracing/coresight/coresight-replicator.c writel_relaxed(0xff, drvdata->base + reg); base 144 drivers/hwtracing/coresight/coresight-replicator.c if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) && base 145 drivers/hwtracing/coresight/coresight-replicator.c (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff)) base 146 drivers/hwtracing/coresight/coresight-replicator.c coresight_disclaim_device_unlocked(drvdata->base); base 147 drivers/hwtracing/coresight/coresight-replicator.c CS_LOCK(drvdata->base); base 159 drivers/hwtracing/coresight/coresight-replicator.c if (drvdata->base) base 206 drivers/hwtracing/coresight/coresight-replicator.c void __iomem *base; base 233 drivers/hwtracing/coresight/coresight-replicator.c base = devm_ioremap_resource(dev, res); base 234 drivers/hwtracing/coresight/coresight-replicator.c if (IS_ERR(base)) { base 235 drivers/hwtracing/coresight/coresight-replicator.c ret = PTR_ERR(base); base 238 drivers/hwtracing/coresight/coresight-replicator.c drvdata->base = base; base 85 drivers/hwtracing/coresight/coresight-stm.c #define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \ base 106 drivers/hwtracing/coresight/coresight-stm.c void __iomem *base; base 132 drivers/hwtracing/coresight/coresight-stm.c void __iomem *base; base 151 drivers/hwtracing/coresight/coresight-stm.c CS_UNLOCK(drvdata->base); base 153 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR); base 154 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER); base 155 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER); base 158 drivers/hwtracing/coresight/coresight-stm.c drvdata->base + STMHEMCR); base 160 drivers/hwtracing/coresight/coresight-stm.c CS_LOCK(drvdata->base); base 165 drivers/hwtracing/coresight/coresight-stm.c CS_UNLOCK(drvdata->base); base 168 drivers/hwtracing/coresight/coresight-stm.c drvdata->base + STMSPTRIGCSR); base 169 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); base 170 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); base 172 drivers/hwtracing/coresight/coresight-stm.c CS_LOCK(drvdata->base); base 182 drivers/hwtracing/coresight/coresight-stm.c CS_UNLOCK(drvdata->base); base 185 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(0xFFF, drvdata->base + STMSYNCR); base 189 drivers/hwtracing/coresight/coresight-stm.c drvdata->base + STMTCSR); base 191 drivers/hwtracing/coresight/coresight-stm.c CS_LOCK(drvdata->base); base 221 drivers/hwtracing/coresight/coresight-stm.c CS_UNLOCK(drvdata->base); base 223 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(0x0, drvdata->base + STMHEMCR); base 224 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(0x0, drvdata->base + STMHEER); base 225 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(0x0, drvdata->base + STMHETER); base 227 drivers/hwtracing/coresight/coresight-stm.c CS_LOCK(drvdata->base); base 232 drivers/hwtracing/coresight/coresight-stm.c CS_UNLOCK(drvdata->base); base 234 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(0x0, drvdata->base + STMSPER); base 235 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR); base 237 drivers/hwtracing/coresight/coresight-stm.c CS_LOCK(drvdata->base); base 244 drivers/hwtracing/coresight/coresight-stm.c CS_UNLOCK(drvdata->base); base 246 drivers/hwtracing/coresight/coresight-stm.c val = readl_relaxed(drvdata->base + STMTCSR); base 248 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(val, drvdata->base + STMTCSR); base 250 drivers/hwtracing/coresight/coresight-stm.c CS_LOCK(drvdata->base); base 273 drivers/hwtracing/coresight/coresight-stm.c coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0); base 525 drivers/hwtracing/coresight/coresight-stm.c val = readl_relaxed(drvdata->base + STMSPSCR); base 548 drivers/hwtracing/coresight/coresight-stm.c CS_UNLOCK(drvdata->base); base 550 drivers/hwtracing/coresight/coresight-stm.c stmsper = readl_relaxed(drvdata->base + STMSPER); base 551 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(0x0, drvdata->base + STMSPER); base 552 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); base 553 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(stmsper, drvdata->base + STMSPER); base 554 drivers/hwtracing/coresight/coresight-stm.c CS_LOCK(drvdata->base); base 572 drivers/hwtracing/coresight/coresight-stm.c val = readl_relaxed(drvdata->base + STMSPER); base 595 drivers/hwtracing/coresight/coresight-stm.c CS_UNLOCK(drvdata->base); base 596 drivers/hwtracing/coresight/coresight-stm.c writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); base 597 drivers/hwtracing/coresight/coresight-stm.c CS_LOCK(drvdata->base); base 784 drivers/hwtracing/coresight/coresight-stm.c stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R); base 798 drivers/hwtracing/coresight/coresight-stm.c numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID); base 856 drivers/hwtracing/coresight/coresight-stm.c void __iomem *base; base 882 drivers/hwtracing/coresight/coresight-stm.c base = devm_ioremap_resource(dev, res); base 883 drivers/hwtracing/coresight/coresight-stm.c if (IS_ERR(base)) base 884 drivers/hwtracing/coresight/coresight-stm.c return PTR_ERR(base); base 885 drivers/hwtracing/coresight/coresight-stm.c drvdata->base = base; base 892 drivers/hwtracing/coresight/coresight-stm.c base = devm_ioremap_resource(dev, &ch_res); base 893 drivers/hwtracing/coresight/coresight-stm.c if (IS_ERR(base)) base 894 drivers/hwtracing/coresight/coresight-stm.c return PTR_ERR(base); base 895 drivers/hwtracing/coresight/coresight-stm.c drvdata->chs.base = base; base 21 drivers/hwtracing/coresight/coresight-tmc-etf.c CS_UNLOCK(drvdata->base); base 26 drivers/hwtracing/coresight/coresight-tmc-etf.c writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); base 30 drivers/hwtracing/coresight/coresight-tmc-etf.c drvdata->base + TMC_FFCR); base 32 drivers/hwtracing/coresight/coresight-tmc-etf.c writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); base 35 drivers/hwtracing/coresight/coresight-tmc-etf.c CS_LOCK(drvdata->base); base 40 drivers/hwtracing/coresight/coresight-tmc-etf.c int rc = coresight_claim_device(drvdata->base); base 55 drivers/hwtracing/coresight/coresight-tmc-etf.c lost = readl_relaxed(drvdata->base + TMC_STS) & TMC_STS_FULL; base 59 drivers/hwtracing/coresight/coresight-tmc-etf.c read_data = readl_relaxed(drvdata->base + TMC_RRD); base 74 drivers/hwtracing/coresight/coresight-tmc-etf.c CS_UNLOCK(drvdata->base); base 85 drivers/hwtracing/coresight/coresight-tmc-etf.c CS_LOCK(drvdata->base); base 91 drivers/hwtracing/coresight/coresight-tmc-etf.c coresight_disclaim_device(drvdata->base); base 96 drivers/hwtracing/coresight/coresight-tmc-etf.c CS_UNLOCK(drvdata->base); base 101 drivers/hwtracing/coresight/coresight-tmc-etf.c writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE); base 103 drivers/hwtracing/coresight/coresight-tmc-etf.c drvdata->base + TMC_FFCR); base 104 drivers/hwtracing/coresight/coresight-tmc-etf.c writel_relaxed(0x0, drvdata->base + TMC_BUFWM); base 107 drivers/hwtracing/coresight/coresight-tmc-etf.c CS_LOCK(drvdata->base); base 112 drivers/hwtracing/coresight/coresight-tmc-etf.c int rc = coresight_claim_device(drvdata->base); base 123 drivers/hwtracing/coresight/coresight-tmc-etf.c CS_UNLOCK(drvdata->base); base 127 drivers/hwtracing/coresight/coresight-tmc-etf.c coresight_disclaim_device_unlocked(drvdata->base); base 128 drivers/hwtracing/coresight/coresight-tmc-etf.c CS_LOCK(drvdata->base); base 467 drivers/hwtracing/coresight/coresight-tmc-etf.c CS_UNLOCK(drvdata->base); base 478 drivers/hwtracing/coresight/coresight-tmc-etf.c status = readl_relaxed(drvdata->base + TMC_STS); base 527 drivers/hwtracing/coresight/coresight-tmc-etf.c *buf_ptr = readl_relaxed(drvdata->base + TMC_RRD); base 552 drivers/hwtracing/coresight/coresight-tmc-etf.c CS_LOCK(drvdata->base); base 600 drivers/hwtracing/coresight/coresight-tmc-etf.c mode = readl_relaxed(drvdata->base + TMC_MODE); base 643 drivers/hwtracing/coresight/coresight-tmc-etf.c mode = readl_relaxed(drvdata->base + TMC_MODE); base 412 drivers/hwtracing/coresight/coresight-tmc-etr.c unsigned long base; base 417 drivers/hwtracing/coresight/coresight-tmc-etr.c base = (unsigned long)sg_table->table_vaddr; base 420 drivers/hwtracing/coresight/coresight-tmc-etr.c base = (unsigned long)sg_table->data_vaddr; base 426 drivers/hwtracing/coresight/coresight-tmc-etr.c return base + offset; base 930 drivers/hwtracing/coresight/coresight-tmc-etr.c status = readl_relaxed(drvdata->base + TMC_STS); base 956 drivers/hwtracing/coresight/coresight-tmc-etr.c CS_UNLOCK(drvdata->base); base 961 drivers/hwtracing/coresight/coresight-tmc-etr.c writel_relaxed(etr_buf->size / 4, drvdata->base + TMC_RSZ); base 962 drivers/hwtracing/coresight/coresight-tmc-etr.c writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); base 964 drivers/hwtracing/coresight/coresight-tmc-etr.c axictl = readl_relaxed(drvdata->base + TMC_AXICTL); base 977 drivers/hwtracing/coresight/coresight-tmc-etr.c writel_relaxed(axictl, drvdata->base + TMC_AXICTL); base 987 drivers/hwtracing/coresight/coresight-tmc-etr.c sts = readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL; base 988 drivers/hwtracing/coresight/coresight-tmc-etr.c writel_relaxed(sts, drvdata->base + TMC_STS); base 994 drivers/hwtracing/coresight/coresight-tmc-etr.c drvdata->base + TMC_FFCR); base 995 drivers/hwtracing/coresight/coresight-tmc-etr.c writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); base 998 drivers/hwtracing/coresight/coresight-tmc-etr.c CS_LOCK(drvdata->base); base 1024 drivers/hwtracing/coresight/coresight-tmc-etr.c rc = coresight_claim_device(drvdata->base); base 1097 drivers/hwtracing/coresight/coresight-tmc-etr.c CS_UNLOCK(drvdata->base); base 1109 drivers/hwtracing/coresight/coresight-tmc-etr.c CS_LOCK(drvdata->base); base 1118 drivers/hwtracing/coresight/coresight-tmc-etr.c coresight_disclaim_device(drvdata->base); base 1500 drivers/hwtracing/coresight/coresight-tmc-etr.c CS_UNLOCK(drvdata->base); base 1505 drivers/hwtracing/coresight/coresight-tmc-etr.c CS_LOCK(drvdata->base); base 37 drivers/hwtracing/coresight/coresight-tmc.c if (coresight_timeout(drvdata->base, base 48 drivers/hwtracing/coresight/coresight-tmc.c ffcr = readl_relaxed(drvdata->base + TMC_FFCR); base 50 drivers/hwtracing/coresight/coresight-tmc.c writel_relaxed(ffcr, drvdata->base + TMC_FFCR); base 52 drivers/hwtracing/coresight/coresight-tmc.c writel_relaxed(ffcr, drvdata->base + TMC_FFCR); base 54 drivers/hwtracing/coresight/coresight-tmc.c if (coresight_timeout(drvdata->base, base 65 drivers/hwtracing/coresight/coresight-tmc.c writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL); base 70 drivers/hwtracing/coresight/coresight-tmc.c writel_relaxed(0x0, drvdata->base + TMC_CTL); base 377 drivers/hwtracing/coresight/coresight-tmc.c u32 auth = readl_relaxed(drvdata->base + TMC_AUTHSTATUS); base 438 drivers/hwtracing/coresight/coresight-tmc.c void __iomem *base; base 454 drivers/hwtracing/coresight/coresight-tmc.c base = devm_ioremap_resource(dev, res); base 455 drivers/hwtracing/coresight/coresight-tmc.c if (IS_ERR(base)) { base 456 drivers/hwtracing/coresight/coresight-tmc.c ret = PTR_ERR(base); base 460 drivers/hwtracing/coresight/coresight-tmc.c drvdata->base = base; base 464 drivers/hwtracing/coresight/coresight-tmc.c devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); base 473 drivers/hwtracing/coresight/coresight-tmc.c drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; base 189 drivers/hwtracing/coresight/coresight-tmc.h void __iomem *base; base 280 drivers/hwtracing/coresight/coresight-tmc.h return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \ base 285 drivers/hwtracing/coresight/coresight-tmc.h coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \ base 58 drivers/hwtracing/coresight/coresight-tpiu.c void __iomem *base; base 65 drivers/hwtracing/coresight/coresight-tpiu.c CS_UNLOCK(drvdata->base); base 69 drivers/hwtracing/coresight/coresight-tpiu.c CS_LOCK(drvdata->base); base 84 drivers/hwtracing/coresight/coresight-tpiu.c CS_UNLOCK(drvdata->base); base 87 drivers/hwtracing/coresight/coresight-tpiu.c writel_relaxed(FFCR_STOP_FI, drvdata->base + TPIU_FFCR); base 89 drivers/hwtracing/coresight/coresight-tpiu.c writel_relaxed(FFCR_STOP_FI | FFCR_FON_MAN, drvdata->base + TPIU_FFCR); base 91 drivers/hwtracing/coresight/coresight-tpiu.c coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0); base 93 drivers/hwtracing/coresight/coresight-tpiu.c coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1); base 95 drivers/hwtracing/coresight/coresight-tpiu.c CS_LOCK(drvdata->base); base 123 drivers/hwtracing/coresight/coresight-tpiu.c void __iomem *base; base 147 drivers/hwtracing/coresight/coresight-tpiu.c base = devm_ioremap_resource(dev, res); base 148 drivers/hwtracing/coresight/coresight-tpiu.c if (IS_ERR(base)) base 149 drivers/hwtracing/coresight/coresight-tpiu.c return PTR_ERR(base); base 151 drivers/hwtracing/coresight/coresight-tpiu.c drvdata->base = base; base 133 drivers/hwtracing/coresight/coresight.c static inline u32 coresight_read_claim_tags(void __iomem *base) base 135 drivers/hwtracing/coresight/coresight.c return readl_relaxed(base + CORESIGHT_CLAIMCLR); base 138 drivers/hwtracing/coresight/coresight.c static inline bool coresight_is_claimed_self_hosted(void __iomem *base) base 140 drivers/hwtracing/coresight/coresight.c return coresight_read_claim_tags(base) == CORESIGHT_CLAIM_SELF_HOSTED; base 143 drivers/hwtracing/coresight/coresight.c static inline bool coresight_is_claimed_any(void __iomem *base) base 145 drivers/hwtracing/coresight/coresight.c return coresight_read_claim_tags(base) != 0; base 148 drivers/hwtracing/coresight/coresight.c static inline void coresight_set_claim_tags(void __iomem *base) base 150 drivers/hwtracing/coresight/coresight.c writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMSET); base 154 drivers/hwtracing/coresight/coresight.c static inline void coresight_clear_claim_tags(void __iomem *base) base 156 drivers/hwtracing/coresight/coresight.c writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMCLR); base 170 drivers/hwtracing/coresight/coresight.c int coresight_claim_device_unlocked(void __iomem *base) base 172 drivers/hwtracing/coresight/coresight.c if (coresight_is_claimed_any(base)) base 175 drivers/hwtracing/coresight/coresight.c coresight_set_claim_tags(base); base 176 drivers/hwtracing/coresight/coresight.c if (coresight_is_claimed_self_hosted(base)) base 179 drivers/hwtracing/coresight/coresight.c coresight_clear_claim_tags(base); base 183 drivers/hwtracing/coresight/coresight.c int coresight_claim_device(void __iomem *base) base 187 drivers/hwtracing/coresight/coresight.c CS_UNLOCK(base); base 188 drivers/hwtracing/coresight/coresight.c rc = coresight_claim_device_unlocked(base); base 189 drivers/hwtracing/coresight/coresight.c CS_LOCK(base); base 198 drivers/hwtracing/coresight/coresight.c void coresight_disclaim_device_unlocked(void __iomem *base) base 201 drivers/hwtracing/coresight/coresight.c if (coresight_is_claimed_self_hosted(base)) base 202 drivers/hwtracing/coresight/coresight.c coresight_clear_claim_tags(base); base 212 drivers/hwtracing/coresight/coresight.c void coresight_disclaim_device(void __iomem *base) base 214 drivers/hwtracing/coresight/coresight.c CS_UNLOCK(base); base 215 drivers/hwtracing/coresight/coresight.c coresight_disclaim_device_unlocked(base); base 216 drivers/hwtracing/coresight/coresight.c CS_LOCK(base); base 52 drivers/hwtracing/intel_th/gth.c void __iomem *base; base 68 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); base 71 drivers/hwtracing/intel_th/gth.c iowrite32(val, gth->base + reg); base 80 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); base 94 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); base 97 drivers/hwtracing/intel_th/gth.c iowrite32(val, gth->base + reg); base 106 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); base 135 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); base 139 drivers/hwtracing/intel_th/gth.c iowrite32(val, gth->base + reg); base 283 drivers/hwtracing/intel_th/gth.c reg = ioread32(gth->base + REG_GTH_SCRPD0); base 289 drivers/hwtracing/intel_th/gth.c iowrite32(reg, gth->base + REG_GTH_SCRPD0); base 301 drivers/hwtracing/intel_th/gth.c iowrite32(0, gth->base + REG_GTH_DESTOVR); base 305 drivers/hwtracing/intel_th/gth.c iowrite32(0, gth->base + REG_GTH_SWDEST0 + i * 4); base 308 drivers/hwtracing/intel_th/gth.c iowrite32(0, gth->base + REG_GTH_SCR); base 309 drivers/hwtracing/intel_th/gth.c iowrite32(0xfc, gth->base + REG_GTH_SCR2); base 312 drivers/hwtracing/intel_th/gth.c iowrite32(CTS_EVENT_ENABLE_IF_ANYTHING, gth->base + REG_CTS_C0S0_EN); base 314 drivers/hwtracing/intel_th/gth.c CTS_ACTION_CONTROL_TRIGGER, gth->base + REG_CTS_C0S0_ACT); base 485 drivers/hwtracing/intel_th/gth.c iowrite32(0, gth->base + REG_GTH_SCR); base 486 drivers/hwtracing/intel_th/gth.c iowrite32(scr2, gth->base + REG_GTH_SCR2); base 491 drivers/hwtracing/intel_th/gth.c reg = ioread32(gth->base + REG_GTH_STAT); base 504 drivers/hwtracing/intel_th/gth.c iowrite32(0xfc, gth->base + REG_GTH_SCR2); base 522 drivers/hwtracing/intel_th/gth.c iowrite32(scr, gth->base + REG_GTH_SCR); base 523 drivers/hwtracing/intel_th/gth.c iowrite32(0, gth->base + REG_GTH_SCR2); base 553 drivers/hwtracing/intel_th/gth.c reg = ioread32(gth->base + REG_GTH_SCRPD0); base 555 drivers/hwtracing/intel_th/gth.c iowrite32(reg, gth->base + REG_GTH_SCRPD0); base 562 drivers/hwtracing/intel_th/gth.c reg = ioread32(gth->base + REG_TSCU_TSUCTRL); base 564 drivers/hwtracing/intel_th/gth.c iowrite32(reg, gth->base + REG_TSCU_TSUCTRL); base 595 drivers/hwtracing/intel_th/gth.c scrpd = ioread32(gth->base + REG_GTH_SCRPD0); base 597 drivers/hwtracing/intel_th/gth.c iowrite32(scrpd, gth->base + REG_GTH_SCRPD0); base 618 drivers/hwtracing/intel_th/gth.c iowrite32(0, gth->base + REG_CTS_CTL); base 619 drivers/hwtracing/intel_th/gth.c iowrite32(CTS_CTL_SEQUENCER_ENABLE, gth->base + REG_CTS_CTL); base 623 drivers/hwtracing/intel_th/gth.c reg = ioread32(gth->base + REG_CTS_STAT); base 630 drivers/hwtracing/intel_th/gth.c iowrite32(0, gth->base + REG_CTS_CTL); base 735 drivers/hwtracing/intel_th/gth.c void __iomem *base; base 742 drivers/hwtracing/intel_th/gth.c base = devm_ioremap(dev, res->start, resource_size(res)); base 743 drivers/hwtracing/intel_th/gth.c if (!base) base 751 drivers/hwtracing/intel_th/gth.c gth->base = base; base 144 drivers/hwtracing/intel_th/msu.c void *base; base 936 drivers/hwtracing/intel_th/msu.c msc->base = page_address(page); base 964 drivers/hwtracing/intel_th/msu.c struct page *page = virt_to_page(msc->base + off); base 986 drivers/hwtracing/intel_th/msu.c return virt_to_page(msc->base + (pgoff << PAGE_SHIFT)); base 1102 drivers/hwtracing/intel_th/msu.c msc->base = msc_win_base(win); base 1147 drivers/hwtracing/intel_th/msu.c msc->base = NULL; base 1468 drivers/hwtracing/intel_th/msu.c if (copy_to_user(buf, msc->base + start, tocopy)) base 1479 drivers/hwtracing/intel_th/msu.c if (copy_to_user(buf, msc->base + start, tocopy)) base 1488 drivers/hwtracing/intel_th/msu.c if (copy_to_user(buf, msc->base + start, rem)) base 1694 drivers/hwtracing/intel_th/msu.c msc->base = msc_win_base(msc->cur_win); base 2067 drivers/hwtracing/intel_th/msu.c void __iomem *base; base 2074 drivers/hwtracing/intel_th/msu.c base = devm_ioremap(dev, res->start, resource_size(res)); base 2075 drivers/hwtracing/intel_th/msu.c if (!base) base 2089 drivers/hwtracing/intel_th/msu.c msc->reg_base = base + msc->index * 0x100; base 2090 drivers/hwtracing/intel_th/msu.c msc->msu_base = base; base 23 drivers/hwtracing/intel_th/pti.c void __iomem *base; base 162 drivers/hwtracing/intel_th/pti.c iowrite32(ctl, pti->base + REG_PTI_CTL); base 175 drivers/hwtracing/intel_th/pti.c iowrite32(0, pti->base + REG_PTI_CTL); base 180 drivers/hwtracing/intel_th/pti.c u32 ctl = ioread32(pti->base + REG_PTI_CTL); base 206 drivers/hwtracing/intel_th/pti.c void __iomem *base; base 212 drivers/hwtracing/intel_th/pti.c base = devm_ioremap(dev, res->start, resource_size(res)); base 213 drivers/hwtracing/intel_th/pti.c if (!base) base 221 drivers/hwtracing/intel_th/pti.c pti->base = base; base 22 drivers/hwtracing/intel_th/sth.c void __iomem *base; base 96 drivers/hwtracing/intel_th/sth.c writeb_relaxed(*payload, sth->base + reg); base 173 drivers/hwtracing/intel_th/sth.c reg = ioread32(sth->base + REG_STH_STHCAP1); base 176 drivers/hwtracing/intel_th/sth.c reg = ioread32(sth->base + REG_STH_STHCAP0); base 193 drivers/hwtracing/intel_th/sth.c void __iomem *base, *channels; base 200 drivers/hwtracing/intel_th/sth.c base = devm_ioremap(dev, res->start, resource_size(res)); base 201 drivers/hwtracing/intel_th/sth.c if (!base) base 217 drivers/hwtracing/intel_th/sth.c sth->base = base; base 76 drivers/i2c/busses/i2c-altera.c void __iomem *base; base 101 drivers/i2c/busses/i2c-altera.c int_en = readl(idev->base + ALTR_I2C_ISER); base 107 drivers/i2c/busses/i2c-altera.c writel(idev->isr_mask, idev->base + ALTR_I2C_ISER); base 114 drivers/i2c/busses/i2c-altera.c u32 int_en = readl(idev->base + ALTR_I2C_ISR); base 116 drivers/i2c/busses/i2c-altera.c writel(int_en | mask, idev->base + ALTR_I2C_ISR); base 121 drivers/i2c/busses/i2c-altera.c u32 tmp = readl(idev->base + ALTR_I2C_CTRL); base 123 drivers/i2c/busses/i2c-altera.c writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL); base 128 drivers/i2c/busses/i2c-altera.c u32 tmp = readl(idev->base + ALTR_I2C_CTRL); base 130 drivers/i2c/busses/i2c-altera.c writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL); base 141 drivers/i2c/busses/i2c-altera.c writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD); base 163 drivers/i2c/busses/i2c-altera.c writel(tmp, idev->base + ALTR_I2C_CTRL); base 172 drivers/i2c/busses/i2c-altera.c writel(t_high, idev->base + ALTR_I2C_SCL_HIGH); base 174 drivers/i2c/busses/i2c-altera.c writel(t_low, idev->base + ALTR_I2C_SCL_LOW); base 176 drivers/i2c/busses/i2c-altera.c writel(3 * clk_mhz / 10, idev->base + ALTR_I2C_SDA_HOLD); base 192 drivers/i2c/busses/i2c-altera.c writel(data, idev->base + ALTR_I2C_TFR_CMD); base 201 drivers/i2c/busses/i2c-altera.c size_t rx_fifo_avail = readl(idev->base + ALTR_I2C_RX_FIFO_LVL); base 205 drivers/i2c/busses/i2c-altera.c *idev->buf++ = readl(idev->base + ALTR_I2C_RX_DATA); base 217 drivers/i2c/busses/i2c-altera.c size_t tx_fifo_avail = idev->fifo_size - readl(idev->base + base 236 drivers/i2c/busses/i2c-altera.c idev->isr_status = readl(idev->base + ALTR_I2C_ISR) & idev->isr_mask; base 296 drivers/i2c/busses/i2c-altera.c ret = readl_poll_timeout_atomic(idev->base + ALTR_I2C_STATUS, base 330 drivers/i2c/busses/i2c-altera.c readl(idev->base + ALTR_I2C_RX_DATA); base 331 drivers/i2c/busses/i2c-altera.c } while (readl(idev->base + ALTR_I2C_RX_FIFO_LVL)); base 333 drivers/i2c/busses/i2c-altera.c writel(ALTR_I2C_TFR_CMD_STA | addr, idev->base + ALTR_I2C_TFR_CMD); base 351 drivers/i2c/busses/i2c-altera.c value = readl(idev->base + ALTR_I2C_STATUS) & ALTR_I2C_STAT_CORE; base 400 drivers/i2c/busses/i2c-altera.c idev->base = devm_ioremap_resource(&pdev->dev, res); base 401 drivers/i2c/busses/i2c-altera.c if (IS_ERR(idev->base)) base 402 drivers/i2c/busses/i2c-altera.c return PTR_ERR(idev->base); base 26 drivers/i2c/busses/i2c-amd8111.c int base; base 72 drivers/i2c/busses/i2c-amd8111.c while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout) base 88 drivers/i2c/busses/i2c-amd8111.c while ((~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF) && --timeout) base 108 drivers/i2c/busses/i2c-amd8111.c outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD); base 113 drivers/i2c/busses/i2c-amd8111.c outb(address, smbus->base + AMD_EC_DATA); base 118 drivers/i2c/busses/i2c-amd8111.c *data = inb(smbus->base + AMD_EC_DATA); base 131 drivers/i2c/busses/i2c-amd8111.c outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD); base 136 drivers/i2c/busses/i2c-amd8111.c outb(address, smbus->base + AMD_EC_DATA); base 141 drivers/i2c/busses/i2c-amd8111.c outb(data, smbus->base + AMD_EC_DATA); base 435 drivers/i2c/busses/i2c-amd8111.c smbus->base = pci_resource_start(dev, 0); base 444 drivers/i2c/busses/i2c-amd8111.c if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) { base 451 drivers/i2c/busses/i2c-amd8111.c "SMBus2 AMD8111 adapter at %04x", smbus->base); base 468 drivers/i2c/busses/i2c-amd8111.c release_region(smbus->base, smbus->size); base 479 drivers/i2c/busses/i2c-amd8111.c release_region(smbus->base, smbus->size); base 145 drivers/i2c/busses/i2c-aspeed.c void __iomem *base; base 181 drivers/i2c/busses/i2c-aspeed.c command = readl(bus->base + ASPEED_I2C_CMD_REG); base 191 drivers/i2c/busses/i2c-aspeed.c writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG); base 203 drivers/i2c/busses/i2c-aspeed.c else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & base 214 drivers/i2c/busses/i2c-aspeed.c bus->base + ASPEED_I2C_CMD_REG); base 226 drivers/i2c/busses/i2c-aspeed.c else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & base 252 drivers/i2c/busses/i2c-aspeed.c command = readl(bus->base + ASPEED_I2C_CMD_REG); base 269 drivers/i2c/busses/i2c-aspeed.c value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; base 299 drivers/i2c/busses/i2c-aspeed.c writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG); base 300 drivers/i2c/busses/i2c-aspeed.c writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG); base 310 drivers/i2c/busses/i2c-aspeed.c writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG); base 311 drivers/i2c/busses/i2c-aspeed.c writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG); base 367 drivers/i2c/busses/i2c-aspeed.c writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG); base 368 drivers/i2c/busses/i2c-aspeed.c writel(command, bus->base + ASPEED_I2C_CMD_REG); base 375 drivers/i2c/busses/i2c-aspeed.c writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG); base 464 drivers/i2c/busses/i2c-aspeed.c writel(readl(bus->base + ASPEED_I2C_CMD_REG) & base 466 drivers/i2c/busses/i2c-aspeed.c bus->base + ASPEED_I2C_CMD_REG); base 512 drivers/i2c/busses/i2c-aspeed.c bus->base + ASPEED_I2C_BYTE_BUF_REG); base 514 drivers/i2c/busses/i2c-aspeed.c bus->base + ASPEED_I2C_CMD_REG); base 531 drivers/i2c/busses/i2c-aspeed.c recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; base 550 drivers/i2c/busses/i2c-aspeed.c writel(command, bus->base + ASPEED_I2C_CMD_REG); base 602 drivers/i2c/busses/i2c-aspeed.c irq_received = readl(bus->base + ASPEED_I2C_INTR_STS_REG); base 605 drivers/i2c/busses/i2c-aspeed.c bus->base + ASPEED_I2C_INTR_STS_REG); base 606 drivers/i2c/busses/i2c-aspeed.c readl(bus->base + ASPEED_I2C_INTR_STS_REG); base 651 drivers/i2c/busses/i2c-aspeed.c bus->base + ASPEED_I2C_INTR_STS_REG); base 652 drivers/i2c/busses/i2c-aspeed.c readl(bus->base + ASPEED_I2C_INTR_STS_REG); base 669 drivers/i2c/busses/i2c-aspeed.c (readl(bus->base + ASPEED_I2C_CMD_REG) & base 698 drivers/i2c/busses/i2c-aspeed.c (readl(bus->base + ASPEED_I2C_CMD_REG) & base 729 drivers/i2c/busses/i2c-aspeed.c addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG); base 732 drivers/i2c/busses/i2c-aspeed.c writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG); base 735 drivers/i2c/busses/i2c-aspeed.c func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG); base 737 drivers/i2c/busses/i2c-aspeed.c writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG); base 773 drivers/i2c/busses/i2c-aspeed.c func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG); base 775 drivers/i2c/busses/i2c-aspeed.c writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG); base 884 drivers/i2c/busses/i2c-aspeed.c clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1); base 889 drivers/i2c/busses/i2c-aspeed.c writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1); base 890 drivers/i2c/busses/i2c-aspeed.c writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2); base 903 drivers/i2c/busses/i2c-aspeed.c writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); base 915 drivers/i2c/busses/i2c-aspeed.c writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg, base 916 drivers/i2c/busses/i2c-aspeed.c bus->base + ASPEED_I2C_FUN_CTRL_REG); base 925 drivers/i2c/busses/i2c-aspeed.c writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG); base 939 drivers/i2c/busses/i2c-aspeed.c writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); base 940 drivers/i2c/busses/i2c-aspeed.c writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); base 975 drivers/i2c/busses/i2c-aspeed.c bus->base = devm_ioremap_resource(&pdev->dev, res); base 976 drivers/i2c/busses/i2c-aspeed.c if (IS_ERR(bus->base)) base 977 drivers/i2c/busses/i2c-aspeed.c return PTR_ERR(bus->base); base 1023 drivers/i2c/busses/i2c-aspeed.c writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); base 1024 drivers/i2c/busses/i2c-aspeed.c writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); base 1059 drivers/i2c/busses/i2c-aspeed.c writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); base 1060 drivers/i2c/busses/i2c-aspeed.c writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); base 31 drivers/i2c/busses/i2c-at91-core.c return readl_relaxed(dev->base + reg); base 36 drivers/i2c/busses/i2c-at91-core.c writel_relaxed(val, dev->base + reg); base 218 drivers/i2c/busses/i2c-at91-core.c dev->base = devm_ioremap_resource(&pdev->dev, mem); base 219 drivers/i2c/busses/i2c-at91-core.c if (IS_ERR(dev->base)) base 220 drivers/i2c/busses/i2c-at91-core.c return PTR_ERR(dev->base); base 122 drivers/i2c/busses/i2c-at91-master.c writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR); base 245 drivers/i2c/busses/i2c-at91-master.c *dev->buf = readb_relaxed(dev->base + AT91_TWI_RHR); base 30 drivers/i2c/busses/i2c-at91-slave.c writeb_relaxed(value, dev->base + AT91_TWI_THR); base 45 drivers/i2c/busses/i2c-at91-slave.c writeb_relaxed(value, dev->base + AT91_TWI_THR); base 50 drivers/i2c/busses/i2c-at91-slave.c value = readb_relaxed(dev->base + AT91_TWI_RHR); base 126 drivers/i2c/busses/i2c-at91.h void __iomem *base; base 136 drivers/i2c/busses/i2c-axxia.c void __iomem *base; base 156 drivers/i2c/busses/i2c-axxia.c int_en = readl(idev->base + MST_INT_ENABLE); base 157 drivers/i2c/busses/i2c-axxia.c writel(int_en & ~mask, idev->base + MST_INT_ENABLE); base 164 drivers/i2c/busses/i2c-axxia.c int_en = readl(idev->base + MST_INT_ENABLE); base 165 drivers/i2c/busses/i2c-axxia.c writel(int_en | mask, idev->base + MST_INT_ENABLE); base 190 drivers/i2c/busses/i2c-axxia.c writel(0x01, idev->base + SOFT_RESET); base 192 drivers/i2c/busses/i2c-axxia.c while (readl(idev->base + SOFT_RESET) & 1) { base 200 drivers/i2c/busses/i2c-axxia.c writel(0x1, idev->base + GLOBAL_CONTROL); base 215 drivers/i2c/busses/i2c-axxia.c writel(t_high, idev->base + SCL_HIGH_PERIOD); base 217 drivers/i2c/busses/i2c-axxia.c writel(t_low, idev->base + SCL_LOW_PERIOD); base 219 drivers/i2c/busses/i2c-axxia.c writel(t_setup, idev->base + SDA_SETUP_TIME); base 221 drivers/i2c/busses/i2c-axxia.c writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME); base 223 drivers/i2c/busses/i2c-axxia.c writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN); base 238 drivers/i2c/busses/i2c-axxia.c writel(prescale, idev->base + TIMER_CLOCK_DIV); base 240 drivers/i2c/busses/i2c-axxia.c writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL); base 246 drivers/i2c/busses/i2c-axxia.c writel(0x01, idev->base + INTERRUPT_ENABLE); base 273 drivers/i2c/busses/i2c-axxia.c size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO); base 277 drivers/i2c/busses/i2c-axxia.c int c = readl(idev->base + MST_DATA); base 290 drivers/i2c/busses/i2c-axxia.c writel(msg->len, idev->base + MST_RX_XFER); base 305 drivers/i2c/busses/i2c-axxia.c size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO); base 310 drivers/i2c/busses/i2c-axxia.c writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA); base 317 drivers/i2c/busses/i2c-axxia.c u32 fifo_status = readl(idev->base + SLV_RX_FIFO); base 327 drivers/i2c/busses/i2c-axxia.c val = readl(idev->base + SLV_DATA); base 331 drivers/i2c/busses/i2c-axxia.c readl(idev->base + SLV_DATA); /* dummy read */ base 335 drivers/i2c/busses/i2c-axxia.c readl(idev->base + SLV_DATA); /* dummy read */ base 340 drivers/i2c/busses/i2c-axxia.c u32 status = readl(idev->base + SLV_INT_STATUS); base 349 drivers/i2c/busses/i2c-axxia.c writel(val, idev->base + SLV_DATA); base 353 drivers/i2c/busses/i2c-axxia.c writel(val, idev->base + SLV_DATA); base 358 drivers/i2c/busses/i2c-axxia.c writel(INT_SLV, idev->base + INTERRUPT_STATUS); base 368 drivers/i2c/busses/i2c-axxia.c status = readl(idev->base + INTERRUPT_STATUS); base 376 drivers/i2c/busses/i2c-axxia.c status = readl(idev->base + MST_INT_STATUS); base 405 drivers/i2c/busses/i2c-axxia.c readl(idev->base + MST_RX_BYTES_XFRD), base 406 drivers/i2c/busses/i2c-axxia.c readl(idev->base + MST_RX_XFER), base 407 drivers/i2c/busses/i2c-axxia.c readl(idev->base + MST_TX_BYTES_XFRD), base 408 drivers/i2c/busses/i2c-axxia.c readl(idev->base + MST_TX_XFER)); base 431 drivers/i2c/busses/i2c-axxia.c writel(INT_MST, idev->base + INTERRUPT_STATUS); base 458 drivers/i2c/busses/i2c-axxia.c writel(addr_1, idev->base + MST_ADDR_1); base 459 drivers/i2c/busses/i2c-axxia.c writel(addr_2, idev->base + MST_ADDR_2); base 471 drivers/i2c/busses/i2c-axxia.c if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0) base 487 drivers/i2c/busses/i2c-axxia.c writel(msgs[0].len, idev->base + MST_TX_XFER); base 488 drivers/i2c/busses/i2c-axxia.c writel(rlen, idev->base + MST_RX_XFER); base 497 drivers/i2c/busses/i2c-axxia.c writel(CMD_SEQUENCE, idev->base + MST_COMMAND); base 508 drivers/i2c/busses/i2c-axxia.c } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) { base 551 drivers/i2c/busses/i2c-axxia.c writel(rx_xfer, idev->base + MST_RX_XFER); base 552 drivers/i2c/busses/i2c-axxia.c writel(tx_xfer, idev->base + MST_TX_XFER); base 559 drivers/i2c/busses/i2c-axxia.c wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL)); base 561 drivers/i2c/busses/i2c-axxia.c writel(wt_value, idev->base + WAIT_TIMER_CONTROL); base 567 drivers/i2c/busses/i2c-axxia.c writel(CMD_MANUAL, idev->base + MST_COMMAND); base 570 drivers/i2c/busses/i2c-axxia.c writel(CMD_AUTO, idev->base + MST_COMMAND); base 574 drivers/i2c/busses/i2c-axxia.c writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL); base 583 drivers/i2c/busses/i2c-axxia.c if (readl(idev->base + MST_COMMAND) & CMD_BUSY) base 638 drivers/i2c/busses/i2c-axxia.c return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS); base 647 drivers/i2c/busses/i2c-axxia.c tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC; base 650 drivers/i2c/busses/i2c-axxia.c writel(tmp, idev->base + I2C_BUS_MONITOR); base 657 drivers/i2c/busses/i2c-axxia.c return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS); base 686 drivers/i2c/busses/i2c-axxia.c writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, idev->base + GLOBAL_CONTROL); base 687 drivers/i2c/busses/i2c-axxia.c writel(INT_MST | INT_SLV, idev->base + INTERRUPT_ENABLE); base 694 drivers/i2c/busses/i2c-axxia.c writel(SLV_RX_ACSA1, idev->base + SLV_RX_CTL); base 695 drivers/i2c/busses/i2c-axxia.c writel(dec_ctl, idev->base + SLV_ADDR_DEC_CTL); base 696 drivers/i2c/busses/i2c-axxia.c writel(slave->addr, idev->base + SLV_ADDR_1); base 701 drivers/i2c/busses/i2c-axxia.c writel(slv_int_mask, idev->base + SLV_INT_ENABLE); base 711 drivers/i2c/busses/i2c-axxia.c writel(GLOBAL_MST_EN, idev->base + GLOBAL_CONTROL); base 712 drivers/i2c/busses/i2c-axxia.c writel(INT_MST, idev->base + INTERRUPT_ENABLE); base 738 drivers/i2c/busses/i2c-axxia.c void __iomem *base; base 746 drivers/i2c/busses/i2c-axxia.c base = devm_ioremap_resource(&pdev->dev, res); base 747 drivers/i2c/busses/i2c-axxia.c if (IS_ERR(base)) base 748 drivers/i2c/busses/i2c-axxia.c return PTR_ERR(base); base 762 drivers/i2c/busses/i2c-axxia.c idev->base = base; base 183 drivers/i2c/busses/i2c-bcm-iproc.c void __iomem *base; base 232 drivers/i2c/busses/i2c-bcm-iproc.c val = readl(iproc_i2c->base + offset); base 235 drivers/i2c/busses/i2c-bcm-iproc.c val = readl(iproc_i2c->base + offset); base 248 drivers/i2c/busses/i2c-bcm-iproc.c writel(val, iproc_i2c->base + offset); base 251 drivers/i2c/busses/i2c-bcm-iproc.c writel(val, iproc_i2c->base + offset); base 872 drivers/i2c/busses/i2c-bcm-iproc.c iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res); base 873 drivers/i2c/busses/i2c-bcm-iproc.c if (IS_ERR(iproc_i2c->base)) base 874 drivers/i2c/busses/i2c-bcm-iproc.c return PTR_ERR(iproc_i2c->base); base 157 drivers/i2c/busses/i2c-bcm-kona.c void __iomem *base; base 178 drivers/i2c/busses/i2c-bcm-kona.c dev->base + CS_OFFSET); base 185 drivers/i2c/busses/i2c-bcm-kona.c dev->base + CS_OFFSET); base 192 drivers/i2c/busses/i2c-bcm-kona.c dev->base + CS_OFFSET); base 198 drivers/i2c/busses/i2c-bcm-kona.c dev->base + CS_OFFSET); base 208 drivers/i2c/busses/i2c-bcm-kona.c writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, base 209 drivers/i2c/busses/i2c-bcm-kona.c dev->base + CLKEN_OFFSET); base 214 drivers/i2c/busses/i2c-bcm-kona.c writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, base 215 drivers/i2c/busses/i2c-bcm-kona.c dev->base + CLKEN_OFFSET); base 221 drivers/i2c/busses/i2c-bcm-kona.c uint32_t status = readl(dev->base + ISR_OFFSET); base 229 drivers/i2c/busses/i2c-bcm-kona.c dev->base + TXFCR_OFFSET); base 231 drivers/i2c/busses/i2c-bcm-kona.c writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); base 242 drivers/i2c/busses/i2c-bcm-kona.c while (readl(dev->base + ISR_OFFSET) & ISR_CMDBUSY_MASK) base 264 drivers/i2c/busses/i2c-bcm-kona.c writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); base 276 drivers/i2c/busses/i2c-bcm-kona.c writel(0, dev->base + IER_OFFSET); base 300 drivers/i2c/busses/i2c-bcm-kona.c writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET); base 305 drivers/i2c/busses/i2c-bcm-kona.c dev->base + RXFCR_OFFSET); base 311 drivers/i2c/busses/i2c-bcm-kona.c writel(0, dev->base + IER_OFFSET); base 320 drivers/i2c/busses/i2c-bcm-kona.c *buf = readl(dev->base + RXFIFORDOUT_OFFSET); base 368 drivers/i2c/busses/i2c-bcm-kona.c writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); base 371 drivers/i2c/busses/i2c-bcm-kona.c writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); base 377 drivers/i2c/busses/i2c-bcm-kona.c writel(data, dev->base + DAT_OFFSET); base 383 drivers/i2c/busses/i2c-bcm-kona.c writel(0, dev->base + IER_OFFSET); base 390 drivers/i2c/busses/i2c-bcm-kona.c nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0; base 413 drivers/i2c/busses/i2c-bcm-kona.c dev->base + IER_OFFSET); base 420 drivers/i2c/busses/i2c-bcm-kona.c writel(buf[k], (dev->base + DAT_OFFSET)); base 428 drivers/i2c/busses/i2c-bcm-kona.c fifo_status = readl(dev->base + FIFO_STATUS_OFFSET); base 432 drivers/i2c/busses/i2c-bcm-kona.c writel(0, dev->base + IER_OFFSET); base 435 drivers/i2c/busses/i2c-bcm-kona.c if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) { base 515 drivers/i2c/busses/i2c-bcm-kona.c writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, base 516 drivers/i2c/busses/i2c-bcm-kona.c dev->base + CLKEN_OFFSET); base 521 drivers/i2c/busses/i2c-bcm-kona.c writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, base 522 drivers/i2c/busses/i2c-bcm-kona.c dev->base + HSTIM_OFFSET); base 528 drivers/i2c/busses/i2c-bcm-kona.c dev->base + TIM_OFFSET); base 533 drivers/i2c/busses/i2c-bcm-kona.c dev->base + CLKEN_OFFSET); base 542 drivers/i2c/busses/i2c-bcm-kona.c dev->base + TIM_OFFSET); base 547 drivers/i2c/busses/i2c-bcm-kona.c dev->base + HSTIM_OFFSET); base 549 drivers/i2c/busses/i2c-bcm-kona.c writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK, base 550 drivers/i2c/busses/i2c-bcm-kona.c dev->base + HSTIM_OFFSET); base 617 drivers/i2c/busses/i2c-bcm-kona.c writel(0, dev->base + PADCTL_OFFSET); base 693 drivers/i2c/busses/i2c-bcm-kona.c writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); base 766 drivers/i2c/busses/i2c-bcm-kona.c dev->base = devm_ioremap_resource(dev->device, iomem); base 767 drivers/i2c/busses/i2c-bcm-kona.c if (IS_ERR(dev->base)) base 802 drivers/i2c/busses/i2c-bcm-kona.c writel(0, dev->base + TOUT_OFFSET); base 809 drivers/i2c/busses/i2c-bcm-kona.c dev->base + TXFCR_OFFSET); base 812 drivers/i2c/busses/i2c-bcm-kona.c writel(0, dev->base + IER_OFFSET); base 821 drivers/i2c/busses/i2c-bcm-kona.c dev->base + ISR_OFFSET); base 843 drivers/i2c/busses/i2c-bcm-kona.c writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); base 167 drivers/i2c/busses/i2c-brcmstb.c void __iomem *base; base 186 drivers/i2c/busses/i2c-brcmstb.c __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg)) base 189 drivers/i2c/busses/i2c-brcmstb.c __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg)) base 606 drivers/i2c/busses/i2c-brcmstb.c dev->base = devm_ioremap_resource(dev->device, iomem); base 607 drivers/i2c/busses/i2c-brcmstb.c if (IS_ERR(dev->base)) { base 94 drivers/i2c/busses/i2c-cpm.c char *base; base 122 drivers/i2c/busses/i2c-davinci.c void __iomem *base; base 147 drivers/i2c/busses/i2c-davinci.c writew_relaxed(val, i2c_dev->base + reg); base 152 drivers/i2c/busses/i2c-davinci.c return readw_relaxed(i2c_dev->base + reg); base 818 drivers/i2c/busses/i2c-davinci.c dev->base = devm_ioremap_resource(&pdev->dev, mem); base 819 drivers/i2c/busses/i2c-davinci.c if (IS_ERR(dev->base)) { base 820 drivers/i2c/busses/i2c-davinci.c return PTR_ERR(dev->base); base 61 drivers/i2c/busses/i2c-designware-common.c value = readw_relaxed(dev->base + offset) | base 62 drivers/i2c/busses/i2c-designware-common.c (readw_relaxed(dev->base + offset + 2) << 16); base 64 drivers/i2c/busses/i2c-designware-common.c value = readl_relaxed(dev->base + offset); base 78 drivers/i2c/busses/i2c-designware-common.c writew_relaxed((u16)b, dev->base + offset); base 79 drivers/i2c/busses/i2c-designware-common.c writew_relaxed((u16)(b >> 16), dev->base + offset + 2); base 81 drivers/i2c/busses/i2c-designware-common.c writel_relaxed(b, dev->base + offset); base 227 drivers/i2c/busses/i2c-designware-core.h void __iomem *base; base 256 drivers/i2c/busses/i2c-designware-pcidrv.c dev->base = pcim_iomap_table(pdev)[0]; base 273 drivers/i2c/busses/i2c-designware-platdrv.c dev->base = devm_ioremap_resource(&pdev->dev, mem); base 274 drivers/i2c/busses/i2c-designware-platdrv.c if (IS_ERR(dev->base)) base 275 drivers/i2c/busses/i2c-designware-platdrv.c return PTR_ERR(dev->base); base 115 drivers/i2c/busses/i2c-efm32.c void __iomem *base; base 130 drivers/i2c/busses/i2c-efm32.c return readl(ddata->base + offset); base 136 drivers/i2c/busses/i2c-efm32.c writel(value, ddata->base + offset); base 349 drivers/i2c/busses/i2c-efm32.c ddata->base = devm_ioremap_resource(&pdev->dev, res); base 350 drivers/i2c/busses/i2c-efm32.c if (IS_ERR(ddata->base)) base 351 drivers/i2c/busses/i2c-efm32.c return PTR_ERR(ddata->base); base 37 drivers/i2c/busses/i2c-elektor.c static int base; base 137 drivers/i2c/busses/i2c-elektor.c if (!request_region(base, 2, pcf_isa_ops.name)) { base 139 drivers/i2c/busses/i2c-elektor.c "in use\n", pcf_isa_ops.name, base); base 142 drivers/i2c/busses/i2c-elektor.c base_iomem = ioport_map(base, 2); base 145 drivers/i2c/busses/i2c-elektor.c pcf_isa_ops.name, base); base 146 drivers/i2c/busses/i2c-elektor.c release_region(base, 2); base 150 drivers/i2c/busses/i2c-elektor.c if (!request_mem_region(base, 2, pcf_isa_ops.name)) { base 152 drivers/i2c/busses/i2c-elektor.c "is in use\n", pcf_isa_ops.name, base); base 155 drivers/i2c/busses/i2c-elektor.c base_iomem = ioremap(base, 2); base 158 drivers/i2c/busses/i2c-elektor.c "failed\n", pcf_isa_ops.name, base); base 159 drivers/i2c/busses/i2c-elektor.c release_mem_region(base, 2); base 163 drivers/i2c/busses/i2c-elektor.c pr_debug("%s: registers %#x remapped to %p\n", pcf_isa_ops.name, base, base 202 drivers/i2c/busses/i2c-elektor.c if (base == 0) { base 227 drivers/i2c/busses/i2c-elektor.c base = 0xe0000; base 244 drivers/i2c/busses/i2c-elektor.c if (mmapped && base < 0xc8000) { base 246 drivers/i2c/busses/i2c-elektor.c "for mmapped I/O\n", base); base 250 drivers/i2c/busses/i2c-elektor.c if (base == 0) { base 251 drivers/i2c/busses/i2c-elektor.c base = DEFAULT_BASE; base 265 drivers/i2c/busses/i2c-elektor.c dev_info(dev, "found device at %#x\n", base); base 277 drivers/i2c/busses/i2c-elektor.c release_region(base, 2); base 280 drivers/i2c/busses/i2c-elektor.c release_mem_region(base, 2); base 296 drivers/i2c/busses/i2c-elektor.c release_region(base, 2); base 299 drivers/i2c/busses/i2c-elektor.c release_mem_region(base, 2); base 319 drivers/i2c/busses/i2c-elektor.c module_param_hw(base, int, ioport_or_iomem, 0); base 67 drivers/i2c/busses/i2c-emev2.c void __iomem *base; base 77 drivers/i2c/busses/i2c-emev2.c writeb((readb(priv->base + reg) & ~clear) | set, priv->base + reg); base 92 drivers/i2c/busses/i2c-emev2.c status = readb(priv->base + I2C_OFS_IICSE0); base 111 drivers/i2c/busses/i2c-emev2.c if (readb(priv->base + I2C_OFS_IICACT0) & I2C_BIT_IICE0) { base 113 drivers/i2c/busses/i2c-emev2.c writeb(0, priv->base + I2C_OFS_IICACT0); base 116 drivers/i2c/busses/i2c-emev2.c while (readb(priv->base + I2C_OFS_IICACT0) == 1 && retr) base 122 drivers/i2c/busses/i2c-emev2.c writeb(I2C_BIT_DFC0, priv->base + I2C_OFS_IICCL0); base 125 drivers/i2c/busses/i2c-emev2.c writeb(I2C_BIT_STCEN | I2C_BIT_IICRSV, priv->base + I2C_OFS_IICF0); base 128 drivers/i2c/busses/i2c-emev2.c writeb(I2C_BIT_WTIM0, priv->base + I2C_OFS_IICC0); base 131 drivers/i2c/busses/i2c-emev2.c writeb(I2C_BIT_IICE0, priv->base + I2C_OFS_IICACT0); base 134 drivers/i2c/busses/i2c-emev2.c while (readb(priv->base + I2C_OFS_IICACT0) == 0 && retr) base 150 drivers/i2c/busses/i2c-emev2.c writeb(i2c_8bit_addr_from_msg(msg), priv->base + I2C_OFS_IIC0); base 178 drivers/i2c/busses/i2c-emev2.c msg->buf[count] = readb(priv->base + I2C_OFS_IIC0); base 189 drivers/i2c/busses/i2c-emev2.c writeb(msg->buf[count], priv->base + I2C_OFS_IIC0); base 215 drivers/i2c/busses/i2c-emev2.c if (readb(priv->base + I2C_OFS_IICF0) & I2C_BIT_IICBSY) base 237 drivers/i2c/busses/i2c-emev2.c status = readb(priv->base + I2C_OFS_IICSE0); base 271 drivers/i2c/busses/i2c-emev2.c writeb(value, priv->base + I2C_OFS_IIC0); base 288 drivers/i2c/busses/i2c-emev2.c value = readb(priv->base + I2C_OFS_IIC0); base 330 drivers/i2c/busses/i2c-emev2.c writeb(slave->addr << 1, priv->base + I2C_OFS_SVA0); base 341 drivers/i2c/busses/i2c-emev2.c writeb(0, priv->base + I2C_OFS_SVA0); base 372 drivers/i2c/busses/i2c-emev2.c priv->base = devm_ioremap_resource(&pdev->dev, r); base 373 drivers/i2c/busses/i2c-emev2.c if (IS_ERR(priv->base)) base 374 drivers/i2c/busses/i2c-emev2.c return PTR_ERR(priv->base); base 42 drivers/i2c/busses/i2c-highlander.c void __iomem *base; base 56 drivers/i2c/busses/i2c-highlander.c iowrite16(ioread16(dev->base + SMCR) | SMCR_IEIC, dev->base + SMCR); base 61 drivers/i2c/busses/i2c-highlander.c iowrite16(ioread16(dev->base + SMCR) & ~SMCR_IEIC, dev->base + SMCR); base 66 drivers/i2c/busses/i2c-highlander.c iowrite16(ioread16(dev->base + SMCR) | SMCR_START, dev->base + SMCR); base 71 drivers/i2c/busses/i2c-highlander.c iowrite16(ioread16(dev->base + SMCR) | SMCR_IRIC, dev->base + SMCR); base 78 drivers/i2c/busses/i2c-highlander.c smmr = ioread16(dev->base + SMMR); base 86 drivers/i2c/busses/i2c-highlander.c iowrite16(smmr, dev->base + SMMR); base 120 drivers/i2c/busses/i2c-highlander.c iowrite16(cmd, dev->base + SMSADR + i); base 130 drivers/i2c/busses/i2c-highlander.c while (ioread16(dev->base + SMCR) & SMCR_BBSY) { base 144 drivers/i2c/busses/i2c-highlander.c iowrite16(ioread16(dev->base + SMCR) | SMCR_RST, dev->base + SMCR); base 150 drivers/i2c/busses/i2c-highlander.c u16 tmp = ioread16(dev->base + SMCR); base 177 drivers/i2c/busses/i2c-highlander.c smcr = ioread16(dev->base + SMCR); base 243 drivers/i2c/busses/i2c-highlander.c data[i] = ioread16(dev->base + SMTRDR + (i * sizeof(u16))); base 263 drivers/i2c/busses/i2c-highlander.c iowrite16(data[i], dev->base + SMTRDR + (i * sizeof(u16))); base 308 drivers/i2c/busses/i2c-highlander.c tmp = ioread16(dev->base + SMMR); base 329 drivers/i2c/busses/i2c-highlander.c iowrite16(tmp, dev->base + SMMR); base 335 drivers/i2c/busses/i2c-highlander.c iowrite16((addr << 1) | read_write, dev->base + SMSMADR); base 372 drivers/i2c/busses/i2c-highlander.c dev->base = ioremap_nocache(res->start, resource_size(res)); base 373 drivers/i2c/busses/i2c-highlander.c if (unlikely(!dev->base)) { base 431 drivers/i2c/busses/i2c-highlander.c iounmap(dev->base); base 447 drivers/i2c/busses/i2c-highlander.c iounmap(dev->base); base 105 drivers/i2c/busses/i2c-hydra.c unsigned long base = pci_resource_start(dev, 0); base 108 drivers/i2c/busses/i2c-hydra.c if (!request_mem_region(base+offsetof(struct Hydra, CachePD), 4, base 114 drivers/i2c/busses/i2c-hydra.c release_mem_region(base+offsetof(struct Hydra, CachePD), 4); base 123 drivers/i2c/busses/i2c-hydra.c release_mem_region(base+offsetof(struct Hydra, CachePD), 4); base 368 drivers/i2c/busses/i2c-img-scb.c void __iomem *base; base 416 drivers/i2c/busses/i2c-img-scb.c writel(value, i2c->base + offset); base 421 drivers/i2c/busses/i2c-img-scb.c return readl(i2c->base + offset); base 1342 drivers/i2c/busses/i2c-img-scb.c i2c->base = devm_ioremap_resource(&pdev->dev, res); base 1343 drivers/i2c/busses/i2c-img-scb.c if (IS_ERR(i2c->base)) base 1344 drivers/i2c/busses/i2c-img-scb.c return PTR_ERR(i2c->base); base 104 drivers/i2c/busses/i2c-imx-lpi2c.c void __iomem *base; base 120 drivers/i2c/busses/i2c-imx-lpi2c.c writel(enable, lpi2c_imx->base + LPI2C_MIER); base 129 drivers/i2c/busses/i2c-imx-lpi2c.c temp = readl(lpi2c_imx->base + LPI2C_MSR); base 133 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MSR); base 174 drivers/i2c/busses/i2c-imx-lpi2c.c temp = readl(lpi2c_imx->base + LPI2C_MCR); base 176 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MCR); base 177 drivers/i2c/busses/i2c-imx-lpi2c.c writel(0x7f00, lpi2c_imx->base + LPI2C_MSR); base 180 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MTDR); base 190 drivers/i2c/busses/i2c-imx-lpi2c.c writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR); base 193 drivers/i2c/busses/i2c-imx-lpi2c.c temp = readl(lpi2c_imx->base + LPI2C_MSR); base 244 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MCFGR1); base 248 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MCFGR2); base 256 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MCCR1); base 258 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MCCR0); base 273 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MCR); base 274 drivers/i2c/busses/i2c-imx-lpi2c.c writel(0, lpi2c_imx->base + LPI2C_MCR); base 280 drivers/i2c/busses/i2c-imx-lpi2c.c temp = readl(lpi2c_imx->base + LPI2C_MCR); base 282 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MCR); base 297 drivers/i2c/busses/i2c-imx-lpi2c.c temp = readl(lpi2c_imx->base + LPI2C_MCR); base 299 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MCR); base 322 drivers/i2c/busses/i2c-imx-lpi2c.c txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff; base 324 drivers/i2c/busses/i2c-imx-lpi2c.c if (readl(lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) { base 342 drivers/i2c/busses/i2c-imx-lpi2c.c writel(lpi2c_imx->txfifosize >> 1, lpi2c_imx->base + LPI2C_MFCR); base 356 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp << 16, lpi2c_imx->base + LPI2C_MFCR); base 363 drivers/i2c/busses/i2c-imx-lpi2c.c txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff; base 370 drivers/i2c/busses/i2c-imx-lpi2c.c writel(data, lpi2c_imx->base + LPI2C_MTDR); base 386 drivers/i2c/busses/i2c-imx-lpi2c.c data = readl(lpi2c_imx->base + LPI2C_MRDR); base 417 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MTDR); base 421 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MTDR); base 446 drivers/i2c/busses/i2c-imx-lpi2c.c writel(temp, lpi2c_imx->base + LPI2C_MTDR); base 494 drivers/i2c/busses/i2c-imx-lpi2c.c temp = readl(lpi2c_imx->base + LPI2C_MSR); base 514 drivers/i2c/busses/i2c-imx-lpi2c.c temp = readl(lpi2c_imx->base + LPI2C_MSR); base 555 drivers/i2c/busses/i2c-imx-lpi2c.c lpi2c_imx->base = devm_platform_ioremap_resource(pdev, 0); base 556 drivers/i2c/busses/i2c-imx-lpi2c.c if (IS_ERR(lpi2c_imx->base)) base 557 drivers/i2c/busses/i2c-imx-lpi2c.c return PTR_ERR(lpi2c_imx->base); base 605 drivers/i2c/busses/i2c-imx-lpi2c.c temp = readl(lpi2c_imx->base + LPI2C_PARAM); base 190 drivers/i2c/busses/i2c-imx.c void __iomem *base; base 273 drivers/i2c/busses/i2c-imx.c writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); base 279 drivers/i2c/busses/i2c-imx.c return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); base 1061 drivers/i2c/busses/i2c-imx.c void __iomem *base; base 1075 drivers/i2c/busses/i2c-imx.c base = devm_ioremap_resource(&pdev->dev, res); base 1076 drivers/i2c/busses/i2c-imx.c if (IS_ERR(base)) base 1077 drivers/i2c/busses/i2c-imx.c return PTR_ERR(base); base 1098 drivers/i2c/busses/i2c-imx.c i2c_imx->base = base; base 73 drivers/i2c/busses/i2c-lpc2k.c void __iomem *base; base 87 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR); base 88 drivers/i2c/busses/i2c-lpc2k.c writel(0, i2c->base + LPC24XX_I2ADDR); base 89 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET); base 100 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET); base 103 drivers/i2c/busses/i2c-lpc2k.c while (readl(i2c->base + LPC24XX_I2STAT) != M_I2C_IDLE) { base 125 drivers/i2c/busses/i2c-lpc2k.c status = readl(i2c->base + LPC24XX_I2STAT); base 133 drivers/i2c/busses/i2c-lpc2k.c writel(data, i2c->base + LPC24XX_I2DAT); base 134 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR); base 145 drivers/i2c/busses/i2c-lpc2k.c i2c->base + LPC24XX_I2DAT); base 148 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET); base 149 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); base 164 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR); base 167 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET); base 170 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR); base 183 drivers/i2c/busses/i2c-lpc2k.c readl(i2c->base + LPC24XX_I2DAT); base 188 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET); base 189 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); base 205 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR); base 208 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET); base 211 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR); base 219 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET); base 229 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_STA | LPC24XX_STO, i2c->base + LPC24XX_I2CONCLR); base 249 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); base 256 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET); base 269 drivers/i2c/busses/i2c-lpc2k.c i2c->base + LPC24XX_I2DAT); base 274 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET); base 277 drivers/i2c/busses/i2c-lpc2k.c writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); base 301 drivers/i2c/busses/i2c-lpc2k.c stat = readl(i2c->base + LPC24XX_I2STAT); base 327 drivers/i2c/busses/i2c-lpc2k.c if (readl(i2c->base + LPC24XX_I2CONSET) & LPC24XX_SI) { base 360 drivers/i2c/busses/i2c-lpc2k.c i2c->base = devm_ioremap_resource(&pdev->dev, res); base 361 drivers/i2c/busses/i2c-lpc2k.c if (IS_ERR(i2c->base)) base 362 drivers/i2c/busses/i2c-lpc2k.c return PTR_ERR(i2c->base); base 417 drivers/i2c/busses/i2c-lpc2k.c writel(scl_high, i2c->base + LPC24XX_I2SCLH); base 418 drivers/i2c/busses/i2c-lpc2k.c writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL); base 63 drivers/i2c/busses/i2c-mpc.c void __iomem *base; base 86 drivers/i2c/busses/i2c-mpc.c writeb(x, i2c->base + MPC_I2C_CR); base 92 drivers/i2c/busses/i2c-mpc.c if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) { base 94 drivers/i2c/busses/i2c-mpc.c i2c->interrupt = readb(i2c->base + MPC_I2C_SR); base 95 drivers/i2c/busses/i2c-mpc.c writeb(0, i2c->base + MPC_I2C_SR); base 118 drivers/i2c/busses/i2c-mpc.c readb(i2c->base + MPC_I2C_DR); base 131 drivers/i2c/busses/i2c-mpc.c while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) { base 140 drivers/i2c/busses/i2c-mpc.c cmd_err = readb(i2c->base + MPC_I2C_SR); base 141 drivers/i2c/busses/i2c-mpc.c writeb(0, i2c->base + MPC_I2C_SR); base 243 drivers/i2c/busses/i2c-mpc.c readb(i2c->base + MPC_I2C_FDR)); base 250 drivers/i2c/busses/i2c-mpc.c writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); base 429 drivers/i2c/busses/i2c-mpc.c readb(i2c->base + MPC_I2C_DFSRR), base 430 drivers/i2c/busses/i2c-mpc.c readb(i2c->base + MPC_I2C_FDR)); base 437 drivers/i2c/busses/i2c-mpc.c writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); base 438 drivers/i2c/busses/i2c-mpc.c writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR); base 456 drivers/i2c/busses/i2c-mpc.c writeb(0, i2c->base + MPC_I2C_SR); base 476 drivers/i2c/busses/i2c-mpc.c writeb((target << 1), i2c->base + MPC_I2C_DR); base 484 drivers/i2c/busses/i2c-mpc.c writeb(data[i], i2c->base + MPC_I2C_DR); base 504 drivers/i2c/busses/i2c-mpc.c writeb((target << 1) | 1, i2c->base + MPC_I2C_DR); base 516 drivers/i2c/busses/i2c-mpc.c readb(i2c->base + MPC_I2C_DR); base 541 drivers/i2c/busses/i2c-mpc.c byte = readb(i2c->base + MPC_I2C_DR); base 576 drivers/i2c/busses/i2c-mpc.c while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { base 583 drivers/i2c/busses/i2c-mpc.c u8 status = readb(i2c->base + MPC_I2C_SR); base 588 drivers/i2c/busses/i2c-mpc.c i2c->base + MPC_I2C_SR); base 617 drivers/i2c/busses/i2c-mpc.c while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { base 619 drivers/i2c/busses/i2c-mpc.c u8 status = readb(i2c->base + MPC_I2C_SR); base 624 drivers/i2c/busses/i2c-mpc.c i2c->base + MPC_I2C_SR); base 676 drivers/i2c/busses/i2c-mpc.c i2c->base = of_iomap(op->dev.of_node, 0); base 677 drivers/i2c/busses/i2c-mpc.c if (!i2c->base) { base 756 drivers/i2c/busses/i2c-mpc.c iounmap(i2c->base); base 775 drivers/i2c/busses/i2c-mpc.c iounmap(i2c->base); base 785 drivers/i2c/busses/i2c-mpc.c i2c->fdr = readb(i2c->base + MPC_I2C_FDR); base 786 drivers/i2c/busses/i2c-mpc.c i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR); base 795 drivers/i2c/busses/i2c-mpc.c writeb(i2c->fdr, i2c->base + MPC_I2C_FDR); base 796 drivers/i2c/busses/i2c-mpc.c writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR); base 203 drivers/i2c/busses/i2c-mt65xx.c void __iomem *base; /* i2c base addr */ base 330 drivers/i2c/busses/i2c-mt65xx.c return readw(i2c->base + i2c->dev_comp->regs[reg]); base 336 drivers/i2c/busses/i2c-mt65xx.c writew(val, i2c->base + i2c->dev_comp->regs[reg]); base 925 drivers/i2c/busses/i2c-mt65xx.c i2c->base = devm_ioremap_resource(&pdev->dev, res); base 926 drivers/i2c/busses/i2c-mt65xx.c if (IS_ERR(i2c->base)) base 927 drivers/i2c/busses/i2c-mt65xx.c return PTR_ERR(i2c->base); base 60 drivers/i2c/busses/i2c-mt7621.c void __iomem *base; base 74 drivers/i2c/busses/i2c-mt7621.c ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG, base 96 drivers/i2c/busses/i2c-mt7621.c SM0CTL0_SCL_STRETCH, i2c->base + REG_SM0CTL0_REG); base 97 drivers/i2c/busses/i2c-mt7621.c iowrite32(0, i2c->base + REG_SM0CFG2_REG); base 104 drivers/i2c/busses/i2c-mt7621.c ioread32(i2c->base + REG_SM0CFG2_REG), base 105 drivers/i2c/busses/i2c-mt7621.c ioread32(i2c->base + REG_SM0CTL0_REG), base 106 drivers/i2c/busses/i2c-mt7621.c ioread32(i2c->base + REG_SM0CTL1_REG), base 107 drivers/i2c/busses/i2c-mt7621.c ioread32(i2c->base + REG_SM0D0_REG), base 108 drivers/i2c/busses/i2c-mt7621.c ioread32(i2c->base + REG_SM0D1_REG)); base 113 drivers/i2c/busses/i2c-mt7621.c u32 ack = readl_relaxed(i2c->base + REG_SM0CTL1_REG); base 121 drivers/i2c/busses/i2c-mt7621.c iowrite32(SM0CTL1_START | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG); base 127 drivers/i2c/busses/i2c-mt7621.c iowrite32(SM0CTL1_STOP | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG); base 134 drivers/i2c/busses/i2c-mt7621.c i2c->base + REG_SM0CTL1_REG); base 170 drivers/i2c/busses/i2c-mt7621.c iowrite32(addr, i2c->base + REG_SM0D0_REG); base 177 drivers/i2c/busses/i2c-mt7621.c iowrite32(addr, i2c->base + REG_SM0D0_REG); base 199 drivers/i2c/busses/i2c-mt7621.c iowrite32(data[0], i2c->base + REG_SM0D0_REG); base 200 drivers/i2c/busses/i2c-mt7621.c iowrite32(data[1], i2c->base + REG_SM0D1_REG); base 209 drivers/i2c/busses/i2c-mt7621.c data[0] = ioread32(i2c->base + REG_SM0D0_REG); base 210 drivers/i2c/busses/i2c-mt7621.c data[1] = ioread32(i2c->base + REG_SM0D1_REG); base 284 drivers/i2c/busses/i2c-mt7621.c i2c->base = devm_ioremap_resource(&pdev->dev, res); base 285 drivers/i2c/busses/i2c-mt7621.c if (IS_ERR(i2c->base)) base 286 drivers/i2c/busses/i2c-mt7621.c return PTR_ERR(i2c->base); base 56 drivers/i2c/busses/i2c-nforce2.c int base; base 74 drivers/i2c/busses/i2c-nforce2.c #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */ base 75 drivers/i2c/busses/i2c-nforce2.c #define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */ base 76 drivers/i2c/busses/i2c-nforce2.c #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */ base 77 drivers/i2c/busses/i2c-nforce2.c #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */ base 78 drivers/i2c/busses/i2c-nforce2.c #define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */ base 79 drivers/i2c/busses/i2c-nforce2.c #define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data base 81 drivers/i2c/busses/i2c-nforce2.c #define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to base 84 drivers/i2c/busses/i2c-nforce2.c #define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */ base 323 drivers/i2c/busses/i2c-nforce2.c smbus->base = pci_resource_start(dev, bar); base 324 drivers/i2c/busses/i2c-nforce2.c if (smbus->base) { base 337 drivers/i2c/busses/i2c-nforce2.c smbus->base = iobase & PCI_BASE_ADDRESS_IO_MASK; base 341 drivers/i2c/busses/i2c-nforce2.c error = acpi_check_region(smbus->base, smbus->size, base 346 drivers/i2c/busses/i2c-nforce2.c if (!request_region(smbus->base, smbus->size, nforce2_driver.name)) { base 348 drivers/i2c/busses/i2c-nforce2.c smbus->base, smbus->base+smbus->size-1, name); base 357 drivers/i2c/busses/i2c-nforce2.c "SMBus nForce2 adapter at %04x", smbus->base); base 361 drivers/i2c/busses/i2c-nforce2.c release_region(smbus->base, smbus->size); base 365 drivers/i2c/busses/i2c-nforce2.c smbus->base); base 394 drivers/i2c/busses/i2c-nforce2.c smbuses[0].base = 0; /* to have a check value */ base 400 drivers/i2c/busses/i2c-nforce2.c smbuses[1].base = 0; base 405 drivers/i2c/busses/i2c-nforce2.c smbuses[1].base = 0; /* to have a check value */ base 424 drivers/i2c/busses/i2c-nforce2.c if (smbuses[0].base) { base 426 drivers/i2c/busses/i2c-nforce2.c release_region(smbuses[0].base, smbuses[0].size); base 428 drivers/i2c/busses/i2c-nforce2.c if (smbuses[1].base) { base 430 drivers/i2c/busses/i2c-nforce2.c release_region(smbuses[1].base, smbuses[1].size); base 34 drivers/i2c/busses/i2c-ocores.c void __iomem *base; base 92 drivers/i2c/busses/i2c-ocores.c iowrite8(value, i2c->base + (reg << i2c->reg_shift)); base 97 drivers/i2c/busses/i2c-ocores.c iowrite16(value, i2c->base + (reg << i2c->reg_shift)); base 102 drivers/i2c/busses/i2c-ocores.c iowrite32(value, i2c->base + (reg << i2c->reg_shift)); base 107 drivers/i2c/busses/i2c-ocores.c iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); base 112 drivers/i2c/busses/i2c-ocores.c iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); base 117 drivers/i2c/busses/i2c-ocores.c return ioread8(i2c->base + (reg << i2c->reg_shift)); base 122 drivers/i2c/busses/i2c-ocores.c return ioread16(i2c->base + (reg << i2c->reg_shift)); base 127 drivers/i2c/busses/i2c-ocores.c return ioread32(i2c->base + (reg << i2c->reg_shift)); base 132 drivers/i2c/busses/i2c-ocores.c return ioread16be(i2c->base + (reg << i2c->reg_shift)); base 137 drivers/i2c/busses/i2c-ocores.c return ioread32be(i2c->base + (reg << i2c->reg_shift)); base 502 drivers/i2c/busses/i2c-ocores.c rd = ioread32be(i2c->base + (rreg << i2c->reg_shift)); base 517 drivers/i2c/busses/i2c-ocores.c curr = ioread32be(i2c->base + (rreg << i2c->reg_shift)); base 525 drivers/i2c/busses/i2c-ocores.c iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift)); base 623 drivers/i2c/busses/i2c-ocores.c i2c->base = devm_ioremap_resource(&pdev->dev, res); base 624 drivers/i2c/busses/i2c-ocores.c if (IS_ERR(i2c->base)) base 625 drivers/i2c/busses/i2c-ocores.c return PTR_ERR(i2c->base); base 180 drivers/i2c/busses/i2c-omap.c void __iomem *base; /* virtual */ base 268 drivers/i2c/busses/i2c-omap.c writew_relaxed(val, omap->base + base 274 drivers/i2c/busses/i2c-omap.c return readw_relaxed(omap->base + base 1379 drivers/i2c/busses/i2c-omap.c omap->base = devm_ioremap_resource(&pdev->dev, mem); base 1380 drivers/i2c/busses/i2c-omap.c if (IS_ERR(omap->base)) base 1381 drivers/i2c/busses/i2c-omap.c return PTR_ERR(omap->base); base 1421 drivers/i2c/busses/i2c-omap.c rev = readw_relaxed(omap->base + 0x04); base 99 drivers/i2c/busses/i2c-owl.c void __iomem *base; base 122 drivers/i2c/busses/i2c-owl.c owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, base 125 drivers/i2c/busses/i2c-owl.c owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, base 129 drivers/i2c/busses/i2c-owl.c writel(0, i2c_dev->base + OWL_I2C_REG_STAT); base 137 drivers/i2c/busses/i2c-owl.c owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, base 143 drivers/i2c/busses/i2c-owl.c val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); base 164 drivers/i2c/busses/i2c-owl.c writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); base 179 drivers/i2c/busses/i2c-owl.c fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT); base 186 drivers/i2c/busses/i2c-owl.c stat = readl(i2c_dev->base + OWL_I2C_REG_STAT); base 194 drivers/i2c/busses/i2c-owl.c while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & base 196 drivers/i2c/busses/i2c-owl.c msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base + base 201 drivers/i2c/busses/i2c-owl.c while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & base 204 drivers/i2c/busses/i2c-owl.c i2c_dev->base + OWL_I2C_REG_TXDAT); base 210 drivers/i2c/busses/i2c-owl.c owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, base 231 drivers/i2c/busses/i2c-owl.c while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) { base 278 drivers/i2c/busses/i2c-owl.c val = readl(i2c_dev->base + OWL_I2C_REG_STAT); base 281 drivers/i2c/busses/i2c-owl.c writel(val, i2c_dev->base + OWL_I2C_REG_STAT); base 289 drivers/i2c/busses/i2c-owl.c owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, base 307 drivers/i2c/busses/i2c-owl.c writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); base 312 drivers/i2c/busses/i2c-owl.c i2c_dev->base + OWL_I2C_REG_TXDAT); base 325 drivers/i2c/busses/i2c-owl.c writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT); base 328 drivers/i2c/busses/i2c-owl.c writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); base 334 drivers/i2c/busses/i2c-owl.c if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & base 339 drivers/i2c/busses/i2c-owl.c i2c_dev->base + OWL_I2C_REG_TXDAT); base 347 drivers/i2c/busses/i2c-owl.c owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, base 350 drivers/i2c/busses/i2c-owl.c owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, base 354 drivers/i2c/busses/i2c-owl.c writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD); base 365 drivers/i2c/busses/i2c-owl.c owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, base 379 drivers/i2c/busses/i2c-owl.c owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, base 410 drivers/i2c/busses/i2c-owl.c i2c_dev->base = devm_ioremap_resource(dev, res); base 411 drivers/i2c/busses/i2c-owl.c if (IS_ERR(i2c_dev->base)) base 412 drivers/i2c/busses/i2c-owl.c return PTR_ERR(i2c_dev->base); base 32 drivers/i2c/busses/i2c-parport-light.c static u16 base; base 33 drivers/i2c/busses/i2c-parport-light.c module_param_hw(base, ushort, ioport, 0); base 34 drivers/i2c/busses/i2c-parport-light.c MODULE_PARM_DESC(base, "Base I/O address"); base 44 drivers/i2c/busses/i2c-parport-light.c outb(d, base+p); base 49 drivers/i2c/busses/i2c-parport-light.c return inb(base+p); base 223 drivers/i2c/busses/i2c-parport-light.c if (base == 0) { base 225 drivers/i2c/busses/i2c-parport-light.c base = DEFAULT_BASE; base 228 drivers/i2c/busses/i2c-parport-light.c if (!request_region(base, 3, DRVNAME)) base 238 drivers/i2c/busses/i2c-parport-light.c err = i2c_parport_device_add(base); base 251 drivers/i2c/busses/i2c-parport-light.c release_region(base, 3); base 259 drivers/i2c/busses/i2c-parport-light.c release_region(base, 3); base 23 drivers/i2c/busses/i2c-pasemi.c unsigned long base; base 55 drivers/i2c/busses/i2c-pasemi.c smbus->base + reg, val); base 56 drivers/i2c/busses/i2c-pasemi.c outl(val, smbus->base + reg); base 62 drivers/i2c/busses/i2c-pasemi.c ret = inl(smbus->base + reg); base 64 drivers/i2c/busses/i2c-pasemi.c smbus->base + reg, ret); base 345 drivers/i2c/busses/i2c-pasemi.c smbus->base = pci_resource_start(dev, 0); base 348 drivers/i2c/busses/i2c-pasemi.c if (!request_region(smbus->base, smbus->size, base 356 drivers/i2c/busses/i2c-pasemi.c "PA Semi SMBus adapter at 0x%lx", smbus->base); base 376 drivers/i2c/busses/i2c-pasemi.c release_region(smbus->base, smbus->size); base 387 drivers/i2c/busses/i2c-pasemi.c release_region(smbus->base, smbus->size); base 27 drivers/i2c/busses/i2c-pca-isa.c static unsigned long base; base 42 drivers/i2c/busses/i2c-pca-isa.c base+reg, val); base 44 drivers/i2c/busses/i2c-pca-isa.c outb(val, base+reg); base 49 drivers/i2c/busses/i2c-pca-isa.c int res = inb(base+reg); base 111 drivers/i2c/busses/i2c-pca-isa.c int match = base != 0; base 126 drivers/i2c/busses/i2c-pca-isa.c dev_info(dev, "i/o base %#08lx. irq %d\n", base, irq); base 129 drivers/i2c/busses/i2c-pca-isa.c if (check_legacy_ioport(base)) { base 130 drivers/i2c/busses/i2c-pca-isa.c dev_err(dev, "I/O address %#08lx is not available\n", base); base 135 drivers/i2c/busses/i2c-pca-isa.c if (!request_region(base, IO_SIZE, "i2c-pca-isa")) { base 136 drivers/i2c/busses/i2c-pca-isa.c dev_err(dev, "I/O address %#08lx is in use\n", base); base 159 drivers/i2c/busses/i2c-pca-isa.c release_region(base, IO_SIZE); base 172 drivers/i2c/busses/i2c-pca-isa.c release_region(base, IO_SIZE); base 191 drivers/i2c/busses/i2c-pca-isa.c module_param_hw(base, ulong, ioport, 0); base 192 drivers/i2c/busses/i2c-pca-isa.c MODULE_PARM_DESC(base, "I/O base address"); base 155 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); base 158 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); base 163 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); base 168 drivers/i2c/busses/i2c-qcom-geni.c u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); base 169 drivers/i2c/busses/i2c-qcom-geni.c u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); base 170 drivers/i2c/busses/i2c-qcom-geni.c u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); base 171 drivers/i2c/busses/i2c-qcom-geni.c u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); base 172 drivers/i2c/busses/i2c-qcom-geni.c u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); base 176 drivers/i2c/busses/i2c-qcom-geni.c rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); base 177 drivers/i2c/busses/i2c-qcom-geni.c tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); base 179 drivers/i2c/busses/i2c-qcom-geni.c rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS); base 180 drivers/i2c/busses/i2c-qcom-geni.c tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS); base 205 drivers/i2c/busses/i2c-qcom-geni.c void __iomem *base = gi2c->se.base; base 217 drivers/i2c/busses/i2c-qcom-geni.c m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS); base 218 drivers/i2c/busses/i2c-qcom-geni.c rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS); base 219 drivers/i2c/busses/i2c-qcom-geni.c dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT); base 220 drivers/i2c/busses/i2c-qcom-geni.c dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT); base 221 drivers/i2c/busses/i2c-qcom-geni.c dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN); base 244 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); base 254 drivers/i2c/busses/i2c-qcom-geni.c val = readl_relaxed(base + SE_GENI_RX_FIFOn); base 275 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(val, base + SE_GENI_TX_FIFOn); base 278 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); base 285 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR); base 288 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR); base 290 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR); base 316 drivers/i2c/busses/i2c-qcom-geni.c val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); base 328 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST); base 331 drivers/i2c/busses/i2c-qcom-geni.c val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); base 343 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST); base 346 drivers/i2c/busses/i2c-qcom-geni.c val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); base 370 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); base 411 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); base 421 drivers/i2c/busses/i2c-qcom-geni.c writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG); base 513 drivers/i2c/busses/i2c-qcom-geni.c gi2c->se.base = devm_ioremap_resource(&pdev->dev, res); base 514 drivers/i2c/busses/i2c-qcom-geni.c if (IS_ERR(gi2c->se.base)) base 515 drivers/i2c/busses/i2c-qcom-geni.c return PTR_ERR(gi2c->se.base); base 231 drivers/i2c/busses/i2c-qup.c void __iomem *base; base 293 drivers/i2c/busses/i2c-qup.c bus_err = readl(qup->base + QUP_I2C_STATUS); base 294 drivers/i2c/busses/i2c-qup.c qup_err = readl(qup->base + QUP_ERROR_FLAGS); base 295 drivers/i2c/busses/i2c-qup.c opflags = readl(qup->base + QUP_OPERATIONAL); base 299 drivers/i2c/busses/i2c-qup.c writel(QUP_RESET_STATE, qup->base + QUP_STATE); base 308 drivers/i2c/busses/i2c-qup.c writel(qup_err, qup->base + QUP_ERROR_FLAGS); base 312 drivers/i2c/busses/i2c-qup.c writel(bus_err, qup->base + QUP_I2C_STATUS); base 331 drivers/i2c/busses/i2c-qup.c writel(QUP_RESET_STATE, qup->base + QUP_STATE); base 336 drivers/i2c/busses/i2c-qup.c writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); base 348 drivers/i2c/busses/i2c-qup.c writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); base 392 drivers/i2c/busses/i2c-qup.c state = readl(qup->base + QUP_STATE); base 411 drivers/i2c/busses/i2c-qup.c u32 val = readl(qup->base + QUP_STATE); base 414 drivers/i2c/busses/i2c-qup.c writel(val, qup->base + QUP_STATE); base 432 drivers/i2c/busses/i2c-qup.c writel(state, qup->base + QUP_STATE); base 448 drivers/i2c/busses/i2c-qup.c status = readl(qup->base + QUP_I2C_STATUS); base 492 drivers/i2c/busses/i2c-qup.c writel(val, qup->base + QUP_OUT_FIFO_BASE); base 853 drivers/i2c/busses/i2c-qup.c writel(0, qup->base + QUP_MX_INPUT_CNT); base 854 drivers/i2c/busses/i2c-qup.c writel(0, qup->base + QUP_MX_OUTPUT_CNT); base 857 drivers/i2c/busses/i2c-qup.c writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE); base 860 drivers/i2c/busses/i2c-qup.c writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK); base 867 drivers/i2c/busses/i2c-qup.c writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); base 911 drivers/i2c/busses/i2c-qup.c writel(1, qup->base + QUP_SW_RESET); base 931 drivers/i2c/busses/i2c-qup.c val = readl(qup->base + QUP_IN_FIFO_BASE); base 955 drivers/i2c/busses/i2c-qup.c writel(val, qup->base + QUP_OUT_FIFO_BASE); base 971 drivers/i2c/busses/i2c-qup.c writel(0, qup->base + QUP_MX_WRITE_CNT); base 972 drivers/i2c/busses/i2c-qup.c writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT); base 974 drivers/i2c/busses/i2c-qup.c writel(0, qup->base + QUP_MX_OUTPUT_CNT); base 975 drivers/i2c/busses/i2c-qup.c writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT); base 981 drivers/i2c/busses/i2c-qup.c writel(0, qup->base + QUP_MX_READ_CNT); base 982 drivers/i2c/busses/i2c-qup.c writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT); base 984 drivers/i2c/busses/i2c-qup.c writel(0, qup->base + QUP_MX_INPUT_CNT); base 985 drivers/i2c/busses/i2c-qup.c writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT); base 991 drivers/i2c/busses/i2c-qup.c writel(qup_config, qup->base + QUP_CONFIG); base 992 drivers/i2c/busses/i2c-qup.c writel(io_mode, qup->base + QUP_IO_MODE); base 1013 drivers/i2c/busses/i2c-qup.c writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); base 1082 drivers/i2c/busses/i2c-qup.c writel(1, qup->base + QUP_SW_RESET); base 1088 drivers/i2c/busses/i2c-qup.c writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); base 1136 drivers/i2c/busses/i2c-qup.c qup->base + QUP_MX_OUTPUT_CNT); base 1139 drivers/i2c/busses/i2c-qup.c qup->base + QUP_MX_WRITE_CNT); base 1144 drivers/i2c/busses/i2c-qup.c qup->base + QUP_MX_INPUT_CNT); base 1147 drivers/i2c/busses/i2c-qup.c qup->base + QUP_MX_READ_CNT); base 1152 drivers/i2c/busses/i2c-qup.c writel(qup_config, qup->base + QUP_CONFIG); base 1167 drivers/i2c/busses/i2c-qup.c writel(0, qup->base + QUP_MX_WRITE_CNT); base 1169 drivers/i2c/busses/i2c-qup.c writel(0, qup->base + QUP_MX_OUTPUT_CNT); base 1174 drivers/i2c/busses/i2c-qup.c writel(0, qup->base + QUP_MX_READ_CNT); base 1176 drivers/i2c/busses/i2c-qup.c writel(0, qup->base + QUP_MX_INPUT_CNT); base 1179 drivers/i2c/busses/i2c-qup.c writel(io_mode, qup->base + QUP_IO_MODE); base 1208 drivers/i2c/busses/i2c-qup.c blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); base 1227 drivers/i2c/busses/i2c-qup.c blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); base 1271 drivers/i2c/busses/i2c-qup.c qup->base + QUP_OUT_FIFO_BASE); base 1289 drivers/i2c/busses/i2c-qup.c writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); base 1341 drivers/i2c/busses/i2c-qup.c writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); base 1387 drivers/i2c/busses/i2c-qup.c writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); base 1562 drivers/i2c/busses/i2c-qup.c writel(1, qup->base + QUP_SW_RESET); base 1568 drivers/i2c/busses/i2c-qup.c writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG); base 1569 drivers/i2c/busses/i2c-qup.c writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); base 1651 drivers/i2c/busses/i2c-qup.c config = readl(qup->base + QUP_CONFIG); base 1653 drivers/i2c/busses/i2c-qup.c writel(config, qup->base + QUP_CONFIG); base 1766 drivers/i2c/busses/i2c-qup.c qup->base = devm_ioremap_resource(qup->dev, res); base 1767 drivers/i2c/busses/i2c-qup.c if (IS_ERR(qup->base)) base 1768 drivers/i2c/busses/i2c-qup.c return PTR_ERR(qup->base); base 1804 drivers/i2c/busses/i2c-qup.c writel(1, qup->base + QUP_SW_RESET); base 1817 drivers/i2c/busses/i2c-qup.c hw_ver = readl(qup->base + QUP_HW_VERSION); base 1820 drivers/i2c/busses/i2c-qup.c io_mode = readl(qup->base + QUP_IO_MODE); base 90 drivers/i2c/busses/i2c-riic.c void __iomem *base; base 109 drivers/i2c/busses/i2c-riic.c writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg); base 121 drivers/i2c/busses/i2c-riic.c if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) { base 129 drivers/i2c/busses/i2c-riic.c writeb(0, riic->base + RIIC_ICSR2); base 137 drivers/i2c/busses/i2c-riic.c writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER); base 139 drivers/i2c/busses/i2c-riic.c writeb(start_bit, riic->base + RIIC_ICCR2); base 193 drivers/i2c/busses/i2c-riic.c writeb(val, riic->base + RIIC_ICDRT); base 202 drivers/i2c/busses/i2c-riic.c if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) { base 204 drivers/i2c/busses/i2c-riic.c readb(riic->base + RIIC_ICDRR); /* dummy read */ base 213 drivers/i2c/busses/i2c-riic.c writeb(ICCR2_SP, riic->base + RIIC_ICCR2); base 232 drivers/i2c/busses/i2c-riic.c readb(riic->base + RIIC_ICDRR); /* dummy read */ base 240 drivers/i2c/busses/i2c-riic.c writeb(ICCR2_SP, riic->base + RIIC_ICCR2); base 250 drivers/i2c/busses/i2c-riic.c *riic->buf = readb(riic->base + RIIC_ICDRR); base 262 drivers/i2c/busses/i2c-riic.c writeb(0, riic->base + RIIC_ICSR2); base 263 drivers/i2c/busses/i2c-riic.c readb(riic->base + RIIC_ICSR2); base 264 drivers/i2c/busses/i2c-riic.c writeb(0, riic->base + RIIC_ICIER); base 265 drivers/i2c/busses/i2c-riic.c readb(riic->base + RIIC_ICIER); base 367 drivers/i2c/busses/i2c-riic.c writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1); base 370 drivers/i2c/busses/i2c-riic.c writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1); base 371 drivers/i2c/busses/i2c-riic.c writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH); base 372 drivers/i2c/busses/i2c-riic.c writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL); base 374 drivers/i2c/busses/i2c-riic.c writeb(0, riic->base + RIIC_ICSER); base 375 drivers/i2c/busses/i2c-riic.c writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3); base 405 drivers/i2c/busses/i2c-riic.c riic->base = devm_ioremap_resource(&pdev->dev, res); base 406 drivers/i2c/busses/i2c-riic.c if (IS_ERR(riic->base)) base 407 drivers/i2c/busses/i2c-riic.c return PTR_ERR(riic->base); base 466 drivers/i2c/busses/i2c-riic.c writeb(0, riic->base + RIIC_ICIER); base 70 drivers/i2c/busses/i2c-sirf.c void __iomem *base; base 95 drivers/i2c/busses/i2c-sirf.c data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i); base 115 drivers/i2c/busses/i2c-sirf.c siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); base 128 drivers/i2c/busses/i2c-sirf.c siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); base 130 drivers/i2c/busses/i2c-sirf.c siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); base 136 drivers/i2c/busses/i2c-sirf.c writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START); base 142 drivers/i2c/busses/i2c-sirf.c u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS); base 147 drivers/i2c/busses/i2c-sirf.c writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS); base 159 drivers/i2c/busses/i2c-sirf.c writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, base 160 drivers/i2c/busses/i2c-sirf.c siic->base + SIRFSOC_I2C_CTRL); base 161 drivers/i2c/busses/i2c-sirf.c while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) base 174 drivers/i2c/busses/i2c-sirf.c writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS); base 190 drivers/i2c/busses/i2c-sirf.c writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); base 198 drivers/i2c/busses/i2c-sirf.c writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); base 203 drivers/i2c/busses/i2c-sirf.c u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL); base 210 drivers/i2c/busses/i2c-sirf.c siic->base + SIRFSOC_I2C_CTRL); base 219 drivers/i2c/busses/i2c-sirf.c siic->base + SIRFSOC_I2C_CTRL); base 220 drivers/i2c/busses/i2c-sirf.c writel(0, siic->base + SIRFSOC_I2C_CMD_START); base 224 drivers/i2c/busses/i2c-sirf.c writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, base 225 drivers/i2c/busses/i2c-sirf.c siic->base + SIRFSOC_I2C_CTRL); base 226 drivers/i2c/busses/i2c-sirf.c while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) base 314 drivers/i2c/busses/i2c-sirf.c siic->base = devm_ioremap_resource(&pdev->dev, mem_res); base 315 drivers/i2c/busses/i2c-sirf.c if (IS_ERR(siic->base)) { base 316 drivers/i2c/busses/i2c-sirf.c err = PTR_ERR(siic->base); base 345 drivers/i2c/busses/i2c-sirf.c writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); base 346 drivers/i2c/busses/i2c-sirf.c while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) base 349 drivers/i2c/busses/i2c-sirf.c siic->base + SIRFSOC_I2C_CTRL); base 382 drivers/i2c/busses/i2c-sirf.c writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL); base 384 drivers/i2c/busses/i2c-sirf.c writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY); base 386 drivers/i2c/busses/i2c-sirf.c writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY); base 413 drivers/i2c/busses/i2c-sirf.c writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); base 427 drivers/i2c/busses/i2c-sirf.c siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY); base 428 drivers/i2c/busses/i2c-sirf.c siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL); base 439 drivers/i2c/busses/i2c-sirf.c writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); base 440 drivers/i2c/busses/i2c-sirf.c while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) base 443 drivers/i2c/busses/i2c-sirf.c siic->base + SIRFSOC_I2C_CTRL); base 444 drivers/i2c/busses/i2c-sirf.c writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL); base 445 drivers/i2c/busses/i2c-sirf.c writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY); base 80 drivers/i2c/busses/i2c-sprd.c void __iomem *base; base 94 drivers/i2c/busses/i2c-sprd.c writel(count, i2c_dev->base + I2C_COUNT); base 99 drivers/i2c/busses/i2c-sprd.c u32 tmp = readl(i2c_dev->base + I2C_CTL); base 102 drivers/i2c/busses/i2c-sprd.c writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL); base 104 drivers/i2c/busses/i2c-sprd.c writel(tmp | STP_EN, i2c_dev->base + I2C_CTL); base 109 drivers/i2c/busses/i2c-sprd.c u32 tmp = readl(i2c_dev->base + I2C_CTL); base 111 drivers/i2c/busses/i2c-sprd.c writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL); base 116 drivers/i2c/busses/i2c-sprd.c u32 tmp = readl(i2c_dev->base + I2C_STATUS); base 118 drivers/i2c/busses/i2c-sprd.c writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS); base 123 drivers/i2c/busses/i2c-sprd.c u32 tmp = readl(i2c_dev->base + I2C_STATUS); base 125 drivers/i2c/busses/i2c-sprd.c writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS); base 130 drivers/i2c/busses/i2c-sprd.c writel(I2C_RST, i2c_dev->base + ADDR_RST); base 135 drivers/i2c/busses/i2c-sprd.c writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG); base 143 drivers/i2c/busses/i2c-sprd.c writeb(buf[i], i2c_dev->base + I2C_TX); base 151 drivers/i2c/busses/i2c-sprd.c buf[i] = readb(i2c_dev->base + I2C_RX); base 156 drivers/i2c/busses/i2c-sprd.c u32 tmp = readl(i2c_dev->base + I2C_CTL); base 160 drivers/i2c/busses/i2c-sprd.c writel(tmp, i2c_dev->base + I2C_CTL); base 165 drivers/i2c/busses/i2c-sprd.c u32 tmp = readl(i2c_dev->base + I2C_CTL); base 169 drivers/i2c/busses/i2c-sprd.c writel(tmp, i2c_dev->base + I2C_CTL); base 174 drivers/i2c/busses/i2c-sprd.c u32 tmp = readl(i2c_dev->base + I2C_CTL); base 181 drivers/i2c/busses/i2c-sprd.c writel(tmp, i2c_dev->base + I2C_CTL); base 186 drivers/i2c/busses/i2c-sprd.c u32 tmp = readl(i2c_dev->base + I2C_CTL); base 193 drivers/i2c/busses/i2c-sprd.c writel(tmp, i2c_dev->base + I2C_CTL); base 198 drivers/i2c/busses/i2c-sprd.c u32 tmp = readl(i2c_dev->base + I2C_CTL); base 200 drivers/i2c/busses/i2c-sprd.c writel(tmp | I2C_START, i2c_dev->base + I2C_CTL); base 205 drivers/i2c/busses/i2c-sprd.c u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE; base 207 drivers/i2c/busses/i2c-sprd.c writel(cmd | rw << 3, i2c_dev->base + I2C_CTL); base 336 drivers/i2c/busses/i2c-sprd.c writel(div0, i2c_dev->base + ADDR_DVD0); base 337 drivers/i2c/busses/i2c-sprd.c writel(div1, i2c_dev->base + ADDR_DVD1); base 341 drivers/i2c/busses/i2c-sprd.c writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD); base 343 drivers/i2c/busses/i2c-sprd.c writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD); base 350 drivers/i2c/busses/i2c-sprd.c writel(tmp, i2c_dev->base + I2C_CTL); base 359 drivers/i2c/busses/i2c-sprd.c tmp = readl(i2c_dev->base + I2C_CTL); base 360 drivers/i2c/busses/i2c-sprd.c writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL); base 367 drivers/i2c/busses/i2c-sprd.c bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK); base 411 drivers/i2c/busses/i2c-sprd.c bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK); base 490 drivers/i2c/busses/i2c-sprd.c i2c_dev->base = devm_platform_ioremap_resource(pdev, 0); base 491 drivers/i2c/busses/i2c-sprd.c if (IS_ERR(i2c_dev->base)) base 492 drivers/i2c/busses/i2c-sprd.c return PTR_ERR(i2c_dev->base); base 186 drivers/i2c/busses/i2c-st.c void __iomem *base; base 244 drivers/i2c/busses/i2c-st.c if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR) base 247 drivers/i2c/busses/i2c-st.c count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) & base 251 drivers/i2c/busses/i2c-st.c readl_relaxed(i2c_dev->base + SSC_RBUF); base 262 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); base 263 drivers/i2c/busses/i2c-st.c st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); base 280 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_CLR); base 284 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_CTL); base 291 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_BRG); base 294 drivers/i2c/busses/i2c-st.c writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); base 297 drivers/i2c/busses/i2c-st.c writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C); base 301 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); base 305 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); base 309 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); base 313 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP); base 317 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP); base 321 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE); base 325 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_PRSCALER); base 326 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT); base 330 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH); base 334 drivers/i2c/busses/i2c-st.c writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT); base 352 drivers/i2c/busses/i2c-st.c writel_relaxed(0, i2c_dev->base + SSC_IEN); base 357 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl); base 359 drivers/i2c/busses/i2c-st.c st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM); base 362 drivers/i2c/busses/i2c-st.c writel_relaxed(0, i2c_dev->base + SSC_TBUF); base 364 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM); base 375 drivers/i2c/busses/i2c-st.c sta = readl_relaxed(i2c_dev->base + SSC_STA); base 402 drivers/i2c/busses/i2c-st.c writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF); base 418 drivers/i2c/busses/i2c-st.c sta = readl_relaxed(i2c_dev->base + SSC_STA); base 422 drivers/i2c/busses/i2c-st.c tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); base 448 drivers/i2c/busses/i2c-st.c sta = readl_relaxed(i2c_dev->base + SSC_STA); base 452 drivers/i2c/busses/i2c-st.c tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); base 470 drivers/i2c/busses/i2c-st.c sta = readl_relaxed(i2c_dev->base + SSC_STA); base 474 drivers/i2c/busses/i2c-st.c i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT); base 479 drivers/i2c/busses/i2c-st.c rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1; base 497 drivers/i2c/busses/i2c-st.c st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN); base 498 drivers/i2c/busses/i2c-st.c st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); base 501 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN); base 502 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); base 504 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN); base 505 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG); base 537 drivers/i2c/busses/i2c-st.c readl_relaxed(i2c_dev->base + SSC_RBUF); base 538 drivers/i2c/busses/i2c-st.c st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB); base 548 drivers/i2c/busses/i2c-st.c st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG); base 552 drivers/i2c/busses/i2c-st.c writel_relaxed(ien, i2c_dev->base + SSC_IEN); base 572 drivers/i2c/busses/i2c-st.c ien = readl_relaxed(i2c_dev->base + SSC_IEN); base 573 drivers/i2c/busses/i2c-st.c sta = readl_relaxed(i2c_dev->base + SSC_STA); base 593 drivers/i2c/busses/i2c-st.c writel_relaxed(0, i2c_dev->base + SSC_IEN); base 598 drivers/i2c/busses/i2c-st.c writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR); base 607 drivers/i2c/busses/i2c-st.c writel_relaxed(it, i2c_dev->base + SSC_IEN); base 609 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); base 614 drivers/i2c/busses/i2c-st.c writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR); base 617 drivers/i2c/busses/i2c-st.c writel_relaxed(it, i2c_dev->base + SSC_IEN); base 619 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); base 633 drivers/i2c/busses/i2c-st.c readl(i2c_dev->base + SSC_IEN); base 663 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl); base 668 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c); base 678 drivers/i2c/busses/i2c-st.c writel_relaxed(it, i2c_dev->base + SSC_IEN); base 685 drivers/i2c/busses/i2c-st.c st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); base 699 drivers/i2c/busses/i2c-st.c st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c); base 702 drivers/i2c/busses/i2c-st.c i2c_dev->base + SSC_CLR); base 821 drivers/i2c/busses/i2c-st.c i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); base 822 drivers/i2c/busses/i2c-st.c if (IS_ERR(i2c_dev->base)) base 823 drivers/i2c/busses/i2c-st.c return PTR_ERR(i2c_dev->base); base 126 drivers/i2c/busses/i2c-stm32f4.c void __iomem *base; base 146 drivers/i2c/busses/i2c-stm32f4.c void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; base 186 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); base 222 drivers/i2c/busses/i2c-stm32f4.c i2c_dev->base + STM32F4_I2C_TRISE); base 273 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR); base 293 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1); base 303 drivers/i2c/busses/i2c-stm32f4.c ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2, base 322 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR); base 344 drivers/i2c/busses/i2c-stm32f4.c rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR); base 356 drivers/i2c/busses/i2c-stm32f4.c reg = i2c_dev->base + STM32F4_I2C_CR1; base 372 drivers/i2c/busses/i2c-stm32f4.c void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; base 397 drivers/i2c/busses/i2c-stm32f4.c void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; base 451 drivers/i2c/busses/i2c-stm32f4.c reg = i2c_dev->base + STM32F4_I2C_CR1; base 460 drivers/i2c/busses/i2c-stm32f4.c reg = i2c_dev->base + STM32F4_I2C_CR2; base 472 drivers/i2c/busses/i2c-stm32f4.c reg = i2c_dev->base + STM32F4_I2C_CR1; base 496 drivers/i2c/busses/i2c-stm32f4.c readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); base 506 drivers/i2c/busses/i2c-stm32f4.c cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); base 508 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); base 510 drivers/i2c/busses/i2c-stm32f4.c readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); base 516 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); base 526 drivers/i2c/busses/i2c-stm32f4.c cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); base 529 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); base 531 drivers/i2c/busses/i2c-stm32f4.c readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); base 541 drivers/i2c/busses/i2c-stm32f4.c cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); base 544 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); base 546 drivers/i2c/busses/i2c-stm32f4.c readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); base 563 drivers/i2c/busses/i2c-stm32f4.c cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2); base 570 drivers/i2c/busses/i2c-stm32f4.c status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); base 588 drivers/i2c/busses/i2c-stm32f4.c readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); base 595 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); base 635 drivers/i2c/busses/i2c-stm32f4.c status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); base 640 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); base 650 drivers/i2c/busses/i2c-stm32f4.c reg = i2c_dev->base + STM32F4_I2C_CR1; base 654 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); base 661 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); base 683 drivers/i2c/busses/i2c-stm32f4.c void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1; base 698 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask); base 771 drivers/i2c/busses/i2c-stm32f4.c i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); base 772 drivers/i2c/busses/i2c-stm32f4.c if (IS_ERR(i2c_dev->base)) base 773 drivers/i2c/busses/i2c-stm32f4.c return PTR_ERR(i2c_dev->base); base 289 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base; base 373 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); base 623 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 626 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); base 651 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); base 655 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, base 658 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, base 660 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, base 667 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 670 drivers/i2c/busses/i2c-stm32f7.c writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); base 678 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 681 drivers/i2c/busses/i2c-stm32f7.c *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); base 685 drivers/i2c/busses/i2c-stm32f7.c readb_relaxed(base + STM32F7_I2C_RXDR); base 697 drivers/i2c/busses/i2c-stm32f7.c cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); base 707 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); base 727 drivers/i2c/busses/i2c-stm32f7.c cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); base 730 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); base 739 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, base 752 drivers/i2c/busses/i2c-stm32f7.c ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, base 774 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 786 drivers/i2c/busses/i2c-stm32f7.c cr1 = readl_relaxed(base + STM32F7_I2C_CR1); base 787 drivers/i2c/busses/i2c-stm32f7.c cr2 = readl_relaxed(base + STM32F7_I2C_CR2); base 854 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(cr1, base + STM32F7_I2C_CR1); base 855 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(cr2, base + STM32F7_I2C_CR2); base 864 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 871 drivers/i2c/busses/i2c-stm32f7.c cr2 = readl_relaxed(base + STM32F7_I2C_CR2); base 872 drivers/i2c/busses/i2c-stm32f7.c cr1 = readl_relaxed(base + STM32F7_I2C_CR1); base 1020 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(cr1, base + STM32F7_I2C_CR1); base 1021 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(cr2, base + STM32F7_I2C_CR2); base 1029 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 1033 drivers/i2c/busses/i2c-stm32f7.c cr2 = readl_relaxed(base + STM32F7_I2C_CR2); base 1034 drivers/i2c/busses/i2c-stm32f7.c cr1 = readl_relaxed(base + STM32F7_I2C_CR1); base 1104 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(cr1, base + STM32F7_I2C_CR1); base 1105 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(cr2, base + STM32F7_I2C_CR2); base 1113 drivers/i2c/busses/i2c-stm32f7.c internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); base 1172 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 1185 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); base 1188 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); base 1193 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); base 1196 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(value, base + STM32F7_I2C_TXDR); base 1203 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); base 1213 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); base 1219 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 1223 drivers/i2c/busses/i2c-stm32f7.c isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); base 1237 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(mask, base + STM32F7_I2C_ICR); base 1311 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 1316 drivers/i2c/busses/i2c-stm32f7.c status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); base 1325 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(val, base + STM32F7_I2C_TXDR); base 1334 drivers/i2c/busses/i2c-stm32f7.c val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); base 1339 drivers/i2c/busses/i2c-stm32f7.c cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); base 1341 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); base 1344 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); base 1351 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); base 1365 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); base 1369 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); base 1388 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 1398 drivers/i2c/busses/i2c-stm32f7.c status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); base 1411 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); base 1425 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); base 1439 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); base 1481 drivers/i2c/busses/i2c-stm32f7.c status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); base 1503 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 1508 drivers/i2c/busses/i2c-stm32f7.c status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); base 1513 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); base 1521 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); base 1527 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); base 1677 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 1702 drivers/i2c/busses/i2c-stm32f7.c oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); base 1712 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); base 1715 drivers/i2c/busses/i2c-stm32f7.c oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); base 1725 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); base 1732 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK); base 1737 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); base 1750 drivers/i2c/busses/i2c-stm32f7.c void __iomem *base = i2c_dev->base; base 1766 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); base 1769 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); base 1841 drivers/i2c/busses/i2c-stm32f7.c i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); base 1842 drivers/i2c/busses/i2c-stm32f7.c if (IS_ERR(i2c_dev->base)) base 1843 drivers/i2c/busses/i2c-stm32f7.c return PTR_ERR(i2c_dev->base); base 140 drivers/i2c/busses/i2c-synquacer.c void __iomem *base; base 184 drivers/i2c/busses/i2c-synquacer.c writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR); base 204 drivers/i2c/busses/i2c-synquacer.c writeb(0, i2c->base + SYNQUACER_I2C_REG_ADR); base 208 drivers/i2c/busses/i2c-synquacer.c i2c->base + SYNQUACER_I2C_REG_FSR); base 223 drivers/i2c/busses/i2c-synquacer.c i2c->base + SYNQUACER_I2C_REG_CCR); base 224 drivers/i2c/busses/i2c-synquacer.c writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR); base 237 drivers/i2c/busses/i2c-synquacer.c i2c->base + SYNQUACER_I2C_REG_CCR); base 238 drivers/i2c/busses/i2c-synquacer.c writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR); base 245 drivers/i2c/busses/i2c-synquacer.c writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR); base 246 drivers/i2c/busses/i2c-synquacer.c writeb(0, i2c->base + SYNQUACER_I2C_REG_BC2R); base 252 drivers/i2c/busses/i2c-synquacer.c writeb(0, i2c->base + SYNQUACER_I2C_REG_CCR); base 253 drivers/i2c/busses/i2c-synquacer.c writeb(0, i2c->base + SYNQUACER_I2C_REG_CSR); base 263 drivers/i2c/busses/i2c-synquacer.c writeb(i2c_8bit_addr_from_msg(pmsg), i2c->base + SYNQUACER_I2C_REG_DAR); base 268 drivers/i2c/busses/i2c-synquacer.c bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); base 269 drivers/i2c/busses/i2c-synquacer.c bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); base 281 drivers/i2c/busses/i2c-synquacer.c i2c->base + SYNQUACER_I2C_REG_BCR); base 291 drivers/i2c/busses/i2c-synquacer.c i2c->base + SYNQUACER_I2C_REG_BCR); base 297 drivers/i2c/busses/i2c-synquacer.c bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); base 298 drivers/i2c/busses/i2c-synquacer.c bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); base 318 drivers/i2c/busses/i2c-synquacer.c bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); base 365 drivers/i2c/busses/i2c-synquacer.c bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); base 366 drivers/i2c/busses/i2c-synquacer.c bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR); base 413 drivers/i2c/busses/i2c-synquacer.c i2c->base + SYNQUACER_I2C_REG_DAR); base 419 drivers/i2c/busses/i2c-synquacer.c i2c->base + SYNQUACER_I2C_REG_BCR); base 443 drivers/i2c/busses/i2c-synquacer.c byte = readb(i2c->base + SYNQUACER_I2C_REG_DAR); base 454 drivers/i2c/busses/i2c-synquacer.c i2c->base + SYNQUACER_I2C_REG_BCR); base 462 drivers/i2c/busses/i2c-synquacer.c i2c->base + SYNQUACER_I2C_REG_BCR); base 578 drivers/i2c/busses/i2c-synquacer.c i2c->base = devm_ioremap_resource(&pdev->dev, r); base 579 drivers/i2c/busses/i2c-synquacer.c if (IS_ERR(i2c->base)) base 580 drivers/i2c/busses/i2c-synquacer.c return PTR_ERR(i2c->base); base 259 drivers/i2c/busses/i2c-tegra.c void __iomem *base; base 287 drivers/i2c/busses/i2c-tegra.c writel(val, i2c_dev->base + reg); base 292 drivers/i2c/busses/i2c-tegra.c return readl(i2c_dev->base + reg); base 310 drivers/i2c/busses/i2c-tegra.c writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); base 314 drivers/i2c/busses/i2c-tegra.c readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); base 319 drivers/i2c/busses/i2c-tegra.c return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); base 325 drivers/i2c/busses/i2c-tegra.c writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); base 331 drivers/i2c/busses/i2c-tegra.c readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); base 688 drivers/i2c/busses/i2c-tegra.c addr = i2c_dev->base + reg_offset; base 1515 drivers/i2c/busses/i2c-tegra.c void __iomem *base; base 1522 drivers/i2c/busses/i2c-tegra.c base = devm_ioremap_resource(&pdev->dev, res); base 1523 drivers/i2c/busses/i2c-tegra.c if (IS_ERR(base)) base 1524 drivers/i2c/busses/i2c-tegra.c return PTR_ERR(base); base 1545 drivers/i2c/busses/i2c-tegra.c i2c_dev->base = base; base 26 drivers/i2c/busses/i2c-versatile.c void __iomem *base; base 33 drivers/i2c/busses/i2c-versatile.c writel(SDA, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC)); base 40 drivers/i2c/busses/i2c-versatile.c writel(SCL, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC)); base 46 drivers/i2c/busses/i2c-versatile.c return !!(readl(i2c->base + I2C_CONTROL) & SDA); base 52 drivers/i2c/busses/i2c-versatile.c return !!(readl(i2c->base + I2C_CONTROL) & SCL); base 75 drivers/i2c/busses/i2c-versatile.c i2c->base = devm_ioremap_resource(&dev->dev, r); base 76 drivers/i2c/busses/i2c-versatile.c if (IS_ERR(i2c->base)) base 77 drivers/i2c/busses/i2c-versatile.c return PTR_ERR(i2c->base); base 79 drivers/i2c/busses/i2c-versatile.c writel(SCL | SDA, i2c->base + I2C_CONTROLS); base 88 drivers/i2c/busses/i2c-via.c u16 base; base 101 drivers/i2c/busses/i2c-via.c base = PM_CFG_IOBASE0; base 105 drivers/i2c/busses/i2c-via.c base = PM_CFG_IOBASE1; base 109 drivers/i2c/busses/i2c-via.c base = PM_CFG_IOBASE1; base 113 drivers/i2c/busses/i2c-via.c pci_read_config_word(dev, base, &pm_io_base); base 86 drivers/i2c/busses/i2c-wmt.c void __iomem *base; base 98 drivers/i2c/busses/i2c-wmt.c while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { base 143 drivers/i2c/busses/i2c-wmt.c writew(0, i2c_dev->base + REG_CDR); base 145 drivers/i2c/busses/i2c-wmt.c writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); base 149 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); base 151 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); base 153 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); base 155 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); base 167 drivers/i2c/busses/i2c-wmt.c writew(tcr_val, i2c_dev->base + REG_TCR); base 170 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); base 172 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); base 188 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CSR); base 196 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); base 202 drivers/i2c/busses/i2c-wmt.c writew(CR_ENABLE, i2c_dev->base + REG_CR); base 204 drivers/i2c/busses/i2c-wmt.c writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base + base 206 drivers/i2c/busses/i2c-wmt.c writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR); base 228 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); base 230 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); base 232 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); base 234 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); base 237 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); base 239 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); base 243 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); base 245 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); base 257 drivers/i2c/busses/i2c-wmt.c writew(tcr_val, i2c_dev->base + REG_TCR); base 260 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); base 262 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); base 276 drivers/i2c/busses/i2c-wmt.c pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8; base 280 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); base 282 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); base 284 drivers/i2c/busses/i2c-wmt.c val = readw(i2c_dev->base + REG_CR); base 286 drivers/i2c/busses/i2c-wmt.c writew(val, i2c_dev->base + REG_CR); base 329 drivers/i2c/busses/i2c-wmt.c i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR); base 330 drivers/i2c/busses/i2c-wmt.c writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR); base 354 drivers/i2c/busses/i2c-wmt.c writew(0, i2c_dev->base + REG_CR); base 355 drivers/i2c/busses/i2c-wmt.c writew(MCR_APB_166M, i2c_dev->base + REG_MCR); base 356 drivers/i2c/busses/i2c-wmt.c writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); base 357 drivers/i2c/busses/i2c-wmt.c writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR); base 358 drivers/i2c/busses/i2c-wmt.c writew(CR_ENABLE, i2c_dev->base + REG_CR); base 359 drivers/i2c/busses/i2c-wmt.c readw(i2c_dev->base + REG_CSR); /* read clear */ base 360 drivers/i2c/busses/i2c-wmt.c writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); base 363 drivers/i2c/busses/i2c-wmt.c writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR); base 365 drivers/i2c/busses/i2c-wmt.c writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR); base 384 drivers/i2c/busses/i2c-wmt.c i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); base 385 drivers/i2c/busses/i2c-wmt.c if (IS_ERR(i2c_dev->base)) base 386 drivers/i2c/busses/i2c-wmt.c return PTR_ERR(i2c_dev->base); base 444 drivers/i2c/busses/i2c-wmt.c writew(0, i2c_dev->base + REG_IMR); base 63 drivers/i2c/busses/i2c-xiic.c void __iomem *base; base 181 drivers/i2c/busses/i2c-xiic.c iowrite8(value, i2c->base + reg); base 183 drivers/i2c/busses/i2c-xiic.c iowrite8(value, i2c->base + reg + 3); base 191 drivers/i2c/busses/i2c-xiic.c ret = ioread8(i2c->base + reg); base 193 drivers/i2c/busses/i2c-xiic.c ret = ioread8(i2c->base + reg + 3); base 200 drivers/i2c/busses/i2c-xiic.c iowrite16(value, i2c->base + reg); base 202 drivers/i2c/busses/i2c-xiic.c iowrite16be(value, i2c->base + reg + 2); base 208 drivers/i2c/busses/i2c-xiic.c iowrite32(value, i2c->base + reg); base 210 drivers/i2c/busses/i2c-xiic.c iowrite32be(value, i2c->base + reg); base 218 drivers/i2c/busses/i2c-xiic.c ret = ioread32(i2c->base + reg); base 220 drivers/i2c/busses/i2c-xiic.c ret = ioread32be(i2c->base + reg); base 739 drivers/i2c/busses/i2c-xiic.c i2c->base = devm_ioremap_resource(&pdev->dev, res); base 740 drivers/i2c/busses/i2c-xiic.c if (IS_ERR(i2c->base)) base 741 drivers/i2c/busses/i2c-xiic.c return PTR_ERR(i2c->base); base 94 drivers/i2c/busses/i2c-xlp9xx.c u32 __iomem *base; base 106 drivers/i2c/busses/i2c-xlp9xx.c writel(val, priv->base + reg); base 112 drivers/i2c/busses/i2c-xlp9xx.c return readl(priv->base + reg); base 515 drivers/i2c/busses/i2c-xlp9xx.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 516 drivers/i2c/busses/i2c-xlp9xx.c if (IS_ERR(priv->base)) base 517 drivers/i2c/busses/i2c-xlp9xx.c return PTR_ERR(priv->base); base 64 drivers/i2c/busses/i2c-xlr.c static inline void xlr_i2c_wreg(u32 __iomem *base, unsigned int reg, u32 val) base 66 drivers/i2c/busses/i2c-xlr.c __raw_writel(val, base + reg); base 69 drivers/i2c/busses/i2c-xlr.c static inline u32 xlr_i2c_rdreg(u32 __iomem *base, unsigned int reg) base 71 drivers/i2c/busses/i2c-xlr.c return __raw_readl(base + reg); base 36 drivers/i2c/busses/scx200_acb.c static int base[MAX_DEVICES] = { 0x820, 0x840 }; base 37 drivers/i2c/busses/scx200_acb.c module_param_hw_array(base, int, ioport, NULL, 0); base 38 drivers/i2c/busses/scx200_acb.c MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers"); base 66 drivers/i2c/busses/scx200_acb.c unsigned base; base 80 drivers/i2c/busses/scx200_acb.c #define ACBSDA (iface->base + 0) base 81 drivers/i2c/busses/scx200_acb.c #define ACBST (iface->base + 1) base 87 drivers/i2c/busses/scx200_acb.c #define ACBCST (iface->base + 2) base 89 drivers/i2c/busses/scx200_acb.c #define ACBCTL1 (iface->base + 3) base 95 drivers/i2c/busses/scx200_acb.c #define ACBADDR (iface->base + 4) base 96 drivers/i2c/busses/scx200_acb.c #define ACBCTL2 (iface->base + 5) base 470 drivers/i2c/busses/scx200_acb.c unsigned long base, int index, struct device *dev) base 480 drivers/i2c/busses/scx200_acb.c if (!request_region(base, 8, iface->adapter.name)) { base 481 drivers/i2c/busses/scx200_acb.c pr_err("can't allocate io 0x%lx-0x%lx\n", base, base + 8 - 1); base 485 drivers/i2c/busses/scx200_acb.c iface->base = base; base 491 drivers/i2c/busses/scx200_acb.c release_region(base, 8); base 522 drivers/i2c/busses/scx200_acb.c release_region(iface->base, 8); base 558 drivers/i2c/busses/scx200_acb.c if (base[i] == 0) base 562 drivers/i2c/busses/scx200_acb.c scx200_create_dev("SCx200", base[i], i, NULL); base 160 drivers/i2c/muxes/i2c-mux-ltc4306.c data->gpiochip.base = -1; base 603 drivers/i3c/master.c dev->addr = boardinfo->base.addr; base 678 drivers/i3c/master.c if (dev->boardinfo->base.addr == addr) base 1644 drivers/i3c/master.c i2cboardinfo->base.addr); base 1651 drivers/i3c/master.c i2cboardinfo->base.addr, base 1946 drivers/i3c/master.c ret = of_i2c_get_board_info(dev, node, &boardinfo->base); base 1955 drivers/i3c/master.c if (boardinfo->base.flags & I2C_CLIENT_TEN) { base 2141 drivers/i3c/master.c i2cdev->dev = i2c_new_device(adap, &i2cdev->boardinfo->base); base 2216 drivers/i3c/master.c struct i3c_ibi_slot base; base 2301 drivers/i3c/master.c i3c_master_init_ibi_slot(dev, &slot->base); base 2304 drivers/i3c/master.c slot->base.data = pool->payload_buf + base 2342 drivers/i3c/master.c return slot ? &slot->base : NULL; base 2363 drivers/i3c/master.c slot = container_of(s, struct i3c_generic_ibi_slot, base); base 228 drivers/i3c/master/dw-i3c-master.c struct i3c_master_controller base; base 298 drivers/i3c/master/dw-i3c-master.c return container_of(master, struct dw_i3c_master, base); base 638 drivers/i3c/master/dw-i3c-master.c ret = i3c_master_set_info(&master->base, &info); base 1155 drivers/i3c/master/dw-i3c-master.c ret = i3c_master_register(&master->base, &pdev->dev, base 1176 drivers/i3c/master/dw-i3c-master.c ret = i3c_master_unregister(&master->base); base 393 drivers/i3c/master/i3c-master-cdns.c struct i3c_master_controller base; base 416 drivers/i3c/master/i3c-master-cdns.c return container_of(master, struct cdns_i3c_master, base); base 1056 drivers/i3c/master/i3c-master-cdns.c struct i3c_master_controller *m = &master->base; base 1149 drivers/i3c/master/i3c-master-cdns.c ret = i3c_master_entdaa_locked(&master->base); base 1173 drivers/i3c/master/i3c-master-cdns.c i3c_master_defslvs_locked(&master->base); base 1256 drivers/i3c/master/i3c-master-cdns.c ret = i3c_master_set_info(&master->base, &info); base 1346 drivers/i3c/master/i3c-master-cdns.c queue_work(master->base.wq, &master->hj_work); base 1521 drivers/i3c/master/i3c-master-cdns.c i3c_master_do_daa(&master->base); base 1603 drivers/i3c/master/i3c-master-cdns.c ret = i3c_master_register(&master->base, &pdev->dev, base 1624 drivers/i3c/master/i3c-master-cdns.c ret = i3c_master_unregister(&master->base); base 470 drivers/ide/alim15x3.c unsigned long base = ide_pci_dma_base(hwif, d); base 472 drivers/ide/alim15x3.c if (base == 0) base 475 drivers/ide/alim15x3.c hwif->dma_base = base; base 484 drivers/ide/alim15x3.c outb(inb(base + 2) & 0x60, base + 2); base 487 drivers/ide/alim15x3.c hwif->name, base, base + 7); base 121 drivers/ide/buddha.c static void __init buddha_setup_ports(struct ide_hw *hw, unsigned long base, base 128 drivers/ide/buddha.c hw->io_ports.data_addr = base; base 131 drivers/ide/buddha.c hw->io_ports_array[i] = base + 2 + i * 4; base 212 drivers/ide/buddha.c unsigned long base, ctl, irq_port; base 215 drivers/ide/buddha.c base = buddha_board + buddha_bases[i]; base 216 drivers/ide/buddha.c ctl = base + BUDDHA_CONTROL; base 219 drivers/ide/buddha.c base = buddha_board + xsurf_bases[i]; base 225 drivers/ide/buddha.c buddha_setup_ports(&hw[i], base, ctl, irq_port); base 699 drivers/ide/cmd640.c static int __init cmd640x_init_one(unsigned long base, unsigned long ctl) base 701 drivers/ide/cmd640.c if (!request_region(base, 8, DRV_NAME)) { base 703 drivers/ide/cmd640.c DRV_NAME, base, base + 7); base 710 drivers/ide/cmd640.c release_region(base, 8); base 194 drivers/ide/cmd64x.c unsigned long base = pci_resource_start(dev, 4); base 197 drivers/ide/cmd64x.c u8 mrdmode = inb(base + 1); base 201 drivers/ide/cmd64x.c base + 1); base 221 drivers/ide/cmd64x.c unsigned long base = pci_resource_start(dev, 4); base 224 drivers/ide/cmd64x.c u8 mrdmode = inb(base + 1); base 51 drivers/ide/delkin_cb.c unsigned long base = pci_resource_start(dev, 0); base 54 drivers/ide/delkin_cb.c outb(0x02, base + 0x1e); /* set nIEN to block interrupts */ base 55 drivers/ide/delkin_cb.c inb(base + 0x17); /* read status to clear interrupts */ base 59 drivers/ide/delkin_cb.c outb(setup[i], base + i); base 77 drivers/ide/delkin_cb.c unsigned long base; base 92 drivers/ide/delkin_cb.c base = pci_resource_start(dev, 0); base 97 drivers/ide/delkin_cb.c ide_std_init_ports(&hw, base + 0x10, base + 0x1e); base 79 drivers/ide/gayle.c static void __init gayle_setup_ports(struct ide_hw *hw, unsigned long base, base 86 drivers/ide/gayle.c hw->io_ports.data_addr = base; base 89 drivers/ide/gayle.c hw->io_ports_array[i] = base + 2 + i * 4; base 121 drivers/ide/gayle.c unsigned long base, ctrlport, irqport; base 140 drivers/ide/gayle.c base = (unsigned long)ZTWO_VADDR(pdata->base); base 148 drivers/ide/gayle.c for (i = 0; i < GAYLE_NUM_PROBE_HWIFS; i++, base += GAYLE_NEXT_PORT) { base 150 drivers/ide/gayle.c ctrlport = base + GAYLE_CONTROL; base 152 drivers/ide/gayle.c gayle_setup_ports(&hw[i], base, ctrlport, irqport); base 798 drivers/ide/hpt366.c unsigned long base = hwif->extra_base; base 799 drivers/ide/hpt366.c u8 scr2 = inb(base + 0x6b); base 805 drivers/ide/hpt366.c outb(0x80, base + 0x63); base 806 drivers/ide/hpt366.c outb(0x80, base + 0x67); base 809 drivers/ide/hpt366.c outb(mode, base + 0x6b); base 810 drivers/ide/hpt366.c outb(0xc0, base + 0x69); base 816 drivers/ide/hpt366.c outb(inb(base + 0x60) | 0x32, base + 0x60); base 817 drivers/ide/hpt366.c outb(inb(base + 0x64) | 0x32, base + 0x64); base 820 drivers/ide/hpt366.c outb(0x00, base + 0x69); base 823 drivers/ide/hpt366.c outb(0x00, base + 0x63); base 824 drivers/ide/hpt366.c outb(0x00, base + 0x67); base 1225 drivers/ide/hpt366.c unsigned long flags, base = ide_pci_dma_base(hwif, d); base 1228 drivers/ide/hpt366.c if (base == 0) base 1231 drivers/ide/hpt366.c hwif->dma_base = base; base 1239 drivers/ide/hpt366.c dma_old = inb(base + 2); base 1250 drivers/ide/hpt366.c outb(dma_new, base + 2); base 1255 drivers/ide/hpt366.c hwif->name, base, base + 7); base 1257 drivers/ide/hpt366.c hwif->extra_base = base + (hwif->channel ? 8 : 16); base 118 drivers/ide/icside.c void __iomem *base = state->irq_port; base 124 drivers/ide/icside.c writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); base 125 drivers/ide/icside.c readb(base + ICS_ARCIN_V6_INTROFFSET_2); base 128 drivers/ide/icside.c writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); base 129 drivers/ide/icside.c readb(base + ICS_ARCIN_V6_INTROFFSET_1); base 386 drivers/ide/icside.c static void icside_setup_ports(struct ide_hw *hw, void __iomem *base, base 389 drivers/ide/icside.c unsigned long port = (unsigned long)base + info->dataoffset; base 399 drivers/ide/icside.c hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset; base 413 drivers/ide/icside.c void __iomem *base; base 418 drivers/ide/icside.c base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); base 419 drivers/ide/icside.c if (!base) base 422 drivers/ide/icside.c state->irq_port = base; base 424 drivers/ide/icside.c ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; base 434 drivers/ide/icside.c icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec); base 34 drivers/ide/ide-4drives.c unsigned long base = 0x1f0, ctl = 0x3f6; base 40 drivers/ide/ide-4drives.c if (!request_region(base, 8, DRV_NAME)) { base 42 drivers/ide/ide-4drives.c DRV_NAME, base, base + 7); base 49 drivers/ide/ide-4drives.c release_region(base, 8); base 55 drivers/ide/ide-4drives.c ide_std_init_ports(&hw, base, ctl); base 237 drivers/ide/ide-dma.c static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode) base 244 drivers/ide/ide-dma.c switch (base) { base 10 drivers/ide/ide-legacy.c unsigned long base, ctl; base 14 drivers/ide/ide-legacy.c base = 0x1f0; base 18 drivers/ide/ide-legacy.c base = 0x170; base 23 drivers/ide/ide-legacy.c if (!request_region(base, 8, d->name)) { base 25 drivers/ide/ide-legacy.c d->name, base, base + 7); base 32 drivers/ide/ide-legacy.c release_region(base, 8); base 36 drivers/ide/ide-legacy.c ide_std_init_ports(hw, base, ctl); base 31 drivers/ide/ide-pnp.c unsigned long base, ctl; base 40 drivers/ide/ide-pnp.c base = pnp_port_start(dev, 0); base 43 drivers/ide/ide-pnp.c if (!request_region(base, 8, DRV_NAME)) { base 45 drivers/ide/ide-pnp.c DRV_NAME, base, base + 7); base 52 drivers/ide/ide-pnp.c release_region(base, 8); base 57 drivers/ide/ide-pnp.c ide_std_init_ports(&hw, base, ctl); base 69 drivers/ide/ide-pnp.c release_region(base, 8); base 21 drivers/ide/ide_platform.c static void plat_ide_setup_ports(struct ide_hw *hw, void __iomem *base, base 25 drivers/ide/ide_platform.c unsigned long port = (unsigned long)base; base 48 drivers/ide/ide_platform.c void __iomem *base, *alt_base; base 78 drivers/ide/ide_platform.c base = devm_ioremap(&pdev->dev, base 83 drivers/ide/ide_platform.c base = devm_ioport_map(&pdev->dev, base 90 drivers/ide/ide_platform.c plat_ide_setup_ports(&hw, base, alt_base, pdata, res_irq->start); base 69 drivers/ide/macide.c static void __init macide_setup_ports(struct ide_hw *hw, unsigned long base, base 77 drivers/ide/macide.c hw->io_ports_array[i] = base + i * 4; base 79 drivers/ide/macide.c hw->io_ports.ctl_addr = base + IDE_CONTROL; base 105 drivers/ide/macide.c unsigned long base; base 115 drivers/ide/macide.c base = IDE_BASE; base 119 drivers/ide/macide.c base = IDE_BASE; base 123 drivers/ide/macide.c base = BABOON_BASE; base 134 drivers/ide/macide.c macide_setup_ports(&hw, base, irq); base 64 drivers/ide/palm_bk3710.c static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev, base 79 drivers/ide/palm_bk3710.c val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); base 81 drivers/ide/palm_bk3710.c writel(val32, base + BK3710_UDMASTB); base 84 drivers/ide/palm_bk3710.c val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); base 86 drivers/ide/palm_bk3710.c writel(val32, base + BK3710_UDMATRP); base 89 drivers/ide/palm_bk3710.c val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); base 91 drivers/ide/palm_bk3710.c writel(val32, base + BK3710_UDMAENV); base 94 drivers/ide/palm_bk3710.c val16 = readw(base + BK3710_UDMACTL) | (1 << dev); base 95 drivers/ide/palm_bk3710.c writew(val16, base + BK3710_UDMACTL); base 98 drivers/ide/palm_bk3710.c static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev, base 117 drivers/ide/palm_bk3710.c val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8)); base 119 drivers/ide/palm_bk3710.c writel(val32, base + BK3710_DMASTB); base 121 drivers/ide/palm_bk3710.c val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8)); base 123 drivers/ide/palm_bk3710.c writel(val32, base + BK3710_DMARCVR); base 126 drivers/ide/palm_bk3710.c val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev); base 127 drivers/ide/palm_bk3710.c writew(val16, base + BK3710_UDMACTL); base 130 drivers/ide/palm_bk3710.c static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate, base 147 drivers/ide/palm_bk3710.c val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8)); base 149 drivers/ide/palm_bk3710.c writel(val32, base + BK3710_DATSTB); base 151 drivers/ide/palm_bk3710.c val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8)); base 153 drivers/ide/palm_bk3710.c writel(val32, base + BK3710_DATRCVR); base 169 drivers/ide/palm_bk3710.c val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8)); base 171 drivers/ide/palm_bk3710.c writel(val32, base + BK3710_REGSTB); base 173 drivers/ide/palm_bk3710.c val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8)); base 175 drivers/ide/palm_bk3710.c writel(val32, base + BK3710_REGRCVR); base 181 drivers/ide/palm_bk3710.c void __iomem *base = (void __iomem *)hwif->dma_base; base 185 drivers/ide/palm_bk3710.c palm_bk3710_setudmamode(base, is_slave, base 188 drivers/ide/palm_bk3710.c palm_bk3710_setdmamode(base, is_slave, base 199 drivers/ide/palm_bk3710.c void __iomem *base = (void __iomem *)hwif->dma_base; base 207 drivers/ide/palm_bk3710.c palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio); base 210 drivers/ide/palm_bk3710.c static void palm_bk3710_chipinit(void __iomem *base) base 229 drivers/ide/palm_bk3710.c writew(BIT(15), base + BK3710_IDETIMP); base 237 drivers/ide/palm_bk3710.c writew(0, base + BK3710_UDMACTL); base 245 drivers/ide/palm_bk3710.c writel(0x001, base + BK3710_MISCCTL); base 251 drivers/ide/palm_bk3710.c writel(0xFFFF, base + BK3710_IORDYTMP); base 261 drivers/ide/palm_bk3710.c writew(0, base + BK3710_BMISP); base 263 drivers/ide/palm_bk3710.c palm_bk3710_setpiomode(base, NULL, 0, 600, 0); base 264 drivers/ide/palm_bk3710.c palm_bk3710_setpiomode(base, NULL, 1, 600, 0); base 304 drivers/ide/palm_bk3710.c void __iomem *base; base 339 drivers/ide/palm_bk3710.c base = ioremap(mem->start, mem_size); base 340 drivers/ide/palm_bk3710.c if (!base) { base 347 drivers/ide/palm_bk3710.c palm_bk3710_chipinit(base); base 352 drivers/ide/palm_bk3710.c (base + IDE_PALM_ATA_PRI_REG_OFFSET + i); base 354 drivers/ide/palm_bk3710.c (base + IDE_PALM_ATA_PRI_CTL_OFFSET); base 1117 drivers/ide/pmac.c static void pmac_ide_init_ports(struct ide_hw *hw, unsigned long base) base 1122 drivers/ide/pmac.c hw->io_ports_array[i] = base + i * 0x10; base 1124 drivers/ide/pmac.c hw->io_ports.ctl_addr = base + 0x160; base 1133 drivers/ide/pmac.c void __iomem *base; base 1170 drivers/ide/pmac.c base = ioremap(macio_resource_start(mdev, 0), 0x400); base 1171 drivers/ide/pmac.c regbase = (unsigned long) base; base 1201 drivers/ide/pmac.c iounmap(base); base 1256 drivers/ide/pmac.c void __iomem *base; base 1292 drivers/ide/pmac.c base = ioremap(rbase, rlen); base 1293 drivers/ide/pmac.c pmif->regbase = (unsigned long) base + 0x2000; base 1294 drivers/ide/pmac.c pmif->dma_regs = base + 0x1000; base 1295 drivers/ide/pmac.c pmif->kauai_fcr = base; base 1308 drivers/ide/pmac.c iounmap(base); base 40 drivers/ide/q40ide.c static int q40ide_default_irq(unsigned long base) base 42 drivers/ide/q40ide.c switch (base) { base 55 drivers/ide/q40ide.c static void q40_ide_setup_ports(struct ide_hw *hw, unsigned long base, int irq) base 60 drivers/ide/q40ide.c hw->io_ports.data_addr = Q40_ISA_IO_W(base); base 61 drivers/ide/q40ide.c hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1); base 62 drivers/ide/q40ide.c hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2); base 63 drivers/ide/q40ide.c hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3); base 64 drivers/ide/q40ide.c hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4); base 65 drivers/ide/q40ide.c hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5); base 66 drivers/ide/q40ide.c hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6); base 67 drivers/ide/q40ide.c hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7); base 68 drivers/ide/q40ide.c hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206); base 219 drivers/ide/qd65xx.c u8 base = (hwif->config_data & 0xff00) >> 8; base 293 drivers/ide/qd65xx.c u8 base = (hwif->config_data & 0xff00) >> 8; base 303 drivers/ide/qd65xx.c u8 base = (hwif->config_data & 0xff00) >> 8; base 355 drivers/ide/qd65xx.c static int __init qd_probe(int base) base 363 drivers/ide/qd65xx.c if (! ((config & QD_CONFIG_BASEPORT) >> 1 == (base == 0xb0)) ) base 373 drivers/ide/qd65xx.c if (qd_testreg(base)) base 381 drivers/ide/qd65xx.c printk(KERN_NOTICE "qd6500 at %#x\n", base); base 390 drivers/ide/qd65xx.c if (qd_testreg(base) || qd_testreg(base + 0x02)) base 395 drivers/ide/qd65xx.c printk(KERN_NOTICE "qd6580 at %#x\n", base); base 412 drivers/ide/qd65xx.c rc = ide_legacy_device_add(&d, (base << 8) | config); base 16 drivers/ide/qd65xx.h #define QD_TIM1_PORT (base) base 17 drivers/ide/qd65xx.h #define QD_CONFIG_PORT (base+0x01) base 18 drivers/ide/qd65xx.h #define QD_TIM2_PORT (base+0x02) base 19 drivers/ide/qd65xx.h #define QD_CONTROL_PORT (base+0x03) base 19 drivers/ide/rapide.c static void rapide_setup_ports(struct ide_hw *hw, void __iomem *base, base 22 drivers/ide/rapide.c unsigned long port = (unsigned long)base; base 35 drivers/ide/rapide.c void __iomem *base; base 44 drivers/ide/rapide.c base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); base 45 drivers/ide/rapide.c if (!base) { base 51 drivers/ide/rapide.c rapide_setup_ports(&hw, base, base + 0x818, 1 << 6, ec->irq); base 311 drivers/ide/setup-pci.c unsigned long ctl = 0, base = 0; base 323 drivers/ide/setup-pci.c base = pci_resource_start(dev, 2*port); base 327 drivers/ide/setup-pci.c base = port ? 0x170 : 0x1f0; base 330 drivers/ide/setup-pci.c if (!base || !ctl) { base 338 drivers/ide/setup-pci.c ide_std_init_ports(hw, base, ctl | 2); base 361 drivers/ide/setup-pci.c unsigned long base = ide_pci_dma_base(hwif, d); base 363 drivers/ide/setup-pci.c if (base == 0) base 366 drivers/ide/setup-pci.c hwif->dma_base = base; base 381 drivers/ide/setup-pci.c hwif->name, base, base + 7); base 383 drivers/ide/setup-pci.c hwif->extra_base = base + (hwif->channel ? 8 : 16); base 94 drivers/ide/siimage.c unsigned long base = (unsigned long)hwif->hwif_data; base 96 drivers/ide/siimage.c base += 0xA0 + r; base 98 drivers/ide/siimage.c base += hwif->channel << 6; base 100 drivers/ide/siimage.c base += hwif->channel << 4; base 101 drivers/ide/siimage.c return base; base 117 drivers/ide/siimage.c unsigned long base = (unsigned long)hwif->hwif_data; base 120 drivers/ide/siimage.c base += 0xA0 + r; base 122 drivers/ide/siimage.c base += hwif->channel << 6; base 124 drivers/ide/siimage.c base += hwif->channel << 4; base 125 drivers/ide/siimage.c base |= unit << unit; base 126 drivers/ide/siimage.c return base; base 199 drivers/ide/siimage.c unsigned long base = (unsigned long)hwif->hwif_data; base 202 drivers/ide/siimage.c base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A; base 204 drivers/ide/siimage.c scsc = sil_ioread8(dev, base); base 250 drivers/ide/siimage.c unsigned long base = (unsigned long)hwif->hwif_data; base 278 drivers/ide/siimage.c mode = sil_ioread8(dev, base + addr_mask); base 287 drivers/ide/siimage.c sil_iowrite8(dev, mode, base + addr_mask); base 305 drivers/ide/siimage.c unsigned long base = (unsigned long)hwif->hwif_data; base 315 drivers/ide/siimage.c scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A)); base 316 drivers/ide/siimage.c mode = sil_ioread8 (dev, base + addr_mask); base 336 drivers/ide/siimage.c sil_iowrite8 (dev, mode, base + addr_mask); base 366 drivers/ide/siimage.c unsigned long base = (unsigned long)hwif->hwif_data; base 367 drivers/ide/siimage.c u32 ext_stat = readl((void __iomem *)(base + 0x10)); base 457 drivers/ide/siimage.c unsigned long base, scsc_addr; base 465 drivers/ide/siimage.c base = (unsigned long)ioaddr; base 482 drivers/ide/siimage.c sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80); base 483 drivers/ide/siimage.c sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84); base 485 drivers/ide/siimage.c scsc_addr = base ? (base + 0x4A) : 0x8A; base 506 drivers/ide/siimage.c sil_iowrite8 (dev, 0x72, base + 0xA1); base 507 drivers/ide/siimage.c sil_iowrite16(dev, 0x328A, base + 0xA2); base 508 drivers/ide/siimage.c sil_iowrite32(dev, 0x62DD62DD, base + 0xA4); base 509 drivers/ide/siimage.c sil_iowrite32(dev, 0x43924392, base + 0xA8); base 510 drivers/ide/siimage.c sil_iowrite32(dev, 0x40094009, base + 0xAC); base 511 drivers/ide/siimage.c sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1); base 512 drivers/ide/siimage.c sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2); base 513 drivers/ide/siimage.c sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4); base 514 drivers/ide/siimage.c sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8); base 515 drivers/ide/siimage.c sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC); base 517 drivers/ide/siimage.c if (base && pdev_is_sata(dev)) { base 556 drivers/ide/siimage.c unsigned long base; base 571 drivers/ide/siimage.c base = (unsigned long)addr; base 573 drivers/ide/siimage.c base += 0xC0; base 575 drivers/ide/siimage.c base += 0x80; base 581 drivers/ide/siimage.c io_ports->data_addr = base; base 582 drivers/ide/siimage.c io_ports->error_addr = base + 1; base 583 drivers/ide/siimage.c io_ports->nsect_addr = base + 2; base 584 drivers/ide/siimage.c io_ports->lbal_addr = base + 3; base 585 drivers/ide/siimage.c io_ports->lbam_addr = base + 4; base 586 drivers/ide/siimage.c io_ports->lbah_addr = base + 5; base 587 drivers/ide/siimage.c io_ports->device_addr = base + 6; base 588 drivers/ide/siimage.c io_ports->status_addr = base + 7; base 589 drivers/ide/siimage.c io_ports->ctl_addr = base + 10; base 592 drivers/ide/siimage.c base = (unsigned long)addr; base 594 drivers/ide/siimage.c base += 0x80; base 595 drivers/ide/siimage.c hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; base 596 drivers/ide/siimage.c hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; base 597 drivers/ide/siimage.c hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; base 84 drivers/ide/tx4939ide.c static u16 tx4939ide_readw(void __iomem *base, u32 reg) base 86 drivers/ide/tx4939ide.c return __raw_readw(base + tx4939ide_swizzlew(reg)); base 88 drivers/ide/tx4939ide.c static u8 tx4939ide_readb(void __iomem *base, u32 reg) base 90 drivers/ide/tx4939ide.c return __raw_readb(base + tx4939ide_swizzleb(reg)); base 92 drivers/ide/tx4939ide.c static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg) base 94 drivers/ide/tx4939ide.c __raw_writel(val, base + tx4939ide_swizzlel(reg)); base 96 drivers/ide/tx4939ide.c static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg) base 98 drivers/ide/tx4939ide.c __raw_writew(val, base + tx4939ide_swizzlew(reg)); base 100 drivers/ide/tx4939ide.c static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg) base 102 drivers/ide/tx4939ide.c __raw_writeb(val, base + tx4939ide_swizzleb(reg)); base 151 drivers/ide/tx4939ide.c void __iomem *base = TX4939IDE_BASE(hwif); base 152 drivers/ide/tx4939ide.c u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); base 156 drivers/ide/tx4939ide.c u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl); base 158 drivers/ide/tx4939ide.c tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl); base 161 drivers/ide/tx4939ide.c tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl); base 176 drivers/ide/tx4939ide.c void __iomem *base; base 186 drivers/ide/tx4939ide.c base = TX4939IDE_BASE(hwif); base 188 drivers/ide/tx4939ide.c tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl); base 193 drivers/ide/tx4939ide.c void __iomem *base = TX4939IDE_BASE(hwif); base 195 drivers/ide/tx4939ide.c return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ? base 204 drivers/ide/tx4939ide.c void __iomem *base = TX4939IDE_BASE(hwif); base 205 drivers/ide/tx4939ide.c u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); base 212 drivers/ide/tx4939ide.c tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat); base 218 drivers/ide/tx4939ide.c static u8 tx4939ide_clear_dma_status(void __iomem *base) base 223 drivers/ide/tx4939ide.c dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); base 225 drivers/ide/tx4939ide.c tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base, base 228 drivers/ide/tx4939ide.c tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl); base 290 drivers/ide/tx4939ide.c void __iomem *base = TX4939IDE_BASE(hwif); base 298 drivers/ide/tx4939ide.c tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr); base 301 drivers/ide/tx4939ide.c tx4939ide_writeb(rw, base, TX4939IDE_DMA_Cmd); base 304 drivers/ide/tx4939ide.c tx4939ide_clear_dma_status(base); base 306 drivers/ide/tx4939ide.c tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ? base 309 drivers/ide/tx4939ide.c tx4939ide_writew(blk_rq_sectors(cmd->rq), base, TX4939IDE_Sec_Cnt); base 318 drivers/ide/tx4939ide.c void __iomem *base = TX4939IDE_BASE(hwif); base 319 drivers/ide/tx4939ide.c u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); base 322 drivers/ide/tx4939ide.c dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd); base 324 drivers/ide/tx4939ide.c tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd); base 327 drivers/ide/tx4939ide.c dma_stat = tx4939ide_clear_dma_status(base); base 345 drivers/ide/tx4939ide.c void __iomem *base = TX4939IDE_BASE(hwif); base 355 drivers/ide/tx4939ide.c stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl); base 364 drivers/ide/tx4939ide.c dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); base 377 drivers/ide/tx4939ide.c tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl); base 384 drivers/ide/tx4939ide.c void __iomem *base = TX4939IDE_BASE(hwif); base 386 drivers/ide/tx4939ide.c return tx4939ide_readb(base, TX4939IDE_DMA_Stat); base 394 drivers/ide/tx4939ide.c void __iomem *base = TX4939IDE_BASE(hwif); base 397 drivers/ide/tx4939ide.c tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl); base 400 drivers/ide/tx4939ide.c tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl); base 402 drivers/ide/tx4939ide.c tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base, base 405 drivers/ide/tx4939ide.c tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt); base 406 drivers/ide/tx4939ide.c tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt); base 423 drivers/ide/tx4939ide.c void __iomem *base = TX4939IDE_BASE(hwif); base 432 drivers/ide/tx4939ide.c tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl); base 54 drivers/iio/adc/aspeed_adc.c void __iomem *base; base 100 drivers/iio/adc/aspeed_adc.c *val = readw(data->base + chan->address); base 160 drivers/iio/adc/aspeed_adc.c *readval = readl(data->base + reg); base 189 drivers/iio/adc/aspeed_adc.c data->base = devm_ioremap_resource(&pdev->dev, res); base 190 drivers/iio/adc/aspeed_adc.c if (IS_ERR(data->base)) base 191 drivers/iio/adc/aspeed_adc.c return PTR_ERR(data->base); base 199 drivers/iio/adc/aspeed_adc.c data->base + ASPEED_REG_CLOCK_CONTROL, base 211 drivers/iio/adc/aspeed_adc.c data->base + ASPEED_REG_CLOCK_CONTROL, base 232 drivers/iio/adc/aspeed_adc.c data->base + ASPEED_REG_ENGINE_CONTROL); base 235 drivers/iio/adc/aspeed_adc.c ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL, base 253 drivers/iio/adc/aspeed_adc.c data->base + ASPEED_REG_ENGINE_CONTROL); base 271 drivers/iio/adc/aspeed_adc.c data->base + ASPEED_REG_ENGINE_CONTROL); base 290 drivers/iio/adc/aspeed_adc.c data->base + ASPEED_REG_ENGINE_CONTROL); base 330 drivers/iio/adc/at91-sama5d2_adc.c #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg) base 331 drivers/iio/adc/at91-sama5d2_adc.c #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg) base 385 drivers/iio/adc/at91-sama5d2_adc.c void __iomem *base; base 1738 drivers/iio/adc/at91-sama5d2_adc.c st->base = devm_ioremap_resource(&pdev->dev, res); base 1739 drivers/iio/adc/at91-sama5d2_adc.c if (IS_ERR(st->base)) base 1740 drivers/iio/adc/at91-sama5d2_adc.c return PTR_ERR(st->base); base 1823 drivers/iio/adc/at91-sama5d2_adc.c readl_relaxed(st->base + AT91_SAMA5D2_VERSION)); base 46 drivers/iio/adc/ep93xx_adc.c void __iomem *base; base 96 drivers/iio/adc/ep93xx_adc.c writel_relaxed(0xAA, priv->base + EP93XX_ADC_SW_LOCK); base 98 drivers/iio/adc/ep93xx_adc.c priv->base + EP93XX_ADC_SWITCH); base 107 drivers/iio/adc/ep93xx_adc.c readl_relaxed(priv->base + EP93XX_ADC_RESULT); base 117 drivers/iio/adc/ep93xx_adc.c t = readl_relaxed(priv->base + EP93XX_ADC_RESULT); base 167 drivers/iio/adc/ep93xx_adc.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 168 drivers/iio/adc/ep93xx_adc.c if (IS_ERR(priv->base)) { base 170 drivers/iio/adc/ep93xx_adc.c return PTR_ERR(priv->base); base 54 drivers/iio/adc/ingenic-adc.c void __iomem *base; base 70 drivers/iio/adc/ingenic-adc.c cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask; base 72 drivers/iio/adc/ingenic-adc.c writel(cfg, adc->base + JZ_ADC_REG_CFG); base 85 drivers/iio/adc/ingenic-adc.c val = readb(adc->base + JZ_ADC_REG_ENABLE); base 92 drivers/iio/adc/ingenic-adc.c writeb(val, adc->base + JZ_ADC_REG_ENABLE); base 103 drivers/iio/adc/ingenic-adc.c ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val, base 192 drivers/iio/adc/ingenic-adc.c adc->base + JZ_ADC_REG_ADCLK); base 262 drivers/iio/adc/ingenic-adc.c *val = readw(adc->base + JZ_ADC_REG_ADSDAT); base 265 drivers/iio/adc/ingenic-adc.c *val = readw(adc->base + JZ_ADC_REG_ADBDAT); base 349 drivers/iio/adc/ingenic-adc.c adc->base = devm_ioremap_resource(dev, mem_base); base 350 drivers/iio/adc/ingenic-adc.c if (IS_ERR(adc->base)) base 351 drivers/iio/adc/ingenic-adc.c return PTR_ERR(adc->base); base 375 drivers/iio/adc/ingenic-adc.c writeb(0x00, adc->base + JZ_ADC_REG_ENABLE); base 376 drivers/iio/adc/ingenic-adc.c writeb(0xff, adc->base + JZ_ADC_REG_CTRL); base 44 drivers/iio/adc/lpc18xx_adc.c void __iomem *base; base 76 drivers/iio/adc/lpc18xx_adc.c writel(reg, adc->base + LPC18XX_ADC_CR); base 78 drivers/iio/adc/lpc18xx_adc.c ret = readl_poll_timeout(adc->base + LPC18XX_ADC_GDR, reg, base 137 drivers/iio/adc/lpc18xx_adc.c adc->base = devm_ioremap_resource(&pdev->dev, res); base 138 drivers/iio/adc/lpc18xx_adc.c if (IS_ERR(adc->base)) base 139 drivers/iio/adc/lpc18xx_adc.c return PTR_ERR(adc->base); base 177 drivers/iio/adc/lpc18xx_adc.c writel(adc->cr_reg, adc->base + LPC18XX_ADC_CR); base 188 drivers/iio/adc/lpc18xx_adc.c writel(0, adc->base + LPC18XX_ADC_CR); base 202 drivers/iio/adc/lpc18xx_adc.c writel(0, adc->base + LPC18XX_ADC_CR); base 26 drivers/iio/adc/men_z188_adc.c void __iomem *base; base 59 drivers/iio/adc/men_z188_adc.c tmp = readw(adc->base + chan->channel * 4); base 123 drivers/iio/adc/men_z188_adc.c adc->base = ioremap(mem->start, resource_size(mem)); base 124 drivers/iio/adc/men_z188_adc.c if (adc->base == NULL) base 127 drivers/iio/adc/men_z188_adc.c men_z188_config_channels(adc->base); base 145 drivers/iio/adc/men_z188_adc.c iounmap(adc->base); base 652 drivers/iio/adc/meson_saradc.c void __iomem *base) base 669 drivers/iio/adc/meson_saradc.c priv->clk_div.reg = base + MESON_SAR_ADC_REG3; base 691 drivers/iio/adc/meson_saradc.c priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; base 1191 drivers/iio/adc/meson_saradc.c void __iomem *base; base 1218 drivers/iio/adc/meson_saradc.c base = devm_ioremap_resource(&pdev->dev, res); base 1219 drivers/iio/adc/meson_saradc.c if (IS_ERR(base)) base 1220 drivers/iio/adc/meson_saradc.c return PTR_ERR(base); base 1222 drivers/iio/adc/meson_saradc.c priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 1270 drivers/iio/adc/meson_saradc.c ret = meson_sar_adc_clk_init(indio_dev, base); base 117 drivers/iio/adc/mxs-lradc-adc.c void __iomem *base; base 156 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 157 drivers/iio/adc/mxs-lradc-adc.c writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); base 162 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); base 165 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); base 169 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); base 170 drivers/iio/adc/mxs-lradc-adc.c writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); base 172 drivers/iio/adc/mxs-lradc-adc.c writel(0, adc->base + LRADC_CH(0)); base 176 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); base 177 drivers/iio/adc/mxs-lradc-adc.c writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); base 187 drivers/iio/adc/mxs-lradc-adc.c *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK; base 192 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 388 drivers/iio/adc/mxs-lradc-adc.c unsigned long reg = readl(adc->base + LRADC_CTRL1); base 405 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 422 drivers/iio/adc/mxs-lradc-adc.c adc->buffer[j] = readl(adc->base + LRADC_CH(j)); base 423 drivers/iio/adc/mxs-lradc-adc.c writel(chan_value, adc->base + LRADC_CH(j)); base 442 drivers/iio/adc/mxs-lradc-adc.c writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st)); base 496 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 498 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); base 504 drivers/iio/adc/mxs-lradc-adc.c writel(chan_value, adc->base + LRADC_CH(ofs)); base 510 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); base 511 drivers/iio/adc/mxs-lradc-adc.c writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); base 512 drivers/iio/adc/mxs-lradc-adc.c writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); base 513 drivers/iio/adc/mxs-lradc-adc.c writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); base 515 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET); base 526 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); base 529 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); base 532 drivers/iio/adc/mxs-lradc-adc.c adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 674 drivers/iio/adc/mxs-lradc-adc.c writel(adc_cfg, adc->base + LRADC_DELAY(0)); base 681 drivers/iio/adc/mxs-lradc-adc.c writel(0, adc->base + LRADC_CTRL2); base 686 drivers/iio/adc/mxs-lradc-adc.c writel(0, adc->base + LRADC_DELAY(0)); base 715 drivers/iio/adc/mxs-lradc-adc.c adc->base = devm_ioremap(dev, iores->start, resource_size(iores)); base 716 drivers/iio/adc/mxs-lradc-adc.c if (!adc->base) base 743 drivers/iio/adc/mxs-lradc-adc.c ret = stmp_reset_block(adc->base); base 136 drivers/iio/adc/qcom-spmi-adc5.c u16 base; base 160 drivers/iio/adc/qcom-spmi-adc5.c return regmap_bulk_read(adc->regmap, adc->base + offset, data, len); base 165 drivers/iio/adc/qcom-spmi-adc5.c return regmap_bulk_write(adc->regmap, adc->base + offset, data, len); base 754 drivers/iio/adc/qcom-spmi-adc5.c adc->base = reg; base 109 drivers/iio/adc/qcom-spmi-iadc.c u16 base; base 123 drivers/iio/adc/qcom-spmi-iadc.c ret = regmap_read(iadc->regmap, iadc->base + offset, &val); base 133 drivers/iio/adc/qcom-spmi-iadc.c return regmap_write(iadc->regmap, iadc->base + offset, data); base 274 drivers/iio/adc/qcom-spmi-iadc.c return regmap_bulk_read(iadc->regmap, iadc->base + IADC_DATA, data, 2); base 512 drivers/iio/adc/qcom-spmi-iadc.c iadc->base = res; base 115 drivers/iio/adc/qcom-spmi-vadc.c u16 base; base 139 drivers/iio/adc/qcom-spmi-vadc.c return regmap_bulk_read(vadc->regmap, vadc->base + offset, data, 1); base 144 drivers/iio/adc/qcom-spmi-vadc.c return regmap_write(vadc->regmap, vadc->base + offset, data); base 278 drivers/iio/adc/qcom-spmi-vadc.c ret = regmap_bulk_read(vadc->regmap, vadc->base + VADC_DATA, data, 2); base 875 drivers/iio/adc/qcom-spmi-vadc.c vadc->base = reg; base 79 drivers/iio/adc/sc27xx_adc.c u32 base; base 200 drivers/iio/adc/sc27xx_adc.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, base 205 drivers/iio/adc/sc27xx_adc.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR, base 213 drivers/iio/adc/sc27xx_adc.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG, base 222 drivers/iio/adc/sc27xx_adc.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, base 228 drivers/iio/adc/sc27xx_adc.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, base 234 drivers/iio/adc/sc27xx_adc.c data->base + SC27XX_ADC_INT_RAW, base 243 drivers/iio/adc/sc27xx_adc.c ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, &value); base 250 drivers/iio/adc/sc27xx_adc.c regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, base 507 drivers/iio/adc/sc27xx_adc.c ret = of_property_read_u32(np, "reg", &sc27xx_data->base); base 154 drivers/iio/adc/stm32-adc-core.c val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); base 157 drivers/iio/adc/stm32-adc-core.c writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); base 266 drivers/iio/adc/stm32-adc-core.c val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); base 270 drivers/iio/adc/stm32-adc-core.c writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); base 308 drivers/iio/adc/stm32-adc-core.c ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); base 321 drivers/iio/adc/stm32-adc-core.c status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); base 539 drivers/iio/adc/stm32-adc-core.c writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); base 562 drivers/iio/adc/stm32-adc-core.c priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); base 662 drivers/iio/adc/stm32-adc-core.c priv->common.base = devm_ioremap_resource(&pdev->dev, res); base 663 drivers/iio/adc/stm32-adc-core.c if (IS_ERR(priv->common.base)) base 664 drivers/iio/adc/stm32-adc-core.c return PTR_ERR(priv->common.base); base 175 drivers/iio/adc/stm32-adc-core.h void __iomem *base; base 452 drivers/iio/adc/stm32-adc.c return readl_relaxed(adc->common->base + adc->offset + reg); base 463 drivers/iio/adc/stm32-adc.c return readw_relaxed(adc->common->base + adc->offset + reg); base 468 drivers/iio/adc/stm32-adc.c writel_relaxed(val, adc->common->base + adc->offset + reg); base 235 drivers/iio/adc/stm32-dfsdm-core.c priv->dfsdm.base = devm_ioremap_resource(&pdev->dev, res); base 236 drivers/iio/adc/stm32-dfsdm-core.c if (IS_ERR(priv->dfsdm.base)) base 237 drivers/iio/adc/stm32-dfsdm-core.c return PTR_ERR(priv->dfsdm.base); base 341 drivers/iio/adc/stm32-dfsdm-core.c dfsdm->base, base 303 drivers/iio/adc/stm32-dfsdm.h void __iomem *base; base 42 drivers/iio/adc/stx104.c static unsigned int base[max_num_isa_dev(STX104_EXTENT)]; base 44 drivers/iio/adc/stx104.c module_param_hw_array(base, uint, ioport, &num_stx104, 0); base 45 drivers/iio/adc/stx104.c MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); base 54 drivers/iio/adc/stx104.c unsigned int base; base 67 drivers/iio/adc/stx104.c unsigned int base; base 82 drivers/iio/adc/stx104.c adc_config = inb(priv->base + 11); base 94 drivers/iio/adc/stx104.c outb(chan->channel | (chan->channel << 4), priv->base + 2); base 97 drivers/iio/adc/stx104.c outb(0, priv->base); base 98 drivers/iio/adc/stx104.c while (inb(priv->base + 8) & BIT(7)); base 100 drivers/iio/adc/stx104.c *val = inw(priv->base); base 104 drivers/iio/adc/stx104.c adc_config = inb(priv->base + 11); base 111 drivers/iio/adc/stx104.c adc_config = inb(priv->base + 11); base 133 drivers/iio/adc/stx104.c outb(0, priv->base + 11); base 136 drivers/iio/adc/stx104.c outb(1, priv->base + 11); base 139 drivers/iio/adc/stx104.c outb(2, priv->base + 11); base 142 drivers/iio/adc/stx104.c outb(3, priv->base + 11); base 156 drivers/iio/adc/stx104.c outw(val, priv->base + 4 + 2 * chan->channel); base 225 drivers/iio/adc/stx104.c return !!(inb(stx104gpio->base) & BIT(offset)); base 233 drivers/iio/adc/stx104.c *bits = inb(stx104gpio->base); base 255 drivers/iio/adc/stx104.c outb(stx104gpio->out_state, stx104gpio->base); base 282 drivers/iio/adc/stx104.c outb(stx104gpio->out_state, stx104gpio->base); base 302 drivers/iio/adc/stx104.c if (!devm_request_region(dev, base[id], STX104_EXTENT, base 305 drivers/iio/adc/stx104.c base[id], base[id] + STX104_EXTENT); base 313 drivers/iio/adc/stx104.c if (inb(base[id] + 8) & BIT(5)) { base 325 drivers/iio/adc/stx104.c priv->base = base[id]; base 328 drivers/iio/adc/stx104.c outb(0, base[id] + 9); base 331 drivers/iio/adc/stx104.c outb(0, base[id] + 11); base 334 drivers/iio/adc/stx104.c outw(0, base[id] + 4); base 335 drivers/iio/adc/stx104.c outw(0, base[id] + 6); base 340 drivers/iio/adc/stx104.c stx104gpio->chip.base = -1; base 350 drivers/iio/adc/stx104.c stx104gpio->base = base[id] + 3; base 500 drivers/iio/adc/sun4i-gpadc-iio.c void __iomem *base; base 512 drivers/iio/adc/sun4i-gpadc-iio.c base = devm_ioremap_resource(&pdev->dev, mem); base 513 drivers/iio/adc/sun4i-gpadc-iio.c if (IS_ERR(base)) base 514 drivers/iio/adc/sun4i-gpadc-iio.c return PTR_ERR(base); base 516 drivers/iio/adc/sun4i-gpadc-iio.c info->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 639 drivers/iio/adc/ti-ads7950.c st->chip.base = -1; base 118 drivers/iio/adc/xilinx-xadc-core.c writel(val, xadc->base + reg); base 124 drivers/iio/adc/xilinx-xadc-core.c *val = readl(xadc->base + reg); base 1222 drivers/iio/adc/xilinx-xadc-core.c xadc->base = devm_ioremap_resource(&pdev->dev, mem); base 1223 drivers/iio/adc/xilinx-xadc-core.c if (IS_ERR(xadc->base)) base 1224 drivers/iio/adc/xilinx-xadc-core.c return PTR_ERR(xadc->base); base 45 drivers/iio/adc/xilinx-xadc.h void __iomem *base; base 135 drivers/iio/dac/ad5592r-base.c st->gpiochip.base = -1; base 32 drivers/iio/dac/cio-dac.c static unsigned int base[max_num_isa_dev(CIO_DAC_EXTENT)]; base 34 drivers/iio/dac/cio-dac.c module_param_hw_array(base, uint, ioport, &num_cio_dac, 0); base 35 drivers/iio/dac/cio-dac.c MODULE_PARM_DESC(base, "Measurement Computing CIO-DAC base addresses"); base 44 drivers/iio/dac/cio-dac.c unsigned int base; base 74 drivers/iio/dac/cio-dac.c outw(val, priv->base + chan_addr_offset); base 101 drivers/iio/dac/cio-dac.c if (!devm_request_region(dev, base[id], CIO_DAC_EXTENT, base 104 drivers/iio/dac/cio-dac.c base[id], base[id] + CIO_DAC_EXTENT); base 116 drivers/iio/dac/cio-dac.c priv->base = base[id]; base 120 drivers/iio/dac/cio-dac.c outw(0, base[id] + i); base 35 drivers/iio/dac/lpc18xx_dac.c void __iomem *base; base 58 drivers/iio/dac/lpc18xx_dac.c reg = readl(dac->base + LPC18XX_DAC_CR); base 90 drivers/iio/dac/lpc18xx_dac.c writel(reg, dac->base + LPC18XX_DAC_CR); base 91 drivers/iio/dac/lpc18xx_dac.c writel(LPC18XX_DAC_CTRL_DMA_ENA, dac->base + LPC18XX_DAC_CTRL); base 121 drivers/iio/dac/lpc18xx_dac.c dac->base = devm_ioremap_resource(&pdev->dev, res); base 122 drivers/iio/dac/lpc18xx_dac.c if (IS_ERR(dac->base)) base 123 drivers/iio/dac/lpc18xx_dac.c return PTR_ERR(dac->base); base 156 drivers/iio/dac/lpc18xx_dac.c writel(0, dac->base + LPC18XX_DAC_CTRL); base 157 drivers/iio/dac/lpc18xx_dac.c writel(0, dac->base + LPC18XX_DAC_CR); base 181 drivers/iio/dac/lpc18xx_dac.c writel(0, dac->base + LPC18XX_DAC_CTRL); base 41 drivers/iio/dummy/iio_dummy_evgen.c int base; base 61 drivers/iio/dummy/iio_dummy_evgen.c iio_evgen->base = irq_sim_irqnum(&iio_evgen->irq_sim, 0); base 105 drivers/iio/dummy/iio_dummy_evgen.c iio_evgen->inuse[irq - iio_evgen->base] = false; base 112 drivers/iio/dummy/iio_dummy_evgen.c return &iio_evgen->regs[irq - iio_evgen->base]; base 416 drivers/iio/imu/bmi160/bmi160_core.c int i, ret, j = 0, base = BMI160_REG_DATA_MAGN_XOUT_L; base 421 drivers/iio/imu/bmi160/bmi160_core.c ret = regmap_bulk_read(data->regmap, base + i * sizeof(sample), base 771 drivers/iio/imu/kmx61.c static int kmx61_read_measurement(struct kmx61_data *data, u8 base, u8 offset) base 774 drivers/iio/imu/kmx61.c u8 reg = base + offset * 2; base 1200 drivers/iio/imu/kmx61.c u8 base; base 1204 drivers/iio/imu/kmx61.c base = KMX61_ACC_XOUT_L; base 1206 drivers/iio/imu/kmx61.c base = KMX61_MAG_XOUT_L; base 1211 drivers/iio/imu/kmx61.c ret = kmx61_read_measurement(data, base, bit); base 34 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c #define ST_LSM6DSX_SLV_ADDR(n, base) ((base) + (n) * 3) base 35 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c #define ST_LSM6DSX_SLV_SUB_ADDR(n, base) ((base) + 1 + (n) * 3) base 36 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c #define ST_LSM6DSX_SLV_CONFIG(n, base) ((base) + 2 + (n) * 3) base 1039 drivers/infiniband/core/uverbs_cmd.c resp.base.cq_handle = obj->uobject.id; base 1040 drivers/infiniband/core/uverbs_cmd.c resp.base.cqe = cq->cqe; base 1451 drivers/infiniband/core/uverbs_cmd.c resp.base.qpn = qp->qp_num; base 1452 drivers/infiniband/core/uverbs_cmd.c resp.base.qp_handle = obj->uevent.uobject.id; base 1453 drivers/infiniband/core/uverbs_cmd.c resp.base.max_recv_sge = attr.cap.max_recv_sge; base 1454 drivers/infiniband/core/uverbs_cmd.c resp.base.max_send_sge = attr.cap.max_send_sge; base 1455 drivers/infiniband/core/uverbs_cmd.c resp.base.max_recv_wr = attr.cap.max_recv_wr; base 1456 drivers/infiniband/core/uverbs_cmd.c resp.base.max_send_wr = attr.cap.max_send_wr; base 1457 drivers/infiniband/core/uverbs_cmd.c resp.base.max_inline_data = attr.cap.max_inline_data; base 1771 drivers/infiniband/core/uverbs_cmd.c qp = uobj_get_obj_read(qp, UVERBS_OBJECT_QP, cmd->base.qp_handle, base 1778 drivers/infiniband/core/uverbs_cmd.c if ((cmd->base.attr_mask & IB_QP_PORT) && base 1779 drivers/infiniband/core/uverbs_cmd.c !rdma_is_port_valid(qp->device, cmd->base.port_num)) { base 1784 drivers/infiniband/core/uverbs_cmd.c if ((cmd->base.attr_mask & IB_QP_AV)) { base 1785 drivers/infiniband/core/uverbs_cmd.c if (!rdma_is_port_valid(qp->device, cmd->base.dest.port_num)) { base 1790 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_STATE && base 1791 drivers/infiniband/core/uverbs_cmd.c cmd->base.qp_state == IB_QPS_RTR) { base 1806 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.dest.port_num != qp->real_qp->port) { base 1824 drivers/infiniband/core/uverbs_cmd.c if (((cmd->base.attr_mask & (IB_QP_AV | IB_QP_PORT)) base 1826 drivers/infiniband/core/uverbs_cmd.c cmd->base.port_num != cmd->base.dest.port_num) { base 1830 drivers/infiniband/core/uverbs_cmd.c if ((cmd->base.attr_mask & (IB_QP_AV | IB_QP_PORT)) base 1832 drivers/infiniband/core/uverbs_cmd.c cmd->base.attr_mask |= IB_QP_PORT; base 1833 drivers/infiniband/core/uverbs_cmd.c cmd->base.port_num = cmd->base.dest.port_num; base 1838 drivers/infiniband/core/uverbs_cmd.c if ((cmd->base.attr_mask & IB_QP_ALT_PATH) && base 1839 drivers/infiniband/core/uverbs_cmd.c (!rdma_is_port_valid(qp->device, cmd->base.alt_port_num) || base 1840 drivers/infiniband/core/uverbs_cmd.c !rdma_is_port_valid(qp->device, cmd->base.alt_dest.port_num) || base 1841 drivers/infiniband/core/uverbs_cmd.c cmd->base.alt_port_num != cmd->base.alt_dest.port_num)) { base 1846 drivers/infiniband/core/uverbs_cmd.c if ((cmd->base.attr_mask & IB_QP_CUR_STATE && base 1847 drivers/infiniband/core/uverbs_cmd.c cmd->base.cur_qp_state > IB_QPS_ERR) || base 1848 drivers/infiniband/core/uverbs_cmd.c (cmd->base.attr_mask & IB_QP_STATE && base 1849 drivers/infiniband/core/uverbs_cmd.c cmd->base.qp_state > IB_QPS_ERR)) { base 1854 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_STATE) base 1855 drivers/infiniband/core/uverbs_cmd.c attr->qp_state = cmd->base.qp_state; base 1856 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_CUR_STATE) base 1857 drivers/infiniband/core/uverbs_cmd.c attr->cur_qp_state = cmd->base.cur_qp_state; base 1858 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_PATH_MTU) base 1859 drivers/infiniband/core/uverbs_cmd.c attr->path_mtu = cmd->base.path_mtu; base 1860 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_PATH_MIG_STATE) base 1861 drivers/infiniband/core/uverbs_cmd.c attr->path_mig_state = cmd->base.path_mig_state; base 1862 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_QKEY) base 1863 drivers/infiniband/core/uverbs_cmd.c attr->qkey = cmd->base.qkey; base 1864 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_RQ_PSN) base 1865 drivers/infiniband/core/uverbs_cmd.c attr->rq_psn = cmd->base.rq_psn; base 1866 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_SQ_PSN) base 1867 drivers/infiniband/core/uverbs_cmd.c attr->sq_psn = cmd->base.sq_psn; base 1868 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_DEST_QPN) base 1869 drivers/infiniband/core/uverbs_cmd.c attr->dest_qp_num = cmd->base.dest_qp_num; base 1870 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_ACCESS_FLAGS) base 1871 drivers/infiniband/core/uverbs_cmd.c attr->qp_access_flags = cmd->base.qp_access_flags; base 1872 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_PKEY_INDEX) base 1873 drivers/infiniband/core/uverbs_cmd.c attr->pkey_index = cmd->base.pkey_index; base 1874 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) base 1875 drivers/infiniband/core/uverbs_cmd.c attr->en_sqd_async_notify = cmd->base.en_sqd_async_notify; base 1876 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_MAX_QP_RD_ATOMIC) base 1877 drivers/infiniband/core/uverbs_cmd.c attr->max_rd_atomic = cmd->base.max_rd_atomic; base 1878 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) base 1879 drivers/infiniband/core/uverbs_cmd.c attr->max_dest_rd_atomic = cmd->base.max_dest_rd_atomic; base 1880 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_MIN_RNR_TIMER) base 1881 drivers/infiniband/core/uverbs_cmd.c attr->min_rnr_timer = cmd->base.min_rnr_timer; base 1882 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_PORT) base 1883 drivers/infiniband/core/uverbs_cmd.c attr->port_num = cmd->base.port_num; base 1884 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_TIMEOUT) base 1885 drivers/infiniband/core/uverbs_cmd.c attr->timeout = cmd->base.timeout; base 1886 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_RETRY_CNT) base 1887 drivers/infiniband/core/uverbs_cmd.c attr->retry_cnt = cmd->base.retry_cnt; base 1888 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_RNR_RETRY) base 1889 drivers/infiniband/core/uverbs_cmd.c attr->rnr_retry = cmd->base.rnr_retry; base 1890 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_ALT_PATH) { base 1891 drivers/infiniband/core/uverbs_cmd.c attr->alt_port_num = cmd->base.alt_port_num; base 1892 drivers/infiniband/core/uverbs_cmd.c attr->alt_timeout = cmd->base.alt_timeout; base 1893 drivers/infiniband/core/uverbs_cmd.c attr->alt_pkey_index = cmd->base.alt_pkey_index; base 1895 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_RATE_LIMIT) base 1898 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_AV) base 1900 drivers/infiniband/core/uverbs_cmd.c &cmd->base.dest); base 1902 drivers/infiniband/core/uverbs_cmd.c if (cmd->base.attr_mask & IB_QP_ALT_PATH) base 1904 drivers/infiniband/core/uverbs_cmd.c &cmd->base.alt_dest); base 1908 drivers/infiniband/core/uverbs_cmd.c cmd->base.attr_mask), base 1924 drivers/infiniband/core/uverbs_cmd.c ret = uverbs_request(attrs, &cmd.base, sizeof(cmd.base)); base 1928 drivers/infiniband/core/uverbs_cmd.c if (cmd.base.attr_mask & base 1953 drivers/infiniband/core/uverbs_cmd.c if (cmd.base.attr_mask & base 3638 drivers/infiniband/core/uverbs_cmd.c copy_query_dev_fields(ucontext, &resp.base, &attr); base 3968 drivers/infiniband/core/uverbs_cmd.c base, base 1257 drivers/infiniband/core/uverbs_main.c dev_t base; base 1296 drivers/infiniband/core/uverbs_main.c base = dynamic_uverbs_dev + devnum - IB_UVERBS_NUM_FIXED_MINOR; base 1298 drivers/infiniband/core/uverbs_main.c base = IB_UVERBS_BASE_DEV + devnum; base 1303 drivers/infiniband/core/uverbs_main.c uverbs_dev->dev.devt = base; base 1753 drivers/infiniband/core/verbs.c netdev_speed = lksettings.base.speed; base 1347 drivers/infiniband/hw/hfi1/chip.c void __iomem *base = hfi1_addr_from_offset(dd, offset); base 1352 drivers/infiniband/hw/hfi1/chip.c writeq(value, base); base 94 drivers/infiniband/hw/hfi1/exp_rcv.c grp->base = tidbase; base 121 drivers/infiniband/hw/hfi1/exp_rcv.h u32 base; base 350 drivers/infiniband/hw/hfi1/init.c u32 base; base 393 drivers/infiniband/hw/hfi1/init.c base = ctxt * (dd->rcv_entries.ngroups + 1); base 396 drivers/infiniband/hw/hfi1/init.c base = kctxt_ngroups + base 402 drivers/infiniband/hw/hfi1/init.c base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) + base 405 drivers/infiniband/hw/hfi1/init.c base += ct * (dd->rcv_entries.ngroups + 1); base 408 drivers/infiniband/hw/hfi1/init.c base += dd->rcv_entries.nctxt_extra + base 412 drivers/infiniband/hw/hfi1/init.c rcd->eager_base = base * dd->rcv_entries.group_size; base 443 drivers/infiniband/hw/hfi1/pio.c u16 base; base 471 drivers/infiniband/hw/hfi1/pio.c base = 1; base 479 drivers/infiniband/hw/hfi1/pio.c sci->base = base; base 483 drivers/infiniband/hw/hfi1/pio.c base += scs->size; base 768 drivers/infiniband/hw/hfi1/pio.c | ((sci->base & SC(CTRL_CTXT_BASE_MASK)) base 2168 drivers/infiniband/hw/hfi1/pio.c i, sci->type, sci->base, sci->credits); base 150 drivers/infiniband/hw/hfi1/pio.h u16 base; /* base in PIO array */ base 1214 drivers/infiniband/hw/hfi1/tid_rdma.c grp->base, grp->map, grp->used, cnt); base 1306 drivers/infiniband/hw/hfi1/tid_rdma.c rcventry = grp->base + i; base 1371 drivers/infiniband/hw/hfi1/tid_rdma.c rcventry = grp->base + i; base 638 drivers/infiniband/hw/hfi1/trace_tid.h TP_PROTO(struct rvt_qp *qp, const char *msg, u32 index, u32 base, base 640 drivers/infiniband/hw/hfi1/trace_tid.h TP_ARGS(qp, msg, index, base, map, used, cnt), base 646 drivers/infiniband/hw/hfi1/trace_tid.h __field(u32, base) base 656 drivers/infiniband/hw/hfi1/trace_tid.h __entry->base = base; base 667 drivers/infiniband/hw/hfi1/trace_tid.h __entry->base, base 676 drivers/infiniband/hw/hfi1/trace_tid.h TP_PROTO(struct rvt_qp *qp, const char *msg, u32 index, u32 base, base 678 drivers/infiniband/hw/hfi1/trace_tid.h TP_ARGS(qp, msg, index, base, map, used, cnt) base 702 drivers/infiniband/hw/hfi1/user_exp_rcv.c rcv_array_wc_fill(dd, grp->base + idx); base 717 drivers/infiniband/hw/hfi1/user_exp_rcv.c rcv_array_wc_fill(dd, grp->base + useidx); base 722 drivers/infiniband/hw/hfi1/user_exp_rcv.c rcventry = grp->base + useidx; base 743 drivers/infiniband/hw/hfi1/user_exp_rcv.c rcv_array_wc_fill(dd, grp->base + useidx); base 861 drivers/infiniband/hw/hfi1/user_exp_rcv.c node->grp->map &= ~(1 << (node->rcventry - node->grp->base)); base 888 drivers/infiniband/hw/hfi1/user_exp_rcv.c u16 rcventry = grp->base + i; base 956 drivers/infiniband/hw/hfi1/user_exp_rcv.c u32 base = fdata->uctxt->expected_base; base 958 drivers/infiniband/hw/hfi1/user_exp_rcv.c fdata->entry_to_rb[tnode->rcventry - base] = tnode; base 965 drivers/infiniband/hw/hfi1/user_exp_rcv.c u32 base = fdata->uctxt->expected_base; base 967 drivers/infiniband/hw/hfi1/user_exp_rcv.c fdata->entry_to_rb[tnode->rcventry - base] = NULL; base 744 drivers/infiniband/hw/hfi1/user_sdma.c unsigned long base, offset; base 749 drivers/infiniband/hw/hfi1/user_sdma.c base = (unsigned long)iovec->iov.iov_base; base 750 drivers/infiniband/hw/hfi1/user_sdma.c offset = offset_in_page(base + iovec->offset + iov_offset); base 751 drivers/infiniband/hw/hfi1/user_sdma.c pageidx = (((iovec->offset + iov_offset + base) - (base & PAGE_MASK)) >> base 112 drivers/infiniband/hw/hns/hns_roce_qp.c int align, unsigned long *base) base 117 drivers/infiniband/hw/hns/hns_roce_qp.c base) ? base 141 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u64 base = 0; base 150 drivers/infiniband/hw/i40iw/i40iw_ctrl.c info[i].base = 0; base 155 drivers/infiniband/hw/i40iw/i40iw_ctrl.c info[i].base = RS_64_1(temp, 32) * 512; base 156 drivers/infiniband/hw/i40iw/i40iw_ctrl.c if (info[i].base > base) { base 157 drivers/infiniband/hw/i40iw/i40iw_ctrl.c base = info[i].base; base 171 drivers/infiniband/hw/i40iw/i40iw_ctrl.c size = info[k].cnt * info[k].size + info[k].base; base 67 drivers/infiniband/hw/i40iw/i40iw_hmc.c fpm_addr = hmc_info->hmc_obj[(type)].base + base 97 drivers/infiniband/hw/i40iw/i40iw_hmc.c fpm_adr = hmc_info->hmc_obj[type].base + base 89 drivers/infiniband/hw/i40iw/i40iw_hmc.h u64 base; base 89 drivers/infiniband/hw/i40iw/i40iw_pble.c pble_rsrc->fpm_base_addr = hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].base; base 225 drivers/infiniband/hw/mlx4/mad.c __be16 *base; base 265 drivers/infiniband/hw/mlx4/mad.c base = (__be16 *) &(((struct ib_smp *)mad)->data[0]); base 269 drivers/infiniband/hw/mlx4/mad.c i + bn*32, be16_to_cpu(base[i])); base 270 drivers/infiniband/hw/mlx4/mad.c if (be16_to_cpu(base[i]) != base 274 drivers/infiniband/hw/mlx4/mad.c be16_to_cpu(base[i]); base 619 drivers/infiniband/hw/mlx5/devx.c rq->base.mqp.qpn) == obj_id || base 621 drivers/infiniband/hw/mlx5/devx.c sq->base.mqp.qpn) == obj_id || base 155 drivers/infiniband/hw/mlx5/ib_rep.c sq->base.mqp.qpn); base 53 drivers/infiniband/hw/mlx5/mem.c u64 base = ~0, p = 0; base 68 drivers/infiniband/hw/mlx5/mem.c if (base + p != pfn) { base 76 drivers/infiniband/hw/mlx5/mem.c base = pfn; base 136 drivers/infiniband/hw/mlx5/mem.c u64 base; base 157 drivers/infiniband/hw/mlx5/mem.c base = sg_dma_address(sg); base 175 drivers/infiniband/hw/mlx5/mem.c cur = base + (k << PAGE_SHIFT); base 353 drivers/infiniband/hw/mlx5/mlx5_ib.h struct mlx5_ib_qp_base base; base 365 drivers/infiniband/hw/mlx5/mlx5_ib.h struct mlx5_ib_qp_base base; base 375 drivers/infiniband/hw/mlx5/mlx5_ib.h struct mlx5_ib_qp_base base; base 1033 drivers/infiniband/hw/mlx5/odp.c u32 qpn = qp->trans_qp.base.mqp.qpn; base 169 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp_base *base = &qp->trans_qp.base; base 170 drivers/infiniband/hw/mlx5/qp.c struct ib_umem *umem = base->ubuffer.umem; base 235 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp_base *base = &qp->trans_qp.base; base 236 drivers/infiniband/hw/mlx5/qp.c struct ib_umem *umem = base->ubuffer.umem; base 524 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp_base *base, base 552 drivers/infiniband/hw/mlx5/qp.c base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; base 555 drivers/infiniband/hw/mlx5/qp.c base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + base 860 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp_base *base) base 864 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; base 913 drivers/infiniband/hw/mlx5/qp.c err = set_user_buf_size(dev, qp, &ucmd, base, attr); base 986 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base, base 996 drivers/infiniband/hw/mlx5/qp.c ib_umem_release(base->ubuffer.umem); base 1034 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp_base *base) base 1066 drivers/infiniband/hw/mlx5/qp.c base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); base 1068 drivers/infiniband/hw/mlx5/qp.c err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, base 1277 drivers/infiniband/hw/mlx5/qp.c err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); base 1297 drivers/infiniband/hw/mlx5/qp.c mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); base 1320 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp *mqp = rq->base.container_mibqp; base 1367 drivers/infiniband/hw/mlx5/qp.c err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); base 1377 drivers/infiniband/hw/mlx5/qp.c mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); base 1418 drivers/infiniband/hw/mlx5/qp.c MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); base 1478 drivers/infiniband/hw/mlx5/qp.c resp->sqn = sq->base.mqp.qpn; base 1482 drivers/infiniband/hw/mlx5/qp.c sq->base.container_mibqp = qp; base 1483 drivers/infiniband/hw/mlx5/qp.c sq->base.mqp.event = mlx5_ib_qp_event; base 1487 drivers/infiniband/hw/mlx5/qp.c rq->base.container_mibqp = qp; base 1504 drivers/infiniband/hw/mlx5/qp.c resp->rqn = rq->base.mqp.qpn; base 1525 drivers/infiniband/hw/mlx5/qp.c qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : base 1526 drivers/infiniband/hw/mlx5/qp.c rq->base.mqp.qpn; base 1831 drivers/infiniband/hw/mlx5/qp.c qp->trans_qp.base.mqp.qpn = 0; base 1960 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp_base *base; base 2114 drivers/infiniband/hw/mlx5/qp.c base = (init_attr->qp_type == IB_QPT_RAW_PACKET || base 2116 drivers/infiniband/hw/mlx5/qp.c &qp->raw_packet_qp.rq.base : base 2117 drivers/infiniband/hw/mlx5/qp.c &qp->trans_qp.base; base 2148 drivers/infiniband/hw/mlx5/qp.c &resp, &inlen, base); base 2153 drivers/infiniband/hw/mlx5/qp.c base); base 2287 drivers/infiniband/hw/mlx5/qp.c err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); base 2297 drivers/infiniband/hw/mlx5/qp.c base->container_mibqp = qp; base 2298 drivers/infiniband/hw/mlx5/qp.c base->mqp.event = mlx5_ib_qp_event; base 2321 drivers/infiniband/hw/mlx5/qp.c destroy_qp_user(dev, pd, qp, base, udata); base 2436 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp_base *base; base 2445 drivers/infiniband/hw/mlx5/qp.c base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || base 2447 drivers/infiniband/hw/mlx5/qp.c &qp->raw_packet_qp.rq.base : base 2448 drivers/infiniband/hw/mlx5/qp.c &qp->trans_qp.base; base 2455 drivers/infiniband/hw/mlx5/qp.c NULL, &base->mqp); base 2465 drivers/infiniband/hw/mlx5/qp.c base->mqp.qpn); base 2482 drivers/infiniband/hw/mlx5/qp.c __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, base 2485 drivers/infiniband/hw/mlx5/qp.c __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, base 2495 drivers/infiniband/hw/mlx5/qp.c err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); base 2498 drivers/infiniband/hw/mlx5/qp.c base->mqp.qpn); base 2504 drivers/infiniband/hw/mlx5/qp.c destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata); base 2721 drivers/infiniband/hw/mlx5/qp.c qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; base 2724 drivers/infiniband/hw/mlx5/qp.c qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, base 3180 drivers/infiniband/hw/mlx5/qp.c err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); base 3195 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; base 3243 drivers/infiniband/hw/mlx5/qp.c err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); base 3391 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp_base *base; base 3399 drivers/infiniband/hw/mlx5/qp.c base = &mqp->trans_qp.base; base 3405 drivers/infiniband/hw/mlx5/qp.c &context, &base->mqp); base 3454 drivers/infiniband/hw/mlx5/qp.c struct mlx5_ib_qp_base *base = &qp->trans_qp.base; base 3504 drivers/infiniband/hw/mlx5/qp.c tx_affinity = get_tx_affinity(dev, pd, base, p, base 3693 drivers/infiniband/hw/mlx5/qp.c &base->mqp); base 3716 drivers/infiniband/hw/mlx5/qp.c mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, base 3719 drivers/infiniband/hw/mlx5/qp.c mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); base 4941 drivers/infiniband/hw/mlx5/qp.c ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); base 5519 drivers/infiniband/hw/mlx5/qp.c err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); base 5542 drivers/infiniband/hw/mlx5/qp.c err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); base 5589 drivers/infiniband/hw/mlx5/qp.c qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, base 5590 drivers/infiniband/hw/mlx5/qp.c qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); base 5640 drivers/infiniband/hw/mlx5/qp.c err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, base 751 drivers/infiniband/hw/mthca/mthca_cmd.c static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base) base 760 drivers/infiniband/hw/mthca/mthca_cmd.c if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) { base 763 drivers/infiniband/hw/mthca/mthca_cmd.c (unsigned long long) base, max_off); base 768 drivers/infiniband/hw/mthca/mthca_cmd.c ((pci_resource_len(dev->pdev, 2) - 1) & base); base 781 drivers/infiniband/hw/mthca/mthca_cmd.c u64 base; base 841 drivers/infiniband/hw/mthca/mthca_cmd.c MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE); base 846 drivers/infiniband/hw/mthca/mthca_cmd.c mthca_setup_cmd_doorbells(dev, base); base 646 drivers/infiniband/hw/mthca/mthca_eq.c phys_addr_t base = pci_resource_start(dev->pdev, 0); base 648 drivers/infiniband/hw/mthca/mthca_eq.c *map = ioremap(base + offset, size); base 925 drivers/infiniband/hw/qib/qib_init.c void *base = rcd->rcvegrbuf[e]; base 929 drivers/infiniband/hw/qib/qib_init.c base, rcd->rcvegrbuf_phys[e]); base 174 drivers/infiniband/hw/qib/qib_pcie.c u64 __iomem *base = (void __iomem *) dd->kregbase; base 177 drivers/infiniband/hw/qib/qib_pcie.c iounmap(base); base 185 drivers/infiniband/ulp/ipoib/ipoib_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 186 drivers/infiniband/ulp/ipoib/ipoib_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 204 drivers/infiniband/ulp/ipoib/ipoib_ethtool.c cmd->base.speed = speed * width; base 205 drivers/infiniband/ulp/ipoib/ipoib_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 207 drivers/infiniband/ulp/ipoib/ipoib_ethtool.c cmd->base.phy_address = 0xFF; base 209 drivers/infiniband/ulp/ipoib/ipoib_ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 210 drivers/infiniband/ulp/ipoib/ipoib_ethtool.c cmd->base.port = PORT_OTHER; base 206 drivers/input/keyboard/adp5588-keys.c kpad->gc.base = gpio_data->gpio_start; base 227 drivers/input/keyboard/adp5588-keys.c kpad->gc.base, kpad->gc.ngpio, base 248 drivers/input/keyboard/adp5588-keys.c kpad->gc.base, kpad->gc.ngpio, base 523 drivers/input/keyboard/adp5589-keys.c kpad->gc.base = gpio_data->gpio_start; base 544 drivers/input/keyboard/adp5589-keys.c kpad->gc.base, kpad->gc.ngpio, base 565 drivers/input/keyboard/adp5589-keys.c kpad->gc.base, kpad->gc.ngpio, base 77 drivers/input/keyboard/bcm-keypad.c void __iomem *base; base 112 drivers/input/keyboard/bcm-keypad.c writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num)); base 114 drivers/input/keyboard/bcm-keypad.c state = readl(kp->base + KPSSRN_OFFSET(reg_num)); base 153 drivers/input/keyboard/bcm-keypad.c writel(kp->kpior, kp->base + KPIOR_OFFSET); base 155 drivers/input/keyboard/bcm-keypad.c writel(kp->imr0_val, kp->base + KPIMR0_OFFSET); base 156 drivers/input/keyboard/bcm-keypad.c writel(kp->imr1_val, kp->base + KPIMR1_OFFSET); base 158 drivers/input/keyboard/bcm-keypad.c writel(kp->kpemr, kp->base + KPEMR0_OFFSET); base 159 drivers/input/keyboard/bcm-keypad.c writel(kp->kpemr, kp->base + KPEMR1_OFFSET); base 160 drivers/input/keyboard/bcm-keypad.c writel(kp->kpemr, kp->base + KPEMR2_OFFSET); base 161 drivers/input/keyboard/bcm-keypad.c writel(kp->kpemr, kp->base + KPEMR3_OFFSET); base 163 drivers/input/keyboard/bcm-keypad.c writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET); base 164 drivers/input/keyboard/bcm-keypad.c writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET); base 166 drivers/input/keyboard/bcm-keypad.c kp->last_state[0] = readl(kp->base + KPSSR0_OFFSET); base 167 drivers/input/keyboard/bcm-keypad.c kp->last_state[0] = readl(kp->base + KPSSR1_OFFSET); base 169 drivers/input/keyboard/bcm-keypad.c writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET); base 178 drivers/input/keyboard/bcm-keypad.c val = readl(kp->base + KPCR_OFFSET); base 180 drivers/input/keyboard/bcm-keypad.c writel(0, kp->base + KPCR_OFFSET); base 181 drivers/input/keyboard/bcm-keypad.c writel(0, kp->base + KPIMR0_OFFSET); base 182 drivers/input/keyboard/bcm-keypad.c writel(0, kp->base + KPIMR1_OFFSET); base 183 drivers/input/keyboard/bcm-keypad.c writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET); base 184 drivers/input/keyboard/bcm-keypad.c writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET); base 374 drivers/input/keyboard/bcm-keypad.c kp->base = devm_ioremap_resource(&pdev->dev, res); base 375 drivers/input/keyboard/bcm-keypad.c if (IS_ERR(kp->base)) base 376 drivers/input/keyboard/bcm-keypad.c return PTR_ERR(kp->base); base 56 drivers/input/keyboard/davinci_keyscan.c void __iomem *base; base 71 drivers/input/keyboard/davinci_keyscan.c davinci_ks->base + DAVINCI_KEYSCAN_INTENA); base 75 drivers/input/keyboard/davinci_keyscan.c davinci_ks->base + DAVINCI_KEYSCAN_INTCLR); base 79 drivers/input/keyboard/davinci_keyscan.c davinci_ks->base + DAVINCI_KEYSCAN_STRBWIDTH); base 81 drivers/input/keyboard/davinci_keyscan.c davinci_ks->base + DAVINCI_KEYSCAN_INTERVAL); base 83 drivers/input/keyboard/davinci_keyscan.c davinci_ks->base + DAVINCI_KEYSCAN_CONTTIME); base 100 drivers/input/keyboard/davinci_keyscan.c matrix_ctrl, davinci_ks->base + DAVINCI_KEYSCAN_KEYCTRL); base 117 drivers/input/keyboard/davinci_keyscan.c __raw_writel(0x0, davinci_ks->base + DAVINCI_KEYSCAN_INTENA); base 120 drivers/input/keyboard/davinci_keyscan.c prev_status = __raw_readl(davinci_ks->base + DAVINCI_KEYSCAN_PREVSTATE); base 121 drivers/input/keyboard/davinci_keyscan.c new_status = __raw_readl(davinci_ks->base + DAVINCI_KEYSCAN_CURRENTST); base 143 drivers/input/keyboard/davinci_keyscan.c davinci_ks->base + DAVINCI_KEYSCAN_INTCLR); base 147 drivers/input/keyboard/davinci_keyscan.c __raw_writel(0x1, davinci_ks->base + DAVINCI_KEYSCAN_INTENA); base 218 drivers/input/keyboard/davinci_keyscan.c davinci_ks->base = ioremap(davinci_ks->pbase, davinci_ks->base_size); base 219 drivers/input/keyboard/davinci_keyscan.c if (!davinci_ks->base) { base 277 drivers/input/keyboard/davinci_keyscan.c iounmap(davinci_ks->base); base 296 drivers/input/keyboard/davinci_keyscan.c iounmap(davinci_ks->base); base 63 drivers/input/keyboard/locomokbd.c unsigned long base; base 117 drivers/input/keyboard/locomokbd.c unsigned long membase = locomokbd->base; base 182 drivers/input/keyboard/locomokbd.c r = locomo_readl(locomokbd->base + LOCOMO_KIC); base 186 drivers/input/keyboard/locomokbd.c locomo_writel(r & ~0x0100, locomokbd->base + LOCOMO_KIC); /* Ack */ base 210 drivers/input/keyboard/locomokbd.c r = locomo_readl(locomokbd->base + LOCOMO_KIC) | 0x0010; base 211 drivers/input/keyboard/locomokbd.c locomo_writel(r, locomokbd->base + LOCOMO_KIC); base 220 drivers/input/keyboard/locomokbd.c r = locomo_readl(locomokbd->base + LOCOMO_KIC) & ~0x0010; base 221 drivers/input/keyboard/locomokbd.c locomo_writel(r, locomokbd->base + LOCOMO_KIC); base 248 drivers/input/keyboard/locomokbd.c locomokbd->base = (unsigned long) dev->mapbase; base 71 drivers/input/keyboard/omap4-keypad.c void __iomem *base; base 87 drivers/input/keyboard/omap4-keypad.c return __raw_readl(keypad_data->base + base 94 drivers/input/keyboard/omap4-keypad.c keypad_data->base + keypad_data->reg_offset + offset); base 99 drivers/input/keyboard/omap4-keypad.c return __raw_readl(keypad_data->base + base 107 drivers/input/keyboard/omap4-keypad.c keypad_data->base + keypad_data->irqreg_offset + offset); base 267 drivers/input/keyboard/omap4-keypad.c keypad_data->base = ioremap(res->start, resource_size(res)); base 268 drivers/input/keyboard/omap4-keypad.c if (!keypad_data->base) { base 285 drivers/input/keyboard/omap4-keypad.c rev = __raw_readl(keypad_data->base + OMAP4_KBD_REVISION); base 376 drivers/input/keyboard/omap4-keypad.c iounmap(keypad_data->base); base 395 drivers/input/keyboard/omap4-keypad.c iounmap(keypad_data->base); base 66 drivers/input/keyboard/samsung-keypad.c void __iomem *base; base 94 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCOL); base 97 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFROW); base 102 drivers/input/keyboard/samsung-keypad.c writel(0, keypad->base + SAMSUNG_KEYIFCOL); base 155 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFSTSCLR); base 157 drivers/input/keyboard/samsung-keypad.c writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR); base 185 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFCON); base 187 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCON); base 190 drivers/input/keyboard/samsung-keypad.c writel(0, keypad->base + SAMSUNG_KEYIFCOL); base 207 drivers/input/keyboard/samsung-keypad.c writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR); base 210 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFCON); base 212 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCON); base 362 drivers/input/keyboard/samsung-keypad.c keypad->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); base 363 drivers/input/keyboard/samsung-keypad.c if (!keypad->base) base 478 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFCON); base 480 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCON); base 498 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFCON); base 500 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCON); base 517 drivers/input/keyboard/samsung-keypad.c val = readl(keypad->base + SAMSUNG_KEYIFCON); base 527 drivers/input/keyboard/samsung-keypad.c writel(val, keypad->base + SAMSUNG_KEYIFCON); base 29 drivers/input/keyboard/st-keyscan.c void __iomem *base; base 46 drivers/input/keyboard/st-keyscan.c state = readl(keypad->base + KEYSCAN_MATRIX_STATE_OFF) & 0xffff; base 68 drivers/input/keyboard/st-keyscan.c keypad->base + KEYSCAN_DEBOUNCE_TIME_OFF); base 72 drivers/input/keyboard/st-keyscan.c keypad->base + KEYSCAN_MATRIX_DIM_OFF); base 74 drivers/input/keyboard/st-keyscan.c writel(KEYSCAN_CONFIG_ENABLE, keypad->base + KEYSCAN_CONFIG_OFF); base 81 drivers/input/keyboard/st-keyscan.c writel(0, keypad->base + KEYSCAN_CONFIG_OFF); base 171 drivers/input/keyboard/st-keyscan.c keypad_data->base = devm_ioremap_resource(&pdev->dev, res); base 172 drivers/input/keyboard/st-keyscan.c if (IS_ERR(keypad_data->base)) base 173 drivers/input/keyboard/st-keyscan.c return PTR_ERR(keypad_data->base); base 85 drivers/input/keyboard/sun4i-lradc-keys.c void __iomem *base; base 99 drivers/input/keyboard/sun4i-lradc-keys.c ints = readl(lradc->base + LRADC_INTS); base 112 drivers/input/keyboard/sun4i-lradc-keys.c val = readl(lradc->base + LRADC_DATA0) & 0x3f; base 129 drivers/input/keyboard/sun4i-lradc-keys.c writel(ints, lradc->base + LRADC_INTS); base 151 drivers/input/keyboard/sun4i-lradc-keys.c SAMPLE_RATE(0) | ENABLE(1), lradc->base + LRADC_CTRL); base 153 drivers/input/keyboard/sun4i-lradc-keys.c writel(CHAN0_KEYUP_IRQ | CHAN0_KEYDOWN_IRQ, lradc->base + LRADC_INTC); base 164 drivers/input/keyboard/sun4i-lradc-keys.c SAMPLE_RATE(2), lradc->base + LRADC_CTRL); base 165 drivers/input/keyboard/sun4i-lradc-keys.c writel(0, lradc->base + LRADC_INTC); base 270 drivers/input/keyboard/sun4i-lradc-keys.c lradc->base = devm_ioremap_resource(dev, base 272 drivers/input/keyboard/sun4i-lradc-keys.c if (IS_ERR(lradc->base)) base 273 drivers/input/keyboard/sun4i-lradc-keys.c return PTR_ERR(lradc->base); base 36 drivers/input/misc/msm-vibrator.c void __iomem *base; base 47 drivers/input/misc/msm-vibrator.c writel(value, vibrator->base + offset); base 199 drivers/input/misc/msm-vibrator.c vibrator->base = devm_ioremap(&pdev->dev, res->start, base 201 drivers/input/misc/msm-vibrator.c if (!vibrator->base) { base 21 drivers/input/misc/sc27xx-vibra.c u32 base; base 29 drivers/input/misc/sc27xx-vibra.c regmap_update_bits(info->regmap, info->base, LDO_VIBR_PD, 0); base 30 drivers/input/misc/sc27xx-vibra.c regmap_update_bits(info->regmap, info->base, base 34 drivers/input/misc/sc27xx-vibra.c regmap_update_bits(info->regmap, info->base, LDO_VIBR_PD, base 36 drivers/input/misc/sc27xx-vibra.c regmap_update_bits(info->regmap, info->base, base 44 drivers/input/misc/sc27xx-vibra.c return regmap_update_bits(info->regmap, info->base, CUR_DRV_CAL_SEL, 0); base 93 drivers/input/misc/sc27xx-vibra.c error = device_property_read_u32(&pdev->dev, "reg", &info->base); base 78 drivers/input/misc/wistron_btns.c static ssize_t __init locate_wistron_bios(void __iomem *base) base 85 drivers/input/misc/wistron_btns.c if (check_signature(base + offset, signature, base 94 drivers/input/misc/wistron_btns.c void __iomem *base; base 98 drivers/input/misc/wistron_btns.c base = ioremap(0xF0000, 0x10000); /* Can't fail */ base 99 drivers/input/misc/wistron_btns.c offset = locate_wistron_bios(base); base 102 drivers/input/misc/wistron_btns.c iounmap(base); base 106 drivers/input/misc/wistron_btns.c entry_point = readl(base + offset + 5); base 109 drivers/input/misc/wistron_btns.c base + offset, entry_point); base 112 drivers/input/misc/wistron_btns.c bios_code_map_base = base; base 115 drivers/input/misc/wistron_btns.c iounmap(base); base 79 drivers/input/rmi4/rmi_f34v7.c u8 base; base 82 drivers/input/rmi4/rmi_f34v7.c base = f34->fn->fd.data_base_addr; base 125 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.partition_id, base 140 drivers/input/rmi4/rmi_f34v7.c u8 base; base 143 drivers/input/rmi4/rmi_f34v7.c base = f34->fn->fd.data_base_addr; base 198 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.flash_cmd, base 212 drivers/input/rmi4/rmi_f34v7.c u8 base; base 215 drivers/input/rmi4/rmi_f34v7.c base = f34->fn->fd.data_base_addr; base 265 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.partition_id, base 280 drivers/input/rmi4/rmi_f34v7.c u8 base; base 284 drivers/input/rmi4/rmi_f34v7.c base = f34->fn->fd.data_base_addr; base 293 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.block_number, base 304 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.transfer_length, base 333 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.payload, base 424 drivers/input/rmi4/rmi_f34v7.c u8 base; base 429 drivers/input/rmi4/rmi_f34v7.c base = f34->fn->fd.query_base_addr; base 432 drivers/input/rmi4/rmi_f34v7.c base, base 444 drivers/input/rmi4/rmi_f34v7.c base + offset, base 466 drivers/input/rmi4/rmi_f34v7.c u8 base; base 472 drivers/input/rmi4/rmi_f34v7.c base = f34->fn->fd.query_base_addr; base 475 drivers/input/rmi4/rmi_f34v7.c base, base 487 drivers/input/rmi4/rmi_f34v7.c base + offset, base 744 drivers/input/rmi4/rmi_f34v7.c u8 base; base 752 drivers/input/rmi4/rmi_f34v7.c base = f34->fn->fd.data_base_addr; base 759 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.block_number, base 775 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.transfer_length, base 795 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.payload, base 817 drivers/input/rmi4/rmi_f34v7.c u8 base; base 824 drivers/input/rmi4/rmi_f34v7.c base = f34->fn->fd.data_base_addr; base 831 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.block_number, base 851 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.transfer_length, base 865 drivers/input/rmi4/rmi_f34v7.c base + f34->v7.off.payload, base 24 drivers/input/serio/altera_ps2.c void __iomem *base; base 37 drivers/input/serio/altera_ps2.c while ((status = readl(ps2if->base)) & 0xffff0000) { base 52 drivers/input/serio/altera_ps2.c writel(val, ps2if->base); base 61 drivers/input/serio/altera_ps2.c while (readl(ps2if->base) & 0xffff0000) base 64 drivers/input/serio/altera_ps2.c writel(1, ps2if->base + 4); /* enable rx irq */ base 72 drivers/input/serio/altera_ps2.c writel(0, ps2if->base + 4); /* disable rx irq */ base 90 drivers/input/serio/altera_ps2.c ps2if->base = devm_ioremap_resource(&pdev->dev, res); base 91 drivers/input/serio/altera_ps2.c if (IS_ERR(ps2if->base)) base 92 drivers/input/serio/altera_ps2.c return PTR_ERR(ps2if->base); base 119 drivers/input/serio/altera_ps2.c dev_info(&pdev->dev, "base %p, irq %d\n", ps2if->base, irq); base 24 drivers/input/serio/ambakmi.c #define KMI_BASE (kmi->base) base 29 drivers/input/serio/ambakmi.c void __iomem *base; base 135 drivers/input/serio/ambakmi.c kmi->base = ioremap(dev->res.start, resource_size(&dev->res)); base 136 drivers/input/serio/ambakmi.c if (!kmi->base) { base 154 drivers/input/serio/ambakmi.c iounmap(kmi->base); base 168 drivers/input/serio/ambakmi.c iounmap(kmi->base); base 67 drivers/input/serio/olpc_apsp.c void __iomem *base; base 85 drivers/input/serio/olpc_apsp.c u32 sts = readl(priv->base + COMMAND_FIFO_STATUS); base 88 drivers/input/serio/olpc_apsp.c priv->base + SECURE_PROCESSOR_COMMAND); base 96 drivers/input/serio/olpc_apsp.c readl(priv->base + COMMAND_FIFO_STATUS)); base 111 drivers/input/serio/olpc_apsp.c tmp = readl(priv->base + PJ_RST_INTERRUPT); base 117 drivers/input/serio/olpc_apsp.c w = readl(priv->base + COMMAND_RETURN_STATUS); base 128 drivers/input/serio/olpc_apsp.c writel(tmp | SP_COMMAND_COMPLETE_RESET, priv->base + PJ_RST_INTERRUPT); base 129 drivers/input/serio/olpc_apsp.c writel(PORT_MASK, priv->base + SECURE_PROCESSOR_COMMAND); base 142 drivers/input/serio/olpc_apsp.c l = readl(priv->base + COMMAND_FIFO_STATUS); base 149 drivers/input/serio/olpc_apsp.c tmp = readl(priv->base + PJ_INTERRUPT_MASK); base 150 drivers/input/serio/olpc_apsp.c writel(tmp & ~INT_0, priv->base + PJ_INTERRUPT_MASK); base 163 drivers/input/serio/olpc_apsp.c tmp = readl(priv->base + PJ_INTERRUPT_MASK); base 164 drivers/input/serio/olpc_apsp.c writel(tmp | INT_0, priv->base + PJ_INTERRUPT_MASK); base 182 drivers/input/serio/olpc_apsp.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 183 drivers/input/serio/olpc_apsp.c if (IS_ERR(priv->base)) { base 185 drivers/input/serio/olpc_apsp.c return PTR_ERR(priv->base); base 39 drivers/input/serio/pcips2.c unsigned int base; base 49 drivers/input/serio/pcips2.c stat = inb(ps2if->base + PS2_STATUS); base 53 drivers/input/serio/pcips2.c outb(val, ps2if->base + PS2_DATA); base 67 drivers/input/serio/pcips2.c status = inb(ps2if->base + PS2_STATUS); base 71 drivers/input/serio/pcips2.c scancode = inb(ps2if->base + PS2_DATA); base 90 drivers/input/serio/pcips2.c status = inb(ps2if->base + PS2_STATUS); base 93 drivers/input/serio/pcips2.c scancode = inb(ps2if->base + PS2_DATA); base 104 drivers/input/serio/pcips2.c outb(PS2_CTRL_ENABLE, ps2if->base); base 112 drivers/input/serio/pcips2.c outb(val, ps2if->base); base 121 drivers/input/serio/pcips2.c outb(0, ps2if->base); base 158 drivers/input/serio/pcips2.c ps2if->base = pci_resource_start(dev, 0); base 46 drivers/input/serio/sa1111ps2.c void __iomem *base; base 66 drivers/input/serio/sa1111ps2.c status = readl_relaxed(ps2if->base + PS2STAT); base 69 drivers/input/serio/sa1111ps2.c writel_relaxed(PS2STAT_STP, ps2if->base + PS2STAT); base 74 drivers/input/serio/sa1111ps2.c scancode = readl_relaxed(ps2if->base + PS2DATA) & 0xff; base 81 drivers/input/serio/sa1111ps2.c status = readl_relaxed(ps2if->base + PS2STAT); base 96 drivers/input/serio/sa1111ps2.c status = readl_relaxed(ps2if->base + PS2STAT); base 101 drivers/input/serio/sa1111ps2.c writel_relaxed(ps2if->buf[ps2if->tail], ps2if->base + PS2DATA); base 124 drivers/input/serio/sa1111ps2.c if (readl_relaxed(ps2if->base + PS2STAT) & PS2STAT_TXE) { base 125 drivers/input/serio/sa1111ps2.c writel_relaxed(val, ps2if->base + PS2DATA); base 172 drivers/input/serio/sa1111ps2.c writel_relaxed(PS2CR_ENA, ps2if->base + PS2CR); base 180 drivers/input/serio/sa1111ps2.c writel_relaxed(0, ps2if->base + PS2CR); base 200 drivers/input/serio/sa1111ps2.c if ((readl_relaxed(ps2if->base + PS2DATA) & 0xff) == 0xff) base 210 drivers/input/serio/sa1111ps2.c writel_relaxed(PS2CR_ENA | mask, ps2if->base + PS2CR); base 214 drivers/input/serio/sa1111ps2.c val = readl_relaxed(ps2if->base + PS2STAT); base 245 drivers/input/serio/sa1111ps2.c writel_relaxed(0, ps2if->base + PS2CR); base 305 drivers/input/serio/sa1111ps2.c ps2if->base = dev->mapbase; base 310 drivers/input/serio/sa1111ps2.c writel_relaxed(0, ps2if->base + PS2CLKDIV); base 311 drivers/input/serio/sa1111ps2.c writel_relaxed(127, ps2if->base + PS2PRECNT); base 471 drivers/input/touchscreen/ad7879.c ts->gc.base = -1; base 480 drivers/input/touchscreen/ad7879.c ts->gc.base); base 1262 drivers/input/touchscreen/atmel_mxt_ts.c static u32 mxt_calculate_crc(u8 *base, off_t start_off, off_t end_off) base 1265 drivers/input/touchscreen/atmel_mxt_ts.c u8 *ptr = base + start_off; base 1266 drivers/input/touchscreen/atmel_mxt_ts.c u8 *last_val = base + end_off - 1; base 45 drivers/input/touchscreen/mxs-lradc-ts.c void __iomem *base; base 93 drivers/input/touchscreen/mxs-lradc-ts.c return !!(readl(ts->base + LRADC_STATUS) & base 101 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); base 103 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); base 118 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CH(ch)); base 125 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CH(ch) + STMP_OFFSET_REG_CLR); base 138 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_DELAY(3)); base 141 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 151 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_DELAY(2)); base 175 drivers/input/touchscreen/mxs-lradc-ts.c writel(reg, ts->base + LRADC_CH(ch1)); base 176 drivers/input/touchscreen/mxs-lradc-ts.c writel(reg, ts->base + LRADC_CH(ch2)); base 183 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CH(ch1) + STMP_OFFSET_REG_CLR); base 185 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CH(ch2) + STMP_OFFSET_REG_CLR); base 192 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_DELAY(3)); base 195 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 205 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_DELAY(2)); base 214 drivers/input/touchscreen/mxs-lradc-ts.c reg = readl(ts->base + LRADC_CH(channel)); base 231 drivers/input/touchscreen/mxs-lradc-ts.c reg = readl(ts->base + LRADC_CTRL1) & mask; base 234 drivers/input/touchscreen/mxs-lradc-ts.c reg = readl(ts->base + LRADC_CTRL1) & mask; base 283 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); base 285 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); base 305 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); base 307 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); base 331 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); base 333 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); base 357 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); base 359 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); base 374 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 376 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); base 382 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 384 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); base 409 drivers/input/touchscreen/mxs-lradc-ts.c writel(0, ts->base + LRADC_CH(TOUCHSCREEN_VCHANNEL1)); base 412 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 415 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_DELAY(2)); base 445 drivers/input/touchscreen/mxs-lradc-ts.c writel(0, ts->base + LRADC_DELAY(2)); base 446 drivers/input/touchscreen/mxs-lradc-ts.c writel(0, ts->base + LRADC_DELAY(3)); base 450 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 452 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); base 463 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 497 drivers/input/touchscreen/mxs-lradc-ts.c unsigned long reg = readl(ts->base + LRADC_CTRL1); base 516 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 541 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 545 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); base 548 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); base 551 drivers/input/touchscreen/mxs-lradc-ts.c writel(0, ts->base + LRADC_DELAY(i)); base 568 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); base 572 drivers/input/touchscreen/mxs-lradc-ts.c ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); base 622 drivers/input/touchscreen/mxs-lradc-ts.c ts->base = devm_platform_ioremap_resource(pdev, 0); base 623 drivers/input/touchscreen/mxs-lradc-ts.c if (IS_ERR(ts->base)) base 624 drivers/input/touchscreen/mxs-lradc-ts.c return PTR_ERR(ts->base); base 667 drivers/input/touchscreen/mxs-lradc-ts.c ret = stmp_reset_block(ts->base); base 109 drivers/input/touchscreen/sun4i-ts.c void __iomem *base; base 122 drivers/input/touchscreen/sun4i-ts.c x = readl(ts->base + TP_DATA); base 123 drivers/input/touchscreen/sun4i-ts.c y = readl(ts->base + TP_DATA); base 152 drivers/input/touchscreen/sun4i-ts.c reg_val = readl(ts->base + TP_INT_FIFOS); base 155 drivers/input/touchscreen/sun4i-ts.c ts->temp_data = readl(ts->base + TEMP_DATA); base 160 drivers/input/touchscreen/sun4i-ts.c writel(reg_val, ts->base + TP_INT_FIFOS); base 171 drivers/input/touchscreen/sun4i-ts.c TP_UP_IRQ_EN(1), ts->base + TP_INT_FIFOC); base 181 drivers/input/touchscreen/sun4i-ts.c writel(TEMP_IRQ_EN(1), ts->base + TP_INT_FIFOC); base 304 drivers/input/touchscreen/sun4i-ts.c ts->base = devm_platform_ioremap_resource(pdev, 0); base 305 drivers/input/touchscreen/sun4i-ts.c if (IS_ERR(ts->base)) base 306 drivers/input/touchscreen/sun4i-ts.c return PTR_ERR(ts->base); base 318 drivers/input/touchscreen/sun4i-ts.c ts->base + TP_CTRL0); base 327 drivers/input/touchscreen/sun4i-ts.c ts->base + TP_CTRL2); base 334 drivers/input/touchscreen/sun4i-ts.c writel(FILTER_EN(1) | FILTER_TYPE(filter_type), ts->base + TP_CTRL3); base 337 drivers/input/touchscreen/sun4i-ts.c writel(TEMP_ENABLE(1) | TEMP_PERIOD(1953), ts->base + TP_TPR); base 348 drivers/input/touchscreen/sun4i-ts.c writel(reg, ts->base + TP_CTRL1); base 364 drivers/input/touchscreen/sun4i-ts.c writel(TEMP_IRQ_EN(1), ts->base + TP_INT_FIFOC); base 369 drivers/input/touchscreen/sun4i-ts.c writel(0, ts->base + TP_INT_FIFOC); base 387 drivers/input/touchscreen/sun4i-ts.c writel(0, ts->base + TP_INT_FIFOC); base 40 drivers/input/touchscreen/ts4800-ts.c void __iomem *base; base 77 drivers/input/touchscreen/ts4800-ts.c u16 last_x = readw(ts->base + X_OFFSET); base 78 drivers/input/touchscreen/ts4800-ts.c u16 last_y = readw(ts->base + Y_OFFSET); base 161 drivers/input/touchscreen/ts4800-ts.c ts->base = devm_platform_ioremap_resource(pdev, 0); base 162 drivers/input/touchscreen/ts4800-ts.c if (IS_ERR(ts->base)) base 163 drivers/input/touchscreen/ts4800-ts.c return PTR_ERR(ts->base); base 4491 drivers/iommu/amd_iommu.c ir_data->ga_root_ptr = (pi_data->base >> 12); base 1598 drivers/iommu/amd_iommu_init.c u8 *base = (u8 *)ivrs; base 1600 drivers/iommu/amd_iommu_init.c (base + IVRS_HEADER_LENGTH); base 1604 drivers/iommu/amd_iommu_init.c while (((u8 *)ivhd - base < ivrs->length) && base 188 drivers/iommu/arm-smmu-v3.c #define Q_ENT(q, p) ((q)->base + \ base 509 drivers/iommu/arm-smmu-v3.c __le64 *base; base 581 drivers/iommu/arm-smmu-v3.c void __iomem *base; base 689 drivers/iommu/arm-smmu-v3.c return smmu->base + offset; base 1794 drivers/iommu/arm-smmu-v3.c gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); base 1795 drivers/iommu/arm-smmu-v3.c gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); base 1831 drivers/iommu/arm-smmu-v3.c writel(gerror, smmu->base + ARM_SMMU_GERRORN); base 2756 drivers/iommu/arm-smmu-v3.c q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma, base 2758 drivers/iommu/arm-smmu-v3.c if (q->base || qsz < PAGE_SIZE) base 2764 drivers/iommu/arm-smmu-v3.c if (!q->base) { base 2973 drivers/iommu/arm-smmu-v3.c writel_relaxed(val, smmu->base + reg_off); base 2974 drivers/iommu/arm-smmu-v3.c return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, base 2982 drivers/iommu/arm-smmu-v3.c u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA; base 3016 drivers/iommu/arm-smmu-v3.c writeq_relaxed(doorbell, smmu->base + cfg[0]); base 3017 drivers/iommu/arm-smmu-v3.c writel_relaxed(msg->data, smmu->base + cfg[1]); base 3018 drivers/iommu/arm-smmu-v3.c writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]); base 3028 drivers/iommu/arm-smmu-v3.c writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); base 3029 drivers/iommu/arm-smmu-v3.c writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); base 3032 drivers/iommu/arm-smmu-v3.c writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); base 3176 drivers/iommu/arm-smmu-v3.c reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); base 3194 drivers/iommu/arm-smmu-v3.c writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); base 3198 drivers/iommu/arm-smmu-v3.c writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); base 3202 drivers/iommu/arm-smmu-v3.c smmu->base + ARM_SMMU_STRTAB_BASE); base 3204 drivers/iommu/arm-smmu-v3.c smmu->base + ARM_SMMU_STRTAB_BASE_CFG); base 3207 drivers/iommu/arm-smmu-v3.c writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); base 3208 drivers/iommu/arm-smmu-v3.c writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); base 3209 drivers/iommu/arm-smmu-v3.c writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); base 3235 drivers/iommu/arm-smmu-v3.c writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); base 3252 drivers/iommu/arm-smmu-v3.c smmu->base + ARM_SMMU_PRIQ_BASE); base 3310 drivers/iommu/arm-smmu-v3.c reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); base 3402 drivers/iommu/arm-smmu-v3.c reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); base 3440 drivers/iommu/arm-smmu-v3.c reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); base 3610 drivers/iommu/arm-smmu-v3.c smmu->base = devm_ioremap_resource(dev, res); base 3611 drivers/iommu/arm-smmu-v3.c if (IS_ERR(smmu->base)) base 3612 drivers/iommu/arm-smmu-v3.c return PTR_ERR(smmu->base); base 2033 drivers/iommu/arm-smmu.c smmu->base = devm_ioremap_resource(dev, res); base 2034 drivers/iommu/arm-smmu.c if (IS_ERR(smmu->base)) base 2035 drivers/iommu/arm-smmu.c return PTR_ERR(smmu->base); base 228 drivers/iommu/arm-smmu.h void __iomem *base; base 342 drivers/iommu/arm-smmu.h return smmu->base + (n << smmu->pgshift); base 103 drivers/iommu/dma-iommu.c int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) base 117 drivers/iommu/dma-iommu.c cookie->msi_iova = base; base 301 drivers/iommu/dma-iommu.c static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, base 316 drivers/iommu/dma-iommu.c base_pfn = max_t(unsigned long, 1, base >> order); base 320 drivers/iommu/dma-iommu.c if (base > domain->geometry.aperture_end || base 321 drivers/iommu/dma-iommu.c base + size <= domain->geometry.aperture_start) { base 824 drivers/iommu/exynos-iommu.c phys_addr_t base = lv2table_base(domain->pgtable + i); base 826 drivers/iommu/exynos-iommu.c dma_unmap_single(dma_dev, base, LV2TABLE_SIZE, base 829 drivers/iommu/exynos-iommu.c phys_to_virt(base)); base 315 drivers/iommu/intel-iommu-debugfs.c ri_entry = &iommu->ir_table->base[idx]; base 339 drivers/iommu/intel-iommu-debugfs.c pi_entry = &iommu->ir_table->base[idx]; base 375 drivers/iommu/intel-iommu-debugfs.c irta = virt_to_phys(iommu->ir_table->base); base 394 drivers/iommu/intel-iommu-debugfs.c irta = virt_to_phys(iommu->ir_table->base); base 173 drivers/iommu/intel_irq_remapping.c irte = &iommu->ir_table->base[index]; base 249 drivers/iommu/intel_irq_remapping.c start = iommu->ir_table->base + index; base 455 drivers/iommu/intel_irq_remapping.c memcpy(iommu->ir_table->base, old_ir_table, size); base 457 drivers/iommu/intel_irq_remapping.c __iommu_flush_cache(iommu, iommu->ir_table->base, size); base 464 drivers/iommu/intel_irq_remapping.c if (iommu->ir_table->base[i].present) base 480 drivers/iommu/intel_irq_remapping.c addr = virt_to_phys((void *)iommu->ir_table->base); base 576 drivers/iommu/intel_irq_remapping.c ir_table->base = page_address(pages); base 640 drivers/iommu/intel_irq_remapping.c free_pages((unsigned long)iommu->ir_table->base, base 57 drivers/iommu/ipmmu-vmsa.c void __iomem *base; base 258 drivers/iommu/ipmmu-vmsa.c return ioread32(mmu->base + offset); base 264 drivers/iommu/ipmmu-vmsa.c iowrite32(data, mmu->base + offset); base 1068 drivers/iommu/ipmmu-vmsa.c mmu->base = devm_ioremap_resource(&pdev->dev, res); base 1069 drivers/iommu/ipmmu-vmsa.c if (IS_ERR(mmu->base)) base 1070 drivers/iommu/ipmmu-vmsa.c return PTR_ERR(mmu->base); base 1085 drivers/iommu/ipmmu-vmsa.c mmu->base += IM_NS_ALIAS_OFFSET; base 79 drivers/iommu/msm_iommu.c static void msm_iommu_reset(void __iomem *base, int ncb) base 83 drivers/iommu/msm_iommu.c SET_RPUE(base, 0); base 84 drivers/iommu/msm_iommu.c SET_RPUEIE(base, 0); base 85 drivers/iommu/msm_iommu.c SET_ESRRESTORE(base, 0); base 86 drivers/iommu/msm_iommu.c SET_TBE(base, 0); base 87 drivers/iommu/msm_iommu.c SET_CR(base, 0); base 88 drivers/iommu/msm_iommu.c SET_SPDMBE(base, 0); base 89 drivers/iommu/msm_iommu.c SET_TESTBUSCR(base, 0); base 90 drivers/iommu/msm_iommu.c SET_TLBRSW(base, 0); base 91 drivers/iommu/msm_iommu.c SET_GLOBAL_TLBIALL(base, 0); base 92 drivers/iommu/msm_iommu.c SET_RPU_ACR(base, 0); base 93 drivers/iommu/msm_iommu.c SET_TLBLKCRWE(base, 1); base 96 drivers/iommu/msm_iommu.c SET_BPRCOSH(base, ctx, 0); base 97 drivers/iommu/msm_iommu.c SET_BPRCISH(base, ctx, 0); base 98 drivers/iommu/msm_iommu.c SET_BPRCNSH(base, ctx, 0); base 99 drivers/iommu/msm_iommu.c SET_BPSHCFG(base, ctx, 0); base 100 drivers/iommu/msm_iommu.c SET_BPMTCFG(base, ctx, 0); base 101 drivers/iommu/msm_iommu.c SET_ACTLR(base, ctx, 0); base 102 drivers/iommu/msm_iommu.c SET_SCTLR(base, ctx, 0); base 103 drivers/iommu/msm_iommu.c SET_FSRRESTORE(base, ctx, 0); base 104 drivers/iommu/msm_iommu.c SET_TTBR0(base, ctx, 0); base 105 drivers/iommu/msm_iommu.c SET_TTBR1(base, ctx, 0); base 106 drivers/iommu/msm_iommu.c SET_TTBCR(base, ctx, 0); base 107 drivers/iommu/msm_iommu.c SET_BFBCR(base, ctx, 0); base 108 drivers/iommu/msm_iommu.c SET_PAR(base, ctx, 0); base 109 drivers/iommu/msm_iommu.c SET_FAR(base, ctx, 0); base 110 drivers/iommu/msm_iommu.c SET_CTX_TLBIALL(base, ctx, 0); base 111 drivers/iommu/msm_iommu.c SET_TLBFLPTER(base, ctx, 0); base 112 drivers/iommu/msm_iommu.c SET_TLBSLPTER(base, ctx, 0); base 113 drivers/iommu/msm_iommu.c SET_TLBLKCR(base, ctx, 0); base 114 drivers/iommu/msm_iommu.c SET_CONTEXTIDR(base, ctx, 0); base 131 drivers/iommu/msm_iommu.c SET_CTX_TLBIALL(iommu->base, master->num, 0); base 157 drivers/iommu/msm_iommu.c iova |= GET_CONTEXTIDR_ASID(iommu->base, base 159 drivers/iommu/msm_iommu.c SET_TLBIVA(iommu->base, master->num, iova); base 223 drivers/iommu/msm_iommu.c SET_M2VCBR_N(iommu->base, mid, 0); base 224 drivers/iommu/msm_iommu.c SET_CBACR_N(iommu->base, ctx, 0); base 227 drivers/iommu/msm_iommu.c SET_VMID(iommu->base, mid, 0); base 230 drivers/iommu/msm_iommu.c SET_CBNDX(iommu->base, mid, ctx); base 233 drivers/iommu/msm_iommu.c SET_CBVMID(iommu->base, ctx, 0); base 236 drivers/iommu/msm_iommu.c SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx); base 239 drivers/iommu/msm_iommu.c SET_NSCFG(iommu->base, mid, 3); base 243 drivers/iommu/msm_iommu.c static void __reset_context(void __iomem *base, int ctx) base 245 drivers/iommu/msm_iommu.c SET_BPRCOSH(base, ctx, 0); base 246 drivers/iommu/msm_iommu.c SET_BPRCISH(base, ctx, 0); base 247 drivers/iommu/msm_iommu.c SET_BPRCNSH(base, ctx, 0); base 248 drivers/iommu/msm_iommu.c SET_BPSHCFG(base, ctx, 0); base 249 drivers/iommu/msm_iommu.c SET_BPMTCFG(base, ctx, 0); base 250 drivers/iommu/msm_iommu.c SET_ACTLR(base, ctx, 0); base 251 drivers/iommu/msm_iommu.c SET_SCTLR(base, ctx, 0); base 252 drivers/iommu/msm_iommu.c SET_FSRRESTORE(base, ctx, 0); base 253 drivers/iommu/msm_iommu.c SET_TTBR0(base, ctx, 0); base 254 drivers/iommu/msm_iommu.c SET_TTBR1(base, ctx, 0); base 255 drivers/iommu/msm_iommu.c SET_TTBCR(base, ctx, 0); base 256 drivers/iommu/msm_iommu.c SET_BFBCR(base, ctx, 0); base 257 drivers/iommu/msm_iommu.c SET_PAR(base, ctx, 0); base 258 drivers/iommu/msm_iommu.c SET_FAR(base, ctx, 0); base 259 drivers/iommu/msm_iommu.c SET_CTX_TLBIALL(base, ctx, 0); base 260 drivers/iommu/msm_iommu.c SET_TLBFLPTER(base, ctx, 0); base 261 drivers/iommu/msm_iommu.c SET_TLBSLPTER(base, ctx, 0); base 262 drivers/iommu/msm_iommu.c SET_TLBLKCR(base, ctx, 0); base 265 drivers/iommu/msm_iommu.c static void __program_context(void __iomem *base, int ctx, base 268 drivers/iommu/msm_iommu.c __reset_context(base, ctx); base 271 drivers/iommu/msm_iommu.c SET_TRE(base, ctx, 1); base 272 drivers/iommu/msm_iommu.c SET_AFE(base, ctx, 1); base 276 drivers/iommu/msm_iommu.c SET_TLBMCFG(base, ctx, 0x3); base 279 drivers/iommu/msm_iommu.c SET_V2PCFG(base, ctx, 0x3); base 281 drivers/iommu/msm_iommu.c SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr); base 282 drivers/iommu/msm_iommu.c SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]); base 283 drivers/iommu/msm_iommu.c SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]); base 286 drivers/iommu/msm_iommu.c SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr); base 287 drivers/iommu/msm_iommu.c SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr); base 290 drivers/iommu/msm_iommu.c SET_CTX_TLBIALL(base, ctx, 0); base 293 drivers/iommu/msm_iommu.c SET_IRPTNDX(base, ctx, 0); base 296 drivers/iommu/msm_iommu.c SET_CFEIE(base, ctx, 1); base 299 drivers/iommu/msm_iommu.c SET_CFCFG(base, ctx, 1); base 302 drivers/iommu/msm_iommu.c SET_RCISH(base, ctx, 1); base 303 drivers/iommu/msm_iommu.c SET_RCOSH(base, ctx, 1); base 304 drivers/iommu/msm_iommu.c SET_RCNSH(base, ctx, 1); base 307 drivers/iommu/msm_iommu.c SET_BFBDFE(base, ctx, 1); base 310 drivers/iommu/msm_iommu.c SET_M(base, ctx, 1); base 465 drivers/iommu/msm_iommu.c __program_context(iommu->base, master->num, base 498 drivers/iommu/msm_iommu.c __reset_context(iommu->base, master->num); base 562 drivers/iommu/msm_iommu.c SET_CTX_TLBIALL(iommu->base, master->num, 0); base 563 drivers/iommu/msm_iommu.c SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA); base 565 drivers/iommu/msm_iommu.c par = GET_PAR(iommu->base, master->num); base 568 drivers/iommu/msm_iommu.c if (GET_NOFAULT_SS(iommu->base, master->num)) base 573 drivers/iommu/msm_iommu.c if (GET_FAULT(iommu->base, master->num)) base 587 drivers/iommu/msm_iommu.c static void print_ctx_regs(void __iomem *base, int ctx) base 589 drivers/iommu/msm_iommu.c unsigned int fsr = GET_FSR(base, ctx); base 591 drivers/iommu/msm_iommu.c GET_FAR(base, ctx), GET_PAR(base, ctx)); base 605 drivers/iommu/msm_iommu.c GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx)); base 607 drivers/iommu/msm_iommu.c GET_TTBR0(base, ctx), GET_TTBR1(base, ctx)); base 609 drivers/iommu/msm_iommu.c GET_SCTLR(base, ctx), GET_ACTLR(base, ctx)); base 674 drivers/iommu/msm_iommu.c pr_err("base = %08x\n", (unsigned int)iommu->base); base 681 drivers/iommu/msm_iommu.c fsr = GET_FSR(iommu->base, i); base 685 drivers/iommu/msm_iommu.c print_ctx_regs(iommu->base, i); base 686 drivers/iommu/msm_iommu.c SET_FSR(iommu->base, i, 0x4000000F); base 759 drivers/iommu/msm_iommu.c iommu->base = devm_ioremap_resource(iommu->dev, r); base 760 drivers/iommu/msm_iommu.c if (IS_ERR(iommu->base)) { base 762 drivers/iommu/msm_iommu.c ret = PTR_ERR(iommu->base); base 780 drivers/iommu/msm_iommu.c msm_iommu_reset(iommu->base, iommu->ncb); base 781 drivers/iommu/msm_iommu.c SET_M(iommu->base, 0, 1); base 782 drivers/iommu/msm_iommu.c SET_PAR(iommu->base, 0, 0); base 783 drivers/iommu/msm_iommu.c SET_V2PCFG(iommu->base, 0, 1); base 784 drivers/iommu/msm_iommu.c SET_V2PPR(iommu->base, 0, 0); base 785 drivers/iommu/msm_iommu.c par = GET_PAR(iommu->base, 0); base 786 drivers/iommu/msm_iommu.c SET_V2PCFG(iommu->base, 0, 0); base 787 drivers/iommu/msm_iommu.c SET_M(iommu->base, 0, 0); base 826 drivers/iommu/msm_iommu.c iommu->base, iommu->irq, iommu->ncb); base 49 drivers/iommu/msm_iommu.h void __iomem *base; base 10 drivers/iommu/msm_iommu_hw-8xxx.h #define GET_GLOBAL_REG(reg, base) (readl((base) + (reg))) base 11 drivers/iommu/msm_iommu_hw-8xxx.h #define GET_CTX_REG(reg, base, ctx) \ base 12 drivers/iommu/msm_iommu_hw-8xxx.h (readl((base) + (reg) + ((ctx) << CTX_SHIFT))) base 14 drivers/iommu/msm_iommu_hw-8xxx.h #define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg))) base 16 drivers/iommu/msm_iommu_hw-8xxx.h #define SET_CTX_REG(reg, base, ctx, val) \ base 17 drivers/iommu/msm_iommu_hw-8xxx.h writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT))) base 170 drivers/iommu/mtk_iommu.c data->base + REG_MMU_INV_SEL); base 171 drivers/iommu/mtk_iommu.c writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); base 184 drivers/iommu/mtk_iommu.c data->base + REG_MMU_INV_SEL); base 186 drivers/iommu/mtk_iommu.c writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); base 188 drivers/iommu/mtk_iommu.c data->base + REG_MMU_INVLD_END_A); base 190 drivers/iommu/mtk_iommu.c data->base + REG_MMU_INVALIDATE); base 206 drivers/iommu/mtk_iommu.c ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, base 214 drivers/iommu/mtk_iommu.c writel_relaxed(0, data->base + REG_MMU_CPE_DONE); base 271 drivers/iommu/mtk_iommu.c int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); base 273 drivers/iommu/mtk_iommu.c regval = readl_relaxed(data->base + REG_MMU0_INT_ID); base 274 drivers/iommu/mtk_iommu.c fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); base 275 drivers/iommu/mtk_iommu.c fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); base 277 drivers/iommu/mtk_iommu.c regval = readl_relaxed(data->base + REG_MMU1_INT_ID); base 278 drivers/iommu/mtk_iommu.c fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); base 279 drivers/iommu/mtk_iommu.c fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); base 298 drivers/iommu/mtk_iommu.c regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); base 300 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); base 411 drivers/iommu/mtk_iommu.c data->base + REG_MMU_PT_BASE_ADDR); base 606 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); base 614 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); base 623 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); base 630 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); base 638 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); base 640 drivers/iommu/mtk_iommu.c writel_relaxed(0, data->base + REG_MMU_DCM_DIS); base 643 drivers/iommu/mtk_iommu.c writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); base 647 drivers/iommu/mtk_iommu.c writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); base 689 drivers/iommu/mtk_iommu.c data->base = devm_ioremap_resource(dev, res); base 690 drivers/iommu/mtk_iommu.c if (IS_ERR(data->base)) base 691 drivers/iommu/mtk_iommu.c return PTR_ERR(data->base); base 785 drivers/iommu/mtk_iommu.c void __iomem *base = data->base; base 787 drivers/iommu/mtk_iommu.c reg->standard_axi_mode = readl_relaxed(base + base 789 drivers/iommu/mtk_iommu.c reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); base 790 drivers/iommu/mtk_iommu.c reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); base 791 drivers/iommu/mtk_iommu.c reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); base 792 drivers/iommu/mtk_iommu.c reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); base 793 drivers/iommu/mtk_iommu.c reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); base 794 drivers/iommu/mtk_iommu.c reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); base 804 drivers/iommu/mtk_iommu.c void __iomem *base = data->base; base 813 drivers/iommu/mtk_iommu.c base + REG_MMU_STANDARD_AXI_MODE); base 814 drivers/iommu/mtk_iommu.c writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); base 815 drivers/iommu/mtk_iommu.c writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); base 816 drivers/iommu/mtk_iommu.c writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); base 817 drivers/iommu/mtk_iommu.c writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); base 818 drivers/iommu/mtk_iommu.c writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); base 819 drivers/iommu/mtk_iommu.c writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); base 822 drivers/iommu/mtk_iommu.c base + REG_MMU_PT_BASE_ADDR); base 51 drivers/iommu/mtk_iommu.h void __iomem *base; base 130 drivers/iommu/mtk_iommu_v1.c data->base + REG_MMU_INV_SEL); base 131 drivers/iommu/mtk_iommu_v1.c writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); base 142 drivers/iommu/mtk_iommu_v1.c data->base + REG_MMU_INV_SEL); base 144 drivers/iommu/mtk_iommu_v1.c data->base + REG_MMU_INVLD_START_A); base 146 drivers/iommu/mtk_iommu_v1.c data->base + REG_MMU_INVLD_END_A); base 147 drivers/iommu/mtk_iommu_v1.c writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); base 149 drivers/iommu/mtk_iommu_v1.c ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, base 157 drivers/iommu/mtk_iommu_v1.c writel_relaxed(0, data->base + REG_MMU_CPE_DONE); base 168 drivers/iommu/mtk_iommu_v1.c int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); base 169 drivers/iommu/mtk_iommu_v1.c fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); base 172 drivers/iommu/mtk_iommu_v1.c fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); base 173 drivers/iommu/mtk_iommu_v1.c regval = readl_relaxed(data->base + REG_MMU_INT_ID); base 189 drivers/iommu/mtk_iommu_v1.c regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); base 191 drivers/iommu/mtk_iommu_v1.c writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); base 232 drivers/iommu/mtk_iommu_v1.c writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); base 500 drivers/iommu/mtk_iommu_v1.c writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); base 510 drivers/iommu/mtk_iommu_v1.c writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); base 514 drivers/iommu/mtk_iommu_v1.c data->base + REG_MMU_IVRP_PADDR); base 516 drivers/iommu/mtk_iommu_v1.c writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); base 520 drivers/iommu/mtk_iommu_v1.c writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); base 577 drivers/iommu/mtk_iommu_v1.c data->base = devm_ioremap_resource(dev, res); base 578 drivers/iommu/mtk_iommu_v1.c if (IS_ERR(data->base)) base 579 drivers/iommu/mtk_iommu_v1.c return PTR_ERR(data->base); base 663 drivers/iommu/mtk_iommu_v1.c void __iomem *base = data->base; base 665 drivers/iommu/mtk_iommu_v1.c reg->standard_axi_mode = readl_relaxed(base + base 667 drivers/iommu/mtk_iommu_v1.c reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); base 668 drivers/iommu/mtk_iommu_v1.c reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); base 669 drivers/iommu/mtk_iommu_v1.c reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); base 677 drivers/iommu/mtk_iommu_v1.c void __iomem *base = data->base; base 679 drivers/iommu/mtk_iommu_v1.c writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); base 681 drivers/iommu/mtk_iommu_v1.c base + REG_MMU_STANDARD_AXI_MODE); base 682 drivers/iommu/mtk_iommu_v1.c writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); base 683 drivers/iommu/mtk_iommu_v1.c writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); base 684 drivers/iommu/mtk_iommu_v1.c writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); base 685 drivers/iommu/mtk_iommu_v1.c writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); base 268 drivers/iommu/omap-iommu.c l->base = MMU_LOCK_BASE(val); base 276 drivers/iommu/omap-iommu.c val = (l->base << MMU_LOCK_BASE_SHIFT); base 353 drivers/iommu/omap-iommu.c if (l.base == obj->nr_tlb_entries) { base 374 drivers/iommu/omap-iommu.c l.vict = l.base; base 388 drivers/iommu/omap-iommu.c l.base++; base 391 drivers/iommu/omap-iommu.c l.vict = l.base; base 460 drivers/iommu/omap-iommu.c l.base = 0; base 921 drivers/iommu/omap-iommu.c obj->num_cr_ctx = lock.base; base 940 drivers/iommu/omap-iommu.c l.base = 0; base 947 drivers/iommu/omap-iommu.c l.base = obj->num_cr_ctx; base 109 drivers/iommu/omap-iommu.h short base; base 56 drivers/iommu/qcom_iommu.c void __iomem *base; base 95 drivers/iommu/qcom_iommu.c writel_relaxed(val, ctx->base + reg); base 101 drivers/iommu/qcom_iommu.c writeq_relaxed(val, ctx->base + reg); base 107 drivers/iommu/qcom_iommu.c return readl_relaxed(ctx->base + reg); base 113 drivers/iommu/qcom_iommu.c return readq_relaxed(ctx->base + reg); base 127 drivers/iommu/qcom_iommu.c ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val, base 719 drivers/iommu/qcom_iommu.c ctx->base = devm_ioremap_resource(dev, res); base 720 drivers/iommu/qcom_iommu.c if (IS_ERR(ctx->base)) base 721 drivers/iommu/qcom_iommu.c return PTR_ERR(ctx->base); base 275 drivers/iommu/rockchip-iommu.c static u32 rk_iommu_read(void __iomem *base, u32 offset) base 277 drivers/iommu/rockchip-iommu.c return readl(base + offset); base 280 drivers/iommu/rockchip-iommu.c static void rk_iommu_write(void __iomem *base, u32 offset, u32 value) base 282 drivers/iommu/rockchip-iommu.c writel(value, base + offset); base 293 drivers/iommu/rockchip-iommu.c static void rk_iommu_base_command(void __iomem *base, u32 command) base 295 drivers/iommu/rockchip-iommu.c writel(command, base + RK_MMU_COMMAND); base 475 drivers/iommu/rockchip-iommu.c void __iomem *base = iommu->bases[index]; base 491 drivers/iommu/rockchip-iommu.c mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR); base 32 drivers/irqchip/exynos-combiner.c void __iomem *base; base 48 drivers/irqchip/exynos-combiner.c return combiner_data->base; base 75 drivers/irqchip/exynos-combiner.c status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS); base 127 drivers/irqchip/exynos-combiner.c void __iomem *base, unsigned int irq) base 129 drivers/irqchip/exynos-combiner.c combiner_data->base = base; base 135 drivers/irqchip/exynos-combiner.c writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR); base 218 drivers/irqchip/exynos-combiner.c readl_relaxed(combiner_data[i].base + COMBINER_ENABLE_SET); base 236 drivers/irqchip/exynos-combiner.c combiner_data[i].base + COMBINER_ENABLE_CLEAR); base 238 drivers/irqchip/exynos-combiner.c combiner_data[i].base + COMBINER_ENABLE_SET); base 38 drivers/irqchip/irq-al-fic.c void __iomem *base; base 50 drivers/irqchip/irq-al-fic.c u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); base 61 drivers/irqchip/irq-al-fic.c writel_relaxed(control, fic->base + AL_FIC_CONTROL); base 119 drivers/irqchip/irq-al-fic.c pending = readl_relaxed(fic->base + AL_FIC_CAUSE); base 135 drivers/irqchip/irq-al-fic.c writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE); base 166 drivers/irqchip/irq-al-fic.c gc->reg_base = fic->base; base 201 drivers/irqchip/irq-al-fic.c void __iomem *base, base 213 drivers/irqchip/irq-al-fic.c fic->base = base; base 218 drivers/irqchip/irq-al-fic.c writel_relaxed(0xFFFFFFFF, fic->base + AL_FIC_MASK); base 221 drivers/irqchip/irq-al-fic.c writel_relaxed(0, fic->base + AL_FIC_CAUSE); base 223 drivers/irqchip/irq-al-fic.c writel_relaxed(control, fic->base + AL_FIC_CONTROL); base 245 drivers/irqchip/irq-al-fic.c void __iomem *base; base 255 drivers/irqchip/irq-al-fic.c base = of_iomap(node, 0); base 256 drivers/irqchip/irq-al-fic.c if (!base) { base 269 drivers/irqchip/irq-al-fic.c base, base 285 drivers/irqchip/irq-al-fic.c iounmap(base); base 22 drivers/irqchip/irq-aspeed-i2c-ic.c void __iomem *base; base 40 drivers/irqchip/irq-aspeed-i2c-ic.c status = readl(i2c_ic->base); base 75 drivers/irqchip/irq-aspeed-i2c-ic.c i2c_ic->base = of_iomap(node, 0); base 76 drivers/irqchip/irq-aspeed-i2c-ic.c if (!i2c_ic->base) { base 105 drivers/irqchip/irq-aspeed-i2c-ic.c iounmap(i2c_ic->base); base 52 drivers/irqchip/irq-aspeed-vic.c void __iomem *base; base 63 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); base 64 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); base 67 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); base 68 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); base 71 drivers/irqchip/irq-aspeed-vic.c writel(0, vic->base + AVIC_INT_SELECT); base 72 drivers/irqchip/irq-aspeed-vic.c writel(0, vic->base + AVIC_INT_SELECT + 4); base 78 drivers/irqchip/irq-aspeed-vic.c sense = readl(vic->base + AVIC_INT_SENSE); base 80 drivers/irqchip/irq-aspeed-vic.c sense = readl(vic->base + AVIC_INT_SENSE + 4); base 84 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_EDGE_CLR); base 85 drivers/irqchip/irq-aspeed-vic.c writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4); base 95 drivers/irqchip/irq-aspeed-vic.c stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS); base 97 drivers/irqchip/irq-aspeed-vic.c stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4); base 115 drivers/irqchip/irq-aspeed-vic.c writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4); base 124 drivers/irqchip/irq-aspeed-vic.c writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4); base 133 drivers/irqchip/irq-aspeed-vic.c writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4); base 144 drivers/irqchip/irq-aspeed-vic.c writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4); base 148 drivers/irqchip/irq-aspeed-vic.c writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4); base 204 drivers/irqchip/irq-aspeed-vic.c vic->base = regs; base 36 drivers/irqchip/irq-ath79-misc.c void __iomem *base = domain->host_data; base 41 drivers/irqchip/irq-ath79-misc.c pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & base 42 drivers/irqchip/irq-ath79-misc.c __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); base 62 drivers/irqchip/irq-ath79-misc.c void __iomem *base = irq_data_get_irq_chip_data(d); base 66 drivers/irqchip/irq-ath79-misc.c t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); base 67 drivers/irqchip/irq-ath79-misc.c __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); base 70 drivers/irqchip/irq-ath79-misc.c __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); base 75 drivers/irqchip/irq-ath79-misc.c void __iomem *base = irq_data_get_irq_chip_data(d); base 79 drivers/irqchip/irq-ath79-misc.c t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); base 80 drivers/irqchip/irq-ath79-misc.c __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); base 83 drivers/irqchip/irq-ath79-misc.c __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); base 88 drivers/irqchip/irq-ath79-misc.c void __iomem *base = irq_data_get_irq_chip_data(d); base 92 drivers/irqchip/irq-ath79-misc.c t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); base 93 drivers/irqchip/irq-ath79-misc.c __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); base 96 drivers/irqchip/irq-ath79-misc.c __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); base 120 drivers/irqchip/irq-ath79-misc.c void __iomem *base = domain->host_data; base 125 drivers/irqchip/irq-ath79-misc.c __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); base 126 drivers/irqchip/irq-ath79-misc.c __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); base 135 drivers/irqchip/irq-ath79-misc.c void __iomem *base; base 144 drivers/irqchip/irq-ath79-misc.c base = of_iomap(node, 0); base 145 drivers/irqchip/irq-ath79-misc.c if (!base) { base 151 drivers/irqchip/irq-ath79-misc.c &misc_irq_domain_ops, base); base 79 drivers/irqchip/irq-bcm2835.c void __iomem *base; base 136 drivers/irqchip/irq-bcm2835.c void __iomem *base; base 139 drivers/irqchip/irq-bcm2835.c base = of_iomap(node, 0); base 140 drivers/irqchip/irq-bcm2835.c if (!base) base 149 drivers/irqchip/irq-bcm2835.c intc.pending[b] = base + reg_pending[b]; base 150 drivers/irqchip/irq-bcm2835.c intc.enable[b] = base + reg_enable[b]; base 151 drivers/irqchip/irq-bcm2835.c intc.disable[b] = base + reg_disable[b]; base 19 drivers/irqchip/irq-bcm2836.c void __iomem *base; base 28 drivers/irqchip/irq-bcm2836.c void __iomem *reg = intc.base + reg_offset + 4 * cpu; base 37 drivers/irqchip/irq-bcm2836.c void __iomem *reg = intc.base + reg_offset + 4 * cpu; base 64 drivers/irqchip/irq-bcm2836.c writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR); base 69 drivers/irqchip/irq-bcm2836.c writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET); base 129 drivers/irqchip/irq-bcm2836.c stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu); base 132 drivers/irqchip/irq-bcm2836.c void __iomem *mailbox0 = (intc.base + base 152 drivers/irqchip/irq-bcm2836.c void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0; base 210 drivers/irqchip/irq-bcm2836.c writel(0, intc.base + LOCAL_CONTROL); base 216 drivers/irqchip/irq-bcm2836.c writel(0x80000000, intc.base + LOCAL_PRESCALER); base 222 drivers/irqchip/irq-bcm2836.c intc.base = of_iomap(node, 0); base 223 drivers/irqchip/irq-bcm2836.c if (!intc.base) { base 132 drivers/irqchip/irq-bcm6345-l1.c int base = idx * IRQS_PER_WORD; base 141 drivers/irqchip/irq-bcm6345-l1.c irq = irq_linear_revmap(intc->domain, base + hwirq); base 130 drivers/irqchip/irq-bcm7038-l1.c int base = idx * IRQS_PER_WORD; base 141 drivers/irqchip/irq-bcm7038-l1.c base + hwirq)); base 65 drivers/irqchip/irq-bcm7120-l2.c int base = idx * IRQS_PER_WORD; base 67 drivers/irqchip/irq-bcm7120-l2.c irq_get_domain_generic_chip(b->domain, base); base 79 drivers/irqchip/irq-bcm7120-l2.c base + hwirq)); base 192 drivers/irqchip/irq-bcm7120-l2.c void __iomem *base = min(en, stat); base 197 drivers/irqchip/irq-bcm7120-l2.c if (!base) base 200 drivers/irqchip/irq-bcm7120-l2.c data->pair_base[gc_idx] = base; base 201 drivers/irqchip/irq-bcm7120-l2.c data->en_offset[gc_idx] = en - base; base 202 drivers/irqchip/irq-bcm7120-l2.c data->stat_offset[gc_idx] = stat - base; base 169 drivers/irqchip/irq-brcmstb-l2.c void __iomem *base; base 175 drivers/irqchip/irq-brcmstb-l2.c base = of_iomap(np, 0); base 176 drivers/irqchip/irq-brcmstb-l2.c if (!base) { base 183 drivers/irqchip/irq-brcmstb-l2.c writel(0xffffffff, base + init_params->cpu_mask_set); base 188 drivers/irqchip/irq-brcmstb-l2.c writel(0xffffffff, base + init_params->cpu_clear); base 224 drivers/irqchip/irq-brcmstb-l2.c data->gc->reg_base = base; base 266 drivers/irqchip/irq-brcmstb-l2.c iounmap(base); base 65 drivers/irqchip/irq-clps711x.c void __iomem *base; base 95 drivers/irqchip/irq-clps711x.c writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hwirq].eoi); base 145 drivers/irqchip/irq-clps711x.c writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hw].eoi); base 154 drivers/irqchip/irq-clps711x.c phys_addr_t base, resource_size_t size) base 162 drivers/irqchip/irq-clps711x.c clps711x_intc->base = ioremap(base, size); base 163 drivers/irqchip/irq-clps711x.c if (!clps711x_intc->base) { base 168 drivers/irqchip/irq-clps711x.c clps711x_intc->intsr[0] = clps711x_intc->base + CLPS711X_INTSR1; base 169 drivers/irqchip/irq-clps711x.c clps711x_intc->intmr[0] = clps711x_intc->base + CLPS711X_INTMR1; base 170 drivers/irqchip/irq-clps711x.c clps711x_intc->intsr[1] = clps711x_intc->base + CLPS711X_INTSR2; base 171 drivers/irqchip/irq-clps711x.c clps711x_intc->intmr[1] = clps711x_intc->base + CLPS711X_INTMR2; base 172 drivers/irqchip/irq-clps711x.c clps711x_intc->intsr[2] = clps711x_intc->base + CLPS711X_INTSR3; base 173 drivers/irqchip/irq-clps711x.c clps711x_intc->intmr[2] = clps711x_intc->base + CLPS711X_INTMR3; base 207 drivers/irqchip/irq-clps711x.c iounmap(clps711x_intc->base); base 215 drivers/irqchip/irq-clps711x.c void __init clps711x_intc_init(phys_addr_t base, resource_size_t size) base 217 drivers/irqchip/irq-clps711x.c BUG_ON(_clps711x_intc_init(NULL, base, size)); base 43 drivers/irqchip/irq-davinci-aintc.c davinci_aintc_setup_gc(void __iomem *base, base 50 drivers/irqchip/irq-davinci-aintc.c gc->reg_base = base; base 49 drivers/irqchip/irq-ftintc010.c void __iomem *base; base 59 drivers/irqchip/irq-ftintc010.c mask = readl(FT010_IRQ_MASK(f->base)); base 61 drivers/irqchip/irq-ftintc010.c writel(mask, FT010_IRQ_MASK(f->base)); base 69 drivers/irqchip/irq-ftintc010.c mask = readl(FT010_IRQ_MASK(f->base)); base 71 drivers/irqchip/irq-ftintc010.c writel(mask, FT010_IRQ_MASK(f->base)); base 78 drivers/irqchip/irq-ftintc010.c writel(BIT(irqd_to_hwirq(d)), FT010_IRQ_CLEAR(f->base)); base 87 drivers/irqchip/irq-ftintc010.c mode = readl(FT010_IRQ_MODE(f->base)); base 88 drivers/irqchip/irq-ftintc010.c polarity = readl(FT010_IRQ_POLARITY(f->base)); base 112 drivers/irqchip/irq-ftintc010.c writel(mode, FT010_IRQ_MODE(f->base)); base 113 drivers/irqchip/irq-ftintc010.c writel(polarity, FT010_IRQ_POLARITY(f->base)); base 135 drivers/irqchip/irq-ftintc010.c while ((status = readl(FT010_IRQ_STATUS(f->base)))) { base 177 drivers/irqchip/irq-ftintc010.c f->base = of_iomap(node, 0); base 178 drivers/irqchip/irq-ftintc010.c WARN(!f->base, "unable to map gemini irq registers\n"); base 181 drivers/irqchip/irq-ftintc010.c writel(0, FT010_IRQ_MASK(f->base)); base 182 drivers/irqchip/irq-ftintc010.c writel(0, FT010_FIQ_MASK(f->base)); base 55 drivers/irqchip/irq-gic-common.c void __iomem *base, void (*sync_access)(void)) base 68 drivers/irqchip/irq-gic-common.c val = oldval = readl_relaxed(base + confoff); base 88 drivers/irqchip/irq-gic-common.c writel_relaxed(val, base + confoff); base 89 drivers/irqchip/irq-gic-common.c if (readl_relaxed(base + confoff) != val) base 100 drivers/irqchip/irq-gic-common.c void gic_dist_config(void __iomem *base, int gic_irqs, base 110 drivers/irqchip/irq-gic-common.c base + GIC_DIST_CONFIG + i / 4); base 116 drivers/irqchip/irq-gic-common.c writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); base 124 drivers/irqchip/irq-gic-common.c base + GIC_DIST_ACTIVE_CLEAR + i / 8); base 126 drivers/irqchip/irq-gic-common.c base + GIC_DIST_ENABLE_CLEAR + i / 8); base 133 drivers/irqchip/irq-gic-common.c void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void)) base 143 drivers/irqchip/irq-gic-common.c base + GIC_DIST_ACTIVE_CLEAR + i / 8); base 145 drivers/irqchip/irq-gic-common.c base + GIC_DIST_ENABLE_CLEAR + i / 8); base 153 drivers/irqchip/irq-gic-common.c base + GIC_DIST_PRI + i * 4 / 4); base 156 drivers/irqchip/irq-gic-common.c writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); base 22 drivers/irqchip/irq-gic-common.h void __iomem *base, void (*sync_access)(void)); base 23 drivers/irqchip/irq-gic-common.h void gic_dist_config(void __iomem *base, int gic_irqs, base 25 drivers/irqchip/irq-gic-common.h void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void)); base 65 drivers/irqchip/irq-gic-v2m.c void __iomem *base; /* GICv2m virt address */ base 236 drivers/irqchip/irq-gic-v2m.c static bool is_msi_spi_valid(u32 base, u32 num) base 238 drivers/irqchip/irq-gic-v2m.c if (base < V2M_MIN_SPI) { base 239 drivers/irqchip/irq-gic-v2m.c pr_err("Invalid MSI base SPI (base:%u)\n", base); base 243 drivers/irqchip/irq-gic-v2m.c if ((num == 0) || (base + num > V2M_MAX_SPI)) { base 272 drivers/irqchip/irq-gic-v2m.c iounmap(v2m->base); base 336 drivers/irqchip/irq-gic-v2m.c v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res)); base 337 drivers/irqchip/irq-gic-v2m.c if (!v2m->base) { base 354 drivers/irqchip/irq-gic-v2m.c typer = readl_relaxed(v2m->base + V2M_MSI_TYPER); base 379 drivers/irqchip/irq-gic-v2m.c switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) { base 404 drivers/irqchip/irq-gic-v2m.c iounmap(v2m->base); base 76 drivers/irqchip/irq-gic-v3-its.c void *base; base 97 drivers/irqchip/irq-gic-v3-its.c void __iomem *base; base 691 drivers/irqchip/irq-gic-v3-its.c ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); base 734 drivers/irqchip/irq-gic-v3-its.c writel_relaxed(wr, its->base + GITS_CWRITER); base 768 drivers/irqchip/irq-gic-v3-its.c rd_idx = readl_relaxed(its->base + GITS_CREADR); base 827 drivers/irqchip/irq-gic-v3-its.c rd_idx = readl_relaxed(its->base + GITS_CREADR); \ base 1480 drivers/irqchip/irq-gic-v3-its.c static struct lpi_range *mk_lpi_range(u32 base, u32 span) base 1486 drivers/irqchip/irq-gic-v3-its.c range->base_id = base; base 1493 drivers/irqchip/irq-gic-v3-its.c static int alloc_lpi_range(u32 nr_lpis, u32 *base) base 1502 drivers/irqchip/irq-gic-v3-its.c *base = range->base_id; base 1518 drivers/irqchip/irq-gic-v3-its.c pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis); base 1534 drivers/irqchip/irq-gic-v3-its.c static int free_lpi_range(u32 base, u32 nr_lpis) base 1538 drivers/irqchip/irq-gic-v3-its.c new = mk_lpi_range(base, nr_lpis); base 1545 drivers/irqchip/irq-gic-v3-its.c if (old->base_id < base) base 1590 drivers/irqchip/irq-gic-v3-its.c static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids) base 1596 drivers/irqchip/irq-gic-v3-its.c err = alloc_lpi_range(nr_irqs, base); base 1617 drivers/irqchip/irq-gic-v3-its.c *base = *nr_ids = 0; base 1622 drivers/irqchip/irq-gic-v3-its.c static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids) base 1624 drivers/irqchip/irq-gic-v3-its.c WARN_ON(free_lpi_range(base, nr_ids)); base 1742 drivers/irqchip/irq-gic-v3-its.c return gits_read_baser(its->base + GITS_BASER + (idx << 3)); base 1750 drivers/irqchip/irq-gic-v3-its.c gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); base 1764 drivers/irqchip/irq-gic-v3-its.c void *base; base 1780 drivers/irqchip/irq-gic-v3-its.c base = (void *)page_address(page); base 1781 drivers/irqchip/irq-gic-v3-its.c baser_phys = virt_to_phys(base); base 1789 drivers/irqchip/irq-gic-v3-its.c free_pages((unsigned long)base, order); base 1834 drivers/irqchip/irq-gic-v3-its.c gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); base 1845 drivers/irqchip/irq-gic-v3-its.c free_pages((unsigned long)base, order); base 1846 drivers/irqchip/irq-gic-v3-its.c baser->base = NULL; base 1862 drivers/irqchip/irq-gic-v3-its.c free_pages((unsigned long)base, order); base 1867 drivers/irqchip/irq-gic-v3-its.c baser->base = base; base 1874 drivers/irqchip/irq-gic-v3-its.c (unsigned long)virt_to_phys(base), base 1940 drivers/irqchip/irq-gic-v3-its.c if (its->tables[i].base) { base 1941 drivers/irqchip/irq-gic-v3-its.c free_pages((unsigned long)its->tables[i].base, base 1943 drivers/irqchip/irq-gic-v3-its.c its->tables[i].base = NULL; base 2250 drivers/irqchip/irq-gic-v3-its.c if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { base 2330 drivers/irqchip/irq-gic-v3-its.c table = baser->base; base 3084 drivers/irqchip/irq-gic-v3-its.c int base, nr_ids, i, err = 0; base 3088 drivers/irqchip/irq-gic-v3-its.c bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids); base 3093 drivers/irqchip/irq-gic-v3-its.c its_lpi_free(bitmap, base, nr_ids); base 3099 drivers/irqchip/irq-gic-v3-its.c its_lpi_free(bitmap, base, nr_ids); base 3104 drivers/irqchip/irq-gic-v3-its.c vm->db_lpi_base = base; base 3109 drivers/irqchip/irq-gic-v3-its.c vm->vpes[i]->vpe_db_lpi = base + i; base 3126 drivers/irqchip/irq-gic-v3-its.c its_lpi_free(bitmap, base, nr_ids); base 3187 drivers/irqchip/irq-gic-v3-its.c static int its_force_quiescent(void __iomem *base) base 3192 drivers/irqchip/irq-gic-v3-its.c val = readl_relaxed(base + GITS_CTLR); base 3203 drivers/irqchip/irq-gic-v3-its.c writel_relaxed(val, base + GITS_CTLR); base 3207 drivers/irqchip/irq-gic-v3-its.c val = readl_relaxed(base + GITS_CTLR); base 3353 drivers/irqchip/irq-gic-v3-its.c u32 iidr = readl_relaxed(its->base + GITS_IIDR); base 3365 drivers/irqchip/irq-gic-v3-its.c void __iomem *base; base 3370 drivers/irqchip/irq-gic-v3-its.c base = its->base; base 3371 drivers/irqchip/irq-gic-v3-its.c its->ctlr_save = readl_relaxed(base + GITS_CTLR); base 3372 drivers/irqchip/irq-gic-v3-its.c err = its_force_quiescent(base); base 3376 drivers/irqchip/irq-gic-v3-its.c writel_relaxed(its->ctlr_save, base + GITS_CTLR); base 3380 drivers/irqchip/irq-gic-v3-its.c its->cbaser_save = gits_read_cbaser(base + GITS_CBASER); base 3386 drivers/irqchip/irq-gic-v3-its.c void __iomem *base; base 3391 drivers/irqchip/irq-gic-v3-its.c base = its->base; base 3392 drivers/irqchip/irq-gic-v3-its.c writel_relaxed(its->ctlr_save, base + GITS_CTLR); base 3407 drivers/irqchip/irq-gic-v3-its.c void __iomem *base; base 3413 drivers/irqchip/irq-gic-v3-its.c base = its->base; base 3421 drivers/irqchip/irq-gic-v3-its.c ret = its_force_quiescent(base); base 3428 drivers/irqchip/irq-gic-v3-its.c gits_write_cbaser(its->cbaser_save, base + GITS_CBASER); base 3435 drivers/irqchip/irq-gic-v3-its.c gits_write_cwriter(0, base + GITS_CWRITER); base 3446 drivers/irqchip/irq-gic-v3-its.c writel_relaxed(its->ctlr_save, base + GITS_CTLR); base 3454 drivers/irqchip/irq-gic-v3-its.c GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER))) base 3611 drivers/irqchip/irq-gic-v3-its.c its->base = its_base; base 3661 drivers/irqchip/irq-gic-v3-its.c gits_write_cbaser(baser, its->base + GITS_CBASER); base 3662 drivers/irqchip/irq-gic-v3-its.c tmp = gits_read_cbaser(its->base + GITS_CBASER); base 3674 drivers/irqchip/irq-gic-v3-its.c gits_write_cbaser(baser, its->base + GITS_CBASER); base 3680 drivers/irqchip/irq-gic-v3-its.c gits_write_cwriter(0, its->base + GITS_CWRITER); base 3681 drivers/irqchip/irq-gic-v3-its.c ctlr = readl_relaxed(its->base + GITS_CTLR); base 3685 drivers/irqchip/irq-gic-v3-its.c writel_relaxed(ctlr, its->base + GITS_CTLR); base 165 drivers/irqchip/irq-gic-v3.c static void gic_do_wait_for_rwp(void __iomem *base) base 169 drivers/irqchip/irq-gic-v3.c while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { base 294 drivers/irqchip/irq-gic-v3.c void __iomem *base; base 301 drivers/irqchip/irq-gic-v3.c base = gic_data_rdist_sgi_base(); base 303 drivers/irqchip/irq-gic-v3.c base = gic_data.dist_base; base 305 drivers/irqchip/irq-gic-v3.c return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask); base 311 drivers/irqchip/irq-gic-v3.c void __iomem *base; base 318 drivers/irqchip/irq-gic-v3.c base = gic_data_rdist_sgi_base(); base 321 drivers/irqchip/irq-gic-v3.c base = gic_data.dist_base; base 325 drivers/irqchip/irq-gic-v3.c writel_relaxed(mask, base + offset + (index / 32) * 4); base 417 drivers/irqchip/irq-gic-v3.c void __iomem *base = gic_dist_base(d); base 422 drivers/irqchip/irq-gic-v3.c writeb_relaxed(prio, base + offset + index); base 528 drivers/irqchip/irq-gic-v3.c void __iomem *base; base 544 drivers/irqchip/irq-gic-v3.c base = gic_data_rdist_sgi_base(); base 547 drivers/irqchip/irq-gic-v3.c base = gic_data.dist_base; base 553 drivers/irqchip/irq-gic-v3.c ret = gic_configure_irq(index, type, base + offset, rwp_wait); base 716 drivers/irqchip/irq-gic-v3.c void __iomem *base = gic_data.dist_base; base 719 drivers/irqchip/irq-gic-v3.c writel_relaxed(0, base + GICD_CTLR); base 729 drivers/irqchip/irq-gic-v3.c writel_relaxed(~0, base + GICD_IGROUPR + i / 8); base 733 drivers/irqchip/irq-gic-v3.c writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8); base 734 drivers/irqchip/irq-gic-v3.c writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8); base 738 drivers/irqchip/irq-gic-v3.c writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8); base 741 drivers/irqchip/irq-gic-v3.c writel_relaxed(0, base + GICD_ICFGRnE + i / 4); base 744 drivers/irqchip/irq-gic-v3.c writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); base 747 drivers/irqchip/irq-gic-v3.c gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp); base 751 drivers/irqchip/irq-gic-v3.c base + GICD_CTLR); base 759 drivers/irqchip/irq-gic-v3.c gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); base 762 drivers/irqchip/irq-gic-v3.c gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8); base 128 drivers/irqchip/irq-gic.c static void __iomem *gic_get_percpu_base(union gic_base *base) base 130 drivers/irqchip/irq-gic.c return raw_cpu_read(*base->percpu_base); base 133 drivers/irqchip/irq-gic.c static void __iomem *gic_get_common_base(union gic_base *base) base 135 drivers/irqchip/irq-gic.c return base->common_base; base 292 drivers/irqchip/irq-gic.c void __iomem *base = gic_dist_base(d); base 305 drivers/irqchip/irq-gic.c ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL); base 444 drivers/irqchip/irq-gic.c void __iomem *base = gic_data_dist_base(gic); base 448 drivers/irqchip/irq-gic.c mask = readl_relaxed(base + GIC_DIST_TARGET + i); base 461 drivers/irqchip/irq-gic.c static bool gic_check_gicv2(void __iomem *base) base 463 drivers/irqchip/irq-gic.c u32 val = readl_relaxed(base + GIC_CPU_IDENT); base 496 drivers/irqchip/irq-gic.c void __iomem *base = gic_data_dist_base(gic); base 498 drivers/irqchip/irq-gic.c writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); base 507 drivers/irqchip/irq-gic.c writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); base 509 drivers/irqchip/irq-gic.c gic_dist_config(base, gic_irqs, NULL); base 511 drivers/irqchip/irq-gic.c writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); base 517 drivers/irqchip/irq-gic.c void __iomem *base = gic_data_cpu_base(gic); base 548 drivers/irqchip/irq-gic.c writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); base 1275 drivers/irqchip/irq-gic.c static bool gic_check_eoimode(struct device_node *node, void __iomem **base) base 1289 drivers/irqchip/irq-gic.c if (!gic_check_gicv2(*base)) base 1308 drivers/irqchip/irq-gic.c iounmap(*base); base 1309 drivers/irqchip/irq-gic.c *base = alt; base 1326 drivers/irqchip/irq-gic.c iounmap(*base); base 1327 drivers/irqchip/irq-gic.c *base = alt; base 1335 drivers/irqchip/irq-gic.c if (!gic_check_gicv2(*base) || base 1336 drivers/irqchip/irq-gic.c !gic_check_gicv2(*base + 0xf000)) base 1344 drivers/irqchip/irq-gic.c *base += 0xf000; base 29 drivers/irqchip/irq-goldfish-pic.c void __iomem *base; base 41 drivers/irqchip/irq-goldfish-pic.c pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING); base 78 drivers/irqchip/irq-goldfish-pic.c gfpic->base = of_iomap(of_node, 0); base 79 drivers/irqchip/irq-goldfish-pic.c if (!gfpic->base) { base 86 drivers/irqchip/irq-goldfish-pic.c writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL); base 88 drivers/irqchip/irq-goldfish-pic.c gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base, base 125 drivers/irqchip/irq-goldfish-pic.c iounmap(gfpic->base); base 118 drivers/irqchip/irq-hip04.c void __iomem *base = hip04_dist_base(d); base 133 drivers/irqchip/irq-hip04.c ret = gic_configure_irq(irq, type, base + GIC_DIST_CONFIG, NULL); base 216 drivers/irqchip/irq-hip04.c void __iomem *base = intc->dist_base; base 220 drivers/irqchip/irq-hip04.c mask = readl_relaxed(base + GIC_DIST_TARGET + i * 2); base 237 drivers/irqchip/irq-hip04.c void __iomem *base = intc->dist_base; base 239 drivers/irqchip/irq-hip04.c writel_relaxed(0, base + GIC_DIST_CTRL); base 247 drivers/irqchip/irq-hip04.c writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3)); base 249 drivers/irqchip/irq-hip04.c gic_dist_config(base, nr_irqs, NULL); base 251 drivers/irqchip/irq-hip04.c writel_relaxed(1, base + GIC_DIST_CTRL); base 257 drivers/irqchip/irq-hip04.c void __iomem *base = intc->cpu_base; base 278 drivers/irqchip/irq-hip04.c writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); base 279 drivers/irqchip/irq-hip04.c writel_relaxed(1, base + GIC_CPU_CTRL); base 24 drivers/irqchip/irq-ingenic.c void __iomem *base; base 42 drivers/irqchip/irq-ingenic.c irq_reg = readl(intc->base + (i * CHIP_SIZE) + base 105 drivers/irqchip/irq-ingenic.c intc->base = of_iomap(node, 0); base 106 drivers/irqchip/irq-ingenic.c if (!intc->base) { base 121 drivers/irqchip/irq-ingenic.c writel(0xffffffff, intc->base + (i * CHIP_SIZE) + base 126 drivers/irqchip/irq-ingenic.c intc->base + (i * CHIP_SIZE), base 149 drivers/irqchip/irq-ingenic.c iounmap(intc->base); base 310 drivers/irqchip/irq-ixp4xx.c void __iomem *base; base 317 drivers/irqchip/irq-ixp4xx.c base = ioremap(irqbase, 0x100); base 318 drivers/irqchip/irq-ixp4xx.c if (!base) { base 327 drivers/irqchip/irq-ixp4xx.c ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356); base 372 drivers/irqchip/irq-ixp4xx.c void __iomem *base; base 377 drivers/irqchip/irq-ixp4xx.c base = of_iomap(np, 0); base 378 drivers/irqchip/irq-ixp4xx.c if (!base) { base 389 drivers/irqchip/irq-ixp4xx.c ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356); base 79 drivers/irqchip/irq-jcore-aic.c void __iomem *base = of_iomap(node, cpu); base 81 drivers/irqchip/irq-jcore-aic.c if (!base) { base 85 drivers/irqchip/irq-jcore-aic.c __raw_writel(0xffffffff, base + JCORE_AIC1_INTPRI_REG); base 86 drivers/irqchip/irq-jcore-aic.c iounmap(base); base 27 drivers/irqchip/irq-lpc32xx.c void __iomem *base; base 36 drivers/irqchip/irq-lpc32xx.c return readl_relaxed(ic->base + reg); base 42 drivers/irqchip/irq-lpc32xx.c writel_relaxed(val, ic->base + reg); base 186 drivers/irqchip/irq-lpc32xx.c irqc->base = of_iomap(node, 0); base 187 drivers/irqchip/irq-lpc32xx.c if (!irqc->base) { base 206 drivers/irqchip/irq-lpc32xx.c iounmap(irqc->base); base 64 drivers/irqchip/irq-mbigen.c void __iomem *base; base 106 drivers/irqchip/irq-mbigen.c void __iomem *base = data->chip_data; base 111 drivers/irqchip/irq-mbigen.c writel_relaxed(mask, base + addr); base 118 drivers/irqchip/irq-mbigen.c void __iomem *base = data->chip_data; base 126 drivers/irqchip/irq-mbigen.c val = readl_relaxed(base + addr); base 133 drivers/irqchip/irq-mbigen.c writel_relaxed(val, base + addr); base 150 drivers/irqchip/irq-mbigen.c void __iomem *base = d->chip_data; base 156 drivers/irqchip/irq-mbigen.c base += get_mbigen_vec_reg(d->hwirq); base 157 drivers/irqchip/irq-mbigen.c val = readl_relaxed(base); base 165 drivers/irqchip/irq-mbigen.c writel_relaxed(val, base); base 218 drivers/irqchip/irq-mbigen.c &mbigen_irq_chip, mgn_chip->base); base 343 drivers/irqchip/irq-mbigen.c mgn_chip->base = devm_ioremap(&pdev->dev, res->start, base 345 drivers/irqchip/irq-mbigen.c if (!mgn_chip->base) { base 86 drivers/irqchip/irq-meson-gpio.c void __iomem *base; base 97 drivers/irqchip/irq-meson-gpio.c tmp = readl_relaxed(ctl->base + reg); base 100 drivers/irqchip/irq-meson-gpio.c writel_relaxed(tmp, ctl->base + reg); base 401 drivers/irqchip/irq-meson-gpio.c ctl->base = of_iomap(node, 0); base 402 drivers/irqchip/irq-meson-gpio.c if (!ctl->base) { base 428 drivers/irqchip/irq-meson-gpio.c iounmap(ctl->base); base 32 drivers/irqchip/irq-mtk-cirq.c void __iomem *base; base 46 drivers/irqchip/irq-mtk-cirq.c writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4); base 204 drivers/irqchip/irq-mtk-cirq.c writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4); base 209 drivers/irqchip/irq-mtk-cirq.c value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); base 211 drivers/irqchip/irq-mtk-cirq.c writel_relaxed(value, cirq_data->base + CIRQ_CONTROL); base 221 drivers/irqchip/irq-mtk-cirq.c value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); base 222 drivers/irqchip/irq-mtk-cirq.c writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL); base 225 drivers/irqchip/irq-mtk-cirq.c value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); base 227 drivers/irqchip/irq-mtk-cirq.c writel_relaxed(value, cirq_data->base + CIRQ_CONTROL); base 260 drivers/irqchip/irq-mtk-cirq.c cirq_data->base = of_iomap(node, 0); base 261 drivers/irqchip/irq-mtk-cirq.c if (!cirq_data->base) { base 292 drivers/irqchip/irq-mtk-cirq.c iounmap(cirq_data->base); base 31 drivers/irqchip/irq-mtk-sysirq.c void __iomem *base; base 36 drivers/irqchip/irq-mtk-sysirq.c base = chip_data->intpol_bases[intpol_idx]; base 41 drivers/irqchip/irq-mtk-sysirq.c value = readl_relaxed(base + reg_index * 4); base 52 drivers/irqchip/irq-mtk-sysirq.c writel_relaxed(value, base + reg_index * 4); base 53 drivers/irqchip/irq-mvebu-icu.c void __iomem *base; base 81 drivers/irqchip/irq-mvebu-icu.c writel_relaxed(msg[0].address_hi, icu->base + subset->offset_set_ah); base 82 drivers/irqchip/irq-mvebu-icu.c writel_relaxed(msg[0].address_lo, icu->base + subset->offset_set_al); base 88 drivers/irqchip/irq-mvebu-icu.c writel_relaxed(msg[1].address_hi, icu->base + subset->offset_clr_ah); base 89 drivers/irqchip/irq-mvebu-icu.c writel_relaxed(msg[1].address_lo, icu->base + subset->offset_clr_al); base 113 drivers/irqchip/irq-mvebu-icu.c writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq)); base 126 drivers/irqchip/irq-mvebu-icu.c icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID)); base 128 drivers/irqchip/irq-mvebu-icu.c icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID)); base 361 drivers/irqchip/irq-mvebu-icu.c icu->base = devm_ioremap_resource(&pdev->dev, res); base 362 drivers/irqchip/irq-mvebu-icu.c if (IS_ERR(icu->base)) { base 364 drivers/irqchip/irq-mvebu-icu.c return PTR_ERR(icu->base); base 384 drivers/irqchip/irq-mvebu-icu.c icu_int = readl_relaxed(icu->base + ICU_INT_CFG(i)); base 390 drivers/irqchip/irq-mvebu-icu.c writel_relaxed(0x0, icu->base + ICU_INT_CFG(i)); base 39 drivers/irqchip/irq-mvebu-odmi.c void __iomem *base; base 188 drivers/irqchip/irq-mvebu-odmi.c odmi->base = of_io_request_and_map(node, i, "odmi"); base 189 drivers/irqchip/irq-mvebu-odmi.c if (IS_ERR(odmi->base)) { base 190 drivers/irqchip/irq-mvebu-odmi.c ret = PTR_ERR(odmi->base); base 227 drivers/irqchip/irq-mvebu-odmi.c if (odmi->base && !IS_ERR(odmi->base)) base 228 drivers/irqchip/irq-mvebu-odmi.c iounmap(odmis[i].base); base 29 drivers/irqchip/irq-mvebu-pic.c void __iomem *base; base 38 drivers/irqchip/irq-mvebu-pic.c writel(0, pic->base + PIC_MASK); base 39 drivers/irqchip/irq-mvebu-pic.c writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE); base 46 drivers/irqchip/irq-mvebu-pic.c writel(1 << d->hwirq, pic->base + PIC_CAUSE); base 54 drivers/irqchip/irq-mvebu-pic.c reg = readl(pic->base + PIC_MASK); base 56 drivers/irqchip/irq-mvebu-pic.c writel(reg, pic->base + PIC_MASK); base 64 drivers/irqchip/irq-mvebu-pic.c reg = readl(pic->base + PIC_MASK); base 66 drivers/irqchip/irq-mvebu-pic.c writel(reg, pic->base + PIC_MASK); base 96 drivers/irqchip/irq-mvebu-pic.c irqmap = readl_relaxed(pic->base + PIC_CAUSE); base 134 drivers/irqchip/irq-mvebu-pic.c pic->base = devm_ioremap_resource(&pdev->dev, res); base 135 drivers/irqchip/irq-mvebu-pic.c if (IS_ERR(pic->base)) base 136 drivers/irqchip/irq-mvebu-pic.c return PTR_ERR(pic->base); base 41 drivers/irqchip/irq-mvebu-sei.c void __iomem *base; base 62 drivers/irqchip/irq-mvebu-sei.c sei->base + GICP_SECR(reg_idx)); base 73 drivers/irqchip/irq-mvebu-sei.c reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); base 75 drivers/irqchip/irq-mvebu-sei.c writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); base 87 drivers/irqchip/irq-mvebu-sei.c reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); base 89 drivers/irqchip/irq-mvebu-sei.c writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); base 337 drivers/irqchip/irq-mvebu-sei.c irqmap = readl_relaxed(sei->base + GICP_SECR(idx)); base 363 drivers/irqchip/irq-mvebu-sei.c writel_relaxed(0xFFFFFFFF, sei->base + GICP_SECR(reg_idx)); base 364 drivers/irqchip/irq-mvebu-sei.c writel_relaxed(0xFFFFFFFF, sei->base + GICP_SEMR(reg_idx)); base 386 drivers/irqchip/irq-mvebu-sei.c sei->base = devm_ioremap_resource(sei->dev, sei->res); base 387 drivers/irqchip/irq-mvebu-sei.c if (IS_ERR(sei->base)) { base 389 drivers/irqchip/irq-mvebu-sei.c return PTR_ERR(sei->base); base 187 drivers/irqchip/irq-omap-intc.c static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base) base 205 drivers/irqchip/irq-omap-intc.c gc->reg_base = base; base 223 drivers/irqchip/irq-omap-intc.c static void __init omap_alloc_gc_legacy(void __iomem *base, base 229 drivers/irqchip/irq-omap-intc.c gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, base 263 drivers/irqchip/irq-omap-intc.c static int __init omap_init_irq_legacy(u32 base, struct device_node *node) base 267 drivers/irqchip/irq-omap-intc.c omap_irq_base = ioremap(base, SZ_4K); base 297 drivers/irqchip/irq-omap-intc.c static int __init omap_init_irq(u32 base, struct device_node *node) base 314 drivers/irqchip/irq-omap-intc.c base = res.start; base 315 drivers/irqchip/irq-omap-intc.c ret = omap_init_irq_legacy(base, node); base 319 drivers/irqchip/irq-omap-intc.c ret = omap_init_irq_legacy(base, NULL); base 87 drivers/irqchip/irq-ompic.c static inline u32 ompic_readreg(void __iomem *base, loff_t offset) base 89 drivers/irqchip/irq-ompic.c return ioread32be(base + offset); base 92 drivers/irqchip/irq-ompic.c static void ompic_writereg(void __iomem *base, loff_t offset, u32 data) base 94 drivers/irqchip/irq-ompic.c iowrite32be(data, base + offset); base 36 drivers/irqchip/irq-orion.c int n, base = 0; base 38 drivers/irqchip/irq-orion.c for (n = 0; n < dgc->num_chips; n++, base += ORION_IRQS_PER_CHIP) { base 40 drivers/irqchip/irq-orion.c irq_get_domain_generic_chip(orion_irq_domain, base); base 56 drivers/irqchip/irq-orion.c int n, ret, base, num_chips = 0; base 76 drivers/irqchip/irq-orion.c for (n = 0, base = 0; n < num_chips; n++, base += ORION_IRQS_PER_CHIP) { base 78 drivers/irqchip/irq-orion.c irq_get_domain_generic_chip(orion_irq_domain, base); base 43 drivers/irqchip/irq-renesas-rza1.c void __iomem *base; base 60 drivers/irqchip/irq-renesas-rza1.c tmp = readw_relaxed(priv->base + IRQRR); base 63 drivers/irqchip/irq-renesas-rza1.c priv->base + IRQRR); base 95 drivers/irqchip/irq-renesas-rza1.c tmp = readw_relaxed(priv->base + ICR1); base 98 drivers/irqchip/irq-renesas-rza1.c writew_relaxed(tmp, priv->base + ICR1); base 206 drivers/irqchip/irq-renesas-rza1.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 207 drivers/irqchip/irq-renesas-rza1.c if (IS_ERR(priv->base)) base 208 drivers/irqchip/irq-renesas-rza1.c return PTR_ERR(priv->base); base 522 drivers/irqchip/irq-s3c24xx.c void __iomem *base = (void *)0xf6000000; /* static mapping */ base 543 drivers/irqchip/irq-s3c24xx.c intc->reg_pending = base; base 544 drivers/irqchip/irq-s3c24xx.c intc->reg_mask = base + 0x08; base 545 drivers/irqchip/irq-s3c24xx.c intc->reg_intpnd = base + 0x10; base 551 drivers/irqchip/irq-s3c24xx.c intc->reg_pending = base + 0x18; base 552 drivers/irqchip/irq-s3c24xx.c intc->reg_mask = base + 0x1c; base 558 drivers/irqchip/irq-s3c24xx.c intc->reg_pending = base + 0x40; base 559 drivers/irqchip/irq-s3c24xx.c intc->reg_mask = base + 0x48; base 560 drivers/irqchip/irq-s3c24xx.c intc->reg_intpnd = base + 0x50; base 566 drivers/irqchip/irq-s3c24xx.c base = (void *)0xfd000000; base 568 drivers/irqchip/irq-s3c24xx.c intc->reg_mask = base + 0xa4; base 569 drivers/irqchip/irq-s3c24xx.c intc->reg_pending = base + 0xa8; base 36 drivers/irqchip/irq-sirfsoc.c static __init void sirfsoc_alloc_gc(void __iomem *base) base 50 drivers/irqchip/irq-sirfsoc.c gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET; base 60 drivers/irqchip/irq-sirfsoc.c void __iomem *base = sirfsoc_irq_get_regbase(); base 63 drivers/irqchip/irq-sirfsoc.c irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); base 70 drivers/irqchip/irq-sirfsoc.c void __iomem *base = of_iomap(np, 0); base 71 drivers/irqchip/irq-sirfsoc.c if (!base) base 75 drivers/irqchip/irq-sirfsoc.c &irq_generic_chip_ops, base); base 76 drivers/irqchip/irq-sirfsoc.c sirfsoc_alloc_gc(base); base 78 drivers/irqchip/irq-sirfsoc.c writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); base 79 drivers/irqchip/irq-sirfsoc.c writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1); base 81 drivers/irqchip/irq-sirfsoc.c writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0); base 82 drivers/irqchip/irq-sirfsoc.c writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1); base 101 drivers/irqchip/irq-sirfsoc.c void __iomem *base = sirfsoc_irq_get_regbase(); base 103 drivers/irqchip/irq-sirfsoc.c sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0); base 104 drivers/irqchip/irq-sirfsoc.c sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); base 105 drivers/irqchip/irq-sirfsoc.c sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0); base 106 drivers/irqchip/irq-sirfsoc.c sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1); base 113 drivers/irqchip/irq-sirfsoc.c void __iomem *base = sirfsoc_irq_get_regbase(); base 115 drivers/irqchip/irq-sirfsoc.c writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); base 116 drivers/irqchip/irq-sirfsoc.c writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); base 117 drivers/irqchip/irq-sirfsoc.c writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0); base 118 drivers/irqchip/irq-sirfsoc.c writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1); base 36 drivers/irqchip/irq-sni-exiu.c void __iomem *base; base 44 drivers/irqchip/irq-sni-exiu.c writel(BIT(d->hwirq), data->base + EIREQCLR); base 53 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); base 54 drivers/irqchip/irq-sni-exiu.c writel_relaxed(val, data->base + EIMASK); base 63 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); base 64 drivers/irqchip/irq-sni-exiu.c writel_relaxed(val, data->base + EIMASK); base 74 drivers/irqchip/irq-sni-exiu.c writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); base 76 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); base 77 drivers/irqchip/irq-sni-exiu.c writel_relaxed(val, data->base + EIMASK); base 86 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EILVL); base 91 drivers/irqchip/irq-sni-exiu.c writel_relaxed(val, data->base + EILVL); base 93 drivers/irqchip/irq-sni-exiu.c val = readl_relaxed(data->base + EIEDG); base 98 drivers/irqchip/irq-sni-exiu.c writel_relaxed(val, data->base + EIEDG); base 100 drivers/irqchip/irq-sni-exiu.c writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); base 193 drivers/irqchip/irq-sni-exiu.c data->base = ioremap(res->start, resource_size(res)); base 194 drivers/irqchip/irq-sni-exiu.c if (!data->base) { base 200 drivers/irqchip/irq-sni-exiu.c writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR); base 201 drivers/irqchip/irq-sni-exiu.c writel_relaxed(0xFFFFFFFF, data->base + EIMASK); base 250 drivers/irqchip/irq-sni-exiu.c iounmap(data->base); base 285 drivers/irqchip/irq-sni-exiu.c iounmap(data->base); base 65 drivers/irqchip/irq-stm32-exti.c void __iomem *base; base 352 drivers/irqchip/irq-stm32-exti.c void __iomem *base = chip_data->host_data->base; base 355 drivers/irqchip/irq-stm32-exti.c chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); base 356 drivers/irqchip/irq-stm32-exti.c chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); base 358 drivers/irqchip/irq-stm32-exti.c writel_relaxed(wake_active, base + stm32_bank->imr_ofst); base 365 drivers/irqchip/irq-stm32-exti.c void __iomem *base = chip_data->host_data->base; base 368 drivers/irqchip/irq-stm32-exti.c writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); base 369 drivers/irqchip/irq-stm32-exti.c writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); base 371 drivers/irqchip/irq-stm32-exti.c writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); base 437 drivers/irqchip/irq-stm32-exti.c void __iomem *base = chip_data->host_data->base; base 440 drivers/irqchip/irq-stm32-exti.c val = readl_relaxed(base + reg); base 442 drivers/irqchip/irq-stm32-exti.c writel_relaxed(val, base + reg); base 450 drivers/irqchip/irq-stm32-exti.c void __iomem *base = chip_data->host_data->base; base 453 drivers/irqchip/irq-stm32-exti.c val = readl_relaxed(base + reg); base 455 drivers/irqchip/irq-stm32-exti.c writel_relaxed(val, base + reg); base 507 drivers/irqchip/irq-stm32-exti.c void __iomem *base = chip_data->host_data->base; base 517 drivers/irqchip/irq-stm32-exti.c rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); base 518 drivers/irqchip/irq-stm32-exti.c ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); base 524 drivers/irqchip/irq-stm32-exti.c writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); base 525 drivers/irqchip/irq-stm32-exti.c writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); base 668 drivers/irqchip/irq-stm32-exti.c host_data->base = of_iomap(node, 0); base 669 drivers/irqchip/irq-stm32-exti.c if (!host_data->base) { base 693 drivers/irqchip/irq-stm32-exti.c void __iomem *base = h_data->base; base 706 drivers/irqchip/irq-stm32-exti.c writel_relaxed(0, base + stm32_bank->imr_ofst); base 707 drivers/irqchip/irq-stm32-exti.c writel_relaxed(0, base + stm32_bank->emr_ofst); base 753 drivers/irqchip/irq-stm32-exti.c gc->reg_base = host_data->base; base 781 drivers/irqchip/irq-stm32-exti.c iounmap(host_data->base); base 853 drivers/irqchip/irq-stm32-exti.c host_data->base = devm_ioremap_resource(dev, res); base 854 drivers/irqchip/irq-stm32-exti.c if (IS_ERR(host_data->base)) { base 856 drivers/irqchip/irq-stm32-exti.c return PTR_ERR(host_data->base); base 41 drivers/irqchip/irq-tango.c void __iomem *base; base 47 drivers/irqchip/irq-tango.c return readl_relaxed(chip->base + reg); base 52 drivers/irqchip/irq-tango.c writel_relaxed(val, chip->base + reg); base 56 drivers/irqchip/irq-tango.c int base) base 63 drivers/irqchip/irq-tango.c virq = irq_find_mapping(dom, base + hwirq); base 134 drivers/irqchip/irq-tango.c gc->reg_base = chip->base; base 172 drivers/irqchip/irq-tango.c static int __init tangox_irq_init(void __iomem *base, struct resource *baseres, base 191 drivers/irqchip/irq-tango.c chip->base = base; base 214 drivers/irqchip/irq-tango.c void __iomem *base; base 216 drivers/irqchip/irq-tango.c base = of_iomap(node, 0); base 217 drivers/irqchip/irq-tango.c if (!base) base 223 drivers/irqchip/irq-tango.c tangox_irq_init(base, &res, c); base 69 drivers/irqchip/irq-tegra.c void __iomem *base[TEGRA_MAX_NUM_ICTLRS]; base 84 drivers/irqchip/irq-tegra.c void __iomem *base = (void __iomem __force *)d->chip_data; base 88 drivers/irqchip/irq-tegra.c writel_relaxed(mask, base + reg); base 142 drivers/irqchip/irq-tegra.c void __iomem *ictlr = lic->base[i]; base 171 drivers/irqchip/irq-tegra.c void __iomem *ictlr = lic->base[i]; base 260 drivers/irqchip/irq-tegra.c (void __force *)info->base[ictlr]); base 306 drivers/irqchip/irq-tegra.c void __iomem *base; base 308 drivers/irqchip/irq-tegra.c base = of_iomap(node, i); base 309 drivers/irqchip/irq-tegra.c if (!base) base 312 drivers/irqchip/irq-tegra.c lic->base[i] = base; base 315 drivers/irqchip/irq-tegra.c writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR); base 317 drivers/irqchip/irq-tegra.c writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS); base 351 drivers/irqchip/irq-tegra.c iounmap(lic->base[i]); base 94 drivers/irqchip/irq-ti-sci-inta.c void __iomem *base; base 119 drivers/irqchip/irq-ti-sci-inta.c val = readq_relaxed(inta->base + vint_desc->vint_id * 0x1000 + base 370 drivers/irqchip/irq-ti-sci-inta.c inta->base + vint_desc->vint_id * 0x1000 + offset); base 572 drivers/irqchip/irq-ti-sci-inta.c inta->base = devm_ioremap_resource(dev, res); base 573 drivers/irqchip/irq-ti-sci-inta.c if (IS_ERR(inta->base)) base 27 drivers/irqchip/irq-ts4800.c void __iomem *base; base 35 drivers/irqchip/irq-ts4800.c u16 reg = readw(data->base + IRQ_MASK); base 38 drivers/irqchip/irq-ts4800.c writew(reg | mask, data->base + IRQ_MASK); base 44 drivers/irqchip/irq-ts4800.c u16 reg = readw(data->base + IRQ_MASK); base 47 drivers/irqchip/irq-ts4800.c writew(reg & ~mask, data->base + IRQ_MASK); base 71 drivers/irqchip/irq-ts4800.c u16 status = readw(data->base + IRQ_STATUS); base 105 drivers/irqchip/irq-ts4800.c data->base = devm_ioremap_resource(&pdev->dev, res); base 106 drivers/irqchip/irq-ts4800.c if (IS_ERR(data->base)) base 107 drivers/irqchip/irq-ts4800.c return PTR_ERR(data->base); base 109 drivers/irqchip/irq-ts4800.c writew(0xFFFF, data->base + IRQ_MASK); base 43 drivers/irqchip/irq-versatile-fpga.c void __iomem *base; base 59 drivers/irqchip/irq-versatile-fpga.c writel(mask, f->base + IRQ_ENABLE_CLEAR); base 67 drivers/irqchip/irq-versatile-fpga.c writel(mask, f->base + IRQ_ENABLE_SET); base 78 drivers/irqchip/irq-versatile-fpga.c status = readl(f->base + IRQ_STATUS); base 106 drivers/irqchip/irq-versatile-fpga.c while ((status = readl(f->base + IRQ_STATUS))) { base 149 drivers/irqchip/irq-versatile-fpga.c void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start, base 160 drivers/irqchip/irq-versatile-fpga.c f->base = base; base 185 drivers/irqchip/irq-versatile-fpga.c fpga_irq_id, name, base, f->used_irqs); base 198 drivers/irqchip/irq-versatile-fpga.c void __iomem *base; base 206 drivers/irqchip/irq-versatile-fpga.c base = of_iomap(node, 0); base 207 drivers/irqchip/irq-versatile-fpga.c WARN(!base, "unable to map fpga irq registers\n"); base 215 drivers/irqchip/irq-versatile-fpga.c writel(clear_mask, base + IRQ_ENABLE_CLEAR); base 216 drivers/irqchip/irq-versatile-fpga.c writel(clear_mask, base + FIQ_ENABLE_CLEAR); base 225 drivers/irqchip/irq-versatile-fpga.c fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); base 233 drivers/irqchip/irq-versatile-fpga.c writel(0xffd00000, base + PIC_ENABLES); base 60 drivers/irqchip/irq-vic.c void __iomem *base; base 86 drivers/irqchip/irq-vic.c static void vic_init2(void __iomem *base) base 91 drivers/irqchip/irq-vic.c void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); base 95 drivers/irqchip/irq-vic.c writel(32, base + VIC_PL190_DEF_VECT_ADDR); base 101 drivers/irqchip/irq-vic.c void __iomem *base = vic->base; base 103 drivers/irqchip/irq-vic.c printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); base 106 drivers/irqchip/irq-vic.c vic_init2(base); base 108 drivers/irqchip/irq-vic.c writel(vic->int_select, base + VIC_INT_SELECT); base 109 drivers/irqchip/irq-vic.c writel(vic->protect, base + VIC_PROTECT); base 112 drivers/irqchip/irq-vic.c writel(vic->int_enable, base + VIC_INT_ENABLE); base 113 drivers/irqchip/irq-vic.c writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); base 117 drivers/irqchip/irq-vic.c writel(vic->soft_int, base + VIC_INT_SOFT); base 118 drivers/irqchip/irq-vic.c writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); base 131 drivers/irqchip/irq-vic.c void __iomem *base = vic->base; base 133 drivers/irqchip/irq-vic.c printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); base 135 drivers/irqchip/irq-vic.c vic->int_select = readl(base + VIC_INT_SELECT); base 136 drivers/irqchip/irq-vic.c vic->int_enable = readl(base + VIC_INT_ENABLE); base 137 drivers/irqchip/irq-vic.c vic->soft_int = readl(base + VIC_INT_SOFT); base 138 drivers/irqchip/irq-vic.c vic->protect = readl(base + VIC_PROTECT); base 143 drivers/irqchip/irq-vic.c writel(vic->resume_irqs, base + VIC_INT_ENABLE); base 144 drivers/irqchip/irq-vic.c writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); base 190 drivers/irqchip/irq-vic.c irq_set_chip_data(irq, v->base); base 206 drivers/irqchip/irq-vic.c while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { base 223 drivers/irqchip/irq-vic.c while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { base 265 drivers/irqchip/irq-vic.c static void __init vic_register(void __iomem *base, unsigned int parent_irq, base 279 drivers/irqchip/irq-vic.c v->base = base; base 305 drivers/irqchip/irq-vic.c void __iomem *base = irq_data_get_irq_chip_data(d); base 307 drivers/irqchip/irq-vic.c writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); base 309 drivers/irqchip/irq-vic.c writel(1 << irq, base + VIC_INT_SOFT_CLEAR); base 314 drivers/irqchip/irq-vic.c void __iomem *base = irq_data_get_irq_chip_data(d); base 316 drivers/irqchip/irq-vic.c writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); base 321 drivers/irqchip/irq-vic.c void __iomem *base = irq_data_get_irq_chip_data(d); base 323 drivers/irqchip/irq-vic.c writel(1 << irq, base + VIC_INT_ENABLE); base 372 drivers/irqchip/irq-vic.c static void __init vic_disable(void __iomem *base) base 374 drivers/irqchip/irq-vic.c writel(0, base + VIC_INT_SELECT); base 375 drivers/irqchip/irq-vic.c writel(0, base + VIC_INT_ENABLE); base 376 drivers/irqchip/irq-vic.c writel(~0, base + VIC_INT_ENABLE_CLEAR); base 377 drivers/irqchip/irq-vic.c writel(0, base + VIC_ITCR); base 378 drivers/irqchip/irq-vic.c writel(~0, base + VIC_INT_SOFT_CLEAR); base 381 drivers/irqchip/irq-vic.c static void __init vic_clear_interrupts(void __iomem *base) base 385 drivers/irqchip/irq-vic.c writel(0, base + VIC_PL190_VECT_ADDR); base 389 drivers/irqchip/irq-vic.c value = readl(base + VIC_PL190_VECT_ADDR); base 390 drivers/irqchip/irq-vic.c writel(value, base + VIC_PL190_VECT_ADDR); base 401 drivers/irqchip/irq-vic.c static void __init vic_init_st(void __iomem *base, unsigned int irq_start, base 405 drivers/irqchip/irq-vic.c int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; base 408 drivers/irqchip/irq-vic.c vic_disable(base); base 417 drivers/irqchip/irq-vic.c vic_clear_interrupts(base); base 421 drivers/irqchip/irq-vic.c void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); base 425 drivers/irqchip/irq-vic.c writel(32, base + VIC_PL190_DEF_VECT_ADDR); base 428 drivers/irqchip/irq-vic.c vic_register(base, 0, irq_start, vic_sources, 0, node); base 431 drivers/irqchip/irq-vic.c void __init __vic_init(void __iomem *base, int parent_irq, int irq_start, base 442 drivers/irqchip/irq-vic.c addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); base 447 drivers/irqchip/irq-vic.c base, cellid, vendor); base 451 drivers/irqchip/irq-vic.c vic_init_st(base, irq_start, vic_sources, node); base 461 drivers/irqchip/irq-vic.c vic_disable(base); base 464 drivers/irqchip/irq-vic.c vic_clear_interrupts(base); base 466 drivers/irqchip/irq-vic.c vic_init2(base); base 468 drivers/irqchip/irq-vic.c vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node); base 478 drivers/irqchip/irq-vic.c void __init vic_init(void __iomem *base, unsigned int irq_start, base 481 drivers/irqchip/irq-vic.c __vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL); base 493 drivers/irqchip/irq-vic.c int __init vic_init_cascaded(void __iomem *base, unsigned int parent_irq, base 499 drivers/irqchip/irq-vic.c __vic_init(base, parent_irq, 0, vic_sources, resume_sources, NULL); base 62 drivers/irqchip/irq-vt8500.c void __iomem *base; /* IO Memory base address */ base 73 drivers/irqchip/irq-vt8500.c void __iomem *base = priv->base; base 74 drivers/irqchip/irq-vt8500.c void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4); base 78 drivers/irqchip/irq-vt8500.c edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE; base 85 drivers/irqchip/irq-vt8500.c dctr = readb(base + VT8500_ICDC + d->hwirq); base 87 drivers/irqchip/irq-vt8500.c writeb(dctr, base + VT8500_ICDC + d->hwirq); base 94 drivers/irqchip/irq-vt8500.c void __iomem *base = priv->base; base 97 drivers/irqchip/irq-vt8500.c dctr = readb(base + VT8500_ICDC + d->hwirq); base 99 drivers/irqchip/irq-vt8500.c writeb(dctr, base + VT8500_ICDC + d->hwirq); base 105 drivers/irqchip/irq-vt8500.c void __iomem *base = priv->base; base 108 drivers/irqchip/irq-vt8500.c dctr = readb(base + VT8500_ICDC + d->hwirq); base 127 drivers/irqchip/irq-vt8500.c writeb(dctr, base + VT8500_ICDC + d->hwirq); base 140 drivers/irqchip/irq-vt8500.c static void __init vt8500_init_irq_hw(void __iomem *base) base 145 drivers/irqchip/irq-vt8500.c writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ); base 146 drivers/irqchip/irq-vt8500.c writel(0x00, base + VT8500_ICPC_FIQ); base 150 drivers/irqchip/irq-vt8500.c writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i); base 170 drivers/irqchip/irq-vt8500.c void __iomem *base; base 174 drivers/irqchip/irq-vt8500.c base = intc[i].base; base 175 drivers/irqchip/irq-vt8500.c irqnr = readl_relaxed(base) & 0x3F; base 181 drivers/irqchip/irq-vt8500.c stat = readl_relaxed(base + VT8500_ICIS + 4); base 202 drivers/irqchip/irq-vt8500.c intc[active_cnt].base = of_iomap(np, 0); base 206 drivers/irqchip/irq-vt8500.c if (!intc[active_cnt].base) { base 218 drivers/irqchip/irq-vt8500.c vt8500_init_irq_hw(intc[active_cnt].base); base 38 drivers/irqchip/irq-xilinx-intc.c void __iomem *base; base 48 drivers/irqchip/irq-xilinx-intc.c iowrite32be(data, xintc_irqc->base + reg); base 50 drivers/irqchip/irq-xilinx-intc.c iowrite32(data, xintc_irqc->base + reg); base 56 drivers/irqchip/irq-xilinx-intc.c return ioread32be(xintc_irqc->base + reg); base 58 drivers/irqchip/irq-xilinx-intc.c return ioread32(xintc_irqc->base + reg); base 171 drivers/irqchip/irq-xilinx-intc.c irqc->base = of_iomap(intc, 0); base 172 drivers/irqchip/irq-xilinx-intc.c BUG_ON(!irqc->base); base 57 drivers/irqchip/irq-zevio.c static void __init zevio_init_irq_base(void __iomem *base) base 60 drivers/irqchip/irq-zevio.c writel(~0, base + IO_DISABLE); base 63 drivers/irqchip/irq-zevio.c writel(0xF, base + IO_MAX_PRIOTY); base 66 drivers/irqchip/irq-zevio.c readl(base + IO_RESET); base 42 drivers/irqchip/spear-shirq.c void __iomem *base; base 62 drivers/irqchip/spear-shirq.c u32 __iomem *reg = shirq->base + shirq->mask_reg; base 74 drivers/irqchip/spear-shirq.c u32 __iomem *reg = shirq->base + shirq->mask_reg; base 190 drivers/irqchip/spear-shirq.c pend = readl(shirq->base + shirq->status_reg) & shirq->mask; base 223 drivers/irqchip/spear-shirq.c void __iomem *base; base 225 drivers/irqchip/spear-shirq.c base = of_iomap(np, 0); base 226 drivers/irqchip/spear-shirq.c if (!base) { base 248 drivers/irqchip/spear-shirq.c shirq_blocks[i]->base = base; base 262 drivers/irqchip/spear-shirq.c iounmap(base); base 662 drivers/isdn/hardware/mISDN/mISDNisar.c struct isar_ch *base = &isar->ch[0]; base 666 drivers/isdn/hardware/mISDN/mISDNisar.c if (base->dpath == dpath) base 667 drivers/isdn/hardware/mISDN/mISDNisar.c return base; base 668 drivers/isdn/hardware/mISDN/mISDNisar.c base++; base 669 drivers/isdn/hardware/mISDN/mISDNisar.c if (base->dpath == dpath) base 670 drivers/isdn/hardware/mISDN/mISDNisar.c return base; base 70 drivers/isdn/hardware/mISDN/netjet.c u32 base; base 125 drivers/isdn/hardware/mISDN/netjet.c outb(0, card->base + NJ_IRQMASK0); base 126 drivers/isdn/hardware/mISDN/netjet.c outb(0, card->base + NJ_IRQMASK1); base 138 drivers/isdn/hardware/mISDN/netjet.c outb(card->auxd, card->base + NJ_AUXDATA); base 139 drivers/isdn/hardware/mISDN/netjet.c ret = inb(card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2)); base 150 drivers/isdn/hardware/mISDN/netjet.c outb(card->auxd, card->base + NJ_AUXDATA); base 151 drivers/isdn/hardware/mISDN/netjet.c outb(value, card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2)); base 160 drivers/isdn/hardware/mISDN/netjet.c outb(card->auxd, card->base + NJ_AUXDATA); base 161 drivers/isdn/hardware/mISDN/netjet.c insb(card->base + NJ_ISAC_OFF, data, size); base 170 drivers/isdn/hardware/mISDN/netjet.c outb(card->auxd, card->base + NJ_AUXDATA); base 171 drivers/isdn/hardware/mISDN/netjet.c outsb(card->base + NJ_ISAC_OFF, data, size); base 214 drivers/isdn/hardware/mISDN/netjet.c outb(card->dmactrl, card->base + NJ_DMACTRL); base 215 drivers/isdn/hardware/mISDN/netjet.c outb(0, card->base + NJ_IRQMASK0); base 233 drivers/isdn/hardware/mISDN/netjet.c outb(card->dmactrl, card->base + NJ_DMACTRL); base 234 drivers/isdn/hardware/mISDN/netjet.c outb(0x0f, card->base + NJ_IRQMASK0); base 249 drivers/isdn/hardware/mISDN/netjet.c outb(card->dmactrl, card->base + NJ_DMACTRL); base 250 drivers/isdn/hardware/mISDN/netjet.c outb(0x0f, card->base + NJ_IRQMASK0); base 258 drivers/isdn/hardware/mISDN/netjet.c card->send.dmacur = inl(card->base + NJ_DMA_READ_ADR); base 259 drivers/isdn/hardware/mISDN/netjet.c card->recv.dmacur = inl(card->base + NJ_DMA_WRITE_ADR); base 264 drivers/isdn/hardware/mISDN/netjet.c inb(card->base + NJ_DMACTRL), base 265 drivers/isdn/hardware/mISDN/netjet.c inb(card->base + NJ_IRQMASK0), base 266 drivers/isdn/hardware/mISDN/netjet.c inb(card->base + NJ_IRQSTAT0), base 275 drivers/isdn/hardware/mISDN/netjet.c outb(0xff, card->base + NJ_CTRL); /* Reset On */ base 284 drivers/isdn/hardware/mISDN/netjet.c outb(card->ctrlreg, card->base + NJ_CTRL); base 290 drivers/isdn/hardware/mISDN/netjet.c outb(~NJ_ISACIRQ, card->base + NJ_AUXCTRL); base 291 drivers/isdn/hardware/mISDN/netjet.c outb(NJ_ISACIRQ, card->base + NJ_IRQMASK1); base 292 drivers/isdn/hardware/mISDN/netjet.c outb(card->auxd, card->base + NJ_AUXDATA); base 338 drivers/isdn/hardware/mISDN/netjet.c outl(card->send.dmastart, card->base + NJ_DMA_READ_START); base 339 drivers/isdn/hardware/mISDN/netjet.c outl(card->send.dmairq, card->base + NJ_DMA_READ_IRQ); base 340 drivers/isdn/hardware/mISDN/netjet.c outl(card->send.dmaend, card->base + NJ_DMA_READ_END); base 356 drivers/isdn/hardware/mISDN/netjet.c outl(card->recv.dmastart, card->base + NJ_DMA_WRITE_START); base 357 drivers/isdn/hardware/mISDN/netjet.c outl(card->recv.dmairq, card->base + NJ_DMA_WRITE_IRQ); base 358 drivers/isdn/hardware/mISDN/netjet.c outl(card->recv.dmaend, card->base + NJ_DMA_WRITE_END); base 467 drivers/isdn/hardware/mISDN/netjet.c card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR); base 681 drivers/isdn/hardware/mISDN/netjet.c s0val = inb(card->base | NJ_IRQSTAT0); base 682 drivers/isdn/hardware/mISDN/netjet.c s1val = inb(card->base | NJ_IRQSTAT1); base 698 drivers/isdn/hardware/mISDN/netjet.c outb(s0val, card->base | NJ_IRQSTAT0); base 703 drivers/isdn/hardware/mISDN/netjet.c card->recv.dmacur = inl(card->base | NJ_DMA_WRITE_ADR); base 710 drivers/isdn/hardware/mISDN/netjet.c card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR); base 954 drivers/isdn/hardware/mISDN/netjet.c release_region(card->base, card->base_s); base 983 drivers/isdn/hardware/mISDN/netjet.c card->base = pci_resource_start(card->pdev, 0); base 985 drivers/isdn/hardware/mISDN/netjet.c if (!request_region(card->base, card->base_s, card->name)) { base 987 drivers/isdn/hardware/mISDN/netjet.c card->name, card->base, base 988 drivers/isdn/hardware/mISDN/netjet.c (u32)(card->base + card->base_s - 1)); base 1102 drivers/isdn/hardware/mISDN/netjet.c card->base = pci_resource_start(pdev, 0); base 43 drivers/leds/leds-asic3.c unsigned int base; base 47 drivers/leds/leds-asic3.c base = led_n_base[cell->id]; base 48 drivers/leds/leds-asic3.c asic3_write_register(asic, (base + ASIC3_LED_PeriodTime), 32); base 49 drivers/leds/leds-asic3.c asic3_write_register(asic, (base + ASIC3_LED_DutyTime), 32); base 50 drivers/leds/leds-asic3.c asic3_write_register(asic, (base + ASIC3_LED_AutoStopCount), 0); base 51 drivers/leds/leds-asic3.c asic3_write_register(asic, (base + ASIC3_LED_TimeBase), timebase); base 63 drivers/leds/leds-asic3.c unsigned int base; base 79 drivers/leds/leds-asic3.c base = led_n_base[cell->id]; base 80 drivers/leds/leds-asic3.c asic3_write_register(asic, (base + ASIC3_LED_PeriodTime), (on + off)); base 81 drivers/leds/leds-asic3.c asic3_write_register(asic, (base + ASIC3_LED_DutyTime), on); base 82 drivers/leds/leds-asic3.c asic3_write_register(asic, (base + ASIC3_LED_AutoStopCount), 0); base 83 drivers/leds/leds-asic3.c asic3_write_register(asic, (base + ASIC3_LED_TimeBase), (LED_EN|0x4)); base 64 drivers/leds/leds-lm3533.c static inline u8 lm3533_led_get_lv_reg(struct lm3533_led *led, u8 base) base 66 drivers/leds/leds-lm3533.c return base + led->id; base 75 drivers/leds/leds-lm3533.c u8 base) base 77 drivers/leds/leds-lm3533.c return base + lm3533_led_get_pattern(led) * LM3533_REG_PATTERN_STEP; base 243 drivers/leds/leds-lm3533.c static u8 lm3533_led_delay_set(struct lm3533_led *led, u8 base, base 254 drivers/leds/leds-lm3533.c if (base != LM3533_REG_PATTERN_LOW_TIME_BASE) base 261 drivers/leds/leds-lm3533.c reg = lm3533_led_get_pattern_reg(led, base); base 334 drivers/leds/leds-lm3533.c char *buf, u8 base) base 342 drivers/leds/leds-lm3533.c reg = lm3533_led_get_pattern_reg(led, base); base 366 drivers/leds/leds-lm3533.c const char *buf, size_t len, u8 base) base 377 drivers/leds/leds-lm3533.c reg = lm3533_led_get_pattern_reg(led, base); base 334 drivers/leds/leds-lp5562.c u8 base, const u8 *rgb, int size) base 342 drivers/leds/leds-lp5562.c lp55xx_write(chip, base + i, *(rgb + i)); base 344 drivers/leds/leds-lp5562.c lp55xx_write(chip, base + i, 0); base 345 drivers/leds/leds-lp5562.c lp55xx_write(chip, base + i + 1, 0); base 247 drivers/leds/leds-mlxcpld.c static void mlxcpld_led_bus_access_func(u16 base, u8 offset, u8 rw_flag, base 250 drivers/leds/leds-mlxcpld.c u32 addr = base + offset; base 440 drivers/leds/leds-pca9532.c data->gpio.base = pdata->gpio_base; base 452 drivers/leds/leds-pca9532.c data->gpio.base, data->gpio.base + base 549 drivers/leds/leds-pca955x.c pca955x->gpio.base = -1; base 563 drivers/leds/leds-pca955x.c pca955x->gpio.base, pca955x->gpio.base + base 59 drivers/leds/leds-sc27xx-bltc.c u32 base; base 84 drivers/leds/leds-sc27xx-bltc.c return leds->priv->base + SC27XX_LEDS_OFFSET * leds->line; base 89 drivers/leds/leds-sc27xx-bltc.c u32 base = sc27xx_led_get_offset(leds); base 90 drivers/leds/leds-sc27xx-bltc.c u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; base 95 drivers/leds/leds-sc27xx-bltc.c err = regmap_update_bits(regmap, base + SC27XX_LEDS_DUTY, base 110 drivers/leds/leds-sc27xx-bltc.c u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; base 150 drivers/leds/leds-sc27xx-bltc.c u32 base = sc27xx_led_get_offset(leds); base 151 drivers/leds/leds-sc27xx-bltc.c u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; base 158 drivers/leds/leds-sc27xx-bltc.c regmap_write(regmap, base + SC27XX_LEDS_CURVE0, 0); base 159 drivers/leds/leds-sc27xx-bltc.c regmap_write(regmap, base + SC27XX_LEDS_CURVE1, 0); base 176 drivers/leds/leds-sc27xx-bltc.c u32 base = sc27xx_led_get_offset(leds); base 177 drivers/leds/leds-sc27xx-bltc.c u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; base 192 drivers/leds/leds-sc27xx-bltc.c err = regmap_update_bits(regmap, base + SC27XX_LEDS_CURVE0, base 199 drivers/leds/leds-sc27xx-bltc.c err = regmap_update_bits(regmap, base + SC27XX_LEDS_CURVE1, base 206 drivers/leds/leds-sc27xx-bltc.c err = regmap_update_bits(regmap, base + SC27XX_LEDS_CURVE0, base 214 drivers/leds/leds-sc27xx-bltc.c err = regmap_update_bits(regmap, base + SC27XX_LEDS_CURVE1, base 221 drivers/leds/leds-sc27xx-bltc.c err = regmap_update_bits(regmap, base + SC27XX_LEDS_DUTY, base 281 drivers/leds/leds-sc27xx-bltc.c u32 base, count, reg; base 288 drivers/leds/leds-sc27xx-bltc.c err = of_property_read_u32(np, "reg", &base); base 300 drivers/leds/leds-sc27xx-bltc.c priv->base = base; base 653 drivers/leds/leds-tca6507.c tca->gpio.base = pdata->gpio_base; base 667 drivers/leds/leds-tca6507.c pdata->setup(tca->gpio.base, tca->gpio.ngpio); base 32 drivers/macintosh/mediabay.c #define MB_FCR32(bay, r) ((bay)->base + ((r) >> 2)) base 33 drivers/macintosh/mediabay.c #define MB_FCR8(bay, r) (((volatile u8 __iomem *)((bay)->base)) + (r)) base 55 drivers/macintosh/mediabay.c u32 __iomem *base; base 561 drivers/macintosh/mediabay.c unsigned long base; base 574 drivers/macintosh/mediabay.c base = macio_resource_start(mdev, 0) & 0xffff0000u; base 575 drivers/macintosh/mediabay.c regbase = (u32 __iomem *)ioremap(base, 0x100); base 584 drivers/macintosh/mediabay.c bay->base = regbase; base 34 drivers/mailbox/arm_mhu.c void __iomem *base; base 121 drivers/mailbox/arm_mhu.c mhu->base = devm_ioremap_resource(dev, &adev->res); base 122 drivers/mailbox/arm_mhu.c if (IS_ERR(mhu->base)) { base 124 drivers/mailbox/arm_mhu.c return PTR_ERR(mhu->base); base 130 drivers/mailbox/arm_mhu.c mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i]; base 39 drivers/mailbox/armada-37xx-rwtm-mailbox.c void __iomem *base; base 49 drivers/mailbox/armada-37xx-rwtm-mailbox.c rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS); base 51 drivers/mailbox/armada-37xx-rwtm-mailbox.c rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i)); base 62 drivers/mailbox/armada-37xx-rwtm-mailbox.c reg = readl(mbox->base + RWTM_HOST_INT_RESET); base 70 drivers/mailbox/armada-37xx-rwtm-mailbox.c writel(reg, mbox->base + RWTM_HOST_INT_RESET); base 87 drivers/mailbox/armada-37xx-rwtm-mailbox.c reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS); base 97 drivers/mailbox/armada-37xx-rwtm-mailbox.c writel(msg->args[i], mbox->base + RWTM_MBOX_PARAM(i)); base 98 drivers/mailbox/armada-37xx-rwtm-mailbox.c writel(msg->command, mbox->base + RWTM_MBOX_COMMAND); base 117 drivers/mailbox/armada-37xx-rwtm-mailbox.c reg = readl(mbox->base + RWTM_HOST_INT_MASK); base 119 drivers/mailbox/armada-37xx-rwtm-mailbox.c writel(reg, mbox->base + RWTM_HOST_INT_MASK); base 130 drivers/mailbox/armada-37xx-rwtm-mailbox.c reg = readl(mbox->base + RWTM_HOST_INT_MASK); base 132 drivers/mailbox/armada-37xx-rwtm-mailbox.c writel(reg, mbox->base + RWTM_HOST_INT_MASK); base 161 drivers/mailbox/armada-37xx-rwtm-mailbox.c mbox->base = devm_ioremap_resource(&pdev->dev, regs); base 162 drivers/mailbox/armada-37xx-rwtm-mailbox.c if (IS_ERR(mbox->base)) { base 164 drivers/mailbox/armada-37xx-rwtm-mailbox.c return PTR_ERR(mbox->base); base 24 drivers/mailbox/hi3660-mailbox.c #define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40)) base 75 drivers/mailbox/hi3660-mailbox.c void __iomem *base; base 91 drivers/mailbox/hi3660-mailbox.c void __iomem *base = MBOX_BASE(mbox, ch); base 96 drivers/mailbox/hi3660-mailbox.c if (readl(base + MBOX_MODE_REG) & MBOX_STATE_READY) base 100 drivers/mailbox/hi3660-mailbox.c ret = readx_poll_timeout_atomic(readl, base + MBOX_MODE_REG, base 108 drivers/mailbox/hi3660-mailbox.c writel(BIT(mchan->ack_irq), base + MBOX_ICLR_REG); base 119 drivers/mailbox/hi3660-mailbox.c writel(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG); base 121 drivers/mailbox/hi3660-mailbox.c val = readl(mbox->base + MBOX_IPC_LOCK_REG); base 139 drivers/mailbox/hi3660-mailbox.c void __iomem *base = MBOX_BASE(mbox, ch); base 144 drivers/mailbox/hi3660-mailbox.c if (readl(base + MBOX_MODE_REG) & MBOX_STATE_IDLE) { base 145 drivers/mailbox/hi3660-mailbox.c writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG); base 148 drivers/mailbox/hi3660-mailbox.c val = readl(base + MBOX_SRC_REG); base 180 drivers/mailbox/hi3660-mailbox.c void __iomem *base = MBOX_BASE(mbox, ch); base 190 drivers/mailbox/hi3660-mailbox.c writel_relaxed(~BIT(mchan->dst_irq), base + MBOX_IMASK_REG); base 193 drivers/mailbox/hi3660-mailbox.c writel_relaxed(BIT(mchan->dst_irq), base + MBOX_DST_REG); base 196 drivers/mailbox/hi3660-mailbox.c writel_relaxed(MBOX_AUTOMATIC_ACK, base + MBOX_MODE_REG); base 200 drivers/mailbox/hi3660-mailbox.c writel_relaxed(buf[i], base + MBOX_DATA_REG + i * 4); base 203 drivers/mailbox/hi3660-mailbox.c writel(BIT(mchan->ack_irq), base + MBOX_SEND_REG); base 252 drivers/mailbox/hi3660-mailbox.c mbox->base = devm_ioremap_resource(dev, res); base 253 drivers/mailbox/hi3660-mailbox.c if (IS_ERR(mbox->base)) base 254 drivers/mailbox/hi3660-mailbox.c return PTR_ERR(mbox->base); base 79 drivers/mailbox/hi6220-mailbox.c void __iomem *base; base 94 drivers/mailbox/hi6220-mailbox.c status = readl(mbox->base + MBOX_MODE_REG(slot)); base 96 drivers/mailbox/hi6220-mailbox.c writel(status, mbox->base + MBOX_MODE_REG(slot)); base 104 drivers/mailbox/hi6220-mailbox.c mode = readl(mbox->base + MBOX_MODE_REG(slot)); base 106 drivers/mailbox/hi6220-mailbox.c writel(mode, mbox->base + MBOX_MODE_REG(slot)); base 118 drivers/mailbox/hi6220-mailbox.c state = readl(mbox->base + MBOX_MODE_REG(mchan->slot)); base 141 drivers/mailbox/hi6220-mailbox.c writel(buf[i], mbox->base + MBOX_DATA_REG(slot) + i * 4); base 179 drivers/mailbox/hi6220-mailbox.c msg[i] = readl(mbox->base + base 298 drivers/mailbox/hi6220-mailbox.c mbox->base = devm_ioremap_resource(dev, res); base 299 drivers/mailbox/hi6220-mailbox.c if (IS_ERR(mbox->base)) { base 301 drivers/mailbox/hi6220-mailbox.c return PTR_ERR(mbox->base); base 57 drivers/mailbox/imx-mailbox.c void __iomem *base; base 77 drivers/mailbox/imx-mailbox.c iowrite32(val, priv->base + offs); base 82 drivers/mailbox/imx-mailbox.c return ioread32(priv->base + offs); base 290 drivers/mailbox/imx-mailbox.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 291 drivers/mailbox/imx-mailbox.c if (IS_ERR(priv->base)) base 292 drivers/mailbox/imx-mailbox.c return PTR_ERR(priv->base); base 36 drivers/mailbox/mailbox-sti.c #define MBOX_BASE(mdev, inst) ((mdev)->base + ((inst) * 4)) base 56 drivers/mailbox/mailbox-sti.c void __iomem *base; base 126 drivers/mailbox/mailbox-sti.c void __iomem *base = MBOX_BASE(mdev, instance); base 130 drivers/mailbox/mailbox-sti.c writel_relaxed(BIT(channel), base + STI_ENA_SET_OFFSET); base 141 drivers/mailbox/mailbox-sti.c void __iomem *base = MBOX_BASE(mdev, instance); base 145 drivers/mailbox/mailbox-sti.c writel_relaxed(BIT(channel), base + STI_ENA_CLR_OFFSET); base 155 drivers/mailbox/mailbox-sti.c void __iomem *base = MBOX_BASE(mdev, instance); base 157 drivers/mailbox/mailbox-sti.c writel_relaxed(BIT(channel), base + STI_IRQ_CLR_OFFSET); base 167 drivers/mailbox/mailbox-sti.c void __iomem *base = MBOX_BASE(mdev, instance); base 169 drivers/mailbox/mailbox-sti.c bits = readl_relaxed(base + STI_IRQ_VAL_OFFSET); base 257 drivers/mailbox/mailbox-sti.c void __iomem *base = MBOX_BASE(mdev, instance); base 259 drivers/mailbox/mailbox-sti.c if (!(readl_relaxed(base + STI_ENA_VAL_OFFSET) & BIT(channel))) { base 265 drivers/mailbox/mailbox-sti.c if (readl_relaxed(base + STI_IRQ_VAL_OFFSET) & BIT(channel)) { base 280 drivers/mailbox/mailbox-sti.c void __iomem *base = MBOX_BASE(mdev, instance); base 283 drivers/mailbox/mailbox-sti.c writel_relaxed(BIT(channel), base + STI_IRQ_SET_OFFSET); base 429 drivers/mailbox/mailbox-sti.c mdev->base = devm_ioremap_resource(&pdev->dev, res); base 430 drivers/mailbox/mailbox-sti.c if (IS_ERR(mdev->base)) base 431 drivers/mailbox/mailbox-sti.c return PTR_ERR(mdev->base); base 56 drivers/mailbox/mtk-cmdq-mailbox.c void __iomem *base; base 72 drivers/mailbox/mtk-cmdq-mailbox.c void __iomem *base; base 85 drivers/mailbox/mtk-cmdq-mailbox.c writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK); base 88 drivers/mailbox/mtk-cmdq-mailbox.c if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) base 91 drivers/mailbox/mtk-cmdq-mailbox.c if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS, base 94 drivers/mailbox/mtk-cmdq-mailbox.c (u32)(thread->base - cmdq->base)); base 103 drivers/mailbox/mtk-cmdq-mailbox.c writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK); base 111 drivers/mailbox/mtk-cmdq-mailbox.c writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); base 113 drivers/mailbox/mtk-cmdq-mailbox.c writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); base 121 drivers/mailbox/mtk-cmdq-mailbox.c writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET); base 122 drivers/mailbox/mtk-cmdq-mailbox.c if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET, base 126 drivers/mailbox/mtk-cmdq-mailbox.c (u32)(thread->base - cmdq->base)); base 136 drivers/mailbox/mtk-cmdq-mailbox.c writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK); base 142 drivers/mailbox/mtk-cmdq-mailbox.c writel(readl(thread->base + CMDQ_THR_CURR_ADDR), base 143 drivers/mailbox/mtk-cmdq-mailbox.c thread->base + CMDQ_THR_CURR_ADDR); base 178 drivers/mailbox/mtk-cmdq-mailbox.c u64 *base = task->pkt->va_base; base 184 drivers/mailbox/mtk-cmdq-mailbox.c if (cmdq_command_is_wfe(base[i])) base 185 drivers/mailbox/mtk-cmdq-mailbox.c base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 | base 193 drivers/mailbox/mtk-cmdq-mailbox.c return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING; base 202 drivers/mailbox/mtk-cmdq-mailbox.c if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_ADDR, base 230 drivers/mailbox/mtk-cmdq-mailbox.c writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR); base 241 drivers/mailbox/mtk-cmdq-mailbox.c irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS); base 242 drivers/mailbox/mtk-cmdq-mailbox.c writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS); base 250 drivers/mailbox/mtk-cmdq-mailbox.c if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) base 260 drivers/mailbox/mtk-cmdq-mailbox.c curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR); base 293 drivers/mailbox/mtk-cmdq-mailbox.c irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask; base 376 drivers/mailbox/mtk-cmdq-mailbox.c writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR); base 378 drivers/mailbox/mtk-cmdq-mailbox.c thread->base + CMDQ_THR_END_ADDR); base 379 drivers/mailbox/mtk-cmdq-mailbox.c writel(thread->priority, thread->base + CMDQ_THR_PRIORITY); base 380 drivers/mailbox/mtk-cmdq-mailbox.c writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE); base 381 drivers/mailbox/mtk-cmdq-mailbox.c writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK); base 384 drivers/mailbox/mtk-cmdq-mailbox.c curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR); base 385 drivers/mailbox/mtk-cmdq-mailbox.c end_pa = readl(thread->base + CMDQ_THR_END_ADDR); base 399 drivers/mailbox/mtk-cmdq-mailbox.c thread->base + CMDQ_THR_CURR_ADDR); base 411 drivers/mailbox/mtk-cmdq-mailbox.c thread->base + CMDQ_THR_CURR_ADDR); base 418 drivers/mailbox/mtk-cmdq-mailbox.c thread->base + CMDQ_THR_END_ADDR); base 470 drivers/mailbox/mtk-cmdq-mailbox.c cmdq->base = devm_ioremap_resource(dev, res); base 471 drivers/mailbox/mtk-cmdq-mailbox.c if (IS_ERR(cmdq->base)) { base 473 drivers/mailbox/mtk-cmdq-mailbox.c return PTR_ERR(cmdq->base); base 492 drivers/mailbox/mtk-cmdq-mailbox.c dev, cmdq->base, cmdq->irq); base 520 drivers/mailbox/mtk-cmdq-mailbox.c cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE + base 40 drivers/mailbox/platform_mhu.c void __iomem *base; base 131 drivers/mailbox/platform_mhu.c mhu->base = devm_ioremap_resource(dev, res); base 132 drivers/mailbox/platform_mhu.c if (IS_ERR(mhu->base)) { base 134 drivers/mailbox/platform_mhu.c return PTR_ERR(mhu->base); base 144 drivers/mailbox/platform_mhu.c mhu->mlink[i].rx_reg = mhu->base + platform_mhu_reg[i]; base 54 drivers/mailbox/qcom-apcs-ipc-mailbox.c void __iomem *base; base 68 drivers/mailbox/qcom-apcs-ipc-mailbox.c base = devm_ioremap_resource(&pdev->dev, res); base 69 drivers/mailbox/qcom-apcs-ipc-mailbox.c if (IS_ERR(base)) base 70 drivers/mailbox/qcom-apcs-ipc-mailbox.c return PTR_ERR(base); base 72 drivers/mailbox/qcom-apcs-ipc-mailbox.c regmap = devm_regmap_init_mmio(&pdev->dev, base, &apcs_regmap_config); base 126 drivers/mcb/mcb-internal.h void __iomem *base); base 19 drivers/mcb/mcb-lpc.c void __iomem *base; base 46 drivers/mcb/mcb-lpc.c priv->base = devm_ioremap(&pdev->dev, priv->mem->start, base 48 drivers/mcb/mcb-lpc.c if (!priv->base) { base 59 drivers/mcb/mcb-lpc.c ret = chameleon_parse_cells(priv->bus, priv->mem->start, priv->base); base 13 drivers/mcb/mcb-parse.c void __iomem *base; base 31 drivers/mcb/mcb-parse.c void __iomem *base) base 38 drivers/mcb/mcb-parse.c void __iomem *base, int bar_count) base 41 drivers/mcb/mcb-parse.c (struct chameleon_gdd __iomem *) base; base 116 drivers/mcb/mcb-parse.c static void chameleon_parse_bar(void __iomem *base, base 119 drivers/mcb/mcb-parse.c char __iomem *p = base; base 133 drivers/mcb/mcb-parse.c static int chameleon_get_bar(char __iomem **base, phys_addr_t mapbase, base 148 drivers/mcb/mcb-parse.c dtype = get_next_dtype(*base); base 150 drivers/mcb/mcb-parse.c reg = readl(*base); base 161 drivers/mcb/mcb-parse.c chameleon_parse_bar(*base, c, bar_count); base 162 drivers/mcb/mcb-parse.c *base += BAR_DESC_SIZE(bar_count); base 178 drivers/mcb/mcb-parse.c void __iomem *base) base 182 drivers/mcb/mcb-parse.c char __iomem *p = base; base 18 drivers/mcb/mcb-pci.c void __iomem *base; base 64 drivers/mcb/mcb-pci.c priv->base = devm_ioremap(&pdev->dev, priv->mapbase, CHAM_HEADER_SIZE); base 65 drivers/mcb/mcb-pci.c if (!priv->base) { base 89 drivers/mcb/mcb-pci.c ret = chameleon_parse_cells(priv->bus, priv->mapbase, priv->base); base 20 drivers/md/bcache/util.c #define simple_strtoint(c, end, base) simple_strtol(c, end, base) base 21 drivers/md/bcache/util.c #define simple_strtouint(c, end, base) simple_strtoul(c, end, base) base 231 drivers/md/bcache/util.c void bch_bio_map(struct bio *bio, void *base) base 239 drivers/md/bcache/util.c bv->bv_offset = base ? offset_in_page(base) : 0; base 246 drivers/md/bcache/util.c if (base) { base 247 drivers/md/bcache/util.c bv->bv_page = is_vmalloc_addr(base) base 248 drivers/md/bcache/util.c ? vmalloc_to_page(base) base 249 drivers/md/bcache/util.c : virt_to_page(base); base 251 drivers/md/bcache/util.c base += bv->bv_len; base 586 drivers/md/bcache/util.h void bch_bio_map(struct bio *bio, void *base); base 1795 drivers/md/dm-crypt.c crypto_skcipher_alg(any_tfm(cc))->base.cra_driver_name); base 1815 drivers/md/dm-crypt.c crypto_aead_alg(any_tfm_aead(cc))->base.cra_driver_name); base 74 drivers/md/dm-table.c static unsigned int int_log(unsigned int n, unsigned int base) base 79 drivers/md/dm-table.c n = dm_div_up(n, base); base 1068 drivers/md/dm-verity-target.c crypto_hash_alg_common(v->tfm)->base.cra_driver_name); base 699 drivers/md/persistent-data/dm-array.c value_fn fn, void *context, unsigned base, unsigned new_nr) base 709 drivers/md/persistent-data/dm-array.c r = fn(base + i, element_at(info, ab, i), context); base 26 drivers/md/persistent-data/dm-btree.c static void array_insert(void *base, size_t elt_size, unsigned nr_elts, base 31 drivers/md/persistent-data/dm-btree.c memmove(base + (elt_size * (index + 1)), base 32 drivers/md/persistent-data/dm-btree.c base + (elt_size * index), base 35 drivers/md/persistent-data/dm-btree.c memcpy_disk(base + (elt_size * index), elt, elt_size); base 87 drivers/media/cec/cec-adap.c conn_info->drm.connector_id = connector->base.id; base 574 drivers/media/common/saa7146/saa7146_hlp.c u32 base = (u32)(unsigned long)vv->ov_fb.base; base 581 drivers/media/common/saa7146/saa7146_hlp.c vdma1.base_even = base + (w_y * (vdma1.pitch/2)) + (w_x * (b_depth / 8)); base 586 drivers/media/common/saa7146/saa7146_hlp.c vdma1.base_even = base + ((w_y+w_height) * (vdma1.pitch/2)) + (w_x * (b_depth / 8)); base 687 drivers/media/common/saa7146/saa7146_video.c if (NULL == vv->ov_fb.base) { base 1110 drivers/media/dvb-core/dmxdev.c &((struct dmx_stc *)parg)->base); base 657 drivers/media/dvb-frontends/cxd2820r_core.c priv->gpio_chip.base = -1; /* Dynamic allocation */ base 665 drivers/media/dvb-frontends/cxd2820r_core.c priv->gpio_chip.base); base 667 drivers/media/dvb-frontends/cxd2820r_core.c *gpio_chip_base = priv->gpio_chip.base; base 83 drivers/media/dvb-frontends/mxl5xx.c struct mxl_base *base; base 150 drivers/media/dvb-frontends/mxl5xx.c return i2c_read(state->base->i2c, state->base->adr, data, len); base 155 drivers/media/dvb-frontends/mxl5xx.c return i2c_write(state->base->i2c, state->base->adr, data, len); base 188 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->i2c_lock); base 189 drivers/media/dvb-frontends/mxl5xx.c if (state->base->fwversion > 0x02010109) { base 194 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->i2c_lock); base 196 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->i2c_lock); base 202 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->i2c_lock); base 207 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->i2c_lock); base 219 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->i2c_lock); base 221 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->i2c_lock); base 231 drivers/media/dvb-frontends/mxl5xx.c u8 *buf = state->base->buf; base 233 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->i2c_lock); base 244 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->i2c_lock); base 259 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->i2c_lock); base 267 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->i2c_lock); base 277 drivers/media/dvb-frontends/mxl5xx.c u8 *buf = state->base->buf; base 279 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->i2c_lock); base 293 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->i2c_lock); base 370 drivers/media/dvb-frontends/mxl5xx.c state->base->count--; base 371 drivers/media/dvb-frontends/mxl5xx.c if (state->base->count == 0) { base 372 drivers/media/dvb-frontends/mxl5xx.c list_del(&state->base->mxllist); base 373 drivers/media/dvb-frontends/mxl5xx.c kfree(state->base); base 485 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->tune_lock); base 487 drivers/media/dvb-frontends/mxl5xx.c state->base->next_tune)) base 488 drivers/media/dvb-frontends/mxl5xx.c while (time_before(jiffies, state->base->next_tune)) base 490 drivers/media/dvb-frontends/mxl5xx.c state->base->next_tune = jiffies + msecs_to_jiffies(100); base 496 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->tune_lock); base 509 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->tune_lock); base 511 drivers/media/dvb-frontends/mxl5xx.c list_for_each_entry(p, &state->base->mxls, mxl) { base 515 drivers/media/dvb-frontends/mxl5xx.c if (&p->mxl == &state->base->mxls) base 517 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->tune_lock); base 529 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->status_lock); base 535 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->status_lock); base 549 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->status_lock); base 594 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->status_lock); base 606 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->status_lock); base 612 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->status_lock); base 626 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->status_lock); base 632 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->status_lock); base 696 drivers/media/dvb-frontends/mxl5xx.c mutex_lock(&state->base->status_lock); base 710 drivers/media/dvb-frontends/mxl5xx.c mutex_unlock(&state->base->status_lock); base 819 drivers/media/dvb-frontends/mxl5xx.c if (state->base->can_clkout || !enable) base 918 drivers/media/dvb-frontends/mxl5xx.c if (state->base->type == MXL_HYDRA_DEVICE_568) { base 1013 drivers/media/dvb-frontends/mxl5xx.c if (state->base->type == MXL_HYDRA_DEVICE_568) { base 1050 drivers/media/dvb-frontends/mxl5xx.c dev_sku_cfg.sku_type = state->base->sku_type; base 1066 drivers/media/dvb-frontends/mxl5xx.c if ((state->base->type == MXL_HYDRA_DEVICE_541) || base 1067 drivers/media/dvb-frontends/mxl5xx.c (state->base->type == MXL_HYDRA_DEVICE_541S)) base 1070 drivers/media/dvb-frontends/mxl5xx.c if ((state->base->type == MXL_HYDRA_DEVICE_581) || base 1071 drivers/media/dvb-frontends/mxl5xx.c (state->base->type == MXL_HYDRA_DEVICE_581S)) base 1077 drivers/media/dvb-frontends/mxl5xx.c switch (state->base->type) { base 1450 drivers/media/dvb-frontends/mxl5xx.c demod_id = state->base->ts_map[demod_id]; base 1465 drivers/media/dvb-frontends/mxl5xx.c if (state->base->chipversion >= 2) { base 1619 drivers/media/dvb-frontends/mxl5xx.c u32 type = state->base->type; base 1636 drivers/media/dvb-frontends/mxl5xx.c state->base->type = MXL_HYDRA_DEVICE_581; base 1683 drivers/media/dvb-frontends/mxl5xx.c state->base->fwversion = val; base 1716 drivers/media/dvb-frontends/mxl5xx.c state->base->ts_map = ts_map1_to_1; base 1718 drivers/media/dvb-frontends/mxl5xx.c switch (state->base->type) { base 1721 drivers/media/dvb-frontends/mxl5xx.c state->base->can_clkout = 1; base 1722 drivers/media/dvb-frontends/mxl5xx.c state->base->demod_num = 8; base 1723 drivers/media/dvb-frontends/mxl5xx.c state->base->tuner_num = 1; base 1724 drivers/media/dvb-frontends/mxl5xx.c state->base->sku_type = MXL_HYDRA_SKU_TYPE_581; base 1727 drivers/media/dvb-frontends/mxl5xx.c state->base->can_clkout = 1; base 1728 drivers/media/dvb-frontends/mxl5xx.c state->base->demod_num = 8; base 1729 drivers/media/dvb-frontends/mxl5xx.c state->base->tuner_num = 3; base 1730 drivers/media/dvb-frontends/mxl5xx.c state->base->sku_type = MXL_HYDRA_SKU_TYPE_582; base 1733 drivers/media/dvb-frontends/mxl5xx.c state->base->can_clkout = 0; base 1734 drivers/media/dvb-frontends/mxl5xx.c state->base->demod_num = 8; base 1735 drivers/media/dvb-frontends/mxl5xx.c state->base->tuner_num = 4; base 1736 drivers/media/dvb-frontends/mxl5xx.c state->base->sku_type = MXL_HYDRA_SKU_TYPE_585; base 1739 drivers/media/dvb-frontends/mxl5xx.c state->base->can_clkout = 0; base 1740 drivers/media/dvb-frontends/mxl5xx.c state->base->demod_num = 4; base 1741 drivers/media/dvb-frontends/mxl5xx.c state->base->tuner_num = 4; base 1742 drivers/media/dvb-frontends/mxl5xx.c state->base->sku_type = MXL_HYDRA_SKU_TYPE_544; base 1743 drivers/media/dvb-frontends/mxl5xx.c state->base->ts_map = ts_map54x; base 1747 drivers/media/dvb-frontends/mxl5xx.c state->base->can_clkout = 0; base 1748 drivers/media/dvb-frontends/mxl5xx.c state->base->demod_num = 4; base 1749 drivers/media/dvb-frontends/mxl5xx.c state->base->tuner_num = 1; base 1750 drivers/media/dvb-frontends/mxl5xx.c state->base->sku_type = MXL_HYDRA_SKU_TYPE_541; base 1751 drivers/media/dvb-frontends/mxl5xx.c state->base->ts_map = ts_map54x; base 1755 drivers/media/dvb-frontends/mxl5xx.c state->base->can_clkout = 0; base 1756 drivers/media/dvb-frontends/mxl5xx.c state->base->demod_num = 6; base 1757 drivers/media/dvb-frontends/mxl5xx.c state->base->tuner_num = 1; base 1758 drivers/media/dvb-frontends/mxl5xx.c state->base->sku_type = MXL_HYDRA_SKU_TYPE_561; base 1761 drivers/media/dvb-frontends/mxl5xx.c state->base->can_clkout = 0; base 1762 drivers/media/dvb-frontends/mxl5xx.c state->base->demod_num = 8; base 1763 drivers/media/dvb-frontends/mxl5xx.c state->base->tuner_num = 1; base 1764 drivers/media/dvb-frontends/mxl5xx.c state->base->chan_bond = 1; base 1765 drivers/media/dvb-frontends/mxl5xx.c state->base->sku_type = MXL_HYDRA_SKU_TYPE_568; base 1768 drivers/media/dvb-frontends/mxl5xx.c state->base->can_clkout = 1; base 1769 drivers/media/dvb-frontends/mxl5xx.c state->base->demod_num = 4; base 1770 drivers/media/dvb-frontends/mxl5xx.c state->base->tuner_num = 3; base 1771 drivers/media/dvb-frontends/mxl5xx.c state->base->sku_type = MXL_HYDRA_SKU_TYPE_542; base 1772 drivers/media/dvb-frontends/mxl5xx.c state->base->ts_map = ts_map54x; base 1777 drivers/media/dvb-frontends/mxl5xx.c state->base->can_clkout = 0; base 1778 drivers/media/dvb-frontends/mxl5xx.c state->base->demod_num = 8; base 1779 drivers/media/dvb-frontends/mxl5xx.c state->base->tuner_num = 4; base 1780 drivers/media/dvb-frontends/mxl5xx.c state->base->sku_type = MXL_HYDRA_SKU_TYPE_584; base 1792 drivers/media/dvb-frontends/mxl5xx.c state->base->chipversion = 0; base 1794 drivers/media/dvb-frontends/mxl5xx.c state->base->chipversion = (chipver == 2) ? 2 : 1; base 1796 drivers/media/dvb-frontends/mxl5xx.c state->base->chipversion); base 1827 drivers/media/dvb-frontends/mxl5xx.c for (j = 0; j < state->base->demod_num; j++) { base 1842 drivers/media/dvb-frontends/mxl5xx.c struct mxl_base *base; base 1853 drivers/media/dvb-frontends/mxl5xx.c base = match_base(i2c, cfg->adr); base 1854 drivers/media/dvb-frontends/mxl5xx.c if (base) { base 1855 drivers/media/dvb-frontends/mxl5xx.c base->count++; base 1856 drivers/media/dvb-frontends/mxl5xx.c if (base->count > base->demod_num) base 1858 drivers/media/dvb-frontends/mxl5xx.c state->base = base; base 1860 drivers/media/dvb-frontends/mxl5xx.c base = kzalloc(sizeof(struct mxl_base), GFP_KERNEL); base 1861 drivers/media/dvb-frontends/mxl5xx.c if (!base) base 1863 drivers/media/dvb-frontends/mxl5xx.c base->i2c = i2c; base 1864 drivers/media/dvb-frontends/mxl5xx.c base->adr = cfg->adr; base 1865 drivers/media/dvb-frontends/mxl5xx.c base->type = cfg->type; base 1866 drivers/media/dvb-frontends/mxl5xx.c base->count = 1; base 1867 drivers/media/dvb-frontends/mxl5xx.c mutex_init(&base->i2c_lock); base 1868 drivers/media/dvb-frontends/mxl5xx.c mutex_init(&base->status_lock); base 1869 drivers/media/dvb-frontends/mxl5xx.c mutex_init(&base->tune_lock); base 1870 drivers/media/dvb-frontends/mxl5xx.c INIT_LIST_HEAD(&base->mxls); base 1872 drivers/media/dvb-frontends/mxl5xx.c state->base = base; base 1874 drivers/media/dvb-frontends/mxl5xx.c kfree(base); base 1877 drivers/media/dvb-frontends/mxl5xx.c list_add(&base->mxllist, &mxllist); base 1886 drivers/media/dvb-frontends/mxl5xx.c list_add(&state->mxl, &base->mxls); base 91 drivers/media/dvb-frontends/stv0910.c struct stv_base *base; base 143 drivers/media/dvb-frontends/stv0910.c struct i2c_adapter *adap = state->base->i2c; base 145 drivers/media/dvb-frontends/stv0910.c struct i2c_msg msg = {.addr = state->base->adr, .flags = 0, base 150 drivers/media/dvb-frontends/stv0910.c state->base->adr, reg, val); base 175 drivers/media/dvb-frontends/stv0910.c return i2c_read_regs16(state->base->i2c, state->base->adr, base 181 drivers/media/dvb-frontends/stv0910.c return i2c_read_regs16(state->base->i2c, state->base->adr, base 190 drivers/media/dvb-frontends/stv0910.c mutex_lock(&state->base->reg_lock); base 194 drivers/media/dvb-frontends/stv0910.c mutex_unlock(&state->base->reg_lock); base 502 drivers/media/dvb-frontends/stv0910.c symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32); base 805 drivers/media/dvb-frontends/stv0910.c u32 quartz = state->base->extclk / 1000000; base 859 drivers/media/dvb-frontends/stv0910.c state->base->mclk = fvco / (2 * odf) * 1000000; base 1058 drivers/media/dvb-frontends/stv0910.c symb = muldiv32(p->symbol_rate, 65536, state->base->mclk); base 1110 drivers/media/dvb-frontends/stv0910.c freq = (freq << 16) / (state->base->mclk / 1000); base 1138 drivers/media/dvb-frontends/stv0910.c u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32)); base 1248 drivers/media/dvb-frontends/stv0910.c mutex_lock(&state->base->i2c_lock); base 1257 drivers/media/dvb-frontends/stv0910.c if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock))) base 1258 drivers/media/dvb-frontends/stv0910.c mutex_unlock(&state->base->i2c_lock); base 1259 drivers/media/dvb-frontends/stv0910.c dev_err(&state->base->i2c->dev, base 1268 drivers/media/dvb-frontends/stv0910.c if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock))) base 1269 drivers/media/dvb-frontends/stv0910.c mutex_unlock(&state->base->i2c_lock); base 1277 drivers/media/dvb-frontends/stv0910.c state->base->count--; base 1278 drivers/media/dvb-frontends/stv0910.c if (state->base->count == 0) { base 1279 drivers/media/dvb-frontends/stv0910.c list_del(&state->base->stvlist); base 1280 drivers/media/dvb-frontends/stv0910.c kfree(state->base); base 1781 drivers/media/dvb-frontends/stv0910.c struct stv_base *base; base 1800 drivers/media/dvb-frontends/stv0910.c base = match_base(i2c, cfg->adr); base 1801 drivers/media/dvb-frontends/stv0910.c if (base) { base 1802 drivers/media/dvb-frontends/stv0910.c base->count++; base 1803 drivers/media/dvb-frontends/stv0910.c state->base = base; base 1805 drivers/media/dvb-frontends/stv0910.c base = kzalloc(sizeof(*base), GFP_KERNEL); base 1806 drivers/media/dvb-frontends/stv0910.c if (!base) base 1808 drivers/media/dvb-frontends/stv0910.c base->i2c = i2c; base 1809 drivers/media/dvb-frontends/stv0910.c base->adr = cfg->adr; base 1810 drivers/media/dvb-frontends/stv0910.c base->count = 1; base 1811 drivers/media/dvb-frontends/stv0910.c base->extclk = cfg->clk ? cfg->clk : 30000000; base 1813 drivers/media/dvb-frontends/stv0910.c mutex_init(&base->i2c_lock); base 1814 drivers/media/dvb-frontends/stv0910.c mutex_init(&base->reg_lock); base 1815 drivers/media/dvb-frontends/stv0910.c state->base = base; base 1819 drivers/media/dvb-frontends/stv0910.c kfree(base); base 1822 drivers/media/dvb-frontends/stv0910.c list_add(&base->stvlist, &stvlist); base 591 drivers/media/i2c/adv748x/adv748x-core.c if (vep.base.port == ADV748X_PORT_TXA) { base 602 drivers/media/i2c/adv748x/adv748x-core.c if (vep.base.port == ADV748X_PORT_TXB) { base 76 drivers/media/i2c/mt9t112.c #define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff)) base 2154 drivers/media/pci/bt8xx/bttv-driver.c if (NULL != btv->fbuf.base) base 2544 drivers/media/pci/bt8xx/bttv-driver.c if (unlikely(!btv->fbuf.base)) { base 2607 drivers/media/pci/bt8xx/bttv-driver.c btv->fbuf.base = fb->base; base 266 drivers/media/pci/bt8xx/bttv-risc.c addr = (unsigned long)btv->fbuf.base; base 173 drivers/media/pci/ddbridge/ddbridge-core.c u32 i, base; base 177 drivers/media/pci/ddbridge/ddbridge-core.c base = sdma->bufregs; base 180 drivers/media/pci/ddbridge/ddbridge-core.c ddbwritel(dev, mem & 0xffffffff, base + i * 8); base 181 drivers/media/pci/ddbridge/ddbridge-core.c ddbwritel(dev, mem >> 32, base + i * 8 + 4); base 2262 drivers/media/pci/ddbridge/ddbridge-core.c dma->regs = rm->odma->base + rm->odma->size * nr; base 2263 drivers/media/pci/ddbridge/ddbridge-core.c dma->bufregs = rm->odma_buf->base + rm->odma_buf->size * nr; base 2269 drivers/media/pci/ddbridge/ddbridge-core.c dma->regs = rm->idma->base + rm->idma->size * nr; base 2270 drivers/media/pci/ddbridge/ddbridge-core.c dma->bufregs = rm->idma_buf->base + rm->idma_buf->size * nr; base 2291 drivers/media/pci/ddbridge/ddbridge-core.c (rm->input->base + rm->input->size * nr); base 2297 drivers/media/pci/ddbridge/ddbridge-core.c u32 base = rm0->irq_base_idma; base 2304 drivers/media/pci/ddbridge/ddbridge-core.c port->lnr, nr, dma_nr + base); base 2306 drivers/media/pci/ddbridge/ddbridge-core.c ddb_irq_set(dev, 0, dma_nr + base, &input_handler, input); base 2322 drivers/media/pci/ddbridge/ddbridge-core.c (rm->output->base + rm->output->size * nr); base 2329 drivers/media/pci/ddbridge/ddbridge-core.c u32 base = rm0->irq_base_odma; base 2331 drivers/media/pci/ddbridge/ddbridge-core.c ddb_irq_set(dev, 0, nr + base, &output_handler, output); base 25 drivers/media/pci/ddbridge/ddbridge-hw.c .base = 0x200, base 31 drivers/media/pci/ddbridge/ddbridge-hw.c .base = 0x280, base 37 drivers/media/pci/ddbridge/ddbridge-hw.c .base = 0x300, base 43 drivers/media/pci/ddbridge/ddbridge-hw.c .base = 0x2000, base 49 drivers/media/pci/ddbridge/ddbridge-hw.c .base = 0x380, base 55 drivers/media/pci/ddbridge/ddbridge-hw.c .base = 0x2800, base 61 drivers/media/pci/ddbridge/ddbridge-hw.c .base = 0x80, base 67 drivers/media/pci/ddbridge/ddbridge-hw.c .base = 0x1000, base 171 drivers/media/pci/ddbridge/ddbridge-i2c.c (regmap->i2c_buf->base + i2c->bsize * i); base 174 drivers/media/pci/ddbridge/ddbridge-i2c.c (regmap->i2c->base + regmap->i2c->size * i); base 200 drivers/media/pci/ddbridge/ddbridge-i2c.c u32 i, j, num = 0, l, base; base 211 drivers/media/pci/ddbridge/ddbridge-i2c.c base = regmap->irq_base_i2c; base 216 drivers/media/pci/ddbridge/ddbridge-i2c.c ddb_irq_set(dev, l, i + base, i2c_handler, i2c); base 27 drivers/media/pci/ddbridge/ddbridge-mci.c struct ddb_link *link = state->base->link; base 53 drivers/media/pci/ddbridge/ddbridge-mci.c struct ddb_link *link = state->base->link; base 65 drivers/media/pci/ddbridge/ddbridge-mci.c struct ddb_link *link = state->base->link; base 78 drivers/media/pci/ddbridge/ddbridge-mci.c stat = wait_for_completion_timeout(&state->base->completion, HZ); base 80 drivers/media/pci/ddbridge/ddbridge-mci.c dev_warn(state->base->dev, "MCI-%d: MCI timeout\n", state->nr); base 95 drivers/media/pci/ddbridge/ddbridge-mci.c mutex_lock(&state->base->mci_lock); base 99 drivers/media/pci/ddbridge/ddbridge-mci.c mutex_unlock(&state->base->mci_lock); base 105 drivers/media/pci/ddbridge/ddbridge-mci.c struct mci_base *base = (struct mci_base *)priv; base 107 drivers/media/pci/ddbridge/ddbridge-mci.c complete(&base->completion); base 133 drivers/media/pci/ddbridge/ddbridge-mci.c struct mci_base *base; base 141 drivers/media/pci/ddbridge/ddbridge-mci.c base = match_base(key); base 142 drivers/media/pci/ddbridge/ddbridge-mci.c if (base) { base 143 drivers/media/pci/ddbridge/ddbridge-mci.c base->count++; base 144 drivers/media/pci/ddbridge/ddbridge-mci.c state->base = base; base 146 drivers/media/pci/ddbridge/ddbridge-mci.c base = kzalloc(cfg->base_size, GFP_KERNEL); base 147 drivers/media/pci/ddbridge/ddbridge-mci.c if (!base) base 149 drivers/media/pci/ddbridge/ddbridge-mci.c base->key = key; base 150 drivers/media/pci/ddbridge/ddbridge-mci.c base->count = 1; base 151 drivers/media/pci/ddbridge/ddbridge-mci.c base->link = link; base 152 drivers/media/pci/ddbridge/ddbridge-mci.c base->dev = dev->dev; base 153 drivers/media/pci/ddbridge/ddbridge-mci.c mutex_init(&base->mci_lock); base 154 drivers/media/pci/ddbridge/ddbridge-mci.c mutex_init(&base->tuner_lock); base 155 drivers/media/pci/ddbridge/ddbridge-mci.c ddb_irq_set(dev, link->nr, 0, mci_handler, base); base 156 drivers/media/pci/ddbridge/ddbridge-mci.c init_completion(&base->completion); base 157 drivers/media/pci/ddbridge/ddbridge-mci.c state->base = base; base 159 drivers/media/pci/ddbridge/ddbridge-mci.c kfree(base); base 162 drivers/media/pci/ddbridge/ddbridge-mci.c list_add(&base->mci_list, &mci_list); base 164 drivers/media/pci/ddbridge/ddbridge-mci.c cfg->base_init(base); base 234 drivers/media/pci/ddbridge/ddbridge-mci.h struct mci_base *base; base 58 drivers/media/pci/ddbridge/ddbridge-sx8.c struct mci_base *mci_base = state->mci.base; base 136 drivers/media/pci/ddbridge/ddbridge-sx8.c struct mci_base *mci_base = state->mci.base; base 150 drivers/media/pci/ddbridge/ddbridge-sx8.c struct mci_base *mci_base = state->mci.base; base 186 drivers/media/pci/ddbridge/ddbridge-sx8.c struct mci_base *mci_base = state->mci.base; base 313 drivers/media/pci/ddbridge/ddbridge-sx8.c struct mci_base *mci_base = state->mci.base; base 441 drivers/media/pci/ddbridge/ddbridge-sx8.c struct mci_base *mci_base = state->mci.base; base 71 drivers/media/pci/ddbridge/ddbridge.h u32 base; base 359 drivers/media/pci/intel/ipu3/ipu3-cio2.c void __iomem *const base = cio2->base; base 389 drivers/media/pci/intel/ipu3/ipu3-cio2.c CIO2_PBM_WMCTRL1_MID2_2CK, base + CIO2_REG_PBM_WMCTRL1); base 395 drivers/media/pci/intel/ipu3/ipu3-cio2.c CIO2_PBM_WMCTRL2_OBFF_MEM_EN, base + CIO2_REG_PBM_WMCTRL2); base 403 drivers/media/pci/intel/ipu3/ipu3-cio2.c base + CIO2_REG_PBM_ARB_CTRL); base 409 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(CIO2_FB_HPLL_FREQ, base + CIO2_REG_FB_HPLL_FREQ); base 410 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(CIO2_ISCLK_RATIO, base + CIO2_REG_ISCLK_RATIO); base 423 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(CIO2_INT_EN_EXT_IE_MASK, base + CIO2_REG_INT_EN_EXT_IE); base 428 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(CIO2_INT_EN_EXT_OE_MASK, base + CIO2_REG_INT_EN_EXT_OE); base 432 drivers/media/pci/intel/ipu3/ipu3-cio2.c base + CIO2_REG_INT_EN); base 436 drivers/media/pci/intel/ipu3/ipu3-cio2.c base + CIO2_REG_PXM_PXF_FMT_CFG0(csi2bus)); base 443 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(0, base + CIO2_REG_PXM_SID2BID0(csi2bus)); base 458 drivers/media/pci/intel/ipu3/ipu3-cio2.c << CIO2_CGC_CSI_CLKGATE_HOLDOFF_SHIFT, base + CIO2_REG_CGC); base 459 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(CIO2_LTRCTRL_LTRDYNEN, base + CIO2_REG_LTRCTRL); base 464 drivers/media/pci/intel/ipu3/ipu3-cio2.c base + CIO2_REG_LTRVAL01); base 469 drivers/media/pci/intel/ipu3/ipu3-cio2.c base + CIO2_REG_LTRVAL23); base 472 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(0, base + CIO2_REG_CDMABA(i)); base 473 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(0, base + CIO2_REG_CDMAC0(i)); base 474 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(0, base + CIO2_REG_CDMAC1(i)); base 479 drivers/media/pci/intel/ipu3/ipu3-cio2.c base + CIO2_REG_CDMABA(CIO2_DMA_CHAN)); base 487 drivers/media/pci/intel/ipu3/ipu3-cio2.c CIO2_CDMAC0_DMA_HALTED, base + CIO2_REG_CDMAC0(CIO2_DMA_CHAN)); base 490 drivers/media/pci/intel/ipu3/ipu3-cio2.c base + CIO2_REG_CDMAC1(CIO2_DMA_CHAN)); base 492 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(0, base + CIO2_REG_PBM_FOPN_ABORT); base 498 drivers/media/pci/intel/ipu3/ipu3-cio2.c base + CIO2_REG_PXM_FRF_CFG(q->csi2.port)); base 502 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(~0, base + CIO2_REG_INT_STS_EXT_OE); base 503 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(~0, base + CIO2_REG_INT_STS_EXT_IE); base 504 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(~0, base + CIO2_REG_INT_STS); base 515 drivers/media/pci/intel/ipu3/ipu3-cio2.c void __iomem *base = cio2->base; base 525 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(0, base + CIO2_REG_CDMAC0(CIO2_DMA_CHAN)); base 527 drivers/media/pci/intel/ipu3/ipu3-cio2.c if (readl(base + CIO2_REG_CDMAC0(CIO2_DMA_CHAN)) & base 537 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(readl(base + CIO2_REG_PXM_FRF_CFG(i)) | base 538 drivers/media/pci/intel/ipu3/ipu3-cio2.c CIO2_PXM_FRF_CFG_ABORT, base + CIO2_REG_PXM_FRF_CFG(i)); base 539 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(readl(base + CIO2_REG_PBM_FOPN_ABORT) | base 540 drivers/media/pci/intel/ipu3/ipu3-cio2.c CIO2_PBM_FOPN_ABORT(i), base + CIO2_REG_PBM_FOPN_ABORT); base 643 drivers/media/pci/intel/ipu3/ipu3-cio2.c void __iomem *const base = cio2->base; base 654 drivers/media/pci/intel/ipu3/ipu3-cio2.c oe_clear = readl(base + CIO2_REG_INT_STS_EXT_OE); base 669 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(oe_clear, base + CIO2_REG_INT_STS_EXT_OE); base 709 drivers/media/pci/intel/ipu3/ipu3-cio2.c ie_clear = readl(base + CIO2_REG_INT_STS_EXT_IE); base 716 drivers/media/pci/intel/ipu3/ipu3-cio2.c base + CIO2_REG_PIPE_BASE(port); base 755 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(ie_clear, base + CIO2_REG_INT_STS_EXT_IE); base 770 drivers/media/pci/intel/ipu3/ipu3-cio2.c void __iomem *const base = cio2->base; base 774 drivers/media/pci/intel/ipu3/ipu3-cio2.c int_status = readl(base + CIO2_REG_INT_STS); base 780 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(int_status, base + CIO2_REG_INT_STS); base 782 drivers/media/pci/intel/ipu3/ipu3-cio2.c int_status = readl(base + CIO2_REG_INT_STS); base 927 drivers/media/pci/intel/ipu3/ipu3-cio2.c fbpt_rp = (readl(cio2->base + CIO2_REG_CDMARI(CIO2_DMA_CHAN)) base 1412 drivers/media/pci/intel/ipu3/ipu3-cio2.c q->csi_rx_base = cio2->base + CIO2_REG_PIPE_BASE(q->csi2.port); base 1507 drivers/media/pci/intel/ipu3/ipu3-cio2.c s_asd->csi2.port = vep.base.port; base 1775 drivers/media/pci/intel/ipu3/ipu3-cio2.c cio2->base = iomap[CIO2_PCI_BAR]; base 1874 drivers/media/pci/intel/ipu3/ipu3-cio2.c void __iomem *const base = cio2->base; base 1877 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(CIO2_D0I3C_I3, base + CIO2_REG_D0I3C); base 1892 drivers/media/pci/intel/ipu3/ipu3-cio2.c void __iomem *const base = cio2->base; base 1895 drivers/media/pci/intel/ipu3/ipu3-cio2.c writel(CIO2_D0I3C_RR, base + CIO2_REG_D0I3C); base 356 drivers/media/pci/intel/ipu3/ipu3-cio2.h void __iomem *base; base 1414 drivers/media/pci/ivtv/ivtv-ioctl.c fb->base = (void *)itv->osd_video_pbase; base 27 drivers/media/pci/pt3/pt3_dma.c u32 base; base 31 drivers/media/pci/pt3/pt3_dma.c base = get_dma_base(adap->adap_idx); base 32 drivers/media/pci/pt3/pt3_dma.c stat = ioread32(pt3->regs[0] + base + OFST_STATUS); base 36 drivers/media/pci/pt3/pt3_dma.c iowrite32(0x02, pt3->regs[0] + base + OFST_DMA_CTL); base 38 drivers/media/pci/pt3/pt3_dma.c stat = ioread32(pt3->regs[0] + base + OFST_STATUS); base 49 drivers/media/pci/pt3/pt3_dma.c u32 base = get_dma_base(adap->adap_idx); base 51 drivers/media/pci/pt3/pt3_dma.c iowrite32(0x02, pt3->regs[0] + base + OFST_DMA_CTL); base 53 drivers/media/pci/pt3/pt3_dma.c pt3->regs[0] + base + OFST_DMA_DESC_L); base 55 drivers/media/pci/pt3/pt3_dma.c pt3->regs[0] + base + OFST_DMA_DESC_H); base 56 drivers/media/pci/pt3/pt3_dma.c iowrite32(0x01, pt3->regs[0] + base + OFST_DMA_CTL); base 211 drivers/media/pci/saa7134/saa7134-core.c unsigned long base; base 214 drivers/media/pci/saa7134/saa7134-core.c base = saa7134_buffer_startpage(buf) * 4096; base 215 drivers/media/pci/saa7134/saa7134-core.c base += dma->sgl[0].offset; base 216 drivers/media/pci/saa7134/saa7134-core.c return base; base 74 drivers/media/pci/saa7134/saa7134-vbi.c unsigned long control, base; base 85 drivers/media/pci/saa7134/saa7134-vbi.c base = saa7134_buffer_base(buf); base 89 drivers/media/pci/saa7134/saa7134-vbi.c saa_writel(SAA7134_RS_BA1(2), base); base 90 drivers/media/pci/saa7134/saa7134-vbi.c saa_writel(SAA7134_RS_BA2(2), base + dev->vbi_hlen * dev->vbi_vlen); base 93 drivers/media/pci/saa7134/saa7134-vbi.c saa_writel(SAA7134_RS_BA1(3), base); base 94 drivers/media/pci/saa7134/saa7134-vbi.c saa_writel(SAA7134_RS_BA2(3), base + dev->vbi_hlen * dev->vbi_vlen); base 661 drivers/media/pci/saa7134/saa7134-video.c if (!try && (dev->ovbuf.base == NULL || dev->ovfmt == NULL)) base 701 drivers/media/pci/saa7134/saa7134-video.c unsigned long base,control,bpl; base 726 drivers/media/pci/saa7134/saa7134-video.c base = (unsigned long)dev->ovbuf.base; base 727 drivers/media/pci/saa7134/saa7134-video.c base += dev->ovbuf.fmt.bytesperline * dev->win.w.top; base 728 drivers/media/pci/saa7134/saa7134-video.c base += dev->ovfmt->depth/8 * dev->win.w.left; base 736 drivers/media/pci/saa7134/saa7134-video.c saa_writel(SAA7134_RS_BA1(1),base); base 737 drivers/media/pci/saa7134/saa7134-video.c saa_writel(SAA7134_RS_BA2(1),base+bpl); base 741 drivers/media/pci/saa7134/saa7134-video.c saa_writel(SAA7134_RS_BA1(1),base); base 742 drivers/media/pci/saa7134/saa7134-video.c saa_writel(SAA7134_RS_BA2(1),base); base 825 drivers/media/pci/saa7134/saa7134-video.c unsigned long base,control,bpl; base 840 drivers/media/pci/saa7134/saa7134-video.c base = saa7134_buffer_base(buf); base 854 drivers/media/pci/saa7134/saa7134-video.c saa_writel(SAA7134_RS_BA1(0),base); base 855 drivers/media/pci/saa7134/saa7134-video.c saa_writel(SAA7134_RS_BA2(0),base+bpl); base 859 drivers/media/pci/saa7134/saa7134-video.c saa_writel(SAA7134_RS_BA1(0),base); base 860 drivers/media/pci/saa7134/saa7134-video.c saa_writel(SAA7134_RS_BA2(0),base); base 869 drivers/media/pci/saa7134/saa7134-video.c base2 = base + bpl * dev->height; base 165 drivers/media/pci/solo6x10/solo6x10-gpio.c solo_dev->gpio_dev.base = -1; base 204 drivers/media/pci/solo6x10/solo6x10-p2m.c static int solo_p2m_test(struct solo_dev *solo_dev, int base, int size) base 230 drivers/media/pci/solo6x10/solo6x10-p2m.c if (solo_p2m_dma(solo_dev, 1, wr_buf, base, size, 0, 0)) base 233 drivers/media/pci/solo6x10/solo6x10-p2m.c if (solo_p2m_dma(solo_dev, 0, rd_buf, base, size, 0, 0)) base 310 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c unsigned int base, unsigned int base_size) base 345 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c solo_p2m_fill_desc(desc, 0, dma, base + off, base 354 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c ret = solo_p2m_dma_t(solo_dev, 0, dma, base + off, base 359 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c ret = solo_p2m_dma_t(solo_dev, 0, dma + left, base, base 1099 drivers/media/pci/ttpci/av7110.c uint64_t *stc, unsigned int *base) base 1128 drivers/media/pci/ttpci/av7110.c *base = 1; base 139 drivers/media/pci/ttpci/av7110_hw.c u32 base, bootblock = AV7110_BOOT_BLOCK; base 145 drivers/media/pci/ttpci/av7110_hw.c base = DRAM_START_CODE; base 156 drivers/media/pci/ttpci/av7110_hw.c iwdebi(av7110, DEBISWAB, AV7110_BOOT_BASE, swab32(base), 4); base 159 drivers/media/pci/ttpci/av7110_hw.c base += AV7110_BOOT_MAX_SIZE; base 174 drivers/media/pci/ttpci/av7110_hw.c iwdebi(av7110, DEBISWAB, AV7110_BOOT_BASE, swab32(base), 4); base 208 drivers/media/platform/aspeed-video.c void __iomem *base; base 382 drivers/media/platform/aspeed-video.c unsigned int base; base 385 drivers/media/platform/aspeed-video.c base = 256 * i; /* AST HW requires this header spacing */ base 386 drivers/media/platform/aspeed-video.c memcpy(&table[base], aspeed_video_jpeg_header, base 389 drivers/media/platform/aspeed-video.c base += ASPEED_VIDEO_JPEG_HEADER_SIZE; base 390 drivers/media/platform/aspeed-video.c memcpy(&table[base], aspeed_video_jpeg_dct[i], base 393 drivers/media/platform/aspeed-video.c base += ASPEED_VIDEO_JPEG_DCT_SIZE; base 394 drivers/media/platform/aspeed-video.c memcpy(&table[base], aspeed_video_jpeg_quant, base 398 drivers/media/platform/aspeed-video.c table[base + 2] = 0x00220103; base 405 drivers/media/platform/aspeed-video.c u32 t = readl(video->base + reg); base 410 drivers/media/platform/aspeed-video.c writel(t, video->base + reg); base 412 drivers/media/platform/aspeed-video.c readl(video->base + reg)); base 417 drivers/media/platform/aspeed-video.c u32 t = readl(video->base + reg); base 425 drivers/media/platform/aspeed-video.c writel(val, video->base + reg); base 427 drivers/media/platform/aspeed-video.c readl(video->base + reg)); base 1677 drivers/media/platform/aspeed-video.c video->base = devm_ioremap_resource(video->dev, res); base 1679 drivers/media/platform/aspeed-video.c if (IS_ERR(video->base)) base 1680 drivers/media/platform/aspeed-video.c return PTR_ERR(video->base); base 67 drivers/media/platform/cadence/cdns-csi2rx.c void __iomem *base; base 98 drivers/media/platform/cadence/cdns-csi2rx.c csi2rx->base + CSI2RX_SOFT_RESET_REG); base 102 drivers/media/platform/cadence/cdns-csi2rx.c writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); base 137 drivers/media/platform/cadence/cdns-csi2rx.c writel(reg, csi2rx->base + CSI2RX_STATIC_CFG_REG); base 159 drivers/media/platform/cadence/cdns-csi2rx.c csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); base 163 drivers/media/platform/cadence/cdns-csi2rx.c csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i)); base 166 drivers/media/platform/cadence/cdns-csi2rx.c csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); base 195 drivers/media/platform/cadence/cdns-csi2rx.c writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); base 288 drivers/media/platform/cadence/cdns-csi2rx.c csi2rx->base = devm_ioremap_resource(&pdev->dev, res); base 289 drivers/media/platform/cadence/cdns-csi2rx.c if (IS_ERR(csi2rx->base)) base 290 drivers/media/platform/cadence/cdns-csi2rx.c return PTR_ERR(csi2rx->base); base 320 drivers/media/platform/cadence/cdns-csi2rx.c dev_cfg = readl(csi2rx->base + CSI2RX_DEVICE_CFG_REG); base 101 drivers/media/platform/cadence/cdns-csi2tx.c void __iomem *base; base 236 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG); base 253 drivers/media/platform/cadence/cdns-csi2tx.c writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); base 260 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx->base + CSI2TX_DPHY_CFG_REG); base 275 drivers/media/platform/cadence/cdns-csi2tx.c writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); base 289 drivers/media/platform/cadence/cdns-csi2tx.c writel(reg, csi2tx->base + CSI2TX_V2_DPHY_CFG_REG); base 296 drivers/media/platform/cadence/cdns-csi2tx.c writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG); base 309 drivers/media/platform/cadence/cdns-csi2tx.c writel(CSI2TX_CONFIG_CFG_REQ, csi2tx->base + CSI2TX_CONFIG_REG); base 364 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx->base + CSI2TX_DT_CFG_REG(stream)); base 368 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx->base + CSI2TX_DT_FORMAT_REG(stream)); base 375 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx->base + CSI2TX_STREAM_IF_CFG_REG(stream)); base 379 drivers/media/platform/cadence/cdns-csi2tx.c writel(0, csi2tx->base + CSI2TX_CONFIG_REG); base 387 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx->base + CSI2TX_CONFIG_REG); base 441 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx->base = devm_ioremap_resource(&pdev->dev, res); base 442 drivers/media/platform/cadence/cdns-csi2tx.c if (IS_ERR(csi2tx->base)) base 443 drivers/media/platform/cadence/cdns-csi2tx.c return PTR_ERR(csi2tx->base); base 458 drivers/media/platform/cadence/cdns-csi2tx.c dev_cfg = readl(csi2tx->base + CSI2TX_DEVICE_CONFIG_REG); base 25 drivers/media/platform/davinci/ccdc_hw_device.h void (*set_ccdc_base)(void *base, int size); base 242 drivers/media/platform/exynos4-is/fimc-is.c buf = is->memory.vaddr + is->setfile.base; base 257 drivers/media/platform/exynos4-is/fimc-is.c is->setfile.base, fw->size); base 558 drivers/media/platform/exynos4-is/fimc-is.c is->setfile.base = is->i2h_cmd.args[1]; base 677 drivers/media/platform/exynos4-is/fimc-is.c pr_debug("setfile.base: %#x\n", is->setfile.base); base 691 drivers/media/platform/exynos4-is/fimc-is.c is->setfile.base, is->setfile.size); base 148 drivers/media/platform/exynos4-is/fimc-is.h u32 base; base 218 drivers/media/platform/exynos4-is/fimc-is.h u32 base; base 403 drivers/media/platform/exynos4-is/media-dev.c if (WARN_ON(endpoint.base.port == 0) || index >= FIMC_MAX_SENSORS) { base 408 drivers/media/platform/exynos4-is/media-dev.c pd->mux_id = (endpoint.base.port - 1) & 0x1; base 418 drivers/media/platform/exynos4-is/media-dev.c if (fimc_input_is_parallel(endpoint.base.port)) { base 424 drivers/media/platform/exynos4-is/media-dev.c } else if (fimc_input_is_mipi_csi(endpoint.base.port)) { base 432 drivers/media/platform/exynos4-is/media-dev.c endpoint.base.port, rem); base 739 drivers/media/platform/exynos4-is/mipi-csis.c state->index = endpoint.base.port - FIMC_INPUT_MIPI_CSI2_0; base 664 drivers/media/platform/fsl-viu.c if (dev->ovbuf.base == NULL) base 743 drivers/media/platform/fsl-viu.c reg_val.field_base_addr = (u32)(long)dev->ovbuf.base; base 324 drivers/media/platform/marvell-ccic/mcam-core.c unsigned frame, dma_addr_t base) base 330 drivers/media/platform/marvell-ccic/mcam-core.c y = base; base 637 drivers/media/platform/meson/ao-cec-g12a.c void __iomem *base; base 668 drivers/media/platform/meson/ao-cec-g12a.c base = devm_ioremap_resource(&pdev->dev, res); base 669 drivers/media/platform/meson/ao-cec-g12a.c if (IS_ERR(base)) { base 670 drivers/media/platform/meson/ao-cec-g12a.c ret = PTR_ERR(base); base 674 drivers/media/platform/meson/ao-cec-g12a.c ao_cec->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 220 drivers/media/platform/meson/ao-cec.c void __iomem *base; base 235 drivers/media/platform/meson/ao-cec.c while (readl_relaxed(ao_cec->base + CEC_RW_REG) & CEC_RW_BUS_BUSY) { base 260 drivers/media/platform/meson/ao-cec.c writel_relaxed(reg, ao_cec->base + CEC_RW_REG); base 267 drivers/media/platform/meson/ao-cec.c readl_relaxed(ao_cec->base + CEC_RW_REG)); base 295 drivers/media/platform/meson/ao-cec.c writel_relaxed(reg, ao_cec->base + CEC_RW_REG); base 310 drivers/media/platform/meson/ao-cec.c ao_cec->base + CEC_INTR_MASKN_REG); base 374 drivers/media/platform/meson/ao-cec.c u32 stat = readl_relaxed(ao_cec->base + CEC_INTR_STAT_REG); base 412 drivers/media/platform/meson/ao-cec.c writel_relaxed(CEC_INTR_TX, ao_cec->base + CEC_INTR_CLR_REG); base 460 drivers/media/platform/meson/ao-cec.c writel_relaxed(CEC_INTR_RX, ao_cec->base + CEC_INTR_CLR_REG); base 474 drivers/media/platform/meson/ao-cec.c u32 stat = readl_relaxed(ao_cec->base + CEC_INTR_STAT_REG); base 551 drivers/media/platform/meson/ao-cec.c ao_cec->base + CEC_GEN_CNTL_REG); base 560 drivers/media/platform/meson/ao-cec.c ao_cec->base + CEC_GEN_CNTL_REG); base 566 drivers/media/platform/meson/ao-cec.c ao_cec->base + CEC_GEN_CNTL_REG); base 630 drivers/media/platform/meson/ao-cec.c ao_cec->base = devm_ioremap_resource(&pdev->dev, res); base 631 drivers/media/platform/meson/ao-cec.c if (IS_ERR(ao_cec->base)) { base 632 drivers/media/platform/meson/ao-cec.c ret = PTR_ERR(ao_cec->base); base 683 drivers/media/platform/meson/ao-cec.c ao_cec->base + CEC_GEN_CNTL_REG); base 192 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c u32 mtk_jpeg_dec_get_int_status(void __iomem *base) base 196 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c ret = readl(base + JPGDEC_REG_INTERRUPT_STATUS) & BIT_INQST_MASK_ALLIRQ; base 198 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(ret, base + JPGDEC_REG_INTERRUPT_STATUS); base 219 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c void mtk_jpeg_dec_start(void __iomem *base) base 221 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(0, base + JPGDEC_REG_TRIG); base 224 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_soft_reset(void __iomem *base) base 226 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(0x0000FFFF, base + JPGDEC_REG_INTERRUPT_STATUS); base 227 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(0x00, base + JPGDEC_REG_RESET); base 228 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(0x01, base + JPGDEC_REG_RESET); base 231 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_hard_reset(void __iomem *base) base 233 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(0x00, base + JPGDEC_REG_RESET); base 234 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(0x10, base + JPGDEC_REG_RESET); base 237 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c void mtk_jpeg_dec_reset(void __iomem *base) base 239 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_soft_reset(base); base 240 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_hard_reset(base); base 243 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w, base 250 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(val, base + JPGDEC_REG_BRZ_FACTOR); base 253 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, u32 addr_y, base 257 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(addr_y, base + JPGDEC_REG_DEST_ADDR0_Y); base 259 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(addr_u, base + JPGDEC_REG_DEST_ADDR0_U); base 261 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(addr_v, base + JPGDEC_REG_DEST_ADDR0_V); base 264 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, u32 addr_y, base 267 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(addr_y, base + JPGDEC_REG_DEST_ADDR1_Y); base 268 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(addr_u, base + JPGDEC_REG_DEST_ADDR1_U); base 269 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(addr_v, base + JPGDEC_REG_DEST_ADDR1_V); base 272 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_mem_stride(void __iomem *base, u32 stride_y, base 275 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel((stride_y & 0xFFFF), base + JPGDEC_REG_STRIDE_Y); base 276 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel((stride_uv & 0xFFFF), base + JPGDEC_REG_STRIDE_UV); base 279 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_img_stride(void __iomem *base, u32 stride_y, base 282 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel((stride_y & 0xFFFF), base + JPGDEC_REG_IMG_STRIDE_Y); base 283 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel((stride_uv & 0xFFFF), base + JPGDEC_REG_IMG_STRIDE_UV); base 286 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_pause_mcu_idx(void __iomem *base, u32 idx) base 288 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(idx & 0x0003FFFFFF, base + JPGDEC_REG_PAUSE_MCU_NUM); base 291 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_dec_mode(void __iomem *base, u32 mode) base 293 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(mode & 0x03, base + JPGDEC_REG_OPERATION_MODE); base 296 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, u32 ptr) base 299 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(ptr, base + JPGDEC_REG_FILE_BRP); base 302 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_bs_info(void __iomem *base, u32 addr, u32 size) base 306 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(addr, base + JPGDEC_REG_FILE_ADDR); base 307 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(size, base + JPGDEC_REG_FILE_TOTAL_SIZE); base 310 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_comp_id(void __iomem *base, u32 id_y, u32 id_u, base 317 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(val, base + JPGDEC_REG_COMP_ID); base 320 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_total_mcu(void __iomem *base, u32 num) base 322 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(num - 1, base + JPGDEC_REG_TOTAL_MCU_NUM); base 325 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_comp0_du(void __iomem *base, u32 num) base 327 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(num - 1, base + JPGDEC_REG_COMP0_DATA_UNIT_NUM); base 330 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_du_membership(void __iomem *base, u32 member, base 336 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(member, base + JPGDEC_REG_DU_CTRL); base 339 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_q_table(void __iomem *base, u32 id0, u32 id1, base 345 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(val, base + JPGDEC_REG_QT_ID); base 348 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_dma_group(void __iomem *base, u32 mcu_group, base 356 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(val, base + JPGDEC_REG_WDMA_CTRL); base 359 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static void mtk_jpeg_dec_set_sampling_factor(void __iomem *base, u32 comp_num, base 372 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c writel(val, base + JPGDEC_REG_DU_NUM); base 375 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c void mtk_jpeg_dec_set_config(void __iomem *base, base 380 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_brz_factor(base, 0, 0, config->uv_brz_w, 0); base 381 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_dec_mode(base, 0); base 382 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_comp0_du(base, config->unit_num); base 383 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_total_mcu(base, config->total_mcu); base 384 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_bs_info(base, bs->str_addr, bs->size); base 385 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_bs_write_ptr(base, bs->end_addr); base 386 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_du_membership(base, config->membership, 1, base 388 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_comp_id(base, config->comp_id[0], config->comp_id[1], base 390 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_q_table(base, config->qtbl_num[0], base 392 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_sampling_factor(base, config->comp_num, base 399 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_mem_stride(base, config->mem_stride[0], base 401 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_img_stride(base, config->img_stride[0], base 403 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_dst_bank0(base, fb->plane_addr[0], base 405 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_dst_bank1(base, 0, 0, 0); base 406 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_dma_group(base, config->dma_mcu, config->dma_group, base 408 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c mtk_jpeg_dec_set_pause_mcu_idx(base, config->total_mcu); base 76 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.h void mtk_jpeg_dec_set_config(void __iomem *base, base 1216 drivers/media/platform/omap/omap_vout.c a->base = vout->fbuf.base; base 1479 drivers/media/platform/omap/omap_vout.c vout->fbuf.base = (void *)info.paddr; base 705 drivers/media/platform/pxa_camera.c void __iomem *base; base 960 drivers/media/platform/pxa_camera.c __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR); base 962 drivers/media/platform/pxa_camera.c cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; base 964 drivers/media/platform/pxa_camera.c __raw_writel(cicr0, pcdev->base + CICR0); base 973 drivers/media/platform/pxa_camera.c cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; base 974 drivers/media/platform/pxa_camera.c __raw_writel(cicr0, pcdev->base + CICR0); base 1049 drivers/media/platform/pxa_camera.c camera_status = __raw_readl(pcdev->base + CISR); base 1151 drivers/media/platform/pxa_camera.c __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); base 1159 drivers/media/platform/pxa_camera.c __raw_writel(0x3ff, pcdev->base + CICR0); base 1172 drivers/media/platform/pxa_camera.c __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); base 1197 drivers/media/platform/pxa_camera.c __raw_readl(pcdev->base + CISR)); base 1200 drivers/media/platform/pxa_camera.c cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; base 1201 drivers/media/platform/pxa_camera.c __raw_writel(cifr, pcdev->base + CIFR); base 1216 drivers/media/platform/pxa_camera.c status = __raw_readl(pcdev->base + CISR); base 1223 drivers/media/platform/pxa_camera.c __raw_writel(status, pcdev->base + CISR); base 1226 drivers/media/platform/pxa_camera.c cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; base 1227 drivers/media/platform/pxa_camera.c __raw_writel(cicr0, pcdev->base + CICR0); base 1303 drivers/media/platform/pxa_camera.c cicr0 = __raw_readl(pcdev->base + CICR0); base 1305 drivers/media/platform/pxa_camera.c __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); base 1341 drivers/media/platform/pxa_camera.c __raw_writel(cicr1, pcdev->base + CICR1); base 1342 drivers/media/platform/pxa_camera.c __raw_writel(cicr2, pcdev->base + CICR2); base 1343 drivers/media/platform/pxa_camera.c __raw_writel(cicr3, pcdev->base + CICR3); base 1344 drivers/media/platform/pxa_camera.c __raw_writel(cicr4, pcdev->base + CICR4); base 1350 drivers/media/platform/pxa_camera.c __raw_writel(cicr0, pcdev->base + CICR0); base 1823 drivers/media/platform/pxa_camera.c reg->val = __raw_readl(pcdev->base + reg->reg); base 1837 drivers/media/platform/pxa_camera.c __raw_writel(reg->val, pcdev->base + reg->reg); base 2223 drivers/media/platform/pxa_camera.c __raw_writel(0x3ff, pcdev->base + CICR0); base 2254 drivers/media/platform/pxa_camera.c pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); base 2255 drivers/media/platform/pxa_camera.c pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); base 2256 drivers/media/platform/pxa_camera.c pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); base 2257 drivers/media/platform/pxa_camera.c pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); base 2258 drivers/media/platform/pxa_camera.c pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); base 2271 drivers/media/platform/pxa_camera.c __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); base 2272 drivers/media/platform/pxa_camera.c __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); base 2273 drivers/media/platform/pxa_camera.c __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); base 2274 drivers/media/platform/pxa_camera.c __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); base 2275 drivers/media/platform/pxa_camera.c __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); base 2362 drivers/media/platform/pxa_camera.c void __iomem *base; base 2435 drivers/media/platform/pxa_camera.c base = devm_ioremap_resource(&pdev->dev, res); base 2436 drivers/media/platform/pxa_camera.c if (IS_ERR(base)) base 2437 drivers/media/platform/pxa_camera.c return PTR_ERR(base); base 2440 drivers/media/platform/pxa_camera.c pcdev->base = base; base 448 drivers/media/platform/qcom/camss/camss-csid.c value = readl_relaxed(csid->base + CAMSS_CSID_IRQ_STATUS(ver)); base 449 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(value, csid->base + CAMSS_CSID_IRQ_CLEAR_CMD(ver)); base 535 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(0x7fff, csid->base + base 599 drivers/media/platform/qcom/camss/camss-csid.c hw_version = readl_relaxed(csid->base + CAMSS_CSID_HW_VERSION); base 658 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + base 664 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + base 671 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + base 676 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + base 691 drivers/media/platform/qcom/camss/camss-csid.c csid->base + CAMSS_CSID_CORE_CTRL_0); base 697 drivers/media/platform/qcom/camss/camss-csid.c csid->base + CAMSS_CSID_CORE_CTRL_1); base 707 drivers/media/platform/qcom/camss/camss-csid.c val = readl_relaxed(csid->base + base 711 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + base 733 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + base 738 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + base 744 drivers/media/platform/qcom/camss/camss-csid.c writel_relaxed(val, csid->base + base 1110 drivers/media/platform/qcom/camss/camss-csid.c csid->base = devm_ioremap_resource(dev, r); base 1111 drivers/media/platform/qcom/camss/camss-csid.c if (IS_ERR(csid->base)) { base 1113 drivers/media/platform/qcom/camss/camss-csid.c return PTR_ERR(csid->base); base 49 drivers/media/platform/qcom/camss/camss-csid.h void __iomem *base; base 32 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c u8 hw_version = readl_relaxed(csiphy->base + base 44 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); base 46 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); base 96 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x1, csiphy->base + base 98 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x1, csiphy->base + base 103 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG); base 106 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); base 114 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x10, csiphy->base + base 116 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(settle_cnt, csiphy->base + base 118 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x3f, csiphy->base + base 120 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x3f, csiphy->base + base 138 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x0, csiphy->base + base 142 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG); base 158 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c u8 val = readl_relaxed(csiphy->base + base 160 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(val, csiphy->base + base 162 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD); base 163 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD); base 164 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c writel_relaxed(0x0, csiphy->base + base 54 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); base 56 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c hw_version = readl_relaxed(csiphy->base + base 58 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c hw_version |= readl_relaxed(csiphy->base + base 60 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c hw_version |= readl_relaxed(csiphy->base + base 62 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c hw_version |= readl_relaxed(csiphy->base + base 74 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); base 76 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); base 86 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c u8 val = readl_relaxed(csiphy->base + base 89 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + base 93 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); base 94 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); base 97 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(0x0, csiphy->base + base 152 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5)); base 155 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); base 165 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l)); base 168 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l)); base 171 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG3(l)); base 175 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG5(l)); base 178 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG6(l)); base 181 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG7(l)); base 185 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG8(l)); base 188 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG9(l)); base 191 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_TEST_IMP(l)); base 194 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + base 199 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l)); base 202 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l)); base 205 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l)); base 208 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(11)); base 211 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(12)); base 214 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(13)); base 217 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(14)); base 220 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(15)); base 223 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(16)); base 226 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(17)); base 229 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(18)); base 232 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(19)); base 235 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(20)); base 238 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(21)); base 244 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(0, csiphy->base + base 247 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c writel_relaxed(0, csiphy->base + base 566 drivers/media/platform/qcom/camss/camss-csiphy.c csiphy->base = devm_ioremap_resource(dev, r); base 567 drivers/media/platform/qcom/camss/camss-csiphy.c if (IS_ERR(csiphy->base)) { base 569 drivers/media/platform/qcom/camss/camss-csiphy.c return PTR_ERR(csiphy->base); base 64 drivers/media/platform/qcom/camss/camss-csiphy.h void __iomem *base; base 165 drivers/media/platform/qcom/camss/camss-ispif.c value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0)); base 166 drivers/media/platform/qcom/camss/camss-ispif.c value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0)); base 167 drivers/media/platform/qcom/camss/camss-ispif.c value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0)); base 168 drivers/media/platform/qcom/camss/camss-ispif.c value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1)); base 169 drivers/media/platform/qcom/camss/camss-ispif.c value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1)); base 170 drivers/media/platform/qcom/camss/camss-ispif.c value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1)); base 172 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0)); base 173 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0)); base 174 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0)); base 175 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1)); base 176 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1)); base 177 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1)); base 179 drivers/media/platform/qcom/camss/camss-ispif.c writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD); base 229 drivers/media/platform/qcom/camss/camss-ispif.c value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0)); base 230 drivers/media/platform/qcom/camss/camss-ispif.c value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0)); base 231 drivers/media/platform/qcom/camss/camss-ispif.c value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0)); base 233 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0)); base 234 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0)); base 235 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0)); base 237 drivers/media/platform/qcom/camss/camss-ispif.c writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD); base 306 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0); base 460 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + base 464 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + base 468 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + base 472 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + base 476 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + base 523 drivers/media/platform/qcom/camss/camss-ispif.c ret = readl_poll_timeout(ispif->base + addr, base 548 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); base 577 drivers/media/platform/qcom/camss/camss-ispif.c writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); base 613 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + addr); base 619 drivers/media/platform/qcom/camss/camss-ispif.c writel(val, ispif->base + addr); base 636 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); base 640 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); base 642 drivers/media/platform/qcom/camss/camss-ispif.c ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe)); base 645 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); base 649 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); base 651 drivers/media/platform/qcom/camss/camss-ispif.c ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe)); base 654 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); base 658 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); base 660 drivers/media/platform/qcom/camss/camss-ispif.c ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe)); base 663 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); base 667 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); base 669 drivers/media/platform/qcom/camss/camss-ispif.c ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe)); base 672 drivers/media/platform/qcom/camss/camss-ispif.c val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); base 676 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); base 678 drivers/media/platform/qcom/camss/camss-ispif.c ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe)); base 682 drivers/media/platform/qcom/camss/camss-ispif.c writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD); base 731 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(val, ispif->base + addr); base 752 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe)); base 759 drivers/media/platform/qcom/camss/camss-ispif.c writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe)); base 1105 drivers/media/platform/qcom/camss/camss-ispif.c ispif->base = devm_ioremap_resource(dev, r); base 1106 drivers/media/platform/qcom/camss/camss-ispif.c if (IS_ERR(ispif->base)) { base 1108 drivers/media/platform/qcom/camss/camss-ispif.c return PTR_ERR(ispif->base); base 51 drivers/media/platform/qcom/camss/camss-ispif.h void __iomem *base; base 213 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); base 228 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 bits = readl_relaxed(vfe->base + reg); base 230 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(bits & ~clr_bits, vfe->base + reg); base 235 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 bits = readl_relaxed(vfe->base + reg); base 237 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(bits | set_bits, vfe->base + reg); base 252 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); base 258 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe->base + VFE_0_BUS_BDG_CMD); base 263 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); base 347 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + base 356 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + base 359 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(0, vfe->base + base 361 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(0, vfe->base + base 370 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = readl_relaxed(vfe->base + base 379 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); base 386 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); base 396 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); base 402 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); base 409 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); base 415 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); base 422 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); base 430 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG); base 432 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); base 474 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe->base + base 564 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); base 636 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); base 639 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); base 642 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); base 664 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); base 665 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); base 690 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); base 695 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); base 700 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); base 705 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); base 710 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); base 712 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); base 717 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); base 722 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); base 729 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); base 734 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); base 746 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); base 751 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); base 756 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); base 765 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); base 774 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); base 780 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); base 788 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); base 789 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); base 790 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); base 791 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); base 792 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); base 793 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); base 794 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); base 795 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); base 835 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); base 839 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); base 842 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); base 845 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); base 848 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0); base 851 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); base 857 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); base 865 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); base 873 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); base 884 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG); base 886 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG); base 894 drivers/media/platform/qcom/camss/camss-vfe-4-1.c ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, base 907 drivers/media/platform/qcom/camss/camss-vfe-4-1.c *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); base 908 drivers/media/platform/qcom/camss/camss-vfe-4-1.c *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); base 910 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); base 911 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); base 914 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); base 919 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); base 244 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); base 261 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 bits = readl_relaxed(vfe->base + reg); base 263 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(bits & ~clr_bits, vfe->base + reg); base 268 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 bits = readl_relaxed(vfe->base + reg); base 270 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(bits | set_bits, vfe->base + reg); base 286 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); base 288 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); base 294 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe->base + VFE_0_BUS_BDG_CMD); base 299 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); base 397 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + base 406 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + base 409 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(0, vfe->base + base 411 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(0, vfe->base + base 420 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = readl_relaxed(vfe->base + base 429 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); base 436 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); base 446 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); base 452 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); base 459 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); base 465 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); base 472 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); base 480 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG); base 482 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); base 523 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe->base + base 651 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG); base 667 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); base 739 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); base 742 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); base 745 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); base 767 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); base 768 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); base 793 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); base 798 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); base 803 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); base 808 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); base 813 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); base 815 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); base 820 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); base 825 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); base 832 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); base 837 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); base 849 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); base 854 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); base 859 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); base 868 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); base 877 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); base 883 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); base 891 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); base 892 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); base 893 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); base 894 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); base 895 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); base 896 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); base 897 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); base 898 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); base 906 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0); base 907 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1); base 908 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2); base 909 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3); base 910 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4); base 911 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5); base 912 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6); base 913 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7); base 914 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8); base 915 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9); base 916 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10); base 917 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11); base 918 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12); base 919 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13); base 920 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14); base 921 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15); base 922 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16); base 951 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); base 955 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); base 958 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); base 961 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); base 964 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG); base 967 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN); base 970 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); base 976 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); base 984 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); base 992 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); base 1016 drivers/media/platform/qcom/camss/camss-vfe-4-7.c ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, base 1029 drivers/media/platform/qcom/camss/camss-vfe-4-7.c *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); base 1030 drivers/media/platform/qcom/camss/camss-vfe-4-7.c *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); base 1032 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); base 1033 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); base 1036 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); base 1041 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); base 2006 drivers/media/platform/qcom/camss/camss-vfe.c vfe->base = devm_ioremap_resource(dev, r); base 2007 drivers/media/platform/qcom/camss/camss-vfe.c if (IS_ERR(vfe->base)) { base 2009 drivers/media/platform/qcom/camss/camss-vfe.c return PTR_ERR(vfe->base); base 148 drivers/media/platform/qcom/camss/camss-vfe.h void __iomem *base; base 437 drivers/media/platform/qcom/camss/camss.c csd->interface.csiphy_id = vep.base.port; base 238 drivers/media/platform/qcom/venus/core.c core->base = devm_ioremap_resource(dev, r); base 239 drivers/media/platform/qcom/venus/core.c if (IS_ERR(core->base)) base 240 drivers/media/platform/qcom/venus/core.c return PTR_ERR(core->base); base 111 drivers/media/platform/qcom/venus/core.h void __iomem *base; base 30 drivers/media/platform/qcom/venus/firmware.c void __iomem *base = core->base; base 32 drivers/media/platform/qcom/venus/firmware.c writel(0, base + WRAPPER_FW_START_ADDR); base 33 drivers/media/platform/qcom/venus/firmware.c writel(fw_size, base + WRAPPER_FW_END_ADDR); base 34 drivers/media/platform/qcom/venus/firmware.c writel(0, base + WRAPPER_CPA_START_ADDR); base 35 drivers/media/platform/qcom/venus/firmware.c writel(fw_size, base + WRAPPER_CPA_END_ADDR); base 36 drivers/media/platform/qcom/venus/firmware.c writel(fw_size, base + WRAPPER_NONPIX_START_ADDR); base 37 drivers/media/platform/qcom/venus/firmware.c writel(fw_size, base + WRAPPER_NONPIX_END_ADDR); base 38 drivers/media/platform/qcom/venus/firmware.c writel(0x0, base + WRAPPER_CPU_CGC_DIS); base 39 drivers/media/platform/qcom/venus/firmware.c writel(0x0, base + WRAPPER_CPU_CLOCK_CONFIG); base 42 drivers/media/platform/qcom/venus/firmware.c writel(0, base + WRAPPER_A9SS_SW_RESET); base 59 drivers/media/platform/qcom/venus/firmware.c writel(1, core->base + WRAPPER_A9SS_SW_RESET); base 163 drivers/media/platform/qcom/venus/firmware.c void __iomem *base = core->base; base 166 drivers/media/platform/qcom/venus/firmware.c reg = readl_relaxed(base + WRAPPER_A9SS_SW_RESET); base 168 drivers/media/platform/qcom/venus/firmware.c writel_relaxed(reg, base + WRAPPER_A9SS_SW_RESET); base 1345 drivers/media/platform/qcom/venus/helpers.c ctrl = core->base + WRAPPER_VDEC_VCODEC_POWER_CONTROL; base 1347 drivers/media/platform/qcom/venus/helpers.c ctrl = core->base + WRAPPER_VENC_VCODEC_POWER_CONTROL; base 1357 drivers/media/platform/qcom/venus/helpers.c ctrl = core->base + WRAPPER_VCODEC0_MMCC_POWER_CONTROL; base 1358 drivers/media/platform/qcom/venus/helpers.c stat = core->base + WRAPPER_VCODEC0_MMCC_POWER_STATUS; base 1360 drivers/media/platform/qcom/venus/helpers.c ctrl = core->base + WRAPPER_VCODEC1_MMCC_POWER_CONTROL; base 1361 drivers/media/platform/qcom/venus/helpers.c stat = core->base + WRAPPER_VCODEC1_MMCC_POWER_STATUS; base 350 drivers/media/platform/qcom/venus/hfi_venus.c writel(value, hdev->core->base + reg); base 355 drivers/media/platform/qcom/venus/hfi_venus.c return readl(hdev->core->base + reg); base 516 drivers/media/platform/qcom/venus/hfi_venus.c void __iomem *base = hdev->core->base; base 526 drivers/media/platform/qcom/venus/hfi_venus.c ret = readl_poll_timeout(base + WRAPPER_CPU_AXI_HALT_STATUS, base 545 drivers/media/platform/qcom/venus/hfi_venus.c ret = readl_poll_timeout(base + VBIF_AXI_HALT_CTRL1, val, base 621 drivers/media/platform/rcar-vin/rcar-core.c if (vep->base.port || vep->base.id) base 802 drivers/media/platform/rcar-vin/rcar-core.c if (vep->base.port != 1 || vep->base.id >= RVIN_CSI_MAX) base 813 drivers/media/platform/rcar-vin/rcar-core.c if (vin->group->csi[vep->base.id].fwnode) { base 820 drivers/media/platform/rcar-vin/rcar-core.c vin->group->csi[vep->base.id].fwnode = asd->match.fwnode; base 823 drivers/media/platform/rcar-vin/rcar-core.c to_of_node(asd->match.fwnode), vep->base.id); base 1308 drivers/media/platform/rcar-vin/rcar-core.c vin->base = devm_ioremap_resource(vin->dev, mem); base 1309 drivers/media/platform/rcar-vin/rcar-core.c if (IS_ERR(vin->base)) base 1310 drivers/media/platform/rcar-vin/rcar-core.c return PTR_ERR(vin->base); base 356 drivers/media/platform/rcar-vin/rcar-csi2.c void __iomem *base; base 388 drivers/media/platform/rcar-vin/rcar-csi2.c return ioread32(priv->base + reg); base 393 drivers/media/platform/rcar-vin/rcar-csi2.c iowrite32(data, priv->base + reg); base 782 drivers/media/platform/rcar-vin/rcar-csi2.c if (vep->base.port || vep->base.id) base 1007 drivers/media/platform/rcar-vin/rcar-csi2.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 1008 drivers/media/platform/rcar-vin/rcar-csi2.c if (IS_ERR(priv->base)) base 1009 drivers/media/platform/rcar-vin/rcar-csi2.c return PTR_ERR(priv->base); base 146 drivers/media/platform/rcar-vin/rcar-dma.c iowrite32(value, vin->base + offset); base 151 drivers/media/platform/rcar-vin/rcar-dma.c return ioread32(vin->base + offset); base 186 drivers/media/platform/rcar-vin/rcar-vin.h void __iomem *base; base 201 drivers/media/platform/rcar_drif.c void __iomem *base; /* Base register address */ base 248 drivers/media/platform/rcar_drif.c writel(data, ch->base + offset); base 253 drivers/media/platform/rcar_drif.c return readl(ch->base + offset); base 647 drivers/media/platform/rcar_drif.c ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR, base 674 drivers/media/platform/rcar_drif.c ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR, base 714 drivers/media/platform/rcar_drif.c ret = readl_poll_timeout(ch->base + RCAR_DRIF_SICTR, ctr, base 1408 drivers/media/platform/rcar_drif.c ch->base = devm_ioremap_resource(&pdev->dev, res); base 1409 drivers/media/platform/rcar_drif.c if (IS_ERR(ch->base)) base 1410 drivers/media/platform/rcar_drif.c return PTR_ERR(ch->base); base 847 drivers/media/platform/rcar_fdp1.c unsigned int len, unsigned int base) base 856 drivers/media/platform/rcar_fdp1.c fdp1_write(fdp1, lut[i], base + (i*4)); base 862 drivers/media/platform/rcar_fdp1.c fdp1_write(fdp1, pad, base + (i*4)); base 206 drivers/media/platform/renesas-ceu.c void __iomem *base; base 303 drivers/media/platform/renesas-ceu.c iowrite32(data, priv->base + reg_offs); base 308 drivers/media/platform/renesas-ceu.c return ioread32(priv->base + reg_offs); base 1655 drivers/media/platform/renesas-ceu.c ceudev->base = devm_ioremap_resource(dev, res); base 1656 drivers/media/platform/renesas-ceu.c if (IS_ERR(ceudev->base)) { base 1657 drivers/media/platform/renesas-ceu.c ret = PTR_ERR(ceudev->base); base 710 drivers/media/platform/s5p-jpeg/jpeg-core.c static void exynos4_jpeg_set_huff_tbl(void __iomem *base) base 712 drivers/media/platform/s5p-jpeg/jpeg-core.c exynos4_jpeg_set_tbl(base, hdctbl0, EXYNOS4_HUFF_TBL_HDCLL, base 714 drivers/media/platform/s5p-jpeg/jpeg-core.c exynos4_jpeg_set_tbl(base, hdctbl0, EXYNOS4_HUFF_TBL_HDCCL, base 716 drivers/media/platform/s5p-jpeg/jpeg-core.c exynos4_jpeg_set_tbl(base, hdctblg0, EXYNOS4_HUFF_TBL_HDCLV, base 718 drivers/media/platform/s5p-jpeg/jpeg-core.c exynos4_jpeg_set_tbl(base, hdctblg0, EXYNOS4_HUFF_TBL_HDCCV, base 720 drivers/media/platform/s5p-jpeg/jpeg-core.c exynos4_jpeg_set_tbl(base, hactbl0, EXYNOS4_HUFF_TBL_HACLL, base 722 drivers/media/platform/s5p-jpeg/jpeg-core.c exynos4_jpeg_set_tbl(base, hactbl0, EXYNOS4_HUFF_TBL_HACCL, base 724 drivers/media/platform/s5p-jpeg/jpeg-core.c exynos4_jpeg_set_tbl(base, hactblg0, EXYNOS4_HUFF_TBL_HACLV, base 726 drivers/media/platform/s5p-jpeg/jpeg-core.c exynos4_jpeg_set_tbl(base, hactblg0, EXYNOS4_HUFF_TBL_HACCV, base 2179 drivers/media/platform/s5p-jpeg/jpeg-core.c static inline void exynos4_jpeg_set_img_fmt(void __iomem *base, base 2182 drivers/media/platform/s5p-jpeg/jpeg-core.c __exynos4_jpeg_set_img_fmt(base, img_fmt, SJPEG_EXYNOS4); base 2185 drivers/media/platform/s5p-jpeg/jpeg-core.c static inline void exynos5433_jpeg_set_img_fmt(void __iomem *base, base 2188 drivers/media/platform/s5p-jpeg/jpeg-core.c __exynos4_jpeg_set_img_fmt(base, img_fmt, SJPEG_EXYNOS5433); base 2191 drivers/media/platform/s5p-jpeg/jpeg-core.c static inline void exynos4_jpeg_set_enc_out_fmt(void __iomem *base, base 2194 drivers/media/platform/s5p-jpeg/jpeg-core.c __exynos4_jpeg_set_enc_out_fmt(base, out_fmt, SJPEG_EXYNOS4); base 2197 drivers/media/platform/s5p-jpeg/jpeg-core.c static inline void exynos5433_jpeg_set_enc_out_fmt(void __iomem *base, base 2200 drivers/media/platform/s5p-jpeg/jpeg-core.c __exynos4_jpeg_set_enc_out_fmt(base, out_fmt, SJPEG_EXYNOS5433); base 60 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c void exynos3250_jpeg_clk_set(void __iomem *base) base 64 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; base 66 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); base 390 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c void exynos3250_jpeg_coef(void __iomem *base, unsigned int mode) base 394 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c base + EXYNOS3250_JPG_COEF(1)); base 396 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c base + EXYNOS3250_JPG_COEF(2)); base 398 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c base + EXYNOS3250_JPG_COEF(3)); base 401 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c base + EXYNOS3250_JPG_COEF(1)); base 403 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c base + EXYNOS3250_JPG_COEF(2)); base 405 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c base + EXYNOS3250_JPG_COEF(3)); base 20 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.h void exynos3250_jpeg_clk_set(void __iomem *base); base 42 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.h void exynos3250_jpeg_coef(void __iomem *base, unsigned int mode); base 16 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_sw_reset(void __iomem *base) base 20 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_JPEG_CNTL_REG); base 22 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c base + EXYNOS4_JPEG_CNTL_REG); base 24 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_JPEG_CNTL_REG); base 25 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); base 29 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); base 32 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) base 36 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_JPEG_CNTL_REG); base 41 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c base + EXYNOS4_JPEG_CNTL_REG); base 45 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c base + EXYNOS4_JPEG_CNTL_REG); base 48 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c base + EXYNOS4_JPEG_CNTL_REG); base 52 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt, base 67 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_IMG_FMT_REG) & base 133 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_IMG_FMT_REG); base 136 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt, base 141 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_IMG_FMT_REG) & base 166 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_IMG_FMT_REG); base 169 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version) base 174 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_INT_EN_REG) & ~EXYNOS4_INT_EN_MASK; base 175 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg | EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); base 177 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_INT_EN_REG) & base 179 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg | EXYNOS5433_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); base 183 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int exynos4_jpeg_get_int_status(void __iomem *base) base 185 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c return readl(base + EXYNOS4_INT_STATUS_REG); base 188 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int exynos4_jpeg_get_fifo_status(void __iomem *base) base 190 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c return readl(base + EXYNOS4_FIFO_STATUS_REG); base 193 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value) base 197 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~EXYNOS4_HUF_TBL_EN; base 201 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c base + EXYNOS4_JPEG_CNTL_REG); base 204 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c base + EXYNOS4_JPEG_CNTL_REG); base 207 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value) base 211 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~(EXYNOS4_SYS_INT_EN); base 214 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg | EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); base 216 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg & ~EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); base 219 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_stream_buf_address(void __iomem *base, base 222 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(address, base + EXYNOS4_OUT_MEM_BASE_REG); base 225 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_stream_size(void __iomem *base, base 228 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(0x0, base + EXYNOS4_JPEG_IMG_SIZE_REG); /* clear */ base 230 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c base + EXYNOS4_JPEG_IMG_SIZE_REG); base 233 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_frame_buf_address(void __iomem *base, base 236 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(exynos4_jpeg_addr->y, base + EXYNOS4_IMG_BA_PLANE_1_REG); base 237 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(exynos4_jpeg_addr->cb, base + EXYNOS4_IMG_BA_PLANE_2_REG); base 238 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(exynos4_jpeg_addr->cr, base + EXYNOS4_IMG_BA_PLANE_3_REG); base 241 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_encode_tbl_select(void __iomem *base, base 252 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_TBL_SEL_REG); base 255 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_dec_components(void __iomem *base, int n) base 259 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_TBL_SEL_REG); base 262 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_TBL_SEL_REG); base 265 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_select_dec_q_tbl(void __iomem *base, char c, char x) base 269 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_TBL_SEL_REG); base 272 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_TBL_SEL_REG); base 275 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_select_dec_h_tbl(void __iomem *base, char c, char x) base 279 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_TBL_SEL_REG); base 282 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_TBL_SEL_REG); base 285 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_encode_hoff_cnt(void __iomem *base, unsigned int fmt) base 288 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(0xd2, base + EXYNOS4_HUFF_CNT_REG); base 290 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(0x1a2, base + EXYNOS4_HUFF_CNT_REG); base 293 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int exynos4_jpeg_get_stream_size(void __iomem *base) base 295 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c return readl(base + EXYNOS4_BITSTREAM_SIZE_REG); base 298 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size) base 300 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(size, base + EXYNOS4_BITSTREAM_SIZE_REG); base 303 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_get_frame_size(void __iomem *base, base 306 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c *width = (readl(base + EXYNOS4_DECODE_XY_SIZE_REG) & base 308 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c *height = (readl(base + EXYNOS4_DECODE_XY_SIZE_REG) >> 16) & base 312 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int exynos4_jpeg_get_frame_fmt(void __iomem *base) base 314 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c return readl(base + EXYNOS4_DECODE_IMG_FMT_REG) & base 318 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c void exynos4_jpeg_set_timer_count(void __iomem *base, unsigned int size) base 320 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(size, base + EXYNOS4_INT_TIMER_COUNT_REG); base 13 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_sw_reset(void __iomem *base); base 14 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode); base 15 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt, base 17 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt, base 19 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_enc_tbl(void __iomem *base); base 20 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version); base 21 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h unsigned int exynos4_jpeg_get_int_status(void __iomem *base); base 22 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value); base 23 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value); base 24 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_stream_buf_address(void __iomem *base, base 26 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_stream_size(void __iomem *base, base 28 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_frame_buf_address(void __iomem *base, base 30 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_encode_tbl_select(void __iomem *base, base 32 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_dec_components(void __iomem *base, int n); base 33 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_select_dec_q_tbl(void __iomem *base, char c, char x); base 34 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_select_dec_h_tbl(void __iomem *base, char c, char x); base 35 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_encode_hoff_cnt(void __iomem *base, unsigned int fmt); base 36 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size); base 37 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h unsigned int exynos4_jpeg_get_stream_size(void __iomem *base); base 38 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_get_frame_size(void __iomem *base, base 40 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h unsigned int exynos4_jpeg_get_frame_fmt(void __iomem *base); base 41 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h unsigned int exynos4_jpeg_get_fifo_status(void __iomem *base); base 42 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.h void exynos4_jpeg_set_timer_count(void __iomem *base, unsigned int size); base 58 drivers/media/platform/s5p-mfc/s5p_mfc_opr.c dma_addr_t base = dev->dma_base[mem_ctx]; base 64 drivers/media/platform/s5p-mfc/s5p_mfc_opr.c if (b->dma < base) { base 66 drivers/media/platform/s5p-mfc/s5p_mfc_opr.c &b->dma, &base); base 117 drivers/media/platform/sh_veu.c void __iomem *base; base 222 drivers/media/platform/sh_veu.c return ioread32(veu->base + reg); base 228 drivers/media/platform/sh_veu.c iowrite32(value, veu->base + reg); base 1124 drivers/media/platform/sh_veu.c veu->base = devm_ioremap_resource(&pdev->dev, reg_res); base 1125 drivers/media/platform/sh_veu.c if (IS_ERR(veu->base)) base 1126 drivers/media/platform/sh_veu.c return PTR_ERR(veu->base); base 78 drivers/media/platform/sh_vou.c void __iomem *base; base 96 drivers/media/platform/sh_vou.c __raw_writel(value, vou_dev->base + reg); base 102 drivers/media/platform/sh_vou.c __raw_writel(value, vou_dev->base + reg); base 103 drivers/media/platform/sh_vou.c __raw_writel(value, vou_dev->base + reg + 0x1000); base 109 drivers/media/platform/sh_vou.c __raw_writel(value, vou_dev->base + reg + 0x2000); base 114 drivers/media/platform/sh_vou.c return __raw_readl(vou_dev->base + reg); base 120 drivers/media/platform/sh_vou.c u32 old = __raw_readl(vou_dev->base + reg); base 123 drivers/media/platform/sh_vou.c __raw_writel(value, vou_dev->base + reg); base 1263 drivers/media/platform/sh_vou.c vou_dev->base = devm_ioremap_resource(&pdev->dev, reg_res); base 1264 drivers/media/platform/sh_vou.c if (IS_ERR(vou_dev->base)) base 1265 drivers/media/platform/sh_vou.c return PTR_ERR(vou_dev->base); base 453 drivers/media/platform/sti/bdisp/bdisp-hw.c void *base; base 457 drivers/media/platform/sti/bdisp/bdisp-hw.c base = dma_alloc_attrs(dev, node_size * MAX_NB_NODE, &paddr, base 459 drivers/media/platform/sti/bdisp/bdisp-hw.c if (!base) { base 464 drivers/media/platform/sti/bdisp/bdisp-hw.c memset(base, 0, node_size * MAX_NB_NODE); base 467 drivers/media/platform/sti/bdisp/bdisp-hw.c ctx->node[i] = base; base 471 drivers/media/platform/sti/bdisp/bdisp-hw.c base += node_size; base 508 drivers/media/platform/sti/bdisp/bdisp-hw.c void *base; base 513 drivers/media/platform/sti/bdisp/bdisp-hw.c base = dma_alloc_attrs(dev, size, &paddr, GFP_KERNEL, base 515 drivers/media/platform/sti/bdisp/bdisp-hw.c if (!base) base 522 drivers/media/platform/sti/bdisp/bdisp-hw.c memcpy(base, bdisp_h_spec[i].coef, BDISP_HF_NB); base 523 drivers/media/platform/sti/bdisp/bdisp-hw.c bdisp_h_filter[i].virt = base; base 525 drivers/media/platform/sti/bdisp/bdisp-hw.c base += BDISP_HF_NB; base 532 drivers/media/platform/sti/bdisp/bdisp-hw.c memcpy(base, bdisp_v_spec[i].coef, BDISP_VF_NB); base 533 drivers/media/platform/sti/bdisp/bdisp-hw.c bdisp_v_filter[i].virt = base; base 535 drivers/media/platform/sti/bdisp/bdisp-hw.c base += BDISP_VF_NB; base 243 drivers/media/platform/sti/c8sectpfe/c8sectpfe-debugfs.c fei->regset->base = fei->io; base 17 drivers/media/platform/sti/hva/hva-mem.c void *base; base 25 drivers/media/platform/sti/hva/hva-mem.c base = dma_alloc_attrs(dev, size, &paddr, GFP_KERNEL, base 27 drivers/media/platform/sti/hva/hva-mem.c if (!base) { base 37 drivers/media/platform/sti/hva/hva-mem.c b->vaddr = base; base 183 drivers/media/platform/stm32/stm32-dcmi.c static inline u32 reg_read(void __iomem *base, u32 reg) base 185 drivers/media/platform/stm32/stm32-dcmi.c return readl_relaxed(base + reg); base 188 drivers/media/platform/stm32/stm32-dcmi.c static inline void reg_write(void __iomem *base, u32 reg, u32 val) base 190 drivers/media/platform/stm32/stm32-dcmi.c writel_relaxed(val, base + reg); base 193 drivers/media/platform/stm32/stm32-dcmi.c static inline void reg_set(void __iomem *base, u32 reg, u32 mask) base 195 drivers/media/platform/stm32/stm32-dcmi.c reg_write(base, reg, reg_read(base, reg) | mask); base 198 drivers/media/platform/stm32/stm32-dcmi.c static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) base 200 drivers/media/platform/stm32/stm32-dcmi.c reg_write(base, reg, reg_read(base, reg) & ~mask); base 701 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c if (vep->base.port || vep->base.id) { base 76 drivers/media/platform/ti-vpe/cal.c #define reg_read(dev, offset) ioread32(dev->base + offset) base 77 drivers/media/platform/ti-vpe/cal.c #define reg_write(dev, offset, val) iowrite32(val, dev->base + offset) base 224 drivers/media/platform/ti-vpe/cal.c void __iomem *base; base 233 drivers/media/platform/ti-vpe/cal.c void __iomem *base; base 245 drivers/media/platform/ti-vpe/cal.c void __iomem *base; base 374 drivers/media/platform/ti-vpe/cal.c cm->base = devm_ioremap_resource(&pdev->dev, cm->res); base 375 drivers/media/platform/ti-vpe/cal.c if (IS_ERR(cm->base)) { base 377 drivers/media/platform/ti-vpe/cal.c return ERR_CAST(cm->base); base 390 drivers/media/platform/ti-vpe/cal.c if (!ctx->dev->cm->base) { base 416 drivers/media/platform/ti-vpe/cal.c if (!ctx->dev->cm->base) { base 446 drivers/media/platform/ti-vpe/cal.c cc->base = devm_ioremap_resource(&pdev->dev, cc->res); base 447 drivers/media/platform/ti-vpe/cal.c if (IS_ERR(cc->base)) { base 449 drivers/media/platform/ti-vpe/cal.c return ERR_CAST(cc->base); base 489 drivers/media/platform/ti-vpe/cal.c (__force const void *)dev->base, base 496 drivers/media/platform/ti-vpe/cal.c (__force const void *)dev->ctx[0]->cc->base, base 505 drivers/media/platform/ti-vpe/cal.c (__force const void *)dev->ctx[1]->cc->base, base 513 drivers/media/platform/ti-vpe/cal.c (__force const void *)dev->cm->base, base 1705 drivers/media/platform/ti-vpe/cal.c ctx->virtual_channel = endpoint->base.id; base 1831 drivers/media/platform/ti-vpe/cal.c dev->base = devm_ioremap_resource(&pdev->dev, dev->res); base 1832 drivers/media/platform/ti-vpe/cal.c if (IS_ERR(dev->base)) base 1833 drivers/media/platform/ti-vpe/cal.c return PTR_ERR(dev->base); base 95 drivers/media/platform/ti-vpe/csc.c ioread32(csc->base + CSC_##r)) base 189 drivers/media/platform/ti-vpe/csc.c csc->base = devm_ioremap_resource(&pdev->dev, csc->res); base 190 drivers/media/platform/ti-vpe/csc.c if (IS_ERR(csc->base)) { base 192 drivers/media/platform/ti-vpe/csc.c return ERR_CAST(csc->base); base 52 drivers/media/platform/ti-vpe/csc.h void __iomem *base; base 26 drivers/media/platform/ti-vpe/sc.c ioread32(sc->base + CFG_##r)) base 296 drivers/media/platform/ti-vpe/sc.c sc->base = devm_ioremap_resource(&pdev->dev, sc->res); base 297 drivers/media/platform/ti-vpe/sc.c if (IS_ERR(sc->base)) { base 299 drivers/media/platform/ti-vpe/sc.c return ERR_CAST(sc->base); base 186 drivers/media/platform/ti-vpe/sc.h void __iomem *base; base 277 drivers/media/platform/ti-vpe/vpdma.c return ioread32(vpdma->base + offset); base 282 drivers/media/platform/ti-vpe/vpdma.c iowrite32(value, vpdma->base + offset); base 1152 drivers/media/platform/ti-vpe/vpdma.c vpdma->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); base 1153 drivers/media/platform/ti-vpe/vpdma.c if (!vpdma->base) { base 32 drivers/media/platform/ti-vpe/vpdma.h void __iomem *base; base 375 drivers/media/platform/ti-vpe/vpe.c void __iomem *base; base 440 drivers/media/platform/ti-vpe/vpe.c return ioread32(dev->base + offset); base 445 drivers/media/platform/ti-vpe/vpe.c iowrite32(value, dev->base + offset); base 2507 drivers/media/platform/ti-vpe/vpe.c dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K); base 2508 drivers/media/platform/ti-vpe/vpe.c if (!dev->base) { base 726 drivers/media/platform/vivid/vivid-kthread-cap.c if (dev->overlay_cap_owner && dev->fb_cap.base && base 1240 drivers/media/platform/vivid/vivid-vid-cap.c if (a->base == NULL) { base 1241 drivers/media/platform/vivid/vivid-vid-cap.c dev->fb_cap.base = NULL; base 1256 drivers/media/platform/vivid/vivid-vid-cap.c dev->fb_vbase_cap = phys_to_virt((unsigned long)a->base); base 990 drivers/media/platform/vivid/vivid-vid-out.c a->base = (void *)dev->video_pbase; base 32 drivers/media/platform/vsp1/vsp1_brx.c vsp1_dl_body_write(dlb, brx->base + reg, data); base 419 drivers/media/platform/vsp1/vsp1_brx.c brx->base = type == VSP1_ENTITY_BRU ? VI6_BRU_BASE : VI6_BRS_BASE; base 25 drivers/media/platform/vsp1/vsp1_brx.h unsigned int base; base 63 drivers/media/rc/ir-hix5hd2.c void __iomem *base; base 100 drivers/media/rc/ir-hix5hd2.c writel_relaxed(0x01, priv->base + IR_ENABLE); base 101 drivers/media/rc/ir-hix5hd2.c while (readl_relaxed(priv->base + IR_BUSY)) { base 118 drivers/media/rc/ir-hix5hd2.c writel_relaxed(val, priv->base + IR_CONFIG); base 120 drivers/media/rc/ir-hix5hd2.c writel_relaxed(0x00, priv->base + IR_INTM); base 122 drivers/media/rc/ir-hix5hd2.c writel_relaxed(0x01, priv->base + IR_START); base 157 drivers/media/rc/ir-hix5hd2.c irq_sr = readl_relaxed(priv->base + IR_INTS); base 165 drivers/media/rc/ir-hix5hd2.c symb_num = readl_relaxed(priv->base + IR_DATAH); base 167 drivers/media/rc/ir-hix5hd2.c readl_relaxed(priv->base + IR_DATAL); base 169 drivers/media/rc/ir-hix5hd2.c writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC); base 177 drivers/media/rc/ir-hix5hd2.c symb_num = readl_relaxed(priv->base + IR_DATAH); base 179 drivers/media/rc/ir-hix5hd2.c symb_val = readl_relaxed(priv->base + IR_DATAL); base 198 drivers/media/rc/ir-hix5hd2.c writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC); base 200 drivers/media/rc/ir-hix5hd2.c writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC); base 230 drivers/media/rc/ir-hix5hd2.c priv->base = devm_ioremap_resource(dev, res); base 231 drivers/media/rc/ir-hix5hd2.c if (IS_ERR(priv->base)) base 232 drivers/media/rc/ir-hix5hd2.c return PTR_ERR(priv->base); base 332 drivers/media/rc/ir-hix5hd2.c writel_relaxed(0x01, priv->base + IR_ENABLE); base 333 drivers/media/rc/ir-hix5hd2.c writel_relaxed(0x00, priv->base + IR_INTM); base 334 drivers/media/rc/ir-hix5hd2.c writel_relaxed(0xff, priv->base + IR_INTC); base 335 drivers/media/rc/ir-hix5hd2.c writel_relaxed(0x01, priv->base + IR_START); base 89 drivers/media/rc/ir-rx51.c now = timer->base->get_time(); base 138 drivers/media/rc/mtk-cir.c void __iomem *base; base 175 drivers/media/rc/mtk-cir.c tmp = __raw_readl(ir->base + reg); base 177 drivers/media/rc/mtk-cir.c __raw_writel(tmp, ir->base + reg); base 182 drivers/media/rc/mtk-cir.c __raw_writel(val, ir->base + reg); base 187 drivers/media/rc/mtk-cir.c return __raw_readl(ir->base + reg); base 327 drivers/media/rc/mtk-cir.c ir->base = devm_ioremap_resource(dev, res); base 328 drivers/media/rc/mtk-cir.c if (IS_ERR(ir->base)) base 329 drivers/media/rc/mtk-cir.c return PTR_ERR(ir->base); base 22 drivers/media/rc/st_rc.c void __iomem *base; /* Register base address */ base 176 drivers/media/rc/st_rc.c writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM); base 271 drivers/media/rc/st_rc.c rc_dev->base = devm_ioremap_resource(dev, res); base 272 drivers/media/rc/st_rc.c if (IS_ERR(rc_dev->base)) { base 273 drivers/media/rc/st_rc.c ret = PTR_ERR(rc_dev->base); base 278 drivers/media/rc/st_rc.c rc_dev->rx_base = rc_dev->base + 0x40; base 280 drivers/media/rc/st_rc.c rc_dev->rx_base = rc_dev->base; base 95 drivers/media/rc/sunxi-cir.c void __iomem *base; base 114 drivers/media/rc/sunxi-cir.c status = readl(ir->base + SUNXI_IR_RXSTA_REG); base 117 drivers/media/rc/sunxi-cir.c writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); base 127 drivers/media/rc/sunxi-cir.c dt = readb(ir->base + SUNXI_IR_RXFIFO_REG); base 219 drivers/media/rc/sunxi-cir.c ir->base = devm_ioremap_resource(dev, res); base 220 drivers/media/rc/sunxi-cir.c if (IS_ERR(ir->base)) { base 221 drivers/media/rc/sunxi-cir.c ret = PTR_ERR(ir->base); base 270 drivers/media/rc/sunxi-cir.c writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG); base 274 drivers/media/rc/sunxi-cir.c ir->base + SUNXI_IR_CIR_REG); base 277 drivers/media/rc/sunxi-cir.c writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); base 280 drivers/media/rc/sunxi-cir.c writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); base 288 drivers/media/rc/sunxi-cir.c ir->base + SUNXI_IR_RXINT_REG); base 291 drivers/media/rc/sunxi-cir.c tmp = readl(ir->base + SUNXI_IR_CTL_REG); base 292 drivers/media/rc/sunxi-cir.c writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG); base 320 drivers/media/rc/sunxi-cir.c writel(0, ir->base + SUNXI_IR_RXINT_REG); base 322 drivers/media/rc/sunxi-cir.c writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); base 324 drivers/media/rc/sunxi-cir.c writel(0, ir->base + SUNXI_IR_CTL_REG); base 33 drivers/media/rc/zx-irdec.c void __iomem *base; base 42 drivers/media/rc/zx-irdec.c data = readl(irdec->base + reg); base 45 drivers/media/rc/zx-irdec.c writel(data, irdec->base + reg); base 57 drivers/media/rc/zx-irdec.c writel(1, irdec->base + ZX_IR_INTSTCLR); base 60 drivers/media/rc/zx-irdec.c if (readl(irdec->base + ZX_IR_CNUM) & ZX_NECRPT) { base 65 drivers/media/rc/zx-irdec.c rawcode = readl(irdec->base + ZX_IR_CODE); base 94 drivers/media/rc/zx-irdec.c irdec->base = devm_ioremap_resource(dev, res); base 95 drivers/media/rc/zx-irdec.c if (IS_ERR(irdec->base)) base 96 drivers/media/rc/zx-irdec.c return PTR_ERR(irdec->base); base 142 drivers/media/rc/zx-irdec.c writel(1, irdec->base + ZX_IR_INTEN); base 158 drivers/media/rc/zx-irdec.c writel(0, irdec->base + ZX_IR_INTEN); base 1004 drivers/media/usb/gspca/cpia1.c #define COMPGAIN(base, curexp, newexp) \ base 1005 drivers/media/usb/gspca/cpia1.c (u8) ((((float) base - 128.0) * ((float) curexp / (float) newexp)) + 128.5) base 1011 drivers/media/usb/gspca/cpia1.c #define COMPGAIN(base, curexp, newexp) \ base 1012 drivers/media/usb/gspca/cpia1.c (u8)(128 + (((u32)(2*(base-128)*curexp + newexp)) / (2 * newexp))) base 767 drivers/media/v4l2-core/v4l2-compat-ioctl32.c compat_caddr_t base; base 786 drivers/media/v4l2-core/v4l2-compat-ioctl32.c get_user(tmp, &p32->base) || base 787 drivers/media/v4l2-core/v4l2-compat-ioctl32.c put_user_force(compat_ptr(tmp), &p64->base) || base 798 drivers/media/v4l2-core/v4l2-compat-ioctl32.c void *base; base 801 drivers/media/v4l2-core/v4l2-compat-ioctl32.c get_user(base, &p64->base) || base 802 drivers/media/v4l2-core/v4l2-compat-ioctl32.c put_user(ptr_to_compat((void __user *)base), &p32->base) || base 431 drivers/media/v4l2-core/v4l2-fwnode.c memset(&vep->base, 0, sizeof(vep->base)); base 491 drivers/media/v4l2-core/v4l2-fwnode.c fwnode_graph_parse_endpoint(fwnode, &vep->base); base 631 drivers/media/v4l2-core/v4l2-fwnode.c dev_dbg(dev, "ignoring port@%u/endpoint@%u\n", vep.base.port, base 632 drivers/media/v4l2-core/v4l2-fwnode.c vep.base.id); base 636 drivers/media/v4l2-core/v4l2-fwnode.c vep.base.port, vep.base.id, ret); base 385 drivers/media/v4l2-core/v4l2-ioctl.c p->capability, p->flags, p->base, base 558 drivers/media/v4l2-core/videobuf-dma-sg.c bus = (dma_addr_t)(unsigned long)fbuf->base + vb->boff; base 62 drivers/memory/emif.c void __iomem *base; base 231 drivers/memory/emif.c void __iomem *base = emif->base; base 233 drivers/memory/emif.c width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK) base 246 drivers/memory/emif.c void __iomem *base = emif->base; base 248 drivers/memory/emif.c cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT; base 256 drivers/memory/emif.c void __iomem *base = emif->base; base 293 drivers/memory/emif.c temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL); base 296 drivers/memory/emif.c writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL); base 839 drivers/memory/emif.c void __iomem *base; base 841 drivers/memory/emif.c base = emif->base; base 844 drivers/memory/emif.c writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG); base 845 drivers/memory/emif.c temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA); base 850 drivers/memory/emif.c writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG); base 851 drivers/memory/emif.c temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA); base 872 drivers/memory/emif.c void __iomem *base = emif->base; base 874 drivers/memory/emif.c writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); base 875 drivers/memory/emif.c writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); base 877 drivers/memory/emif.c base + EMIF_POWER_MANAGEMENT_CTRL_SHDW); base 882 drivers/memory/emif.c writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW); base 883 drivers/memory/emif.c writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW); base 884 drivers/memory/emif.c writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW); base 895 drivers/memory/emif.c void __iomem *base = emif->base; base 908 drivers/memory/emif.c writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW); base 923 drivers/memory/emif.c void __iomem *base = emif->base; base 946 drivers/memory/emif.c writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); base 947 drivers/memory/emif.c writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW); base 948 drivers/memory/emif.c writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW); base 951 drivers/memory/emif.c static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif) base 1014 drivers/memory/emif.c void __iomem *base = emif->base; base 1019 drivers/memory/emif.c interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); base 1020 drivers/memory/emif.c writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); base 1028 drivers/memory/emif.c ret = handle_temp_alert(base, emif); base 1035 drivers/memory/emif.c interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS); base 1036 drivers/memory/emif.c writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS); base 1079 drivers/memory/emif.c void __iomem *base = emif->base; base 1081 drivers/memory/emif.c writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS), base 1082 drivers/memory/emif.c base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); base 1084 drivers/memory/emif.c writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS), base 1085 drivers/memory/emif.c base + EMIF_LL_OCP_INTERRUPT_STATUS); base 1090 drivers/memory/emif.c void __iomem *base = emif->base; base 1093 drivers/memory/emif.c writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET), base 1094 drivers/memory/emif.c base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR); base 1096 drivers/memory/emif.c writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET), base 1097 drivers/memory/emif.c base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR); base 1106 drivers/memory/emif.c void __iomem *base = emif->base; base 1116 drivers/memory/emif.c writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET); base 1122 drivers/memory/emif.c writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET); base 1137 drivers/memory/emif.c void __iomem *base = emif->base; base 1152 drivers/memory/emif.c writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL); base 1157 drivers/memory/emif.c writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG); base 1168 drivers/memory/emif.c writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG); base 1176 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW); base 1177 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW); base 1178 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW); base 1179 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW); base 1180 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW); base 1181 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW); base 1182 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW); base 1183 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW); base 1184 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW); base 1185 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW); base 1186 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW); base 1187 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW); base 1188 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW); base 1189 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW); base 1190 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW); base 1191 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW); base 1192 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW); base 1193 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW); base 1194 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW); base 1195 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW); base 1196 drivers/memory/emif.c writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW); base 1561 drivers/memory/emif.c emif->base = devm_ioremap_resource(emif->dev, res); base 1562 drivers/memory/emif.c if (IS_ERR(emif->base)) base 1590 drivers/memory/emif.c __func__, emif->base, irq); base 52 drivers/memory/jz4780-nemc.c void __iomem *base; base 97 drivers/memory/jz4780-nemc.c nfcsr = readl(nemc->base + NEMC_NFCSR); base 110 drivers/memory/jz4780-nemc.c writel(nfcsr, nemc->base + NEMC_NFCSR); base 128 drivers/memory/jz4780-nemc.c nfcsr = readl(nemc->base + NEMC_NFCSR); base 135 drivers/memory/jz4780-nemc.c writel(nfcsr, nemc->base + NEMC_NFCSR); base 185 drivers/memory/jz4780-nemc.c smcr = readl(nemc->base + NEMC_SMCRn(bank)); base 264 drivers/memory/jz4780-nemc.c writel(smcr, nemc->base + NEMC_SMCRn(bank)); base 291 drivers/memory/jz4780-nemc.c nemc->base = devm_ioremap_resource(dev, res); base 292 drivers/memory/jz4780-nemc.c if (IS_ERR(nemc->base)) { base 294 drivers/memory/jz4780-nemc.c return PTR_ERR(nemc->base); base 297 drivers/memory/jz4780-nemc.c writel(0, nemc->base + NEMC_NFCSR); base 75 drivers/memory/mtk-smi.c void __iomem *base; /* only for gen2 */ base 82 drivers/memory/mtk-smi.c void __iomem *base; base 169 drivers/memory/mtk-smi.c reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); base 171 drivers/memory/mtk-smi.c writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); base 179 drivers/memory/mtk-smi.c writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN); base 283 drivers/memory/mtk-smi.c larb->base = devm_ioremap_resource(dev, res); base 284 drivers/memory/mtk-smi.c if (IS_ERR(larb->base)) base 285 drivers/memory/mtk-smi.c return PTR_ERR(larb->base); base 470 drivers/memory/mtk-smi.c common->base = devm_ioremap_resource(dev, res); base 471 drivers/memory/mtk-smi.c if (IS_ERR(common->base)) base 472 drivers/memory/mtk-smi.c return PTR_ERR(common->base); base 498 drivers/memory/mtk-smi.c writel(bus_sel, common->base + SMI_BUS_SEL); base 82 drivers/memory/mvebu-devbus.c void __iomem *base; base 225 drivers/memory/mvebu-devbus.c writel(value, devbus->base); base 245 drivers/memory/mvebu-devbus.c devbus->base + ARMADA_READ_PARAM_OFFSET, base 248 drivers/memory/mvebu-devbus.c writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET); base 257 drivers/memory/mvebu-devbus.c devbus->base + ARMADA_WRITE_PARAM_OFFSET, base 260 drivers/memory/mvebu-devbus.c writel(value, devbus->base + ARMADA_WRITE_PARAM_OFFSET); base 281 drivers/memory/mvebu-devbus.c devbus->base = devm_ioremap_resource(&pdev->dev, res); base 282 drivers/memory/mvebu-devbus.c if (IS_ERR(devbus->base)) base 283 drivers/memory/mvebu-devbus.c return PTR_ERR(devbus->base); base 801 drivers/memory/omap-gpmc.c static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) base 810 drivers/memory/omap-gpmc.c if (base & (size - 1)) base 813 drivers/memory/omap-gpmc.c base >>= GPMC_CHUNK_SHIFT; base 820 drivers/memory/omap-gpmc.c l |= base & GPMC_CONFIG7_BASEADDRESS_MASK; base 846 drivers/memory/omap-gpmc.c static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) base 852 drivers/memory/omap-gpmc.c *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; base 907 drivers/memory/omap-gpmc.c static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) base 915 drivers/memory/omap-gpmc.c res->start = base; base 916 drivers/memory/omap-gpmc.c res->end = base + size - 1; base 947 drivers/memory/omap-gpmc.c static int gpmc_cs_remap(int cs, u32 base) base 962 drivers/memory/omap-gpmc.c base &= ~(SZ_16M - 1); base 965 drivers/memory/omap-gpmc.c if (base == old_base) base 972 drivers/memory/omap-gpmc.c ret = gpmc_cs_insert_mem(cs, base, size); base 976 drivers/memory/omap-gpmc.c ret = gpmc_cs_set_memconf(cs, base, size); base 981 drivers/memory/omap-gpmc.c int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) base 1019 drivers/memory/omap-gpmc.c *base = res->start; base 1480 drivers/memory/omap-gpmc.c u32 base, size; base 1484 drivers/memory/omap-gpmc.c gpmc_cs_get_memconf(cs, &base, &size); base 1485 drivers/memory/omap-gpmc.c if (gpmc_cs_insert_mem(cs, base, size)) { base 1487 drivers/memory/omap-gpmc.c __func__, cs, base, base + size); base 2037 drivers/memory/omap-gpmc.c unsigned long base; base 2065 drivers/memory/omap-gpmc.c ret = gpmc_cs_request(cs, resource_size(&res), &base); base 2333 drivers/memory/omap-gpmc.c gpmc->gpio_chip.base = -1; base 54 drivers/memory/pl172.c void __iomem *base; base 76 drivers/memory/pl172.c writel(cycles, pl172->base + reg_offset); base 80 drivers/memory/pl172.c readl(pl172->base + reg_offset)); base 128 drivers/memory/pl172.c writel(cfg, pl172->base + MPMC_STATIC_CFG(cs)); base 247 drivers/memory/pl172.c pl172->base = devm_ioremap(dev, adev->res.start, base 249 drivers/memory/pl172.c if (!pl172->base) { base 159 drivers/memory/samsung/exynos-srom.c static void exynos_srom_save(void __iomem *base, base 164 drivers/memory/samsung/exynos-srom.c rd->value = readl(base + rd->offset); base 167 drivers/memory/samsung/exynos-srom.c static void exynos_srom_restore(void __iomem *base, base 172 drivers/memory/samsung/exynos-srom.c writel(rd->value, base + rd->offset); base 121 drivers/memory/ti-aemif.c void __iomem *base; base 209 drivers/memory/ti-aemif.c val = readl(aemif->base + offset); base 212 drivers/memory/ti-aemif.c writel(val, aemif->base + offset); base 239 drivers/memory/ti-aemif.c val = readl(aemif->base + offset); base 366 drivers/memory/ti-aemif.c aemif->base = devm_ioremap_resource(dev, res); base 367 drivers/memory/ti-aemif.c if (IS_ERR(aemif->base)) { base 368 drivers/memory/ti-aemif.c ret = PTR_ERR(aemif->base); base 29 drivers/mfd/altera-sysmgr.c resource_size_t *base; base 44 drivers/mfd/altera-sysmgr.c static int s10_protected_reg_write(void *base, base 48 drivers/mfd/altera-sysmgr.c unsigned long sysmgr_base = (unsigned long)base; base 66 drivers/mfd/altera-sysmgr.c static int s10_protected_reg_read(void *base, base 70 drivers/mfd/altera-sysmgr.c unsigned long sysmgr_base = (unsigned long)base; base 143 drivers/mfd/altera-sysmgr.c sysmgr->base = (resource_size_t *)res->start; base 147 drivers/mfd/altera-sysmgr.c regmap = devm_regmap_init(dev, NULL, sysmgr->base, base 150 drivers/mfd/altera-sysmgr.c sysmgr->base = devm_ioremap(dev, res->start, base 152 drivers/mfd/altera-sysmgr.c if (!sysmgr->base) base 156 drivers/mfd/altera-sysmgr.c regmap = devm_regmap_init_mmio(dev, sysmgr->base, base 125 drivers/mfd/asic3.c u32 base, int bit) base 132 drivers/mfd/asic3.c base + ASIC3_GPIO_EDGE_TRIGGER); base 135 drivers/mfd/asic3.c base + ASIC3_GPIO_EDGE_TRIGGER, edge); base 164 drivers/mfd/asic3.c unsigned long base, istat; base 166 drivers/mfd/asic3.c base = ASIC3_GPIO_A_BASE base 170 drivers/mfd/asic3.c base + base 174 drivers/mfd/asic3.c base + base 190 drivers/mfd/asic3.c asic3_irq_flip_edge(asic, base, base 996 drivers/mfd/asic3.c asic->gpio.base = pdata->gpio_base; base 32 drivers/mfd/atmel-flexcom.c void __iomem *base; base 59 drivers/mfd/atmel-flexcom.c ddata->base = devm_ioremap_resource(&pdev->dev, res); base 60 drivers/mfd/atmel-flexcom.c if (IS_ERR(ddata->base)) base 61 drivers/mfd/atmel-flexcom.c return PTR_ERR(ddata->base); base 77 drivers/mfd/atmel-flexcom.c writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR); base 102 drivers/mfd/atmel-flexcom.c writel(val, ddata->base + FLEX_MR); base 43 drivers/mfd/bcm2835-pm.c pm->base = devm_ioremap_resource(dev, res); base 44 drivers/mfd/bcm2835-pm.c if (IS_ERR(pm->base)) base 45 drivers/mfd/bcm2835-pm.c return PTR_ERR(pm->base); base 52 drivers/mfd/davinci_voicecodec.c davinci_vc->base = devm_ioremap_resource(&pdev->dev, res); base 53 drivers/mfd/davinci_voicecodec.c if (IS_ERR(davinci_vc->base)) { base 54 drivers/mfd/davinci_voicecodec.c ret = PTR_ERR(davinci_vc->base); base 59 drivers/mfd/davinci_voicecodec.c davinci_vc->base, base 183 drivers/mfd/dm355evm_msp.c .base = -EINVAL, /* dynamic assignment */ base 287 drivers/mfd/dm355evm_msp.c evm_leds[i].gpio = i + dm355evm_msp_gpio.base; base 303 drivers/mfd/dm355evm_msp.c int gpio = dm355evm_msp_gpio.base + config_inputs[i].offset; base 315 drivers/mfd/dm355evm_msp.c mmcsd_setup(dm355evm_msp_gpio.base + 8 + 5); base 57 drivers/mfd/hi6421-pmic-core.c void __iomem *base; base 70 drivers/mfd/hi6421-pmic-core.c base = devm_ioremap_resource(&pdev->dev, res); base 71 drivers/mfd/hi6421-pmic-core.c if (IS_ERR(base)) base 72 drivers/mfd/hi6421-pmic-core.c return PTR_ERR(base); base 74 drivers/mfd/hi6421-pmic-core.c pmic->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, base 98 drivers/mfd/hi655x-pmic.c void __iomem *base; base 106 drivers/mfd/hi655x-pmic.c base = devm_ioremap_resource(dev, pmic->res); base 107 drivers/mfd/hi655x-pmic.c if (IS_ERR(base)) base 108 drivers/mfd/hi655x-pmic.c return PTR_ERR(base); base 110 drivers/mfd/hi655x-pmic.c pmic->regmap = devm_regmap_init_mmio_clk(dev, NULL, base, base 418 drivers/mfd/htc-i2cpld.c gpio_chip->base = plat_chip_data->gpio_out_base; base 430 drivers/mfd/htc-i2cpld.c gpio_chip->base = plat_chip_data->gpio_in_base; base 55 drivers/mfd/ipaq-micro.c val = readl(micro->base + UTCR3); base 57 drivers/mfd/ipaq-micro.c writel(val, micro->base + UTCR3); base 176 drivers/mfd/ipaq-micro.c while ((status = readl(micro->base + UTSR1)) & UTSR1_RNE) { base 177 drivers/mfd/ipaq-micro.c ch = readl(micro->base + UTDR); base 287 drivers/mfd/ipaq-micro.c (readl(micro->base + UTSR1) & UTSR1_TNF)) { base 288 drivers/mfd/ipaq-micro.c writel(tx->buf[tx->index], micro->base + UTDR); base 293 drivers/mfd/ipaq-micro.c val = readl(micro->base + UTCR3); base 295 drivers/mfd/ipaq-micro.c writel(val, micro->base + UTCR3); base 313 drivers/mfd/ipaq-micro.c writel(0x0, micro->base + UTCR3); base 316 drivers/mfd/ipaq-micro.c writel(UTCR0_8BitData | UTCR0_1StpBit, micro->base + UTCR0); base 319 drivers/mfd/ipaq-micro.c writel(0x0, micro->base + UTCR1); base 320 drivers/mfd/ipaq-micro.c writel(0x1, micro->base + UTCR2); base 323 drivers/mfd/ipaq-micro.c writel(0xff, micro->base + UTSR0); base 326 drivers/mfd/ipaq-micro.c writel(UTCR3_TXE | UTCR3_RXE | UTCR3_RIE, micro->base + UTCR3); base 327 drivers/mfd/ipaq-micro.c val = readl(micro->base + UTCR3); base 329 drivers/mfd/ipaq-micro.c writel(val, micro->base + UTCR3); base 338 drivers/mfd/ipaq-micro.c status = readl(micro->base + UTSR0); base 343 drivers/mfd/ipaq-micro.c writel(UTSR0_RID, micro->base + UTSR0); base 350 drivers/mfd/ipaq-micro.c micro->base + UTSR0); base 355 drivers/mfd/ipaq-micro.c status = readl(micro->base + UTSR0); base 395 drivers/mfd/ipaq-micro.c micro->base = devm_ioremap_resource(&pdev->dev, res); base 396 drivers/mfd/ipaq-micro.c if (IS_ERR(micro->base)) base 397 drivers/mfd/ipaq-micro.c return PTR_ERR(micro->base); base 29 drivers/mfd/lm3533-ctrlbank.c static inline u8 lm3533_ctrlbank_get_reg(struct lm3533_ctrlbank *cb, u8 base) base 31 drivers/mfd/lm3533-ctrlbank.c return base + cb->id; base 111 drivers/mfd/omap-usb-host.c static inline void usbhs_write(void __iomem *base, u32 reg, u32 val) base 113 drivers/mfd/omap-usb-host.c writel_relaxed(val, base + reg); base 116 drivers/mfd/omap-usb-host.c static inline u32 usbhs_read(void __iomem *base, u32 reg) base 118 drivers/mfd/omap-usb-host.c return readl_relaxed(base + reg); base 100 drivers/mfd/omap-usb-tll.c void __iomem *base; base 113 drivers/mfd/omap-usb-tll.c static inline void usbtll_write(void __iomem *base, u32 reg, u32 val) base 115 drivers/mfd/omap-usb-tll.c writel_relaxed(val, base + reg); base 118 drivers/mfd/omap-usb-tll.c static inline u32 usbtll_read(void __iomem *base, u32 reg) base 120 drivers/mfd/omap-usb-tll.c return readl_relaxed(base + reg); base 123 drivers/mfd/omap-usb-tll.c static inline void usbtll_writeb(void __iomem *base, u32 reg, u8 val) base 125 drivers/mfd/omap-usb-tll.c writeb_relaxed(val, base + reg); base 128 drivers/mfd/omap-usb-tll.c static inline u8 usbtll_readb(void __iomem *base, u32 reg) base 130 drivers/mfd/omap-usb-tll.c return readb_relaxed(base + reg); base 208 drivers/mfd/omap-usb-tll.c void __iomem *base; base 214 drivers/mfd/omap-usb-tll.c base = devm_ioremap_resource(dev, res); base 215 drivers/mfd/omap-usb-tll.c if (IS_ERR(base)) base 216 drivers/mfd/omap-usb-tll.c return PTR_ERR(base); base 221 drivers/mfd/omap-usb-tll.c ver = usbtll_read(base, OMAP_USBTLL_REVISION); base 246 drivers/mfd/omap-usb-tll.c tll->base = base; base 333 drivers/mfd/omap-usb-tll.c void __iomem *base = tll->base; base 336 drivers/mfd/omap-usb-tll.c reg = usbtll_read(base, OMAP_TLL_SHARED_CONF); base 342 drivers/mfd/omap-usb-tll.c usbtll_write(base, OMAP_TLL_SHARED_CONF, reg); base 346 drivers/mfd/omap-usb-tll.c reg = usbtll_read(base, OMAP_TLL_CHANNEL_CONF(i)); base 375 drivers/mfd/omap-usb-tll.c usbtll_write(base, OMAP_TLL_CHANNEL_CONF(i), reg); base 377 drivers/mfd/omap-usb-tll.c usbtll_writeb(base, base 1018 drivers/mfd/sm501.c int base = pdata->gpio_base; base 1023 drivers/mfd/sm501.c if (base > 0) base 1024 drivers/mfd/sm501.c base += 32; base 1034 drivers/mfd/sm501.c gchip->base = base; base 68 drivers/mfd/ssbi.c void __iomem *base; base 77 drivers/mfd/ssbi.c return readl(ssbi->base + reg); base 82 drivers/mfd/ssbi.c writel(val, ssbi->base + reg); base 274 drivers/mfd/ssbi.c ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res); base 275 drivers/mfd/ssbi.c if (IS_ERR(ssbi->base)) base 276 drivers/mfd/ssbi.c return PTR_ERR(ssbi->base); base 1094 drivers/mfd/stmpe.c int base = irq_create_mapping(stmpe->domain, 0); base 1096 drivers/mfd/stmpe.c handle_nested_irq(base); base 1221 drivers/mfd/stmpe.c int base = 0; base 1224 drivers/mfd/stmpe.c stmpe->domain = irq_domain_add_simple(np, num_irqs, base, base 129 drivers/mfd/sun4i-gpadc.c dev->base = devm_ioremap_resource(&pdev->dev, mem); base 130 drivers/mfd/sun4i-gpadc.c if (IS_ERR(dev->base)) base 131 drivers/mfd/sun4i-gpadc.c return PTR_ERR(dev->base); base 136 drivers/mfd/sun4i-gpadc.c dev->regmap = devm_regmap_init_mmio(dev->dev, dev->base, base 48 drivers/mfd/syscon.c void __iomem *base; base 63 drivers/mfd/syscon.c base = ioremap(res.start, resource_size(&res)); base 64 drivers/mfd/syscon.c if (!base) { base 110 drivers/mfd/syscon.c regmap = regmap_init_mmio(NULL, base, &syscon_config); base 146 drivers/mfd/syscon.c iounmap(base); base 235 drivers/mfd/syscon.c void __iomem *base; base 245 drivers/mfd/syscon.c base = devm_ioremap(dev, res->start, resource_size(res)); base 246 drivers/mfd/syscon.c if (!base) base 252 drivers/mfd/syscon.c syscon->regmap = devm_regmap_init_mmio(dev, base, &syscon_config); base 503 drivers/mfd/tc6393xb.c tc6393xb->gpio.base = gpio_base; base 679 drivers/mfd/tc6393xb.c tc6393xb->gpio.base = -1; base 715 drivers/mfd/tc6393xb.c if (tc6393xb->gpio.base != -1) base 746 drivers/mfd/tc6393xb.c if (tc6393xb->gpio.base != -1) base 107 drivers/mfd/timberdale.c .base = 200 base 111 drivers/mfd/timberdale.c .base = 100 base 29 drivers/mfd/tmio_core.c int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base) base 33 drivers/mfd/tmio_core.c sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); base 48 drivers/mfd/tmio_core.c int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base) base 53 drivers/mfd/tmio_core.c sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); base 624 drivers/mfd/tps65010.c if (board && board->base != 0) { base 637 drivers/mfd/tps65010.c tps->chip.base = board->base; base 146 drivers/mfd/twl-core.c unsigned char base; /* base address */ base 448 drivers/mfd/twl-core.c ret = regmap_bulk_write(regmap, twl_priv->twl_map[mod_no].base + reg, base 476 drivers/mfd/twl-core.c ret = regmap_bulk_read(regmap, twl_priv->twl_map[mod_no].base + reg, base 1119 drivers/mfd/twl-core.c twl_priv->twl_map[TWL_MODULE_MAIN_CHARGE].base = base 50 drivers/mfd/ucb1x00-assabet.c buttons[i].gpio = ucb->gpio.base + i; base 543 drivers/mfd/ucb1x00-core.c ucb->gpio.base = -1; base 568 drivers/mfd/ucb1x00-core.c ucb->gpio.base = pdata->gpio_base; base 625 drivers/mfd/ucb1x00-core.c if (ucb->gpio.base != -1) base 47 drivers/mfd/vexpress-sysreg.c static void __iomem *base; base 49 drivers/mfd/vexpress-sysreg.c if (!base) { base 53 drivers/mfd/vexpress-sysreg.c base = of_iomap(node, 0); base 56 drivers/mfd/vexpress-sysreg.c if (WARN_ON(!base)) base 59 drivers/mfd/vexpress-sysreg.c writel(~0, base + SYS_FLAGSCLR); base 60 drivers/mfd/vexpress-sysreg.c writel(data, base + SYS_FLAGSSET); base 71 drivers/mfd/vexpress-sysreg.c .base = -1, base 77 drivers/mfd/vexpress-sysreg.c .base = -1, base 83 drivers/mfd/vexpress-sysreg.c .base = -1, base 159 drivers/mfd/vexpress-sysreg.c void __iomem *base; base 168 drivers/mfd/vexpress-sysreg.c base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); base 169 drivers/mfd/vexpress-sysreg.c if (!base) base 172 drivers/mfd/vexpress-sysreg.c master = readl(base + SYS_MISC) & SYS_MISC_MASTERSITE ? base 178 drivers/mfd/vexpress-sysreg.c u32 id = readl(base + (master == VEXPRESS_SITE_DB1 ? base 195 drivers/mfd/vexpress-sysreg.c bgpio_init(mmc_gpio_chip, &pdev->dev, 0x4, base + SYS_MCI, base 1439 drivers/misc/cardreader/rtsx_pcr.c u32 base, len; base 1488 drivers/misc/cardreader/rtsx_pcr.c base = pci_resource_start(pcidev, bar); base 1489 drivers/misc/cardreader/rtsx_pcr.c pcr->remap_addr = ioremap_nocache(base, len); base 37 drivers/misc/cs5535-mfgpt.c resource_size_t base; base 230 drivers/misc/cs5535-mfgpt.c return inw(timer->chip->base + reg + (timer->nr * 8)); base 237 drivers/misc/cs5535-mfgpt.c outw(value, timer->chip->base + reg + (timer->nr * 8)); base 346 drivers/misc/cs5535-mfgpt.c cs5535_mfgpt_chip.base = res->start; base 2826 drivers/misc/habanalabs/goya/goya.c void *base; base 2831 drivers/misc/habanalabs/goya/goya.c base = (void *) hdev->pcie_bar[SRAM_CFG_BAR_ID]; base 2875 drivers/misc/habanalabs/goya/goya.c base += offset; base 2878 drivers/misc/habanalabs/goya/goya.c return base; base 18 drivers/misc/habanalabs/goya/goya_security.c static void goya_pb_set_block(struct hl_device *hdev, u64 base) base 20 drivers/misc/habanalabs/goya/goya_security.c u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; base 32 drivers/misc/lkdtm/heap.c int *base, *again; base 39 drivers/misc/lkdtm/heap.c size_t offset = (len / sizeof(*base)) / 2; base 41 drivers/misc/lkdtm/heap.c base = kmalloc(len, GFP_KERNEL); base 42 drivers/misc/lkdtm/heap.c if (!base) base 44 drivers/misc/lkdtm/heap.c pr_info("Allocated memory %p-%p\n", base, &base[offset * 2]); base 46 drivers/misc/lkdtm/heap.c &base[offset]); base 47 drivers/misc/lkdtm/heap.c kfree(base); base 48 drivers/misc/lkdtm/heap.c base[offset] = 0x0abcdef0; base 52 drivers/misc/lkdtm/heap.c if (again != base) base 58 drivers/misc/lkdtm/heap.c int *base, *val, saw; base 65 drivers/misc/lkdtm/heap.c size_t offset = (len / sizeof(*base)) / 2; base 67 drivers/misc/lkdtm/heap.c base = kmalloc(len, GFP_KERNEL); base 68 drivers/misc/lkdtm/heap.c if (!base) { base 76 drivers/misc/lkdtm/heap.c kfree(base); base 81 drivers/misc/lkdtm/heap.c base[offset] = *val; base 82 drivers/misc/lkdtm/heap.c pr_info("Value in memory before free: %x\n", base[offset]); base 84 drivers/misc/lkdtm/heap.c kfree(base); base 87 drivers/misc/lkdtm/heap.c saw = base[offset]; base 122 drivers/misc/lkdtm/heap.c int *base; base 136 drivers/misc/lkdtm/heap.c base = (int *)p; base 139 drivers/misc/lkdtm/heap.c base[0] = *val; base 140 drivers/misc/lkdtm/heap.c pr_info("Value in memory before free: %x\n", base[0]); base 143 drivers/misc/lkdtm/heap.c saw = base[0]; base 779 drivers/misc/mei/hdcp/mei_hdcp.c struct device *base = data; base 785 drivers/misc/mei/hdcp/mei_hdcp.c base = base->parent; base 786 drivers/misc/mei/hdcp/mei_hdcp.c if (!base) base 789 drivers/misc/mei/hdcp/mei_hdcp.c base = base->parent; base 792 drivers/misc/mei/hdcp/mei_hdcp.c return (base && dev && dev == base); base 22 drivers/misc/mic/host/mic_smpt.c return (pa - mdev->smpt->info.base) >> mdev->smpt->info.page_shift; base 27 drivers/misc/mic/host/mic_smpt.c return mdev->smpt->info.base + (index * mdev->smpt->info.page_size); base 55 drivers/misc/mic/host/mic_smpt.c return mdev->smpt->info.base + mic_max_system_memory(mdev) - 1ULL; base 62 drivers/misc/mic/host/mic_smpt.c return pa >= mdev->smpt->info.base && pa <= mic_max_system_addr(mdev); base 42 drivers/misc/mic/host/mic_smpt.h u64 base; base 534 drivers/misc/mic/host/mic_x100.c info->base = 0x8000000000ULL; base 642 drivers/misc/ocxl/config.c int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled, base 652 drivers/misc/ocxl/config.c rc = pnv_ocxl_get_actag(dev, base, enabled, supported); base 343 drivers/misc/ocxl/core.c u16 base, enabled, supported; base 346 drivers/misc/ocxl/core.c rc = ocxl_config_get_actag_info(dev, &base, &enabled, &supported); base 350 drivers/misc/ocxl/core.c fn->actag_base = base; base 96 drivers/misc/pci_endpoint_test.c void __iomem *base; base 118 drivers/misc/pci_endpoint_test.c return readl(test->base + offset); base 124 drivers/misc/pci_endpoint_test.c writel(value, test->base + offset); base 643 drivers/misc/pci_endpoint_test.c void __iomem *base; base 698 drivers/misc/pci_endpoint_test.c base = pci_ioremap_bar(pdev, bar); base 699 drivers/misc/pci_endpoint_test.c if (!base) { base 703 drivers/misc/pci_endpoint_test.c test->bar[bar] = base; base 707 drivers/misc/pci_endpoint_test.c test->base = test->bar[test_reg_bar]; base 708 drivers/misc/pci_endpoint_test.c if (!test->base) { base 19 drivers/misc/pvpanic.c static void __iomem *base; base 30 drivers/misc/pvpanic.c iowrite8(event, base); base 74 drivers/misc/pvpanic.c base = ioport_map(r.start, resource_size(&r)); base 80 drivers/misc/pvpanic.c base = ioremap(r.start, resource_size(&r)); base 101 drivers/misc/pvpanic.c if (!base) base 115 drivers/misc/pvpanic.c iounmap(base); base 146 drivers/misc/pvpanic.c base = devm_ioremap_resource(&pdev->dev, mem); base 147 drivers/misc/pvpanic.c if (IS_ERR(base)) base 148 drivers/misc/pvpanic.c return PTR_ERR(base); base 88 drivers/misc/sgi-gru/gruhandles.h static inline void *get_gseg_base_address(void *base, int ctxnum) base 90 drivers/misc/sgi-gru/gruhandles.h return (void *)(base + GRU_GSEG0_BASE + GRU_GSEG_STRIDE * ctxnum); base 93 drivers/misc/sgi-gru/gruhandles.h static inline void *get_gseg_base_address_cb(void *base, int ctxnum, int line) base 95 drivers/misc/sgi-gru/gruhandles.h return (void *)(get_gseg_base_address(base, ctxnum) + base 99 drivers/misc/sgi-gru/gruhandles.h static inline void *get_gseg_base_address_ds(void *base, int ctxnum, int line) base 101 drivers/misc/sgi-gru/gruhandles.h return (void *)(get_gseg_base_address(base, ctxnum) + GRU_DS_BASE + base 105 drivers/misc/sgi-gru/gruhandles.h static inline struct gru_tlb_fault_map *get_tfm(void *base, int ctxnum) base 107 drivers/misc/sgi-gru/gruhandles.h return (struct gru_tlb_fault_map *)(base + GRU_TFM_BASE + base 111 drivers/misc/sgi-gru/gruhandles.h static inline struct gru_tlb_global_handle *get_tgh(void *base, int ctxnum) base 113 drivers/misc/sgi-gru/gruhandles.h return (struct gru_tlb_global_handle *)(base + GRU_TGH_BASE + base 117 drivers/misc/sgi-gru/gruhandles.h static inline struct gru_control_block_extended *get_cbe(void *base, int ctxnum) base 119 drivers/misc/sgi-gru/gruhandles.h return (struct gru_control_block_extended *)(base + GRU_CBE_BASE + base 123 drivers/misc/sgi-gru/gruhandles.h static inline struct gru_tlb_fault_handle *get_tfh(void *base, int ctxnum) base 125 drivers/misc/sgi-gru/gruhandles.h return (struct gru_tlb_fault_handle *)(base + GRU_TFH_BASE + base 129 drivers/misc/sgi-gru/gruhandles.h static inline struct gru_context_configuration_handle *get_cch(void *base, base 132 drivers/misc/sgi-gru/gruhandles.h return (struct gru_context_configuration_handle *)(base + base 375 drivers/misc/sgi-xp/xpc_main.c xpc_kzalloc_cacheline_aligned(size_t size, gfp_t flags, void **base) base 378 drivers/misc/sgi-xp/xpc_main.c *base = kzalloc(size, flags); base 379 drivers/misc/sgi-xp/xpc_main.c if (*base == NULL) base 382 drivers/misc/sgi-xp/xpc_main.c if ((u64)*base == L1_CACHE_ALIGN((u64)*base)) base 383 drivers/misc/sgi-xp/xpc_main.c return *base; base 385 drivers/misc/sgi-xp/xpc_main.c kfree(*base); base 388 drivers/misc/sgi-xp/xpc_main.c *base = kzalloc(size + L1_CACHE_BYTES, flags); base 389 drivers/misc/sgi-xp/xpc_main.c if (*base == NULL) base 392 drivers/misc/sgi-xp/xpc_main.c return (void *)L1_CACHE_ALIGN((u64)*base); base 41 drivers/misc/sgi-xp/xpc_partition.c xpc_kmalloc_cacheline_aligned(size_t size, gfp_t flags, void **base) base 44 drivers/misc/sgi-xp/xpc_partition.c *base = kmalloc(size, flags); base 45 drivers/misc/sgi-xp/xpc_partition.c if (*base == NULL) base 48 drivers/misc/sgi-xp/xpc_partition.c if ((u64)*base == L1_CACHE_ALIGN((u64)*base)) base 49 drivers/misc/sgi-xp/xpc_partition.c return *base; base 51 drivers/misc/sgi-xp/xpc_partition.c kfree(*base); base 54 drivers/misc/sgi-xp/xpc_partition.c *base = kmalloc(size + L1_CACHE_BYTES, flags); base 55 drivers/misc/sgi-xp/xpc_partition.c if (*base == NULL) base 58 drivers/misc/sgi-xp/xpc_partition.c return (void *)L1_CACHE_ALIGN((u64)*base); base 33 drivers/misc/sram-exec.c unsigned long base = (unsigned long)part->base; base 34 drivers/misc/sram-exec.c unsigned long end = base + block->size; base 36 drivers/misc/sram-exec.c if (!PAGE_ALIGNED(base) || !PAGE_ALIGNED(end)) { base 85 drivers/misc/sram-exec.c unsigned long base; base 102 drivers/misc/sram-exec.c base = (unsigned long)part->base; base 107 drivers/misc/sram-exec.c set_memory_nx((unsigned long)base, pages); base 108 drivers/misc/sram-exec.c set_memory_rw((unsigned long)base, pages); base 112 drivers/misc/sram-exec.c set_memory_ro((unsigned long)base, pages); base 113 drivers/misc/sram-exec.c set_memory_x((unsigned long)base, pages); base 34 drivers/misc/sram.c memcpy_fromio(buf, part->base + pos, count); base 49 drivers/misc/sram.c memcpy_toio(part->base + pos, buf, count); base 65 drivers/misc/sram.c ret = gen_pool_add_virt(part->pool, (unsigned long)part->base, start, base 100 drivers/misc/sram.c part->base = sram->virt_base + block->start; base 9 drivers/misc/sram.h void __iomem *base; base 36 drivers/misc/vexpress-syscfg.c void __iomem *base; base 60 drivers/misc/vexpress-syscfg.c command = readl(syscfg->base + SYS_CFGCTRL); base 74 drivers/misc/vexpress-syscfg.c writel(*data, syscfg->base + SYS_CFGDATA); base 75 drivers/misc/vexpress-syscfg.c writel(0, syscfg->base + SYS_CFGSTAT); base 76 drivers/misc/vexpress-syscfg.c writel(command, syscfg->base + SYS_CFGCTRL); base 92 drivers/misc/vexpress-syscfg.c status = readl(syscfg->base + SYS_CFGSTAT); base 103 drivers/misc/vexpress-syscfg.c *data = readl(syscfg->base + SYS_CFGDATA); base 254 drivers/misc/vexpress-syscfg.c syscfg->base = devm_ioremap_resource(&pdev->dev, res); base 255 drivers/misc/vexpress-syscfg.c if (IS_ERR(syscfg->base)) base 256 drivers/misc/vexpress-syscfg.c return PTR_ERR(syscfg->base); base 468 drivers/mmc/core/mmc_test.c void *base, *addr, *last_addr = NULL; base 474 drivers/mmc/core/mmc_test.c base = page_address(mem->arr[--i].page); base 477 drivers/mmc/core/mmc_test.c addr = base + PAGE_SIZE * --cnt; base 110 drivers/mmc/host/cavium-octeon.c writeq(val, host->base + MIO_EMM_INT(host)); base 112 drivers/mmc/host/cavium-octeon.c writeq(val, host->base + MIO_EMM_INT_EN(host)); base 152 drivers/mmc/host/cavium-octeon.c void __iomem *base; base 213 drivers/mmc/host/cavium-octeon.c base = devm_ioremap_resource(&pdev->dev, res); base 214 drivers/mmc/host/cavium-octeon.c if (IS_ERR(base)) base 215 drivers/mmc/host/cavium-octeon.c return PTR_ERR(base); base 216 drivers/mmc/host/cavium-octeon.c host->base = (void __iomem *)base; base 224 drivers/mmc/host/cavium-octeon.c base = devm_ioremap_resource(&pdev->dev, res); base 225 drivers/mmc/host/cavium-octeon.c if (IS_ERR(base)) base 226 drivers/mmc/host/cavium-octeon.c return PTR_ERR(base); base 227 drivers/mmc/host/cavium-octeon.c host->dma_base = (void __iomem *)base; base 243 drivers/mmc/host/cavium-octeon.c val = readq(host->base + MIO_EMM_INT(host)); base 244 drivers/mmc/host/cavium-octeon.c writeq(val, host->base + MIO_EMM_INT(host)); base 32 drivers/mmc/host/cavium-thunderx.c writeq(val, host->base + MIO_EMM_INT(host)); base 33 drivers/mmc/host/cavium-thunderx.c writeq(val, host->base + MIO_EMM_INT_EN_SET(host)); base 78 drivers/mmc/host/cavium-thunderx.c host->base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0)); base 79 drivers/mmc/host/cavium-thunderx.c if (!host->base) base 83 drivers/mmc/host/cavium-thunderx.c host->dma_base = host->base; base 118 drivers/mmc/host/cavium-thunderx.c writeq(127, host->base + MIO_EMM_INT_EN(host)); base 119 drivers/mmc/host/cavium-thunderx.c writeq(3, host->base + MIO_EMM_DMA_INT_ENA_W1C(host)); base 121 drivers/mmc/host/cavium-thunderx.c writeq(BIT_ULL(16), host->base + MIO_EMM_DMA_FIFO_CFG(host)); base 169 drivers/mmc/host/cavium.c emm_switch = readq(host->base + MIO_EMM_SWITCH(host)); base 212 drivers/mmc/host/cavium.c writeq(emm_switch, host->base + MIO_EMM_SWITCH(host)); base 215 drivers/mmc/host/cavium.c writeq(emm_switch, host->base + MIO_EMM_SWITCH(host)); base 219 drivers/mmc/host/cavium.c rsp_sts = readq(host->base + MIO_EMM_RSP_STS(host)); base 247 drivers/mmc/host/cavium.c writeq(timeout, slot->host->base + MIO_EMM_WDOG(slot->host)); base 255 drivers/mmc/host/cavium.c emm_switch = readq(slot->host->base + MIO_EMM_SWITCH(host)); base 260 drivers/mmc/host/cavium.c wdog = readq(slot->host->base + MIO_EMM_WDOG(host)); base 267 drivers/mmc/host/cavium.c writeq(wdog, slot->host->base + MIO_EMM_WDOG(host)); base 282 drivers/mmc/host/cavium.c old_slot->cached_switch = readq(host->base + MIO_EMM_SWITCH(host)); base 283 drivers/mmc/host/cavium.c old_slot->cached_rca = readq(host->base + MIO_EMM_RCA(host)); base 286 drivers/mmc/host/cavium.c writeq(slot->cached_rca, host->base + MIO_EMM_RCA(host)); base 293 drivers/mmc/host/cavium.c writeq(emm_sample, host->base + MIO_EMM_SAMPLE(host)); base 307 drivers/mmc/host/cavium.c writeq((0x10000 | (dbuf << 6)), host->base + MIO_EMM_BUF_IDX(host)); base 317 drivers/mmc/host/cavium.c dat = readq(host->base + MIO_EMM_BUF_DAT(host)); base 348 drivers/mmc/host/cavium.c rsp_lo = readq(host->base + MIO_EMM_RSP_LO(host)); base 361 drivers/mmc/host/cavium.c rsp_hi = readq(host->base + MIO_EMM_RSP_HI(host)); base 428 drivers/mmc/host/cavium.c emm_dma = readq(host->base + MIO_EMM_DMA(host)); base 432 drivers/mmc/host/cavium.c writeq(emm_dma, host->base + MIO_EMM_DMA(host)); base 449 drivers/mmc/host/cavium.c emm_int = readq(host->base + MIO_EMM_INT(host)); base 450 drivers/mmc/host/cavium.c writeq(emm_int, host->base + MIO_EMM_INT(host)); base 459 drivers/mmc/host/cavium.c rsp_sts = readq(host->base + MIO_EMM_RSP_STS(host)); base 696 drivers/mmc/host/cavium.c writeq(0x00b00000ull, host->base + MIO_EMM_STS_MASK(host)); base 698 drivers/mmc/host/cavium.c writeq(0xe4390080ull, host->base + MIO_EMM_STS_MASK(host)); base 699 drivers/mmc/host/cavium.c writeq(emm_dma, host->base + MIO_EMM_DMA(host)); base 727 drivers/mmc/host/cavium.c writeq(0x10000ull, host->base + MIO_EMM_BUF_IDX(host)); base 744 drivers/mmc/host/cavium.c writeq(dat, host->base + MIO_EMM_BUF_DAT(host)); base 807 drivers/mmc/host/cavium.c writeq(0, host->base + MIO_EMM_STS_MASK(host)); base 810 drivers/mmc/host/cavium.c rsp_sts = readq(host->base + MIO_EMM_RSP_STS(host)); base 821 drivers/mmc/host/cavium.c writeq(emm_cmd, host->base + MIO_EMM_CMD(host)); base 922 drivers/mmc/host/cavium.c writeq(host->emm_cfg, slot->host->base + MIO_EMM_CFG(host)); base 946 drivers/mmc/host/cavium.c writeq(0xe4390080ull, host->base + MIO_EMM_STS_MASK(host)); base 947 drivers/mmc/host/cavium.c writeq(1, host->base + MIO_EMM_RCA(host)); base 57 drivers/mmc/host/cavium.h void __iomem *base; base 174 drivers/mmc/host/davinci_mmc.c void __iomem *base; base 248 drivers/mmc/host/davinci_mmc.c writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); base 252 drivers/mmc/host/davinci_mmc.c iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); base 257 drivers/mmc/host/davinci_mmc.c *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); base 261 drivers/mmc/host/davinci_mmc.c ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); base 343 drivers/mmc/host/davinci_mmc.c writel(0x1FFF, host->base + DAVINCI_MMCTOR); base 366 drivers/mmc/host/davinci_mmc.c writel(cmd->arg, host->base + DAVINCI_MMCARGHL); base 367 drivers/mmc/host/davinci_mmc.c writel(cmd_reg, host->base + DAVINCI_MMCCMD); base 381 drivers/mmc/host/davinci_mmc.c writel(im_val, host->base + DAVINCI_MMCIM); base 528 drivers/mmc/host/davinci_mmc.c writel(0, host->base + DAVINCI_MMCBLEN); base 529 drivers/mmc/host/davinci_mmc.c writel(0, host->base + DAVINCI_MMCNBLK); base 543 drivers/mmc/host/davinci_mmc.c writel(timeout, host->base + DAVINCI_MMCTOD); base 544 drivers/mmc/host/davinci_mmc.c writel(data->blocks, host->base + DAVINCI_MMCNBLK); base 545 drivers/mmc/host/davinci_mmc.c writel(data->blksz, host->base + DAVINCI_MMCBLEN); base 551 drivers/mmc/host/davinci_mmc.c host->base + DAVINCI_MMCFIFOCTL); base 553 drivers/mmc/host/davinci_mmc.c host->base + DAVINCI_MMCFIFOCTL); base 557 drivers/mmc/host/davinci_mmc.c host->base + DAVINCI_MMCFIFOCTL); base 559 drivers/mmc/host/davinci_mmc.c host->base + DAVINCI_MMCFIFOCTL); base 595 drivers/mmc/host/davinci_mmc.c mmcst1 = readl(host->base + DAVINCI_MMCST1); base 658 drivers/mmc/host/davinci_mmc.c temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; base 660 drivers/mmc/host/davinci_mmc.c writel(temp, host->base + DAVINCI_MMCCLK); base 671 drivers/mmc/host/davinci_mmc.c temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; base 672 drivers/mmc/host/davinci_mmc.c writel(temp, host->base + DAVINCI_MMCCLK); base 676 drivers/mmc/host/davinci_mmc.c temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; base 678 drivers/mmc/host/davinci_mmc.c writel(temp, host->base + DAVINCI_MMCCLK); base 680 drivers/mmc/host/davinci_mmc.c writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); base 711 drivers/mmc/host/davinci_mmc.c writel((readl(host->base + DAVINCI_MMCCTL) & base 713 drivers/mmc/host/davinci_mmc.c host->base + DAVINCI_MMCCTL); base 718 drivers/mmc/host/davinci_mmc.c writel((readl(host->base + DAVINCI_MMCCTL) & base 720 drivers/mmc/host/davinci_mmc.c host->base + DAVINCI_MMCCTL); base 722 drivers/mmc/host/davinci_mmc.c writel(readl(host->base + DAVINCI_MMCCTL) | base 724 drivers/mmc/host/davinci_mmc.c host->base + DAVINCI_MMCCTL); base 729 drivers/mmc/host/davinci_mmc.c writel(readl(host->base + DAVINCI_MMCCTL) & base 731 drivers/mmc/host/davinci_mmc.c host->base + DAVINCI_MMCCTL); base 733 drivers/mmc/host/davinci_mmc.c writel(readl(host->base + DAVINCI_MMCCTL) & base 735 drivers/mmc/host/davinci_mmc.c host->base + DAVINCI_MMCCTL); base 747 drivers/mmc/host/davinci_mmc.c writel(0, host->base + DAVINCI_MMCARGHL); base 748 drivers/mmc/host/davinci_mmc.c writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); base 750 drivers/mmc/host/davinci_mmc.c u32 tmp = readl(host->base + DAVINCI_MMCST0); base 776 drivers/mmc/host/davinci_mmc.c if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) & base 778 drivers/mmc/host/davinci_mmc.c writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); base 794 drivers/mmc/host/davinci_mmc.c writel(0, host->base + DAVINCI_MMCIM); base 808 drivers/mmc/host/davinci_mmc.c cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); base 809 drivers/mmc/host/davinci_mmc.c cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); base 810 drivers/mmc/host/davinci_mmc.c cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); base 811 drivers/mmc/host/davinci_mmc.c cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); base 814 drivers/mmc/host/davinci_mmc.c cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); base 822 drivers/mmc/host/davinci_mmc.c writel(0, host->base + DAVINCI_MMCIM); base 832 drivers/mmc/host/davinci_mmc.c temp = readl(host->base + DAVINCI_MMCCTL); base 838 drivers/mmc/host/davinci_mmc.c writel(temp, host->base + DAVINCI_MMCCTL); base 854 drivers/mmc/host/davinci_mmc.c status = readl(host->base + DAVINCI_SDIOIST); base 858 drivers/mmc/host/davinci_mmc.c writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); base 873 drivers/mmc/host/davinci_mmc.c status = readl(host->base + DAVINCI_MMCST0); base 877 drivers/mmc/host/davinci_mmc.c writel(0, host->base + DAVINCI_MMCIM); base 881 drivers/mmc/host/davinci_mmc.c status = readl(host->base + DAVINCI_MMCST0); base 901 drivers/mmc/host/davinci_mmc.c im_val = readl(host->base + DAVINCI_MMCIM); base 902 drivers/mmc/host/davinci_mmc.c writel(0, host->base + DAVINCI_MMCIM); base 906 drivers/mmc/host/davinci_mmc.c status = readl(host->base + DAVINCI_MMCST0); base 917 drivers/mmc/host/davinci_mmc.c writel(im_val, host->base + DAVINCI_MMCIM); base 961 drivers/mmc/host/davinci_mmc.c u32 temp = readb(host->base + DAVINCI_MMCDRSP); base 1036 drivers/mmc/host/davinci_mmc.c if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) { base 1037 drivers/mmc/host/davinci_mmc.c writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); base 1041 drivers/mmc/host/davinci_mmc.c writel(readl(host->base + DAVINCI_SDIOIEN) | base 1042 drivers/mmc/host/davinci_mmc.c SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN); base 1046 drivers/mmc/host/davinci_mmc.c writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, base 1047 drivers/mmc/host/davinci_mmc.c host->base + DAVINCI_SDIOIEN); base 1112 drivers/mmc/host/davinci_mmc.c writel(0, host->base + DAVINCI_MMCCLK); base 1113 drivers/mmc/host/davinci_mmc.c writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); base 1115 drivers/mmc/host/davinci_mmc.c writel(0x1FFF, host->base + DAVINCI_MMCTOR); base 1116 drivers/mmc/host/davinci_mmc.c writel(0xFFFF, host->base + DAVINCI_MMCTOD); base 1221 drivers/mmc/host/davinci_mmc.c host->base = devm_ioremap(&pdev->dev, mem->start, mem_size); base 1222 drivers/mmc/host/davinci_mmc.c if (!host->base) { base 1369 drivers/mmc/host/davinci_mmc.c writel(0, host->base + DAVINCI_MMCIM); base 145 drivers/mmc/host/jz4740_mmc.c void __iomem *base; base 178 drivers/mmc/host/jz4740_mmc.c return writel(val, host->base + JZ_REG_MMC_IMASK); base 180 drivers/mmc/host/jz4740_mmc.c return writew(val, host->base + JZ_REG_MMC_IMASK); base 187 drivers/mmc/host/jz4740_mmc.c writel(val, host->base + JZ_REG_MMC_IREG); base 189 drivers/mmc/host/jz4740_mmc.c writew(val, host->base + JZ_REG_MMC_IREG); base 195 drivers/mmc/host/jz4740_mmc.c return readl(host->base + JZ_REG_MMC_IREG); base 197 drivers/mmc/host/jz4740_mmc.c return readw(host->base + JZ_REG_MMC_IREG); base 380 drivers/mmc/host/jz4740_mmc.c writew(val, host->base + JZ_REG_MMC_STRPCL); base 388 drivers/mmc/host/jz4740_mmc.c writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); base 390 drivers/mmc/host/jz4740_mmc.c status = readl(host->base + JZ_REG_MMC_STATUS); base 399 drivers/mmc/host/jz4740_mmc.c writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); base 402 drivers/mmc/host/jz4740_mmc.c status = readl(host->base + JZ_REG_MMC_STATUS); base 445 drivers/mmc/host/jz4740_mmc.c status = readl(host->base + JZ_REG_MMC_STATUS); base 469 drivers/mmc/host/jz4740_mmc.c void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO; base 524 drivers/mmc/host/jz4740_mmc.c void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO; base 579 drivers/mmc/host/jz4740_mmc.c status = readl(host->base + JZ_REG_MMC_STATUS); base 582 drivers/mmc/host/jz4740_mmc.c status = readl(host->base + JZ_REG_MMC_STATUS); base 613 drivers/mmc/host/jz4740_mmc.c void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO; base 675 drivers/mmc/host/jz4740_mmc.c host->base + JZ_REG_MMC_DMAC); base 680 drivers/mmc/host/jz4740_mmc.c writel(0, host->base + JZ_REG_MMC_DMAC); base 683 drivers/mmc/host/jz4740_mmc.c writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); base 684 drivers/mmc/host/jz4740_mmc.c writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); base 687 drivers/mmc/host/jz4740_mmc.c writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); base 688 drivers/mmc/host/jz4740_mmc.c writel(cmd->arg, host->base + JZ_REG_MMC_ARG); base 689 drivers/mmc/host/jz4740_mmc.c writel(cmdat, host->base + JZ_REG_MMC_CMDAT); base 796 drivers/mmc/host/jz4740_mmc.c status = readl(host->base + JZ_REG_MMC_STATUS); base 854 drivers/mmc/host/jz4740_mmc.c writew(div, host->base + JZ_REG_MMC_CLKRT); base 979 drivers/mmc/host/jz4740_mmc.c host->base = devm_ioremap_resource(&pdev->dev, host->mem_res); base 980 drivers/mmc/host/jz4740_mmc.c if (IS_ERR(host->base)) { base 981 drivers/mmc/host/jz4740_mmc.c ret = PTR_ERR(host->base); base 111 drivers/mmc/host/meson-mx-sdio.c void __iomem *base; base 131 drivers/mmc/host/meson-mx-sdio.c regval = readl(host->base + reg); base 135 drivers/mmc/host/meson-mx-sdio.c writel(regval, host->base + reg); base 140 drivers/mmc/host/meson-mx-sdio.c writel(MESON_MX_SDIO_IRQC_SOFT_RESET, host->base + MESON_MX_SDIO_IRQC); base 218 drivers/mmc/host/meson-mx-sdio.c mult = readl(host->base + MESON_MX_SDIO_MULT); base 222 drivers/mmc/host/meson-mx-sdio.c writel(mult, host->base + MESON_MX_SDIO_MULT); base 234 drivers/mmc/host/meson-mx-sdio.c writel(cmd->arg, host->base + MESON_MX_SDIO_ARGU); base 235 drivers/mmc/host/meson-mx-sdio.c writel(ext, host->base + MESON_MX_SDIO_EXT); base 236 drivers/mmc/host/meson-mx-sdio.c writel(send, host->base + MESON_MX_SDIO_SEND); base 352 drivers/mmc/host/meson-mx-sdio.c host->base + MESON_MX_SDIO_ADDR); base 367 drivers/mmc/host/meson-mx-sdio.c mult = readl(host->base + MESON_MX_SDIO_MULT); base 371 drivers/mmc/host/meson-mx-sdio.c writel(mult, host->base + MESON_MX_SDIO_MULT); base 375 drivers/mmc/host/meson-mx-sdio.c resp[3 - i] = readl(host->base + MESON_MX_SDIO_ARGU); base 381 drivers/mmc/host/meson-mx-sdio.c cmd->resp[0] = readl(host->base + MESON_MX_SDIO_ARGU); base 423 drivers/mmc/host/meson-mx-sdio.c irqs = readl(host->base + MESON_MX_SDIO_IRQS); base 424 drivers/mmc/host/meson-mx-sdio.c send = readl(host->base + MESON_MX_SDIO_SEND); base 432 drivers/mmc/host/meson-mx-sdio.c writel(irqs, host->base + MESON_MX_SDIO_IRQS); base 475 drivers/mmc/host/meson-mx-sdio.c irqc = readl(host->base + MESON_MX_SDIO_IRQC); base 477 drivers/mmc/host/meson-mx-sdio.c writel(irqc, host->base + MESON_MX_SDIO_IRQC); base 490 drivers/mmc/host/meson-mx-sdio.c host->cmd->opcode, readl(host->base + MESON_MX_SDIO_IRQS), base 491 drivers/mmc/host/meson-mx-sdio.c readl(host->base + MESON_MX_SDIO_ARGU)); base 613 drivers/mmc/host/meson-mx-sdio.c host->cfg_div.reg = host->base + MESON_MX_SDIO_CONF; base 658 drivers/mmc/host/meson-mx-sdio.c host->base = devm_ioremap_resource(host->controller_dev, res); base 659 drivers/mmc/host/meson-mx-sdio.c if (IS_ERR(host->base)) { base 660 drivers/mmc/host/meson-mx-sdio.c ret = PTR_ERR(host->base); base 705 drivers/mmc/host/meson-mx-sdio.c writel(conf, host->base + MESON_MX_SDIO_CONF); base 302 drivers/mmc/host/mmci.c if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) base 331 drivers/mmc/host/mmci.c writel(clk, host->base + MMCICLOCK); base 342 drivers/mmc/host/mmci.c writel(pwr, host->base + MMCIPOWER); base 356 drivers/mmc/host/mmci.c writel(datactrl, host->base + MMCIDATACTRL); base 528 drivers/mmc/host/mmci.c writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, base 529 drivers/mmc/host/mmci.c host->base + MMCIMASK0); base 554 drivers/mmc/host/mmci.c writel(0, host->base + MMCICOMMAND); base 566 drivers/mmc/host/mmci.c void __iomem *base = host->base; base 570 drivers/mmc/host/mmci.c unsigned int mask0 = readl(base + MMCIMASK0); base 575 drivers/mmc/host/mmci.c writel(mask0, base + MMCIMASK0); base 579 drivers/mmc/host/mmci.c writel(mask, base + MMCIMASK1); base 753 drivers/mmc/host/mmci.c status = readl(host->base + MMCISTATUS); base 995 drivers/mmc/host/mmci.c void __iomem *base; base 1009 drivers/mmc/host/mmci.c base = host->base; base 1010 drivers/mmc/host/mmci.c writel(timeout, base + MMCIDATATIMER); base 1011 drivers/mmc/host/mmci.c writel(host->size, base + MMCIDATALENGTH); base 1070 drivers/mmc/host/mmci.c writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); base 1077 drivers/mmc/host/mmci.c void __iomem *base = host->base; base 1082 drivers/mmc/host/mmci.c if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { base 1083 drivers/mmc/host/mmci.c writel(0, base + MMCICOMMAND); base 1108 drivers/mmc/host/mmci.c writel(cmd->arg, base + MMCIARGUMENT); base 1109 drivers/mmc/host/mmci.c writel(c, base + MMCICOMMAND); base 1147 drivers/mmc/host/mmci.c remain = readl(host->base + MMCIDATACNT); base 1204 drivers/mmc/host/mmci.c void __iomem *base = host->base; base 1240 drivers/mmc/host/mmci.c (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { base 1242 drivers/mmc/host/mmci.c writel(readl(base + MMCIMASK0) | base 1244 drivers/mmc/host/mmci.c base + MMCIMASK0); base 1265 drivers/mmc/host/mmci.c host->base + MMCICLEAR); base 1278 drivers/mmc/host/mmci.c host->base + MMCICLEAR); base 1280 drivers/mmc/host/mmci.c writel(readl(base + MMCIMASK0) & base 1282 drivers/mmc/host/mmci.c base + MMCIMASK0); base 1294 drivers/mmc/host/mmci.c cmd->resp[0] = readl(base + MMCIRESPONSE0); base 1295 drivers/mmc/host/mmci.c cmd->resp[1] = readl(base + MMCIRESPONSE1); base 1296 drivers/mmc/host/mmci.c cmd->resp[2] = readl(base + MMCIRESPONSE2); base 1297 drivers/mmc/host/mmci.c cmd->resp[3] = readl(base + MMCIRESPONSE3); base 1322 drivers/mmc/host/mmci.c return remain - (readl(host->base + MMCIFIFOCNT) << 2); base 1341 drivers/mmc/host/mmci.c void __iomem *base = host->base; base 1343 drivers/mmc/host/mmci.c u32 status = readl(host->base + MMCISTATUS); base 1364 drivers/mmc/host/mmci.c ioread32_rep(base + MMCIFIFO, buf, 1); base 1367 drivers/mmc/host/mmci.c ioread32_rep(base + MMCIFIFO, ptr, count >> 2); base 1371 drivers/mmc/host/mmci.c ioread32_rep(base + MMCIFIFO, ptr, count >> 2); base 1381 drivers/mmc/host/mmci.c status = readl(base + MMCISTATUS); base 1390 drivers/mmc/host/mmci.c void __iomem *base = host->base; base 1408 drivers/mmc/host/mmci.c iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); base 1416 drivers/mmc/host/mmci.c status = readl(base + MMCISTATUS); base 1430 drivers/mmc/host/mmci.c void __iomem *base = host->base; base 1433 drivers/mmc/host/mmci.c status = readl(base + MMCISTATUS); base 1471 drivers/mmc/host/mmci.c status = readl(base + MMCISTATUS); base 1491 drivers/mmc/host/mmci.c writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); base 1509 drivers/mmc/host/mmci.c status = readl(host->base + MMCISTATUS); base 1522 drivers/mmc/host/mmci.c status &= readl(host->base + MMCIMASK0); base 1525 drivers/mmc/host/mmci.c host->base + MMCICLEAR); base 1527 drivers/mmc/host/mmci.c writel(status, host->base + MMCICLEAR); base 1888 drivers/mmc/host/mmci.c host->base = devm_ioremap_resource(&dev->dev, &dev->res); base 1889 drivers/mmc/host/mmci.c if (IS_ERR(host->base)) { base 1890 drivers/mmc/host/mmci.c ret = PTR_ERR(host->base); base 2004 drivers/mmc/host/mmci.c writel(0, host->base + MMCIMASK0); base 2007 drivers/mmc/host/mmci.c writel(0, host->base + MMCIMASK1); base 2009 drivers/mmc/host/mmci.c writel(0xfff, host->base + MMCICLEAR); base 2042 drivers/mmc/host/mmci.c writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); base 2084 drivers/mmc/host/mmci.c writel(0, host->base + MMCIMASK0); base 2087 drivers/mmc/host/mmci.c writel(0, host->base + MMCIMASK1); base 2089 drivers/mmc/host/mmci.c writel(0, host->base + MMCICOMMAND); base 2090 drivers/mmc/host/mmci.c writel(0, host->base + MMCIDATACTRL); base 2107 drivers/mmc/host/mmci.c writel(0, host->base + MMCIMASK0); base 2109 drivers/mmc/host/mmci.c writel(0, host->base + MMCIDATACTRL); base 2110 drivers/mmc/host/mmci.c writel(0, host->base + MMCIPOWER); base 2111 drivers/mmc/host/mmci.c writel(0, host->base + MMCICLOCK); base 2125 drivers/mmc/host/mmci.c writel(host->clk_reg, host->base + MMCICLOCK); base 2126 drivers/mmc/host/mmci.c writel(host->datactrl_reg, host->base + MMCIDATACTRL); base 2127 drivers/mmc/host/mmci.c writel(host->pwr_reg, host->base + MMCIPOWER); base 2130 drivers/mmc/host/mmci.c host->base + MMCIMASK0); base 373 drivers/mmc/host/mmci.h void __iomem *base; base 51 drivers/mmc/host/mmci_qcom_dml.c void __iomem *base = host->base + DML_OFFSET; base 61 drivers/mmc/host/mmci_qcom_dml.c config = readl_relaxed(base + DML_CONFIG); base 64 drivers/mmc/host/mmci_qcom_dml.c writel_relaxed(config, base + DML_CONFIG); base 67 drivers/mmc/host/mmci_qcom_dml.c writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); base 71 drivers/mmc/host/mmci_qcom_dml.c base + DML_PRODUCER_BAM_TRANS_SIZE); base 73 drivers/mmc/host/mmci_qcom_dml.c config = readl_relaxed(base + DML_CONFIG); base 75 drivers/mmc/host/mmci_qcom_dml.c writel_relaxed(config, base + DML_CONFIG); base 77 drivers/mmc/host/mmci_qcom_dml.c writel_relaxed(1, base + DML_PRODUCER_START); base 81 drivers/mmc/host/mmci_qcom_dml.c config = readl_relaxed(base + DML_CONFIG); base 84 drivers/mmc/host/mmci_qcom_dml.c writel_relaxed(config, base + DML_CONFIG); base 86 drivers/mmc/host/mmci_qcom_dml.c config = readl_relaxed(base + DML_CONFIG); base 88 drivers/mmc/host/mmci_qcom_dml.c writel_relaxed(config, base + DML_CONFIG); base 90 drivers/mmc/host/mmci_qcom_dml.c writel_relaxed(1, base + DML_CONSUMER_START); base 122 drivers/mmc/host/mmci_qcom_dml.c void __iomem *base; base 137 drivers/mmc/host/mmci_qcom_dml.c base = host->base + DML_OFFSET; base 140 drivers/mmc/host/mmci_qcom_dml.c writel_relaxed(1, base + DML_SW_RESET); base 161 drivers/mmc/host/mmci_qcom_dml.c writel_relaxed(config, base + DML_CONFIG); base 168 drivers/mmc/host/mmci_qcom_dml.c base + DML_PRODUCER_PIPE_LOGICAL_SIZE); base 170 drivers/mmc/host/mmci_qcom_dml.c base + DML_CONSUMER_PIPE_LOGICAL_SIZE); base 174 drivers/mmc/host/mmci_qcom_dml.c base + DML_PIPE_ID); base 134 drivers/mmc/host/mmci_stm32_sdmmc.c host->base + MMCI_STM32_IDMABASE0R); base 136 drivers/mmc/host/mmci_stm32_sdmmc.c host->base + MMCI_STM32_IDMACTRLR); base 152 drivers/mmc/host/mmci_stm32_sdmmc.c writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR); base 153 drivers/mmc/host/mmci_stm32_sdmmc.c writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR); base 154 drivers/mmc/host/mmci_stm32_sdmmc.c writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R); base 155 drivers/mmc/host/mmci_stm32_sdmmc.c writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER); base 157 drivers/mmc/host/mmci_stm32_sdmmc.c host->base + MMCI_STM32_IDMACTRLR); base 164 drivers/mmc/host/mmci_stm32_sdmmc.c writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR); base 258 drivers/mmc/host/mmci_stm32_sdmmc.c host->base + MMCIMASK0); base 125 drivers/mmc/host/moxart-mmc.c void __iomem *base; base 187 drivers/mmc/host/moxart-mmc.c *status = readl(host->base + REG_STATUS); base 192 drivers/mmc/host/moxart-mmc.c writel(*status & mask, host->base + REG_CLEAR); base 210 drivers/mmc/host/moxart-mmc.c RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR); base 211 drivers/mmc/host/moxart-mmc.c writel(cmd->arg, host->base + REG_ARGUMENT); base 225 drivers/mmc/host/moxart-mmc.c writel(cmdctrl | CMD_EN, host->base + REG_COMMAND); base 240 drivers/mmc/host/moxart-mmc.c cmd->resp[3] = readl(host->base + REG_RESPONSE0); base 241 drivers/mmc/host/moxart-mmc.c cmd->resp[2] = readl(host->base + REG_RESPONSE1); base 242 drivers/mmc/host/moxart-mmc.c cmd->resp[1] = readl(host->base + REG_RESPONSE2); base 243 drivers/mmc/host/moxart-mmc.c cmd->resp[0] = readl(host->base + REG_RESPONSE3); base 245 drivers/mmc/host/moxart-mmc.c cmd->resp[0] = readl(host->base + REG_RESPONSE0); base 326 drivers/mmc/host/moxart-mmc.c iowrite32(*sgp, host->base + REG_DATA_WINDOW); base 344 drivers/mmc/host/moxart-mmc.c *sgp = ioread32be(host->base + base 347 drivers/mmc/host/moxart-mmc.c *sgp = ioread32(host->base + base 388 drivers/mmc/host/moxart-mmc.c writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL); base 389 drivers/mmc/host/moxart-mmc.c writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR); base 390 drivers/mmc/host/moxart-mmc.c writel(host->rate, host->base + REG_DATA_TIMER); base 391 drivers/mmc/host/moxart-mmc.c writel(host->data_len, host->base + REG_DATA_LENGTH); base 392 drivers/mmc/host/moxart-mmc.c writel(datactrl, host->base + REG_DATA_CONTROL); base 409 drivers/mmc/host/moxart-mmc.c if (readl(host->base + REG_STATUS) & CARD_DETECT) { base 420 drivers/mmc/host/moxart-mmc.c writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); base 429 drivers/mmc/host/moxart-mmc.c writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK); base 472 drivers/mmc/host/moxart-mmc.c status = readl(host->base + REG_STATUS); base 480 drivers/mmc/host/moxart-mmc.c writel(MASK_INTR_PIO, host->base + REG_CLEAR); base 481 drivers/mmc/host/moxart-mmc.c writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); base 510 drivers/mmc/host/moxart-mmc.c writel(ctrl, host->base + REG_CLOCK_CONTROL); base 514 drivers/mmc/host/moxart-mmc.c writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON, base 515 drivers/mmc/host/moxart-mmc.c host->base + REG_POWER_CONTROL); base 523 drivers/mmc/host/moxart-mmc.c host->base + REG_POWER_CONTROL); base 528 drivers/mmc/host/moxart-mmc.c writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH); base 531 drivers/mmc/host/moxart-mmc.c writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH); base 534 drivers/mmc/host/moxart-mmc.c writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH); base 546 drivers/mmc/host/moxart-mmc.c return !!(readl(host->base + REG_STATUS) & WRITE_PROT); base 606 drivers/mmc/host/moxart-mmc.c host->base = reg_mmc; base 610 drivers/mmc/host/moxart-mmc.c host->fifo_width = readl(host->base + REG_FEATURE) << 2; base 648 drivers/mmc/host/moxart-mmc.c switch ((readl(host->base + REG_BUS_WIDTH) >> 3) & 3) { base 659 drivers/mmc/host/moxart-mmc.c writel(0, host->base + REG_INTERRUPT_MASK); base 661 drivers/mmc/host/moxart-mmc.c writel(CMD_SDC_RESET, host->base + REG_COMMAND); base 663 drivers/mmc/host/moxart-mmc.c if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET)) base 700 drivers/mmc/host/moxart-mmc.c writel(0, host->base + REG_INTERRUPT_MASK); base 701 drivers/mmc/host/moxart-mmc.c writel(0, host->base + REG_POWER_CONTROL); base 702 drivers/mmc/host/moxart-mmc.c writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF, base 703 drivers/mmc/host/moxart-mmc.c host->base + REG_CLOCK_CONTROL); base 401 drivers/mmc/host/mtk-sd.c void __iomem *base; /* host base address */ base 580 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); base 581 drivers/mmc/host/mtk-sd.c while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) base 584 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); base 585 drivers/mmc/host/mtk-sd.c while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) base 588 drivers/mmc/host/mtk-sd.c val = readl(host->base + MSDC_INT); base 589 drivers/mmc/host/mtk-sd.c writel(val, host->base + MSDC_INT); base 666 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); base 667 drivers/mmc/host/mtk-sd.c dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); base 670 drivers/mmc/host/mtk-sd.c writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); base 672 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, base 674 drivers/mmc/host/mtk-sd.c writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); base 718 drivers/mmc/host/mtk-sd.c sdr_get_field(host->base + MSDC_CFG, base 721 drivers/mmc/host/mtk-sd.c sdr_get_field(host->base + MSDC_CFG, base 728 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); base 745 drivers/mmc/host/mtk-sd.c while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) base 761 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); base 765 drivers/mmc/host/mtk-sd.c flags = readl(host->base + MSDC_INTEN); base 766 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_INTEN, flags); base 768 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); base 770 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_CFG, base 792 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_CFG, base 795 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_CFG, base 814 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); base 824 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_CFG, base 828 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_CFG, base 836 drivers/mmc/host/mtk-sd.c while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) base 838 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); base 844 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_INTEN, flags); base 851 drivers/mmc/host/mtk-sd.c writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); base 859 drivers/mmc/host/mtk-sd.c host->base + tune_reg); base 862 drivers/mmc/host/mtk-sd.c writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); base 864 drivers/mmc/host/mtk-sd.c host->base + PAD_CMD_TUNE); base 872 drivers/mmc/host/mtk-sd.c host->base + tune_reg); base 878 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + tune_reg, base 955 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); base 962 drivers/mmc/host/mtk-sd.c writel(data->blocks, host->base + SDC_BLK_NUM); base 978 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); base 979 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); base 990 drivers/mmc/host/mtk-sd.c rsp[0] = readl(host->base + SDC_ACMD_RESP); base 1069 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); base 1073 drivers/mmc/host/mtk-sd.c rsp[0] = readl(host->base + SDC_RESP3); base 1074 drivers/mmc/host/mtk-sd.c rsp[1] = readl(host->base + SDC_RESP2); base 1075 drivers/mmc/host/mtk-sd.c rsp[2] = readl(host->base + SDC_RESP1); base 1076 drivers/mmc/host/mtk-sd.c rsp[3] = readl(host->base + SDC_RESP0); base 1078 drivers/mmc/host/mtk-sd.c rsp[0] = readl(host->base + SDC_RESP0); base 1120 drivers/mmc/host/mtk-sd.c while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && base 1123 drivers/mmc/host/mtk-sd.c if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { base 1133 drivers/mmc/host/mtk-sd.c while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && base 1136 drivers/mmc/host/mtk-sd.c if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { base 1159 drivers/mmc/host/mtk-sd.c if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || base 1160 drivers/mmc/host/mtk-sd.c readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { base 1169 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); base 1172 drivers/mmc/host/mtk-sd.c writel(cmd->arg, host->base + SDC_ARG); base 1173 drivers/mmc/host/mtk-sd.c writel(rawcmd, host->base + SDC_CMD); base 1274 drivers/mmc/host/mtk-sd.c readl(host->base + MSDC_DMA_CFG)); base 1275 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, base 1277 drivers/mmc/host/mtk-sd.c while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) base 1279 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); base 1309 drivers/mmc/host/mtk-sd.c u32 val = readl(host->base + SDC_CFG); base 1326 drivers/mmc/host/mtk-sd.c writel(val, host->base + SDC_CFG); base 1360 drivers/mmc/host/mtk-sd.c u32 status = readl(host->base + MSDC_PS); base 1394 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); base 1395 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); base 1397 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); base 1398 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); base 1429 drivers/mmc/host/mtk-sd.c events = readl(host->base + MSDC_INT); base 1430 drivers/mmc/host/mtk-sd.c event_mask = readl(host->base + MSDC_INTEN); base 1434 drivers/mmc/host/mtk-sd.c writel(events & event_mask, host->base + MSDC_INT); base 1478 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); base 1484 drivers/mmc/host/mtk-sd.c writel(0, host->base + MSDC_INTEN); base 1485 drivers/mmc/host/mtk-sd.c val = readl(host->base + MSDC_INT); base 1486 drivers/mmc/host/mtk-sd.c writel(val, host->base + MSDC_INT); base 1490 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, base 1492 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); base 1493 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); base 1494 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); base 1496 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); base 1497 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); base 1498 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); base 1505 drivers/mmc/host/mtk-sd.c writel(0, host->base + tune_reg); base 1507 drivers/mmc/host/mtk-sd.c writel(0, host->base + MSDC_IOCON); base 1508 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); base 1509 drivers/mmc/host/mtk-sd.c writel(0x403c0046, host->base + MSDC_PATCH_BIT); base 1510 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); base 1511 drivers/mmc/host/mtk-sd.c writel(0xffff4089, host->base + MSDC_PATCH_BIT1); base 1512 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); base 1515 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_PATCH_BIT1, base 1517 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + SDC_FIFO_CFG, base 1519 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + SDC_FIFO_CFG, base 1524 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); base 1527 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_PATCH_BIT2, base 1534 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + SDC_ADV_CFG0, base 1537 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_PATCH_BIT2, base 1539 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_PATCH_BIT2, base 1543 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_PATCH_BIT2, base 1545 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_PATCH_BIT2, base 1550 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_PATCH_BIT2, base 1561 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + tune_reg, base 1571 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + tune_reg, base 1578 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); base 1581 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); base 1582 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); base 1585 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); base 1587 drivers/mmc/host/mtk-sd.c host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); base 1588 drivers/mmc/host/mtk-sd.c host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); base 1599 drivers/mmc/host/mtk-sd.c host->def_tune_para.pad_tune = readl(host->base + tune_reg); base 1600 drivers/mmc/host/mtk-sd.c host->saved_tune_para.pad_tune = readl(host->base + tune_reg); base 1611 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); base 1612 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); base 1616 drivers/mmc/host/mtk-sd.c writel(0, host->base + MSDC_INTEN); base 1618 drivers/mmc/host/mtk-sd.c val = readl(host->base + MSDC_INT); base 1619 drivers/mmc/host/mtk-sd.c writel(val, host->base + MSDC_INT); base 1764 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, base 1776 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, base 1794 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + tune_reg, base 1798 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); base 1822 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); base 1847 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); base 1850 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); base 1859 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + tune_reg, base 1867 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, base 1884 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); base 1885 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); base 1889 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_PAD_TUNE, base 1894 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); base 1896 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); base 1898 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + PAD_CMD_TUNE, base 1916 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, base 1932 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, base 1934 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); base 1935 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); base 1948 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); base 1949 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); base 1961 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); base 1962 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); base 1965 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); base 1966 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); base 1987 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, base 1990 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); base 1991 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, base 2006 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); base 2007 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_IOCON, base 2021 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); base 2022 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, base 2026 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); base 2027 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + MSDC_IOCON, base 2048 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_IOCON, base 2070 drivers/mmc/host/mtk-sd.c host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); base 2071 drivers/mmc/host/mtk-sd.c host->saved_tune_para.pad_tune = readl(host->base + tune_reg); base 2072 drivers/mmc/host/mtk-sd.c host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); base 2091 drivers/mmc/host/mtk-sd.c writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); base 2093 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); base 2095 drivers/mmc/host/mtk-sd.c sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); base 2104 drivers/mmc/host/mtk-sd.c sdr_set_bits(host->base + EMMC_IOCON, 1); base 2106 drivers/mmc/host/mtk-sd.c sdr_clr_bits(host->base + EMMC_IOCON, 1); base 2130 drivers/mmc/host/mtk-sd.c val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; base 2198 drivers/mmc/host/mtk-sd.c host->base = devm_ioremap_resource(&pdev->dev, res); base 2199 drivers/mmc/host/mtk-sd.c if (IS_ERR(host->base)) { base 2200 drivers/mmc/host/mtk-sd.c ret = PTR_ERR(host->base); base 2392 drivers/mmc/host/mtk-sd.c host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); base 2393 drivers/mmc/host/mtk-sd.c host->save_para.iocon = readl(host->base + MSDC_IOCON); base 2394 drivers/mmc/host/mtk-sd.c host->save_para.sdc_cfg = readl(host->base + SDC_CFG); base 2395 drivers/mmc/host/mtk-sd.c host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); base 2396 drivers/mmc/host/mtk-sd.c host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); base 2397 drivers/mmc/host/mtk-sd.c host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); base 2398 drivers/mmc/host/mtk-sd.c host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); base 2399 drivers/mmc/host/mtk-sd.c host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); base 2400 drivers/mmc/host/mtk-sd.c host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); base 2401 drivers/mmc/host/mtk-sd.c host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); base 2402 drivers/mmc/host/mtk-sd.c host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); base 2411 drivers/mmc/host/mtk-sd.c host->save_para.pad_tune = readl(host->base + tune_reg); base 2419 drivers/mmc/host/mtk-sd.c writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); base 2420 drivers/mmc/host/mtk-sd.c writel(host->save_para.iocon, host->base + MSDC_IOCON); base 2421 drivers/mmc/host/mtk-sd.c writel(host->save_para.sdc_cfg, host->base + SDC_CFG); base 2422 drivers/mmc/host/mtk-sd.c writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); base 2423 drivers/mmc/host/mtk-sd.c writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); base 2424 drivers/mmc/host/mtk-sd.c writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); base 2425 drivers/mmc/host/mtk-sd.c writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); base 2426 drivers/mmc/host/mtk-sd.c writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); base 2427 drivers/mmc/host/mtk-sd.c writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); base 2428 drivers/mmc/host/mtk-sd.c writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); base 2429 drivers/mmc/host/mtk-sd.c writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); base 2438 drivers/mmc/host/mtk-sd.c writel(host->save_para.pad_tune, host->base + tune_reg); base 35 drivers/mmc/host/mvsdio.c void __iomem *base; base 58 drivers/mmc/host/mvsdio.c void __iomem *iobase = host->base; base 139 drivers/mmc/host/mvsdio.c void __iomem *iobase = host->base; base 244 drivers/mmc/host/mvsdio.c void __iomem *iobase = host->base; base 289 drivers/mmc/host/mvsdio.c void __iomem *iobase = host->base; base 347 drivers/mmc/host/mvsdio.c void __iomem *iobase = host->base; base 513 drivers/mmc/host/mvsdio.c void __iomem *iobase = host->base; base 554 drivers/mmc/host/mvsdio.c void __iomem *iobase = host->base; base 572 drivers/mmc/host/mvsdio.c void __iomem *iobase = host->base; base 586 drivers/mmc/host/mvsdio.c void __iomem *iobase = host->base; base 601 drivers/mmc/host/mvsdio.c void __iomem *iobase = host->base; base 675 drivers/mmc/host/mvsdio.c void __iomem *iobase = host->base; base 689 drivers/mmc/host/mvsdio.c writel(cs->base, iobase + MVSD_WINDOW_BASE(i)); base 761 drivers/mmc/host/mvsdio.c host->base = devm_ioremap_resource(&pdev->dev, r); base 762 drivers/mmc/host/mvsdio.c if (IS_ERR(host->base)) { base 763 drivers/mmc/host/mvsdio.c ret = PTR_ERR(host->base); base 122 drivers/mmc/host/mxcmmc.c void __iomem *base; base 205 drivers/mmc/host/mxcmmc.c return ioread32be(host->base + reg); base 207 drivers/mmc/host/mxcmmc.c return readl(host->base + reg); base 213 drivers/mmc/host/mxcmmc.c iowrite32be(val, host->base + reg); base 215 drivers/mmc/host/mxcmmc.c writel(val, host->base + reg); base 221 drivers/mmc/host/mxcmmc.c return ioread32be(host->base + reg); base 223 drivers/mmc/host/mxcmmc.c return readw(host->base + reg); base 229 drivers/mmc/host/mxcmmc.c iowrite32be(val, host->base + reg); base 231 drivers/mmc/host/mxcmmc.c writew(val, host->base + reg); base 1022 drivers/mmc/host/mxcmmc.c host->base = devm_ioremap_resource(&pdev->dev, res); base 1023 drivers/mmc/host/mxcmmc.c if (IS_ERR(host->base)) { base 1024 drivers/mmc/host/mxcmmc.c ret = PTR_ERR(host->base); base 76 drivers/mmc/host/mxs-mmc.c !(readl(ssp->base + HW_SSP_STATUS(ssp)) & base 91 drivers/mmc/host/mxs-mmc.c ret = stmp_reset_block(ssp->base); base 109 drivers/mmc/host/mxs-mmc.c ssp->base + HW_SSP_TIMING(ssp)); base 116 drivers/mmc/host/mxs-mmc.c writel(ctrl0, ssp->base + HW_SSP_CTRL0); base 117 drivers/mmc/host/mxs-mmc.c writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp)); base 133 drivers/mmc/host/mxs-mmc.c cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); base 134 drivers/mmc/host/mxs-mmc.c cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp)); base 135 drivers/mmc/host/mxs-mmc.c cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp)); base 136 drivers/mmc/host/mxs-mmc.c cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp)); base 138 drivers/mmc/host/mxs-mmc.c cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); base 186 drivers/mmc/host/mxs-mmc.c stat = readl(ssp->base + HW_SSP_CTRL1(ssp)); base 188 drivers/mmc/host/mxs-mmc.c ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); base 407 drivers/mmc/host/mxs-mmc.c writel(data_size, ssp->base + HW_SSP_XFER_SIZE); base 410 drivers/mmc/host/mxs-mmc.c ssp->base + HW_SSP_BLOCK_SIZE); base 425 drivers/mmc/host/mxs-mmc.c val = readl(ssp->base + HW_SSP_TIMING(ssp)); base 428 drivers/mmc/host/mxs-mmc.c writel(val, ssp->base + HW_SSP_TIMING(ssp)); base 522 drivers/mmc/host/mxs-mmc.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); base 524 drivers/mmc/host/mxs-mmc.c ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET); base 527 drivers/mmc/host/mxs-mmc.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); base 529 drivers/mmc/host/mxs-mmc.c ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); base 534 drivers/mmc/host/mxs-mmc.c if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) & base 590 drivers/mmc/host/mxs-mmc.c ssp->base = devm_platform_ioremap_resource(pdev, 0); base 591 drivers/mmc/host/mxs-mmc.c if (IS_ERR(ssp->base)) { base 592 drivers/mmc/host/mxs-mmc.c ret = PTR_ERR(ssp->base); base 158 drivers/mmc/host/omap_hsmmc.c #define OMAP_HSMMC_READ(base, reg) \ base 159 drivers/mmc/host/omap_hsmmc.c __raw_readl((base) + OMAP_HSMMC_##reg) base 161 drivers/mmc/host/omap_hsmmc.c #define OMAP_HSMMC_WRITE(base, reg, val) \ base 162 drivers/mmc/host/omap_hsmmc.c __raw_writel((val), (base) + OMAP_HSMMC_##reg) base 179 drivers/mmc/host/omap_hsmmc.c void __iomem *base; base 465 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, SYSCTL, base 466 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); base 474 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, SYSCTL, base 475 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); base 476 drivers/mmc/host/omap_hsmmc.c if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) base 494 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); base 495 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); base 500 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, IE, irq_mask); base 513 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); base 514 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, IE, irq_mask); base 515 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); base 544 drivers/mmc/host/omap_hsmmc.c regval = OMAP_HSMMC_READ(host->base, SYSCTL); base 548 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); base 549 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, SYSCTL, base 550 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); base 554 drivers/mmc/host/omap_hsmmc.c while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS base 570 drivers/mmc/host/omap_hsmmc.c ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { base 571 drivers/mmc/host/omap_hsmmc.c regval = OMAP_HSMMC_READ(host->base, HCTL); base 577 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, regval); base 588 drivers/mmc/host/omap_hsmmc.c con = OMAP_HSMMC_READ(host->base, CON); base 596 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CON, con | DW8); base 599 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); base 600 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, base 601 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); base 604 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); base 605 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, base 606 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); base 616 drivers/mmc/host/omap_hsmmc.c con = OMAP_HSMMC_READ(host->base, CON); base 618 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CON, con | OD); base 620 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); base 635 drivers/mmc/host/omap_hsmmc.c if (host->con == OMAP_HSMMC_READ(host->base, CON) && base 636 drivers/mmc/host/omap_hsmmc.c host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && base 637 drivers/mmc/host/omap_hsmmc.c host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && base 638 drivers/mmc/host/omap_hsmmc.c host->capa == OMAP_HSMMC_READ(host->base, CAPA)) base 658 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, base 659 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, HCTL) | hctl); base 661 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CAPA, base 662 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, CAPA) | capa); base 664 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, base 665 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, HCTL) | SDBP); base 668 drivers/mmc/host/omap_hsmmc.c while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP base 672 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, ISE, 0); base 673 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, IE, 0); base 674 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); base 697 drivers/mmc/host/omap_hsmmc.c host->con = OMAP_HSMMC_READ(host->base, CON); base 698 drivers/mmc/host/omap_hsmmc.c host->hctl = OMAP_HSMMC_READ(host->base, HCTL); base 699 drivers/mmc/host/omap_hsmmc.c host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); base 700 drivers/mmc/host/omap_hsmmc.c host->capa = OMAP_HSMMC_READ(host->base, CAPA); base 727 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); base 728 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CON, base 729 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); base 730 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); base 734 drivers/mmc/host/omap_hsmmc.c reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; base 736 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CON, base 737 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); base 739 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); base 740 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, STAT); base 796 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); base 811 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); base 812 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); base 892 drivers/mmc/host/omap_hsmmc.c cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); base 893 drivers/mmc/host/omap_hsmmc.c cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); base 894 drivers/mmc/host/omap_hsmmc.c cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); base 895 drivers/mmc/host/omap_hsmmc.c cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); base 898 drivers/mmc/host/omap_hsmmc.c cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); base 981 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, SYSCTL, base 982 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, SYSCTL) | bit); base 989 drivers/mmc/host/omap_hsmmc.c while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) base 995 drivers/mmc/host/omap_hsmmc.c while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && base 999 drivers/mmc/host/omap_hsmmc.c if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) base 1047 drivers/mmc/host/omap_hsmmc.c ac12 = OMAP_HSMMC_READ(host->base, AC12); base 1061 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, STAT, status); base 1076 drivers/mmc/host/omap_hsmmc.c status = OMAP_HSMMC_READ(host->base, STAT); base 1085 drivers/mmc/host/omap_hsmmc.c status = OMAP_HSMMC_READ(host->base, STAT); base 1095 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, base 1096 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, HCTL) | SDBP); base 1098 drivers/mmc/host/omap_hsmmc.c if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) base 1132 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, base 1133 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); base 1134 drivers/mmc/host/omap_hsmmc.c reg_val = OMAP_HSMMC_READ(host->base, HCTL); base 1156 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); base 1309 drivers/mmc/host/omap_hsmmc.c reg = OMAP_HSMMC_READ(host->base, SYSCTL); base 1336 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); base 1346 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) base 1366 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, BLK, 0); base 1487 drivers/mmc/host/omap_hsmmc.c if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && base 1555 drivers/mmc/host/omap_hsmmc.c con = OMAP_HSMMC_READ(host->base, CON); base 1556 drivers/mmc/host/omap_hsmmc.c irq_mask = OMAP_HSMMC_READ(host->base, ISE); base 1566 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CON, con); base 1567 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, IE, irq_mask); base 1574 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); base 1577 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, IE); base 1627 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, base 1628 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, HCTL) | IWE); base 1652 drivers/mmc/host/omap_hsmmc.c value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; base 1653 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); base 1655 drivers/mmc/host/omap_hsmmc.c value = OMAP_HSMMC_READ(host->base, CAPA); base 1656 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); base 1704 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, CON)); base 1706 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, PSTATE)); base 1708 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, HCTL)); base 1710 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, SYSCTL)); base 1712 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, IE)); base 1714 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, ISE)); base 1716 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, CAPA)); base 1824 drivers/mmc/host/omap_hsmmc.c void __iomem *base; base 1850 drivers/mmc/host/omap_hsmmc.c base = devm_ioremap_resource(&pdev->dev, res); base 1851 drivers/mmc/host/omap_hsmmc.c if (IS_ERR(base)) base 1852 drivers/mmc/host/omap_hsmmc.c return PTR_ERR(base); base 1872 drivers/mmc/host/omap_hsmmc.c host->base = base + pdata->reg_offset; base 2068 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, ISE, 0); base 2069 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, IE, 0); base 2070 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); base 2071 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, base 2072 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); base 2118 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, ISE, 0); base 2119 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, IE, 0); base 2121 drivers/mmc/host/omap_hsmmc.c if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { base 2128 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); base 2129 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); base 2130 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); base 2162 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); base 2163 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); base 2164 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); base 54 drivers/mmc/host/pxamci.c void __iomem *base; base 119 drivers/mmc/host/pxamci.c if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { base 123 drivers/mmc/host/pxamci.c writel(STOP_CLOCK, host->base + MMC_STRPCL); base 126 drivers/mmc/host/pxamci.c v = readl(host->base + MMC_STAT); base 143 drivers/mmc/host/pxamci.c writel(host->imask, host->base + MMC_I_MASK); base 153 drivers/mmc/host/pxamci.c writel(host->imask, host->base + MMC_I_MASK); base 172 drivers/mmc/host/pxamci.c writel(nob, host->base + MMC_NOB); base 173 drivers/mmc/host/pxamci.c writel(data->blksz, host->base + MMC_BLKLEN); base 178 drivers/mmc/host/pxamci.c writel((timeout + 255) / 256, host->base + MMC_RDTO); base 256 drivers/mmc/host/pxamci.c writel(cmd->opcode, host->base + MMC_CMD); base 257 drivers/mmc/host/pxamci.c writel(cmd->arg >> 16, host->base + MMC_ARGH); base 258 drivers/mmc/host/pxamci.c writel(cmd->arg & 0xffff, host->base + MMC_ARGL); base 259 drivers/mmc/host/pxamci.c writel(cmdat, host->base + MMC_CMDAT); base 260 drivers/mmc/host/pxamci.c writel(host->clkrt, host->base + MMC_CLKRT); base 262 drivers/mmc/host/pxamci.c writel(START_CLOCK, host->base + MMC_STRPCL); base 290 drivers/mmc/host/pxamci.c v = readl(host->base + MMC_RES) & 0xffff; base 292 drivers/mmc/host/pxamci.c u32 w1 = readl(host->base + MMC_RES) & 0xffff; base 293 drivers/mmc/host/pxamci.c u32 w2 = readl(host->base + MMC_RES) & 0xffff; base 380 drivers/mmc/host/pxamci.c ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK); base 383 drivers/mmc/host/pxamci.c unsigned stat = readl(host->base + MMC_STAT); base 550 drivers/mmc/host/pxamci.c writel(BUF_PART_FULL, host->base + MMC_PRTBUF); base 691 drivers/mmc/host/pxamci.c host->base = devm_ioremap_resource(dev, r); base 692 drivers/mmc/host/pxamci.c if (IS_ERR(host->base)) { base 693 drivers/mmc/host/pxamci.c ret = PTR_ERR(host->base); base 702 drivers/mmc/host/pxamci.c writel(0, host->base + MMC_SPI); base 703 drivers/mmc/host/pxamci.c writel(64, host->base + MMC_RESTO); base 704 drivers/mmc/host/pxamci.c writel(host->imask, host->base + MMC_I_MASK); base 794 drivers/mmc/host/pxamci.c host->base + MMC_I_MASK); base 156 drivers/mmc/host/s3cmci.c con = readl(host->base + S3C2410_SDICON); base 157 drivers/mmc/host/s3cmci.c pre = readl(host->base + S3C2410_SDIPRE); base 158 drivers/mmc/host/s3cmci.c cmdarg = readl(host->base + S3C2410_SDICMDARG); base 159 drivers/mmc/host/s3cmci.c cmdcon = readl(host->base + S3C2410_SDICMDCON); base 160 drivers/mmc/host/s3cmci.c cmdsta = readl(host->base + S3C2410_SDICMDSTAT); base 161 drivers/mmc/host/s3cmci.c r0 = readl(host->base + S3C2410_SDIRSP0); base 162 drivers/mmc/host/s3cmci.c r1 = readl(host->base + S3C2410_SDIRSP1); base 163 drivers/mmc/host/s3cmci.c r2 = readl(host->base + S3C2410_SDIRSP2); base 164 drivers/mmc/host/s3cmci.c r3 = readl(host->base + S3C2410_SDIRSP3); base 165 drivers/mmc/host/s3cmci.c timer = readl(host->base + S3C2410_SDITIMER); base 166 drivers/mmc/host/s3cmci.c bsize = readl(host->base + S3C2410_SDIBSIZE); base 167 drivers/mmc/host/s3cmci.c datcon = readl(host->base + S3C2410_SDIDCON); base 168 drivers/mmc/host/s3cmci.c datcnt = readl(host->base + S3C2410_SDIDCNT); base 169 drivers/mmc/host/s3cmci.c datsta = readl(host->base + S3C2410_SDIDSTA); base 170 drivers/mmc/host/s3cmci.c fsta = readl(host->base + S3C2410_SDIFSTA); base 171 drivers/mmc/host/s3cmci.c imask = readl(host->base + host->sdiimsk); base 231 drivers/mmc/host/s3cmci.c readl(host->base + S3C2410_SDIDCNT)); base 266 drivers/mmc/host/s3cmci.c newmask = readl(host->base + host->sdiimsk); base 269 drivers/mmc/host/s3cmci.c writel(newmask, host->base + host->sdiimsk); base 278 drivers/mmc/host/s3cmci.c newmask = readl(host->base + host->sdiimsk); base 281 drivers/mmc/host/s3cmci.c writel(newmask, host->base + host->sdiimsk); base 288 drivers/mmc/host/s3cmci.c u32 mask = readl(host->base + host->sdiimsk); base 292 drivers/mmc/host/s3cmci.c writel(mask, host->base + host->sdiimsk); base 348 drivers/mmc/host/s3cmci.c u32 fifostat = readl(host->base + S3C2410_SDIFSTA); base 356 drivers/mmc/host/s3cmci.c u32 fifostat = readl(host->base + S3C2410_SDIFSTA); base 429 drivers/mmc/host/s3cmci.c writel(host->prescaler, host->base + S3C2410_SDIPRE); base 431 drivers/mmc/host/s3cmci.c from_ptr = host->base + host->sdidata; base 454 drivers/mmc/host/s3cmci.c readl(host->base + S3C2410_SDIDCNT)); base 510 drivers/mmc/host/s3cmci.c to_ptr = host->base + host->sdidata; base 617 drivers/mmc/host/s3cmci.c mci_dsta = readl(host->base + S3C2410_SDIDSTA); base 618 drivers/mmc/host/s3cmci.c mci_imsk = readl(host->base + host->sdiimsk); base 623 drivers/mmc/host/s3cmci.c writel(mci_dclear, host->base + S3C2410_SDIDSTA); base 632 drivers/mmc/host/s3cmci.c mci_csta = readl(host->base + S3C2410_SDICMDSTAT); base 633 drivers/mmc/host/s3cmci.c mci_dcnt = readl(host->base + S3C2410_SDIDCNT); base 634 drivers/mmc/host/s3cmci.c mci_fsta = readl(host->base + S3C2410_SDIFSTA); base 784 drivers/mmc/host/s3cmci.c writel(mci_cclear, host->base + S3C2410_SDICMDSTAT); base 785 drivers/mmc/host/s3cmci.c writel(mci_dclear, host->base + S3C2410_SDIDSTA); base 853 drivers/mmc/host/s3cmci.c cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0); base 854 drivers/mmc/host/s3cmci.c cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1); base 855 drivers/mmc/host/s3cmci.c cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2); base 856 drivers/mmc/host/s3cmci.c cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3); base 858 drivers/mmc/host/s3cmci.c writel(host->prescaler, host->base + S3C2410_SDIPRE); base 869 drivers/mmc/host/s3cmci.c writel(0, host->base + S3C2410_SDICMDARG); base 870 drivers/mmc/host/s3cmci.c writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON); base 871 drivers/mmc/host/s3cmci.c writel(0, host->base + S3C2410_SDICMDCON); base 905 drivers/mmc/host/s3cmci.c host->base + S3C2410_SDIFSTA); base 910 drivers/mmc/host/s3cmci.c mci_con = readl(host->base + S3C2410_SDICON); base 913 drivers/mmc/host/s3cmci.c writel(mci_con, host->base + S3C2410_SDICON); base 943 drivers/mmc/host/s3cmci.c writel(cmd->arg, host->base + S3C2410_SDICMDARG); base 954 drivers/mmc/host/s3cmci.c writel(ccon, host->base + S3C2410_SDICMDCON); base 964 drivers/mmc/host/s3cmci.c writel(0, host->base + S3C2410_SDIDCON); base 979 drivers/mmc/host/s3cmci.c while (readl(host->base + S3C2410_SDIDSTA) & base 985 drivers/mmc/host/s3cmci.c writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON); base 1019 drivers/mmc/host/s3cmci.c writel(dcon, host->base + S3C2410_SDIDCON); base 1023 drivers/mmc/host/s3cmci.c writel(data->blksz, host->base + S3C2410_SDIBSIZE); base 1034 drivers/mmc/host/s3cmci.c writel(0x007FFFFF, host->base + S3C2410_SDITIMER); base 1036 drivers/mmc/host/s3cmci.c writel(0x0000FFFF, host->base + S3C2410_SDITIMER); base 1040 drivers/mmc/host/s3cmci.c writel(0xFF, host->base + S3C2410_SDIPRE); base 1084 drivers/mmc/host/s3cmci.c writel(host->prescaler, host->base + S3C2410_SDIPRE); base 1125 drivers/mmc/host/s3cmci.c writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT); base 1126 drivers/mmc/host/s3cmci.c writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA); base 1127 drivers/mmc/host/s3cmci.c writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA); base 1197 drivers/mmc/host/s3cmci.c writel(host->prescaler, host->base + S3C2410_SDIPRE); base 1211 drivers/mmc/host/s3cmci.c mci_con = readl(host->base + S3C2410_SDICON); base 1251 drivers/mmc/host/s3cmci.c writel(mci_con, host->base + S3C2410_SDICON); base 1266 drivers/mmc/host/s3cmci.c u32 con = readl(host->base + S3C2410_SDICON); base 1269 drivers/mmc/host/s3cmci.c writel(con, host->base + S3C2410_SDICON); base 1280 drivers/mmc/host/s3cmci.c con = readl(host->base + S3C2410_SDICON); base 1304 drivers/mmc/host/s3cmci.c writel(con, host->base + S3C2410_SDICON); base 1389 drivers/mmc/host/s3cmci.c seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base); base 1440 drivers/mmc/host/s3cmci.c readl(host->base + rptr->addr)); base 1442 drivers/mmc/host/s3cmci.c seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk)); base 1608 drivers/mmc/host/s3cmci.c host->base = ioremap(host->mem->start, resource_size(host->mem)); base 1609 drivers/mmc/host/s3cmci.c if (!host->base) { base 1684 drivers/mmc/host/s3cmci.c host->base, host->irq, host->irq_cd, host->dma); base 1724 drivers/mmc/host/s3cmci.c iounmap(host->base); base 1776 drivers/mmc/host/s3cmci.c iounmap(host->base); base 23 drivers/mmc/host/s3cmci.h void __iomem *base; base 299 drivers/mmc/host/sdhci-esdhc-imx.c void __iomem *base = host->ioaddr + (reg & ~0x3); base 302 drivers/mmc/host/sdhci-esdhc-imx.c writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); base 356 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; base 358 drivers/mmc/host/sdhci-of-esdhc.c value = ioread32be(host->ioaddr + base); base 367 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; base 369 drivers/mmc/host/sdhci-of-esdhc.c value = ioread32(host->ioaddr + base); base 378 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; base 380 drivers/mmc/host/sdhci-of-esdhc.c value = ioread32be(host->ioaddr + base); base 389 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; base 391 drivers/mmc/host/sdhci-of-esdhc.c value = ioread32(host->ioaddr + base); base 416 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; base 420 drivers/mmc/host/sdhci-of-esdhc.c value = ioread32be(host->ioaddr + base); base 423 drivers/mmc/host/sdhci-of-esdhc.c iowrite32be(ret, host->ioaddr + base); base 428 drivers/mmc/host/sdhci-of-esdhc.c if (base == ESDHC_SYSTEM_CONTROL_2) { base 433 drivers/mmc/host/sdhci-of-esdhc.c iowrite32be(ret, host->ioaddr + base); base 442 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; base 446 drivers/mmc/host/sdhci-of-esdhc.c value = ioread32(host->ioaddr + base); base 449 drivers/mmc/host/sdhci-of-esdhc.c iowrite32(ret, host->ioaddr + base); base 454 drivers/mmc/host/sdhci-of-esdhc.c if (base == ESDHC_SYSTEM_CONTROL_2) { base 459 drivers/mmc/host/sdhci-of-esdhc.c iowrite32(ret, host->ioaddr + base); base 466 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; base 470 drivers/mmc/host/sdhci-of-esdhc.c value = ioread32be(host->ioaddr + base); base 472 drivers/mmc/host/sdhci-of-esdhc.c iowrite32be(ret, host->ioaddr + base); base 477 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; base 481 drivers/mmc/host/sdhci-of-esdhc.c value = ioread32(host->ioaddr + base); base 483 drivers/mmc/host/sdhci-of-esdhc.c iowrite32(ret, host->ioaddr + base); base 96 drivers/mmc/host/sdhci-omap.c void __iomem *base; base 117 drivers/mmc/host/sdhci-omap.c return readl(host->base + offset); base 123 drivers/mmc/host/sdhci-omap.c writel(data, host->base + offset); base 1062 drivers/mmc/host/sdhci-omap.c omap_host->base = host->ioaddr; base 61 drivers/mmc/host/sdhci-pltfm.h int base = reg & ~0x3; base 78 drivers/mmc/host/sdhci-pltfm.h clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift); base 83 drivers/mmc/host/sdhci-pltfm.h int base = reg & ~0x3; base 86 drivers/mmc/host/sdhci-pltfm.h clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift); base 110 drivers/mmc/host/sdhci-pxav3.c writel(cs->base, regs + SDHCI_WINDOW_BASE(i)); base 79 drivers/mmc/host/sdhci_am654.c struct regmap *base; base 106 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); base 118 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); base 126 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, base 149 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, base 160 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL5, base 172 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); base 174 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, base 180 drivers/mmc/host/sdhci_am654.c ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, base 202 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); base 331 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); base 334 drivers/mmc/host/sdhci_am654.c regmap_read(sdhci_am654->base, PHY_STAT1, &val); base 337 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL1, base 339 drivers/mmc/host/sdhci_am654.c ret = regmap_read_poll_timeout(sdhci_am654->base, base 350 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL1, base 357 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, base 441 drivers/mmc/host/sdhci_am654.c void __iomem *base; base 472 drivers/mmc/host/sdhci_am654.c base = devm_ioremap_resource(dev, res); base 473 drivers/mmc/host/sdhci_am654.c if (IS_ERR(base)) { base 474 drivers/mmc/host/sdhci_am654.c ret = PTR_ERR(base); base 478 drivers/mmc/host/sdhci_am654.c sdhci_am654->base = devm_regmap_init_mmio(dev, base, base 480 drivers/mmc/host/sdhci_am654.c if (IS_ERR(sdhci_am654->base)) { base 482 drivers/mmc/host/sdhci_am654.c ret = PTR_ERR(sdhci_am654->base); base 609 drivers/mmc/host/toshsd.c resource_size_t base; base 656 drivers/mmc/host/toshsd.c base = pci_resource_start(pdev, 0); base 657 drivers/mmc/host/toshsd.c dev_dbg(&pdev->dev, "MMIO %pa, IRQ %d\n", &base, pdev->irq); base 159 drivers/mmc/host/usdhi6rol0.c void __iomem *base; base 210 drivers/mmc/host/usdhi6rol0.c iowrite32(data, host->base + reg); base 212 drivers/mmc/host/usdhi6rol0.c host->base, reg, data); base 217 drivers/mmc/host/usdhi6rol0.c iowrite16(data, host->base + reg); base 219 drivers/mmc/host/usdhi6rol0.c host->base, reg, data); base 224 drivers/mmc/host/usdhi6rol0.c u32 data = ioread32(host->base + reg); base 226 drivers/mmc/host/usdhi6rol0.c host->base, reg, data); base 232 drivers/mmc/host/usdhi6rol0.c u16 data = ioread16(host->base + reg); base 234 drivers/mmc/host/usdhi6rol0.c host->base, reg, data); base 1786 drivers/mmc/host/usdhi6rol0.c host->base = devm_ioremap_resource(dev, res); base 1787 drivers/mmc/host/usdhi6rol0.c if (IS_ERR(host->base)) { base 1788 drivers/mmc/host/usdhi6rol0.c ret = PTR_ERR(host->base); base 1077 drivers/mmc/host/via-sdmmc.c u32 base, len; base 1108 drivers/mmc/host/via-sdmmc.c base = pci_resource_start(pcidev, 0); base 1109 drivers/mmc/host/via-sdmmc.c sdhost->mmiobase = ioremap_nocache(base, len); base 115 drivers/mmc/host/wbsd.c outb(index, host->base + WBSD_IDXR); base 116 drivers/mmc/host/wbsd.c outb(value, host->base + WBSD_DATAR); base 121 drivers/mmc/host/wbsd.c outb(index, host->base + WBSD_IDXR); base 122 drivers/mmc/host/wbsd.c return inb(host->base + WBSD_DATAR); base 155 drivers/mmc/host/wbsd.c outb(WBSD_POWER_N, host->base + WBSD_CSR); base 165 drivers/mmc/host/wbsd.c if (inb(host->base + WBSD_CSR) & WBSD_CARDPRESENT) base 180 drivers/mmc/host/wbsd.c outb(ier, host->base + WBSD_EIR); base 185 drivers/mmc/host/wbsd.c inb(host->base + WBSD_ISR); base 353 drivers/mmc/host/wbsd.c outb(cmd->opcode, host->base + WBSD_CMDR); base 355 drivers/mmc/host/wbsd.c outb((cmd->arg >> (i * 8)) & 0xff, host->base + WBSD_CMDR); base 417 drivers/mmc/host/wbsd.c while (!((fsr = inb(host->base + WBSD_FSR)) & WBSD_FIFO_EMPTY)) { base 430 drivers/mmc/host/wbsd.c buffer[idx++] = inb(host->base + WBSD_DFR); base 483 drivers/mmc/host/wbsd.c while (!((fsr = inb(host->base + WBSD_FSR)) & WBSD_FIFO_FULL)) { base 496 drivers/mmc/host/wbsd.c outb(buffer[idx], host->base + WBSD_DFR); base 871 drivers/mmc/host/wbsd.c pwr = inb(host->base + WBSD_CSR); base 873 drivers/mmc/host/wbsd.c outb(pwr, host->base + WBSD_CSR); base 915 drivers/mmc/host/wbsd.c csr = inb(host->base + WBSD_CSR); base 917 drivers/mmc/host/wbsd.c outb(csr, host->base + WBSD_CSR); base 921 drivers/mmc/host/wbsd.c csr = inb(host->base + WBSD_CSR); base 923 drivers/mmc/host/wbsd.c outb(csr, host->base + WBSD_CSR); base 1001 drivers/mmc/host/wbsd.c csr = inb(host->base + WBSD_CSR); base 1146 drivers/mmc/host/wbsd.c isr = inb(host->base + WBSD_ISR); base 1329 drivers/mmc/host/wbsd.c static int wbsd_request_region(struct wbsd_host *host, int base) base 1331 drivers/mmc/host/wbsd.c if (base & 0x7) base 1334 drivers/mmc/host/wbsd.c if (!request_region(base, 8, DRIVER_NAME)) base 1337 drivers/mmc/host/wbsd.c host->base = base; base 1344 drivers/mmc/host/wbsd.c if (host->base) base 1345 drivers/mmc/host/wbsd.c release_region(host->base, 8); base 1347 drivers/mmc/host/wbsd.c host->base = 0; base 1494 drivers/mmc/host/wbsd.c int base, int irq, int dma) base 1501 drivers/mmc/host/wbsd.c ret = wbsd_request_region(host, base); base 1558 drivers/mmc/host/wbsd.c wbsd_write_config(host, WBSD_CONF_PORT_HI, host->base >> 8); base 1559 drivers/mmc/host/wbsd.c wbsd_write_config(host, WBSD_CONF_PORT_LO, host->base & 0xff); base 1581 drivers/mmc/host/wbsd.c int base, irq, dma; base 1593 drivers/mmc/host/wbsd.c base = wbsd_read_config(host, WBSD_CONF_PORT_HI) << 8; base 1594 drivers/mmc/host/wbsd.c base |= wbsd_read_config(host, WBSD_CONF_PORT_LO); base 1605 drivers/mmc/host/wbsd.c if (base != host->base) base 1635 drivers/mmc/host/wbsd.c static int wbsd_init(struct device *dev, int base, int irq, int dma, base 1665 drivers/mmc/host/wbsd.c ret = wbsd_request_resources(host, base, irq, dma); base 1709 drivers/mmc/host/wbsd.c printk(" at 0x%x irq %d", (int)host->base, (int)host->irq); base 170 drivers/mmc/host/wbsd.h int base; /* I/O port base */ base 1492 drivers/mtd/chips/cfi_cmdset_0002.c unsigned long base; base 1511 drivers/mtd/chips/cfi_cmdset_0002.c base = chip->start; base 1516 drivers/mtd/chips/cfi_cmdset_0002.c ret = get_chip(map, chip, base, FL_CFI_QUERY); base 1521 drivers/mtd/chips/cfi_cmdset_0002.c cfi_qry_mode_on(base, map, cfi); base 1522 drivers/mtd/chips/cfi_cmdset_0002.c otp = cfi_read_query(map, base + 0x3 * ofs_factor); base 1523 drivers/mtd/chips/cfi_cmdset_0002.c cfi_qry_mode_off(base, map, cfi); base 1524 drivers/mtd/chips/cfi_cmdset_0002.c put_chip(map, chip, base); base 1537 drivers/mtd/chips/cfi_cmdset_0002.c ret = get_chip(map, chip, base, FL_LOCKING); base 27 drivers/mtd/chips/cfi_probe.c static int cfi_probe_chip(struct map_info *map, __u32 base, base 38 drivers/mtd/chips/cfi_probe.c #define xip_allowed(base, map) \ base 40 drivers/mtd/chips/cfi_probe.c (void) map_read(map, base); \ base 45 drivers/mtd/chips/cfi_probe.c #define xip_enable(base, map, cfi) \ base 47 drivers/mtd/chips/cfi_probe.c cfi_qry_mode_off(base, map, cfi); \ base 48 drivers/mtd/chips/cfi_probe.c xip_allowed(base, map); \ base 51 drivers/mtd/chips/cfi_probe.c #define xip_disable_qry(base, map, cfi) \ base 54 drivers/mtd/chips/cfi_probe.c cfi_qry_mode_on(base, map, cfi); \ base 60 drivers/mtd/chips/cfi_probe.c #define xip_allowed(base, map) do { } while (0) base 61 drivers/mtd/chips/cfi_probe.c #define xip_enable(base, map, cfi) do { } while (0) base 62 drivers/mtd/chips/cfi_probe.c #define xip_disable_qry(base, map, cfi) do { } while (0) base 95 drivers/mtd/chips/cfi_probe.c static int __xipram cfi_probe_chip(struct map_info *map, __u32 base, base 100 drivers/mtd/chips/cfi_probe.c if ((base + 0) >= map->size) { base 103 drivers/mtd/chips/cfi_probe.c (unsigned long)base, map->size -1); base 106 drivers/mtd/chips/cfi_probe.c if ((base + 0xff) >= map->size) { base 109 drivers/mtd/chips/cfi_probe.c (unsigned long)base + 0x55, map->size -1); base 114 drivers/mtd/chips/cfi_probe.c if (!cfi_qry_mode_on(base, map, cfi)) { base 115 drivers/mtd/chips/cfi_probe.c xip_enable(base, map, cfi); base 126 drivers/mtd/chips/cfi_probe.c for (i=0; i < (base >> cfi->chipshift); i++) { base 142 drivers/mtd/chips/cfi_probe.c xip_allowed(base, map); base 144 drivers/mtd/chips/cfi_probe.c map->name, base, start); base 151 drivers/mtd/chips/cfi_probe.c cfi_qry_mode_off(base, map, cfi); base 153 drivers/mtd/chips/cfi_probe.c if (cfi_qry_present(map, base, cfi)) { base 154 drivers/mtd/chips/cfi_probe.c xip_allowed(base, map); base 156 drivers/mtd/chips/cfi_probe.c map->name, base, start); base 164 drivers/mtd/chips/cfi_probe.c set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */ base 168 drivers/mtd/chips/cfi_probe.c cfi_qry_mode_off(base, map, cfi); base 169 drivers/mtd/chips/cfi_probe.c xip_allowed(base, map); base 172 drivers/mtd/chips/cfi_probe.c map->name, cfi->interleave, cfi->device_type*8, base, base 198 drivers/mtd/chips/cfi_probe.c __u32 base = 0; base 199 drivers/mtd/chips/cfi_probe.c int num_erase_regions = cfi_read_query(map, base + (0x10 + 28)*ofs_factor); base 203 drivers/mtd/chips/cfi_probe.c xip_enable(base, map, cfi); base 221 drivers/mtd/chips/cfi_probe.c xip_disable_qry(base, map, cfi); base 223 drivers/mtd/chips/cfi_probe.c ((unsigned char *)cfi->cfiq)[i] = cfi_read_query(map,base + (0x10 + i)*ofs_factor); base 262 drivers/mtd/chips/cfi_probe.c cfi_send_gen_cmd(0xf0, 0, base, map, cfi, cfi->device_type, NULL); base 263 drivers/mtd/chips/cfi_probe.c cfi_send_gen_cmd(0xaa, addr_unlock1, base, map, cfi, cfi->device_type, NULL); base 264 drivers/mtd/chips/cfi_probe.c cfi_send_gen_cmd(0x55, addr_unlock2, base, map, cfi, cfi->device_type, NULL); base 265 drivers/mtd/chips/cfi_probe.c cfi_send_gen_cmd(0x90, addr_unlock1, base, map, cfi, cfi->device_type, NULL); base 266 drivers/mtd/chips/cfi_probe.c cfi->mfr = cfi_read_query16(map, base); base 267 drivers/mtd/chips/cfi_probe.c cfi->id = cfi_read_query16(map, base + ofs_factor); base 271 drivers/mtd/chips/cfi_probe.c cfi->id = cfi_read_query(map, base + 0xe * ofs_factor) << 8 | base 272 drivers/mtd/chips/cfi_probe.c cfi_read_query(map, base + 0xf * ofs_factor); base 275 drivers/mtd/chips/cfi_probe.c cfi_qry_mode_off(base, map, cfi); base 276 drivers/mtd/chips/cfi_probe.c xip_allowed(base, map); base 281 drivers/mtd/chips/cfi_probe.c map->name, cfi->interleave, cfi->device_type*8, base, base 203 drivers/mtd/chips/cfi_util.c uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base, base 208 drivers/mtd/chips/cfi_util.c uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, map, cfi); base 216 drivers/mtd/chips/cfi_util.c return addr - base; base 220 drivers/mtd/chips/cfi_util.c int __xipram cfi_qry_present(struct map_info *map, __u32 base, base 231 drivers/mtd/chips/cfi_util.c val[0] = map_read(map, base + osf*0x10); base 232 drivers/mtd/chips/cfi_util.c val[1] = map_read(map, base + osf*0x11); base 233 drivers/mtd/chips/cfi_util.c val[2] = map_read(map, base + osf*0x12); base 248 drivers/mtd/chips/cfi_util.c int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map, base 251 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); base 252 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL); base 253 drivers/mtd/chips/cfi_util.c if (cfi_qry_present(map, base, cfi)) base 257 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); base 258 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); base 259 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL); base 260 drivers/mtd/chips/cfi_util.c if (cfi_qry_present(map, base, cfi)) base 263 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); base 264 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0x98, 0x555, base, map, cfi, cfi->device_type, NULL); base 265 drivers/mtd/chips/cfi_util.c if (cfi_qry_present(map, base, cfi)) base 268 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); base 269 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0xAA, 0x5555, base, map, cfi, cfi->device_type, NULL); base 270 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0x55, 0x2AAA, base, map, cfi, cfi->device_type, NULL); base 271 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0x98, 0x5555, base, map, cfi, cfi->device_type, NULL); base 272 drivers/mtd/chips/cfi_util.c if (cfi_qry_present(map, base, cfi)) base 275 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); base 276 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0xAA, 0x555, base, map, cfi, cfi->device_type, NULL); base 277 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0x55, 0x2AA, base, map, cfi, cfi->device_type, NULL); base 278 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0x98, 0x555, base, map, cfi, cfi->device_type, NULL); base 279 drivers/mtd/chips/cfi_util.c if (cfi_qry_present(map, base, cfi)) base 286 drivers/mtd/chips/cfi_util.c void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map, base 289 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); base 290 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); base 294 drivers/mtd/chips/cfi_util.c cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); base 302 drivers/mtd/chips/cfi_util.c __u32 base = 0; // cfi->chips[0].start; base 321 drivers/mtd/chips/cfi_util.c cfi_qry_mode_on(base, map, cfi); base 325 drivers/mtd/chips/cfi_util.c cfi_read_query(map, base+((adr+i)*ofs_factor)); base 329 drivers/mtd/chips/cfi_util.c cfi_qry_mode_off(base, map, cfi); base 332 drivers/mtd/chips/cfi_util.c (void) map_read(map, base); base 1910 drivers/mtd/chips/jedec_probe.c static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base, base 1926 drivers/mtd/chips/jedec_probe.c result = map_read(map, base + ofs); base 1933 drivers/mtd/chips/jedec_probe.c static inline u32 jedec_read_id(struct map_info *map, uint32_t base, base 1940 drivers/mtd/chips/jedec_probe.c result = map_read(map, base + ofs); base 1944 drivers/mtd/chips/jedec_probe.c static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi) base 1957 drivers/mtd/chips/jedec_probe.c cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); base 1958 drivers/mtd/chips/jedec_probe.c cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); base 1961 drivers/mtd/chips/jedec_probe.c cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); base 1967 drivers/mtd/chips/jedec_probe.c cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); base 2030 drivers/mtd/chips/jedec_probe.c static inline int jedec_match( uint32_t base, base 2083 drivers/mtd/chips/jedec_probe.c __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) ); base 2084 drivers/mtd/chips/jedec_probe.c if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) { base 2119 drivers/mtd/chips/jedec_probe.c jedec_reset( base, map, cfi ); base 2120 drivers/mtd/chips/jedec_probe.c mfr = jedec_read_mfr( map, base, cfi ); base 2121 drivers/mtd/chips/jedec_probe.c id = jedec_read_id( map, base, cfi ); base 2138 drivers/mtd/chips/jedec_probe.c cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); base 2139 drivers/mtd/chips/jedec_probe.c cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); base 2141 drivers/mtd/chips/jedec_probe.c cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); base 2149 drivers/mtd/chips/jedec_probe.c static int jedec_probe_chip(struct map_info *map, __u32 base, base 2168 drivers/mtd/chips/jedec_probe.c if (base >= map->size) { base 2171 drivers/mtd/chips/jedec_probe.c base, map->size -1); base 2178 drivers/mtd/chips/jedec_probe.c if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || base 2179 drivers/mtd/chips/jedec_probe.c ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) base 2183 drivers/mtd/chips/jedec_probe.c jedec_reset(base, map, cfi); base 2187 drivers/mtd/chips/jedec_probe.c cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); base 2188 drivers/mtd/chips/jedec_probe.c cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); base 2190 drivers/mtd/chips/jedec_probe.c cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); base 2197 drivers/mtd/chips/jedec_probe.c cfi->mfr = jedec_read_mfr(map, base, cfi); base 2198 drivers/mtd/chips/jedec_probe.c cfi->id = jedec_read_id(map, base, cfi); base 2202 drivers/mtd/chips/jedec_probe.c if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) { base 2217 drivers/mtd/chips/jedec_probe.c mfr = jedec_read_mfr(map, base, cfi); base 2218 drivers/mtd/chips/jedec_probe.c id = jedec_read_id(map, base, cfi); base 2222 drivers/mtd/chips/jedec_probe.c map->name, mfr, id, base); base 2223 drivers/mtd/chips/jedec_probe.c jedec_reset(base, map, cfi); base 2229 drivers/mtd/chips/jedec_probe.c for (i=0; i < (base >> cfi->chipshift); i++) { base 2242 drivers/mtd/chips/jedec_probe.c if (jedec_read_mfr(map, base, cfi) != cfi->mfr || base 2243 drivers/mtd/chips/jedec_probe.c jedec_read_id(map, base, cfi) != cfi->id) { base 2245 drivers/mtd/chips/jedec_probe.c map->name, base, start); base 2253 drivers/mtd/chips/jedec_probe.c jedec_reset(base, map, cfi); base 2254 drivers/mtd/chips/jedec_probe.c if (jedec_read_mfr(map, base, cfi) == cfi->mfr && base 2255 drivers/mtd/chips/jedec_probe.c jedec_read_id(map, base, cfi) == cfi->id) { base 2257 drivers/mtd/chips/jedec_probe.c map->name, base, start); base 2265 drivers/mtd/chips/jedec_probe.c set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */ base 2270 drivers/mtd/chips/jedec_probe.c jedec_reset(base, map, cfi); base 2273 drivers/mtd/chips/jedec_probe.c map->name, cfi_interleave(cfi), cfi->device_type*8, base, base 326 drivers/mtd/devices/block2mtd.c static int ustrtoul(const char *cp, char **endp, unsigned int base) base 328 drivers/mtd/devices/block2mtd.c unsigned long result = simple_strtoul(cp, endp, base); base 94 drivers/mtd/devices/docg3.c u8 val = readb(docg3->cascade->base + reg); base 102 drivers/mtd/devices/docg3.c u16 val = readw(docg3->cascade->base + reg); base 110 drivers/mtd/devices/docg3.c writeb(val, docg3->cascade->base + reg); base 116 drivers/mtd/devices/docg3.c writew(val, docg3->cascade->base + reg); base 1839 drivers/mtd/devices/docg3.c docg3->cascade->base, floor); base 1968 drivers/mtd/devices/docg3.c void __iomem *base; base 1978 drivers/mtd/devices/docg3.c base = devm_ioremap(dev, ress->start, DOC_IOSPACE_SIZE); base 1985 drivers/mtd/devices/docg3.c cascade->base = base; base 266 drivers/mtd/devices/docg3.h void __iomem *base; base 450 drivers/mtd/devices/mtd_dataflash.c static ssize_t otp_read(struct spi_device *spi, unsigned base, base 467 drivers/mtd/devices/mtd_dataflash.c l = 4 + base + off + len; base 487 drivers/mtd/devices/mtd_dataflash.c memcpy(buf, scratch + 4 + base + off, len); base 257 drivers/mtd/devices/st_spi_fsm.c void __iomem *base; base 705 drivers/mtd/devices/st_spi_fsm.c return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10; base 710 drivers/mtd/devices/st_spi_fsm.c return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f; base 716 drivers/mtd/devices/st_spi_fsm.c void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE; base 769 drivers/mtd/devices/st_spi_fsm.c readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words); base 809 drivers/mtd/devices/st_spi_fsm.c readl(fsm->base + SPI_FAST_SEQ_DATA_REG); base 831 drivers/mtd/devices/st_spi_fsm.c readl(fsm->base + SPI_FAST_SEQ_DATA_REG); base 845 drivers/mtd/devices/st_spi_fsm.c writesl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words); base 904 drivers/mtd/devices/st_spi_fsm.c writel(seq->seq_cfg, fsm->base + SPI_FAST_SEQ_CFG); base 1621 drivers/mtd/devices/st_spi_fsm.c writel(0x00040000, fsm->base + SPI_FAST_SEQ_CFG); base 1628 drivers/mtd/devices/st_spi_fsm.c readl(fsm->base + SPI_FAST_SEQ_CFG); base 1883 drivers/mtd/devices/st_spi_fsm.c ret = readl(fsm->base + SPI_STA_MODE_CHANGE); base 1892 drivers/mtd/devices/st_spi_fsm.c writel(mode, fsm->base + SPI_MODESELECT); base 1930 drivers/mtd/devices/st_spi_fsm.c writel(clk_div, fsm->base + SPI_CLOCKDIV); base 1938 drivers/mtd/devices/st_spi_fsm.c writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG); base 1940 drivers/mtd/devices/st_spi_fsm.c writel(0, fsm->base + SPI_FAST_SEQ_CFG); base 1955 drivers/mtd/devices/st_spi_fsm.c fsm->base + SPI_CONFIGDATA); base 1956 drivers/mtd/devices/st_spi_fsm.c writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG); base 1963 drivers/mtd/devices/st_spi_fsm.c writel(0x00000001, fsm->base + SPI_PROGRAM_ERASE_TIME); base 2043 drivers/mtd/devices/st_spi_fsm.c fsm->base = devm_ioremap_resource(&pdev->dev, res); base 2044 drivers/mtd/devices/st_spi_fsm.c if (IS_ERR(fsm->base)) { base 2047 drivers/mtd/devices/st_spi_fsm.c return PTR_ERR(fsm->base); base 31 drivers/mtd/maps/pci.c void __iomem *base; base 41 drivers/mtd/maps/pci.c val.x[0]= readb(map->base + map->translate(map, ofs)); base 49 drivers/mtd/maps/pci.c val.x[0] = readl(map->base + map->translate(map, ofs)); base 56 drivers/mtd/maps/pci.c memcpy_fromio(to, map->base + map->translate(map, from), len); base 62 drivers/mtd/maps/pci.c writeb(val.x[0], map->base + map->translate(map, ofs)); base 68 drivers/mtd/maps/pci.c writel(val.x[0], map->base + map->translate(map, ofs)); base 74 drivers/mtd/maps/pci.c memcpy_toio(map->base + map->translate(map, to), from, len); base 97 drivers/mtd/maps/pci.c map->base = ioremap_nocache(pci_resource_start(dev, 0), base 100 drivers/mtd/maps/pci.c if (!map->base) base 118 drivers/mtd/maps/pci.c if (map->base) base 119 drivers/mtd/maps/pci.c iounmap(map->base); base 133 drivers/mtd/maps/pci.c writel(0x00000008, map->base + 0x1558); base 134 drivers/mtd/maps/pci.c writel(0x00000000, map->base + 0x1550); base 136 drivers/mtd/maps/pci.c writel(0x00000007, map->base + 0x1558); base 137 drivers/mtd/maps/pci.c writel(0x00800000, map->base + 0x1550); base 158 drivers/mtd/maps/pci.c unsigned long base, len; base 160 drivers/mtd/maps/pci.c base = pci_resource_start(dev, PCI_ROM_RESOURCE); base 163 drivers/mtd/maps/pci.c if (!len || !base) { base 167 drivers/mtd/maps/pci.c base = pci_resource_start(dev, 2); base 184 drivers/mtd/maps/pci.c if (!len || !base) base 191 drivers/mtd/maps/pci.c map->base = ioremap_nocache(base, len); base 193 drivers/mtd/maps/pci.c if (!map->base) base 202 drivers/mtd/maps/pci.c if (map->base) base 203 drivers/mtd/maps/pci.c iounmap(map->base); base 36 drivers/mtd/maps/pismo.c phys_addr_t base; base 94 drivers/mtd/maps/pismo.c phys_addr_t base = region->base; base 97 drivers/mtd/maps/pismo.c if (base == ~0) base 100 drivers/mtd/maps/pismo.c res.start = base; base 101 drivers/mtd/maps/pismo.c res.end = base + region->size - 1; base 156 drivers/mtd/maps/pismo.c const struct pismo_cs_block *cs, phys_addr_t base) base 161 drivers/mtd/maps/pismo.c region.base = base; base 79 drivers/mtd/maps/scx200_docflash.c unsigned base; base 99 drivers/mtd/maps/scx200_docflash.c pci_read_config_dword(bridge, SCx200_DOCCS_BASE, &base); base 105 drivers/mtd/maps/scx200_docflash.c if (base == 0 base 122 drivers/mtd/maps/scx200_docflash.c docmem.start = base; base 123 drivers/mtd/maps/scx200_docflash.c docmem.end = base + size; base 775 drivers/mtd/mtdswap.c unsigned int h, x, y, dist, base; base 793 drivers/mtd/mtdswap.c base = COLLECT_NONDIRTY_BASE; base 795 drivers/mtd/mtdswap.c x = dist - base; base 796 drivers/mtd/mtdswap.c y = (x * h + base / 2) / base; base 879 drivers/mtd/mtdswap.c loff_t base, pos; base 891 drivers/mtd/mtdswap.c base = mtdswap_eb_offset(d, eb); base 895 drivers/mtd/mtdswap.c pos = base; base 907 drivers/mtd/mtdswap.c pos = base; base 49 drivers/mtd/nand/onenand/generic.c info->onenand.base = ioremap(res->start, size); base 50 drivers/mtd/nand/onenand/generic.c if (!info->onenand.base) { base 74 drivers/mtd/nand/onenand/generic.c iounmap(info->onenand.base); base 92 drivers/mtd/nand/onenand/generic.c iounmap(info->onenand.base); base 61 drivers/mtd/nand/onenand/omap2.c return readw(c->onenand.base + reg); base 67 drivers/mtd/nand/onenand/omap2.c writew(value, c->onenand.base + reg); base 385 drivers/mtd/nand/onenand/omap2.c memcpy(buf + count, this->base + bram_offset + count, xtra); base 404 drivers/mtd/nand/onenand/omap2.c memcpy(buf, this->base + bram_offset, count); base 444 drivers/mtd/nand/onenand/omap2.c memcpy(this->base + bram_offset, buf, count); base 456 drivers/mtd/nand/onenand/omap2.c memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE); base 491 drivers/mtd/nand/onenand/omap2.c c->onenand.base = devm_ioremap_resource(dev, res); base 492 drivers/mtd/nand/onenand/omap2.c if (IS_ERR(c->onenand.base)) base 493 drivers/mtd/nand/onenand/omap2.c return PTR_ERR(c->onenand.base); base 529 drivers/mtd/nand/onenand/omap2.c c->gpmc_cs, c->phys_base, c->onenand.base, base 457 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); base 472 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); base 476 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); base 504 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8); base 508 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + ONENAND_REG_START_BUFFER); base 512 drivers/mtd/nand/onenand/onenand_base.c this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT); base 515 drivers/mtd/nand/onenand/onenand_base.c this->write_word(cmd, this->base + ONENAND_REG_COMMAND); base 529 drivers/mtd/nand/onenand/onenand_base.c return this->read_word(this->base + ONENAND_REG_ECC_STATUS); base 532 drivers/mtd/nand/onenand/onenand_base.c ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS + i*2); base 564 drivers/mtd/nand/onenand/onenand_base.c interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); base 573 drivers/mtd/nand/onenand/onenand_base.c interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); base 575 drivers/mtd/nand/onenand/onenand_base.c ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); base 718 drivers/mtd/nand/onenand/onenand_base.c syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); base 720 drivers/mtd/nand/onenand/onenand_base.c this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); base 764 drivers/mtd/nand/onenand/onenand_base.c bufferram = this->base + area; base 800 drivers/mtd/nand/onenand/onenand_base.c bufferram = this->base + area; base 840 drivers/mtd/nand/onenand/onenand_base.c bufferram = this->base + area; base 925 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); base 1281 drivers/mtd/nand/onenand/onenand_base.c this->write_word(ONENAND_DDP_CHIP0, this->base + ONENAND_REG_START_ADDRESS2); base 1310 drivers/mtd/nand/onenand/onenand_base.c this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2); base 1488 drivers/mtd/nand/onenand/onenand_base.c interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); base 1493 drivers/mtd/nand/onenand/onenand_base.c interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); base 1494 drivers/mtd/nand/onenand/onenand_base.c ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); base 1495 drivers/mtd/nand/onenand/onenand_base.c addr1 = this->read_word(this->base + ONENAND_REG_START_ADDRESS1); base 1496 drivers/mtd/nand/onenand/onenand_base.c addr8 = this->read_word(this->base + ONENAND_REG_START_ADDRESS8); base 1683 drivers/mtd/nand/onenand/onenand_base.c interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); base 2518 drivers/mtd/nand/onenand/onenand_base.c this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS); base 2520 drivers/mtd/nand/onenand/onenand_base.c this->write_word(end, this->base + ONENAND_REG_END_BLOCK_ADDRESS); base 2528 drivers/mtd/nand/onenand/onenand_base.c while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) base 2533 drivers/mtd/nand/onenand/onenand_base.c status = this->read_word(this->base + ONENAND_REG_WP_STATUS); base 2545 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); base 2548 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); base 2550 drivers/mtd/nand/onenand/onenand_base.c this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); base 2558 drivers/mtd/nand/onenand/onenand_base.c while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) base 2563 drivers/mtd/nand/onenand/onenand_base.c status = this->read_word(this->base + ONENAND_REG_WP_STATUS); base 2623 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); base 2626 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); base 2628 drivers/mtd/nand/onenand/onenand_base.c this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); base 2631 drivers/mtd/nand/onenand/onenand_base.c status = this->read_word(this->base + ONENAND_REG_WP_STATUS); base 2656 drivers/mtd/nand/onenand/onenand_base.c this->write_word(0, this->base + ONENAND_REG_START_BLOCK_ADDRESS); base 2664 drivers/mtd/nand/onenand/onenand_base.c while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) base 2728 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + base 2747 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + base 2752 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + ONENAND_REG_START_BUFFER); base 2756 drivers/mtd/nand/onenand/onenand_base.c this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT); base 2759 drivers/mtd/nand/onenand/onenand_base.c this->write_word(cmd, this->base + ONENAND_REG_COMMAND); base 2809 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + base 2818 drivers/mtd/nand/onenand/onenand_base.c this->write_word(value, this->base + base 2858 drivers/mtd/nand/onenand/onenand_base.c status = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); base 3256 drivers/mtd/nand/onenand/onenand_base.c numbufs = this->read_word(this->base + ONENAND_REG_NUM_BUFFERS) >> 8; base 3398 drivers/mtd/nand/onenand/onenand_base.c syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); base 3399 drivers/mtd/nand/onenand/onenand_base.c this->write_word((syscfg | 0x0100), this->base + ONENAND_REG_SYS_CFG1); base 3408 drivers/mtd/nand/onenand/onenand_base.c bdry = this->read_word(this->base + ONENAND_DATARAM); base 3423 drivers/mtd/nand/onenand/onenand_base.c this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); base 3602 drivers/mtd/nand/onenand/onenand_base.c thisboundary = this->read_word(this->base + ONENAND_DATARAM); base 3625 drivers/mtd/nand/onenand/onenand_base.c this->write_word(boundary, this->base + ONENAND_DATARAM); base 3637 drivers/mtd/nand/onenand/onenand_base.c this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND); base 3660 drivers/mtd/nand/onenand/onenand_base.c syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); base 3662 drivers/mtd/nand/onenand/onenand_base.c this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE), this->base + ONENAND_REG_SYS_CFG1); base 3665 drivers/mtd/nand/onenand/onenand_base.c this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM); base 3668 drivers/mtd/nand/onenand/onenand_base.c bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0); base 3669 drivers/mtd/nand/onenand/onenand_base.c bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2); base 3672 drivers/mtd/nand/onenand/onenand_base.c this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM); base 3677 drivers/mtd/nand/onenand/onenand_base.c this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); base 3684 drivers/mtd/nand/onenand/onenand_base.c maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID); base 3685 drivers/mtd/nand/onenand/onenand_base.c dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); base 3710 drivers/mtd/nand/onenand/onenand_base.c dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); base 3711 drivers/mtd/nand/onenand/onenand_base.c ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID); base 3712 drivers/mtd/nand/onenand/onenand_base.c this->technology = this->read_word(this->base + ONENAND_REG_TECHNOLOGY); base 3743 drivers/mtd/nand/onenand/onenand_base.c mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE); base 126 drivers/mtd/nand/onenand/samsung.c void __iomem *base; base 147 drivers/mtd/nand/onenand/samsung.c return readl(onenand->base + offset); base 152 drivers/mtd/nand/onenand/samsung.c writel(value, onenand->base + offset); base 172 drivers/mtd/nand/onenand/samsung.c (unsigned int) onenand->base + i, base 220 drivers/mtd/nand/onenand/samsung.c int reg = addr - this->base; base 270 drivers/mtd/nand/onenand/samsung.c unsigned int reg = addr - this->base; base 519 drivers/mtd/nand/onenand/samsung.c void __iomem *base = onenand->dma_addr; base 523 drivers/mtd/nand/onenand/samsung.c writel(src, base + S5PC110_DMA_SRC_ADDR); base 524 drivers/mtd/nand/onenand/samsung.c writel(dst, base + S5PC110_DMA_DST_ADDR); base 527 drivers/mtd/nand/onenand/samsung.c writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG); base 528 drivers/mtd/nand/onenand/samsung.c writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG); base 530 drivers/mtd/nand/onenand/samsung.c writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG); base 531 drivers/mtd/nand/onenand/samsung.c writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG); base 534 drivers/mtd/nand/onenand/samsung.c writel(count, base + S5PC110_DMA_TRANS_SIZE); base 535 drivers/mtd/nand/onenand/samsung.c writel(direction, base + S5PC110_DMA_TRANS_DIR); base 537 drivers/mtd/nand/onenand/samsung.c writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD); base 547 drivers/mtd/nand/onenand/samsung.c status = readl(base + S5PC110_DMA_TRANS_STATUS); base 550 drivers/mtd/nand/onenand/samsung.c base + S5PC110_DMA_TRANS_CMD); base 556 drivers/mtd/nand/onenand/samsung.c writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD); base 563 drivers/mtd/nand/onenand/samsung.c void __iomem *base = onenand->dma_addr; base 566 drivers/mtd/nand/onenand/samsung.c status = readl(base + S5PC110_INTC_DMA_STATUS); base 574 drivers/mtd/nand/onenand/samsung.c writel(cmd, base + S5PC110_DMA_TRANS_CMD); base 575 drivers/mtd/nand/onenand/samsung.c writel(status, base + S5PC110_INTC_DMA_CLR); base 585 drivers/mtd/nand/onenand/samsung.c void __iomem *base = onenand->dma_addr; base 588 drivers/mtd/nand/onenand/samsung.c status = readl(base + S5PC110_INTC_DMA_MASK); base 591 drivers/mtd/nand/onenand/samsung.c writel(status, base + S5PC110_INTC_DMA_MASK); base 594 drivers/mtd/nand/onenand/samsung.c writel(src, base + S5PC110_DMA_SRC_ADDR); base 595 drivers/mtd/nand/onenand/samsung.c writel(dst, base + S5PC110_DMA_DST_ADDR); base 598 drivers/mtd/nand/onenand/samsung.c writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG); base 599 drivers/mtd/nand/onenand/samsung.c writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG); base 601 drivers/mtd/nand/onenand/samsung.c writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG); base 602 drivers/mtd/nand/onenand/samsung.c writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG); base 605 drivers/mtd/nand/onenand/samsung.c writel(count, base + S5PC110_DMA_TRANS_SIZE); base 606 drivers/mtd/nand/onenand/samsung.c writel(direction, base + S5PC110_DMA_TRANS_DIR); base 608 drivers/mtd/nand/onenand/samsung.c writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD); base 625 drivers/mtd/nand/onenand/samsung.c p = this->base + area; base 653 drivers/mtd/nand/onenand/samsung.c dma_src = onenand->phys_base + (p - this->base); base 657 drivers/mtd/nand/onenand/samsung.c dma_src = onenand->phys_base + (p - this->base); base 864 drivers/mtd/nand/onenand/samsung.c onenand->base = devm_ioremap_resource(&pdev->dev, r); base 865 drivers/mtd/nand/onenand/samsung.c if (IS_ERR(onenand->base)) base 866 drivers/mtd/nand/onenand/samsung.c return PTR_ERR(onenand->base); base 871 drivers/mtd/nand/onenand/samsung.c this->base = onenand->base; base 31 drivers/mtd/nand/raw/ams-delta.c struct nand_controller base; base 308 drivers/mtd/nand/raw/ams-delta.c priv->base.ops = &ams_delta_ops; base 309 drivers/mtd/nand/raw/ams-delta.c nand_controller_init(&priv->base); base 310 drivers/mtd/nand/raw/ams-delta.c this->controller = &priv->base; base 163 drivers/mtd/nand/raw/atmel/nand-controller.c struct nand_chip base; base 173 drivers/mtd/nand/raw/atmel/nand-controller.c return container_of(chip, struct atmel_nand, base); base 217 drivers/mtd/nand/raw/atmel/nand-controller.c struct nand_controller base; base 230 drivers/mtd/nand/raw/atmel/nand-controller.c return container_of(ctl, struct atmel_nand_controller, base); base 239 drivers/mtd/nand/raw/atmel/nand-controller.c struct atmel_nand_controller base; base 248 drivers/mtd/nand/raw/atmel/nand-controller.c struct atmel_smc_nand_controller, base); base 252 drivers/mtd/nand/raw/atmel/nand-controller.c struct atmel_nand_controller base; base 272 drivers/mtd/nand/raw/atmel/nand-controller.c struct atmel_hsmc_nand_controller, base); base 289 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr); base 295 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd); base 314 drivers/mtd/nand/raw/atmel/nand-controller.c ret = regmap_read_poll_timeout(nc->base.smc, base 321 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER, base 330 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); base 334 drivers/mtd/nand/raw/atmel/nand-controller.c dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n"); base 339 drivers/mtd/nand/raw/atmel/nand-controller.c dev_err(nc->base.dev, "Access to an undefined area\n"); base 344 drivers/mtd/nand/raw/atmel/nand-controller.c dev_err(nc->base.dev, "Access while busy\n"); base 349 drivers/mtd/nand/raw/atmel/nand-controller.c dev_err(nc->base.dev, "Wrong access size\n"); base 513 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status); base 529 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, base 537 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG, base 545 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, base 562 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++); base 582 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val); base 589 drivers/mtd/nand/raw/atmel/nand-controller.c dev_err(nc->base.dev, base 655 drivers/mtd/nand/raw/atmel/nand-controller.c if (nc->base.dmac) base 656 drivers/mtd/nand/raw/atmel/nand-controller.c ret = atmel_nand_dma_transfer(&nc->base, (void *)buf, base 678 drivers/mtd/nand/raw/atmel/nand-controller.c if (nc->base.dmac) base 679 drivers/mtd/nand/raw/atmel/nand-controller.c ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma, base 929 drivers/mtd/nand/raw/atmel/nand-controller.c dev_err(nc->base.dev, base 949 drivers/mtd/nand/raw/atmel/nand-controller.c dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n", base 1014 drivers/mtd/nand/raw/atmel/nand-controller.c dev_err(nc->base.dev, base 1075 drivers/mtd/nand/raw/atmel/nand-controller.c else if (chip->base.eccreq.strength) base 1076 drivers/mtd/nand/raw/atmel/nand-controller.c req.ecc.strength = chip->base.eccreq.strength; base 1082 drivers/mtd/nand/raw/atmel/nand-controller.c else if (chip->base.eccreq.step_size) base 1083 drivers/mtd/nand/raw/atmel/nand-controller.c req.ecc.sectorsize = chip->base.eccreq.step_size; base 1178 drivers/mtd/nand/raw/atmel/nand-controller.c nc = to_nand_controller(nand->base.controller); base 1390 drivers/mtd/nand/raw/atmel/nand-controller.c if (nand->base.options & NAND_BUSWIDTH_16) base 1409 drivers/mtd/nand/raw/atmel/nand-controller.c nc = to_nand_controller(nand->base.controller); base 1434 drivers/mtd/nand/raw/atmel/nand-controller.c nc = to_hsmc_nand_controller(nand->base.controller); base 1449 drivers/mtd/nand/raw/atmel/nand-controller.c atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id, base 1461 drivers/mtd/nand/raw/atmel/nand-controller.c nc = to_nand_controller(nand->base.controller); base 1473 drivers/mtd/nand/raw/atmel/nand-controller.c struct nand_chip *chip = &nand->base; base 1477 drivers/mtd/nand/raw/atmel/nand-controller.c nand->base.controller = &nc->base; base 1507 drivers/mtd/nand/raw/atmel/nand-controller.c struct nand_chip *chip = &nand->base; base 1533 drivers/mtd/nand/raw/atmel/nand-controller.c struct nand_chip *chip = &nand->base; base 1544 drivers/mtd/nand/raw/atmel/nand-controller.c struct nand_chip *chip = &nand->base; base 1658 drivers/mtd/nand/raw/atmel/nand-controller.c nand_set_flash_node(&nand->base, np); base 1667 drivers/mtd/nand/raw/atmel/nand-controller.c struct nand_chip *chip = &nand->base; base 1783 drivers/mtd/nand/raw/atmel/nand-controller.c nand_set_flash_node(&nand->base, nc->dev->of_node); base 1970 drivers/mtd/nand/raw/atmel/nand-controller.c nand_controller_init(&nc->base); base 1971 drivers/mtd/nand/raw/atmel/nand-controller.c nc->base.ops = &atmel_nand_controller_ops; base 2028 drivers/mtd/nand/raw/atmel/nand-controller.c struct device *dev = nc->base.dev; base 2034 drivers/mtd/nand/raw/atmel/nand-controller.c if (nc->base.caps->legacy_of_bindings) base 2038 drivers/mtd/nand/raw/atmel/nand-controller.c nc->base.caps->ebi_csa_regmap_name, 0); base 2078 drivers/mtd/nand/raw/atmel/nand-controller.c struct device *dev = nc->base.dev; base 2153 drivers/mtd/nand/raw/atmel/nand-controller.c nc->base.smc = devm_regmap_init_mmio(dev, iomem, ®map_conf); base 2154 drivers/mtd/nand/raw/atmel/nand-controller.c if (IS_ERR(nc->base.smc)) { base 2155 drivers/mtd/nand/raw/atmel/nand-controller.c ret = PTR_ERR(nc->base.smc); base 2185 drivers/mtd/nand/raw/atmel/nand-controller.c struct device *dev = nc->base.dev; base 2221 drivers/mtd/nand/raw/atmel/nand-controller.c nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node, base 2224 drivers/mtd/nand/raw/atmel/nand-controller.c dev_err(nc->base.dev, "Missing SRAM\n"); base 2232 drivers/mtd/nand/raw/atmel/nand-controller.c dev_err(nc->base.dev, base 2250 drivers/mtd/nand/raw/atmel/nand-controller.c hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base); base 2277 drivers/mtd/nand/raw/atmel/nand-controller.c ret = atmel_nand_controller_init(&nc->base, pdev, caps); base 2290 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); base 2301 drivers/mtd/nand/raw/atmel/nand-controller.c regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG, base 2304 drivers/mtd/nand/raw/atmel/nand-controller.c ret = atmel_nand_controller_add_nands(&nc->base); base 2311 drivers/mtd/nand/raw/atmel/nand-controller.c atmel_hsmc_nand_controller_remove(&nc->base); base 2351 drivers/mtd/nand/raw/atmel/nand-controller.c ret = atmel_nand_controller_init(&nc->base, pdev, caps); base 2359 drivers/mtd/nand/raw/atmel/nand-controller.c return atmel_nand_controller_add_nands(&nc->base); base 2573 drivers/mtd/nand/raw/atmel/nand-controller.c nand_reset(&nand->base, i); base 153 drivers/mtd/nand/raw/atmel/pmecc.c void __iomem *base; base 437 drivers/mtd/nand/raw/atmel/pmecc.c value = readl_relaxed(user->pmecc->regs.base + base 760 drivers/mtd/nand/raw/atmel/pmecc.c ptr[i] = readb_relaxed(pmecc->regs.base + base 767 drivers/mtd/nand/raw/atmel/pmecc.c writel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL); base 768 drivers/mtd/nand/raw/atmel/pmecc.c writel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL); base 790 drivers/mtd/nand/raw/atmel/pmecc.c writel(cfg, pmecc->regs.base + ATMEL_PMECC_CFG); base 791 drivers/mtd/nand/raw/atmel/pmecc.c writel(user->cache.sarea, pmecc->regs.base + ATMEL_PMECC_SAREA); base 792 drivers/mtd/nand/raw/atmel/pmecc.c writel(user->cache.saddr, pmecc->regs.base + ATMEL_PMECC_SADDR); base 793 drivers/mtd/nand/raw/atmel/pmecc.c writel(user->cache.eaddr, pmecc->regs.base + ATMEL_PMECC_EADDR); base 795 drivers/mtd/nand/raw/atmel/pmecc.c writel(PMECC_CTRL_ENABLE, pmecc->regs.base + ATMEL_PMECC_CTRL); base 796 drivers/mtd/nand/raw/atmel/pmecc.c writel(PMECC_CTRL_DATA, pmecc->regs.base + ATMEL_PMECC_CTRL); base 815 drivers/mtd/nand/raw/atmel/pmecc.c ret = readl_relaxed_poll_timeout(pmecc->regs.base + base 825 drivers/mtd/nand/raw/atmel/pmecc.c user->isr = readl_relaxed(pmecc->regs.base + ATMEL_PMECC_ISR); base 848 drivers/mtd/nand/raw/atmel/pmecc.c pmecc->regs.base = devm_ioremap_resource(dev, res); base 849 drivers/mtd/nand/raw/atmel/pmecc.c if (IS_ERR(pmecc->regs.base)) base 850 drivers/mtd/nand/raw/atmel/pmecc.c return ERR_CAST(pmecc->regs.base); base 858 drivers/mtd/nand/raw/atmel/pmecc.c writel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR); base 22 drivers/mtd/nand/raw/au1550nd.c void __iomem *base; base 177 drivers/mtd/nand/raw/au1550nd.c this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_CMD; base 181 drivers/mtd/nand/raw/au1550nd.c this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA; base 185 drivers/mtd/nand/raw/au1550nd.c this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_ADDR; base 189 drivers/mtd/nand/raw/au1550nd.c this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA; base 357 drivers/mtd/nand/raw/au1550nd.c void __iomem *base = base 364 drivers/mtd/nand/raw/au1550nd.c staddr = __raw_readl(base + addr + 0x08); /* STADDRx */ base 407 drivers/mtd/nand/raw/au1550nd.c ctx->base = ioremap_nocache(r->start, 0x1000); base 408 drivers/mtd/nand/raw/au1550nd.c if (!ctx->base) { base 457 drivers/mtd/nand/raw/au1550nd.c iounmap(ctx->base); base 471 drivers/mtd/nand/raw/au1550nd.c iounmap(ctx->base); base 427 drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c chipsize = nanddev_target_size(&b47n->nand_chip.base) >> 20; base 19 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c void __iomem *base; base 33 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c void __iomem *mmio = priv->base + BCM63138_NAND_INT_STATUS; base 48 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c void __iomem *mmio = priv->base + BCM63138_NAND_INT_EN; base 72 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c priv->base = devm_ioremap_resource(dev, res); base 73 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c if (IS_ERR(priv->base)) base 74 drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c return PTR_ERR(priv->base); base 28 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c void __iomem *base; base 54 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c void __iomem *mmio = priv->base + BCM6368_NAND_INT; base 72 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c void __iomem *mmio = priv->base + BCM6368_NAND_INT; base 100 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c priv->base = devm_ioremap_resource(dev, res); base 101 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c if (IS_ERR(priv->base)) base 102 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c return PTR_ERR(priv->base); base 108 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c brcmnand_writel(0, priv->base + BCM6368_NAND_INT); base 110 drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c priv->base + BCM6368_NAND_INT); base 2263 drivers/mtd/nand/raw/brcmnand/brcmnand.c if (chip->base.eccreq.step_size && chip->base.eccreq.strength) { base 2265 drivers/mtd/nand/raw/brcmnand/brcmnand.c chip->ecc.size = chip->base.eccreq.step_size; base 2266 drivers/mtd/nand/raw/brcmnand/brcmnand.c chip->ecc.strength = chip->base.eccreq.strength; base 47 drivers/mtd/nand/raw/davinci_nand.c void __iomem *base; base 72 drivers/mtd/nand/raw/davinci_nand.c return __raw_readl(info->base + offset); base 78 drivers/mtd/nand/raw/davinci_nand.c __raw_writel(value, info->base + offset); base 695 drivers/mtd/nand/raw/davinci_nand.c void __iomem *base; base 735 drivers/mtd/nand/raw/davinci_nand.c base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2)); base 736 drivers/mtd/nand/raw/davinci_nand.c if (!base) { base 742 drivers/mtd/nand/raw/davinci_nand.c info->base = base; base 941 drivers/mtd/nand/raw/denali.c memorg = nanddev_get_memorg(&chip->base); base 1041 drivers/mtd/nand/raw/diskonchip.c memorg = nanddev_get_memorg(&this->base); base 1295 drivers/mtd/nand/raw/diskonchip.c if (nanddev_ntargets(&this->base) > doc->chips_per_floor) { base 775 drivers/mtd/nand/raw/fsl_elbc_nand.c nanddev_ntargets(&chip->base)); base 777 drivers/mtd/nand/raw/fsl_elbc_nand.c nanddev_target_size(&chip->base)); base 712 drivers/mtd/nand/raw/fsl_ifc_nand.c nanddev_ntargets(&chip->base)); base 714 drivers/mtd/nand/raw/fsl_ifc_nand.c nanddev_target_size(&chip->base)); base 56 drivers/mtd/nand/raw/fsmc_nand.c #define FSMC_NOR_REG(base, bank, reg) ((base) + \ base 135 drivers/mtd/nand/raw/fsmc_nand.c struct nand_controller base; base 976 drivers/mtd/nand/raw/fsmc_nand.c void __iomem *base; base 1011 drivers/mtd/nand/raw/fsmc_nand.c base = devm_ioremap_resource(&pdev->dev, res); base 1012 drivers/mtd/nand/raw/fsmc_nand.c if (IS_ERR(base)) base 1013 drivers/mtd/nand/raw/fsmc_nand.c return PTR_ERR(base); base 1015 drivers/mtd/nand/raw/fsmc_nand.c host->regs_va = base + FSMC_NOR_REG_SIZE + base 1033 drivers/mtd/nand/raw/fsmc_nand.c pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) & base 1091 drivers/mtd/nand/raw/fsmc_nand.c nand_controller_init(&host->base); base 1092 drivers/mtd/nand/raw/fsmc_nand.c host->base.ops = &fsmc_nand_controller_ops; base 1093 drivers/mtd/nand/raw/fsmc_nand.c nand->controller = &host->base; base 275 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c chip->base.eccreq.strength, base 276 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c chip->base.eccreq.step_size); base 520 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c if (!(chip->base.eccreq.strength > 0 && base 521 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c chip->base.eccreq.step_size > 0)) base 525 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c chip->base.eccreq.strength, base 526 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c chip->base.eccreq.step_size); base 2092 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c block_count = nanddev_eraseblocks_per_target(&chip->base); base 2585 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c nand_controller_init(&this->base); base 2586 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c this->base.ops = &gpmi_nand_controller_ops; base 2587 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c chip->controller = &this->base; base 137 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h struct nand_controller base; base 843 drivers/mtd/nand/raw/hisi504_nand.c for (cs = 0; cs < nanddev_ntargets(&chip->base); cs++) base 138 drivers/mtd/nand/raw/ingenic/ingenic_ecc.c ecc->base = devm_ioremap_resource(dev, res); base 139 drivers/mtd/nand/raw/ingenic/ingenic_ecc.c if (IS_ERR(ecc->base)) base 140 drivers/mtd/nand/raw/ingenic/ingenic_ecc.c return PTR_ERR(ecc->base); base 76 drivers/mtd/nand/raw/ingenic/ingenic_ecc.h void __iomem *base; base 42 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c void __iomem *base; base 178 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c writeb(cmd, cs->base + nfc->soc_info->addr_offset); base 180 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c writeb(cmd, cs->base + nfc->soc_info->cmd_offset); base 328 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c cs->base = devm_platform_ioremap_resource(pdev, chipnr); base 329 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c if (IS_ERR(cs->base)) base 330 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c return PTR_ERR(cs->base); base 362 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c chip->legacy.IO_ADDR_R = cs->base + nfc->soc_info->data_offset; base 363 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c chip->legacy.IO_ADDR_W = cs->base + nfc->soc_info->data_offset; base 64 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c writel(cfg, bch->base + BCH_BHCSR); base 69 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c writel(cfg, bch->base + BCH_BHCCR); base 78 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); base 107 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c writel(reg, bch->base + BCH_BHCNT); base 115 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); base 125 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c writeb(*buf++, bch->base + BCH_BHDR); base 139 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c *dest32++ = readl_relaxed(bch->base + BCH_BHPAR0 + offset); base 144 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c val = readl_relaxed(bch->base + BCH_BHPAR0 + offset); base 170 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c ret = readl_relaxed_poll_timeout(bch->base + BCH_BHINT, reg, base 178 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c writel(reg, bch->base + BCH_BHINT); base 258 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c reg = readl(bch->base + BCH_BHERR0 + (i * 4)); base 50 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); base 53 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); base 62 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); base 76 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c status = readl(ecc->base + JZ_REG_NAND_IRQ_STAT); base 82 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); base 84 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); base 87 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c ecc_code[i] = readb(ecc->base + JZ_REG_NAND_PAR0 + i); base 128 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writeb(ecc_code[i], ecc->base + JZ_REG_NAND_PAR0 + i); base 130 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); base 132 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); base 135 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c status = readl(ecc->base + JZ_REG_NAND_IRQ_STAT); base 141 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); base 143 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); base 152 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c error = readl(ecc->base + JZ_REG_NAND_ERR(i)); base 168 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); base 169 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); base 171 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); base 68 drivers/mtd/nand/raw/ingenic/jz4780_bch.c writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); base 73 drivers/mtd/nand/raw/ingenic/jz4780_bch.c writel(reg, bch->base + BCH_BHCNT); base 80 drivers/mtd/nand/raw/ingenic/jz4780_bch.c writel(reg, bch->base + BCH_BHCR); base 85 drivers/mtd/nand/raw/ingenic/jz4780_bch.c writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); base 86 drivers/mtd/nand/raw/ingenic/jz4780_bch.c writel(BCH_BHCR_BCHE, bch->base + BCH_BHCCR); base 99 drivers/mtd/nand/raw/ingenic/jz4780_bch.c writel(*src32++, bch->base + BCH_BHDR); base 103 drivers/mtd/nand/raw/ingenic/jz4780_bch.c writeb(*src8++, bch->base + BCH_BHDR); base 117 drivers/mtd/nand/raw/ingenic/jz4780_bch.c *dest32++ = readl(bch->base + BCH_BHPAR0 + offset); base 122 drivers/mtd/nand/raw/ingenic/jz4780_bch.c val = readl(bch->base + BCH_BHPAR0 + offset); base 148 drivers/mtd/nand/raw/ingenic/jz4780_bch.c ret = readl_poll_timeout(bch->base + BCH_BHINT, reg, base 156 drivers/mtd/nand/raw/ingenic/jz4780_bch.c writel(reg, bch->base + BCH_BHINT); base 214 drivers/mtd/nand/raw/ingenic/jz4780_bch.c reg = readl(bch->base + BCH_BHERR0 + (i * 4)); base 114 drivers/mtd/nand/raw/internals.h if (WARN_ON(op->cs >= nanddev_ntargets(&chip->base))) base 2251 drivers/mtd/nand/raw/marvell_nand.c if (chip->base.eccreq.step_size && chip->base.eccreq.strength) { base 2252 drivers/mtd/nand/raw/marvell_nand.c ecc->size = chip->base.eccreq.step_size; base 2253 drivers/mtd/nand/raw/marvell_nand.c ecc->strength = chip->base.eccreq.strength; base 1237 drivers/mtd/nand/raw/mtk_nand.c nand->ecc.strength = nand->base.eccreq.strength; base 1238 drivers/mtd/nand/raw/mtk_nand.c nand->ecc.size = nand->base.eccreq.step_size; base 169 drivers/mtd/nand/raw/mxc_nand.c void __iomem *base; base 1826 drivers/mtd/nand/raw/mxc_nand.c host->base = devm_ioremap_resource(&pdev->dev, res); base 1827 drivers/mtd/nand/raw/mxc_nand.c if (IS_ERR(host->base)) base 1828 drivers/mtd/nand/raw/mxc_nand.c return PTR_ERR(host->base); base 1830 drivers/mtd/nand/raw/mxc_nand.c host->main_area0 = host->base; base 1833 drivers/mtd/nand/raw/mxc_nand.c host->regs = host->base + host->devtype_data->regs_offset; base 1834 drivers/mtd/nand/raw/mxc_nand.c host->spare0 = host->base + host->devtype_data->spare0_offset; base 1836 drivers/mtd/nand/raw/mxc_nand.c host->regs_axi = host->base + host->devtype_data->axi_offset; base 16 drivers/mtd/nand/raw/nand_amd.c memorg = nanddev_get_memorg(&chip->base); base 242 drivers/mtd/nand/raw/nand_base.c if (WARN_ON(cs > nanddev_ntargets(&chip->base))) base 4477 drivers/mtd/nand/raw/nand_base.c memorg = nanddev_get_memorg(&chip->base); base 4513 drivers/mtd/nand/raw/nand_base.c memorg = nanddev_get_memorg(&chip->base); base 4554 drivers/mtd/nand/raw/nand_base.c memorg = nanddev_get_memorg(&chip->base); base 4571 drivers/mtd/nand/raw/nand_base.c chip->base.eccreq.strength = NAND_ECC_STRENGTH(type); base 4572 drivers/mtd/nand/raw/nand_base.c chip->base.eccreq.step_size = NAND_ECC_STEP(type); base 4600 drivers/mtd/nand/raw/nand_base.c memorg = nanddev_get_memorg(&chip->base); base 4662 drivers/mtd/nand/raw/nand_base.c memorg = nanddev_get_memorg(&chip->base); base 4801 drivers/mtd/nand/raw/nand_base.c targetsize = nanddev_target_size(&chip->base); base 5005 drivers/mtd/nand/raw/nand_base.c memorg = nanddev_get_memorg(&chip->base); base 5071 drivers/mtd/nand/raw/nand_base.c mtd->size = i * nanddev_target_size(&chip->base); base 5252 drivers/mtd/nand/raw/nand_base.c int req_step = chip->base.eccreq.step_size; base 5253 drivers/mtd/nand/raw/nand_base.c int req_strength = chip->base.eccreq.strength; base 5446 drivers/mtd/nand/raw/nand_base.c if (ecc->size == 0 || chip->base.eccreq.step_size == 0) base 5455 drivers/mtd/nand/raw/nand_base.c ds_corr = (mtd->writesize * chip->base.eccreq.strength) / base 5456 drivers/mtd/nand/raw/nand_base.c chip->base.eccreq.step_size; base 5458 drivers/mtd/nand/raw/nand_base.c return corr >= ds_corr && ecc->strength >= chip->base.eccreq.strength; base 5464 drivers/mtd/nand/raw/nand_base.c base); base 5481 drivers/mtd/nand/raw/nand_base.c base); base 5489 drivers/mtd/nand/raw/nand_base.c base); base 5773 drivers/mtd/nand/raw/nand_base.c ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner); base 5813 drivers/mtd/nand/raw/nand_base.c for (i = 0; i < nanddev_ntargets(&chip->base); i++) { base 5832 drivers/mtd/nand/raw/nand_base.c nanddev_cleanup(&chip->base); base 5910 drivers/mtd/nand/raw/nand_base.c nanddev_cleanup(&chip->base); base 263 drivers/mtd/nand/raw/nand_bbt.c u64 targetsize = nanddev_target_size(&this->base); base 268 drivers/mtd/nand/raw/nand_bbt.c for (i = 0; i < nanddev_ntargets(&this->base); i++) { base 464 drivers/mtd/nand/raw/nand_bbt.c u64 targetsize = nanddev_target_size(&this->base); base 476 drivers/mtd/nand/raw/nand_bbt.c if (chip >= nanddev_ntargets(&this->base)) { base 478 drivers/mtd/nand/raw/nand_bbt.c chip + 1, nanddev_ntargets(&this->base)); base 526 drivers/mtd/nand/raw/nand_bbt.c u64 targetsize = nanddev_target_size(&this->base); base 545 drivers/mtd/nand/raw/nand_bbt.c chips = nanddev_ntargets(&this->base); base 624 drivers/mtd/nand/raw/nand_bbt.c u64 targetsize = nanddev_target_size(&this->base); base 638 drivers/mtd/nand/raw/nand_bbt.c numblocks *= nanddev_ntargets(&this->base); base 716 drivers/mtd/nand/raw/nand_bbt.c u64 targetsize = nanddev_target_size(&this->base); base 740 drivers/mtd/nand/raw/nand_bbt.c nrchips = nanddev_ntargets(&this->base); base 927 drivers/mtd/nand/raw/nand_bbt.c chips = nanddev_ntargets(&this->base); base 1099 drivers/mtd/nand/raw/nand_bbt.c u64 targetsize = nanddev_target_size(&this->base); base 1106 drivers/mtd/nand/raw/nand_bbt.c chips = nanddev_ntargets(&this->base); base 1160 drivers/mtd/nand/raw/nand_bbt.c u64 targetsize = nanddev_target_size(&this->base); base 17 drivers/mtd/nand/raw/nand_esmt.c chip->base.eccreq.step_size = 512; base 20 drivers/mtd/nand/raw/nand_esmt.c chip->base.eccreq.strength = 4; base 23 drivers/mtd/nand/raw/nand_esmt.c chip->base.eccreq.strength = 2; base 26 drivers/mtd/nand/raw/nand_esmt.c chip->base.eccreq.strength = 1; base 30 drivers/mtd/nand/raw/nand_esmt.c chip->base.eccreq.step_size = 0; base 415 drivers/mtd/nand/raw/nand_hynix.c memorg = nanddev_get_memorg(&chip->base); base 502 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.step_size = 1024; base 506 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.step_size = 0; base 507 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 0; base 510 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 4; base 513 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 24; base 516 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 32; base 519 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 40; base 522 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 50; base 525 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 60; base 546 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.step_size = 512; base 547 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 1 << ecc_level; base 550 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.step_size = 2048; base 552 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.step_size = 1024; base 553 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 24; base 566 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.step_size = 0; base 567 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 0; base 569 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.step_size = 512; base 570 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 1 << (ecc_level - 1); base 572 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.step_size = 1024; base 573 drivers/mtd/nand/raw/nand_hynix.c chip->base.eccreq.strength = 24 + base 586 drivers/mtd/nand/raw/nand_hynix.c if (nanddev_bits_per_cell(&chip->base) > 2) base 612 drivers/mtd/nand/raw/nand_hynix.c memorg = nanddev_get_memorg(&chip->base); base 32 drivers/mtd/nand/raw/nand_jedec.c memorg = nanddev_get_memorg(&chip->base); base 113 drivers/mtd/nand/raw/nand_jedec.c chip->base.eccreq.strength = ecc->ecc_bits; base 114 drivers/mtd/nand/raw/nand_jedec.c chip->base.eccreq.step_size = 1 << ecc->codeword_size; base 379 drivers/mtd/nand/raw/nand_micron.c if (nanddev_bits_per_cell(&chip->base) != 1) base 385 drivers/mtd/nand/raw/nand_micron.c if (chip->base.eccreq.strength != 4 && chip->base.eccreq.strength != 8) base 426 drivers/mtd/nand/raw/nand_micron.c if (chip->base.eccreq.strength != 4 && chip->base.eccreq.strength != 8) base 483 drivers/mtd/nand/raw/nand_micron.c if (chip->base.eccreq.strength == 4) { base 493 drivers/mtd/nand/raw/nand_micron.c if (chip->base.eccreq.strength == 4) base 500 drivers/mtd/nand/raw/nand_micron.c chip->ecc.bytes = chip->base.eccreq.strength * 2; base 502 drivers/mtd/nand/raw/nand_micron.c chip->ecc.strength = chip->base.eccreq.strength; base 97 drivers/mtd/nand/raw/nand_onfi.c chip->base.eccreq.strength = ecc->ecc_bits; base 98 drivers/mtd/nand/raw/nand_onfi.c chip->base.eccreq.step_size = 1 << ecc->codeword_size; base 150 drivers/mtd/nand/raw/nand_onfi.c memorg = nanddev_get_memorg(&chip->base); base 255 drivers/mtd/nand/raw/nand_onfi.c chip->base.eccreq.strength = p->ecc_bits; base 256 drivers/mtd/nand/raw/nand_onfi.c chip->base.eccreq.step_size = 512; base 16 drivers/mtd/nand/raw/nand_samsung.c memorg = nanddev_get_memorg(&chip->base); base 74 drivers/mtd/nand/raw/nand_samsung.c chip->base.eccreq.step_size = 512; base 75 drivers/mtd/nand/raw/nand_samsung.c chip->base.eccreq.strength = 1 << extid; base 77 drivers/mtd/nand/raw/nand_samsung.c chip->base.eccreq.step_size = 1024; base 80 drivers/mtd/nand/raw/nand_samsung.c chip->base.eccreq.strength = 24; base 83 drivers/mtd/nand/raw/nand_samsung.c chip->base.eccreq.strength = 40; base 86 drivers/mtd/nand/raw/nand_samsung.c chip->base.eccreq.strength = 60; base 90 drivers/mtd/nand/raw/nand_samsung.c chip->base.eccreq.step_size = 0; base 100 drivers/mtd/nand/raw/nand_samsung.c chip->base.eccreq.step_size = 512; base 101 drivers/mtd/nand/raw/nand_samsung.c chip->base.eccreq.strength = 1; base 97 drivers/mtd/nand/raw/nand_toshiba.c memorg = nanddev_get_memorg(&chip->base); base 124 drivers/mtd/nand/raw/nand_toshiba.c chip->base.eccreq.step_size = 512; base 127 drivers/mtd/nand/raw/nand_toshiba.c chip->base.eccreq.strength = 1; base 130 drivers/mtd/nand/raw/nand_toshiba.c chip->base.eccreq.strength = 4; base 133 drivers/mtd/nand/raw/nand_toshiba.c chip->base.eccreq.strength = 8; base 137 drivers/mtd/nand/raw/nand_toshiba.c chip->base.eccreq.step_size = 0; base 289 drivers/mtd/nand/raw/nandsim.c struct nand_controller base; base 2297 drivers/mtd/nand/raw/nandsim.c nand_controller_init(&ns->base); base 2298 drivers/mtd/nand/raw/nandsim.c ns->base.ops = &ns_controller_ops; base 2299 drivers/mtd/nand/raw/nandsim.c chip->controller = &ns->base; base 2312 drivers/mtd/nand/raw/nandsim.c memorg = nanddev_get_memorg(&chip->base); base 2323 drivers/mtd/nand/raw/nandsim.c targetsize = nanddev_target_size(&chip->base); base 31 drivers/mtd/nand/raw/oxnas_nand.c struct nand_controller base; base 92 drivers/mtd/nand/raw/oxnas_nand.c nand_controller_init(&oxnas->base); base 122 drivers/mtd/nand/raw/oxnas_nand.c chip->controller = &oxnas->base; base 365 drivers/mtd/nand/raw/qcom_nandc.c void __iomem *base; base 574 drivers/mtd/nand/raw/qcom_nandc.c return ioread32(nandc->base + offset); base 580 drivers/mtd/nand/raw/qcom_nandc.c iowrite32(val, nandc->base + offset); base 2934 drivers/mtd/nand/raw/qcom_nandc.c nandc->base = devm_ioremap_resource(dev, res); base 2935 drivers/mtd/nand/raw/qcom_nandc.c if (IS_ERR(nandc->base)) base 2936 drivers/mtd/nand/raw/qcom_nandc.c return PTR_ERR(nandc->base); base 987 drivers/mtd/nand/raw/sh_flctl.c u64 targetsize = nanddev_target_size(&chip->base); base 251 drivers/mtd/nand/raw/stm32_fmc2_nand.c struct nand_controller base; base 279 drivers/mtd/nand/raw/stm32_fmc2_nand.c static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base) base 281 drivers/mtd/nand/raw/stm32_fmc2_nand.c return container_of(base, struct stm32_fmc2_nfc, base); base 1877 drivers/mtd/nand/raw/stm32_fmc2_nand.c nand_controller_init(&fmc2->base); base 1878 drivers/mtd/nand/raw/stm32_fmc2_nand.c fmc2->base.ops = &stm32_fmc2_nand_controller_ops; base 1961 drivers/mtd/nand/raw/stm32_fmc2_nand.c chip->controller = &fmc2->base; base 1748 drivers/mtd/nand/raw/sunxi_nand.c ecc->size = nand->base.eccreq.step_size; base 1749 drivers/mtd/nand/raw/sunxi_nand.c ecc->strength = nand->base.eccreq.strength; base 96 drivers/mtd/nand/raw/tango_nand.c void __iomem *base; base 121 drivers/mtd/nand/raw/tango_nand.c writeb_relaxed(dat, tchip->base + PBUS_CMD); base 124 drivers/mtd/nand/raw/tango_nand.c writeb_relaxed(dat, tchip->base + PBUS_ADDR); base 138 drivers/mtd/nand/raw/tango_nand.c return readb_relaxed(tchip->base + PBUS_DATA); base 145 drivers/mtd/nand/raw/tango_nand.c ioread8_rep(tchip->base + PBUS_DATA, buf, len); base 152 drivers/mtd/nand/raw/tango_nand.c iowrite8_rep(tchip->base + PBUS_DATA, buf, len); base 575 drivers/mtd/nand/raw/tango_nand.c tchip->base = nfc->pbus_base + (cs * 256); base 856 drivers/mtd/nand/raw/tegra_nand.c if (strength_sel < chip->base.eccreq.strength) base 920 drivers/mtd/nand/raw/tegra_nand.c if (chip->base.eccreq.step_size != 512) { base 922 drivers/mtd/nand/raw/tegra_nand.c chip->base.eccreq.step_size); base 953 drivers/mtd/nand/raw/tegra_nand.c chip->base.eccreq.strength); base 70 drivers/mtd/nand/raw/txx9ndfmc.c void __iomem *base; base 88 drivers/mtd/nand/raw/txx9ndfmc.c return drvdata->base + (reg << plat->shift); base 284 drivers/mtd/nand/raw/txx9ndfmc.c drvdata->base = devm_ioremap_resource(&dev->dev, res); base 285 drivers/mtd/nand/raw/txx9ndfmc.c if (IS_ERR(drvdata->base)) base 286 drivers/mtd/nand/raw/txx9ndfmc.c return PTR_ERR(drvdata->base); base 151 drivers/mtd/nand/raw/vf610_nfc.c struct nand_controller base; base 891 drivers/mtd/nand/raw/vf610_nfc.c nand_controller_init(&nfc->base); base 892 drivers/mtd/nand/raw/vf610_nfc.c nfc->base.ops = &vf610_nfc_controller_ops; base 893 drivers/mtd/nand/raw/vf610_nfc.c chip->controller = &nfc->base; base 144 drivers/mtd/spi-nor/intel-spi.c void __iomem *base; base 167 drivers/mtd/spi-nor/intel-spi.c dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG)); base 169 drivers/mtd/spi-nor/intel-spi.c value = readl(ispi->base + HSFSTS_CTL); base 174 drivers/mtd/spi-nor/intel-spi.c dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR)); base 175 drivers/mtd/spi-nor/intel-spi.c dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK)); base 179 drivers/mtd/spi-nor/intel-spi.c i, readl(ispi->base + FDATA(i))); base 181 drivers/mtd/spi-nor/intel-spi.c dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC)); base 185 drivers/mtd/spi-nor/intel-spi.c readl(ispi->base + FREG(i))); base 198 drivers/mtd/spi-nor/intel-spi.c dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR)); base 200 drivers/mtd/spi-nor/intel-spi.c dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC)); base 201 drivers/mtd/spi-nor/intel-spi.c dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC)); base 205 drivers/mtd/spi-nor/intel-spi.c u32 base, limit; base 212 drivers/mtd/spi-nor/intel-spi.c base = value & PR_BASE_MASK; base 215 drivers/mtd/spi-nor/intel-spi.c i, base << 12, (limit << 12) | 0xfff, base 222 drivers/mtd/spi-nor/intel-spi.c u32 region, base, limit; base 224 drivers/mtd/spi-nor/intel-spi.c region = readl(ispi->base + FREG(i)); base 225 drivers/mtd/spi-nor/intel-spi.c base = region & FREG_BASE_MASK; base 228 drivers/mtd/spi-nor/intel-spi.c if (base >= limit || (i > 0 && limit == 0)) base 232 drivers/mtd/spi-nor/intel-spi.c i, base << 12, (limit << 12) | 0xfff); base 252 drivers/mtd/spi-nor/intel-spi.c memcpy_fromio(buf, ispi->base + FDATA(i), bytes); base 273 drivers/mtd/spi-nor/intel-spi.c memcpy_toio(ispi->base + FDATA(i), buf, bytes); base 286 drivers/mtd/spi-nor/intel-spi.c return readl_poll_timeout(ispi->base + HSFSTS_CTL, val, base 307 drivers/mtd/spi-nor/intel-spi.c ispi->sregs = ispi->base + BYT_SSFSTS_CTL; base 308 drivers/mtd/spi-nor/intel-spi.c ispi->pregs = ispi->base + BYT_PR; base 315 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + BYT_BCR); base 318 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + BYT_BCR); base 319 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + BYT_BCR); base 328 drivers/mtd/spi-nor/intel-spi.c ispi->sregs = ispi->base + LPT_SSFSTS_CTL; base 329 drivers/mtd/spi-nor/intel-spi.c ispi->pregs = ispi->base + LPT_PR; base 336 drivers/mtd/spi-nor/intel-spi.c ispi->sregs = ispi->base + BXT_SSFSTS_CTL; base 337 drivers/mtd/spi-nor/intel-spi.c ispi->pregs = ispi->base + BXT_PR; base 348 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); base 350 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + HSFSTS_CTL); base 360 drivers/mtd/spi-nor/intel-spi.c lvscc = readl(ispi->base + LVSCC); base 361 drivers/mtd/spi-nor/intel-spi.c uvscc = readl(ispi->base + UVSCC); base 383 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); base 434 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); base 457 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + HSFSTS_CTL); base 463 drivers/mtd/spi-nor/intel-spi.c status = readl(ispi->base + HSFSTS_CTL); base 544 drivers/mtd/spi-nor/intel-spi.c writel(0, ispi->base + FADDR); base 593 drivers/mtd/spi-nor/intel-spi.c writel(0, ispi->base + FADDR); base 638 drivers/mtd/spi-nor/intel-spi.c writel(from, ispi->base + FADDR); base 640 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); base 646 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + HSFSTS_CTL); base 652 drivers/mtd/spi-nor/intel-spi.c status = readl(ispi->base + HSFSTS_CTL); base 695 drivers/mtd/spi-nor/intel-spi.c writel(to, ispi->base + FADDR); base 697 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); base 711 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + HSFSTS_CTL); base 719 drivers/mtd/spi-nor/intel-spi.c status = readl(ispi->base + HSFSTS_CTL); base 758 drivers/mtd/spi-nor/intel-spi.c writel(offs, ispi->base + FADDR); base 776 drivers/mtd/spi-nor/intel-spi.c writel(offs, ispi->base + FADDR); base 778 drivers/mtd/spi-nor/intel-spi.c val = readl(ispi->base + HSFSTS_CTL); base 783 drivers/mtd/spi-nor/intel-spi.c writel(val, ispi->base + HSFSTS_CTL); base 789 drivers/mtd/spi-nor/intel-spi.c status = readl(ispi->base + HSFSTS_CTL); base 803 drivers/mtd/spi-nor/intel-spi.c unsigned int base, unsigned int limit) base 817 drivers/mtd/spi-nor/intel-spi.c if (pr_base >= base && pr_limit <= limit) base 845 drivers/mtd/spi-nor/intel-spi.c u32 region, base, limit; base 847 drivers/mtd/spi-nor/intel-spi.c region = readl(ispi->base + FREG(i)); base 848 drivers/mtd/spi-nor/intel-spi.c base = region & FREG_BASE_MASK; base 851 drivers/mtd/spi-nor/intel-spi.c if (base >= limit || limit == 0) base 858 drivers/mtd/spi-nor/intel-spi.c if (intel_spi_is_protected(ispi, base, limit)) base 886 drivers/mtd/spi-nor/intel-spi.c ispi->base = devm_ioremap_resource(dev, mem); base 887 drivers/mtd/spi-nor/intel-spi.c if (IS_ERR(ispi->base)) base 888 drivers/mtd/spi-nor/intel-spi.c return ERR_CAST(ispi->base); base 108 drivers/mtd/spi-nor/mtk-quadspi.c void __iomem *base; /* nor flash base address */ base 119 drivers/mtd/spi-nor/mtk-quadspi.c writeb(nor->read_opcode, mtk_nor->base + base 121 drivers/mtd/spi-nor/mtk-quadspi.c writeb(MTK_NOR_FAST_READ, mtk_nor->base + base 125 drivers/mtd/spi-nor/mtk-quadspi.c writeb(nor->read_opcode, mtk_nor->base + base 127 drivers/mtd/spi-nor/mtk-quadspi.c writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base + base 131 drivers/mtd/spi-nor/mtk-quadspi.c writeb(nor->read_opcode, mtk_nor->base + base 133 drivers/mtd/spi-nor/mtk-quadspi.c writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base + base 137 drivers/mtd/spi-nor/mtk-quadspi.c writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base + base 148 drivers/mtd/spi-nor/mtk-quadspi.c writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG); base 149 drivers/mtd/spi-nor/mtk-quadspi.c return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg, base 162 drivers/mtd/spi-nor/mtk-quadspi.c writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG); base 168 drivers/mtd/spi-nor/mtk-quadspi.c writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx)); base 173 drivers/mtd/spi-nor/mtk-quadspi.c writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx)); base 177 drivers/mtd/spi-nor/mtk-quadspi.c writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx)); base 190 drivers/mtd/spi-nor/mtk-quadspi.c rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx)); base 198 drivers/mtd/spi-nor/mtk-quadspi.c writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG); base 199 drivers/mtd/spi-nor/mtk-quadspi.c writeb(8, mtk_nor->base + MTK_NOR_CNT_REG); base 211 drivers/mtd/spi-nor/mtk-quadspi.c writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG); base 212 drivers/mtd/spi-nor/mtk-quadspi.c return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg, base 220 drivers/mtd/spi-nor/mtk-quadspi.c writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG); base 221 drivers/mtd/spi-nor/mtk-quadspi.c return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg, base 231 drivers/mtd/spi-nor/mtk-quadspi.c val = readb(mtk_nor->base + MTK_NOR_DUAL_REG); base 246 drivers/mtd/spi-nor/mtk-quadspi.c writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG); base 256 drivers/mtd/spi-nor/mtk-quadspi.c writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4); base 260 drivers/mtd/spi-nor/mtk-quadspi.c writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG); base 279 drivers/mtd/spi-nor/mtk-quadspi.c buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG); base 292 drivers/mtd/spi-nor/mtk-quadspi.c writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG); base 312 drivers/mtd/spi-nor/mtk-quadspi.c writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG); base 368 drivers/mtd/spi-nor/mtk-quadspi.c *buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG); base 435 drivers/mtd/spi-nor/mtk-quadspi.c writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG); base 474 drivers/mtd/spi-nor/mtk-quadspi.c mtk_nor->base = devm_ioremap_resource(&pdev->dev, res); base 475 drivers/mtd/spi-nor/mtk-quadspi.c if (IS_ERR(mtk_nor->base)) base 476 drivers/mtd/spi-nor/mtk-quadspi.c return PTR_ERR(mtk_nor->base); base 372 drivers/net/appletalk/ltpc.c int base = dev->base_addr; base 385 drivers/net/appletalk/ltpc.c inb_p(base+3); base 386 drivers/net/appletalk/ltpc.c inb_p(base+2); base 395 drivers/net/appletalk/ltpc.c int base = dev->base_addr; base 407 drivers/net/appletalk/ltpc.c inb_p(base+3); base 408 drivers/net/appletalk/ltpc.c inb_p(base+2); base 419 drivers/net/appletalk/ltpc.c int base = dev->base_addr; base 431 drivers/net/appletalk/ltpc.c inb_p(base+3); base 432 drivers/net/appletalk/ltpc.c inb_p(base+2); base 447 drivers/net/appletalk/ltpc.c int base = dev->base_addr; base 460 drivers/net/appletalk/ltpc.c inb_p(base+3); base 461 drivers/net/appletalk/ltpc.c inb_p(base+2); base 469 drivers/net/appletalk/ltpc.c int base = dev->base_addr; base 480 drivers/net/appletalk/ltpc.c inb_p(base+3); base 481 drivers/net/appletalk/ltpc.c inb_p(base+2); base 505 drivers/net/appletalk/ltpc.c int base = dev->base_addr; base 516 drivers/net/appletalk/ltpc.c (void) inb_p(base+6); base 526 drivers/net/appletalk/ltpc.c state = inb_p(base+6); base 527 drivers/net/appletalk/ltpc.c if (state != inb_p(base+6)) goto loop; base 586 drivers/net/appletalk/ltpc.c if(0xfa==inb_p(base+6)) { base 640 drivers/net/appletalk/ltpc.c inb_p(base+7); base 641 drivers/net/appletalk/ltpc.c inb_p(base+7); base 933 drivers/net/appletalk/ltpc.c static int __init ltpc_probe_dma(int base, int dma) base 208 drivers/net/arcnet/com90xx.c void __iomem *base; base 225 drivers/net/arcnet/com90xx.c base = ioremap(*p, MIRROR_SIZE); base 226 drivers/net/arcnet/com90xx.c if (!base) { base 233 drivers/net/arcnet/com90xx.c if (arcnet_readb(base, COM9026_REG_R_STATUS) != TESTvalue) { base 235 drivers/net/arcnet/com90xx.c arcnet_readb(base, COM9026_REG_R_STATUS), base 247 drivers/net/arcnet/com90xx.c arcnet_writeb(0x42, base, COM9026_REG_W_INTMASK); base 248 drivers/net/arcnet/com90xx.c if (arcnet_readb(base, COM9026_REG_R_STATUS) != 0x42) { base 257 drivers/net/arcnet/com90xx.c iomem[index] = base; base 260 drivers/net/arcnet/com90xx.c iounmap(base); base 389 drivers/net/arcnet/com90xx.c void __iomem *base = iomem[index]; base 391 drivers/net/arcnet/com90xx.c if (arcnet_readb(base, COM9026_REG_R_STATUS) == TESTvalue) { /* found one */ base 396 drivers/net/arcnet/com90xx.c if (com90xx_found(*port, airq, ptr, base) == 0) base 406 drivers/net/arcnet/com90xx.c arcnet_readb(base, COM9026_REG_R_STATUS)); base 383 drivers/net/bonding/bond_main.c if (ecmd.base.speed == 0 || ecmd.base.speed == ((__u32)-1)) base 385 drivers/net/bonding/bond_main.c switch (ecmd.base.duplex) { base 393 drivers/net/bonding/bond_main.c slave->speed = ecmd.base.speed; base 394 drivers/net/bonding/bond_main.c slave->duplex = ecmd.base.duplex; base 4257 drivers/net/bonding/bond_main.c cmd->base.duplex = DUPLEX_UNKNOWN; base 4258 drivers/net/bonding/bond_main.c cmd->base.port = PORT_OTHER; base 4269 drivers/net/bonding/bond_main.c if (cmd->base.duplex == DUPLEX_UNKNOWN && base 4271 drivers/net/bonding/bond_main.c cmd->base.duplex = slave->duplex; base 4274 drivers/net/bonding/bond_main.c cmd->base.speed = speed ? : SPEED_UNKNOWN; base 208 drivers/net/can/c_can/c_can.h void __iomem *base; base 53 drivers/net/can/c_can/c_can_pci.c return readw(priv->base + priv->regs[index]); base 59 drivers/net/can/c_can/c_can_pci.c writew(val, priv->base + priv->regs[index]); base 65 drivers/net/can/c_can/c_can_pci.c return readw(priv->base + 2 * priv->regs[index]); base 71 drivers/net/can/c_can/c_can_pci.c writew(val, priv->base + 2 * priv->regs[index]); base 77 drivers/net/can/c_can/c_can_pci.c return (u16)ioread32(priv->base + 2 * priv->regs[index]); base 83 drivers/net/can/c_can/c_can_pci.c iowrite32((u32)val, priv->base + 2 * priv->regs[index]); base 106 drivers/net/can/c_can/c_can_pci.c u32 __iomem *addr = priv->base + PCH_PCI_SOFT_RESET; base 163 drivers/net/can/c_can/c_can_pci.c priv->base = addr; base 247 drivers/net/can/c_can/c_can_pci.c pci_iounmap(pdev, priv->base); base 53 drivers/net/can/c_can/c_can_platform.c return readw(priv->base + priv->regs[index]); base 59 drivers/net/can/c_can/c_can_platform.c writew(val, priv->base + priv->regs[index]); base 65 drivers/net/can/c_can/c_can_platform.c return readw(priv->base + 2 * priv->regs[index]); base 71 drivers/net/can/c_can/c_can_platform.c writew(val, priv->base + 2 * priv->regs[index]); base 161 drivers/net/can/c_can/c_can_platform.c return readl(priv->base + priv->regs[index]); base 167 drivers/net/can/c_can/c_can_platform.c writel(val, priv->base + priv->regs[index]); base 379 drivers/net/can/c_can/c_can_platform.c priv->base = addr; base 396 drivers/net/can/c_can/c_can_platform.c KBUILD_MODNAME, priv->base, dev->irq); base 137 drivers/net/can/cc770/cc770_isa.c unsigned long base = (unsigned long)priv->reg_base; base 142 drivers/net/can/cc770/cc770_isa.c outb(reg, base); base 143 drivers/net/can/cc770/cc770_isa.c val = inb(base + 1); base 152 drivers/net/can/cc770/cc770_isa.c unsigned long base = (unsigned long)priv->reg_base; base 156 drivers/net/can/cc770/cc770_isa.c outb(reg, base); base 157 drivers/net/can/cc770/cc770_isa.c outb(val, base + 1); base 165 drivers/net/can/cc770/cc770_isa.c void __iomem *base = NULL; base 178 drivers/net/can/cc770/cc770_isa.c base = ioremap_nocache(mem[idx], iosize); base 179 drivers/net/can/cc770/cc770_isa.c if (!base) { base 203 drivers/net/can/cc770/cc770_isa.c priv->reg_base = base; base 276 drivers/net/can/cc770/cc770_isa.c iounmap(base); base 165 drivers/net/can/cc770/cc770_platform.c void __iomem *base; base 177 drivers/net/can/cc770/cc770_platform.c base = ioremap(mem->start, mem_size); base 178 drivers/net/can/cc770/cc770_platform.c if (!base) { base 194 drivers/net/can/cc770/cc770_platform.c priv->reg_base = base; base 226 drivers/net/can/cc770/cc770_platform.c iounmap(base); base 1582 drivers/net/can/grcan.c void __iomem *base, base 1603 drivers/net/can/grcan.c priv->regs = base; base 1658 drivers/net/can/grcan.c void __iomem *base; base 1676 drivers/net/can/grcan.c base = devm_ioremap_resource(&ofdev->dev, res); base 1677 drivers/net/can/grcan.c if (IS_ERR(base)) { base 1678 drivers/net/can/grcan.c err = PTR_ERR(base); base 1691 drivers/net/can/grcan.c err = grcan_setup_netdev(ofdev, base, irq, ambafreq, txbug); base 223 drivers/net/can/ifi_canfd/ifi_canfd.c void __iomem *base; base 245 drivers/net/can/ifi_canfd/ifi_canfd.c priv->base + IFI_CANFD_IRQMASK); base 260 drivers/net/can/ifi_canfd/ifi_canfd.c rxdlc = readl(priv->base + IFI_CANFD_RXFIFO_DLC); base 278 drivers/net/can/ifi_canfd/ifi_canfd.c rxid = readl(priv->base + IFI_CANFD_RXFIFO_ID); base 310 drivers/net/can/ifi_canfd/ifi_canfd.c readl(priv->base + IFI_CANFD_RXFIFO_DATA + i); base 315 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_RXSTCMD_REMOVE_MSG, priv->base + IFI_CANFD_RXSTCMD); base 316 drivers/net/can/ifi_canfd/ifi_canfd.c writel(rx_irq_mask, priv->base + IFI_CANFD_INTERRUPT); base 330 drivers/net/can/ifi_canfd/ifi_canfd.c rxst = readl(priv->base + IFI_CANFD_RXSTCMD); base 345 drivers/net/can/ifi_canfd/ifi_canfd.c rxst = readl(priv->base + IFI_CANFD_RXSTCMD); base 383 drivers/net/can/ifi_canfd/ifi_canfd.c u32 errctr = readl(priv->base + IFI_CANFD_ERROR_CTR); base 428 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_ERROR_CTR_ER_RESET, priv->base + IFI_CANFD_ERROR_CTR); base 430 drivers/net/can/ifi_canfd/ifi_canfd.c priv->base + IFI_CANFD_INTERRUPT); base 431 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_ERROR_CTR_ER_ENABLE, priv->base + IFI_CANFD_ERROR_CTR); base 446 drivers/net/can/ifi_canfd/ifi_canfd.c err = readl(priv->base + IFI_CANFD_ERROR); base 535 drivers/net/can/ifi_canfd/ifi_canfd.c u32 stcmd = readl(priv->base + IFI_CANFD_STCMD); base 573 drivers/net/can/ifi_canfd/ifi_canfd.c u32 rxstcmd = readl(priv->base + IFI_CANFD_RXSTCMD); base 615 drivers/net/can/ifi_canfd/ifi_canfd.c isr = readl(priv->base + IFI_CANFD_INTERRUPT); base 622 drivers/net/can/ifi_canfd/ifi_canfd.c writel(clr_irq_mask, priv->base + IFI_CANFD_INTERRUPT); base 671 drivers/net/can/ifi_canfd/ifi_canfd.c priv->base + IFI_CANFD_TIME); base 682 drivers/net/can/ifi_canfd/ifi_canfd.c priv->base + IFI_CANFD_FTIME); base 687 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_TDELAY_EN | tdc, priv->base + IFI_CANFD_TDELAY); base 695 drivers/net/can/ifi_canfd/ifi_canfd.c writel(mask, priv->base + IFI_CANFD_FILTER_MASK(id)); base 696 drivers/net/can/ifi_canfd/ifi_canfd.c writel(ident, priv->base + IFI_CANFD_FILTER_IDENT(id)); base 730 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_STCMD_HARDRESET, priv->base + IFI_CANFD_STCMD); base 732 drivers/net/can/ifi_canfd/ifi_canfd.c priv->base + IFI_CANFD_STCMD); base 738 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_RXSTCMD_RESET, priv->base + IFI_CANFD_RXSTCMD); base 739 drivers/net/can/ifi_canfd/ifi_canfd.c writel(0, priv->base + IFI_CANFD_RXSTCMD); base 740 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_TXSTCMD_RESET, priv->base + IFI_CANFD_TXSTCMD); base 741 drivers/net/can/ifi_canfd/ifi_canfd.c writel(0, priv->base + IFI_CANFD_TXSTCMD); base 744 drivers/net/can/ifi_canfd/ifi_canfd.c writel(0, priv->base + IFI_CANFD_REPEAT); base 745 drivers/net/can/ifi_canfd/ifi_canfd.c writel(0, priv->base + IFI_CANFD_SUSPEND); base 749 drivers/net/can/ifi_canfd/ifi_canfd.c priv->base + IFI_CANFD_INTERRUPT); base 773 drivers/net/can/ifi_canfd/ifi_canfd.c priv->base + IFI_CANFD_ERROR_CTR); base 774 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_ERROR_CTR_ER_RESET, priv->base + IFI_CANFD_ERROR_CTR); base 775 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_ERROR_CTR_ER_ENABLE, priv->base + IFI_CANFD_ERROR_CTR); base 778 drivers/net/can/ifi_canfd/ifi_canfd.c writel(stcmd, priv->base + IFI_CANFD_STCMD); base 786 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_ERROR_CTR_ER_RESET, priv->base + IFI_CANFD_ERROR_CTR); base 787 drivers/net/can/ifi_canfd/ifi_canfd.c writel(0, priv->base + IFI_CANFD_ERROR_CTR); base 790 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_STCMD_HARDRESET, priv->base + IFI_CANFD_STCMD); base 793 drivers/net/can/ifi_canfd/ifi_canfd.c writel(~0, priv->base + IFI_CANFD_IRQMASK); base 797 drivers/net/can/ifi_canfd/ifi_canfd.c priv->base + IFI_CANFD_INTERRUPT); base 878 drivers/net/can/ifi_canfd/ifi_canfd.c txst = readl(priv->base + IFI_CANFD_TXSTCMD); base 914 drivers/net/can/ifi_canfd/ifi_canfd.c writel(txid, priv->base + IFI_CANFD_TXFIFO_ID); base 915 drivers/net/can/ifi_canfd/ifi_canfd.c writel(txdlc, priv->base + IFI_CANFD_TXFIFO_DLC); base 919 drivers/net/can/ifi_canfd/ifi_canfd.c priv->base + IFI_CANFD_TXFIFO_DATA + i); base 922 drivers/net/can/ifi_canfd/ifi_canfd.c writel(0, priv->base + IFI_CANFD_TXFIFO_REPEATCOUNT); base 923 drivers/net/can/ifi_canfd/ifi_canfd.c writel(0, priv->base + IFI_CANFD_TXFIFO_SUSPEND_US); base 928 drivers/net/can/ifi_canfd/ifi_canfd.c writel(IFI_CANFD_TXSTCMD_ADD_MSG, priv->base + IFI_CANFD_TXSTCMD); base 979 drivers/net/can/ifi_canfd/ifi_canfd.c priv->base = addr; base 1014 drivers/net/can/ifi_canfd/ifi_canfd.c priv->base, ndev->irq, priv->can.clock.freq); base 13 drivers/net/can/m_can/m_can_platform.c void __iomem *base; base 21 drivers/net/can/m_can/m_can_platform.c return readl(priv->base + reg); base 35 drivers/net/can/m_can/m_can_platform.c writel(val, priv->base + reg); base 98 drivers/net/can/m_can/m_can_platform.c priv->base = addr; base 287 drivers/net/can/mscan/mpc5xxx_can.c void __iomem *base; base 297 drivers/net/can/mscan/mpc5xxx_can.c base = of_iomap(np, 0); base 298 drivers/net/can/mscan/mpc5xxx_can.c if (!base) { base 317 drivers/net/can/mscan/mpc5xxx_can.c priv->reg_base = base; base 348 drivers/net/can/mscan/mpc5xxx_can.c iounmap(base); base 497 drivers/net/can/rcar/rcar_canfd.c void __iomem *base; /* Register base address */ base 509 drivers/net/can/rcar/rcar_canfd.c void __iomem *base; /* Register base address */ base 567 drivers/net/can/rcar/rcar_canfd.c static inline u32 rcar_canfd_read(void __iomem *base, u32 offset) base 569 drivers/net/can/rcar/rcar_canfd.c return readl(base + (offset)); base 572 drivers/net/can/rcar/rcar_canfd.c static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val) base 574 drivers/net/can/rcar/rcar_canfd.c writel(val, base + (offset)); base 577 drivers/net/can/rcar/rcar_canfd.c static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val) base 579 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update(val, val, base + (reg)); base 582 drivers/net/can/rcar/rcar_canfd.c static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val) base 584 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update(val, 0, base + (reg)); base 587 drivers/net/can/rcar/rcar_canfd.c static void rcar_canfd_update_bit(void __iomem *base, u32 reg, base 590 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update(mask, val, base + (reg)); base 601 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_read(priv->base, off + (i * sizeof(u32))); base 611 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, off + (i * sizeof(u32)), base 631 drivers/net/can/rcar/rcar_canfd.c err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts, base 639 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR); base 640 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, base 644 drivers/net/can/rcar/rcar_canfd.c err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts, base 652 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0); base 656 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG, base 659 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG, base 664 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_clear_bit(gpriv->base, base 667 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch), base 672 drivers/net/can/rcar/rcar_canfd.c err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts, base 701 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg); base 705 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch), base 707 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch), base 724 drivers/net/can/rcar/rcar_canfd.c cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG0); base 730 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR, base 735 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0, base 743 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0); base 745 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0); base 747 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0); base 749 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(gpriv->base, RCANFD_GAFLP1(offset, start), base 753 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_clear_bit(gpriv->base, base 774 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(gpriv->base, RCANFD_RFCC(ridx), cfg); base 799 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(gpriv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg); base 803 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(gpriv->base, base 812 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0); base 819 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr); base 826 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0); base 829 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0); base 838 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0); base 846 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr); base 859 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr); base 862 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0); base 874 drivers/net/can/rcar/rcar_canfd.c gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL); base 884 drivers/net/can/rcar/rcar_canfd.c sts = rcar_canfd_read(priv->base, base 889 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, base 894 drivers/net/can/rcar/rcar_canfd.c sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx)); base 898 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx), base 913 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, RCANFD_GERFL, 0); base 1025 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, RCANFD_CERFL(ch), base 1051 drivers/net/can/rcar/rcar_canfd.c sts = rcar_canfd_read(priv->base, base 1068 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX), base 1090 drivers/net/can/rcar/rcar_canfd.c gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL); base 1095 drivers/net/can/rcar/rcar_canfd.c sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx)); base 1099 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_clear_bit(priv->base, base 1156 drivers/net/can/rcar/rcar_canfd.c cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch)); base 1157 drivers/net/can/rcar/rcar_canfd.c sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch)); base 1169 drivers/net/can/rcar/rcar_canfd.c sts = rcar_canfd_read(priv->base, base 1197 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg); base 1210 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg); base 1218 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg); base 1237 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch), base 1241 drivers/net/can/rcar/rcar_canfd.c err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts, base 1249 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), base 1251 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE); base 1304 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch), base 1308 drivers/net/can/rcar/rcar_canfd.c err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts, base 1316 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), base 1318 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE); base 1363 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, base 1365 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, base 1378 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, base 1384 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, base 1386 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, base 1405 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, base 1422 drivers/net/can/rcar/rcar_canfd.c id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx)); base 1423 drivers/net/can/rcar/rcar_canfd.c dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx)); base 1425 drivers/net/can/rcar/rcar_canfd.c sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx)); base 1432 drivers/net/can/rcar/rcar_canfd.c id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx)); base 1433 drivers/net/can/rcar/rcar_canfd.c dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx)); base 1477 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, RCANFD_RFPCTR(ridx), 0xff); base 1496 drivers/net/can/rcar/rcar_canfd.c sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx)); base 1505 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx), base 1513 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx), base 1543 drivers/net/can/rcar/rcar_canfd.c val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch)); base 1575 drivers/net/can/rcar/rcar_canfd.c priv->base = gpriv->base; base 1713 drivers/net/can/rcar/rcar_canfd.c gpriv->base = addr; base 1766 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK, base 1770 drivers/net/can/rcar/rcar_canfd.c err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts, base 1813 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR); base 161 drivers/net/can/sja1000/ems_pcmcia.c static int ems_pcmcia_add_card(struct pcmcia_device *pdev, unsigned long base) base 176 drivers/net/can/sja1000/ems_pcmcia.c card->base_addr = ioremap(base, EMS_PCMCIA_MEM_SIZE); base 94 drivers/net/can/sja1000/sja1000_isa.c unsigned long flags, base = (unsigned long)priv->reg_base; base 98 drivers/net/can/sja1000/sja1000_isa.c outb(reg, base); base 99 drivers/net/can/sja1000/sja1000_isa.c readval = inb(base + 1); base 108 drivers/net/can/sja1000/sja1000_isa.c unsigned long flags, base = (unsigned long)priv->reg_base; base 111 drivers/net/can/sja1000/sja1000_isa.c outb(reg, base); base 112 drivers/net/can/sja1000/sja1000_isa.c outb(val, base + 1); base 120 drivers/net/can/sja1000/sja1000_isa.c void __iomem *base = NULL; base 133 drivers/net/can/sja1000/sja1000_isa.c base = ioremap_nocache(mem[idx], iosize); base 134 drivers/net/can/sja1000/sja1000_isa.c if (!base) { base 158 drivers/net/can/sja1000/sja1000_isa.c priv->reg_base = base; base 214 drivers/net/can/sja1000/sja1000_isa.c iounmap(base); base 205 drivers/net/can/sun4i_can.c void __iomem *base; base 227 drivers/net/can/sun4i_can.c writel(val, priv->base + SUN4I_REG_CMD_ADDR); base 238 drivers/net/can/sun4i_can.c mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); base 240 drivers/net/can/sun4i_can.c writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); base 243 drivers/net/can/sun4i_can.c if (readl(priv->base + SUN4I_REG_MSEL_ADDR) & SUN4I_MSEL_RESET_MODE) { base 259 drivers/net/can/sun4i_can.c mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); base 261 drivers/net/can/sun4i_can.c writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); base 264 drivers/net/can/sun4i_can.c if (!(readl(priv->base + SUN4I_REG_MSEL_ADDR) & base 288 drivers/net/can/sun4i_can.c writel(cfg, priv->base + SUN4I_REG_BTIME_ADDR); base 306 drivers/net/can/sun4i_can.c errors = readl(priv->base + SUN4I_REG_ERRC_ADDR); base 330 drivers/net/can/sun4i_can.c writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR); base 331 drivers/net/can/sun4i_can.c writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR); base 334 drivers/net/can/sun4i_can.c writel(0, priv->base + SUN4I_REG_ERRC_ADDR); base 338 drivers/net/can/sun4i_can.c writel(0xFF, priv->base + SUN4I_REG_INTEN_ADDR); base 341 drivers/net/can/sun4i_can.c priv->base + SUN4I_REG_INTEN_ADDR); base 344 drivers/net/can/sun4i_can.c mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); base 349 drivers/net/can/sun4i_can.c writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); base 381 drivers/net/can/sun4i_can.c writel(0, priv->base + SUN4I_REG_INTEN_ADDR); base 436 drivers/net/can/sun4i_can.c writel((id >> 21) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR); base 437 drivers/net/can/sun4i_can.c writel((id >> 13) & 0xFF, priv->base + SUN4I_REG_BUF2_ADDR); base 438 drivers/net/can/sun4i_can.c writel((id >> 5) & 0xFF, priv->base + SUN4I_REG_BUF3_ADDR); base 439 drivers/net/can/sun4i_can.c writel((id << 3) & 0xF8, priv->base + SUN4I_REG_BUF4_ADDR); base 442 drivers/net/can/sun4i_can.c writel((id >> 3) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR); base 443 drivers/net/can/sun4i_can.c writel((id << 5) & 0xE0, priv->base + SUN4I_REG_BUF2_ADDR); base 447 drivers/net/can/sun4i_can.c writel(cf->data[i], priv->base + (dreg + i * 4)); base 449 drivers/net/can/sun4i_can.c writel(msg_flag_n, priv->base + SUN4I_REG_BUF0_ADDR); base 477 drivers/net/can/sun4i_can.c fi = readl(priv->base + SUN4I_REG_BUF0_ADDR); base 481 drivers/net/can/sun4i_can.c id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 21) | base 482 drivers/net/can/sun4i_can.c (readl(priv->base + SUN4I_REG_BUF2_ADDR) << 13) | base 483 drivers/net/can/sun4i_can.c (readl(priv->base + SUN4I_REG_BUF3_ADDR) << 5) | base 484 drivers/net/can/sun4i_can.c ((readl(priv->base + SUN4I_REG_BUF4_ADDR) >> 3) & 0x1f); base 488 drivers/net/can/sun4i_can.c id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 3) | base 489 drivers/net/can/sun4i_can.c ((readl(priv->base + SUN4I_REG_BUF2_ADDR) >> 5) & 0x7); base 497 drivers/net/can/sun4i_can.c cf->data[i] = readl(priv->base + dreg + i * 4); base 524 drivers/net/can/sun4i_can.c errc = readl(priv->base + SUN4I_REG_ERRC_ADDR); base 570 drivers/net/can/sun4i_can.c ecc = readl(priv->base + SUN4I_REG_STA_ADDR); base 605 drivers/net/can/sun4i_can.c alc = readl(priv->base + SUN4I_REG_STA_ADDR); base 645 drivers/net/can/sun4i_can.c while ((isrc = readl(priv->base + SUN4I_REG_INT_ADDR)) && base 648 drivers/net/can/sun4i_can.c status = readl(priv->base + SUN4I_REG_STA_ADDR); base 656 drivers/net/can/sun4i_can.c readl(priv->base + base 669 drivers/net/can/sun4i_can.c status = readl(priv->base + SUN4I_REG_STA_ADDR); base 680 drivers/net/can/sun4i_can.c writel(isrc, priv->base + SUN4I_REG_INT_ADDR); base 681 drivers/net/can/sun4i_can.c readl(priv->base + SUN4I_REG_INT_ADDR); base 822 drivers/net/can/sun4i_can.c priv->base = addr; base 838 drivers/net/can/sun4i_can.c priv->base, dev->irq); base 192 drivers/net/can/ti_hecc.c void __iomem *base; base 240 drivers/net/can/ti_hecc.c __raw_writel(val, priv->base + reg); base 245 drivers/net/can/ti_hecc.c return __raw_readl(priv->base + reg); base 873 drivers/net/can/ti_hecc.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 874 drivers/net/can/ti_hecc.c if (IS_ERR(priv->base)) { base 876 drivers/net/can/ti_hecc.c return PTR_ERR(priv->base); base 960 drivers/net/can/ti_hecc.c priv->base, (u32)ndev->irq); base 2379 drivers/net/dsa/b53/b53_common.c struct b53_device *b53_switch_alloc(struct device *base, base 2386 drivers/net/dsa/b53/b53_common.c ds = dsa_switch_alloc(base, DSA_MAX_PORTS); base 2390 drivers/net/dsa/b53/b53_common.c dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); base 2395 drivers/net/dsa/b53/b53_common.c dev->dev = base; base 214 drivers/net/dsa/b53/b53_priv.h struct b53_device *b53_switch_alloc(struct device *base, base 1060 drivers/net/dsa/bcm_sf2.c void __iomem **base; base 1128 drivers/net/dsa/bcm_sf2.c base = &priv->core; base 1130 drivers/net/dsa/bcm_sf2.c *base = devm_platform_ioremap_resource(pdev, i); base 1131 drivers/net/dsa/bcm_sf2.c if (IS_ERR(*base)) { base 1133 drivers/net/dsa/bcm_sf2.c return PTR_ERR(*base); base 1135 drivers/net/dsa/bcm_sf2.c base++; base 1284 drivers/net/dsa/lan9303-core.c int base; base 1292 drivers/net/dsa/lan9303-core.c base = chip->phy_addr_base; base 1293 drivers/net/dsa/lan9303-core.c chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base); base 396 drivers/net/dsa/microchip/ksz_common.c struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) base 401 drivers/net/dsa/microchip/ksz_common.c ds = dsa_switch_alloc(base, DSA_MAX_PORTS); base 405 drivers/net/dsa/microchip/ksz_common.c swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); base 410 drivers/net/dsa/microchip/ksz_common.c swdev->dev = base; base 148 drivers/net/dsa/microchip/ksz_common.h struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); base 22 drivers/net/dsa/realtek-smi-core.h unsigned int base; base 69 drivers/net/dsa/sja1105/sja1105_main.c .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0}, base 319 drivers/net/dsa/sja1105/sja1105_static_config.c sja1105_packing(buf, &entry->base[i], base 353 drivers/net/dsa/sja1105/sja1105_static_config.c sja1105_packing(buf, &entry->base[i], base 239 drivers/net/dsa/sja1105/sja1105_static_config.h u64 base[8]; base 1115 drivers/net/dsa/vitesse-vsc73xx-core.c vsc->gc.base = -1; base 1054 drivers/net/ethernet/3com/3c509.c cmd->base.port = PORT_TP; base 1057 drivers/net/ethernet/3com/3c509.c cmd->base.port = PORT_AUI; base 1060 drivers/net/ethernet/3com/3c509.c cmd->base.port = PORT_BNC; base 1065 drivers/net/ethernet/3com/3c509.c cmd->base.duplex = DUPLEX_HALF; base 1078 drivers/net/ethernet/3com/3c509.c cmd->base.duplex = DUPLEX_FULL; base 1083 drivers/net/ethernet/3com/3c509.c cmd->base.speed = SPEED_10; base 1094 drivers/net/ethernet/3com/3c509.c if (cmd->base.speed != SPEED_10) base 1096 drivers/net/ethernet/3com/3c509.c if ((cmd->base.duplex != DUPLEX_HALF) && base 1097 drivers/net/ethernet/3com/3c509.c (cmd->base.duplex != DUPLEX_FULL)) base 1103 drivers/net/ethernet/3com/3c509.c switch (cmd->base.port) { base 1133 drivers/net/ethernet/3com/3c509.c if (cmd->base.duplex == DUPLEX_FULL) base 1254 drivers/net/ethernet/3com/3c59x.c int base; base 1257 drivers/net/ethernet/3com/3c59x.c base = 0x230; base 1259 drivers/net/ethernet/3com/3c59x.c base = EEPROM_Read + 0x30; base 1261 drivers/net/ethernet/3com/3c59x.c base = EEPROM_Read; base 1265 drivers/net/ethernet/3com/3c59x.c window_write16(vp, base + i, 0, Wn0EepromCmd); base 486 drivers/net/ethernet/3com/typhoon.c u8 *base = tp->respRing.ringBase; base 494 drivers/net/ethernet/3com/typhoon.c resp = (struct resp_desc *)(base + cleared); base 512 drivers/net/ethernet/3com/typhoon.c memcpy(resp_save, base, wrap_len); base 1032 drivers/net/ethernet/3com/typhoon.c cmd->base.port = PORT_FIBRE; base 1038 drivers/net/ethernet/3com/typhoon.c cmd->base.port = PORT_TP; base 1043 drivers/net/ethernet/3com/typhoon.c cmd->base.speed = tp->speed; base 1044 drivers/net/ethernet/3com/typhoon.c cmd->base.duplex = tp->duplex; base 1045 drivers/net/ethernet/3com/typhoon.c cmd->base.phy_address = 0; base 1047 drivers/net/ethernet/3com/typhoon.c cmd->base.autoneg = AUTONEG_ENABLE; base 1049 drivers/net/ethernet/3com/typhoon.c cmd->base.autoneg = AUTONEG_DISABLE; base 1064 drivers/net/ethernet/3com/typhoon.c u32 speed = cmd->base.speed; base 1070 drivers/net/ethernet/3com/typhoon.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 1073 drivers/net/ethernet/3com/typhoon.c if (cmd->base.duplex == DUPLEX_HALF) { base 1080 drivers/net/ethernet/3com/typhoon.c } else if (cmd->base.duplex == DUPLEX_FULL) { base 1098 drivers/net/ethernet/3com/typhoon.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 1103 drivers/net/ethernet/3com/typhoon.c tp->duplex = cmd->base.duplex; base 112 drivers/net/ethernet/8390/axnet_cs.c caddr_t base; base 569 drivers/net/ethernet/8390/etherh.c cmd->base.speed = SPEED_10; base 570 drivers/net/ethernet/8390/etherh.c cmd->base.duplex = DUPLEX_HALF; base 571 drivers/net/ethernet/8390/etherh.c cmd->base.port = dev->if_port == IF_PORT_10BASET ? PORT_TP : PORT_BNC; base 572 drivers/net/ethernet/8390/etherh.c cmd->base.autoneg = (dev->flags & IFF_AUTOMEDIA ? AUTONEG_ENABLE : base 580 drivers/net/ethernet/8390/etherh.c switch (cmd->base.autoneg) { base 586 drivers/net/ethernet/8390/etherh.c switch (cmd->base.port) { base 205 drivers/net/ethernet/8390/pcnet_cs.c void __iomem *base; base 280 drivers/net/ethernet/8390/pcnet_cs.c u_char __iomem *base, *virt; base 300 drivers/net/ethernet/8390/pcnet_cs.c base = &virt[hw_info[i].offset & (resource_size(link->resource[2])-1)]; base 301 drivers/net/ethernet/8390/pcnet_cs.c if ((readb(base+0) == hw_info[i].a0) && base 302 drivers/net/ethernet/8390/pcnet_cs.c (readb(base+2) == hw_info[i].a1) && base 303 drivers/net/ethernet/8390/pcnet_cs.c (readb(base+4) == hw_info[i].a2)) { base 305 drivers/net/ethernet/8390/pcnet_cs.c dev->dev_addr[j] = readb(base + (j<<1)); base 647 drivers/net/ethernet/8390/pcnet_cs.c iounmap(info->base); base 1372 drivers/net/ethernet/8390/pcnet_cs.c void __iomem *base = ei_status.mem; base 1380 drivers/net/ethernet/8390/pcnet_cs.c copyin(buf, base + offset, semi_count); base 1385 drivers/net/ethernet/8390/pcnet_cs.c copyin(buf, base + offset, count); base 1429 drivers/net/ethernet/8390/pcnet_cs.c info->base = ioremap(link->resource[3]->start, base 1431 drivers/net/ethernet/8390/pcnet_cs.c if (unlikely(!info->base)) { base 1437 drivers/net/ethernet/8390/pcnet_cs.c __raw_writew((i>>1), info->base+offset+i); base 1440 drivers/net/ethernet/8390/pcnet_cs.c if (__raw_readw(info->base+offset+i) != (i>>1)) break; base 1443 drivers/net/ethernet/8390/pcnet_cs.c iounmap(info->base); base 1445 drivers/net/ethernet/8390/pcnet_cs.c info->base = NULL; base 1449 drivers/net/ethernet/8390/pcnet_cs.c ei_status.mem = info->base + offset; base 571 drivers/net/ethernet/adaptec/starfire.c void __iomem *base; base 653 drivers/net/ethernet/adaptec/starfire.c void __iomem *base; base 687 drivers/net/ethernet/adaptec/starfire.c base = ioremap(ioaddr, io_size); base 688 drivers/net/ethernet/adaptec/starfire.c if (!base) { base 714 drivers/net/ethernet/adaptec/starfire.c dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i); base 720 drivers/net/ethernet/adaptec/starfire.c (unsigned int)readb(base + EEPROMCtrl + i), base 725 drivers/net/ethernet/adaptec/starfire.c writel(MiiSoftReset, base + TxMode); base 727 drivers/net/ethernet/adaptec/starfire.c writel(0, base + TxMode); base 730 drivers/net/ethernet/adaptec/starfire.c writel(1, base + PCIDeviceConfig); base 734 drivers/net/ethernet/adaptec/starfire.c if ((readl(base + PCIDeviceConfig) & 1) == 0) base 744 drivers/net/ethernet/adaptec/starfire.c np->base = base; base 797 drivers/net/ethernet/adaptec/starfire.c dev->name, netdrv_tbl[chip_idx].name, base, base 837 drivers/net/ethernet/adaptec/starfire.c iounmap(base); base 850 drivers/net/ethernet/adaptec/starfire.c void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2); base 867 drivers/net/ethernet/adaptec/starfire.c void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2); base 878 drivers/net/ethernet/adaptec/starfire.c void __iomem *ioaddr = np->base; base 1111 drivers/net/ethernet/adaptec/starfire.c void __iomem *ioaddr = np->base; base 1164 drivers/net/ethernet/adaptec/starfire.c writew(i - 1, np->base + RxDescQIdx); base 1277 drivers/net/ethernet/adaptec/starfire.c writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx); base 1315 drivers/net/ethernet/adaptec/starfire.c void __iomem *ioaddr = np->base; base 1550 drivers/net/ethernet/adaptec/starfire.c writew(np->rx_done, np->base + CompletionQConsumerIdx); base 1565 drivers/net/ethernet/adaptec/starfire.c void __iomem *ioaddr = np->base; base 1620 drivers/net/ethernet/adaptec/starfire.c writew(entry, np->base + RxDescQIdx); base 1627 drivers/net/ethernet/adaptec/starfire.c void __iomem *ioaddr = np->base; base 1706 drivers/net/ethernet/adaptec/starfire.c writel(++np->tx_threshold, np->base + TxThreshold); base 1729 drivers/net/ethernet/adaptec/starfire.c void __iomem *ioaddr = np->base; base 1757 drivers/net/ethernet/adaptec/starfire.c void __iomem *filter_addr = np->base + HashTable + 8; base 1782 drivers/net/ethernet/adaptec/starfire.c void __iomem *ioaddr = np->base; base 1937 drivers/net/ethernet/adaptec/starfire.c void __iomem *ioaddr = np->base; base 2053 drivers/net/ethernet/adaptec/starfire.c iounmap(np->base); base 1124 drivers/net/ethernet/alacritech/slicoss.c u32 base; base 1177 drivers/net/ethernet/alacritech/slicoss.c base = sectstart[sect]; base 1181 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, SLIC_REG_WCS, base + addr); base 1197 drivers/net/ethernet/alacritech/slicoss.c base = sectstart[sect]; base 1198 drivers/net/ethernet/alacritech/slicoss.c if (base < 0x8000) base 1204 drivers/net/ethernet/alacritech/slicoss.c SLIC_WCS_COMPARE | (base + addr)); base 2593 drivers/net/ethernet/alteon/acenic.c cmd->base.port = PORT_FIBRE; base 2597 drivers/net/ethernet/alteon/acenic.c cmd->base.speed = SPEED_1000; base 2601 drivers/net/ethernet/alteon/acenic.c cmd->base.speed = SPEED_100; base 2603 drivers/net/ethernet/alteon/acenic.c cmd->base.speed = SPEED_10; base 2605 drivers/net/ethernet/alteon/acenic.c cmd->base.speed = 0; base 2608 drivers/net/ethernet/alteon/acenic.c cmd->base.duplex = DUPLEX_FULL; base 2610 drivers/net/ethernet/alteon/acenic.c cmd->base.duplex = DUPLEX_HALF; base 2613 drivers/net/ethernet/alteon/acenic.c cmd->base.autoneg = AUTONEG_ENABLE; base 2615 drivers/net/ethernet/alteon/acenic.c cmd->base.autoneg = AUTONEG_DISABLE; base 2657 drivers/net/ethernet/alteon/acenic.c if (cmd->base.autoneg == AUTONEG_ENABLE) base 2659 drivers/net/ethernet/alteon/acenic.c if (cmd->base.speed != speed) { base 2661 drivers/net/ethernet/alteon/acenic.c switch (cmd->base.speed) { base 2674 drivers/net/ethernet/alteon/acenic.c if (cmd->base.duplex == DUPLEX_FULL) base 230 drivers/net/ethernet/altera/altera_sgdma.c struct sgdma_descrip __iomem *base = base 238 drivers/net/ethernet/altera/altera_sgdma.c desc = &base[0]; base 272 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h struct ena_eth_io_rx_cdesc_base base; base 285 drivers/net/ethernet/amazon/ena/ena_ethtool.c link_ksettings->base.speed = link->speed; base 294 drivers/net/ethernet/amazon/ena/ena_ethtool.c link_ksettings->base.autoneg = base 298 drivers/net/ethernet/amazon/ena/ena_ethtool.c link_ksettings->base.duplex = DUPLEX_FULL; base 45 drivers/net/ethernet/amd/7990.c #define WRITERAP(lp, x) out_be16(lp->base + LANCE_RAP, (x)) base 46 drivers/net/ethernet/amd/7990.c #define WRITERDP(lp, x) out_be16(lp->base + LANCE_RDP, (x)) base 47 drivers/net/ethernet/amd/7990.c #define READRDP(lp) in_be16(lp->base + LANCE_RDP) base 69 drivers/net/ethernet/amd/7990.c out_be16(lp->base + HPLANCE_REGOFF + LANCE_RAP, value); base 70 drivers/net/ethernet/amd/7990.c } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0); base 76 drivers/net/ethernet/amd/7990.c out_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP, value); base 77 drivers/net/ethernet/amd/7990.c } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0); base 84 drivers/net/ethernet/amd/7990.c value = in_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP); base 85 drivers/net/ethernet/amd/7990.c } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0); base 103 drivers/net/ethernet/amd/7990.h unsigned long base; base 47 drivers/net/ethernet/amd/am79c961a.c static void write_rreg(u_long base, u_int reg, u_int val) base 67 drivers/net/ethernet/amd/am79c961a.c static inline void write_ireg(u_long base, u_int reg, u_int val) base 123 drivers/net/ethernet/amd/atarilance.c unsigned short base; /* Low word of base addr */ base 131 drivers/net/ethernet/amd/atarilance.c unsigned short base; /* Low word of base addr */ base 241 drivers/net/ethernet/amd/atarilance.c #define PKTBUF_ADDR(head) (((unsigned char *)(MEM)) + (head)->base) base 707 drivers/net/ethernet/amd/atarilance.c MEM->tx_head[i].base = offset; base 717 drivers/net/ethernet/amd/atarilance.c MEM->rx_head[i].base = offset; base 753 drivers/net/ethernet/amd/atarilance.c i, MEM->rx_head[i].base, base 758 drivers/net/ethernet/amd/atarilance.c i, MEM->tx_head[i].base, base 1085 drivers/net/ethernet/amd/au1000_eth.c struct resource *base, *macen, *macdma; base 1087 drivers/net/ethernet/amd/au1000_eth.c base = platform_get_resource(pdev, IORESOURCE_MEM, 0); base 1088 drivers/net/ethernet/amd/au1000_eth.c if (!base) { base 1114 drivers/net/ethernet/amd/au1000_eth.c if (!request_mem_region(base->start, resource_size(base), base 1164 drivers/net/ethernet/amd/au1000_eth.c ioremap_nocache(base->start, resource_size(base)); base 1283 drivers/net/ethernet/amd/au1000_eth.c dev->base_addr = base->start; base 1302 drivers/net/ethernet/amd/au1000_eth.c (unsigned long)base->start, irq); base 1344 drivers/net/ethernet/amd/au1000_eth.c release_mem_region(base->start, resource_size(base)); base 1354 drivers/net/ethernet/amd/au1000_eth.c struct resource *base, *macen; base 1376 drivers/net/ethernet/amd/au1000_eth.c base = platform_get_resource(pdev, IORESOURCE_MEM, 2); base 1377 drivers/net/ethernet/amd/au1000_eth.c release_mem_region(base->start, resource_size(base)); base 1379 drivers/net/ethernet/amd/au1000_eth.c base = platform_get_resource(pdev, IORESOURCE_MEM, 0); base 1380 drivers/net/ethernet/amd/au1000_eth.c release_mem_region(base->start, resource_size(base)); base 153 drivers/net/ethernet/amd/hplance.c lp->lance.base = va; base 174 drivers/net/ethernet/amd/hplance.c out_be16(lp->base + HPLANCE_REGOFF + LANCE_RAP, value); base 175 drivers/net/ethernet/amd/hplance.c } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0); base 182 drivers/net/ethernet/amd/hplance.c out_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP, value); base 183 drivers/net/ethernet/amd/hplance.c } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0); base 191 drivers/net/ethernet/amd/hplance.c value = in_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP); base 192 drivers/net/ethernet/amd/hplance.c } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0); base 205 drivers/net/ethernet/amd/hplance.c out_8(lp->base + HPLANCE_STATUS, LE_IE); base 214 drivers/net/ethernet/amd/hplance.c out_8(lp->base + HPLANCE_STATUS, 0); /* disable interrupts at boardlevel */ base 214 drivers/net/ethernet/amd/lance.c s32 base; base 220 drivers/net/ethernet/amd/lance.c s32 base; base 846 drivers/net/ethernet/amd/lance.c lp->rx_ring[i].base = 0; /* Not owned by LANCE chip. */ base 880 drivers/net/ethernet/amd/lance.c lp->rx_ring[i].base = 0; base 882 drivers/net/ethernet/amd/lance.c lp->rx_ring[i].base = (u32)isa_virt_to_bus(rx_buff) | 0x80000000; base 889 drivers/net/ethernet/amd/lance.c lp->tx_ring[i].base = 0; base 934 drivers/net/ethernet/amd/lance.c lp->rx_ring[i].base, -lp->rx_ring[i].buf_length, base 938 drivers/net/ethernet/amd/lance.c lp->tx_ring[i].base, -lp->tx_ring[i].length, base 998 drivers/net/ethernet/amd/lance.c lp->tx_ring[entry].base = base 1003 drivers/net/ethernet/amd/lance.c lp->tx_ring[entry].base = ((u32)isa_virt_to_bus(skb->data) & 0xffffff) | 0x83000000; base 1052 drivers/net/ethernet/amd/lance.c int status = lp->tx_ring[entry].base; base 1057 drivers/net/ethernet/amd/lance.c lp->tx_ring[entry].base = 0; base 1151 drivers/net/ethernet/amd/lance.c while (lp->rx_ring[entry].base >= 0) { base 1152 drivers/net/ethernet/amd/lance.c int status = lp->rx_ring[entry].base >> 24; base 1169 drivers/net/ethernet/amd/lance.c lp->rx_ring[entry].base &= 0x03ffffff; base 1189 drivers/net/ethernet/amd/lance.c if (lp->rx_ring[(entry+i) & RX_RING_MOD_MASK].base < 0) base 1195 drivers/net/ethernet/amd/lance.c lp->rx_ring[entry].base |= 0x80000000; base 1203 drivers/net/ethernet/amd/lance.c (unsigned char *)isa_bus_to_virt((lp->rx_ring[entry].base & 0x00ffffff)), base 1214 drivers/net/ethernet/amd/lance.c lp->rx_ring[entry].base |= 0x80000000; base 122 drivers/net/ethernet/amd/mvme147.c lp->lance.base = dev->base_addr; base 147 drivers/net/ethernet/amd/mvme147.c out_be16(lp->base + LANCE_RAP, value); base 152 drivers/net/ethernet/amd/mvme147.c out_be16(lp->base + LANCE_RDP, value); base 157 drivers/net/ethernet/amd/mvme147.c return in_be16(lp->base + LANCE_RDP); base 217 drivers/net/ethernet/amd/pcnet32.c __le32 base; base 225 drivers/net/ethernet/amd/pcnet32.c __le32 base; base 596 drivers/net/ethernet/amd/pcnet32.c new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]); base 740 drivers/net/ethernet/amd/pcnet32.c cmd->base.autoneg = AUTONEG_ENABLE; base 742 drivers/net/ethernet/amd/pcnet32.c cmd->base.port = PORT_AUI; base 744 drivers/net/ethernet/amd/pcnet32.c cmd->base.port = PORT_TP; base 746 drivers/net/ethernet/amd/pcnet32.c cmd->base.autoneg = AUTONEG_DISABLE; base 747 drivers/net/ethernet/amd/pcnet32.c cmd->base.port = lp->port_tp ? PORT_TP : PORT_AUI; base 749 drivers/net/ethernet/amd/pcnet32.c cmd->base.duplex = lp->fdx ? DUPLEX_FULL : DUPLEX_HALF; base 750 drivers/net/ethernet/amd/pcnet32.c cmd->base.speed = SPEED_10; base 776 drivers/net/ethernet/amd/pcnet32.c lp->autoneg = cmd->base.autoneg == AUTONEG_ENABLE; base 778 drivers/net/ethernet/amd/pcnet32.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 783 drivers/net/ethernet/amd/pcnet32.c lp->port_tp = cmd->base.port == PORT_TP; base 785 drivers/net/ethernet/amd/pcnet32.c if (cmd->base.port == PORT_TP) base 790 drivers/net/ethernet/amd/pcnet32.c lp->fdx = cmd->base.duplex == DUPLEX_FULL; base 792 drivers/net/ethernet/amd/pcnet32.c if (cmd->base.duplex == DUPLEX_FULL) base 1052 drivers/net/ethernet/amd/pcnet32.c lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]); base 1252 drivers/net/ethernet/amd/pcnet32.c rxp->base = cpu_to_le32(new_dma_addr); base 1324 drivers/net/ethernet/amd/pcnet32.c lp->tx_ring[entry].base = 0; base 2401 drivers/net/ethernet/amd/pcnet32.c lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]); base 2411 drivers/net/ethernet/amd/pcnet32.c lp->tx_ring[i].base = 0; base 2478 drivers/net/ethernet/amd/pcnet32.c le32_to_cpu(lp->rx_ring[i].base), base 2484 drivers/net/ethernet/amd/pcnet32.c le32_to_cpu(lp->tx_ring[i].base), base 2538 drivers/net/ethernet/amd/pcnet32.c lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]); base 2548 drivers/net/ethernet/amd/pcnet32.c if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) { base 106 drivers/net/ethernet/amd/sun3lance.c #define PKTBUF_ADDR(head) (void *)((unsigned long)(MEM) | (head)->base) base 111 drivers/net/ethernet/amd/sun3lance.c unsigned short base; /* Low word of base addr */ base 119 drivers/net/ethernet/amd/sun3lance.c unsigned short base; /* Low word of base addr */ base 466 drivers/net/ethernet/amd/sun3lance.c MEM->tx_head[i].base = dvma_vtob(MEM->tx_data[i]); base 475 drivers/net/ethernet/amd/sun3lance.c MEM->rx_head[i].base = dvma_vtob(MEM->rx_data[i]); base 550 drivers/net/ethernet/amd/sun3lance.c i, MEM->rx_head[i].base, base 555 drivers/net/ethernet/amd/sun3lance.c i, MEM->tx_head[i].base, base 315 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c cmd->base.phy_address = pdata->phy.address; base 317 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c cmd->base.autoneg = pdata->phy.autoneg; base 318 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c cmd->base.speed = pdata->phy.speed; base 319 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c cmd->base.duplex = pdata->phy.duplex; base 321 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c cmd->base.port = PORT_NONE; base 339 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c speed = cmd->base.speed; base 341 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c if (cmd->base.phy_address != pdata->phy.address) { base 343 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c cmd->base.phy_address); base 347 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c if ((cmd->base.autoneg != AUTONEG_ENABLE) && base 348 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c (cmd->base.autoneg != AUTONEG_DISABLE)) { base 350 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c cmd->base.autoneg); base 354 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c if (cmd->base.autoneg == AUTONEG_DISABLE) { base 360 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c if (cmd->base.duplex != DUPLEX_FULL) { base 362 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c cmd->base.duplex); base 376 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c if ((cmd->base.autoneg == AUTONEG_ENABLE) && base 384 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c pdata->phy.autoneg = cmd->base.autoneg; base 386 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c pdata->phy.duplex = cmd->base.duplex; base 390 drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE) base 269 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c u8 base[64]; base 827 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c sfp_base = sfp_eeprom->base; base 910 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], base 917 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], base 1129 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c sfp_base = sfp_eeprom->base; base 1198 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], base 1204 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], base 1210 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], base 1259 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], base 1260 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c sfp_eeprom.base, base 1261 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c sizeof(sfp_eeprom.base) - 1)) { base 105 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c static int xgene_cle_poll_cmd_done(void __iomem *base, base 112 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c status = ioread32(base + INDCMD_STATUS); base 128 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c void __iomem *base = cle->base; base 142 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c iowrite32(ind_addr, base + INDADDR); base 144 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c iowrite32(data[j], base + DATA_RAM0 + (j * 4)); base 145 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c iowrite32(cmd, base + INDCMD); base 147 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c ret = xgene_cle_poll_cmd_done(base, cmd); base 159 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c void __iomem *addr, *base = cle->base; base 167 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c addr = base + cle->active_parser * offset; base 169 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c addr = base + (i * offset); base 618 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c void __iomem *base = enet_cle->base; base 635 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c base_addr = base + DFCLSRESDB00 + offset; base 640 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c iowrite32(def_cls, base + DFCLSRESDBPTR0 + offset); base 732 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c void __iomem *base = cle->base; base 745 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c writel(val, base + RSS_CTRL0 + offset); base 279 drivers/net/ethernet/apm/xgene/xgene_enet_cle.h void __iomem *base; base 144 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c cmd->base.speed = SPEED_1000; base 145 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 146 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c cmd->base.port = PORT_MII; base 147 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 157 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c cmd->base.speed = SPEED_10000; base 158 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 159 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c cmd->base.port = PORT_FIBRE; base 160 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 1784 drivers/net/ethernet/apm/xgene/xgene_enet_main.c pdata->cle.base = base_addr + BLOCK_ETH_CLE_CSR_OFFSET; base 43 drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c cmd->base.speed = netif_carrier_ok(ndev) ? base 782 drivers/net/ethernet/aquantia/atlantic/aq_nic.c cmd->base.port = PORT_FIBRE; base 784 drivers/net/ethernet/aquantia/atlantic/aq_nic.c cmd->base.port = PORT_TP; base 786 drivers/net/ethernet/aquantia/atlantic/aq_nic.c cmd->base.duplex = DUPLEX_FULL; base 787 drivers/net/ethernet/aquantia/atlantic/aq_nic.c cmd->base.autoneg = self->aq_nic_cfg.is_autoneg; base 870 drivers/net/ethernet/aquantia/atlantic/aq_nic.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 874 drivers/net/ethernet/aquantia/atlantic/aq_nic.c speed = cmd->base.speed; base 147 drivers/net/ethernet/atheros/alx/ethtool.c cmd->base.port = PORT_TP; base 148 drivers/net/ethernet/atheros/alx/ethtool.c cmd->base.phy_address = 0; base 151 drivers/net/ethernet/atheros/alx/ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 153 drivers/net/ethernet/atheros/alx/ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 166 drivers/net/ethernet/atheros/alx/ethtool.c cmd->base.speed = hw->link_speed; base 167 drivers/net/ethernet/atheros/alx/ethtool.c cmd->base.duplex = hw->duplex; base 190 drivers/net/ethernet/atheros/alx/ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 195 drivers/net/ethernet/atheros/alx/ethtool.c adv_cfg = alx_speed_to_ethadv(cmd->base.speed, base 196 drivers/net/ethernet/atheros/alx/ethtool.c cmd->base.duplex); base 35 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c cmd->base.port = PORT_TP; base 36 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c cmd->base.phy_address = 0; base 39 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c cmd->base.speed = adapter->link_speed; base 41 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 43 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c cmd->base.duplex = DUPLEX_HALF; base 45 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 46 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 49 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 69 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 72 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c u32 speed = cmd->base.speed; base 74 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c if (cmd->base.duplex != DUPLEX_FULL) { base 83 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c if (cmd->base.duplex == DUPLEX_FULL) base 88 drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c if (cmd->base.duplex == DUPLEX_FULL) base 36 drivers/net/ethernet/atheros/atl1e/atl1e_ethtool.c cmd->base.port = PORT_TP; base 37 drivers/net/ethernet/atheros/atl1e/atl1e_ethtool.c cmd->base.phy_address = 0; base 40 drivers/net/ethernet/atheros/atl1e/atl1e_ethtool.c cmd->base.speed = adapter->link_speed; base 42 drivers/net/ethernet/atheros/atl1e/atl1e_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 44 drivers/net/ethernet/atheros/atl1e/atl1e_ethtool.c cmd->base.duplex = DUPLEX_HALF; base 46 drivers/net/ethernet/atheros/atl1e/atl1e_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 47 drivers/net/ethernet/atheros/atl1e/atl1e_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 50 drivers/net/ethernet/atheros/atl1e/atl1e_ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 73 drivers/net/ethernet/atheros/atl1e/atl1e_ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 3221 drivers/net/ethernet/atheros/atlx/atl1.c cmd->base.port = PORT_TP; base 3222 drivers/net/ethernet/atheros/atlx/atl1.c cmd->base.phy_address = 0; base 3227 drivers/net/ethernet/atheros/atlx/atl1.c cmd->base.speed = link_speed; base 3229 drivers/net/ethernet/atheros/atlx/atl1.c cmd->base.duplex = DUPLEX_FULL; base 3231 drivers/net/ethernet/atheros/atlx/atl1.c cmd->base.duplex = DUPLEX_HALF; base 3233 drivers/net/ethernet/atheros/atlx/atl1.c cmd->base.speed = SPEED_UNKNOWN; base 3234 drivers/net/ethernet/atheros/atlx/atl1.c cmd->base.duplex = DUPLEX_UNKNOWN; base 3238 drivers/net/ethernet/atheros/atlx/atl1.c cmd->base.autoneg = AUTONEG_ENABLE; base 3240 drivers/net/ethernet/atheros/atlx/atl1.c cmd->base.autoneg = AUTONEG_DISABLE; base 3266 drivers/net/ethernet/atheros/atlx/atl1.c if (cmd->base.autoneg == AUTONEG_ENABLE) base 3269 drivers/net/ethernet/atheros/atlx/atl1.c u32 speed = cmd->base.speed; base 3271 drivers/net/ethernet/atheros/atlx/atl1.c if (cmd->base.duplex != DUPLEX_FULL) { base 3280 drivers/net/ethernet/atheros/atlx/atl1.c if (cmd->base.duplex == DUPLEX_FULL) base 3285 drivers/net/ethernet/atheros/atlx/atl1.c if (cmd->base.duplex == DUPLEX_FULL) base 1740 drivers/net/ethernet/atheros/atlx/atl2.c cmd->base.port = PORT_TP; base 1741 drivers/net/ethernet/atheros/atlx/atl2.c cmd->base.phy_address = 0; base 1744 drivers/net/ethernet/atheros/atlx/atl2.c cmd->base.speed = adapter->link_speed; base 1746 drivers/net/ethernet/atheros/atlx/atl2.c cmd->base.duplex = DUPLEX_FULL; base 1748 drivers/net/ethernet/atheros/atlx/atl2.c cmd->base.duplex = DUPLEX_HALF; base 1750 drivers/net/ethernet/atheros/atlx/atl2.c cmd->base.speed = SPEED_UNKNOWN; base 1751 drivers/net/ethernet/atheros/atlx/atl2.c cmd->base.duplex = DUPLEX_UNKNOWN; base 1754 drivers/net/ethernet/atheros/atlx/atl2.c cmd->base.autoneg = AUTONEG_ENABLE; base 1777 drivers/net/ethernet/atheros/atlx/atl2.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 37 drivers/net/ethernet/aurora/nb8800.c return readb_relaxed(priv->base + reg); base 42 drivers/net/ethernet/aurora/nb8800.c return readl_relaxed(priv->base + reg); base 47 drivers/net/ethernet/aurora/nb8800.c writeb_relaxed(val, priv->base + reg); base 52 drivers/net/ethernet/aurora/nb8800.c writew_relaxed(val, priv->base + reg); base 57 drivers/net/ethernet/aurora/nb8800.c writel_relaxed(val, priv->base + reg); base 117 drivers/net/ethernet/aurora/nb8800.c return readl_poll_timeout_atomic(priv->base + NB8800_MDIO_CMD, base 717 drivers/net/ethernet/aurora/nb8800.c readb_poll_timeout_atomic(priv->base + NB8800_MC_INIT, val, !val, base 883 drivers/net/ethernet/aurora/nb8800.c err = readl_poll_timeout_atomic(priv->base + NB8800_TXC_CR, txcr, base 914 drivers/net/ethernet/aurora/nb8800.c err = readl_poll_timeout_atomic(priv->base + NB8800_RXC_CR, base 1345 drivers/net/ethernet/aurora/nb8800.c void __iomem *base; base 1358 drivers/net/ethernet/aurora/nb8800.c base = devm_ioremap_resource(&pdev->dev, res); base 1359 drivers/net/ethernet/aurora/nb8800.c if (IS_ERR(base)) base 1360 drivers/net/ethernet/aurora/nb8800.c return PTR_ERR(base); base 1372 drivers/net/ethernet/aurora/nb8800.c priv->base = base; base 242 drivers/net/ethernet/aurora/nb8800.h void __iomem *base; base 1862 drivers/net/ethernet/broadcom/b44.c cmd->base.speed = (bp->flags & B44_FLAG_100_BASE_T) ? base 1864 drivers/net/ethernet/broadcom/b44.c cmd->base.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ? base 1866 drivers/net/ethernet/broadcom/b44.c cmd->base.port = 0; base 1867 drivers/net/ethernet/broadcom/b44.c cmd->base.phy_address = bp->phy_addr; base 1868 drivers/net/ethernet/broadcom/b44.c cmd->base.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ? base 1870 drivers/net/ethernet/broadcom/b44.c if (cmd->base.autoneg == AUTONEG_ENABLE) base 1879 drivers/net/ethernet/broadcom/b44.c cmd->base.speed = 0; base 1880 drivers/net/ethernet/broadcom/b44.c cmd->base.duplex = 0xff; base 1907 drivers/net/ethernet/broadcom/b44.c speed = cmd->base.speed; base 1913 drivers/net/ethernet/broadcom/b44.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 1920 drivers/net/ethernet/broadcom/b44.c (cmd->base.duplex != DUPLEX_HALF && base 1921 drivers/net/ethernet/broadcom/b44.c cmd->base.duplex != DUPLEX_FULL)) { base 1927 drivers/net/ethernet/broadcom/b44.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 1955 drivers/net/ethernet/broadcom/b44.c if (cmd->base.duplex == DUPLEX_FULL) base 39 drivers/net/ethernet/broadcom/bcm63xx_enet.c return bcm_readl(priv->base + off); base 45 drivers/net/ethernet/broadcom/bcm63xx_enet.c bcm_writel(val, priv->base + off); base 53 drivers/net/ethernet/broadcom/bcm63xx_enet.c return bcm_readl(priv->base + off); base 59 drivers/net/ethernet/broadcom/bcm63xx_enet.c bcm_writel(val, priv->base + off); base 64 drivers/net/ethernet/broadcom/bcm63xx_enet.c return bcm_readw(priv->base + off); base 70 drivers/net/ethernet/broadcom/bcm63xx_enet.c bcm_writew(val, priv->base + off); base 75 drivers/net/ethernet/broadcom/bcm63xx_enet.c return bcm_readb(priv->base + off); base 81 drivers/net/ethernet/broadcom/bcm63xx_enet.c bcm_writeb(val, priv->base + off); base 1437 drivers/net/ethernet/broadcom/bcm63xx_enet.c cmd->base.autoneg = 0; base 1438 drivers/net/ethernet/broadcom/bcm63xx_enet.c cmd->base.speed = (priv->force_speed_100) ? base 1440 drivers/net/ethernet/broadcom/bcm63xx_enet.c cmd->base.duplex = (priv->force_duplex_full) ? base 1451 drivers/net/ethernet/broadcom/bcm63xx_enet.c cmd->base.port = PORT_MII; base 1468 drivers/net/ethernet/broadcom/bcm63xx_enet.c if (cmd->base.autoneg || base 1469 drivers/net/ethernet/broadcom/bcm63xx_enet.c (cmd->base.speed != SPEED_100 && base 1470 drivers/net/ethernet/broadcom/bcm63xx_enet.c cmd->base.speed != SPEED_10) || base 1471 drivers/net/ethernet/broadcom/bcm63xx_enet.c cmd->base.port != PORT_MII) base 1475 drivers/net/ethernet/broadcom/bcm63xx_enet.c (cmd->base.speed == SPEED_100) ? 1 : 0; base 1477 drivers/net/ethernet/broadcom/bcm63xx_enet.c (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0; base 1722 drivers/net/ethernet/broadcom/bcm63xx_enet.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 1723 drivers/net/ethernet/broadcom/bcm63xx_enet.c if (IS_ERR(priv->base)) { base 1724 drivers/net/ethernet/broadcom/bcm63xx_enet.c ret = PTR_ERR(priv->base); base 2686 drivers/net/ethernet/broadcom/bcm63xx_enet.c priv->base = devm_ioremap_resource(&pdev->dev, res_mem); base 2687 drivers/net/ethernet/broadcom/bcm63xx_enet.c if (IS_ERR(priv->base)) { base 2688 drivers/net/ethernet/broadcom/bcm63xx_enet.c ret = PTR_ERR(priv->base); base 197 drivers/net/ethernet/broadcom/bcm63xx_enet.h void __iomem *base; base 32 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg = readl_relaxed(priv->base + offset + off); \ base 38 drivers/net/ethernet/broadcom/bcmsysport.c writel_relaxed(val, priv->base + offset + off); \ base 59 drivers/net/ethernet/broadcom/bcmsysport.c return readl_relaxed(priv->base + SYS_PORT_RDMA_OFFSET + off); base 66 drivers/net/ethernet/broadcom/bcmsysport.c writel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off); base 1645 drivers/net/ethernet/broadcom/bcmsysport.c priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET; base 2475 drivers/net/ethernet/broadcom/bcmsysport.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 2476 drivers/net/ethernet/broadcom/bcmsysport.c if (IS_ERR(priv->base)) { base 2477 drivers/net/ethernet/broadcom/bcmsysport.c ret = PTR_ERR(priv->base); base 730 drivers/net/ethernet/broadcom/bcmsysport.h void __iomem *base; base 38 drivers/net/ethernet/broadcom/bgmac-platform.c return readl(bgmac->plat.base + offset); base 43 drivers/net/ethernet/broadcom/bgmac-platform.c writel(value, bgmac->plat.base + offset); base 211 drivers/net/ethernet/broadcom/bgmac-platform.c bgmac->plat.base = devm_ioremap_resource(&pdev->dev, regs); base 212 drivers/net/ethernet/broadcom/bgmac-platform.c if (IS_ERR(bgmac->plat.base)) base 213 drivers/net/ethernet/broadcom/bgmac-platform.c return PTR_ERR(bgmac->plat.base); base 482 drivers/net/ethernet/broadcom/bgmac.h void __iomem *base; base 5081 drivers/net/ethernet/broadcom/bnx2.c u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) + base 5084 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, base, base 5089 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, base 5093 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF, base 5096 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF, base 5100 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF, base 6928 drivers/net/ethernet/broadcom/bnx2.c cmd->base.port = bp->phy_port; base 6932 drivers/net/ethernet/broadcom/bnx2.c cmd->base.autoneg = AUTONEG_ENABLE; base 6934 drivers/net/ethernet/broadcom/bnx2.c cmd->base.autoneg = AUTONEG_DISABLE; base 6938 drivers/net/ethernet/broadcom/bnx2.c cmd->base.speed = bp->line_speed; base 6939 drivers/net/ethernet/broadcom/bnx2.c cmd->base.duplex = bp->duplex; base 6942 drivers/net/ethernet/broadcom/bnx2.c cmd->base.eth_tp_mdix = ETH_TP_MDI_X; base 6944 drivers/net/ethernet/broadcom/bnx2.c cmd->base.eth_tp_mdix = ETH_TP_MDI; base 6948 drivers/net/ethernet/broadcom/bnx2.c cmd->base.speed = SPEED_UNKNOWN; base 6949 drivers/net/ethernet/broadcom/bnx2.c cmd->base.duplex = DUPLEX_UNKNOWN; base 6953 drivers/net/ethernet/broadcom/bnx2.c cmd->base.phy_address = bp->phy_addr; base 6976 drivers/net/ethernet/broadcom/bnx2.c if (cmd->base.port != PORT_TP && cmd->base.port != PORT_FIBRE) base 6979 drivers/net/ethernet/broadcom/bnx2.c if (cmd->base.port != bp->phy_port && base 6986 drivers/net/ethernet/broadcom/bnx2.c if (!netif_running(dev) && cmd->base.port != bp->phy_port) base 6989 drivers/net/ethernet/broadcom/bnx2.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 6995 drivers/net/ethernet/broadcom/bnx2.c if (cmd->base.port == PORT_TP) { base 7007 drivers/net/ethernet/broadcom/bnx2.c u32 speed = cmd->base.speed; base 7009 drivers/net/ethernet/broadcom/bnx2.c if (cmd->base.port == PORT_FIBRE) { base 7012 drivers/net/ethernet/broadcom/bnx2.c (cmd->base.duplex != DUPLEX_FULL)) base 7023 drivers/net/ethernet/broadcom/bnx2.c req_duplex = cmd->base.duplex; base 7037 drivers/net/ethernet/broadcom/bnx2.c err = bnx2_setup_phy(bp, cmd->base.port); base 1186 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h u32 base; base 235 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 237 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.duplex = DUPLEX_HALF; base 239 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.speed = bp->vf_link_vars.line_speed; base 241 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 242 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 245 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.port = PORT_OTHER; base 246 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.phy_address = 0; base 247 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 253 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.cmd, supported, advertising, base 254 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.speed, base 255 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.duplex, cmd->base.port, cmd->base.phy_address, base 256 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.autoneg); base 285 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.duplex = bp->link_vars.duplex; base 288 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.speed = bnx2x_get_mf_speed(bp); base 290 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.speed = bp->link_vars.line_speed; base 292 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 293 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 296 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.port = bnx2x_get_port_type(bp); base 298 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.phy_address = bp->mdio.prtad; base 301 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 303 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 360 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.cmd, supported, advertising, base 361 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.speed, base 362 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.duplex, cmd->base.port, cmd->base.phy_address, base 363 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.autoneg); base 375 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u8 duplex = cmd->base.duplex; base 389 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.cmd, supported, advertising, base 390 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.speed, base 391 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.duplex, cmd->base.port, cmd->base.phy_address, base 392 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c cmd->base.autoneg); base 394 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c speed = cmd->base.speed; base 434 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (cmd->base.port != bnx2x_get_port_type(bp)) { base 435 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c switch (cmd->base.port) { base 485 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 15 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base) base 17 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[151].base + ((assertListEntry) * IRO[151].m1)) base 19 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \ base 22 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \ base 25 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[163].base + ((funcId) * IRO[163].m1)) base 27 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[153].base + ((funcId) * IRO[153].m1)) base 29 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2)) base 31 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \ base 33 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h #define CSTORM_IGU_MODE_OFFSET (IRO[161].base) base 35 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[323].base + ((pfId) * IRO[323].m1)) base 37 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[324].base + ((pfId) * IRO[324].m1)) base 39 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2)) base 41 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2)) base 43 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2)) base 45 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2)) base 47 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2)) base 49 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2)) base 51 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2)) base 53 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[322].base + ((pfId) * IRO[322].m1)) base 55 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[314].base + ((pfId) * IRO[314].m1)) base 57 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[313].base + ((pfId) * IRO[313].m1)) base 59 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[312].base + ((pfId) * IRO[312].m1)) base 61 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[155].base + ((funcId) * IRO[155].m1)) base 63 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[146].base + ((pfId) * IRO[146].m1)) base 65 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[147].base + ((pfId) * IRO[147].m1)) base 67 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[145].base + ((pfId) * IRO[145].m1)) base 70 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[148].base + ((pfId) * IRO[148].m1)) base 73 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2)) base 75 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[137].base + ((sbId) * IRO[137].m1)) base 77 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[138].base + ((sbId) * IRO[138].m1)) base 79 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2)) base 81 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[136].base + ((sbId) * IRO[136].m1)) base 84 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[141].base + ((sbId) * IRO[141].m1)) base 87 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[159].base + ((vfId) * IRO[159].m1)) base 89 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[160].base + ((vfId) * IRO[160].m1)) base 91 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[154].base + ((funcId) * IRO[154].m1)) base 93 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[207].base + ((pfId) * IRO[207].m1)) base 94 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h #define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base) base 96 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[101].base + ((assertListEntry) * IRO[101].m1)) base 98 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[205].base + ((pfId) * IRO[205].m1)) base 100 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[107].base + ((funcId) * IRO[107].m1)) base 102 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[278].base + ((pfId) * IRO[278].m1)) base 104 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[279].base + ((pfId) * IRO[279].m1)) base 106 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[280].base + ((pfId) * IRO[280].m1)) base 108 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[281].base + ((pfId) * IRO[281].m1)) base 110 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[277].base + ((pfId) * IRO[277].m1)) base 112 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[276].base + ((pfId) * IRO[276].m1)) base 114 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[275].base + ((pfId) * IRO[275].m1)) base 116 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[274].base + ((pfId) * IRO[274].m1)) base 118 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[284].base + ((pfId) * IRO[284].m1)) base 120 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[270].base + ((pfId) * IRO[270].m1)) base 122 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[271].base + ((pfId) * IRO[271].m1)) base 124 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[272].base + ((pfId) * IRO[272].m1)) base 126 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[273].base + ((pfId) * IRO[273].m1)) base 128 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[206].base + ((pfId) * IRO[206].m1)) base 130 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[109].base + ((funcId) * IRO[109].m1)) base 132 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[223].base + ((pfId) * IRO[223].m1)) base 134 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[108].base + ((funcId) * IRO[108].m1)) base 135 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h #define USTORM_AGG_DATA_OFFSET (IRO[212].base) base 137 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base) base 139 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[180].base + ((assertListEntry) * IRO[180].m1)) base 141 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[187].base + ((portId) * IRO[187].m1)) base 143 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[325].base + ((pfId) * IRO[325].m1)) base 145 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[182].base + ((funcId) * IRO[182].m1)) base 147 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[289].base + ((pfId) * IRO[289].m1)) base 149 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[290].base + ((pfId) * IRO[290].m1)) base 151 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[294].base + ((pfId) * IRO[294].m1)) base 153 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[291].base + ((pfId) * IRO[291].m1)) base 155 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[287].base + ((pfId) * IRO[287].m1)) base 157 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[286].base + ((pfId) * IRO[286].m1)) base 159 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[285].base + ((pfId) * IRO[285].m1)) base 161 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[288].base + ((pfId) * IRO[288].m1)) base 163 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[292].base + ((pfId) * IRO[292].m1)) base 165 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[293].base + ((pfId) * IRO[293].m1)) base 167 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[186].base + ((pfId) * IRO[186].m1)) base 169 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[184].base + ((funcId) * IRO[184].m1)) base 171 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \ base 174 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[216].base + ((qzoneId) * IRO[216].m1)) base 175 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h #define USTORM_TPA_BTR_OFFSET (IRO[213].base) base 178 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[183].base + ((funcId) * IRO[183].m1)) base 179 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base) base 180 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base) base 181 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h #define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base) base 183 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[50].base + ((assertListEntry) * IRO[50].m1)) base 185 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[43].base + ((portId) * IRO[43].m1)) base 187 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[45].base + ((pfId) * IRO[45].m1)) base 189 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[47].base + ((funcId) * IRO[47].m1)) base 191 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[302].base + ((pfId) * IRO[302].m1)) base 193 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[305].base + ((pfId) * IRO[305].m1)) base 195 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[306].base + ((pfId) * IRO[306].m1)) base 197 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[307].base + ((pfId) * IRO[307].m1)) base 199 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[308].base + ((pfId) * IRO[308].m1)) base 201 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[309].base + ((pfId) * IRO[309].m1)) base 203 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[310].base + ((pfId) * IRO[310].m1)) base 205 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[311].base + ((pfId) * IRO[311].m1)) base 207 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[301].base + ((pfId) * IRO[301].m1)) base 209 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[300].base + ((pfId) * IRO[300].m1)) base 211 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[299].base + ((pfId) * IRO[299].m1)) base 213 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[304].base + ((pfId) * IRO[304].m1)) base 215 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[303].base + ((pfId) * IRO[303].m1)) base 217 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[298].base + ((pfId) * IRO[298].m1)) base 219 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[297].base + ((pfId) * IRO[297].m1)) base 221 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[296].base + ((pfId) * IRO[296].m1)) base 223 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[295].base + ((pfId) * IRO[295].m1)) base 225 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[44].base + ((pfId) * IRO[44].m1)) base 227 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[49].base + ((funcId) * IRO[49].m1)) base 229 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[32].base + ((funcId) * IRO[32].m1)) base 232 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[30].base + ((funcId) * IRO[30].m1)) base 234 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[31].base + ((funcId) * IRO[31].m1)) base 236 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[217].base + ((portId) * IRO[217].m1)) base 238 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[218].base + ((portId) * IRO[218].m1)) base 240 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \ base 243 drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h (IRO[48].base + ((funcId) * IRO[48].m1)) base 147 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h #define IF_IS_INT_TABLE_ADDR(base, addr) \ base 148 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h if (((base) <= (addr)) && ((base) + 0x400 >= (addr))) base 150 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h #define IF_IS_PRAM_ADDR(base, addr) \ base 151 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h if (((base) <= (addr)) && ((base) + 0x40000 >= (addr))) base 7785 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 i, base = FUNC_ILT_BASE(func); base 7786 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c for (i = base; i < base + ILT_PER_FUNC; i++) base 10467 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; base 10468 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; base 10469 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c return base + (BP_ABS_FUNC(bp)) * stride; base 13500 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c target[i].base = be32_to_cpu(source[j]); base 607 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c int n, u8 *base, u8 stride, u8 size) base 610 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c u8 *next = base; base 4323 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c int base, int credit) base 4337 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c p->base_pool_offset = base; base 4358 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c if (base < 0) { base 329 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h struct bnx2x_vlan_mac_obj *o, int n, u8 *base, base 1507 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h int base, int credit); base 1452 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c struct ethtool_link_settings *base = &lk_ksettings->base; base 1464 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->autoneg = AUTONEG_ENABLE; base 1469 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->duplex = DUPLEX_UNKNOWN; base 1471 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->duplex = DUPLEX_FULL; base 1473 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->duplex = DUPLEX_HALF; base 1475 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->autoneg = AUTONEG_DISABLE; base 1478 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->duplex = DUPLEX_HALF; base 1480 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->duplex = DUPLEX_FULL; base 1482 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->speed = ethtool_speed; base 1484 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->port = PORT_NONE; base 1486 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->port = PORT_TP; base 1498 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->port = PORT_DA; base 1501 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->port = PORT_FIBRE; base 1503 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c base->phy_address = link_info->phy_addr; base 1587 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c const struct ethtool_link_settings *base = &lk_ksettings->base; base 1597 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c if (base->autoneg == AUTONEG_ENABLE) { base 1620 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c if (base->duplex == DUPLEX_HALF) { base 1625 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c speed = base->speed; base 4452 drivers/net/ethernet/broadcom/cnic.c u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) + base 4455 drivers/net/ethernet/broadcom/cnic.c CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT); base 4457 drivers/net/ethernet/broadcom/cnic.c CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8); base 4458 drivers/net/ethernet/broadcom/cnic.c CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220); base 4459 drivers/net/ethernet/broadcom/cnic.c CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220); base 385 drivers/net/ethernet/broadcom/cnic.h #define BNX2X_SHMEM_ADDR(base, field) (base + \ base 388 drivers/net/ethernet/broadcom/cnic.h #define BNX2X_SHMEM2_ADDR(base, field) (base + \ base 391 drivers/net/ethernet/broadcom/cnic.h #define BNX2X_SHMEM2_HAS(base, field) \ base 392 drivers/net/ethernet/broadcom/cnic.h ((base) && \ base 393 drivers/net/ethernet/broadcom/cnic.h (CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) > \ base 396 drivers/net/ethernet/broadcom/cnic.h #define BNX2X_MF_CFG_ADDR(base, field) \ base 397 drivers/net/ethernet/broadcom/cnic.h ((base) + offsetof(struct mf_cfg, field)) base 175 drivers/net/ethernet/broadcom/genet/bcmgenet.c return bcmgenet_readl(priv->base + base 184 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + base 193 drivers/net/ethernet/broadcom/genet/bcmgenet.c return bcmgenet_readl(priv->base + base 202 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + base 345 drivers/net/ethernet/broadcom/genet/bcmgenet.c return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + base 352 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + base 359 drivers/net/ethernet/broadcom/genet/bcmgenet.c return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + base 366 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + base 437 drivers/net/ethernet/broadcom/genet/bcmgenet.c return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + base 446 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + base 455 drivers/net/ethernet/broadcom/genet/bcmgenet.c return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + base 464 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + base 1037 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_readl(priv->base + off); base 1042 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(reg, priv->base + off); base 2554 drivers/net/ethernet/broadcom/genet/bcmgenet.c priv->rx_bds = priv->base + priv->hw_params->rdma_offset; base 2567 drivers/net/ethernet/broadcom/genet/bcmgenet.c priv->tx_bds = priv->base + priv->hw_params->tdma_offset; base 3484 drivers/net/ethernet/broadcom/genet/bcmgenet.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 3485 drivers/net/ethernet/broadcom/genet/bcmgenet.c if (IS_ERR(priv->base)) { base 3486 drivers/net/ethernet/broadcom/genet/bcmgenet.c err = PTR_ERR(priv->base); base 609 drivers/net/ethernet/broadcom/genet/bcmgenet.h void __iomem *base; base 691 drivers/net/ethernet/broadcom/genet/bcmgenet.h return __raw_readl(priv->base + offset + off); \ base 693 drivers/net/ethernet/broadcom/genet/bcmgenet.h return readl_relaxed(priv->base + offset + off); \ base 699 drivers/net/ethernet/broadcom/genet/bcmgenet.h __raw_writel(val, priv->base + offset + off); \ base 701 drivers/net/ethernet/broadcom/genet/bcmgenet.h writel_relaxed(val, priv->base + offset + off); \ base 291 drivers/net/ethernet/broadcom/sb1250-mac.c static int sbmac_init(struct platform_device *pldev, long long base); base 2159 drivers/net/ethernet/broadcom/sb1250-mac.c static int sbmac_init(struct platform_device *pldev, long long base) base 2258 drivers/net/ethernet/broadcom/sb1250-mac.c dev->name, base, eaddr); base 7663 drivers/net/ethernet/broadcom/tg3.c u32 base = (u32) mapping & 0xffffffff; base 7665 drivers/net/ethernet/broadcom/tg3.c return base + len + 8 < base; base 7675 drivers/net/ethernet/broadcom/tg3.c u32 base = (u32) mapping & 0xffffffff; base 7677 drivers/net/ethernet/broadcom/tg3.c return ((base + len + (mss & 0x3fff)) < base); base 12174 drivers/net/ethernet/broadcom/tg3.c cmd->base.port = PORT_TP; base 12177 drivers/net/ethernet/broadcom/tg3.c cmd->base.port = PORT_FIBRE; base 12199 drivers/net/ethernet/broadcom/tg3.c cmd->base.speed = tp->link_config.active_speed; base 12200 drivers/net/ethernet/broadcom/tg3.c cmd->base.duplex = tp->link_config.active_duplex; base 12207 drivers/net/ethernet/broadcom/tg3.c cmd->base.eth_tp_mdix = ETH_TP_MDI_X; base 12209 drivers/net/ethernet/broadcom/tg3.c cmd->base.eth_tp_mdix = ETH_TP_MDI; base 12212 drivers/net/ethernet/broadcom/tg3.c cmd->base.speed = SPEED_UNKNOWN; base 12213 drivers/net/ethernet/broadcom/tg3.c cmd->base.duplex = DUPLEX_UNKNOWN; base 12214 drivers/net/ethernet/broadcom/tg3.c cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; base 12216 drivers/net/ethernet/broadcom/tg3.c cmd->base.phy_address = tp->phy_addr; base 12217 drivers/net/ethernet/broadcom/tg3.c cmd->base.autoneg = tp->link_config.autoneg; base 12225 drivers/net/ethernet/broadcom/tg3.c u32 speed = cmd->base.speed; base 12236 drivers/net/ethernet/broadcom/tg3.c if (cmd->base.autoneg != AUTONEG_ENABLE && base 12237 drivers/net/ethernet/broadcom/tg3.c cmd->base.autoneg != AUTONEG_DISABLE) base 12240 drivers/net/ethernet/broadcom/tg3.c if (cmd->base.autoneg == AUTONEG_DISABLE && base 12241 drivers/net/ethernet/broadcom/tg3.c cmd->base.duplex != DUPLEX_FULL && base 12242 drivers/net/ethernet/broadcom/tg3.c cmd->base.duplex != DUPLEX_HALF) base 12248 drivers/net/ethernet/broadcom/tg3.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 12282 drivers/net/ethernet/broadcom/tg3.c if (cmd->base.duplex != DUPLEX_FULL) base 12293 drivers/net/ethernet/broadcom/tg3.c tp->link_config.autoneg = cmd->base.autoneg; base 12294 drivers/net/ethernet/broadcom/tg3.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 12302 drivers/net/ethernet/broadcom/tg3.c tp->link_config.duplex = cmd->base.duplex; base 98 drivers/net/ethernet/brocade/bna/bfi_enet.h struct bfi_enet_txq_wi_base base; base 104 drivers/net/ethernet/brocade/bna/bfi_enet.h #define wi_hdr wi.base base 242 drivers/net/ethernet/brocade/bna/bnad_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 245 drivers/net/ethernet/brocade/bna/bnad_ethtool.c cmd->base.port = PORT_FIBRE; base 246 drivers/net/ethernet/brocade/bna/bnad_ethtool.c cmd->base.phy_address = 0; base 249 drivers/net/ethernet/brocade/bna/bnad_ethtool.c cmd->base.speed = SPEED_10000; base 250 drivers/net/ethernet/brocade/bna/bnad_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 252 drivers/net/ethernet/brocade/bna/bnad_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 253 drivers/net/ethernet/brocade/bna/bnad_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 269 drivers/net/ethernet/brocade/bna/bnad_ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE) base 272 drivers/net/ethernet/brocade/bna/bnad_ethtool.c if ((cmd->base.speed == SPEED_10000) && base 273 drivers/net/ethernet/brocade/bna/bnad_ethtool.c (cmd->base.duplex == DUPLEX_FULL)) base 366 drivers/net/ethernet/calxeda/xgmac.c void __iomem *base; base 529 drivers/net/ethernet/calxeda/xgmac.c xgmac_dma_flush_tx_fifo(priv->base); base 661 drivers/net/ethernet/calxeda/xgmac.c writel(flow, priv->base + XGMAC_FLOW_CTRL); base 663 drivers/net/ethernet/calxeda/xgmac.c reg = readl(priv->base + XGMAC_OMR); base 665 drivers/net/ethernet/calxeda/xgmac.c writel(reg, priv->base + XGMAC_OMR); base 667 drivers/net/ethernet/calxeda/xgmac.c writel(0, priv->base + XGMAC_FLOW_CTRL); base 669 drivers/net/ethernet/calxeda/xgmac.c reg = readl(priv->base + XGMAC_OMR); base 671 drivers/net/ethernet/calxeda/xgmac.c writel(reg, priv->base + XGMAC_OMR); base 773 drivers/net/ethernet/calxeda/xgmac.c writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR); base 774 drivers/net/ethernet/calxeda/xgmac.c writel(priv->dma_rx_phy, priv->base + XGMAC_DMA_RX_BASE_ADDR); base 912 drivers/net/ethernet/calxeda/xgmac.c writel(0, priv->base + XGMAC_DMA_INTR_ENA); base 916 drivers/net/ethernet/calxeda/xgmac.c reg = readl(priv->base + XGMAC_DMA_CONTROL); base 917 drivers/net/ethernet/calxeda/xgmac.c writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL); base 919 drivers/net/ethernet/calxeda/xgmac.c value = readl(priv->base + XGMAC_DMA_STATUS) & 0x700000; base 926 drivers/net/ethernet/calxeda/xgmac.c writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR); base 927 drivers/net/ethernet/calxeda/xgmac.c writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL); base 930 drivers/net/ethernet/calxeda/xgmac.c priv->base + XGMAC_DMA_STATUS); base 938 drivers/net/ethernet/calxeda/xgmac.c writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_STATUS); base 939 drivers/net/ethernet/calxeda/xgmac.c writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA); base 947 drivers/net/ethernet/calxeda/xgmac.c void __iomem *ioaddr = priv->base; base 1006 drivers/net/ethernet/calxeda/xgmac.c void __iomem *ioaddr = priv->base; base 1052 drivers/net/ethernet/calxeda/xgmac.c if (readl(priv->base + XGMAC_DMA_INTR_ENA)) base 1055 drivers/net/ethernet/calxeda/xgmac.c writel(0, priv->base + XGMAC_DMA_INTR_ENA); base 1060 drivers/net/ethernet/calxeda/xgmac.c xgmac_mac_disable(priv->base); base 1134 drivers/net/ethernet/calxeda/xgmac.c writel(1, priv->base + XGMAC_DMA_TX_POLL); base 1241 drivers/net/ethernet/calxeda/xgmac.c __raw_writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA); base 1273 drivers/net/ethernet/calxeda/xgmac.c void __iomem *ioaddr = priv->base; base 1368 drivers/net/ethernet/calxeda/xgmac.c void __iomem *ioaddr = priv->base; base 1387 drivers/net/ethernet/calxeda/xgmac.c intr_status = __raw_readl(priv->base + XGMAC_DMA_STATUS); base 1388 drivers/net/ethernet/calxeda/xgmac.c intr_status &= __raw_readl(priv->base + XGMAC_DMA_INTR_ENA); base 1389 drivers/net/ethernet/calxeda/xgmac.c __raw_writel(intr_status, priv->base + XGMAC_DMA_STATUS); base 1421 drivers/net/ethernet/calxeda/xgmac.c __raw_writel(DMA_INTR_ABNORMAL, priv->base + XGMAC_DMA_INTR_ENA); base 1444 drivers/net/ethernet/calxeda/xgmac.c void __iomem *base = priv->base; base 1448 drivers/net/ethernet/calxeda/xgmac.c writel(XGMAC_MMC_CTRL_CNT_FRZ, base + XGMAC_MMC_CTRL); base 1450 drivers/net/ethernet/calxeda/xgmac.c storage->rx_bytes = readl(base + XGMAC_MMC_RXOCTET_G_LO); base 1451 drivers/net/ethernet/calxeda/xgmac.c storage->rx_bytes |= (u64)(readl(base + XGMAC_MMC_RXOCTET_G_HI)) << 32; base 1453 drivers/net/ethernet/calxeda/xgmac.c storage->rx_packets = readl(base + XGMAC_MMC_RXFRAME_GB_LO); base 1454 drivers/net/ethernet/calxeda/xgmac.c storage->multicast = readl(base + XGMAC_MMC_RXMCFRAME_G); base 1455 drivers/net/ethernet/calxeda/xgmac.c storage->rx_crc_errors = readl(base + XGMAC_MMC_RXCRCERR); base 1456 drivers/net/ethernet/calxeda/xgmac.c storage->rx_length_errors = readl(base + XGMAC_MMC_RXLENGTHERR); base 1457 drivers/net/ethernet/calxeda/xgmac.c storage->rx_missed_errors = readl(base + XGMAC_MMC_RXOVERFLOW); base 1459 drivers/net/ethernet/calxeda/xgmac.c storage->tx_bytes = readl(base + XGMAC_MMC_TXOCTET_G_LO); base 1460 drivers/net/ethernet/calxeda/xgmac.c storage->tx_bytes |= (u64)(readl(base + XGMAC_MMC_TXOCTET_G_HI)) << 32; base 1462 drivers/net/ethernet/calxeda/xgmac.c count = readl(base + XGMAC_MMC_TXFRAME_GB_LO); base 1463 drivers/net/ethernet/calxeda/xgmac.c storage->tx_errors = count - readl(base + XGMAC_MMC_TXFRAME_G_LO); base 1465 drivers/net/ethernet/calxeda/xgmac.c storage->tx_fifo_errors = readl(base + XGMAC_MMC_TXUNDERFLOW); base 1467 drivers/net/ethernet/calxeda/xgmac.c writel(0, base + XGMAC_MMC_CTRL); base 1474 drivers/net/ethernet/calxeda/xgmac.c void __iomem *ioaddr = priv->base; base 1491 drivers/net/ethernet/calxeda/xgmac.c void __iomem *ioaddr = priv->base; base 1525 drivers/net/ethernet/calxeda/xgmac.c cmd->base.autoneg = 0; base 1526 drivers/net/ethernet/calxeda/xgmac.c cmd->base.duplex = DUPLEX_FULL; base 1527 drivers/net/ethernet/calxeda/xgmac.c cmd->base.speed = 10000; base 1597 drivers/net/ethernet/calxeda/xgmac.c *data++ = readl(priv->base + base 1722 drivers/net/ethernet/calxeda/xgmac.c priv->base = ioremap(res->start, resource_size(res)); base 1723 drivers/net/ethernet/calxeda/xgmac.c if (!priv->base) { base 1729 drivers/net/ethernet/calxeda/xgmac.c uid = readl(priv->base + XGMAC_VERSION); base 1733 drivers/net/ethernet/calxeda/xgmac.c writel(1, priv->base + XGMAC_ADDR_HIGH(31)); base 1734 drivers/net/ethernet/calxeda/xgmac.c if (readl(priv->base + XGMAC_ADDR_HIGH(31)) == 1) base 1739 drivers/net/ethernet/calxeda/xgmac.c writel(0, priv->base + XGMAC_DMA_INTR_ENA); base 1775 drivers/net/ethernet/calxeda/xgmac.c if (readl(priv->base + XGMAC_DMA_HW_FEATURE) & DMA_HW_FEAT_TXCOESEL) base 1786 drivers/net/ethernet/calxeda/xgmac.c xgmac_get_mac_addr(priv->base, ndev->dev_addr, 0); base 1804 drivers/net/ethernet/calxeda/xgmac.c iounmap(priv->base); base 1825 drivers/net/ethernet/calxeda/xgmac.c xgmac_mac_disable(priv->base); base 1834 drivers/net/ethernet/calxeda/xgmac.c iounmap(priv->base); base 1867 drivers/net/ethernet/calxeda/xgmac.c writel(0, priv->base + XGMAC_DMA_INTR_ENA); base 1871 drivers/net/ethernet/calxeda/xgmac.c value = readl(priv->base + XGMAC_DMA_CONTROL); base 1873 drivers/net/ethernet/calxeda/xgmac.c writel(value, priv->base + XGMAC_DMA_CONTROL); base 1875 drivers/net/ethernet/calxeda/xgmac.c xgmac_pmt(priv->base, priv->wolopts); base 1877 drivers/net/ethernet/calxeda/xgmac.c xgmac_mac_disable(priv->base); base 1886 drivers/net/ethernet/calxeda/xgmac.c void __iomem *ioaddr = priv->base; base 33 drivers/net/ethernet/cavium/common/cavium_ptp.c void __iomem *base; base 41 drivers/net/ethernet/cavium/common/cavium_ptp.c base = pci_ioremap_bar(pdev, PCI_RST_BAR_NO); base 42 drivers/net/ethernet/cavium/common/cavium_ptp.c if (!base) base 45 drivers/net/ethernet/cavium/common/cavium_ptp.c ret = CLOCK_BASE_RATE * ((readq(base + RST_BOOT) >> 33) & 0x3f); base 47 drivers/net/ethernet/cavium/common/cavium_ptp.c iounmap(base); base 228 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.port = PORT_TP; base 229 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.autoneg = AUTONEG_DISABLE; base 247 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.transceiver = XCVR_EXTERNAL; base 253 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.port = PORT_FIBRE; base 254 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.autoneg = AUTONEG_DISABLE; base 383 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.speed = linfo->link.s.speed; base 384 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.duplex = linfo->link.s.duplex; base 386 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.speed = SPEED_UNKNOWN; base 387 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.duplex = DUPLEX_UNKNOWN; base 396 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c const int speed = ecmd->base.speed; base 415 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c if ((ecmd->base.duplex != DUPLEX_UNKNOWN && base 416 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.duplex != linfo->link.s.duplex) || base 417 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.autoneg != AUTONEG_DISABLE || base 418 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (ecmd->base.speed != 10000 && ecmd->base.speed != 25000 && base 419 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c ecmd->base.speed != SPEED_UNKNOWN)) base 148 drivers/net/ethernet/cavium/liquidio/octeon_console.c u64 base, base 152 drivers/net/ethernet/cavium/liquidio/octeon_console.c base = (1ull << 63) | (base + offset); base 155 drivers/net/ethernet/cavium/liquidio/octeon_console.c return octeon_read_device_mem32(oct, base); base 157 drivers/net/ethernet/cavium/liquidio/octeon_console.c return octeon_read_device_mem64(oct, base); base 129 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 130 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 136 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c cmd->base.port = PORT_MII | PORT_TP; base 137 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 155 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c cmd->base.port = PORT_TP; base 158 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c cmd->base.port = PORT_FIBRE; base 161 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 165 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c cmd->base.port = PORT_FIBRE; base 166 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 171 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c cmd->base.duplex = nic->duplex; base 172 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c cmd->base.speed = nic->speed; base 66 drivers/net/ethernet/cavium/thunder/nicvf_queues.c dmem->base = dmem->unalign_base + (dmem->phys_base - dmem->dma); base 79 drivers/net/ethernet/cavium/thunder/nicvf_queues.c dmem->base = NULL; base 266 drivers/net/ethernet/cavium/thunder/nicvf_queues.c rbdr->desc = rbdr->dmem.base; base 329 drivers/net/ethernet/cavium/thunder/nicvf_queues.c if (!rbdr->dmem.base) base 485 drivers/net/ethernet/cavium/thunder/nicvf_queues.c cq->desc = cq->dmem.base; base 496 drivers/net/ethernet/cavium/thunder/nicvf_queues.c if (!cq->dmem.base) base 513 drivers/net/ethernet/cavium/thunder/nicvf_queues.c sq->desc = sq->dmem.base; base 580 drivers/net/ethernet/cavium/thunder/nicvf_queues.c if (!sq->dmem.base) base 211 drivers/net/ethernet/cavium/thunder/nicvf_queues.h void *base; base 578 drivers/net/ethernet/chelsio/cxgb/cxgb2.c cmd->base.speed = p->link_config.speed; base 579 drivers/net/ethernet/chelsio/cxgb/cxgb2.c cmd->base.duplex = p->link_config.duplex; base 581 drivers/net/ethernet/chelsio/cxgb/cxgb2.c cmd->base.speed = SPEED_UNKNOWN; base 582 drivers/net/ethernet/chelsio/cxgb/cxgb2.c cmd->base.duplex = DUPLEX_UNKNOWN; base 585 drivers/net/ethernet/chelsio/cxgb/cxgb2.c cmd->base.port = (supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE; base 586 drivers/net/ethernet/chelsio/cxgb/cxgb2.c cmd->base.phy_address = p->phy->mdio.prtad; base 587 drivers/net/ethernet/chelsio/cxgb/cxgb2.c cmd->base.autoneg = p->link_config.autoneg; base 646 drivers/net/ethernet/chelsio/cxgb/cxgb2.c if (cmd->base.autoneg == AUTONEG_DISABLE) { base 647 drivers/net/ethernet/chelsio/cxgb/cxgb2.c u32 speed = cmd->base.speed; base 648 drivers/net/ethernet/chelsio/cxgb/cxgb2.c int cap = speed_duplex_to_caps(speed, cmd->base.duplex); base 653 drivers/net/ethernet/chelsio/cxgb/cxgb2.c lc->requested_duplex = cmd->base.duplex; base 666 drivers/net/ethernet/chelsio/cxgb/cxgb2.c lc->autoneg = cmd->base.autoneg; base 69 drivers/net/ethernet/chelsio/cxgb3/cxgb3_ctl_defs.h unsigned int base; /* first TID */ base 1816 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c cmd->base.speed = p->link_config.speed; base 1817 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c cmd->base.duplex = p->link_config.duplex; base 1819 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c cmd->base.speed = SPEED_UNKNOWN; base 1820 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c cmd->base.duplex = DUPLEX_UNKNOWN; base 1826 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c cmd->base.port = (supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE; base 1827 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c cmd->base.phy_address = p->phy.mdio.prtad; base 1828 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c cmd->base.autoneg = p->link_config.autoneg; base 1882 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c if (cmd->base.autoneg == AUTONEG_DISABLE) { base 1883 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c u32 speed = cmd->base.speed; base 1884 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c int cap = speed_duplex_to_caps(speed, cmd->base.duplex); base 1891 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c if (cmd->base.autoneg == AUTONEG_DISABLE) { base 1892 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c u32 speed = cmd->base.speed; base 1893 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c int cap = speed_duplex_to_caps(speed, cmd->base.duplex); base 1898 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c lc->requested_duplex = cmd->base.duplex; base 1909 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c lc->autoneg = cmd->base.autoneg; base 400 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c tid->base = 0; base 405 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c tid->base = t3_mc5_size(&adapter->mc5) - tid->num - base 1247 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c stid_range.num, ATID_BASE, stid_range.base); base 618 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c unsigned int base = adapter->params.pci.vpd_cap_addr; base 623 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pci_write_config_word(adapter->pdev, base + PCI_VPD_ADDR, addr); base 626 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val); base 633 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pci_read_config_dword(adapter->pdev, base + PCI_VPD_DATA, &v); base 651 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c unsigned int base = adapter->params.pci.vpd_cap_addr; base 656 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pci_write_config_dword(adapter->pdev, base + PCI_VPD_DATA, base 658 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pci_write_config_word(adapter->pdev,base + PCI_VPD_ADDR, base 662 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val); base 684 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c static int vpdstrtouint(char *s, u8 len, unsigned int base, unsigned int *val) base 690 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c return kstrtouint(strim(tok), base, val); base 693 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c static int vpdstrtou16(char *s, u8 len, unsigned int base, u16 *val) base 699 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c return kstrtou16(strim(tok), base, val); base 26 drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; base 106 drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h u32 base; base 125 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c return ((const struct cudbg_mem_desc *)a)->base - base 126 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c ((const struct cudbg_mem_desc *)b)->base; base 153 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base = base 156 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base + base 164 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base = base 167 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base + base 176 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base = base 179 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base + base 187 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base = base 190 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base + base 198 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base = base 201 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base + base 209 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base = base 212 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[i].base + base 225 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A); base 226 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A); base 227 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A); base 228 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A); base 229 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A); base 230 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A); base 231 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A); base 232 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A); base 233 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A); base 236 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A); base 237 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->limit = md->base - 1 + base 242 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A); base 243 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->limit = md->base - 1 + base 251 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A); base 254 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = t4_read_reg(padap, base 259 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = 0; base 265 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\ base 278 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = 0; base 293 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = BASEADDR_G(t4_read_reg(padap, base 295 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->limit = md->base + (size << 2) - 1; base 301 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A); base 304 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A); base 308 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = padap->vres.ocq.start; base 310 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->limit = md->base + padap->vres.ocq.size - 1; base 318 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo_buff->avail[n + 1].base) base 319 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->base = meminfo_buff->avail[n].limit; base 322 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->base = meminfo_buff->avail[n].limit; base 559 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size, base 804 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo->mem[i + 1].base - 1 : ~0; base 808 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c if (meminfo->mem[i].base < meminfo->avail[mc].base && base 809 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c meminfo->mem[i].limit < meminfo->avail[mc].base) base 812 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c if (meminfo->mem[i].base > meminfo->avail[mc].limit) base 841 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c if (*out_base < meminfo->avail[mc_idx].base) base 844 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c *out_base -= meminfo->avail[mc_idx].base; base 849 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c *out_end -= meminfo->avail[mc_idx].base; base 875 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c payload->start = mem_desc.base; base 1082 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c mem_info.avail[mc_idx].base; base 1866 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c &mem_desc.base, base 1873 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c ctx_info[i].start = mem_desc.base; base 3063 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c u32 base; base 3095 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c base = urxq->nrxq; base 3097 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c QDESC_GET_RXQ(&urxq->uldrxq[base + i].rspq, base 1721 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); base 335 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; base 362 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c t4_read_cimq_cfg(adap, base, size, thres); base 368 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c qname[i], base[i], size[i], thres[i], base 374 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c qname[i], base[i], size[i], base 375 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c QUERDADDR_G(p[0]) & 0x3fff, wr[0] - base[i], base 3285 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c meminfo.avail[i].base, base 3295 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c meminfo.mem[i + 1].base - 1 : ~0; base 3297 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c meminfo.mem[i].base, meminfo.mem[i].limit); base 596 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c struct ethtool_link_settings *base = &link_ksettings->base; base 609 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c base->port = from_fw_port_mod_type(pi->port_type, pi->mod_type); base 612 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c base->phy_address = pi->mdio_addr; base 613 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c base->mdio_support = (pi->port_type == FW_PORT_TYPE_BT_SGMII base 617 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c base->phy_address = 255; base 618 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c base->mdio_support = 0; base 631 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c base->speed = (netif_carrier_ok(dev) base 634 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c base->duplex = DUPLEX_FULL; base 636 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c base->autoneg = pi->link_cfg.autoneg; base 652 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c const struct ethtool_link_settings *base = &link_ksettings->base; base 658 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c if (base->duplex != DUPLEX_FULL) base 663 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c base->autoneg == AUTONEG_DISABLE) { base 664 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c fw_caps = speed_to_fw_caps(base->speed); base 680 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c lc->autoneg = base->autoneg; base 9720 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) base 9731 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c *base++ = CIMQBASE_G(v) * 256; base 9740 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c *base++ = CIMQBASE_G(v) * 256; base 963 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h u8 base; base 1442 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c struct ethtool_link_settings *base = &link_ksettings->base; base 1455 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c base->port = from_fw_port_mod_type(pi->port_type, pi->mod_type); base 1458 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c base->phy_address = pi->mdio_addr; base 1459 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c base->mdio_support = (pi->port_type == FW_PORT_TYPE_BT_SGMII base 1463 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c base->phy_address = 255; base 1464 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c base->mdio_support = 0; base 1475 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c base->speed = pi->link_cfg.speed; base 1476 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c base->duplex = DUPLEX_FULL; base 1478 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c base->speed = SPEED_UNKNOWN; base 1479 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c base->duplex = DUPLEX_UNKNOWN; base 1482 drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c base->autoneg = pi->link_cfg.autoneg; base 122 drivers/net/ethernet/chelsio/libcxgb/libcxgb_ppm.h unsigned int base; /* base index */ base 111 drivers/net/ethernet/cisco/enic/enic_ethtool.c struct ethtool_link_settings *base = &ecmd->base; base 119 drivers/net/ethernet/cisco/enic/enic_ethtool.c base->port = PORT_FIBRE; base 122 drivers/net/ethernet/cisco/enic/enic_ethtool.c base->speed = vnic_dev_port_speed(enic->vdev); base 123 drivers/net/ethernet/cisco/enic/enic_ethtool.c base->duplex = DUPLEX_FULL; base 125 drivers/net/ethernet/cisco/enic/enic_ethtool.c base->speed = SPEED_UNKNOWN; base 126 drivers/net/ethernet/cisco/enic/enic_ethtool.c base->duplex = DUPLEX_UNKNOWN; base 129 drivers/net/ethernet/cisco/enic/enic_ethtool.c base->autoneg = AUTONEG_DISABLE; base 151 drivers/net/ethernet/cortina/gemini.c void __iomem *base; base 711 drivers/net/ethernet/cortina/gemini.c qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id); base 770 drivers/net/ethernet/cortina/gemini.c qhdr = geth->base + base 888 drivers/net/ethernet/cortina/gemini.c rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG); base 922 drivers/net/ethernet/cortina/gemini.c writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); base 966 drivers/net/ethernet/cortina/gemini.c qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG); base 968 drivers/net/ethernet/cortina/gemini.c writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG); base 971 drivers/net/ethernet/cortina/gemini.c writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG); base 973 drivers/net/ethernet/cortina/gemini.c geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); base 1010 drivers/net/ethernet/cortina/gemini.c writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG), base 1011 drivers/net/ethernet/cortina/gemini.c geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); base 1012 drivers/net/ethernet/cortina/gemini.c writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); base 1085 drivers/net/ethernet/cortina/gemini.c en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); base 1087 drivers/net/ethernet/cortina/gemini.c writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); base 1104 drivers/net/ethernet/cortina/gemini.c writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); base 1122 drivers/net/ethernet/cortina/gemini.c writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); base 1124 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); base 1126 drivers/net/ethernet/cortina/gemini.c writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); base 1319 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); base 1321 drivers/net/ethernet/cortina/gemini.c writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); base 1324 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); base 1326 drivers/net/ethernet/cortina/gemini.c writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); base 1329 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); base 1331 drivers/net/ethernet/cortina/gemini.c writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); base 1348 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); base 1350 drivers/net/ethernet/cortina/gemini.c writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); base 1418 drivers/net/ethernet/cortina/gemini.c geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); base 1544 drivers/net/ethernet/cortina/gemini.c reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); base 1545 drivers/net/ethernet/cortina/gemini.c reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); base 1546 drivers/net/ethernet/cortina/gemini.c reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG); base 1547 drivers/net/ethernet/cortina/gemini.c reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG); base 1548 drivers/net/ethernet/cortina/gemini.c reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); base 1553 drivers/net/ethernet/cortina/gemini.c reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); base 1554 drivers/net/ethernet/cortina/gemini.c reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); base 1555 drivers/net/ethernet/cortina/gemini.c reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG); base 1556 drivers/net/ethernet/cortina/gemini.c reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG); base 1557 drivers/net/ethernet/cortina/gemini.c reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); base 1594 drivers/net/ethernet/cortina/gemini.c ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG; base 1599 drivers/net/ethernet/cortina/gemini.c ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG; base 1632 drivers/net/ethernet/cortina/gemini.c geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); base 1654 drivers/net/ethernet/cortina/gemini.c irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs; base 1655 drivers/net/ethernet/cortina/gemini.c irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs; base 1722 drivers/net/ethernet/cortina/gemini.c geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); base 2257 drivers/net/ethernet/cortina/gemini.c writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); base 2259 drivers/net/ethernet/cortina/gemini.c irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); base 2260 drivers/net/ethernet/cortina/gemini.c writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); base 2276 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); base 2277 drivers/net/ethernet/cortina/gemini.c en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); base 2286 drivers/net/ethernet/cortina/gemini.c writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); base 2313 drivers/net/ethernet/cortina/gemini.c writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); base 2314 drivers/net/ethernet/cortina/gemini.c writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); base 2315 drivers/net/ethernet/cortina/gemini.c writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG); base 2316 drivers/net/ethernet/cortina/gemini.c writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG); base 2317 drivers/net/ethernet/cortina/gemini.c writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); base 2329 drivers/net/ethernet/cortina/gemini.c writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG); base 2330 drivers/net/ethernet/cortina/gemini.c writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG); base 2331 drivers/net/ethernet/cortina/gemini.c writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG); base 2332 drivers/net/ethernet/cortina/gemini.c writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG); base 2333 drivers/net/ethernet/cortina/gemini.c writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG); base 2336 drivers/net/ethernet/cortina/gemini.c writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); base 2337 drivers/net/ethernet/cortina/gemini.c writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); base 2338 drivers/net/ethernet/cortina/gemini.c writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG); base 2339 drivers/net/ethernet/cortina/gemini.c writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG); base 2340 drivers/net/ethernet/cortina/gemini.c writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); base 2343 drivers/net/ethernet/cortina/gemini.c writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); base 2344 drivers/net/ethernet/cortina/gemini.c writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG); base 2345 drivers/net/ethernet/cortina/gemini.c writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG); base 2346 drivers/net/ethernet/cortina/gemini.c writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG); base 2565 drivers/net/ethernet/cortina/gemini.c geth->base = devm_ioremap_resource(dev, res); base 2566 drivers/net/ethernet/cortina/gemini.c if (IS_ERR(geth->base)) base 2567 drivers/net/ethernet/cortina/gemini.c return PTR_ERR(geth->base); base 2573 drivers/net/ethernet/cortina/gemini.c val = readl(geth->base + GLOBAL_TOE_VERSION_REG); base 1491 drivers/net/ethernet/dec/tulip/de2104x.c cmd->base.phy_address = 0; base 1497 drivers/net/ethernet/dec/tulip/de2104x.c cmd->base.port = PORT_AUI; base 1500 drivers/net/ethernet/dec/tulip/de2104x.c cmd->base.port = PORT_BNC; base 1503 drivers/net/ethernet/dec/tulip/de2104x.c cmd->base.port = PORT_TP; base 1507 drivers/net/ethernet/dec/tulip/de2104x.c cmd->base.speed = 10; base 1510 drivers/net/ethernet/dec/tulip/de2104x.c cmd->base.duplex = DUPLEX_FULL; base 1512 drivers/net/ethernet/dec/tulip/de2104x.c cmd->base.duplex = DUPLEX_HALF; base 1515 drivers/net/ethernet/dec/tulip/de2104x.c cmd->base.autoneg = AUTONEG_DISABLE; base 1517 drivers/net/ethernet/dec/tulip/de2104x.c cmd->base.autoneg = AUTONEG_ENABLE; base 1527 drivers/net/ethernet/dec/tulip/de2104x.c u8 duplex = cmd->base.duplex; base 1528 drivers/net/ethernet/dec/tulip/de2104x.c u8 port = cmd->base.port; base 1529 drivers/net/ethernet/dec/tulip/de2104x.c u8 autoneg = cmd->base.autoneg; base 1535 drivers/net/ethernet/dec/tulip/de2104x.c if (cmd->base.speed != 10) base 943 drivers/net/ethernet/dec/tulip/uli526x.c cmd->base.port = PORT_MII; base 944 drivers/net/ethernet/dec/tulip/uli526x.c cmd->base.phy_address = db->phy_addr; base 946 drivers/net/ethernet/dec/tulip/uli526x.c cmd->base.speed = SPEED_10; base 947 drivers/net/ethernet/dec/tulip/uli526x.c cmd->base.duplex = DUPLEX_HALF; base 951 drivers/net/ethernet/dec/tulip/uli526x.c cmd->base.speed = SPEED_100; base 955 drivers/net/ethernet/dec/tulip/uli526x.c cmd->base.duplex = DUPLEX_FULL; base 959 drivers/net/ethernet/dec/tulip/uli526x.c cmd->base.speed = SPEED_UNKNOWN; base 960 drivers/net/ethernet/dec/tulip/uli526x.c cmd->base.duplex = DUPLEX_UNKNOWN; base 965 drivers/net/ethernet/dec/tulip/uli526x.c cmd->base.autoneg = AUTONEG_ENABLE; base 1261 drivers/net/ethernet/dlink/dl2k.c cmd->base.port = PORT_FIBRE; base 1272 drivers/net/ethernet/dlink/dl2k.c cmd->base.port = PORT_MII; base 1275 drivers/net/ethernet/dlink/dl2k.c cmd->base.speed = np->speed; base 1276 drivers/net/ethernet/dlink/dl2k.c cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; base 1278 drivers/net/ethernet/dlink/dl2k.c cmd->base.speed = SPEED_UNKNOWN; base 1279 drivers/net/ethernet/dlink/dl2k.c cmd->base.duplex = DUPLEX_UNKNOWN; base 1282 drivers/net/ethernet/dlink/dl2k.c cmd->base.autoneg = AUTONEG_ENABLE; base 1284 drivers/net/ethernet/dlink/dl2k.c cmd->base.autoneg = AUTONEG_DISABLE; base 1286 drivers/net/ethernet/dlink/dl2k.c cmd->base.phy_address = np->phy_addr; base 1300 drivers/net/ethernet/dlink/dl2k.c u32 speed = cmd->base.speed; base 1301 drivers/net/ethernet/dlink/dl2k.c u8 duplex = cmd->base.duplex; base 1304 drivers/net/ethernet/dlink/dl2k.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 417 drivers/net/ethernet/dlink/sundance.c void __iomem *base; base 456 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base + ASICCtrl; base 549 drivers/net/ethernet/dlink/sundance.c np->base = ioaddr; base 775 drivers/net/ethernet/dlink/sundance.c void __iomem *mdio_addr = np->base + MIICtrl; base 805 drivers/net/ethernet/dlink/sundance.c void __iomem *mdio_addr = np->base + MIICtrl; base 851 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 929 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 958 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 975 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 998 drivers/net/ethernet/dlink/sundance.c ioread32(np->base + TxListPtr), base 1093 drivers/net/ethernet/dlink/sundance.c if (ioread32 (np->base + TxListPtr) == 0) base 1095 drivers/net/ethernet/dlink/sundance.c np->base + TxListPtr); base 1151 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 1189 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 1336 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 1462 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 1527 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 1569 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 1613 drivers/net/ethernet/dlink/sundance.c iowrite16(addr16, np->base + StationAddr); base 1615 drivers/net/ethernet/dlink/sundance.c iowrite16(addr16, np->base + StationAddr+2); base 1617 drivers/net/ethernet/dlink/sundance.c iowrite16(addr16, np->base + StationAddr+4); base 1751 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 1771 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 1833 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 1941 drivers/net/ethernet/dlink/sundance.c pci_iounmap(pdev, np->base); base 1953 drivers/net/ethernet/dlink/sundance.c void __iomem *ioaddr = np->base; base 377 drivers/net/ethernet/emulex/benet/be_ethtool.c unsigned int i, j, base = 0, start; base 383 drivers/net/ethernet/emulex/benet/be_ethtool.c base += ETHTOOL_STATS_NUM; base 390 drivers/net/ethernet/emulex/benet/be_ethtool.c data[base] = stats->rx_bytes; base 391 drivers/net/ethernet/emulex/benet/be_ethtool.c data[base + 1] = stats->rx_pkts; base 396 drivers/net/ethernet/emulex/benet/be_ethtool.c data[base + i] = *(u32 *)p; base 398 drivers/net/ethernet/emulex/benet/be_ethtool.c base += ETHTOOL_RXSTATS_NUM; base 406 drivers/net/ethernet/emulex/benet/be_ethtool.c data[base] = stats->tx_compl; base 413 drivers/net/ethernet/emulex/benet/be_ethtool.c data[base + i] = base 418 drivers/net/ethernet/emulex/benet/be_ethtool.c base += ETHTOOL_TXSTATS_NUM; base 624 drivers/net/ethernet/emulex/benet/be_ethtool.c cmd->base.speed = link_speed; base 640 drivers/net/ethernet/emulex/benet/be_ethtool.c cmd->base.port = be_get_port_type(adapter); base 644 drivers/net/ethernet/emulex/benet/be_ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 652 drivers/net/ethernet/emulex/benet/be_ethtool.c cmd->base.port = PORT_OTHER; base 653 drivers/net/ethernet/emulex/benet/be_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 657 drivers/net/ethernet/emulex/benet/be_ethtool.c adapter->phy.link_speed = cmd->base.speed; base 658 drivers/net/ethernet/emulex/benet/be_ethtool.c adapter->phy.port_type = cmd->base.port; base 659 drivers/net/ethernet/emulex/benet/be_ethtool.c adapter->phy.autoneg = cmd->base.autoneg; base 663 drivers/net/ethernet/emulex/benet/be_ethtool.c cmd->base.speed = adapter->phy.link_speed; base 664 drivers/net/ethernet/emulex/benet/be_ethtool.c cmd->base.port = adapter->phy.port_type; base 665 drivers/net/ethernet/emulex/benet/be_ethtool.c cmd->base.autoneg = adapter->phy.autoneg; base 670 drivers/net/ethernet/emulex/benet/be_ethtool.c cmd->base.duplex = netif_carrier_ok(netdev) ? base 672 drivers/net/ethernet/emulex/benet/be_ethtool.c cmd->base.phy_address = adapter->port_num; base 57 drivers/net/ethernet/faraday/ftgmac100.c void __iomem *base; base 118 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); base 120 drivers/net/ethernet/faraday/ftgmac100.c priv->base + FTGMAC100_OFFSET_MACCR); base 124 drivers/net/ethernet/faraday/ftgmac100.c maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); base 174 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); base 175 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); base 193 drivers/net/ethernet/faraday/ftgmac100.c m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR); base 194 drivers/net/ethernet/faraday/ftgmac100.c l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR); base 241 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR); base 249 drivers/net/ethernet/faraday/ftgmac100.c reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR); base 250 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR); base 253 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR); base 256 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); base 260 drivers/net/ethernet/faraday/ftgmac100.c priv->base + FTGMAC100_OFFSET_RBSR); base 264 drivers/net/ethernet/faraday/ftgmac100.c priv->base + FTGMAC100_OFFSET_APTC); base 270 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); base 271 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); base 285 drivers/net/ethernet/faraday/ftgmac100.c priv->base + FTGMAC100_OFFSET_DBLAC); base 293 drivers/net/ethernet/faraday/ftgmac100.c priv->base + FTGMAC100_OFFSET_ITC); base 296 drivers/net/ethernet/faraday/ftgmac100.c reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR); base 299 drivers/net/ethernet/faraday/ftgmac100.c reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR); base 303 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR); base 308 drivers/net/ethernet/faraday/ftgmac100.c u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); base 338 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); base 343 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); base 375 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0); base 376 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1); base 823 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); base 1039 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); base 1082 drivers/net/ethernet/faraday/ftgmac100.c phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); base 1091 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); base 1094 drivers/net/ethernet/faraday/ftgmac100.c phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); base 1099 drivers/net/ethernet/faraday/ftgmac100.c data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); base 1119 drivers/net/ethernet/faraday/ftgmac100.c phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); base 1130 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); base 1131 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); base 1134 drivers/net/ethernet/faraday/ftgmac100.c phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); base 1237 drivers/net/ethernet/faraday/ftgmac100.c status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); base 1238 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); base 1258 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); base 1273 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER); base 1313 drivers/net/ethernet/faraday/ftgmac100.c priv->base + FTGMAC100_OFFSET_IER); base 1329 drivers/net/ethernet/faraday/ftgmac100.c priv->base + FTGMAC100_OFFSET_ISR); base 1334 drivers/net/ethernet/faraday/ftgmac100.c ioread32(priv->base + FTGMAC100_OFFSET_ISR); base 1346 drivers/net/ethernet/faraday/ftgmac100.c priv->base + FTGMAC100_OFFSET_IER); base 1374 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER); base 1500 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); base 1518 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); base 1550 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); base 1569 drivers/net/ethernet/faraday/ftgmac100.c maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); base 1574 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); base 1629 drivers/net/ethernet/faraday/ftgmac100.c reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR); base 1631 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR); base 1786 drivers/net/ethernet/faraday/ftgmac100.c priv->base = ioremap(res->start, resource_size(res)); base 1787 drivers/net/ethernet/faraday/ftgmac100.c if (!priv->base) { base 1884 drivers/net/ethernet/faraday/ftgmac100.c netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base); base 1892 drivers/net/ethernet/faraday/ftgmac100.c iounmap(priv->base); base 1920 drivers/net/ethernet/faraday/ftgmac100.c iounmap(priv->base); base 52 drivers/net/ethernet/faraday/ftmac100.c void __iomem *base; base 90 drivers/net/ethernet/faraday/ftmac100.c iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTMAC100_OFFSET_IMR); base 95 drivers/net/ethernet/faraday/ftmac100.c iowrite32(INT_MASK_ALL_DISABLED, priv->base + FTMAC100_OFFSET_IMR); base 100 drivers/net/ethernet/faraday/ftmac100.c iowrite32(addr, priv->base + FTMAC100_OFFSET_RXR_BADR); base 105 drivers/net/ethernet/faraday/ftmac100.c iowrite32(addr, priv->base + FTMAC100_OFFSET_TXR_BADR); base 110 drivers/net/ethernet/faraday/ftmac100.c iowrite32(1, priv->base + FTMAC100_OFFSET_TXPD); base 119 drivers/net/ethernet/faraday/ftmac100.c iowrite32(FTMAC100_MACCR_SW_RST, priv->base + FTMAC100_OFFSET_MACCR); base 124 drivers/net/ethernet/faraday/ftmac100.c maccr = ioread32(priv->base + FTMAC100_OFFSET_MACCR); base 147 drivers/net/ethernet/faraday/ftmac100.c iowrite32(maddr, priv->base + FTMAC100_OFFSET_MAC_MADR); base 148 drivers/net/ethernet/faraday/ftmac100.c iowrite32(laddr, priv->base + FTMAC100_OFFSET_MAC_LADR); base 175 drivers/net/ethernet/faraday/ftmac100.c iowrite32(FTMAC100_APTC_RXPOLL_CNT(1), priv->base + FTMAC100_OFFSET_APTC); base 179 drivers/net/ethernet/faraday/ftmac100.c iowrite32(MACCR_ENABLE_ALL, priv->base + FTMAC100_OFFSET_MACCR); base 185 drivers/net/ethernet/faraday/ftmac100.c iowrite32(0, priv->base + FTMAC100_OFFSET_MACCR); base 762 drivers/net/ethernet/faraday/ftmac100.c iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR); base 765 drivers/net/ethernet/faraday/ftmac100.c phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR); base 790 drivers/net/ethernet/faraday/ftmac100.c iowrite32(data, priv->base + FTMAC100_OFFSET_PHYWDATA); base 791 drivers/net/ethernet/faraday/ftmac100.c iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR); base 794 drivers/net/ethernet/faraday/ftmac100.c phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR); base 880 drivers/net/ethernet/faraday/ftmac100.c status = ioread32(priv->base + FTMAC100_OFFSET_ISR); base 1105 drivers/net/ethernet/faraday/ftmac100.c priv->base = ioremap(res->start, resource_size(res)); base 1106 drivers/net/ethernet/faraday/ftmac100.c if (!priv->base) { base 1129 drivers/net/ethernet/faraday/ftmac100.c netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base); base 1140 drivers/net/ethernet/faraday/ftmac100.c iounmap(priv->base); base 1160 drivers/net/ethernet/faraday/ftmac100.c iounmap(priv->base); base 88 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c link_settings->base.autoneg = AUTONEG_DISABLE; base 90 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c link_settings->base.duplex = DUPLEX_FULL; base 91 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c link_settings->base.speed = priv->link_state.rate; base 115 drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c void __iomem *base; base 148 drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c base = of_iomap(node, 0); base 149 drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c if (!base) { base 179 drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c err = ptp_qoriq_init(ptp_qoriq, base, &dpaa2_ptp_caps); base 193 drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c iounmap(base); base 33 drivers/net/ethernet/freescale/enetc/enetc_ptp.c void __iomem *base; base 74 drivers/net/ethernet/freescale/enetc/enetc_ptp.c base = ioremap(pci_resource_start(pdev, ENETC_BAR_REGS), len); base 75 drivers/net/ethernet/freescale/enetc/enetc_ptp.c if (!base) { base 98 drivers/net/ethernet/freescale/enetc/enetc_ptp.c err = ptp_qoriq_init(ptp_qoriq, base, &enetc_ptp_caps); base 112 drivers/net/ethernet/freescale/enetc/enetc_ptp.c iounmap(base); base 463 drivers/net/ethernet/freescale/fec.h struct bufdesc *base; base 288 drivers/net/ethernet/freescale/fec_main.c return (bdp >= bd->last) ? bd->base base 295 drivers/net/ethernet/freescale/fec_main.c return (bdp <= bd->base) ? bd->last base 302 drivers/net/ethernet/freescale/fec_main.c return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; base 345 drivers/net/ethernet/freescale/fec_main.c bdp = txq->bd.base; base 358 drivers/net/ethernet/freescale/fec_main.c } while (bdp != txq->bd.base); base 839 drivers/net/ethernet/freescale/fec_main.c bdp = rxq->bd.base; base 855 drivers/net/ethernet/freescale/fec_main.c rxq->bd.cur = rxq->bd.base; base 861 drivers/net/ethernet/freescale/fec_main.c bdp = txq->bd.base; base 2754 drivers/net/ethernet/freescale/fec_main.c bdp = rxq->bd.base; base 2771 drivers/net/ethernet/freescale/fec_main.c bdp = txq->bd.base; base 2863 drivers/net/ethernet/freescale/fec_main.c bdp = rxq->bd.base; base 2904 drivers/net/ethernet/freescale/fec_main.c bdp = txq->bd.base; base 3278 drivers/net/ethernet/freescale/fec_main.c rxq->bd.base = cbd_base; base 3294 drivers/net/ethernet/freescale/fec_main.c txq->bd.base = cbd_base; base 65 drivers/net/ethernet/freescale/fman/fman_muram.c struct muram_info *fman_muram_init(phys_addr_t base, size_t size) base 81 drivers/net/ethernet/freescale/fman/fman_muram.c vaddr = ioremap(base, size); base 88 drivers/net/ethernet/freescale/fman/fman_muram.c base, size, -1); base 98 drivers/net/ethernet/freescale/fman/fman_muram.c muram->pbase = base; base 42 drivers/net/ethernet/freescale/fman/fman_muram.h struct muram_info *fman_muram_init(phys_addr_t base, size_t size); base 1759 drivers/net/ethernet/freescale/gianfar.c struct txbd8 *base, int ring_size) base 1763 drivers/net/ethernet/freescale/gianfar.c return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; base 1766 drivers/net/ethernet/freescale/gianfar.c static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, base 1769 drivers/net/ethernet/freescale/gianfar.c return skip_txbd(bdp, 1, base, ring_size); base 1800 drivers/net/ethernet/freescale/gianfar.c struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; base 1811 drivers/net/ethernet/freescale/gianfar.c base = tx_queue->tx_bd_base; base 1913 drivers/net/ethernet/freescale/gianfar.c txbdp_tstamp = txbdp = next_txbd(txbdp, base, base 1928 drivers/net/ethernet/freescale/gianfar.c txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); base 1995 drivers/net/ethernet/freescale/gianfar.c tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); base 2022 drivers/net/ethernet/freescale/gianfar.c txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size); base 2024 drivers/net/ethernet/freescale/gianfar.c txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); base 2035 drivers/net/ethernet/freescale/gianfar.c txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); base 2190 drivers/net/ethernet/freescale/gianfar.c struct txbd8 *base = tx_queue->tx_bd_base; base 2222 drivers/net/ethernet/freescale/gianfar.c lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); base 2232 drivers/net/ethernet/freescale/gianfar.c next = next_txbd(bdp, base, tx_ring_size); base 2255 drivers/net/ethernet/freescale/gianfar.c bdp = next_txbd(bdp, base, tx_ring_size); base 2262 drivers/net/ethernet/freescale/gianfar.c bdp = next_txbd(bdp, base, tx_ring_size); base 307 drivers/net/ethernet/freescale/ucc_geth_ethtool.c u32 __iomem *base; base 312 drivers/net/ethernet/freescale/ucc_geth_ethtool.c base = (u32 __iomem *)&ugeth->ug_regs->tx64; base 314 drivers/net/ethernet/freescale/ucc_geth_ethtool.c base = NULL; base 317 drivers/net/ethernet/freescale/ucc_geth_ethtool.c data[j++] = base ? in_be32(&base[i]) : 0; base 320 drivers/net/ethernet/freescale/ucc_geth_ethtool.c base = (u32 __iomem *)ugeth->p_tx_fw_statistics_pram; base 322 drivers/net/ethernet/freescale/ucc_geth_ethtool.c data[j++] = base ? in_be32(&base[i]) : 0; base 325 drivers/net/ethernet/freescale/ucc_geth_ethtool.c base = (u32 __iomem *)ugeth->p_rx_fw_statistics_pram; base 327 drivers/net/ethernet/freescale/ucc_geth_ethtool.c data[j++] = base ? in_be32(&base[i]) : 0; base 117 drivers/net/ethernet/fujitsu/fmvj18x_cs.c u_char __iomem *base; base 246 drivers/net/ethernet/fujitsu/fmvj18x_cs.c lp->base = NULL; base 539 drivers/net/ethernet/fujitsu/fmvj18x_cs.c u_char __iomem *base; base 549 drivers/net/ethernet/fujitsu/fmvj18x_cs.c base = ioremap(link->resource[2]->start, resource_size(link->resource[2])); base 550 drivers/net/ethernet/fujitsu/fmvj18x_cs.c if (!base) { base 564 drivers/net/ethernet/fujitsu/fmvj18x_cs.c if (readb(base+i*2) == 0x22) { base 565 drivers/net/ethernet/fujitsu/fmvj18x_cs.c if (readb(base+(i-1)*2) == 0xff && base 566 drivers/net/ethernet/fujitsu/fmvj18x_cs.c readb(base+(i+5)*2) == 0x04 && base 567 drivers/net/ethernet/fujitsu/fmvj18x_cs.c readb(base+(i+6)*2) == 0x06 && base 568 drivers/net/ethernet/fujitsu/fmvj18x_cs.c readb(base+(i+13)*2) == 0xff) base 575 drivers/net/ethernet/fujitsu/fmvj18x_cs.c node_id[j] = readb(base+(i+7)*2); base 579 drivers/net/ethernet/fujitsu/fmvj18x_cs.c iounmap(base); base 600 drivers/net/ethernet/fujitsu/fmvj18x_cs.c lp->base = ioremap(link->resource[3]->start, base 602 drivers/net/ethernet/fujitsu/fmvj18x_cs.c if (lp->base == NULL) { base 609 drivers/net/ethernet/fujitsu/fmvj18x_cs.c iounmap(lp->base); base 610 drivers/net/ethernet/fujitsu/fmvj18x_cs.c lp->base = NULL; base 615 drivers/net/ethernet/fujitsu/fmvj18x_cs.c writeb(0x47, lp->base+0x800); /* Config Option Register of LAN */ base 616 drivers/net/ethernet/fujitsu/fmvj18x_cs.c writeb(0x0, lp->base+0x802); /* Config and Status Register */ base 618 drivers/net/ethernet/fujitsu/fmvj18x_cs.c writeb(ioaddr & 0xff, lp->base+0x80a); /* I/O Base(Low) of LAN */ base 619 drivers/net/ethernet/fujitsu/fmvj18x_cs.c writeb((ioaddr >> 8) & 0xff, lp->base+0x80c); /* I/O Base(High) of LAN */ base 621 drivers/net/ethernet/fujitsu/fmvj18x_cs.c writeb(0x45, lp->base+0x820); /* Config Option Register of Modem */ base 622 drivers/net/ethernet/fujitsu/fmvj18x_cs.c writeb(0x8, lp->base+0x822); /* Config and Status Register */ base 638 drivers/net/ethernet/fujitsu/fmvj18x_cs.c if (lp->base != NULL) { base 639 drivers/net/ethernet/fujitsu/fmvj18x_cs.c tmp = lp->base; base 640 drivers/net/ethernet/fujitsu/fmvj18x_cs.c lp->base = NULL; /* set NULL before iounmap */ base 765 drivers/net/ethernet/fujitsu/fmvj18x_cs.c if (lp->base != NULL) { base 767 drivers/net/ethernet/fujitsu/fmvj18x_cs.c writeb(0x01, lp->base+0x802); base 768 drivers/net/ethernet/fujitsu/fmvj18x_cs.c writeb(0x09, lp->base+0x822); base 104 drivers/net/ethernet/google/gve/gve.h void *base; /* address of base of FIFO */ base 31 drivers/net/ethernet/google/gve/gve_tx.c fifo->base = vmap(fifo->qpl->pages, fifo->qpl->num_entries, VM_MAP, base 33 drivers/net/ethernet/google/gve/gve_tx.c if (unlikely(!fifo->base)) { base 50 drivers/net/ethernet/google/gve/gve_tx.c vunmap(fifo->base); base 448 drivers/net/ethernet/google/gve/gve_tx.c tx->tx_fifo.base + info->iov[hdr_nfrags - 1].iov_offset, base 464 drivers/net/ethernet/google/gve/gve_tx.c tx->tx_fifo.base + info->iov[i].iov_offset, base 210 drivers/net/ethernet/hisilicon/hip04_eth.c void __iomem *base; base 284 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_PORT_MODE); base 287 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_DUPLEX_TYPE); base 290 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG); base 316 drivers/net/ethernet/hisilicon/hip04_eth.c val = readl_relaxed(priv->base + PPE_CFG_STS_MODE); base 318 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_STS_MODE); base 325 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN); base 336 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG); base 339 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG); base 342 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG); base 345 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG); base 348 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG); base 351 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG); base 353 drivers/net/ethernet/hisilicon/hip04_eth.c val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG); base 355 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG); base 358 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG); base 360 drivers/net/ethernet/hisilicon/hip04_eth.c val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG); base 362 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG); base 366 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG); base 376 drivers/net/ethernet/hisilicon/hip04_eth.c val = readl_relaxed(priv->base + GE_PORT_EN); base 378 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_PORT_EN); base 382 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_RINT); base 386 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT); base 390 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN); base 400 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN); base 403 drivers/net/ethernet/hisilicon/hip04_eth.c val = readl_relaxed(priv->base + GE_PORT_EN); base 405 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(val, priv->base + GE_PORT_EN); base 413 drivers/net/ethernet/hisilicon/hip04_eth.c writel(val, priv->base + PPE_CFG_CPU_ADD_ADDR); base 426 drivers/net/ethernet/hisilicon/hip04_eth.c return readl(priv->base + PPE_HIS_RX_PKT_CNT); base 434 drivers/net/ethernet/hisilicon/hip04_eth.c priv->base + GE_STATION_MAC_ADDRESS); base 437 drivers/net/ethernet/hisilicon/hip04_eth.c priv->base + GE_STATION_MAC_ADDRESS + 4); base 562 drivers/net/ethernet/hisilicon/hip04_eth.c priv->base + PPE_INTEN); base 650 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN); base 666 drivers/net/ethernet/hisilicon/hip04_eth.c u32 ists = readl_relaxed(priv->base + PPE_INTSTS); base 671 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT); base 688 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN); base 705 drivers/net/ethernet/hisilicon/hip04_eth.c writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN); base 921 drivers/net/ethernet/hisilicon/hip04_eth.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 922 drivers/net/ethernet/hisilicon/hip04_eth.c if (IS_ERR(priv->base)) { base 923 drivers/net/ethernet/hisilicon/hip04_eth.c ret = PTR_ERR(priv->base); base 248 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c void __iomem *base; base 318 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); base 325 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(val, priv->base + PORT_MODE); base 326 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + MODE_CHANGE_EN); base 327 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); base 332 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); base 333 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); base 334 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + RX_FQ_REG_EN); base 336 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); base 337 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH); base 338 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + RX_BQ_REG_EN); base 340 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN); base 341 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH); base 342 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + TX_BQ_REG_EN); base 344 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN); base 345 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH); base 346 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + TX_RQ_REG_EN); base 351 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN); base 352 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR); base 353 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + RX_FQ_REG_EN); base 358 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN); base 359 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR); base 360 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + RX_BQ_REG_EN); base 365 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN); base 366 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR); base 367 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + TX_BQ_REG_EN); base 372 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN); base 373 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR); base 374 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + TX_RQ_REG_EN); base 390 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + ENA_PMU_INT); base 391 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(~0, priv->base + RAW_PMU_INT); base 393 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL); base 394 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD); base 395 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + COL_SLOT_TIME); base 398 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(val, priv->base + IN_QUEUE_TH); base 400 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH); base 401 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH); base 409 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT); base 414 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + ENA_PMU_INT); base 419 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA); base 420 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN); base 425 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(~(u32)(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN); base 426 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(0, priv->base + DESC_WR_RD_ENA); base 436 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(val, priv->base + STATION_ADDR_HIGH); base 439 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(val, priv->base + STATION_ADDR_LOW); base 473 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c start = dma_cnt(readl_relaxed(priv->base + RX_FQ_WR_ADDR)); base 475 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c end = dma_cnt(readl_relaxed(priv->base + RX_FQ_RD_ADDR)); base 505 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR); base 517 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c start = dma_cnt(readl_relaxed(priv->base + RX_BQ_RD_ADDR)); base 519 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c end = dma_cnt(readl_relaxed(priv->base + RX_BQ_WR_ADDR)); base 559 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR); base 599 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c start = dma_cnt(readl_relaxed(priv->base + TX_RQ_RD_ADDR)); base 601 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c end = dma_cnt(readl_relaxed(priv->base + TX_RQ_WR_ADDR)); base 629 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR); base 656 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c ints = readl_relaxed(priv->base + RAW_PMU_INT); base 657 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(ints, priv->base + RAW_PMU_INT); base 672 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c int ints = readl_relaxed(priv->base + RAW_PMU_INT); base 674 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(ints, priv->base + RAW_PMU_INT); base 745 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c pos = dma_cnt(readl_relaxed(priv->base + TX_BQ_WR_ADDR)); base 783 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR); base 920 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c void __iomem *base = priv->base; base 923 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) { base 935 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c void __iomem *base = priv->base; base 942 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD); base 947 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = readl_relaxed(base + MDIO_RDATA_STATUS); base 954 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c val = readl_relaxed(priv->base + MDIO_SINGLE_DATA); base 963 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c void __iomem *base = priv->base; base 970 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(val, base + MDIO_SINGLE_DATA); base 971 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD); base 1121 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 1122 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c if (IS_ERR(priv->base)) { base 1123 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c ret = PTR_ERR(priv->base); base 972 drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c u8 __iomem *base = dsaf_dev->io_base; base 976 drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c return base + 0x40000 + mac_id * 0x4000 - base 508 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c #define RCB_COMM_BASE_TO_RING_BASE(base, ringid)\ base 509 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c ((base) + 0x10000 + HNS_RCB_REG_OFFSET * (ringid)) base 1017 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline void dsaf_write_reg(u8 __iomem *base, u32 reg, u32 value) base 1019 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h writel(value, base + reg); base 1025 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline u32 dsaf_read_reg(u8 __iomem *base, u32 reg) base 1027 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h return readl(base + reg); base 1030 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline void dsaf_write_syscon(struct regmap *base, u32 reg, u32 value) base 1032 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h regmap_write(base, reg, value); base 1035 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline int dsaf_read_syscon(struct regmap *base, u32 reg, u32 *val) base 1037 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h return regmap_read(base, reg, val); base 1052 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline void dsaf_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, base 1055 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h u32 origin = dsaf_read_reg(base, reg); base 1058 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_write_reg(base, reg, origin); base 1072 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline u32 dsaf_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, base 1077 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h origin = dsaf_read_reg(base, reg); base 69 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_INVALID; base 70 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; base 87 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI; base 90 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_X; base 93 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; base 96 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_INVALID; base 101 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; base 103 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.eth_tp_mdix = ETH_TP_MDI_X; base 105 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.eth_tp_mdix = ETH_TP_MDI; base 144 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.autoneg = false; base 145 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.speed = speed; base 146 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.duplex = duplex; base 153 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.speed = (u32)SPEED_UNKNOWN; base 154 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 157 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c if (cmd->base.autoneg) base 171 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.port = PORT_FIBRE; base 174 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.port = PORT_TP; base 189 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.mdio_support = ETH_MDIO_SUPPORTS_C45 | ETH_MDIO_SUPPORTS_C22; base 216 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c speed = cmd->base.speed; base 219 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE || base 221 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.duplex != DUPLEX_FULL) base 224 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c if (!net_dev->phydev && cmd->base.autoneg == AUTONEG_ENABLE) base 227 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c if (speed == SPEED_1000 && cmd->base.duplex == DUPLEX_HALF) base 233 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c speed != SPEED_1000) || (cmd->base.duplex != DUPLEX_HALF && base 234 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c cmd->base.duplex != DUPLEX_FULL)) base 243 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c h->dev->ops->adjust_link(h, (int)speed, cmd->base.duplex); base 577 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h static inline u32 hns3_read_reg(void __iomem *base, u32 reg) base 579 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h return readl(base + reg); base 582 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) base 584 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h u8 __iomem *reg_addr = READ_ONCE(base); base 639 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c &cmd->base.autoneg, base 640 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c &cmd->base.speed, base 641 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c &cmd->base.duplex); base 651 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c ops->get_mdix_mode(h, &cmd->base.eth_tp_mdix_ctrl, base 652 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c &cmd->base.eth_tp_mdix); base 672 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c cmd->base.port = PORT_NONE; base 677 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c cmd->base.port = PORT_DA; base 679 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c cmd->base.port = PORT_FIBRE; base 684 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c cmd->base.port = PORT_NONE; base 688 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c cmd->base.port = PORT_TP; base 701 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c cmd->base.mdio_support = ETH_MDIO_SUPPORTS_C22; base 705 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 706 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 727 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c if (cmd->base.autoneg) base 732 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c if (cmd->base.autoneg == autoneg && cmd->base.speed == speed && base 733 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c cmd->base.duplex == duplex) base 740 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c if (cmd->base.duplex != DUPLEX_FULL && base 748 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c ret = ops->check_port_speed(handle, cmd->base.speed); base 766 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c if (cmd->base.speed == SPEED_1000 && cmd->base.duplex == DUPLEX_HALF) base 772 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c cmd->base.autoneg, cmd->base.speed, cmd->base.duplex); base 786 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c ret = ops->set_autoneg(handle, cmd->base.autoneg); base 794 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c if (cmd->base.autoneg) { base 801 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c ret = ops->cfg_mac_speed_dup_h(handle, cmd->base.speed, base 802 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c cmd->base.duplex); base 1067 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) base 1069 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h writel(value, base + reg); base 1077 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) base 1079 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h u8 __iomem *reg_addr = READ_ONCE(base); base 256 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value) base 258 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h writel(value, base + reg); base 261 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg) base 263 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h u8 __iomem *reg_addr = READ_ONCE(base); base 95 drivers/net/ethernet/hisilicon/hns_mdio.c static void mdio_write_reg(u8 __iomem *base, u32 reg, u32 value) base 97 drivers/net/ethernet/hisilicon/hns_mdio.c writel_relaxed(value, base + reg); base 103 drivers/net/ethernet/hisilicon/hns_mdio.c static u32 mdio_read_reg(u8 __iomem *base, u32 reg) base 105 drivers/net/ethernet/hisilicon/hns_mdio.c return readl_relaxed(base + reg); base 116 drivers/net/ethernet/hisilicon/hns_mdio.c static void mdio_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift, base 119 drivers/net/ethernet/hisilicon/hns_mdio.c u32 origin = mdio_read_reg(base, reg); base 122 drivers/net/ethernet/hisilicon/hns_mdio.c mdio_write_reg(base, reg, origin); base 128 drivers/net/ethernet/hisilicon/hns_mdio.c static u32 mdio_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift) base 132 drivers/net/ethernet/hisilicon/hns_mdio.c origin = mdio_read_reg(base, reg); base 41 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.speed = SPEED_10; base 45 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.speed = SPEED_100; base 49 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.speed = SPEED_1000; base 53 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.speed = SPEED_10000; base 57 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.speed = SPEED_25000; base 61 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.speed = SPEED_40000; base 65 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.speed = SPEED_100000; base 69 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.speed = SPEED_UNKNOWN; base 87 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.speed = SPEED_UNKNOWN; base 88 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.autoneg = AUTONEG_DISABLE; base 89 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.duplex = DUPLEX_UNKNOWN; base 109 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.autoneg = AUTONEG_ENABLE; base 111 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c link_ksettings->base.duplex = (port_cap.duplex == HINIC_DUPLEX_FULL) ? base 1006 drivers/net/ethernet/i825xx/ether1.c priv(dev)->base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); base 1007 drivers/net/ethernet/i825xx/ether1.c if (!priv(dev)->base) { base 22 drivers/net/ethernet/i825xx/ether1.h #define REG_PAGE (priv(dev)->base + 0x0000) base 25 drivers/net/ethernet/i825xx/ether1.h #define REG_CONTROL (priv(dev)->base + 0x0004) base 31 drivers/net/ethernet/i825xx/ether1.h #define ETHER1_RAM (priv(dev)->base + 0x2000) base 34 drivers/net/ethernet/i825xx/ether1.h #define IDPROM_ADDRESS (priv(dev)->base + 0x0024) base 37 drivers/net/ethernet/i825xx/ether1.h void __iomem *base; base 65 drivers/net/ethernet/i825xx/sun3_82586.c #define make24(ptr32) (char *)swab32(( ((unsigned long) (ptr32)) - p->base)) base 145 drivers/net/ethernet/i825xx/sun3_82586.c unsigned long base; base 214 drivers/net/ethernet/i825xx/sun3_82586.c p->base = (unsigned long) dvma_btov(0); base 216 drivers/net/ethernet/i825xx/sun3_82586.c p->scp = (struct scp_struct *)(p->base + SCP_DEFAULT_ADDRESS); base 253 drivers/net/ethernet/i825xx/sun3_82586.c p->scp = (struct scp_struct *) (p->base + SCP_DEFAULT_ADDRESS); base 377 drivers/net/ethernet/i825xx/sun3_82586.c ((struct priv *)netdev_priv(dev))->base = (unsigned long) dvma_btov(0); base 786 drivers/net/ethernet/i825xx/sun3_82586.c skb_copy_to_linear_data(skb,(char *) p->base+swab32((unsigned long) rbd->buffer),totlen); base 51 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c cmd->base.duplex = port->full_duplex == 1 ? base 55 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 57 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c cmd->base.speed = speed; base 59 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c if (cmd->base.speed == SPEED_10000) { base 62 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c cmd->base.port = PORT_FIBRE; base 70 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c cmd->base.port = PORT_TP; base 73 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c cmd->base.autoneg = port->autoneg == 1 ? base 91 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 96 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c switch (cmd->base.speed) { base 98 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c if (cmd->base.duplex == DUPLEX_FULL) base 105 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c if (cmd->base.duplex == DUPLEX_FULL) base 112 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c if (cmd->base.duplex == DUPLEX_FULL) base 119 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c if (cmd->base.duplex == DUPLEX_FULL) base 2045 drivers/net/ethernet/ibm/emac/core.c cmd->base.port = PORT_MII; base 2046 drivers/net/ethernet/ibm/emac/core.c cmd->base.phy_address = dev->phy.address; base 2050 drivers/net/ethernet/ibm/emac/core.c cmd->base.autoneg = dev->phy.autoneg; base 2051 drivers/net/ethernet/ibm/emac/core.c cmd->base.speed = dev->phy.speed; base 2052 drivers/net/ethernet/ibm/emac/core.c cmd->base.duplex = dev->phy.duplex; base 2075 drivers/net/ethernet/ibm/emac/core.c cmd->base.autoneg, cmd->base.speed, cmd->base.duplex, advertising); base 2080 drivers/net/ethernet/ibm/emac/core.c if (cmd->base.autoneg != AUTONEG_ENABLE && base 2081 drivers/net/ethernet/ibm/emac/core.c cmd->base.autoneg != AUTONEG_DISABLE) base 2083 drivers/net/ethernet/ibm/emac/core.c if (cmd->base.autoneg == AUTONEG_ENABLE && advertising == 0) base 2085 drivers/net/ethernet/ibm/emac/core.c if (cmd->base.duplex != DUPLEX_HALF && cmd->base.duplex != DUPLEX_FULL) base 2088 drivers/net/ethernet/ibm/emac/core.c if (cmd->base.autoneg == AUTONEG_DISABLE) { base 2089 drivers/net/ethernet/ibm/emac/core.c switch (cmd->base.speed) { base 2091 drivers/net/ethernet/ibm/emac/core.c if (cmd->base.duplex == DUPLEX_HALF && base 2094 drivers/net/ethernet/ibm/emac/core.c if (cmd->base.duplex == DUPLEX_FULL && base 2099 drivers/net/ethernet/ibm/emac/core.c if (cmd->base.duplex == DUPLEX_HALF && base 2102 drivers/net/ethernet/ibm/emac/core.c if (cmd->base.duplex == DUPLEX_FULL && base 2107 drivers/net/ethernet/ibm/emac/core.c if (cmd->base.duplex == DUPLEX_HALF && base 2110 drivers/net/ethernet/ibm/emac/core.c if (cmd->base.duplex == DUPLEX_FULL && base 2119 drivers/net/ethernet/ibm/emac/core.c dev->phy.def->ops->setup_forced(&dev->phy, cmd->base.speed, base 2120 drivers/net/ethernet/ibm/emac/core.c cmd->base.duplex); base 81 drivers/net/ethernet/ibm/emac/rgmii.c struct rgmii_regs __iomem *p = dev->base; base 110 drivers/net/ethernet/ibm/emac/rgmii.c struct rgmii_regs __iomem *p = dev->base; base 134 drivers/net/ethernet/ibm/emac/rgmii.c struct rgmii_regs __iomem *p = dev->base; base 155 drivers/net/ethernet/ibm/emac/rgmii.c struct rgmii_regs __iomem *p = dev->base; base 179 drivers/net/ethernet/ibm/emac/rgmii.c p = dev->base; base 210 drivers/net/ethernet/ibm/emac/rgmii.c memcpy_fromio(regs, dev->base, sizeof(struct rgmii_regs)); base 237 drivers/net/ethernet/ibm/emac/rgmii.c dev->base = (struct rgmii_regs __iomem *)ioremap(regs.start, base 239 drivers/net/ethernet/ibm/emac/rgmii.c if (dev->base == NULL) { base 253 drivers/net/ethernet/ibm/emac/rgmii.c in_be32(&dev->base->fer), in_be32(&dev->base->ssr)); base 256 drivers/net/ethernet/ibm/emac/rgmii.c out_be32(&dev->base->fer, 0); base 280 drivers/net/ethernet/ibm/emac/rgmii.c iounmap(dev->base); base 37 drivers/net/ethernet/ibm/emac/rgmii.h struct rgmii_regs __iomem *base; base 47 drivers/net/ethernet/ibm/emac/tah.c struct tah_regs __iomem *p = dev->base; base 82 drivers/net/ethernet/ibm/emac/tah.c memcpy_fromio(regs, dev->base, sizeof(struct tah_regs)); base 108 drivers/net/ethernet/ibm/emac/tah.c dev->base = (struct tah_regs __iomem *)ioremap(regs.start, base 110 drivers/net/ethernet/ibm/emac/tah.c if (dev->base == NULL) { base 137 drivers/net/ethernet/ibm/emac/tah.c iounmap(dev->base); base 38 drivers/net/ethernet/ibm/emac/tah.h struct tah_regs __iomem *base; base 84 drivers/net/ethernet/ibm/emac/zmii.c struct zmii_regs __iomem *p = dev->base; base 156 drivers/net/ethernet/ibm/emac/zmii.c fer = in_be32(&dev->base->fer) & ~ZMII_FER_MDI_ALL; base 157 drivers/net/ethernet/ibm/emac/zmii.c out_be32(&dev->base->fer, fer | ZMII_FER_MDI(input)); base 176 drivers/net/ethernet/ibm/emac/zmii.c ssr = in_be32(&dev->base->ssr); base 185 drivers/net/ethernet/ibm/emac/zmii.c out_be32(&dev->base->ssr, ssr); base 201 drivers/net/ethernet/ibm/emac/zmii.c out_be32(&dev->base->fer, base 202 drivers/net/ethernet/ibm/emac/zmii.c in_be32(&dev->base->fer) & ~zmii_mode_mask(dev->mode, input)); base 226 drivers/net/ethernet/ibm/emac/zmii.c memcpy_fromio(regs, dev->base, sizeof(struct zmii_regs)); base 253 drivers/net/ethernet/ibm/emac/zmii.c dev->base = (struct zmii_regs __iomem *)ioremap(regs.start, base 255 drivers/net/ethernet/ibm/emac/zmii.c if (dev->base == NULL) { base 261 drivers/net/ethernet/ibm/emac/zmii.c dev->fer_save = in_be32(&dev->base->fer); base 264 drivers/net/ethernet/ibm/emac/zmii.c out_be32(&dev->base->fer, 0); base 284 drivers/net/ethernet/ibm/emac/zmii.c iounmap(dev->base); base 31 drivers/net/ethernet/ibm/emac/zmii.h struct zmii_regs __iomem *base; base 724 drivers/net/ethernet/ibm/ibmveth.c cmd->base.speed = SPEED_1000; base 725 drivers/net/ethernet/ibm/ibmveth.c cmd->base.duplex = DUPLEX_FULL; base 726 drivers/net/ethernet/ibm/ibmveth.c cmd->base.port = PORT_FIBRE; base 727 drivers/net/ethernet/ibm/ibmveth.c cmd->base.phy_address = 0; base 728 drivers/net/ethernet/ibm/ibmveth.c cmd->base.autoneg = AUTONEG_ENABLE; base 2399 drivers/net/ethernet/ibm/ibmvnic.c cmd->base.speed = adapter->speed; base 2400 drivers/net/ethernet/ibm/ibmvnic.c cmd->base.duplex = adapter->duplex; base 2401 drivers/net/ethernet/ibm/ibmvnic.c cmd->base.port = PORT_FIBRE; base 2402 drivers/net/ethernet/ibm/ibmvnic.c cmd->base.phy_address = 0; base 2403 drivers/net/ethernet/ibm/ibmvnic.c cmd->base.autoneg = AUTONEG_ENABLE; base 109 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.port = PORT_TP; base 110 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.phy_address = hw->phy_addr; base 120 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.port = PORT_FIBRE; base 126 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.speed = adapter->link_speed; base 132 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 134 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.duplex = DUPLEX_HALF; base 136 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 137 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 140 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.autoneg = ((hw->media_type == e1000_media_type_fiber) || base 146 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.eth_tp_mdix = (!!adapter->phy_info.mdix_mode ? base 149 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; base 152 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; base 154 drivers/net/ethernet/intel/e1000/e1000_ethtool.c cmd->base.eth_tp_mdix_ctrl = hw->mdix; base 178 drivers/net/ethernet/intel/e1000/e1000_ethtool.c if (cmd->base.eth_tp_mdix_ctrl) { base 182 drivers/net/ethernet/intel/e1000/e1000_ethtool.c if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && base 183 drivers/net/ethernet/intel/e1000/e1000_ethtool.c (cmd->base.autoneg != AUTONEG_ENABLE)) { base 192 drivers/net/ethernet/intel/e1000/e1000_ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 203 drivers/net/ethernet/intel/e1000/e1000_ethtool.c u32 speed = cmd->base.speed; base 205 drivers/net/ethernet/intel/e1000/e1000_ethtool.c if (e1000_set_spd_dplx(adapter, speed, cmd->base.duplex)) { base 212 drivers/net/ethernet/intel/e1000/e1000_ethtool.c if (cmd->base.eth_tp_mdix_ctrl) { base 213 drivers/net/ethernet/intel/e1000/e1000_ethtool.c if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) base 216 drivers/net/ethernet/intel/e1000/e1000_ethtool.c hw->mdix = cmd->base.eth_tp_mdix_ctrl; base 22 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \ base 23 drivers/net/ethernet/intel/e1000/e1000_osdep.h (iowrite16_rep(base + offset, data, count)) base 25 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define GBE_CONFIG_FLASH_READ(base, offset, count, data) \ base 26 drivers/net/ethernet/intel/e1000/e1000_osdep.h (ioread16_rep(base + (offset << 1), data, count)) base 128 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.port = PORT_TP; base 129 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.phy_address = hw->phy.addr; base 139 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.port = PORT_FIBRE; base 143 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 148 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.duplex = adapter->link_duplex - 1; base 162 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.duplex = DUPLEX_FULL; base 164 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.duplex = DUPLEX_HALF; base 168 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.speed = speed; base 169 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.autoneg = ((hw->phy.media_type == e1000_media_type_fiber) || base 175 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.eth_tp_mdix = hw->phy.is_mdix ? base 178 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; base 181 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; base 183 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix; base 186 drivers/net/ethernet/intel/e1000e/ethtool.c cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_INVALID; base 278 drivers/net/ethernet/intel/e1000e/ethtool.c if (cmd->base.eth_tp_mdix_ctrl) { base 284 drivers/net/ethernet/intel/e1000e/ethtool.c if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && base 285 drivers/net/ethernet/intel/e1000e/ethtool.c (cmd->base.autoneg != AUTONEG_ENABLE)) { base 295 drivers/net/ethernet/intel/e1000e/ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 307 drivers/net/ethernet/intel/e1000e/ethtool.c u32 speed = cmd->base.speed; base 309 drivers/net/ethernet/intel/e1000e/ethtool.c if (e1000_set_spd_dplx(adapter, speed, cmd->base.duplex)) { base 316 drivers/net/ethernet/intel/e1000e/ethtool.c if (cmd->base.eth_tp_mdix_ctrl) { base 320 drivers/net/ethernet/intel/e1000e/ethtool.c if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) base 323 drivers/net/ethernet/intel/e1000e/ethtool.c hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl; base 87 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 base:13; /* 0:12 Protected Range Base */ base 4122 drivers/net/ethernet/intel/e1000e/ich8lan.c pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; base 986 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.speed = SPEED_40000; base 989 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.speed = SPEED_25000; base 992 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.speed = SPEED_20000; base 995 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.speed = SPEED_10000; base 998 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.speed = SPEED_5000; base 1001 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.speed = SPEED_2500; base 1004 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.speed = SPEED_1000; base 1007 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.speed = SPEED_100; base 1010 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.speed = SPEED_UNKNOWN; base 1013 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.duplex = DUPLEX_FULL; base 1034 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.speed = SPEED_UNKNOWN; base 1035 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.duplex = DUPLEX_UNKNOWN; base 1064 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.autoneg = ((hw_link_info->an_info & I40E_AQ_AN_COMPLETED) ? base 1075 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.port = PORT_NONE; base 1080 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.port = PORT_TP; base 1086 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.port = PORT_DA; base 1091 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.port = PORT_FIBRE; base 1095 drivers/net/ethernet/intel/i40e/i40e_ethtool.c ks->base.port = PORT_OTHER; base 1178 drivers/net/ethernet/intel/i40e/i40e_ethtool.c autoneg = copy_ks.base.autoneg; base 1182 drivers/net/ethernet/intel/i40e/i40e_ethtool.c safe_ks.base.cmd = copy_ks.base.cmd; base 1183 drivers/net/ethernet/intel/i40e/i40e_ethtool.c safe_ks.base.link_mode_masks_nwords = base 1184 drivers/net/ethernet/intel/i40e/i40e_ethtool.c copy_ks.base.link_mode_masks_nwords; base 1196 drivers/net/ethernet/intel/i40e/i40e_ethtool.c copy_ks.base.autoneg = safe_ks.base.autoneg; base 1201 drivers/net/ethernet/intel/i40e/i40e_ethtool.c if (memcmp(©_ks.base, &safe_ks.base, base 20 drivers/net/ethernet/intel/i40e/i40e_hmc.h u64 base; /* base addr in FPM */ base 159 drivers/net/ethernet/intel/i40e/i40e_hmc.h fpm_addr = (hmc_info)->hmc_obj[(type)].base + \ base 183 drivers/net/ethernet/intel/i40e/i40e_hmc.h fpm_adr = (hmc_info)->hmc_obj[(type)].base + \ base 101 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c full_obj->base = 0; base 108 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c obj->base = 0; base 128 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c obj->base = hw->hmc.hmc_obj[I40E_HMC_LAN_TX].base + base 131 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c obj->base = i40e_align_l2obj_base(obj->base); base 151 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c obj->base = hw->hmc.hmc_obj[I40E_HMC_LAN_RX].base + base 154 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c obj->base = i40e_align_l2obj_base(obj->base); base 174 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c obj->base = hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].base + base 177 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c obj->base = i40e_align_l2obj_base(obj->base); base 488 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c (u32)((obj->base & I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK) / 512)); base 494 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c (u32)((obj->base & I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK) / 512)); base 500 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c (u32)((obj->base & I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK) / 512)); base 506 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c (u32)((obj->base & I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK) / 512)); base 676 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c {I40E_HMC_STORE(i40e_hmc_obj_txq, base), 57, 32 }, base 702 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c { I40E_HMC_STORE(i40e_hmc_obj_rxq, base), 57, 32 }, base 1020 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c obj_offset_in_fpm = hmc_info->hmc_obj[rsrc_type].base + base 22 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.h u64 base; base 55 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.h u64 base; base 3158 drivers/net/ethernet/intel/i40e/i40e_main.c tx_ctx.base = (ring->dma / 128); base 3296 drivers/net/ethernet/intel/i40e/i40e_main.c rx_ctx.base = (ring->dma / 128); base 3771 drivers/net/ethernet/intel/i40e/i40e_main.c int base = vsi->base_vector; base 3781 drivers/net/ethernet/intel/i40e/i40e_main.c irq_num = pf->msix_entries[base + vector].vector; base 3828 drivers/net/ethernet/intel/i40e/i40e_main.c irq_num = pf->msix_entries[base + vector].vector; base 3844 drivers/net/ethernet/intel/i40e/i40e_main.c int base = vsi->base_vector; base 3872 drivers/net/ethernet/intel/i40e/i40e_main.c synchronize_irq(pf->msix_entries[i + base].vector); base 4603 drivers/net/ethernet/intel/i40e/i40e_main.c int base = vsi->base_vector; base 4619 drivers/net/ethernet/intel/i40e/i40e_main.c vector = i + base; base 570 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c tx_ctx.base = info->dma_ring_addr / 128; base 636 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c rx_ctx.base = info->dma_ring_addr / 128; base 279 drivers/net/ethernet/intel/iavf/iavf_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 280 drivers/net/ethernet/intel/iavf/iavf_ethtool.c cmd->base.port = PORT_NONE; base 284 drivers/net/ethernet/intel/iavf/iavf_ethtool.c cmd->base.speed = SPEED_40000; base 288 drivers/net/ethernet/intel/iavf/iavf_ethtool.c cmd->base.speed = SPEED_25000; base 295 drivers/net/ethernet/intel/iavf/iavf_ethtool.c cmd->base.speed = SPEED_20000; base 298 drivers/net/ethernet/intel/iavf/iavf_ethtool.c cmd->base.speed = SPEED_10000; base 301 drivers/net/ethernet/intel/iavf/iavf_ethtool.c cmd->base.speed = SPEED_1000; base 304 drivers/net/ethernet/intel/iavf/iavf_ethtool.c cmd->base.speed = SPEED_100; base 309 drivers/net/ethernet/intel/iavf/iavf_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 1112 drivers/net/ethernet/intel/ice/ice_common.c ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), base 1161 drivers/net/ethernet/intel/ice/ice_common.c ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), base 1992 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.speed = SPEED_100000; base 1995 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.speed = SPEED_50000; base 1998 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.speed = SPEED_40000; base 2001 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.speed = SPEED_25000; base 2004 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.speed = SPEED_20000; base 2007 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.speed = SPEED_10000; base 2010 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.speed = SPEED_5000; base 2013 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.speed = SPEED_2500; base 2016 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.speed = SPEED_1000; base 2019 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.speed = SPEED_100; base 2027 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.duplex = DUPLEX_FULL; base 2074 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.speed = SPEED_UNKNOWN; base 2075 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.duplex = DUPLEX_UNKNOWN; base 2108 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.autoneg = (hw_link_info->an_info & ICE_AQ_AN_COMPLETED) ? base 2115 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.port = PORT_FIBRE; base 2120 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.port = PORT_TP; base 2128 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.port = PORT_NONE; base 2133 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.port = PORT_DA; base 2136 drivers/net/ethernet/intel/ice/ice_ethtool.c ks->base.port = PORT_OTHER; base 2390 drivers/net/ethernet/intel/ice/ice_ethtool.c autoneg = copy_ks.base.autoneg; base 2407 drivers/net/ethernet/intel/ice/ice_ethtool.c safe_ks.base.cmd = copy_ks.base.cmd; base 2408 drivers/net/ethernet/intel/ice/ice_ethtool.c safe_ks.base.link_mode_masks_nwords = base 2409 drivers/net/ethernet/intel/ice/ice_ethtool.c copy_ks.base.link_mode_masks_nwords; base 2413 drivers/net/ethernet/intel/ice/ice_ethtool.c copy_ks.base.autoneg = safe_ks.base.autoneg; base 2415 drivers/net/ethernet/intel/ice/ice_ethtool.c copy_ks.base.speed = safe_ks.base.speed; base 2420 drivers/net/ethernet/intel/ice/ice_ethtool.c if (memcmp(©_ks.base, &safe_ks.base, sizeof(copy_ks.base))) base 274 drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h u64 base; base 420 drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h u64 base; /* base is defined in 128-byte units */ base 30 drivers/net/ethernet/intel/ice/ice_lib.c rlan_ctx.base = ring->dma >> 7; base 121 drivers/net/ethernet/intel/ice/ice_lib.c tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S; base 2712 drivers/net/ethernet/intel/ice/ice_lib.c int base = vsi->base_vector; base 2724 drivers/net/ethernet/intel/ice/ice_lib.c u16 vector = i + base; base 2887 drivers/net/ethernet/intel/ice/ice_lib.c int base = vsi->base_vector; base 2934 drivers/net/ethernet/intel/ice/ice_lib.c synchronize_irq(pf->msix_entries[i + base].vector); base 1606 drivers/net/ethernet/intel/ice/ice_main.c int base = vsi->base_vector; base 1615 drivers/net/ethernet/intel/ice/ice_main.c irq_num = pf->msix_entries[base + vector].vector; base 1655 drivers/net/ethernet/intel/ice/ice_main.c irq_num = pf->msix_entries[base + vector].vector, base 1094 drivers/net/ethernet/intel/ice/ice_sched.c ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base, base 1099 drivers/net/ethernet/intel/ice/ice_sched.c for (i = 0; i < base->num_children; i++) { base 1100 drivers/net/ethernet/intel/ice/ice_sched.c struct ice_sched_node *child = base->children[i]; base 165 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.port = PORT_TP; base 166 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.phy_address = hw->phy.addr; base 191 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.port = PORT_FIBRE; base 225 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 227 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.duplex = DUPLEX_HALF; base 230 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 232 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.speed = speed; base 235 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 237 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 241 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : base 244 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; base 247 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; base 249 drivers/net/ethernet/intel/igb/igb_ethtool.c cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix; base 279 drivers/net/ethernet/intel/igb/igb_ethtool.c if (cmd->base.eth_tp_mdix_ctrl) { base 283 drivers/net/ethernet/intel/igb/igb_ethtool.c if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && base 284 drivers/net/ethernet/intel/igb/igb_ethtool.c (cmd->base.autoneg != AUTONEG_ENABLE)) { base 296 drivers/net/ethernet/intel/igb/igb_ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 327 drivers/net/ethernet/intel/igb/igb_ethtool.c u32 speed = cmd->base.speed; base 329 drivers/net/ethernet/intel/igb/igb_ethtool.c if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) { base 336 drivers/net/ethernet/intel/igb/igb_ethtool.c if (cmd->base.eth_tp_mdix_ctrl) { base 340 drivers/net/ethernet/intel/igb/igb_ethtool.c if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) base 343 drivers/net/ethernet/intel/igb/igb_ethtool.c hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl; base 22 drivers/net/ethernet/intel/igbvf/ethtool.c #define IGBVF_STAT(current, base) \ base 25 drivers/net/ethernet/intel/igbvf/ethtool.c offsetof(struct igbvf_adapter, base) base 63 drivers/net/ethernet/intel/igbvf/ethtool.c cmd->base.port = -1; base 68 drivers/net/ethernet/intel/igbvf/ethtool.c cmd->base.speed = SPEED_1000; base 70 drivers/net/ethernet/intel/igbvf/ethtool.c cmd->base.speed = SPEED_100; base 72 drivers/net/ethernet/intel/igbvf/ethtool.c cmd->base.speed = SPEED_10; base 75 drivers/net/ethernet/intel/igbvf/ethtool.c cmd->base.duplex = DUPLEX_FULL; base 77 drivers/net/ethernet/intel/igbvf/ethtool.c cmd->base.duplex = DUPLEX_HALF; base 79 drivers/net/ethernet/intel/igbvf/ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 80 drivers/net/ethernet/intel/igbvf/ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 83 drivers/net/ethernet/intel/igbvf/ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 1669 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.port = PORT_TP; base 1670 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.phy_address = hw->phy.addr; base 1728 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 1730 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.duplex = DUPLEX_HALF; base 1733 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 1735 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.speed = speed; base 1737 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 1739 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 1743 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : base 1746 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; base 1749 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; base 1751 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix; base 1776 drivers/net/ethernet/intel/igc/igc_ethtool.c if (cmd->base.eth_tp_mdix_ctrl) { base 1777 drivers/net/ethernet/intel/igc/igc_ethtool.c if (cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO && base 1778 drivers/net/ethernet/intel/igc/igc_ethtool.c cmd->base.autoneg != AUTONEG_ENABLE) { base 1790 drivers/net/ethernet/intel/igc/igc_ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 1802 drivers/net/ethernet/intel/igc/igc_ethtool.c if (cmd->base.eth_tp_mdix_ctrl) { base 1806 drivers/net/ethernet/intel/igc/igc_ethtool.c if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) base 1809 drivers/net/ethernet/intel/igc/igc_ethtool.c hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl; base 85 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c cmd->base.port = PORT_FIBRE; base 88 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c cmd->base.speed = SPEED_10000; base 89 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 91 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 92 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 95 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 114 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c u32 speed = cmd->base.speed; base 116 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c if (cmd->base.autoneg == AUTONEG_ENABLE || base 117 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL)) base 227 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 229 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 240 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.port = PORT_TP; base 245 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.port = PORT_FIBRE; base 265 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.port = PORT_DA; base 277 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.port = PORT_FIBRE; base 282 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.port = PORT_NONE; base 288 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.port = PORT_TP; base 294 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.port = PORT_OTHER; base 301 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.port = PORT_NONE; base 309 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.port = PORT_OTHER; base 335 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.speed = SPEED_10000; base 338 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.speed = SPEED_5000; base 341 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.speed = SPEED_2500; base 344 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.speed = SPEED_1000; base 347 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.speed = SPEED_100; base 350 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.speed = SPEED_10; base 355 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 357 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 358 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 393 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c if (!cmd->base.autoneg && hw->phy.multispeed_fiber) { base 429 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c u32 speed = cmd->base.speed; base 431 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c if ((cmd->base.autoneg == AUTONEG_ENABLE) || base 433 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL)) base 91 drivers/net/ethernet/intel/ixgbevf/ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 92 drivers/net/ethernet/intel/ixgbevf/ethtool.c cmd->base.port = -1; base 109 drivers/net/ethernet/intel/ixgbevf/ethtool.c cmd->base.speed = speed; base 110 drivers/net/ethernet/intel/ixgbevf/ethtool.c cmd->base.duplex = DUPLEX_FULL; base 112 drivers/net/ethernet/intel/ixgbevf/ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 113 drivers/net/ethernet/intel/ixgbevf/ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 2608 drivers/net/ethernet/jme.c if (cmd->base.speed == SPEED_1000 && base 2609 drivers/net/ethernet/jme.c cmd->base.autoneg != AUTONEG_ENABLE) base 2617 drivers/net/ethernet/jme.c cmd->base.autoneg != AUTONEG_ENABLE && base 2618 drivers/net/ethernet/jme.c (jme->mii_if.full_duplex != cmd->base.duplex)) base 263 drivers/net/ethernet/marvell/mv643xx_eth.c void __iomem *base; base 368 drivers/net/ethernet/marvell/mv643xx_eth.c void __iomem *base; base 420 drivers/net/ethernet/marvell/mv643xx_eth.c return readl(mp->shared->base + offset); base 425 drivers/net/ethernet/marvell/mv643xx_eth.c return readl(mp->base + offset); base 430 drivers/net/ethernet/marvell/mv643xx_eth.c writel(data, mp->shared->base + offset); base 435 drivers/net/ethernet/marvell/mv643xx_eth.c writel(data, mp->base + offset); base 1517 drivers/net/ethernet/marvell/mv643xx_eth.c cmd->base.speed = SPEED_10; base 1520 drivers/net/ethernet/marvell/mv643xx_eth.c cmd->base.speed = SPEED_100; base 1523 drivers/net/ethernet/marvell/mv643xx_eth.c cmd->base.speed = SPEED_1000; base 1526 drivers/net/ethernet/marvell/mv643xx_eth.c cmd->base.speed = -1; base 1529 drivers/net/ethernet/marvell/mv643xx_eth.c cmd->base.duplex = (port_status & FULL_DUPLEX) ? base 1531 drivers/net/ethernet/marvell/mv643xx_eth.c cmd->base.port = PORT_MII; base 1532 drivers/net/ethernet/marvell/mv643xx_eth.c cmd->base.phy_address = 0; base 1533 drivers/net/ethernet/marvell/mv643xx_eth.c cmd->base.autoneg = AUTONEG_DISABLE; base 2622 drivers/net/ethernet/marvell/mv643xx_eth.c void __iomem *base = msp->base; base 2628 drivers/net/ethernet/marvell/mv643xx_eth.c writel(0, base + WINDOW_BASE(i)); base 2629 drivers/net/ethernet/marvell/mv643xx_eth.c writel(0, base + WINDOW_SIZE(i)); base 2631 drivers/net/ethernet/marvell/mv643xx_eth.c writel(0, base + WINDOW_REMAP_HIGH(i)); base 2640 drivers/net/ethernet/marvell/mv643xx_eth.c writel((cs->base & 0xffff0000) | base 2642 drivers/net/ethernet/marvell/mv643xx_eth.c dram->mbus_dram_target_id, base + WINDOW_BASE(i)); base 2643 drivers/net/ethernet/marvell/mv643xx_eth.c writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); base 2649 drivers/net/ethernet/marvell/mv643xx_eth.c writel(win_enable, base + WINDOW_BAR_ENABLE); base 2660 drivers/net/ethernet/marvell/mv643xx_eth.c writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); base 2661 drivers/net/ethernet/marvell/mv643xx_eth.c if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) base 2671 drivers/net/ethernet/marvell/mv643xx_eth.c writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); base 2672 drivers/net/ethernet/marvell/mv643xx_eth.c if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { base 2675 drivers/net/ethernet/marvell/mv643xx_eth.c writel(7, msp->base + 0x0400 + TX_BW_RATE); base 2676 drivers/net/ethernet/marvell/mv643xx_eth.c if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) base 2853 drivers/net/ethernet/marvell/mv643xx_eth.c msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); base 2854 drivers/net/ethernet/marvell/mv643xx_eth.c if (msp->base == NULL) base 3107 drivers/net/ethernet/marvell/mv643xx_eth.c mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); base 414 drivers/net/ethernet/marvell/mvneta.c void __iomem *base; base 659 drivers/net/ethernet/marvell/mvneta.c writel(data, pp->base + offset); base 665 drivers/net/ethernet/marvell/mvneta.c return readl(pp->base + offset); base 980 drivers/net/ethernet/marvell/mvneta.c static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, base 1008 drivers/net/ethernet/marvell/mvneta.c mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | base 4098 drivers/net/ethernet/marvell/mvneta.c void __iomem *base = pp->base; base 4110 drivers/net/ethernet/marvell/mvneta.c val = readl_relaxed(base + s->offset); base 4114 drivers/net/ethernet/marvell/mvneta.c low = readl_relaxed(base + s->offset); base 4115 drivers/net/ethernet/marvell/mvneta.c high = readl_relaxed(base + s->offset + 4); base 4442 drivers/net/ethernet/marvell/mvneta.c (cs->base & 0xffff0000) | base 4569 drivers/net/ethernet/marvell/mvneta.c pp->base = devm_platform_ioremap_resource(pdev, 0); base 4570 drivers/net/ethernet/marvell/mvneta.c if (IS_ERR(pp->base)) { base 4571 drivers/net/ethernet/marvell/mvneta.c err = PTR_ERR(pp->base); base 903 drivers/net/ethernet/marvell/mvpp2/mvpp2.h void __iomem *base; base 1241 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); base 1243 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); base 1248 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); base 1253 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); base 1262 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); base 1265 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); base 1271 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); base 1273 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); base 1285 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_GMAC_INT_MASK); base 1287 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_GMAC_INT_MASK); base 1291 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_INT_MASK); base 1293 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_INT_MASK); base 1330 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG); base 1333 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL0_REG); base 1335 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); base 1338 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); base 1348 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG); base 1350 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL0_REG); base 1353 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); base 1355 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); base 1363 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & base 1365 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); base 1374 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); base 1387 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); base 1607 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | base 1609 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); base 1612 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG) & base 1614 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL0_REG); base 1674 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); base 1678 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); base 1686 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL1_REG); base 1690 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL1_REG); base 1700 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); base 1704 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); base 2741 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_INT_STAT); base 2744 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_STATUS); base 2751 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_GMAC_INT_STAT); base 2754 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_STATUS0); base 3426 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); base 3434 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); base 3537 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); base 4831 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_STATUS); base 4835 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG); base 4847 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_STATUS0); base 4883 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG); base 4900 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); base 4903 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c port->base + MVPP2_GMAC_AUTONEG_CONFIG); base 4905 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c port->base + MVPP2_GMAC_AUTONEG_CONFIG); base 4914 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c old_ctrl0 = ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); base 4915 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c old_ctrl4 = ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG); base 4934 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); base 4936 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG); base 4939 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c while (!(readl(port->base + MVPP22_XLG_CTRL0_REG) & base 4953 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); base 4954 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); base 4955 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); base 4956 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); base 5059 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(old_an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); base 5065 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(old_ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); base 5069 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); base 5071 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); base 5073 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); base 5075 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); base 5078 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & base 5136 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG); base 5139 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL0_REG); base 5141 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); base 5144 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); base 5164 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP22_XLG_CTRL0_REG); base 5167 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP22_XLG_CTRL0_REG); base 5169 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); base 5172 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); base 5295 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c port->base = devm_platform_ioremap_resource(pdev, 2 + id); base 5296 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (IS_ERR(port->base)) { base 5297 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c err = PTR_ERR(port->base); base 5312 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); base 5481 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | base 5697 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c void __iomem *base; base 5722 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c base = devm_platform_ioremap_resource(pdev, 0); base 5723 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (IS_ERR(base)) base 5724 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c return PTR_ERR(base); base 5781 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c priv->swth_base[i] = base + i * addr_space_sz; base 43 drivers/net/ethernet/marvell/octeontx2/af/common.h void *base; base 67 drivers/net/ethernet/marvell/octeontx2/af/common.h qmem->base = dma_alloc_coherent(dev, qmem->alloc_sz, base 69 drivers/net/ethernet/marvell/octeontx2/af/common.h if (!qmem->base) base 76 drivers/net/ethernet/marvell/octeontx2/af/common.h qmem->base += qmem->align; base 86 drivers/net/ethernet/marvell/octeontx2/af/common.h if (qmem->base) base 88 drivers/net/ethernet/marvell/octeontx2/af/common.h qmem->base - qmem->align, base 2277 drivers/net/ethernet/marvell/octeontx2/af/rvu.c void __iomem *base; base 2285 drivers/net/ethernet/marvell/octeontx2/af/rvu.c base = pci_ioremap_bar(pdev, 0); base 2286 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!base) base 2290 drivers/net/ethernet/marvell/octeontx2/af/rvu.c ret = (readq(base + 0x10) >> 32) & 0xffff; base 2291 drivers/net/ethernet/marvell/octeontx2/af/rvu.c iounmap(base); base 421 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c result = (struct nix_aq_res_s *)aq->res->base; base 427 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)), base 546 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c memset(aq->res->base, 0, aq->res->entry_sz); base 548 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c ctx = aq->res->base + 128; base 550 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mask = aq->res->base + 256; base 26 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c result = (struct npa_aq_res_s *)aq->res->base; base 32 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)), base 98 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c memset(aq->res->base, 0, aq->res->entry_sz); base 100 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c ctx = aq->res->base + 128; base 102 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c mask = aq->res->base + 256; base 431 drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h u64 base; base 246 drivers/net/ethernet/marvell/pxa168_eth.c void __iomem *base; base 275 drivers/net/ethernet/marvell/pxa168_eth.c return readl_relaxed(pep->base + offset); base 280 drivers/net/ethernet/marvell/pxa168_eth.c writel_relaxed(data, pep->base + offset); base 977 drivers/net/ethernet/marvell/pxa168_eth.c cmd.base.phy_address = pep->phy_addr; base 978 drivers/net/ethernet/marvell/pxa168_eth.c cmd.base.speed = pep->phy_speed; base 979 drivers/net/ethernet/marvell/pxa168_eth.c cmd.base.duplex = pep->phy_duplex; base 982 drivers/net/ethernet/marvell/pxa168_eth.c cmd.base.autoneg = AUTONEG_ENABLE; base 984 drivers/net/ethernet/marvell/pxa168_eth.c if (cmd.base.speed != 0) base 985 drivers/net/ethernet/marvell/pxa168_eth.c cmd.base.autoneg = AUTONEG_DISABLE; base 1428 drivers/net/ethernet/marvell/pxa168_eth.c pep->base = devm_platform_ioremap_resource(pdev, 0); base 1429 drivers/net/ethernet/marvell/pxa168_eth.c if (IS_ERR(pep->base)) { base 303 drivers/net/ethernet/marvell/skge.c cmd->base.port = PORT_TP; base 304 drivers/net/ethernet/marvell/skge.c cmd->base.phy_address = hw->phy_addr; base 306 drivers/net/ethernet/marvell/skge.c cmd->base.port = PORT_FIBRE; base 309 drivers/net/ethernet/marvell/skge.c cmd->base.autoneg = skge->autoneg; base 310 drivers/net/ethernet/marvell/skge.c cmd->base.speed = skge->speed; base 311 drivers/net/ethernet/marvell/skge.c cmd->base.duplex = skge->duplex; base 333 drivers/net/ethernet/marvell/skge.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 339 drivers/net/ethernet/marvell/skge.c u32 speed = cmd->base.speed; base 343 drivers/net/ethernet/marvell/skge.c if (cmd->base.duplex == DUPLEX_FULL) base 345 drivers/net/ethernet/marvell/skge.c else if (cmd->base.duplex == DUPLEX_HALF) base 351 drivers/net/ethernet/marvell/skge.c if (cmd->base.duplex == DUPLEX_FULL) base 353 drivers/net/ethernet/marvell/skge.c else if (cmd->base.duplex == DUPLEX_HALF) base 360 drivers/net/ethernet/marvell/skge.c if (cmd->base.duplex == DUPLEX_FULL) base 362 drivers/net/ethernet/marvell/skge.c else if (cmd->base.duplex == DUPLEX_HALF) base 375 drivers/net/ethernet/marvell/skge.c skge->duplex = cmd->base.duplex; base 378 drivers/net/ethernet/marvell/skge.c skge->autoneg = cmd->base.autoneg; base 909 drivers/net/ethernet/marvell/skge.c static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base) base 923 drivers/net/ethernet/marvell/skge.c d->next_offset = base; base 926 drivers/net/ethernet/marvell/skge.c d->next_offset = base + (i+1) * sizeof(*d); base 2514 drivers/net/ethernet/marvell/skge.c u64 base = skge->dma + (e->desc - skge->mem); base 2522 drivers/net/ethernet/marvell/skge.c skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); base 2523 drivers/net/ethernet/marvell/skge.c skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); base 3583 drivers/net/ethernet/marvell/sky2.c cmd->base.phy_address = PHY_ADDR_MARV; base 3585 drivers/net/ethernet/marvell/sky2.c cmd->base.port = PORT_TP; base 3586 drivers/net/ethernet/marvell/sky2.c cmd->base.speed = sky2->speed; base 3589 drivers/net/ethernet/marvell/sky2.c cmd->base.speed = SPEED_1000; base 3590 drivers/net/ethernet/marvell/sky2.c cmd->base.port = PORT_FIBRE; base 3595 drivers/net/ethernet/marvell/sky2.c cmd->base.autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) base 3597 drivers/net/ethernet/marvell/sky2.c cmd->base.duplex = sky2->duplex; base 3618 drivers/net/ethernet/marvell/sky2.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 3636 drivers/net/ethernet/marvell/sky2.c u32 speed = cmd->base.speed; base 3640 drivers/net/ethernet/marvell/sky2.c if (cmd->base.duplex == DUPLEX_FULL) base 3642 drivers/net/ethernet/marvell/sky2.c else if (cmd->base.duplex == DUPLEX_HALF) base 3648 drivers/net/ethernet/marvell/sky2.c if (cmd->base.duplex == DUPLEX_FULL) base 3650 drivers/net/ethernet/marvell/sky2.c else if (cmd->base.duplex == DUPLEX_HALF) base 3657 drivers/net/ethernet/marvell/sky2.c if (cmd->base.duplex == DUPLEX_FULL) base 3659 drivers/net/ethernet/marvell/sky2.c else if (cmd->base.duplex == DUPLEX_HALF) base 3672 drivers/net/ethernet/marvell/sky2.c sky2->duplex = cmd->base.duplex; base 2363 drivers/net/ethernet/marvell/sky2.h unsigned base = SK_GMAC_REG(port, reg); base 2364 drivers/net/ethernet/marvell/sky2.h return (u32) sky2_read16(hw, base) base 2365 drivers/net/ethernet/marvell/sky2.h | (u32) sky2_read16(hw, base+4) << 16; base 2370 drivers/net/ethernet/marvell/sky2.h unsigned base = SK_GMAC_REG(port, reg); base 2372 drivers/net/ethernet/marvell/sky2.h return (u64) sky2_read16(hw, base) base 2373 drivers/net/ethernet/marvell/sky2.h | (u64) sky2_read16(hw, base+4) << 16 base 2374 drivers/net/ethernet/marvell/sky2.h | (u64) sky2_read16(hw, base+8) << 32 base 2375 drivers/net/ethernet/marvell/sky2.h | (u64) sky2_read16(hw, base+12) << 48; base 60 drivers/net/ethernet/mediatek/mtk_eth_soc.c __raw_writel(val, eth->base + reg); base 65 drivers/net/ethernet/mediatek/mtk_eth_soc.c return __raw_readl(eth->base + reg); base 669 drivers/net/ethernet/mediatek/mtk_eth_soc.c unsigned int base = MTK_GDM1_TX_GBCNT; base 672 drivers/net/ethernet/mediatek/mtk_eth_soc.c base += hw_stats->reg_offset; base 676 drivers/net/ethernet/mediatek/mtk_eth_soc.c hw_stats->rx_bytes += mtk_r32(mac->hw, base); base 677 drivers/net/ethernet/mediatek/mtk_eth_soc.c stats = mtk_r32(mac->hw, base + 0x04); base 680 drivers/net/ethernet/mediatek/mtk_eth_soc.c hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); base 681 drivers/net/ethernet/mediatek/mtk_eth_soc.c hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); base 682 drivers/net/ethernet/mediatek/mtk_eth_soc.c hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); base 683 drivers/net/ethernet/mediatek/mtk_eth_soc.c hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); base 684 drivers/net/ethernet/mediatek/mtk_eth_soc.c hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); base 685 drivers/net/ethernet/mediatek/mtk_eth_soc.c hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); base 687 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_r32(mac->hw, base + 0x24); base 688 drivers/net/ethernet/mediatek/mtk_eth_soc.c hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); base 689 drivers/net/ethernet/mediatek/mtk_eth_soc.c hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); base 690 drivers/net/ethernet/mediatek/mtk_eth_soc.c hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); base 691 drivers/net/ethernet/mediatek/mtk_eth_soc.c stats = mtk_r32(mac->hw, base + 0x34); base 694 drivers/net/ethernet/mediatek/mtk_eth_soc.c hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); base 2858 drivers/net/ethernet/mediatek/mtk_eth_soc.c eth->netdev[id]->base_addr = (unsigned long)eth->base; base 2892 drivers/net/ethernet/mediatek/mtk_eth_soc.c eth->base = devm_platform_ioremap_resource(pdev, 0); base 2893 drivers/net/ethernet/mediatek/mtk_eth_soc.c if (IS_ERR(eth->base)) base 2894 drivers/net/ethernet/mediatek/mtk_eth_soc.c return PTR_ERR(eth->base); base 860 drivers/net/ethernet/mediatek/mtk_eth_soc.h void __iomem *base; base 799 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.port = ptys_get_active_port(&ptys_reg); base 808 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.autoneg base 822 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.phy_address = 0; base 823 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.mdio_support = 0; base 824 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID; base 825 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; base 837 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.autoneg = AUTONEG_DISABLE; base 849 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.port = PORT_FIBRE; base 855 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.port = PORT_TP; base 861 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.port = -1; base 885 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.speed = priv->port_state.link_speed; base 886 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.duplex = DUPLEX_FULL; base 888 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.speed = SPEED_UNKNOWN; base 889 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.duplex = DUPLEX_UNKNOWN; base 925 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c const int speed = link_ksettings->base.speed; base 931 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.autoneg, base 932 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c link_ksettings->base.duplex); base 936 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c (link_ksettings->base.duplex == DUPLEX_HALF)) base 953 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c if (link_ksettings->base.autoneg == AUTONEG_DISABLE) { base 974 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c (link_ksettings->base.autoneg == cur_autoneg))) base 1027 drivers/net/ethernet/mellanox/mlx4/mlx4.h int *base, u8 flags); base 1174 drivers/net/ethernet/mellanox/mlx4/port.c int num_gids, base, offset; base 1178 drivers/net/ethernet/mellanox/mlx4/port.c base = mlx4_get_base_gid_ix(dev, slave, port); base 1184 drivers/net/ethernet/mellanox/mlx4/port.c for (i = 0, offset = base; i < num_gids; offset++, i++) base 1344 drivers/net/ethernet/mellanox/mlx4/port.c int base; base 1410 drivers/net/ethernet/mellanox/mlx4/port.c base = mlx4_get_base_gid_ix(dev, slave, port); base 1435 drivers/net/ethernet/mellanox/mlx4/port.c if (i >= base && i < base + num_gids) base 1458 drivers/net/ethernet/mellanox/mlx4/port.c for (i = 0, offset = base; i < num_gids; gid_entry_mbox++, offset++, i++) base 220 drivers/net/ethernet/mellanox/mlx4/qp.c int *base, u8 flags) base 239 drivers/net/ethernet/mellanox/mlx4/qp.c *base = mlx4_zone_alloc_entries(qp_table->zones, uid, cnt, align, base 241 drivers/net/ethernet/mellanox/mlx4/qp.c if (*base == -1) base 248 drivers/net/ethernet/mellanox/mlx4/qp.c int *base, u8 flags, u8 usage) base 268 drivers/net/ethernet/mellanox/mlx4/qp.c *base = get_param_l(&out_param); base 271 drivers/net/ethernet/mellanox/mlx4/qp.c return __mlx4_qp_reserve_range(dev, cnt, align, base, flags); base 1278 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count, base 1293 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c res_arr[i] = alloc_tr(base + i, type, slave, extra); base 1305 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c if (find_res(dev, base + i, type)) { base 1465 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count, base 1475 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c for (i = base; i < base + count; ++i) { base 1490 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c for (i = base; i < base + count; ++i) { base 1792 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int base; base 1808 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c err = __mlx4_qp_reserve_range(dev, count, align, &base, flags); base 1814 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c err = add_res_range(dev, slave, base, count, RES_QP, 0); base 1817 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c __mlx4_qp_release_range(dev, base, count); base 1820 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c set_param_l(out_param, base); base 1857 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int base; base 1869 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c base = __mlx4_alloc_mtt_range(dev, order); base 1870 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c if (base == -1) { base 1875 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c err = add_res_range(dev, slave, base, 1, RES_MTT, order); base 1878 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c __mlx4_free_mtt_range(dev, base, order); base 1880 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c set_param_l(out_param, base); base 2364 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int base; base 2369 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c base = get_param_l(&in_param) & 0x7fffff; base 2371 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c err = rem_res_range(dev, slave, base, count, RES_QP, 0); base 2375 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c __mlx4_qp_release_range(dev, base, count); base 2403 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int base; base 2409 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c base = get_param_l(&in_param); base 2411 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c err = rem_res_range(dev, slave, base, 1, RES_MTT, order); base 2414 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c __mlx4_free_mtt_range(dev, base, order); base 4936 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int base; base 4948 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c base = mtt->com.res_id; base 4953 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c __mlx4_free_mtt_range(dev, base, base 5071 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c u64 base; base 5083 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c base = fs_rule->com.res_id; base 5089 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c err = mlx4_cmd(dev, base, 0, 0, base 59 drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls.h struct tls_offload_context_tx base; base 71 drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls.h base); base 75 drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls.h struct tls_offload_context_rx base; base 86 drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls.h base); base 109 drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_rxtx.c spin_lock_irqsave(&context->base.lock, flags); base 110 drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_rxtx.c record = tls_get_record(&context->base, tcp_seq, &info->rcd_sn); base 139 drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_rxtx.c spin_unlock_irqrestore(&context->base.lock, flags); base 801 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c link_ksettings->base.speed = speed; base 802 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c link_ksettings->base.duplex = duplex; base 941 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c link_ksettings->base.port = get_connector_port(eth_proto_oper, base 951 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE : base 1052 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c autoneg = link_ksettings->base.autoneg; base 1053 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c speed = link_ksettings->base.speed; base 2254 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c struct fs_node *base; base 2269 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c base = &fs_prio->node; base 2275 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c base = &fs_ns->node; base 2282 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c base, init_node, prio); base 227 drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c link_ksettings->base.duplex = DUPLEX_FULL; base 228 drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c link_ksettings->base.port = PORT_OTHER; base 230 drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c link_ksettings->base.autoneg = AUTONEG_DISABLE; base 232 drivers/net/ethernet/mellanox/mlx5/core/ipoib/ethtool.c link_ksettings->base.speed = speed; base 2699 drivers/net/ethernet/mellanox/mlxsw/spectrum.c cmd->base.speed = SPEED_UNKNOWN; base 2700 drivers/net/ethernet/mellanox/mlxsw/spectrum.c cmd->base.duplex = DUPLEX_UNKNOWN; base 2705 drivers/net/ethernet/mellanox/mlxsw/spectrum.c cmd->base.speed = mlxsw_sp1_from_ptys_speed(mlxsw_sp, ptys_eth_proto); base 2706 drivers/net/ethernet/mellanox/mlxsw/spectrum.c if (cmd->base.speed != SPEED_UNKNOWN) base 2707 drivers/net/ethernet/mellanox/mlxsw/spectrum.c cmd->base.duplex = DUPLEX_FULL; base 3095 drivers/net/ethernet/mellanox/mlxsw/spectrum.c cmd->base.speed = SPEED_UNKNOWN; base 3096 drivers/net/ethernet/mellanox/mlxsw/spectrum.c cmd->base.duplex = DUPLEX_UNKNOWN; base 3101 drivers/net/ethernet/mellanox/mlxsw/spectrum.c cmd->base.speed = mlxsw_sp2_from_ptys_speed(mlxsw_sp, ptys_eth_proto); base 3102 drivers/net/ethernet/mellanox/mlxsw/spectrum.c if (cmd->base.speed != SPEED_UNKNOWN) base 3103 drivers/net/ethernet/mellanox/mlxsw/spectrum.c cmd->base.duplex = DUPLEX_FULL; base 3320 drivers/net/ethernet/mellanox/mlxsw/spectrum.c cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; base 3322 drivers/net/ethernet/mellanox/mlxsw/spectrum.c cmd->base.port = mlxsw_sp_port_connector_port(connector_type); base 3350 drivers/net/ethernet/mellanox/mlxsw/spectrum.c autoneg = cmd->base.autoneg == AUTONEG_ENABLE; base 3355 drivers/net/ethernet/mellanox/mlxsw/spectrum.c cmd->base.speed); base 707 drivers/net/ethernet/mellanox/mlxsw/switchx2.c cmd->base.speed = speed; base 708 drivers/net/ethernet/mellanox/mlxsw/switchx2.c cmd->base.duplex = duplex; base 763 drivers/net/ethernet/mellanox/mlxsw/switchx2.c cmd->base.port = mlxsw_sx_port_connector_port(eth_proto_oper); base 827 drivers/net/ethernet/mellanox/mlxsw/switchx2.c speed = cmd->base.speed; base 832 drivers/net/ethernet/mellanox/mlxsw/switchx2.c eth_proto_new = cmd->base.autoneg == AUTONEG_ENABLE ? base 5977 drivers/net/ethernet/micrel/ksz884x.c u32 speed = cmd->base.speed; base 5988 drivers/net/ethernet/micrel/ksz884x.c if (cmd->base.autoneg && priv->advertising == advertising) { base 5998 drivers/net/ethernet/micrel/ksz884x.c if (0 == cmd->base.duplex) base 6002 drivers/net/ethernet/micrel/ksz884x.c else if (1 == cmd->base.duplex) base 6008 drivers/net/ethernet/micrel/ksz884x.c if (cmd->base.autoneg && base 6014 drivers/net/ethernet/micrel/ksz884x.c port->duplex = cmd->base.duplex + 1; base 6017 drivers/net/ethernet/micrel/ksz884x.c if (cmd->base.autoneg) base 1487 drivers/net/ethernet/microchip/enc28j60.c cmd->base.speed = SPEED_10; base 1488 drivers/net/ethernet/microchip/enc28j60.c cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; base 1489 drivers/net/ethernet/microchip/enc28j60.c cmd->base.port = PORT_TP; base 1490 drivers/net/ethernet/microchip/enc28j60.c cmd->base.autoneg = AUTONEG_DISABLE; base 1499 drivers/net/ethernet/microchip/enc28j60.c return enc28j60_setlink(dev, cmd->base.autoneg, base 1500 drivers/net/ethernet/microchip/enc28j60.c cmd->base.speed, cmd->base.duplex); base 951 drivers/net/ethernet/microchip/encx24j600.c cmd->base.speed = priv->speed; base 952 drivers/net/ethernet/microchip/encx24j600.c cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; base 953 drivers/net/ethernet/microchip/encx24j600.c cmd->base.port = PORT_TP; base 954 drivers/net/ethernet/microchip/encx24j600.c cmd->base.autoneg = priv->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; base 963 drivers/net/ethernet/microchip/encx24j600.c return encx24j600_setlink(dev, cmd->base.autoneg, base 964 drivers/net/ethernet/microchip/encx24j600.c cmd->base.speed, cmd->base.duplex); base 964 drivers/net/ethernet/microchip/lan743x_main.c ksettings.base.duplex, base 967 drivers/net/ethernet/microchip/lan743x_main.c lan743x_ptp_update_latency(adapter, ksettings.base.speed); base 47 drivers/net/ethernet/moxa/moxart_ether.c writel(value, priv->base + reg); base 101 drivers/net/ethernet/moxa/moxart_ether.c writel(SW_RST, priv->base + REG_MAC_CTRL); base 102 drivers/net/ethernet/moxa/moxart_ether.c while (readl(priv->base + REG_MAC_CTRL) & SW_RST) base 105 drivers/net/ethernet/moxa/moxart_ether.c writel(0, priv->base + REG_INTERRUPT_MASK); base 114 drivers/net/ethernet/moxa/moxart_ether.c writel(0x00001010, priv->base + REG_INT_TIMER_CTRL); base 115 drivers/net/ethernet/moxa/moxart_ether.c writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL); base 116 drivers/net/ethernet/moxa/moxart_ether.c writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL); base 119 drivers/net/ethernet/moxa/moxart_ether.c writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); base 122 drivers/net/ethernet/moxa/moxart_ether.c writel(priv->reg_maccr, priv->base + REG_MAC_CTRL); base 167 drivers/net/ethernet/moxa/moxart_ether.c writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS); base 168 drivers/net/ethernet/moxa/moxart_ether.c writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS); base 187 drivers/net/ethernet/moxa/moxart_ether.c __func__, readl(priv->base + REG_INTERRUPT_MASK), base 188 drivers/net/ethernet/moxa/moxart_ether.c readl(priv->base + REG_MAC_CTRL)); base 202 drivers/net/ethernet/moxa/moxart_ether.c writel(0, priv->base + REG_INTERRUPT_MASK); base 205 drivers/net/ethernet/moxa/moxart_ether.c writel(0, priv->base + REG_MAC_CTRL); base 278 drivers/net/ethernet/moxa/moxart_ether.c writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); base 318 drivers/net/ethernet/moxa/moxart_ether.c unsigned int ists = readl(priv->base + REG_INTERRUPT_STATUS); base 326 drivers/net/ethernet/moxa/moxart_ether.c writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); base 392 drivers/net/ethernet/moxa/moxart_ether.c writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND); base 414 drivers/net/ethernet/moxa/moxart_ether.c writel(readl(priv->base + REG_MCAST_HASH_TABLE1) | base 416 drivers/net/ethernet/moxa/moxart_ether.c priv->base + REG_MCAST_HASH_TABLE1); base 418 drivers/net/ethernet/moxa/moxart_ether.c writel(readl(priv->base + REG_MCAST_HASH_TABLE0) | base 420 drivers/net/ethernet/moxa/moxart_ether.c priv->base + REG_MCAST_HASH_TABLE0); base 444 drivers/net/ethernet/moxa/moxart_ether.c writel(priv->reg_maccr, priv->base + REG_MAC_CTRL); base 485 drivers/net/ethernet/moxa/moxart_ether.c priv->base = devm_ioremap_resource(p_dev, res); base 486 drivers/net/ethernet/moxa/moxart_ether.c if (IS_ERR(priv->base)) { base 488 drivers/net/ethernet/moxa/moxart_ether.c ret = PTR_ERR(priv->base); base 296 drivers/net/ethernet/moxa/moxart_ether.h void __iomem *base; base 192 drivers/net/ethernet/mscc/ocelot_ace.c u32 i, col, offset, count, cnt, base, width = vcap_is2.tg_width; base 197 drivers/net/ethernet/mscc/ocelot_ace.c base = (vcap_is2.sw_count - col * cnt - cnt); base 201 drivers/net/ethernet/mscc/ocelot_ace.c offset = ((base + i) * width); base 208 drivers/net/ethernet/mscc/ocelot_ace.c data->key_offset = (base * vcap_is2.entry_width) / vcap_is2.sw_count; base 1618 drivers/net/ethernet/myricom/myri10ge/myri10ge.c cmd->base.autoneg = AUTONEG_DISABLE; base 1619 drivers/net/ethernet/myricom/myri10ge/myri10ge.c cmd->base.speed = SPEED_10000; base 1620 drivers/net/ethernet/myricom/myri10ge/myri10ge.c cmd->base.duplex = DUPLEX_FULL; base 1645 drivers/net/ethernet/myricom/myri10ge/myri10ge.c cmd->base.port = PORT_FIBRE; base 1649 drivers/net/ethernet/myricom/myri10ge/myri10ge.c cmd->base.port = PORT_OTHER; base 2840 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.port = dev->if_port; base 2841 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.speed = np->speed; base 2842 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.duplex = np->duplex; base 2843 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.autoneg = np->autoneg; base 2858 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.phy_address = np->phy_addr_external; base 2878 drivers/net/ethernet/natsemi/natsemi.c switch (ecmd->base.port) { base 2892 drivers/net/ethernet/natsemi/natsemi.c if (ecmd->base.autoneg == AUTONEG_ENABLE) { base 2897 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.speed = SPEED_100; base 2899 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.speed = SPEED_10; base 2901 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.duplex = DUPLEX_FULL; base 2903 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.duplex = DUPLEX_HALF; base 2925 drivers/net/ethernet/natsemi/natsemi.c if (ecmd->base.port != PORT_TP && base 2926 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.port != PORT_MII && base 2927 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.port != PORT_FIBRE) base 2929 drivers/net/ethernet/natsemi/natsemi.c if (ecmd->base.autoneg == AUTONEG_ENABLE) { base 2936 drivers/net/ethernet/natsemi/natsemi.c } else if (ecmd->base.autoneg == AUTONEG_DISABLE) { base 2937 drivers/net/ethernet/natsemi/natsemi.c u32 speed = ecmd->base.speed; base 2940 drivers/net/ethernet/natsemi/natsemi.c if (ecmd->base.duplex != DUPLEX_HALF && base 2941 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.duplex != DUPLEX_FULL) base 2952 drivers/net/ethernet/natsemi/natsemi.c if (np->ignore_phy && (ecmd->base.autoneg == AUTONEG_ENABLE || base 2953 drivers/net/ethernet/natsemi/natsemi.c ecmd->base.port == PORT_TP)) base 2972 drivers/net/ethernet/natsemi/natsemi.c dev->if_port = ecmd->base.port; base 2973 drivers/net/ethernet/natsemi/natsemi.c np->autoneg = ecmd->base.autoneg; base 2974 drivers/net/ethernet/natsemi/natsemi.c np->phy_addr_external = ecmd->base.phy_address & PhyAddrMask; base 2987 drivers/net/ethernet/natsemi/natsemi.c np->speed = ecmd->base.speed; base 2988 drivers/net/ethernet/natsemi/natsemi.c np->duplex = ecmd->base.duplex; base 2995 drivers/net/ethernet/natsemi/natsemi.c if (ecmd->base.port == PORT_TP) base 412 drivers/net/ethernet/natsemi/ns83820.c u8 __iomem *base; base 455 drivers/net/ethernet/natsemi/ns83820.c #define __kick_rx(dev) writel(CR_RXE, dev->base + CR) base 465 drivers/net/ethernet/natsemi/ns83820.c dev->base + RXDP); base 606 drivers/net/ethernet/natsemi/ns83820.c cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; base 610 drivers/net/ethernet/natsemi/ns83820.c tbisr = readl(dev->base + TBISR); base 611 drivers/net/ethernet/natsemi/ns83820.c tanar = readl(dev->base + TANAR); base 612 drivers/net/ethernet/natsemi/ns83820.c tanlpar = readl(dev->base + TANLPAR); base 620 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + TXCFG) base 622 drivers/net/ethernet/natsemi/ns83820.c dev->base + TXCFG); base 623 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, base 624 drivers/net/ethernet/natsemi/ns83820.c dev->base + RXCFG); base 626 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, base 627 drivers/net/ethernet/natsemi/ns83820.c dev->base + GPIOR); base 637 drivers/net/ethernet/natsemi/ns83820.c writel((readl(dev->base + TXCFG) base 639 drivers/net/ethernet/natsemi/ns83820.c dev->base + TXCFG); base 640 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, base 641 drivers/net/ethernet/natsemi/ns83820.c dev->base + RXCFG); base 643 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, base 644 drivers/net/ethernet/natsemi/ns83820.c dev->base + GPIOR); base 663 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + TXCFG) base 665 drivers/net/ethernet/natsemi/ns83820.c dev->base + TXCFG); base 666 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, base 667 drivers/net/ethernet/natsemi/ns83820.c dev->base + RXCFG); base 669 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + TXCFG) base 671 drivers/net/ethernet/natsemi/ns83820.c dev->base + TXCFG); base 672 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD), base 673 drivers/net/ethernet/natsemi/ns83820.c dev->base + RXCFG); base 678 drivers/net/ethernet/natsemi/ns83820.c writel(new_cfg, dev->base + CFG); base 721 drivers/net/ethernet/natsemi/ns83820.c writel(0, dev->base + RXDP_HI); base 722 drivers/net/ethernet/natsemi/ns83820.c writel(dev->rx_info.phy_descs, dev->base + RXDP); base 730 drivers/net/ethernet/natsemi/ns83820.c writel(0x0001, dev->base + CCSR); base 731 drivers/net/ethernet/natsemi/ns83820.c writel(0, dev->base + RFCR); base 732 drivers/net/ethernet/natsemi/ns83820.c writel(0x7fc00000, dev->base + RFCR); base 733 drivers/net/ethernet/natsemi/ns83820.c writel(0xffc00000, dev->base + RFCR); base 752 drivers/net/ethernet/natsemi/ns83820.c writel(dev->IMR_cache, dev->base + IMR); base 753 drivers/net/ethernet/natsemi/ns83820.c writel(1, dev->base + IER); base 773 drivers/net/ethernet/natsemi/ns83820.c writel(dev->IMR_cache, dev->base + IMR); base 781 drivers/net/ethernet/natsemi/ns83820.c readl(dev->base + IMR); base 784 drivers/net/ethernet/natsemi/ns83820.c writel(0, dev->base + RXDP_HI); base 785 drivers/net/ethernet/natsemi/ns83820.c writel(0, dev->base + RXDP); base 829 drivers/net/ethernet/natsemi/ns83820.c readl(dev->base + RXDP), base 931 drivers/net/ethernet/natsemi/ns83820.c writel(ihr, dev->base + IHR); base 935 drivers/net/ethernet/natsemi/ns83820.c writel(dev->IMR_cache, dev->base + IMR); base 948 drivers/net/ethernet/natsemi/ns83820.c writel(CR_TXE, dev->base + CR); base 1177 drivers/net/ethernet/natsemi/ns83820.c u8 __iomem *base = dev->base; base 1180 drivers/net/ethernet/natsemi/ns83820.c ndev->stats.rx_errors += readl(base + 0x60) & 0xffff; base 1181 drivers/net/ethernet/natsemi/ns83820.c ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff; base 1182 drivers/net/ethernet/natsemi/ns83820.c ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff; base 1183 drivers/net/ethernet/natsemi/ns83820.c ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff; base 1184 drivers/net/ethernet/natsemi/ns83820.c /*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70); base 1185 drivers/net/ethernet/natsemi/ns83820.c ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff; base 1186 drivers/net/ethernet/natsemi/ns83820.c ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff; base 1187 drivers/net/ethernet/natsemi/ns83820.c /*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c); base 1188 drivers/net/ethernet/natsemi/ns83820.c /*ndev->stats.rx_pause_count += */ readl(base + 0x80); base 1189 drivers/net/ethernet/natsemi/ns83820.c /*ndev->stats.tx_pause_count += */ readl(base + 0x84); base 1190 drivers/net/ethernet/natsemi/ns83820.c ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff; base 1228 drivers/net/ethernet/natsemi/ns83820.c cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; base 1229 drivers/net/ethernet/natsemi/ns83820.c tanar = readl(dev->base + TANAR); base 1230 drivers/net/ethernet/natsemi/ns83820.c tbicr = readl(dev->base + TBICR); base 1241 drivers/net/ethernet/natsemi/ns83820.c cmd->base.port = PORT_FIBRE; base 1249 drivers/net/ethernet/natsemi/ns83820.c cmd->base.port = PORT_MII; base 1255 drivers/net/ethernet/natsemi/ns83820.c cmd->base.duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF; base 1258 drivers/net/ethernet/natsemi/ns83820.c cmd->base.speed = SPEED_1000; base 1261 drivers/net/ethernet/natsemi/ns83820.c cmd->base.speed = SPEED_100; base 1264 drivers/net/ethernet/natsemi/ns83820.c cmd->base.speed = SPEED_10; base 1267 drivers/net/ethernet/natsemi/ns83820.c cmd->base.autoneg = (tbicr & TBICR_MR_AN_ENABLE) base 1282 drivers/net/ethernet/natsemi/ns83820.c cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; base 1283 drivers/net/ethernet/natsemi/ns83820.c tanar = readl(dev->base + TANAR); base 1299 drivers/net/ethernet/natsemi/ns83820.c if (cmd->base.duplex != fullduplex) { base 1302 drivers/net/ethernet/natsemi/ns83820.c if (cmd->base.duplex == DUPLEX_FULL) { base 1304 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + TXCFG) base 1306 drivers/net/ethernet/natsemi/ns83820.c dev->base + TXCFG); base 1307 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, base 1308 drivers/net/ethernet/natsemi/ns83820.c dev->base + RXCFG); base 1310 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, base 1311 drivers/net/ethernet/natsemi/ns83820.c dev->base + GPIOR); base 1326 drivers/net/ethernet/natsemi/ns83820.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 1329 drivers/net/ethernet/natsemi/ns83820.c dev->base + TBICR); base 1330 drivers/net/ethernet/natsemi/ns83820.c writel(TBICR_MR_AN_ENABLE, dev->base + TBICR); base 1337 drivers/net/ethernet/natsemi/ns83820.c writel(0x00000000, dev->base + TBICR); base 1341 drivers/net/ethernet/natsemi/ns83820.c cmd->base.autoneg ? "ENABLED" : "DISABLED"); base 1363 drivers/net/ethernet/natsemi/ns83820.c u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; base 1376 drivers/net/ethernet/natsemi/ns83820.c writel(0, dev->base + IMR); base 1377 drivers/net/ethernet/natsemi/ns83820.c writel(0, dev->base + IER); base 1378 drivers/net/ethernet/natsemi/ns83820.c readl(dev->base + IER); base 1400 drivers/net/ethernet/natsemi/ns83820.c isr = readl(dev->base + ISR); base 1427 drivers/net/ethernet/natsemi/ns83820.c writel(dev->IMR_cache, dev->base + IMR); base 1449 drivers/net/ethernet/natsemi/ns83820.c writel(CR_RXE, dev->base + CR); base 1453 drivers/net/ethernet/natsemi/ns83820.c txdp = readl(dev->base + TXDP); base 1484 drivers/net/ethernet/natsemi/ns83820.c writel(dev->IMR_cache, dev->base + IMR); base 1498 drivers/net/ethernet/natsemi/ns83820.c writel(dev->IMR_cache, dev->base + IMR); base 1512 drivers/net/ethernet/natsemi/ns83820.c writel(dev->ihr, dev->base + IHR); base 1519 drivers/net/ethernet/natsemi/ns83820.c writel(which, dev->base + CR); base 1522 drivers/net/ethernet/natsemi/ns83820.c } while (readl(dev->base + CR) & which); base 1571 drivers/net/ethernet/natsemi/ns83820.c isr = readl(dev->base + ISR); base 1621 drivers/net/ethernet/natsemi/ns83820.c writel(0, dev->base + PQCR); base 1638 drivers/net/ethernet/natsemi/ns83820.c writel(0, dev->base + TXDP_HI); base 1639 drivers/net/ethernet/natsemi/ns83820.c writel(desc, dev->base + TXDP); base 1662 drivers/net/ethernet/natsemi/ns83820.c writel(i*2, dev->base + RFCR); base 1663 drivers/net/ethernet/natsemi/ns83820.c data = readl(dev->base + RFDR); base 1673 drivers/net/ethernet/natsemi/ns83820.c u8 __iomem *rfcr = dev->base + RFCR; base 1708 drivers/net/ethernet/natsemi/ns83820.c writel(enable, dev->base + PTSCR); base 1711 drivers/net/ethernet/natsemi/ns83820.c status = readl(dev->base + PTSCR); base 1740 drivers/net/ethernet/natsemi/ns83820.c writel(dev->MEAR_cache, dev->base + MEAR); base 1741 drivers/net/ethernet/natsemi/ns83820.c readl(dev->base + MEAR); base 1751 drivers/net/ethernet/natsemi/ns83820.c writel(dev->MEAR_cache, dev->base + MEAR); base 1752 drivers/net/ethernet/natsemi/ns83820.c readl(dev->base + MEAR); base 1759 drivers/net/ethernet/natsemi/ns83820.c writel(dev->MEAR_cache, dev->base + MEAR); base 1760 drivers/net/ethernet/natsemi/ns83820.c readl(dev->base + MEAR); base 1773 drivers/net/ethernet/natsemi/ns83820.c writel(dev->MEAR_cache, dev->base + MEAR); base 1774 drivers/net/ethernet/natsemi/ns83820.c readl(dev->base + MEAR); base 1780 drivers/net/ethernet/natsemi/ns83820.c bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0; base 1782 drivers/net/ethernet/natsemi/ns83820.c writel(dev->MEAR_cache, dev->base + MEAR); base 1940 drivers/net/ethernet/natsemi/ns83820.c dev->base = ioremap_nocache(addr, PAGE_SIZE); base 1946 drivers/net/ethernet/natsemi/ns83820.c if (!dev->base || !dev->tx_descs || !dev->rx_info.descs) base 1980 drivers/net/ethernet/natsemi/ns83820.c ndev->name, le32_to_cpu(readl(dev->base + 0x22c)), base 1991 drivers/net/ethernet/natsemi/ns83820.c writel(PTSCR_RBIST_RST, dev->base + PTSCR); base 1999 drivers/net/ethernet/natsemi/ns83820.c dev->CFG_cache = readl(dev->base + CFG); base 2035 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR); base 2038 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base + TANAR) base 2040 drivers/net/ethernet/natsemi/ns83820.c dev->base + TANAR); base 2044 drivers/net/ethernet/natsemi/ns83820.c dev->base + TBICR); base 2045 drivers/net/ethernet/natsemi/ns83820.c writel(TBICR_MR_AN_ENABLE, dev->base + TBICR); base 2051 drivers/net/ethernet/natsemi/ns83820.c writel(dev->CFG_cache, dev->base + CFG); base 2056 drivers/net/ethernet/natsemi/ns83820.c writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG); base 2058 drivers/net/ethernet/natsemi/ns83820.c writel(dev->CFG_cache, dev->base + CFG); base 2064 drivers/net/ethernet/natsemi/ns83820.c if (readl(dev->base + SRR)) base 2065 drivers/net/ethernet/natsemi/ns83820.c writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c); base 2077 drivers/net/ethernet/natsemi/ns83820.c dev->base + TXCFG); base 2080 drivers/net/ethernet/natsemi/ns83820.c writel(0x000, dev->base + IHR); base 2081 drivers/net/ethernet/natsemi/ns83820.c writel(0x100, dev->base + IHR); base 2082 drivers/net/ethernet/natsemi/ns83820.c writel(0x000, dev->base + IHR); base 2093 drivers/net/ethernet/natsemi/ns83820.c | (RXCFG_MXDMA512) | 0, dev->base + RXCFG); base 2096 drivers/net/ethernet/natsemi/ns83820.c writel(0, dev->base + PQCR); base 2116 drivers/net/ethernet/natsemi/ns83820.c writel(VRCR_INIT_VALUE, dev->base + VRCR); base 2127 drivers/net/ethernet/natsemi/ns83820.c writel(VTCR_INIT_VALUE, dev->base + VTCR); base 2133 drivers/net/ethernet/natsemi/ns83820.c dev->base + PCR); base 2136 drivers/net/ethernet/natsemi/ns83820.c writel(0, dev->base + WCSR); base 2159 drivers/net/ethernet/natsemi/ns83820.c (unsigned)readl(dev->base + SRR) >> 8, base 2160 drivers/net/ethernet/natsemi/ns83820.c (unsigned)readl(dev->base + SRR) & 0xff, base 2184 drivers/net/ethernet/natsemi/ns83820.c if (dev->base) base 2185 drivers/net/ethernet/natsemi/ns83820.c iounmap(dev->base); base 2207 drivers/net/ethernet/natsemi/ns83820.c iounmap(dev->base); base 351 drivers/net/ethernet/natsemi/sonic.h static inline void sonic_buf_put(u16 *base, int bitmode, base 356 drivers/net/ethernet/natsemi/sonic.h __raw_writew(val, base + (offset * 2) + 1); base 358 drivers/net/ethernet/natsemi/sonic.h __raw_writew(val, base + (offset * 2) + 0); base 361 drivers/net/ethernet/natsemi/sonic.h __raw_writew(val, base + (offset * 1) + 0); base 364 drivers/net/ethernet/natsemi/sonic.h static inline __u16 sonic_buf_get(u16 *base, int bitmode, base 369 drivers/net/ethernet/natsemi/sonic.h return __raw_readw(base + (offset * 2) + 1); base 371 drivers/net/ethernet/natsemi/sonic.h return __raw_readw(base + (offset * 2) + 0); base 374 drivers/net/ethernet/natsemi/sonic.h return __raw_readw(base + (offset * 1) + 0); base 5269 drivers/net/ethernet/neterion/s2io.c if ((cmd->base.autoneg == AUTONEG_ENABLE) || base 5270 drivers/net/ethernet/neterion/s2io.c (cmd->base.speed != SPEED_10000) || base 5271 drivers/net/ethernet/neterion/s2io.c (cmd->base.duplex != DUPLEX_FULL)) base 5307 drivers/net/ethernet/neterion/s2io.c cmd->base.port = PORT_FIBRE; base 5310 drivers/net/ethernet/neterion/s2io.c cmd->base.speed = SPEED_10000; base 5311 drivers/net/ethernet/neterion/s2io.c cmd->base.duplex = DUPLEX_FULL; base 5313 drivers/net/ethernet/neterion/s2io.c cmd->base.speed = SPEED_UNKNOWN; base 5314 drivers/net/ethernet/neterion/s2io.c cmd->base.duplex = DUPLEX_UNKNOWN; base 5317 drivers/net/ethernet/neterion/s2io.c cmd->base.autoneg = AUTONEG_DISABLE; base 56 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c if ((cmd->base.autoneg == AUTONEG_ENABLE) || base 57 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c (cmd->base.speed != SPEED_10000) || base 58 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c (cmd->base.duplex != DUPLEX_FULL)) base 85 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c cmd->base.port = PORT_FIBRE; base 88 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c cmd->base.speed = SPEED_10000; base 89 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c cmd->base.duplex = DUPLEX_FULL; base 91 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 92 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 95 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 256 drivers/net/ethernet/netronome/nfp/bpf/jit.c static void emit_rtn(struct nfp_prog *nfp_prog, swreg base, u8 defer) base 261 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_unrestricted(reg_none(), base, reg_imm(0), ®); base 559 drivers/net/ethernet/netronome/nfp/flower/main.c eth_tbl->ports[i].base, base 269 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c cmd->base.port = PORT_OTHER; base 270 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 271 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 276 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c cmd->base.autoneg = eth_port->aneg != NFP_ANEG_DISABLED ? base 286 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c cmd->base.port = eth_port->port_type; base 287 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c cmd->base.speed = eth_port->speed; base 288 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 306 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c cmd->base.speed = ls_to_ethtool[ls]; base 307 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 335 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c err = __nfp_eth_set_aneg(nsp, cmd->base.autoneg == AUTONEG_ENABLE ? base 339 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c if (cmd->base.speed != SPEED_UNKNOWN) { base 340 drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c u32 speed = cmd->base.speed / eth_port->lanes; base 133 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c u64 base; /* CPP address base */ base 272 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c int base, slot; base 275 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c base = bar->index >> 3; base 279 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c xbar = NFP_PCIE_CPP_BAR_PCIETOCPPEXPANSIONBAR(base, slot); base 284 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c xbar = NFP_PCIE_CFG_BAR_PCIETOCPPEXPANSIONBAR(base, slot); base 306 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c bar->base = newbase; base 363 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c bar->base <= offset && base 364 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c (bar->base + (1 << bar->bitsize)) >= (offset + size)) base 591 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c bar->base = 0; base 157 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h unsigned int base; base 138 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c dst->base = index % NSP_ETH_NBI_PORT_COUNT; base 794 drivers/net/ethernet/nvidia/forcedeth.c void __iomem *base; base 941 drivers/net/ethernet/nvidia/forcedeth.c return ((struct fe_priv *)netdev_priv(dev))->base; base 944 drivers/net/ethernet/nvidia/forcedeth.c static inline void pci_push(u8 __iomem *base) base 947 drivers/net/ethernet/nvidia/forcedeth.c readl(base); base 971 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 973 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 979 drivers/net/ethernet/nvidia/forcedeth.c } while ((readl(base + offset) & mask) != target); base 999 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1003 drivers/net/ethernet/nvidia/forcedeth.c writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); base 1005 drivers/net/ethernet/nvidia/forcedeth.c writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); base 1008 drivers/net/ethernet/nvidia/forcedeth.c writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); base 1009 drivers/net/ethernet/nvidia/forcedeth.c writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); base 1012 drivers/net/ethernet/nvidia/forcedeth.c writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); base 1013 drivers/net/ethernet/nvidia/forcedeth.c writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh); base 1056 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1061 drivers/net/ethernet/nvidia/forcedeth.c powerstate = readl(base + NvRegPowerState2); base 1066 drivers/net/ethernet/nvidia/forcedeth.c writel(powerstate, base + NvRegPowerState2); base 1105 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1107 drivers/net/ethernet/nvidia/forcedeth.c writel(mask, base + NvRegIrqMask); base 1113 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1116 drivers/net/ethernet/nvidia/forcedeth.c writel(mask, base + NvRegIrqMask); base 1119 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMSIIrqMask); base 1120 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegIrqMask); base 1145 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1149 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus); base 1151 drivers/net/ethernet/nvidia/forcedeth.c reg = readl(base + NvRegMIIControl); base 1153 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); base 1159 drivers/net/ethernet/nvidia/forcedeth.c writel(value, base + NvRegMIIData); base 1162 drivers/net/ethernet/nvidia/forcedeth.c writel(reg, base + NvRegMIIControl); base 1170 drivers/net/ethernet/nvidia/forcedeth.c } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { base 1173 drivers/net/ethernet/nvidia/forcedeth.c retval = readl(base + NvRegMIIData); base 1230 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1231 drivers/net/ethernet/nvidia/forcedeth.c u32 powerstate = readl(base + NvRegPowerState2); base 1235 drivers/net/ethernet/nvidia/forcedeth.c writel(powerstate, base + NvRegPowerState2); base 1239 drivers/net/ethernet/nvidia/forcedeth.c writel(powerstate, base + NvRegPowerState2); base 1390 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1440 drivers/net/ethernet/nvidia/forcedeth.c phyinterface = readl(base + NvRegPhyInterface); base 1535 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1536 drivers/net/ethernet/nvidia/forcedeth.c u32 rx_ctrl = readl(base + NvRegReceiverControl); base 1539 drivers/net/ethernet/nvidia/forcedeth.c if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { base 1541 drivers/net/ethernet/nvidia/forcedeth.c writel(rx_ctrl, base + NvRegReceiverControl); base 1542 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 1544 drivers/net/ethernet/nvidia/forcedeth.c writel(np->linkspeed, base + NvRegLinkSpeed); base 1545 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 1549 drivers/net/ethernet/nvidia/forcedeth.c writel(rx_ctrl, base + NvRegReceiverControl); base 1550 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 1556 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1557 drivers/net/ethernet/nvidia/forcedeth.c u32 rx_ctrl = readl(base + NvRegReceiverControl); base 1563 drivers/net/ethernet/nvidia/forcedeth.c writel(rx_ctrl, base + NvRegReceiverControl); base 1571 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegLinkSpeed); base 1577 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1578 drivers/net/ethernet/nvidia/forcedeth.c u32 tx_ctrl = readl(base + NvRegTransmitterControl); base 1583 drivers/net/ethernet/nvidia/forcedeth.c writel(tx_ctrl, base + NvRegTransmitterControl); base 1584 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 1590 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1591 drivers/net/ethernet/nvidia/forcedeth.c u32 tx_ctrl = readl(base + NvRegTransmitterControl); base 1597 drivers/net/ethernet/nvidia/forcedeth.c writel(tx_ctrl, base + NvRegTransmitterControl); base 1605 drivers/net/ethernet/nvidia/forcedeth.c writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base 1606 drivers/net/ethernet/nvidia/forcedeth.c base + NvRegTransmitPoll); base 1624 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1626 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); base 1627 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 1629 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); base 1630 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 1636 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1639 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); base 1640 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 1643 drivers/net/ethernet/nvidia/forcedeth.c temp1 = readl(base + NvRegMacAddrA); base 1644 drivers/net/ethernet/nvidia/forcedeth.c temp2 = readl(base + NvRegMacAddrB); base 1645 drivers/net/ethernet/nvidia/forcedeth.c temp3 = readl(base + NvRegTransmitPoll); base 1647 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); base 1648 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 1650 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMacReset); base 1651 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 1655 drivers/net/ethernet/nvidia/forcedeth.c writel(temp1, base + NvRegMacAddrA); base 1656 drivers/net/ethernet/nvidia/forcedeth.c writel(temp2, base + NvRegMacAddrB); base 1657 drivers/net/ethernet/nvidia/forcedeth.c writel(temp3, base + NvRegTransmitPoll); base 1659 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); base 1660 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 1667 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 1676 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_bytes += readl(base + NvRegTxCnt); base 1677 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); base 1678 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); base 1679 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); base 1680 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_late_collision += readl(base + NvRegTxLateCol); base 1681 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); base 1682 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); base 1683 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); base 1684 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); base 1685 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); base 1686 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); base 1687 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_late_collision += readl(base + NvRegRxLateCol); base 1688 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_runt += readl(base + NvRegRxRunt); base 1689 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); base 1690 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_over_errors += readl(base + NvRegRxOverflow); base 1691 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); base 1692 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); base 1693 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_length_error += readl(base + NvRegRxLenErr); base 1694 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_unicast += readl(base + NvRegRxUnicast); base 1695 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_multicast += readl(base + NvRegRxMulticast); base 1696 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); base 1717 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_deferral += readl(base + NvRegTxDef); base 1718 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_packets += readl(base + NvRegTxFrame); base 1719 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_bytes += readl(base + NvRegRxCnt); base 1720 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_pause += readl(base + NvRegTxPause); base 1721 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_pause += readl(base + NvRegRxPause); base 1722 drivers/net/ethernet/nvidia/forcedeth.c np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); base 1727 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_unicast += readl(base + NvRegTxUnicast); base 1728 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_multicast += readl(base + NvRegTxMulticast); base 1729 drivers/net/ethernet/nvidia/forcedeth.c np->estats.tx_broadcast += readl(base + NvRegTxBroadcast); base 2100 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 2105 drivers/net/ethernet/nvidia/forcedeth.c reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK; base 2112 drivers/net/ethernet/nvidia/forcedeth.c tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START; base 2116 drivers/net/ethernet/nvidia/forcedeth.c writel(reg, base + NvRegSlotTime); base 2149 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 2193 drivers/net/ethernet/nvidia/forcedeth.c writel(temp, base + NvRegBackOffControl); base 2202 drivers/net/ethernet/nvidia/forcedeth.c writel(temp, base + NvRegBackOffControl); base 2706 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 2712 drivers/net/ethernet/nvidia/forcedeth.c status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; base 2714 drivers/net/ethernet/nvidia/forcedeth.c status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; base 2728 drivers/net/ethernet/nvidia/forcedeth.c readl(base + i + 0), readl(base + i + 4), base 2729 drivers/net/ethernet/nvidia/forcedeth.c readl(base + i + 8), readl(base + i + 12), base 2730 drivers/net/ethernet/nvidia/forcedeth.c readl(base + i + 16), readl(base + i + 20), base 2731 drivers/net/ethernet/nvidia/forcedeth.c readl(base + i + 24), readl(base + i + 28)); base 3075 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3099 drivers/net/ethernet/nvidia/forcedeth.c writel(np->rx_buf_sz, base + NvRegOffloadConfig); base 3102 drivers/net/ethernet/nvidia/forcedeth.c base + NvRegRingSizes); base 3103 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 3105 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 3120 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3127 drivers/net/ethernet/nvidia/forcedeth.c writel(mac[0], base + NvRegMacAddrA); base 3128 drivers/net/ethernet/nvidia/forcedeth.c writel(mac[1], base + NvRegMacAddrB); base 3175 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3178 drivers/net/ethernet/nvidia/forcedeth.c u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX; base 3223 drivers/net/ethernet/nvidia/forcedeth.c writel(addr[0], base + NvRegMulticastAddrA); base 3224 drivers/net/ethernet/nvidia/forcedeth.c writel(addr[1], base + NvRegMulticastAddrB); base 3225 drivers/net/ethernet/nvidia/forcedeth.c writel(mask[0], base + NvRegMulticastMaskA); base 3226 drivers/net/ethernet/nvidia/forcedeth.c writel(mask[1], base + NvRegMulticastMaskB); base 3227 drivers/net/ethernet/nvidia/forcedeth.c writel(pff, base + NvRegPacketFilterFlags); base 3235 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3240 drivers/net/ethernet/nvidia/forcedeth.c u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX; base 3242 drivers/net/ethernet/nvidia/forcedeth.c writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags); base 3245 drivers/net/ethernet/nvidia/forcedeth.c writel(pff, base + NvRegPacketFilterFlags); base 3249 drivers/net/ethernet/nvidia/forcedeth.c u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX; base 3257 drivers/net/ethernet/nvidia/forcedeth.c writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit); base 3259 drivers/net/ethernet/nvidia/forcedeth.c writel(pause_enable, base + NvRegTxPauseFrame); base 3260 drivers/net/ethernet/nvidia/forcedeth.c writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); base 3263 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); base 3264 drivers/net/ethernet/nvidia/forcedeth.c writel(regmisc, base + NvRegMisc1); base 3272 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3283 drivers/net/ethernet/nvidia/forcedeth.c phyreg = readl(base + NvRegSlotTime); base 3291 drivers/net/ethernet/nvidia/forcedeth.c writel(phyreg, base + NvRegSlotTime); base 3294 drivers/net/ethernet/nvidia/forcedeth.c phyreg = readl(base + NvRegPhyInterface); base 3303 drivers/net/ethernet/nvidia/forcedeth.c writel(phyreg, base + NvRegPhyInterface); base 3314 drivers/net/ethernet/nvidia/forcedeth.c writel(txreg, base + NvRegTxDeferral); base 3325 drivers/net/ethernet/nvidia/forcedeth.c writel(txreg, base + NvRegTxWatermark); base 3328 drivers/net/ethernet/nvidia/forcedeth.c base + NvRegMisc1); base 3329 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 3330 drivers/net/ethernet/nvidia/forcedeth.c writel(np->linkspeed, base + NvRegLinkSpeed); base 3331 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 3348 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3456 drivers/net/ethernet/nvidia/forcedeth.c if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) { base 3460 drivers/net/ethernet/nvidia/forcedeth.c if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { base 3466 drivers/net/ethernet/nvidia/forcedeth.c phyreg = readl(base + NvRegSlotTime); base 3473 drivers/net/ethernet/nvidia/forcedeth.c writel(phyreg, base + NvRegSlotTime); base 3476 drivers/net/ethernet/nvidia/forcedeth.c phyreg = readl(base + NvRegPhyInterface); base 3484 drivers/net/ethernet/nvidia/forcedeth.c writel(phyreg, base + NvRegPhyInterface); base 3506 drivers/net/ethernet/nvidia/forcedeth.c writel(txreg, base + NvRegTxDeferral); base 3516 drivers/net/ethernet/nvidia/forcedeth.c writel(txreg, base + NvRegTxWatermark); base 3519 drivers/net/ethernet/nvidia/forcedeth.c base + NvRegMisc1); base 3520 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 3521 drivers/net/ethernet/nvidia/forcedeth.c writel(np->linkspeed, base + NvRegLinkSpeed); base 3522 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 3588 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3591 drivers/net/ethernet/nvidia/forcedeth.c miistat = readl(base + NvRegMIIStatus); base 3592 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); base 3605 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = np->base; base 3607 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMSIIrqMask); base 3608 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); base 3644 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3647 drivers/net/ethernet/nvidia/forcedeth.c np->events = readl(base + NvRegIrqStatus); base 3648 drivers/net/ethernet/nvidia/forcedeth.c writel(np->events, base + NvRegIrqStatus); base 3650 drivers/net/ethernet/nvidia/forcedeth.c np->events = readl(base + NvRegMSIXIrqStatus); base 3651 drivers/net/ethernet/nvidia/forcedeth.c writel(np->events, base + NvRegMSIXIrqStatus); base 3662 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegIrqMask); base 3677 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3680 drivers/net/ethernet/nvidia/forcedeth.c np->events = readl(base + NvRegIrqStatus); base 3681 drivers/net/ethernet/nvidia/forcedeth.c writel(np->events, base + NvRegIrqStatus); base 3683 drivers/net/ethernet/nvidia/forcedeth.c np->events = readl(base + NvRegMSIXIrqStatus); base 3684 drivers/net/ethernet/nvidia/forcedeth.c writel(np->events, base + NvRegMSIXIrqStatus); base 3695 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegIrqMask); base 3706 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3712 drivers/net/ethernet/nvidia/forcedeth.c events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; base 3713 drivers/net/ethernet/nvidia/forcedeth.c writel(events, base + NvRegMSIXIrqStatus); base 3725 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); base 3726 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 3747 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3809 drivers/net/ethernet/nvidia/forcedeth.c writel(np->irqmask, base + NvRegIrqMask); base 3818 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3824 drivers/net/ethernet/nvidia/forcedeth.c events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; base 3825 drivers/net/ethernet/nvidia/forcedeth.c writel(events, base + NvRegMSIXIrqStatus); base 3842 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); base 3843 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 3863 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3869 drivers/net/ethernet/nvidia/forcedeth.c events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; base 3870 drivers/net/ethernet/nvidia/forcedeth.c writel(events, base + NvRegMSIXIrqStatus); base 3894 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); base 3895 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 3908 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); base 3909 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 3930 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3934 drivers/net/ethernet/nvidia/forcedeth.c events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; base 3935 drivers/net/ethernet/nvidia/forcedeth.c writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus); base 3937 drivers/net/ethernet/nvidia/forcedeth.c events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; base 3938 drivers/net/ethernet/nvidia/forcedeth.c writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); base 3940 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 3955 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 3967 drivers/net/ethernet/nvidia/forcedeth.c writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); base 3974 drivers/net/ethernet/nvidia/forcedeth.c writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); base 3980 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 4041 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMSIXMap0); base 4042 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMSIXMap1); base 4060 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMSIXMap0); base 4061 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMSIXMap1); base 4081 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMSIMap0); base 4082 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMSIMap1); base 4084 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); base 4125 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 4181 drivers/net/ethernet/nvidia/forcedeth.c writel(np->rx_buf_sz, base + NvRegOffloadConfig); base 4184 drivers/net/ethernet/nvidia/forcedeth.c base + NvRegRingSizes); base 4185 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 4187 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 4190 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); base 4192 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); base 4202 drivers/net/ethernet/nvidia/forcedeth.c writel(mask, base + NvRegIrqMask); base 4203 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 4279 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 4290 drivers/net/ethernet/nvidia/forcedeth.c writel(flags, base + NvRegWakeUpFlags); base 4305 drivers/net/ethernet/nvidia/forcedeth.c cmd->base.port = PORT_MII; base 4331 drivers/net/ethernet/nvidia/forcedeth.c cmd->base.duplex = DUPLEX_HALF; base 4333 drivers/net/ethernet/nvidia/forcedeth.c cmd->base.duplex = DUPLEX_FULL; base 4336 drivers/net/ethernet/nvidia/forcedeth.c cmd->base.duplex = DUPLEX_UNKNOWN; base 4338 drivers/net/ethernet/nvidia/forcedeth.c cmd->base.speed = speed; base 4339 drivers/net/ethernet/nvidia/forcedeth.c cmd->base.autoneg = np->autoneg; base 4366 drivers/net/ethernet/nvidia/forcedeth.c cmd->base.phy_address = np->phyaddr; base 4382 drivers/net/ethernet/nvidia/forcedeth.c u32 speed = cmd->base.speed; base 4388 drivers/net/ethernet/nvidia/forcedeth.c if (cmd->base.port != PORT_MII) base 4390 drivers/net/ethernet/nvidia/forcedeth.c if (cmd->base.phy_address != np->phyaddr) { base 4395 drivers/net/ethernet/nvidia/forcedeth.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 4406 drivers/net/ethernet/nvidia/forcedeth.c } else if (cmd->base.autoneg == AUTONEG_DISABLE) { base 4412 drivers/net/ethernet/nvidia/forcedeth.c if (cmd->base.duplex != DUPLEX_HALF && base 4413 drivers/net/ethernet/nvidia/forcedeth.c cmd->base.duplex != DUPLEX_FULL) base 4443 drivers/net/ethernet/nvidia/forcedeth.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 4495 drivers/net/ethernet/nvidia/forcedeth.c if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_HALF) base 4497 drivers/net/ethernet/nvidia/forcedeth.c if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_FULL) base 4499 drivers/net/ethernet/nvidia/forcedeth.c if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_HALF) base 4501 drivers/net/ethernet/nvidia/forcedeth.c if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_FULL) base 4562 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 4569 drivers/net/ethernet/nvidia/forcedeth.c rbuf[i] = readl(base + i*sizeof(u32)); base 4634 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 4734 drivers/net/ethernet/nvidia/forcedeth.c writel(np->rx_buf_sz, base + NvRegOffloadConfig); base 4737 drivers/net/ethernet/nvidia/forcedeth.c base + NvRegRingSizes); base 4738 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 4740 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 4923 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 4942 drivers/net/ethernet/nvidia/forcedeth.c writel(np->txrxctl_bits, base + NvRegTxRxControl); base 5008 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 5013 drivers/net/ethernet/nvidia/forcedeth.c orig_read = readl(base + nv_registers_test[i].reg); base 5018 drivers/net/ethernet/nvidia/forcedeth.c writel(orig_read, base + nv_registers_test[i].reg); base 5020 drivers/net/ethernet/nvidia/forcedeth.c new_read = readl(base + nv_registers_test[i].reg); base 5027 drivers/net/ethernet/nvidia/forcedeth.c writel(orig_read, base + nv_registers_test[i].reg); base 5037 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 5045 drivers/net/ethernet/nvidia/forcedeth.c save_poll_interval = readl(base+NvRegPollingInterval); base 5059 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); base 5060 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); base 5076 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); base 5078 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); base 5087 drivers/net/ethernet/nvidia/forcedeth.c writel(save_poll_interval, base + NvRegPollingInterval); base 5088 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); base 5100 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 5113 drivers/net/ethernet/nvidia/forcedeth.c filter_flags = readl(base + NvRegPacketFilterFlags); base 5114 drivers/net/ethernet/nvidia/forcedeth.c misc1_flags = readl(base + NvRegMisc1); base 5124 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MISC1_FORCE, base + NvRegMisc1); base 5125 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags); base 5128 drivers/net/ethernet/nvidia/forcedeth.c writel(np->rx_buf_sz, base + NvRegOffloadConfig); base 5131 drivers/net/ethernet/nvidia/forcedeth.c base + NvRegRingSizes); base 5132 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 5215 drivers/net/ethernet/nvidia/forcedeth.c writel(misc1_flags, base + NvRegMisc1); base 5216 drivers/net/ethernet/nvidia/forcedeth.c writel(filter_flags, base + NvRegPacketFilterFlags); base 5226 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 5246 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); base 5248 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); base 5287 drivers/net/ethernet/nvidia/forcedeth.c writel(np->rx_buf_sz, base + NvRegOffloadConfig); base 5290 drivers/net/ethernet/nvidia/forcedeth.c base + NvRegRingSizes); base 5291 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 5293 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 5340 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 5345 drivers/net/ethernet/nvidia/forcedeth.c mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK; base 5355 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl = readl(base + NvRegTransmitterControl); base 5357 drivers/net/ethernet/nvidia/forcedeth.c writel(tx_ctrl, base + NvRegTransmitterControl); base 5360 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl = readl(base + NvRegTransmitterControl); base 5375 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 5380 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl = readl(base + NvRegTransmitterControl); base 5382 drivers/net/ethernet/nvidia/forcedeth.c writel(tx_ctrl, base + NvRegTransmitterControl); base 5391 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 5392 drivers/net/ethernet/nvidia/forcedeth.c u32 data_ready = readl(base + NvRegTransmitterControl); base 5397 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion); base 5398 drivers/net/ethernet/nvidia/forcedeth.c writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl); base 5401 drivers/net/ethernet/nvidia/forcedeth.c data_ready2 = readl(base + NvRegTransmitterControl); base 5412 drivers/net/ethernet/nvidia/forcedeth.c np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION; base 5420 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 5433 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); base 5434 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMulticastAddrB); base 5435 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); base 5436 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); base 5437 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegPacketFilterFlags); base 5439 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegTransmitterControl); base 5440 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegReceiverControl); base 5442 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegAdapterControl); base 5445 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); base 5451 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegLinkSpeed); base 5452 drivers/net/ethernet/nvidia/forcedeth.c writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); base 5454 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegUnknownSetupReg6); base 5461 drivers/net/ethernet/nvidia/forcedeth.c base + NvRegRingSizes); base 5463 drivers/net/ethernet/nvidia/forcedeth.c writel(np->linkspeed, base + NvRegLinkSpeed); base 5465 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); base 5467 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); base 5468 drivers/net/ethernet/nvidia/forcedeth.c writel(np->txrxctl_bits, base + NvRegTxRxControl); base 5469 drivers/net/ethernet/nvidia/forcedeth.c writel(np->vlanctl_bits, base + NvRegVlanControl); base 5470 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 5471 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); base 5478 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMIIMask); base 5479 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); base 5480 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); base 5482 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); base 5483 drivers/net/ethernet/nvidia/forcedeth.c writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); base 5484 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); base 5485 drivers/net/ethernet/nvidia/forcedeth.c writel(np->rx_buf_sz, base + NvRegOffloadConfig); base 5487 drivers/net/ethernet/nvidia/forcedeth.c writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); base 5492 drivers/net/ethernet/nvidia/forcedeth.c writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime); base 5496 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime); base 5498 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime); base 5502 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); base 5503 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); base 5506 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); base 5508 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); base 5510 drivers/net/ethernet/nvidia/forcedeth.c writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); base 5511 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); base 5513 drivers/net/ethernet/nvidia/forcedeth.c base + NvRegAdapterControl); base 5514 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); base 5515 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask); base 5517 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); base 5519 drivers/net/ethernet/nvidia/forcedeth.c i = readl(base + NvRegPowerState); base 5521 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); base 5523 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 5525 drivers/net/ethernet/nvidia/forcedeth.c writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); base 5528 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 5529 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); base 5530 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); base 5531 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 5540 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); base 5541 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMulticastAddrB); base 5542 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); base 5543 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); base 5544 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); base 5548 drivers/net/ethernet/nvidia/forcedeth.c readl(base + NvRegMIIStatus); base 5549 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); base 5590 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base; base 5609 drivers/net/ethernet/nvidia/forcedeth.c base = get_hwbase(dev); base 5611 drivers/net/ethernet/nvidia/forcedeth.c pci_push(base); base 5621 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); base 5674 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base; base 5805 drivers/net/ethernet/nvidia/forcedeth.c np->base = ioremap(addr, np->register_size); base 5806 drivers/net/ethernet/nvidia/forcedeth.c if (!np->base) base 5849 drivers/net/ethernet/nvidia/forcedeth.c base = get_hwbase(dev); base 5850 drivers/net/ethernet/nvidia/forcedeth.c np->orig_mac[0] = readl(base + NvRegMacAddrA); base 5851 drivers/net/ethernet/nvidia/forcedeth.c np->orig_mac[1] = readl(base + NvRegMacAddrB); base 5854 drivers/net/ethernet/nvidia/forcedeth.c txreg = readl(base + NvRegTransmitPoll); base 5887 drivers/net/ethernet/nvidia/forcedeth.c writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); base 5910 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegWakeUpFlags); base 5917 drivers/net/ethernet/nvidia/forcedeth.c powerstate = readl(base + NvRegPowerState2); base 5922 drivers/net/ethernet/nvidia/forcedeth.c writel(powerstate, base + NvRegPowerState2); base 5978 drivers/net/ethernet/nvidia/forcedeth.c writel(0, base + NvRegMIIMask); base 5979 drivers/net/ethernet/nvidia/forcedeth.c phystate = readl(base + NvRegAdapterControl); base 5983 drivers/net/ethernet/nvidia/forcedeth.c writel(phystate, base + NvRegAdapterControl); base 5985 drivers/net/ethernet/nvidia/forcedeth.c writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); base 5989 drivers/net/ethernet/nvidia/forcedeth.c if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) && base 5990 drivers/net/ethernet/nvidia/forcedeth.c (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) && base 5995 drivers/net/ethernet/nvidia/forcedeth.c np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; base 5998 drivers/net/ethernet/nvidia/forcedeth.c ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == base 6103 drivers/net/ethernet/nvidia/forcedeth.c writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); base 6146 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 6151 drivers/net/ethernet/nvidia/forcedeth.c writel(np->orig_mac[0], base + NvRegMacAddrA); base 6152 drivers/net/ethernet/nvidia/forcedeth.c writel(np->orig_mac[1], base + NvRegMacAddrB); base 6153 drivers/net/ethernet/nvidia/forcedeth.c writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV, base 6154 drivers/net/ethernet/nvidia/forcedeth.c base + NvRegTransmitPoll); base 6186 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 6197 drivers/net/ethernet/nvidia/forcedeth.c np->saved_config_space[i] = readl(base + i*sizeof(u32)); base 6207 drivers/net/ethernet/nvidia/forcedeth.c u8 __iomem *base = get_hwbase(dev); base 6212 drivers/net/ethernet/nvidia/forcedeth.c writel(np->saved_config_space[i], base+i*sizeof(u32)); base 94 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c ecmd->base.speed = SPEED_UNKNOWN; base 113 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c u32 speed = ecmd->base.speed; base 125 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c copy_ecmd.base.speed = speed; base 126 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c copy_ecmd.base.duplex = DUPLEX_FULL; base 134 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c hw->mac.link_duplex = copy_ecmd.base.duplex; base 138 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c hw->mac.autoneg = copy_ecmd.base.autoneg; base 507 drivers/net/ethernet/packetengines/hamachi.c void __iomem *base; base 586 drivers/net/ethernet/packetengines/hamachi.c unsigned long base; base 605 drivers/net/ethernet/packetengines/hamachi.c base = pci_resource_start(pdev, 0); base 607 drivers/net/ethernet/packetengines/hamachi.c base |= (pci_resource_start(pdev, 1) << 32); base 617 drivers/net/ethernet/packetengines/hamachi.c ioaddr = ioremap(base, 0x400); base 684 drivers/net/ethernet/packetengines/hamachi.c hmp->base = ioaddr; base 814 drivers/net/ethernet/packetengines/hamachi.c void __iomem *ioaddr = hmp->base; base 832 drivers/net/ethernet/packetengines/hamachi.c void __iomem *ioaddr = hmp->base; base 852 drivers/net/ethernet/packetengines/hamachi.c void __iomem *ioaddr = hmp->base; base 1024 drivers/net/ethernet/packetengines/hamachi.c void __iomem *ioaddr = hmp->base; base 1049 drivers/net/ethernet/packetengines/hamachi.c void __iomem *ioaddr = hmp->base; base 1222 drivers/net/ethernet/packetengines/hamachi.c status=readw(hmp->base + TxStatus); base 1224 drivers/net/ethernet/packetengines/hamachi.c writew(0x0001, hmp->base + TxCmd); base 1260 drivers/net/ethernet/packetengines/hamachi.c status=readw(hmp->base + TxStatus); base 1262 drivers/net/ethernet/packetengines/hamachi.c writew(0x0001, hmp->base + TxCmd); base 1293 drivers/net/ethernet/packetengines/hamachi.c void __iomem *ioaddr = hmp->base; base 1603 drivers/net/ethernet/packetengines/hamachi.c if (readw(hmp->base + RxStatus) & 0x0002) base 1604 drivers/net/ethernet/packetengines/hamachi.c writew(0x0001, hmp->base + RxCmd); base 1614 drivers/net/ethernet/packetengines/hamachi.c void __iomem *ioaddr = hmp->base; base 1648 drivers/net/ethernet/packetengines/hamachi.c void __iomem *ioaddr = hmp->base; base 1734 drivers/net/ethernet/packetengines/hamachi.c void __iomem *ioaddr = hmp->base; base 1770 drivers/net/ethernet/packetengines/hamachi.c void __iomem *ioaddr = hmp->base; base 1877 drivers/net/ethernet/packetengines/hamachi.c writel(d[0], np->base + TxIntrCtrl); base 1878 drivers/net/ethernet/packetengines/hamachi.c writel(d[1], np->base + RxIntrCtrl); base 1880 drivers/net/ethernet/packetengines/hamachi.c (u32) readl(np->base + TxIntrCtrl), base 1881 drivers/net/ethernet/packetengines/hamachi.c (u32) readl(np->base + RxIntrCtrl)); base 1907 drivers/net/ethernet/packetengines/hamachi.c iounmap(hmp->base); base 338 drivers/net/ethernet/packetengines/yellowfin.c void __iomem *base; base 435 drivers/net/ethernet/packetengines/yellowfin.c np->base = ioaddr; base 568 drivers/net/ethernet/packetengines/yellowfin.c void __iomem *ioaddr = yp->base; base 650 drivers/net/ethernet/packetengines/yellowfin.c void __iomem *ioaddr = yp->base; base 683 drivers/net/ethernet/packetengines/yellowfin.c void __iomem *ioaddr = yp->base; base 710 drivers/net/ethernet/packetengines/yellowfin.c iowrite32(0x10001000, yp->base + TxCtrl); base 870 drivers/net/ethernet/packetengines/yellowfin.c iowrite32(0x10001000, yp->base + TxCtrl); base 895 drivers/net/ethernet/packetengines/yellowfin.c ioaddr = yp->base; base 1188 drivers/net/ethernet/packetengines/yellowfin.c void __iomem *ioaddr = yp->base; base 1280 drivers/net/ethernet/packetengines/yellowfin.c void __iomem *ioaddr = yp->base; base 1340 drivers/net/ethernet/packetengines/yellowfin.c void __iomem *ioaddr = np->base; base 1388 drivers/net/ethernet/packetengines/yellowfin.c pci_iounmap(pdev, np->base); base 154 drivers/net/ethernet/pensando/ionic/ionic_debugfs.c desc_blob->data = q->base; base 181 drivers/net/ethernet/pensando/ionic/ionic_debugfs.c desc_blob->data = cq->base; base 199 drivers/net/ethernet/pensando/ionic/ionic_debugfs.c intr_ctrl_regset->base = &idev->intr_ctrl[intr->index]; base 331 drivers/net/ethernet/pensando/ionic/ionic_dev.c void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa) base 336 drivers/net/ethernet/pensando/ionic/ionic_dev.c cq->base = base; base 340 drivers/net/ethernet/pensando/ionic/ionic_dev.c cur->cq_desc = base + (i * cq->desc_size); base 416 drivers/net/ethernet/pensando/ionic/ionic_dev.c void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) base 421 drivers/net/ethernet/pensando/ionic/ionic_dev.c q->base = base; base 425 drivers/net/ethernet/pensando/ionic/ionic_dev.c cur->desc = base + (i * q->desc_size); base 428 drivers/net/ethernet/pensando/ionic/ionic_dev.c void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) base 433 drivers/net/ethernet/pensando/ionic/ionic_dev.c q->sg_base = base; base 437 drivers/net/ethernet/pensando/ionic/ionic_dev.c cur->sg_desc = base + (i * q->sg_desc_size); base 181 drivers/net/ethernet/pensando/ionic/ionic_dev.h void *base; base 205 drivers/net/ethernet/pensando/ionic/ionic_dev.h void *base; base 279 drivers/net/ethernet/pensando/ionic/ionic_dev.h void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa); base 291 drivers/net/ethernet/pensando/ionic/ionic_dev.h void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa); base 292 drivers/net/ethernet/pensando/ionic/ionic_dev.h void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa); base 225 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c ks->base.port = PORT_DA; base 227 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c ks->base.port = PORT_FIBRE; base 229 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c ks->base.port = PORT_NONE; base 231 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c if (ks->base.port != PORT_NONE) { base 232 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c ks->base.speed = le32_to_cpu(lif->info->status.link_speed); base 235 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c ks->base.duplex = DUPLEX_FULL; base 237 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c ks->base.duplex = DUPLEX_UNKNOWN; base 244 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c ks->base.autoneg = AUTONEG_ENABLE; base 265 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c if (ks->base.autoneg != idev->port_info->config.an_enable) { base 267 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c ionic_dev_cmd_port_autoneg(idev, ks->base.autoneg); base 275 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c if (ks->base.speed != le32_to_cpu(idev->port_info->config.speed)) { base 277 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c ionic_dev_cmd_port_speed(idev, ks->base.speed); base 277 drivers/net/ethernet/pensando/ionic/ionic_lif.c dma_free_coherent(dev, qcq->total_size, qcq->base, qcq->base_pa); base 278 drivers/net/ethernet/pensando/ionic/ionic_lif.c qcq->base = NULL; base 434 drivers/net/ethernet/pensando/ionic/ionic_lif.c new->base = dma_alloc_coherent(dev, total_size, &new->base_pa, base 436 drivers/net/ethernet/pensando/ionic/ionic_lif.c if (!new->base) { base 444 drivers/net/ethernet/pensando/ionic/ionic_lif.c q_base = new->base; base 62 drivers/net/ethernet/pensando/ionic/ionic_lif.h void *base; base 104 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.port = PORT_TP; base 106 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.speed = adapter->link_speed; base 107 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.duplex = adapter->link_duplex; base 108 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.autoneg = adapter->link_autoneg; base 123 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.speed = adapter->link_speed; base 124 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.autoneg = adapter->link_autoneg; base 125 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.duplex = adapter->link_duplex; base 129 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.port = PORT_TP; base 135 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.speed = P3_LINK_SPEED_MHZ * base 138 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.speed = SPEED_10000; base 140 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 141 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 146 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.phy_address = adapter->physical_port; base 163 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.port = PORT_TP; base 164 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.autoneg = (adapter->ahw.board_type == base 175 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.port = PORT_MII; base 176 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 190 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.port = PORT_FIBRE; base 191 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 195 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.autoneg = AUTONEG_DISABLE; base 199 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.port = PORT_FIBRE; base 206 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.port = PORT_TP; base 221 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.port = PORT_FIBRE; base 226 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.port = PORT_TP; base 229 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.port = -1; base 234 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 235 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 251 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c u32 speed = cmd->base.speed; base 260 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c ret = nx_fw_cmd_set_gbe_port(adapter, speed, cmd->base.duplex, base 261 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c cmd->base.autoneg); base 268 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c adapter->link_duplex = cmd->base.duplex; base 269 drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c adapter->link_autoneg = cmd->base.autoneg; base 968 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, base 975 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c addr = base; base 2981 drivers/net/ethernet/qlogic/qed/qed_hsi.h u32 base; base 4247 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base) base 4252 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[1].base + ((port_id) * IRO[1].m1)) base 4257 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[2].base + ((port_id) * IRO[2].m1)) base 4262 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[3].base + ((vf_id) * IRO[3].m1)) base 4267 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[4].base + ((pf_id) * IRO[4].m1)) base 4272 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[5].base + ((pf_id) * IRO[5].m1)) base 4277 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[6].base + ((queue_zone_id) * IRO[6].m1)) base 4282 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[7].base + ((queue_zone_id) * IRO[7].m1)) base 4286 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[8].base) base 4290 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base) base 4294 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base) base 4298 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base) base 4302 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base) base 4306 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define USTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base) base 4311 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1)) base 4316 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1)) base 4321 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1)) base 4326 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1)) base 4331 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[18].base + ((stat_counter_id) * IRO[18].m1)) base 4336 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[19].base + ((queue_id) * IRO[19].m1)) base 4343 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2)) base 4347 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base) base 4352 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[22].base + ((pf_id) * IRO[22].m1)) base 4357 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[23].base + ((stat_counter_id) * IRO[23].m1)) base 4362 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[24].base + ((pf_id) * IRO[24].m1)) base 4367 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[25].base + ((stat_counter_id) * IRO[25].m1)) base 4372 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[26].base + ((pf_id) * IRO[26].m1)) base 4377 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[27].base + ((eth_type_id) * IRO[27].m1)) base 4381 drivers/net/ethernet/qlogic/qed/qed_hsi.h #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base) base 4386 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[29].base + ((pf_id) * IRO[29].m1)) base 4393 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[30].base + ((pf_id) * IRO[30].m1)) base 4398 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[31].base + ((queue_id) * IRO[31].m1)) base 4403 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[32].base + ((rss_id) * IRO[32].m1)) base 4408 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[33].base + ((rss_id) * IRO[33].m1)) base 4413 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[34].base + ((pf_id) * IRO[34].m1)) base 4418 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[35].base + ((cmdq_queue_id) * IRO[35].m1)) base 4425 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2)) base 4430 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[37].base + ((func_id) * IRO[37].m1) + ((bdq_id) * IRO[37].m2)) base 4435 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[38].base + ((pf_id) * IRO[38].m1)) base 4440 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[39].base + ((pf_id) * IRO[39].m1)) base 4445 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[40].base + ((pf_id) * IRO[40].m1)) base 4450 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[41].base + ((pf_id) * IRO[41].m1)) base 4455 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[42].base + ((pf_id) * IRO[42].m1)) base 4460 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[43].base + ((pf_id) * IRO[43].m1)) base 4465 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[44].base + ((pf_id) * IRO[44].m1)) base 4470 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[45].base + ((pf_id) * IRO[45].m1)) base 4475 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1)) base 4480 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[47].base + ((rdma_stat_counter_id) * IRO[47].m1)) base 4485 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[48].base + ((pf_id) * IRO[48].m1)) base 4490 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[49].base + ((pf_id) * IRO[49].m1)) base 4495 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[50].base + ((pf_id) * IRO[50].m1)) base 4500 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[51].base + ((pf_id) * IRO[51].m1)) base 4505 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[52].base + ((pf_id) * IRO[52].m1)) base 4510 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[53].base + ((pf_id) * IRO[53].m1)) base 4515 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[54].base + ((pf_id) * IRO[54].m1)) base 4520 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[55].base + ((roce_pf_id) * IRO[55].m1)) base 4525 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[56].base + ((roce_pf_id) * IRO[56].m1)) base 4530 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[57].base + ((roce_pf_id) * IRO[57].m1)) base 4535 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[58].base + ((roce_pf_id) * IRO[58].m1)) base 4540 drivers/net/ethernet/qlogic/qed/qed_hsi.h (IRO[59].base + ((roce_pf_id) * IRO[59].m1)) base 4509 drivers/net/ethernet/qlogic/qed/qed_sriov.c u16 base, i; base 4515 drivers/net/ethernet/qlogic/qed/qed_sriov.c base = FEAT_NUM(hwfn, QED_PF_L2_QUE) + vfid * params->num_queues; base 4519 drivers/net/ethernet/qlogic/qed/qed_sriov.c params->req_rx_queue[i] = base + i; base 4520 drivers/net/ethernet/qlogic/qed/qed_sriov.c params->req_tx_queue[i] = base + i; base 81 drivers/net/ethernet/qlogic/qede/qede_ethtool.c #define QEDE_STAT_OFFSET(stat_name, type, base) \ base 82 drivers/net/ethernet/qlogic/qede/qede_ethtool.c (offsetof(type, stat_name) + (base)) base 84 drivers/net/ethernet/qlogic/qede/qede_ethtool.c #define _QEDE_STAT(stat_name, type, base, attr) \ base 85 drivers/net/ethernet/qlogic/qede/qede_ethtool.c {QEDE_STAT_OFFSET(stat_name, type, base), \ base 493 drivers/net/ethernet/qlogic/qede/qede_ethtool.c struct ethtool_link_settings *base = &cmd->base; base 512 drivers/net/ethernet/qlogic/qede/qede_ethtool.c base->speed = current_link.speed; base 513 drivers/net/ethernet/qlogic/qede/qede_ethtool.c base->duplex = current_link.duplex; base 515 drivers/net/ethernet/qlogic/qede/qede_ethtool.c base->speed = SPEED_UNKNOWN; base 516 drivers/net/ethernet/qlogic/qede/qede_ethtool.c base->duplex = DUPLEX_UNKNOWN; base 521 drivers/net/ethernet/qlogic/qede/qede_ethtool.c base->port = current_link.port; base 522 drivers/net/ethernet/qlogic/qede/qede_ethtool.c base->autoneg = (current_link.autoneg) ? AUTONEG_ENABLE : base 531 drivers/net/ethernet/qlogic/qede/qede_ethtool.c const struct ethtool_link_settings *base = &cmd->base; base 547 drivers/net/ethernet/qlogic/qede/qede_ethtool.c if (base->autoneg == AUTONEG_ENABLE) { base 559 drivers/net/ethernet/qlogic/qede/qede_ethtool.c params.forced_speed = base->speed; base 560 drivers/net/ethernet/qlogic/qede/qede_ethtool.c switch (base->speed) { base 643 drivers/net/ethernet/qlogic/qede/qede_ethtool.c DP_INFO(edev, "Unsupported speed %u\n", base->speed); base 1717 drivers/net/ethernet/qlogic/qla3xxx.c cmd->base.port = PORT_FIBRE; base 1719 drivers/net/ethernet/qlogic/qla3xxx.c cmd->base.port = PORT_TP; base 1720 drivers/net/ethernet/qlogic/qla3xxx.c cmd->base.phy_address = qdev->PHYAddr; base 1723 drivers/net/ethernet/qlogic/qla3xxx.c cmd->base.autoneg = ql_get_auto_cfg_status(qdev); base 1724 drivers/net/ethernet/qlogic/qla3xxx.c cmd->base.speed = ql_get_speed(qdev); base 1725 drivers/net/ethernet/qlogic/qla3xxx.c cmd->base.duplex = ql_get_full_dup(qdev); base 287 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c void __iomem *base; base 290 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c base = adapter->ahw->pci_base0 + base 292 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c writel(addr, base); base 293 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c val = readl(base); base 3313 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c ecmd->base.speed = ahw->link_speed; base 3314 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c ecmd->base.duplex = ahw->link_duplex; base 3315 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c ecmd->base.autoneg = ahw->link_autoneg; base 3317 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c ecmd->base.speed = SPEED_UNKNOWN; base 3318 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c ecmd->base.duplex = DUPLEX_UNKNOWN; base 3319 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c ecmd->base.autoneg = AUTONEG_DISABLE; base 3331 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c if (ecmd->base.autoneg == AUTONEG_ENABLE) { base 3366 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c ecmd->base.port = PORT_FIBRE; base 3371 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c ecmd->base.port = PORT_TP; base 3376 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c ecmd->base.port = PORT_DA; base 3381 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c ecmd->base.port = PORT_OTHER; base 3384 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c ecmd->base.phy_address = ahw->physical_port; base 3402 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c if (ecmd->base.duplex == DUPLEX_HALF) { base 3408 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c if (ecmd->base.autoneg) { base 3415 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c switch (ecmd->base.speed) { base 311 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.speed = adapter->ahw->link_speed; base 312 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.duplex = adapter->ahw->link_duplex; base 313 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.autoneg = adapter->ahw->link_autoneg; base 335 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.speed = ahw->link_speed; base 336 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.autoneg = ahw->link_autoneg; base 337 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.duplex = ahw->link_duplex; base 341 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.speed = SPEED_UNKNOWN; base 342 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.duplex = DUPLEX_UNKNOWN; base 343 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.autoneg = AUTONEG_DISABLE; base 348 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.phy_address = adapter->ahw->physical_port; base 362 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.port = PORT_TP; base 363 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.autoneg = adapter->ahw->link_autoneg; base 370 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.port = PORT_MII; base 371 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.autoneg = AUTONEG_DISABLE; base 384 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.port = PORT_FIBRE; base 385 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.autoneg = AUTONEG_DISABLE; base 389 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.autoneg = AUTONEG_DISABLE; base 393 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.port = PORT_FIBRE; base 397 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.autoneg = AUTONEG_ENABLE; base 401 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.port = PORT_TP; base 416 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.port = PORT_FIBRE; base 421 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.port = PORT_TP; base 424 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c ecmd->base.port = PORT_OTHER; base 455 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c if (ecmd->base.duplex) base 458 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c if (ecmd->base.autoneg) base 461 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c switch (ecmd->base.speed) { base 504 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c adapter->ahw->link_speed = ecmd->base.speed; base 505 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c adapter->ahw->link_duplex = ecmd->base.duplex; base 506 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c adapter->ahw->link_autoneg = ecmd->base.autoneg; base 223 drivers/net/ethernet/qualcomm/emac/emac-ethtool.c val[i] = readl(adpt->base + emac_regs[i]); base 263 drivers/net/ethernet/qualcomm/emac/emac-mac.c mta = readl(adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2)); base 265 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(mta, adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2)); base 270 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(0, adpt->base + EMAC_HASH_TAB_REG0); base 271 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(0, adpt->base + EMAC_HASH_TAB_REG1); base 286 drivers/net/ethernet/qualcomm/emac/emac-mac.c mac = readl(adpt->base + EMAC_MAC_CTRL); base 298 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(mac, adpt->base + EMAC_MAC_CTRL); base 306 drivers/net/ethernet/qualcomm/emac/emac-mac.c adpt->base + EMAC_DESC_CTRL_1); base 309 drivers/net/ethernet/qualcomm/emac/emac-mac.c adpt->base + EMAC_DESC_CTRL_8); base 312 drivers/net/ethernet/qualcomm/emac/emac-mac.c adpt->base + EMAC_DESC_CTRL_9); base 316 drivers/net/ethernet/qualcomm/emac/emac-mac.c adpt->base + EMAC_DESC_CTRL_0); base 319 drivers/net/ethernet/qualcomm/emac/emac-mac.c adpt->base + EMAC_DESC_CTRL_2); base 321 drivers/net/ethernet/qualcomm/emac/emac-mac.c adpt->base + EMAC_DESC_CTRL_5); base 324 drivers/net/ethernet/qualcomm/emac/emac-mac.c adpt->base + EMAC_DESC_CTRL_3); base 326 drivers/net/ethernet/qualcomm/emac/emac-mac.c adpt->base + EMAC_DESC_CTRL_6); base 329 drivers/net/ethernet/qualcomm/emac/emac-mac.c adpt->base + EMAC_DESC_CTRL_4); base 331 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(0, adpt->base + EMAC_DESC_CTRL_11); base 336 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(1, adpt->base + EMAC_INTER_SRAM_PART9); base 345 drivers/net/ethernet/qualcomm/emac/emac-mac.c JUMBO_TASK_OFFLOAD_THRESHOLD_BMSK, adpt->base + EMAC_TXQ_CTRL_1); base 354 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_TXQ_CTRL_0); base 355 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + EMAC_TXQ_CTRL_2, base 368 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_RXQ_CTRL_0); base 370 drivers/net/ethernet/qualcomm/emac/emac-mac.c val = readl(adpt->base + EMAC_RXQ_CTRL_1); base 376 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_RXQ_CTRL_1); base 378 drivers/net/ethernet/qualcomm/emac/emac-mac.c val = readl(adpt->base + EMAC_RXQ_CTRL_2); base 382 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_RXQ_CTRL_2); base 384 drivers/net/ethernet/qualcomm/emac/emac-mac.c val = readl(adpt->base + EMAC_RXQ_CTRL_3); base 387 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_RXQ_CTRL_3); base 419 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(dma_ctrl, adpt->base + EMAC_DMA_CTRL); base 434 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(sta, adpt->base + EMAC_MAC_STA_ADDR0); base 438 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(sta, adpt->base + EMAC_MAC_STA_ADDR1); base 456 drivers/net/ethernet/qualcomm/emac/emac-mac.c adpt->base + EMAC_MAX_FRAM_LEN_CTRL); base 462 drivers/net/ethernet/qualcomm/emac/emac-mac.c val = readl(adpt->base + EMAC_AXI_MAST_CTRL); base 465 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(val, adpt->base + EMAC_AXI_MAST_CTRL); base 466 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(0, adpt->base + EMAC_CLK_GATE_CTRL); base 467 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(RX_UNCPL_INT_EN, adpt->base + EMAC_MISC_CTRL); base 474 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + EMAC_DMA_MAS_CTRL, 0, SOFT_RST); base 478 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + EMAC_DMA_MAS_CTRL, 0, INT_RD_CLR_EN); base 487 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + EMAC_TXQ_CTRL_0, 0, TXQ_EN); base 490 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + EMAC_RXQ_CTRL_0, 0, RXQ_EN); base 493 drivers/net/ethernet/qualcomm/emac/emac-mac.c mac = readl(adpt->base + EMAC_MAC_CTRL); base 560 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel_relaxed(mac, adpt->base + EMAC_MAC_CTRL); base 566 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel_relaxed(adpt->irq_mod, adpt->base + EMAC_IRQ_MOD_TIM_INIT); base 568 drivers/net/ethernet/qualcomm/emac/emac-mac.c IRQ_MODERATOR2_EN, adpt->base + EMAC_DMA_MAS_CTRL); base 572 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + EMAC_ATHR_HEADER_CTRL, base 578 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + EMAC_RXQ_CTRL_0, RXQ_EN, 0); base 579 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + EMAC_TXQ_CTRL_0, TXQ_EN, 0); base 580 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + EMAC_MAC_CTRL, TXEN | RXEN, 0); base 909 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + rx_q->produce_reg, base 951 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel((u32)~DIS_INT, adpt->base + EMAC_INT_STATUS); base 952 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(adpt->irq.mask, adpt->base + EMAC_INT_MASK); base 976 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(DIS_INT, adpt->base + EMAC_INT_STATUS); base 977 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(0, adpt->base + EMAC_INT_MASK); base 1098 drivers/net/ethernet/qualcomm/emac/emac-mac.c reg = readl_relaxed(adpt->base + rx_q->consume_reg); base 1161 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + rx_q->process_reg, base 1181 drivers/net/ethernet/qualcomm/emac/emac-mac.c u32 reg = readl_relaxed(adpt->base + tx_q->consume_reg); base 1476 drivers/net/ethernet/qualcomm/emac/emac-mac.c emac_reg_update32(adpt->base + tx_q->produce_reg, base 49 drivers/net/ethernet/qualcomm/emac/emac-phy.c emac_reg_update32(adpt->base + EMAC_PHY_STS, PHY_ADDR_BMSK, base 57 drivers/net/ethernet/qualcomm/emac/emac-phy.c writel(reg, adpt->base + EMAC_MDIO_CTRL); base 59 drivers/net/ethernet/qualcomm/emac/emac-phy.c if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg, base 72 drivers/net/ethernet/qualcomm/emac/emac-phy.c emac_reg_update32(adpt->base + EMAC_PHY_STS, PHY_ADDR_BMSK, base 81 drivers/net/ethernet/qualcomm/emac/emac-phy.c writel(reg, adpt->base + EMAC_MDIO_CTRL); base 83 drivers/net/ethernet/qualcomm/emac/emac-phy.c if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg, base 139 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c static void emac_reg_write_all(void __iomem *base, base 145 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c writel(itr->val, base + itr->offset); base 212 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c emac_reg_write_all(phy->base, physical_coding_sublayer_programming, base 214 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c emac_reg_write_all(phy->base, sysclk_refclk_setting, base 216 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c emac_reg_write_all(phy->base, pll_setting, ARRAY_SIZE(pll_setting)); base 217 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c emac_reg_write_all(phy->base, cdr_setting, ARRAY_SIZE(cdr_setting)); base 218 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c emac_reg_write_all(phy->base, tx_rx_setting, ARRAY_SIZE(tx_rx_setting)); base 221 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c writel(SERDES_START, phy->base + EMAC_SGMII_PHY_SERDES_START); base 224 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c if (readl(phy->base + EMAC_QSERDES_COM_RESET_SM) & READY) base 234 drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c writel(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_MASK); base 116 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c static void emac_reg_write_all(void __iomem *base, base 122 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c writel(itr->val, base + itr->offset); base 176 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c void __iomem *phy_regs = phy->base; base 182 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c emac_reg_write_all(phy->base, physical_coding_sublayer_programming, base 106 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c static void emac_reg_write_all(void __iomem *base, base 112 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c writel(itr->val, base + itr->offset); base 163 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c void __iomem *phy_regs = phy->base; base 169 drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c emac_reg_write_all(phy->base, physical_coding_sublayer_programming, base 97 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); base 100 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); base 108 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); base 109 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD); base 117 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c if (readl_poll_timeout_atomic(phy->base + base 127 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD); base 128 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); base 145 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c status = readl(phy->base + EMAC_SGMII_PHY_INTERRUPT_STATUS); base 185 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); base 186 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel(((val & ~PHY_RESET) | PHY_RESET), phy->base + base 190 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); base 191 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2); base 222 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); base 241 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); base 258 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); base 261 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); base 402 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c phy->base = ioremap(res->start, resource_size(res)); base 403 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c if (!phy->base) { base 439 drivers/net/ethernet/qualcomm/emac/emac-sgmii.c iounmap(phy->base); base 33 drivers/net/ethernet/qualcomm/emac/emac-sgmii.h void __iomem *base; base 111 drivers/net/ethernet/qualcomm/emac/emac.c writel(irq->mask, adpt->base + EMAC_INT_MASK); base 134 drivers/net/ethernet/qualcomm/emac/emac.c writel(0, adpt->base + EMAC_INT_MASK); base 136 drivers/net/ethernet/qualcomm/emac/emac.c isr = readl_relaxed(adpt->base + EMAC_INT_STATUS); base 168 drivers/net/ethernet/qualcomm/emac/emac.c writel(irq->mask, adpt->base + EMAC_INT_MASK); base 316 drivers/net/ethernet/qualcomm/emac/emac.c void __iomem *base = adpt->base; base 321 drivers/net/ethernet/qualcomm/emac/emac.c *stats_itr += readl_relaxed(base + addr); base 327 drivers/net/ethernet/qualcomm/emac/emac.c stats->rx_crc_align += readl_relaxed(base + EMAC_RXMAC_STATC_REG23); base 328 drivers/net/ethernet/qualcomm/emac/emac.c stats->rx_jabbers += readl_relaxed(base + EMAC_RXMAC_STATC_REG24); base 335 drivers/net/ethernet/qualcomm/emac/emac.c *stats_itr += readl_relaxed(base + addr); base 341 drivers/net/ethernet/qualcomm/emac/emac.c stats->tx_col += readl_relaxed(base + EMAC_TXMAC_STATC_REG25); base 563 drivers/net/ethernet/qualcomm/emac/emac.c adpt->base = devm_platform_ioremap_resource(pdev, 0); base 564 drivers/net/ethernet/qualcomm/emac/emac.c if (IS_ERR(adpt->base)) base 565 drivers/net/ethernet/qualcomm/emac/emac.c return PTR_ERR(adpt->base); base 572 drivers/net/ethernet/qualcomm/emac/emac.c netdev->base_addr = (unsigned long)adpt->base; base 698 drivers/net/ethernet/qualcomm/emac/emac.c reg = readl_relaxed(adpt->base + EMAC_DMA_MAS_CTRL); base 701 drivers/net/ethernet/qualcomm/emac/emac.c reg = readl_relaxed(adpt->base + EMAC_CORE_HW_VERSION); base 741 drivers/net/ethernet/qualcomm/emac/emac.c iounmap(adpt->phy.base); base 330 drivers/net/ethernet/qualcomm/emac/emac.h void __iomem *base; base 180 drivers/net/ethernet/qualcomm/qca_debug.c cmd->base.speed = SPEED_10; base 181 drivers/net/ethernet/qualcomm/qca_debug.c cmd->base.duplex = DUPLEX_HALF; base 182 drivers/net/ethernet/qualcomm/qca_debug.c cmd->base.port = PORT_OTHER; base 183 drivers/net/ethernet/qualcomm/qca_debug.c cmd->base.autoneg = AUTONEG_DISABLE; base 188 drivers/net/ethernet/rdc/r6040.c void __iomem *base; base 243 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = lp->base; base 253 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = lp->base; base 355 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = lp->base; base 375 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = lp->base; base 416 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = priv->base; base 432 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = priv->base; base 447 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = lp->base; base 585 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = priv->base; base 629 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = priv->base; base 650 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = lp->base; base 702 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = lp->base; base 732 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = lp->base; base 800 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = lp->base; base 845 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = lp->base; base 972 drivers/net/ethernet/rdc/r6040.c void __iomem *ioaddr = lp->base; base 1092 drivers/net/ethernet/rdc/r6040.c lp->base = ioaddr; base 1188 drivers/net/ethernet/rdc/r6040.c pci_iounmap(pdev, lp->base); base 1141 drivers/net/ethernet/rocker/rocker_main.c ecmd->base.phy_address = 0xff; base 1142 drivers/net/ethernet/rocker/rocker_main.c ecmd->base.port = PORT_TP; base 1143 drivers/net/ethernet/rocker/rocker_main.c ecmd->base.speed = speed; base 1144 drivers/net/ethernet/rocker/rocker_main.c ecmd->base.duplex = duplex ? DUPLEX_FULL : DUPLEX_HALF; base 1145 drivers/net/ethernet/rocker/rocker_main.c ecmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; base 1265 drivers/net/ethernet/rocker/rocker_main.c ecmd->base.speed)) base 1268 drivers/net/ethernet/rocker/rocker_main.c ecmd->base.duplex)) base 1271 drivers/net/ethernet/rocker/rocker_main.c ecmd->base.autoneg)) base 770 drivers/net/ethernet/seeq/ether3.c priv(dev)->base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); base 771 drivers/net/ethernet/seeq/ether3.c if (!priv(dev)->base) { base 776 drivers/net/ethernet/seeq/ether3.c ec->irqaddr = priv(dev)->base + data->base_offset; base 779 drivers/net/ethernet/seeq/ether3.c priv(dev)->seeq = priv(dev)->base + data->base_offset; base 154 drivers/net/ethernet/seeq/ether3.h void __iomem *base; base 147 drivers/net/ethernet/sfc/ethtool.c cmd->base.speed = link_state->speed; base 148 drivers/net/ethernet/sfc/ethtool.c cmd->base.duplex = link_state->fd ? DUPLEX_FULL : DUPLEX_HALF; base 163 drivers/net/ethernet/sfc/ethtool.c if ((cmd->base.speed == SPEED_1000) && base 164 drivers/net/ethernet/sfc/ethtool.c (cmd->base.duplex != DUPLEX_FULL)) { base 131 drivers/net/ethernet/sfc/falcon/ethtool.c cmd->base.speed = link_state->speed; base 132 drivers/net/ethernet/sfc/falcon/ethtool.c cmd->base.duplex = link_state->fd ? DUPLEX_FULL : DUPLEX_HALF; base 147 drivers/net/ethernet/sfc/falcon/ethtool.c if ((cmd->base.speed == SPEED_1000) && base 148 drivers/net/ethernet/sfc/falcon/ethtool.c (cmd->base.duplex != DUPLEX_FULL)) { base 234 drivers/net/ethernet/sfc/falcon/mdio_10g.c .base.cmd = ETHTOOL_GLINKSETTINGS base 249 drivers/net/ethernet/sfc/falcon/mdio_10g.c cmd->base.speed == prev.base.speed && base 250 drivers/net/ethernet/sfc/falcon/mdio_10g.c cmd->base.duplex == prev.base.duplex && base 251 drivers/net/ethernet/sfc/falcon/mdio_10g.c cmd->base.port == prev.base.port && base 252 drivers/net/ethernet/sfc/falcon/mdio_10g.c cmd->base.autoneg == prev.base.autoneg) base 256 drivers/net/ethernet/sfc/falcon/mdio_10g.c if (prev.base.port != PORT_TP || cmd->base.port != PORT_TP) base 260 drivers/net/ethernet/sfc/falcon/mdio_10g.c if (!cmd->base.autoneg || base 458 drivers/net/ethernet/sfc/falcon/tenxpress.c cmd->base.speed = SPEED_10000; base 465 drivers/net/ethernet/sfc/falcon/tenxpress.c if (!cmd->base.autoneg) base 597 drivers/net/ethernet/sfc/mcdi_port.c cmd->base.speed = efx->link_state.speed; base 598 drivers/net/ethernet/sfc/mcdi_port.c cmd->base.duplex = efx->link_state.fd; base 599 drivers/net/ethernet/sfc/mcdi_port.c cmd->base.port = mcdi_to_ethtool_media(phy_cfg->media); base 600 drivers/net/ethernet/sfc/mcdi_port.c cmd->base.phy_address = phy_cfg->port; base 601 drivers/net/ethernet/sfc/mcdi_port.c cmd->base.autoneg = !!(efx->link_advertising[0] & ADVERTISED_Autoneg); base 602 drivers/net/ethernet/sfc/mcdi_port.c cmd->base.mdio_support = (efx->mdio.mode_support & base 628 drivers/net/ethernet/sfc/mcdi_port.c if (cmd->base.autoneg) { base 631 drivers/net/ethernet/sfc/mcdi_port.c } else if (cmd->base.duplex) { base 632 drivers/net/ethernet/sfc/mcdi_port.c switch (cmd->base.speed) { base 644 drivers/net/ethernet/sfc/mcdi_port.c switch (cmd->base.speed) { base 659 drivers/net/ethernet/sfc/mcdi_port.c if (cmd->base.autoneg) { base 1164 drivers/net/ethernet/silan/sc92031.c cmd->base.speed = (output_status & 0x2) ? SPEED_100 : SPEED_10; base 1165 drivers/net/ethernet/silan/sc92031.c cmd->base.duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF; base 1166 drivers/net/ethernet/silan/sc92031.c cmd->base.port = PORT_MII; base 1167 drivers/net/ethernet/silan/sc92031.c cmd->base.phy_address = phy_address; base 1168 drivers/net/ethernet/silan/sc92031.c cmd->base.autoneg = (phy_ctrl & PhyCtrlAne) ? base 1185 drivers/net/ethernet/silan/sc92031.c u32 speed = cmd->base.speed; base 1195 drivers/net/ethernet/silan/sc92031.c if (!(cmd->base.duplex == DUPLEX_HALF || base 1196 drivers/net/ethernet/silan/sc92031.c cmd->base.duplex == DUPLEX_FULL)) base 1198 drivers/net/ethernet/silan/sc92031.c if (!(cmd->base.port == PORT_MII)) base 1200 drivers/net/ethernet/silan/sc92031.c if (!(cmd->base.phy_address == 0x1f)) base 1202 drivers/net/ethernet/silan/sc92031.c if (!(cmd->base.autoneg == AUTONEG_DISABLE || base 1203 drivers/net/ethernet/silan/sc92031.c cmd->base.autoneg == AUTONEG_ENABLE)) base 1206 drivers/net/ethernet/silan/sc92031.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 1236 drivers/net/ethernet/silan/sc92031.c if (cmd->base.duplex == DUPLEX_FULL) base 1458 drivers/net/ethernet/smsc/smc911x.c cmd->base.speed = SPEED_10; base 1460 drivers/net/ethernet/smsc/smc911x.c cmd->base.speed = SPEED_100; base 1462 drivers/net/ethernet/smsc/smc911x.c cmd->base.autoneg = AUTONEG_DISABLE; base 1463 drivers/net/ethernet/smsc/smc911x.c cmd->base.port = 0; base 1465 drivers/net/ethernet/smsc/smc911x.c cmd->base.duplex = base 1490 drivers/net/ethernet/smsc/smc911x.c if (cmd->base.autoneg != AUTONEG_DISABLE || base 1491 drivers/net/ethernet/smsc/smc911x.c cmd->base.speed != SPEED_10 || base 1492 drivers/net/ethernet/smsc/smc911x.c (cmd->base.duplex != DUPLEX_HALF && base 1493 drivers/net/ethernet/smsc/smc911x.c cmd->base.duplex != DUPLEX_FULL) || base 1494 drivers/net/ethernet/smsc/smc911x.c (cmd->base.port != PORT_TP && base 1495 drivers/net/ethernet/smsc/smc911x.c cmd->base.port != PORT_AUI)) base 1498 drivers/net/ethernet/smsc/smc911x.c lp->ctl_rfduplx = cmd->base.duplex == DUPLEX_FULL; base 2092 drivers/net/ethernet/smsc/smc911x.c lp->base = addr; base 2134 drivers/net/ethernet/smsc/smc911x.c iounmap(lp->base); base 101 drivers/net/ethernet/smsc/smc911x.h void __iomem *base; base 114 drivers/net/ethernet/smsc/smc911x.h void __iomem *ioaddr = lp->base + reg; base 128 drivers/net/ethernet/smsc/smc911x.h void __iomem *ioaddr = lp->base + reg; base 147 drivers/net/ethernet/smsc/smc911x.h void __iomem *ioaddr = lp->base + reg; base 165 drivers/net/ethernet/smsc/smc911x.h void __iomem *ioaddr = lp->base + reg; base 181 drivers/net/ethernet/smsc/smc911x.h #define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16)) base 184 drivers/net/ethernet/smsc/smc911x.h writew(v & 0xFFFF, (lp)->base + (r)); \ base 185 drivers/net/ethernet/smsc/smc911x.h writew(v >> 16, (lp)->base + (r) + 2); \ base 187 drivers/net/ethernet/smsc/smc911x.h #define SMC_insl(lp, r, p, l) ioread16_rep((short*)((lp)->base + (r)), p, l*2) base 188 drivers/net/ethernet/smsc/smc911x.h #define SMC_outsl(lp, r, p, l) iowrite16_rep((short*)((lp)->base + (r)), p, l*2) base 191 drivers/net/ethernet/smsc/smc911x.h #define SMC_inl(lp, r) readl((lp)->base + (r)) base 192 drivers/net/ethernet/smsc/smc911x.h #define SMC_outl(v, lp, r) writel(v, (lp)->base + (r)) base 193 drivers/net/ethernet/smsc/smc911x.h #define SMC_insl(lp, r, p, l) ioread32_rep((int*)((lp)->base + (r)), p, l) base 194 drivers/net/ethernet/smsc/smc911x.h #define SMC_outsl(lp, r, p, l) iowrite32_rep((int*)((lp)->base + (r)), p, l) base 106 drivers/net/ethernet/smsc/smc91c92_cs.c void __iomem *base; base 385 drivers/net/ethernet/smsc/smc91c92_cs.c readb(smc->base+MEGAHERTZ_ISR); base 387 drivers/net/ethernet/smsc/smc91c92_cs.c readb(smc->base+MEGAHERTZ_ISR); base 393 drivers/net/ethernet/smsc/smc91c92_cs.c tmp = readb(smc->base + link->config_base + CISREG_COR); base 395 drivers/net/ethernet/smsc/smc91c92_cs.c writeb(tmp, smc->base + link->config_base + CISREG_COR); base 445 drivers/net/ethernet/smsc/smc91c92_cs.c smc->base = ioremap(link->resource[2]->start, base 524 drivers/net/ethernet/smsc/smc91c92_cs.c writeb(iouart & 0xff, smc->base + MOT_UART + CISREG_IOBASE_0); base 525 drivers/net/ethernet/smsc/smc91c92_cs.c writeb((iouart >> 8) & 0xff, smc->base + MOT_UART + CISREG_IOBASE_1); base 526 drivers/net/ethernet/smsc/smc91c92_cs.c writeb(MOT_NORMAL, smc->base + MOT_UART + CISREG_COR); base 529 drivers/net/ethernet/smsc/smc91c92_cs.c writeb(ioaddr & 0xff, smc->base + MOT_LAN + CISREG_IOBASE_0); base 530 drivers/net/ethernet/smsc/smc91c92_cs.c writeb((ioaddr >> 8) & 0xff, smc->base + MOT_LAN + CISREG_IOBASE_1); base 531 drivers/net/ethernet/smsc/smc91c92_cs.c writeb(MOT_NORMAL, smc->base + MOT_LAN + CISREG_COR); base 959 drivers/net/ethernet/smsc/smc91c92_cs.c iounmap(smc->base); base 1443 drivers/net/ethernet/smsc/smc91c92_cs.c cor = readb(smc->base + MOT_UART + CISREG_COR); base 1444 drivers/net/ethernet/smsc/smc91c92_cs.c writeb(cor & ~COR_IREQ_ENA, smc->base + MOT_UART + CISREG_COR); base 1445 drivers/net/ethernet/smsc/smc91c92_cs.c writeb(cor, smc->base + MOT_UART + CISREG_COR); base 1446 drivers/net/ethernet/smsc/smc91c92_cs.c cor = readb(smc->base + MOT_LAN + CISREG_COR); base 1447 drivers/net/ethernet/smsc/smc91c92_cs.c writeb(cor & ~COR_IREQ_ENA, smc->base + MOT_LAN + CISREG_COR); base 1448 drivers/net/ethernet/smsc/smc91c92_cs.c writeb(cor, smc->base + MOT_LAN + CISREG_COR); base 1451 drivers/net/ethernet/smsc/smc91c92_cs.c if ((smc->base != NULL) && /* Megahertz MFC's */ base 1456 drivers/net/ethernet/smsc/smc91c92_cs.c tmp = readb(smc->base+MEGAHERTZ_ISR); base 1457 drivers/net/ethernet/smsc/smc91c92_cs.c tmp = readb(smc->base+MEGAHERTZ_ISR); base 1460 drivers/net/ethernet/smsc/smc91c92_cs.c writeb(tmp, smc->base + MEGAHERTZ_ISR); base 1461 drivers/net/ethernet/smsc/smc91c92_cs.c writeb(tmp, smc->base + MEGAHERTZ_ISR); base 1858 drivers/net/ethernet/smsc/smc91c92_cs.c ecmd->base.port = (tmp & CFG_AUI_SELECT) ? PORT_AUI : PORT_TP; base 1859 drivers/net/ethernet/smsc/smc91c92_cs.c ecmd->base.speed = SPEED_10; base 1860 drivers/net/ethernet/smsc/smc91c92_cs.c ecmd->base.phy_address = ioaddr + MGMT; base 1864 drivers/net/ethernet/smsc/smc91c92_cs.c ecmd->base.duplex = (tmp & TCR_FDUPLX) ? DUPLEX_FULL : DUPLEX_HALF; base 1876 drivers/net/ethernet/smsc/smc91c92_cs.c if (ecmd->base.speed != SPEED_10) base 1878 drivers/net/ethernet/smsc/smc91c92_cs.c if (ecmd->base.duplex != DUPLEX_HALF && base 1879 drivers/net/ethernet/smsc/smc91c92_cs.c ecmd->base.duplex != DUPLEX_FULL) base 1881 drivers/net/ethernet/smsc/smc91c92_cs.c if (ecmd->base.port != PORT_TP && ecmd->base.port != PORT_AUI) base 1884 drivers/net/ethernet/smsc/smc91c92_cs.c if (ecmd->base.port == PORT_AUI) base 1891 drivers/net/ethernet/smsc/smc91c92_cs.c if (ecmd->base.duplex == DUPLEX_FULL) base 241 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 335 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 369 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 401 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 542 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 632 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 705 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 763 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 785 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 810 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 841 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 903 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 1006 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 1035 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 1160 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 1184 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 1204 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 1327 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 1369 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 1541 drivers/net/ethernet/smsc/smc91x.c cmd->base.speed = SPEED_10; base 1543 drivers/net/ethernet/smsc/smc91x.c cmd->base.speed = SPEED_100; base 1545 drivers/net/ethernet/smsc/smc91x.c cmd->base.autoneg = AUTONEG_DISABLE; base 1546 drivers/net/ethernet/smsc/smc91x.c cmd->base.port = 0; base 1547 drivers/net/ethernet/smsc/smc91x.c cmd->base.duplex = lp->tcr_cur_mode & TCR_SWFDUP ? base 1569 drivers/net/ethernet/smsc/smc91x.c if (cmd->base.autoneg != AUTONEG_DISABLE || base 1570 drivers/net/ethernet/smsc/smc91x.c cmd->base.speed != SPEED_10 || base 1571 drivers/net/ethernet/smsc/smc91x.c (cmd->base.duplex != DUPLEX_HALF && base 1572 drivers/net/ethernet/smsc/smc91x.c cmd->base.duplex != DUPLEX_FULL) || base 1573 drivers/net/ethernet/smsc/smc91x.c (cmd->base.port != PORT_TP && cmd->base.port != PORT_AUI)) base 1577 drivers/net/ethernet/smsc/smc91x.c lp->ctl_rfduplx = cmd->base.duplex == DUPLEX_FULL; base 1627 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 1655 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 1775 drivers/net/ethernet/smsc/smc91x.c void __iomem *ioaddr = lp->base; base 1919 drivers/net/ethernet/smsc/smc91x.c lp->base = ioaddr; base 2022 drivers/net/ethernet/smsc/smc91x.c lp->base, dev->irq); base 2420 drivers/net/ethernet/smsc/smc91x.c iounmap(lp->base); base 270 drivers/net/ethernet/smsc/smc91x.h void __iomem *base; base 1330 drivers/net/ethernet/socionext/netsec.c u64 base = (u64)addr_h << 32 | addr_l; base 1334 drivers/net/ethernet/socionext/netsec.c ucode = ioremap(base, size * sizeof(u32)); base 250 drivers/net/ethernet/socionext/sni_ave.c void __iomem *base; base 305 drivers/net/ethernet/socionext/sni_ave.c return readl(priv->base + addr); base 323 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + addr); base 350 drivers/net/ethernet/socionext/sni_ave.c ret = readl(priv->base + AVE_GIMR); base 351 drivers/net/ethernet/socionext/sni_ave.c writel(0, priv->base + AVE_GIMR); base 360 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_GIMR); base 367 drivers/net/ethernet/socionext/sni_ave.c writel(readl(priv->base + AVE_GIMR) | bitflag, priv->base + AVE_GIMR); base 368 drivers/net/ethernet/socionext/sni_ave.c writel(bitflag, priv->base + AVE_GISR); base 378 drivers/net/ethernet/socionext/sni_ave.c mac_addr[2] << 16 | mac_addr[3] << 24, priv->base + reg1); base 379 drivers/net/ethernet/socionext/sni_ave.c writel(mac_addr[4] | mac_addr[5] << 8, priv->base + reg2); base 387 drivers/net/ethernet/socionext/sni_ave.c vr = readl(priv->base + AVE_VR); base 501 drivers/net/ethernet/socionext/sni_ave.c writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); base 504 drivers/net/ethernet/socionext/sni_ave.c mdioctl = readl(priv->base + AVE_MDIOCTR); base 506 drivers/net/ethernet/socionext/sni_ave.c priv->base + AVE_MDIOCTR); base 508 drivers/net/ethernet/socionext/sni_ave.c ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, base 516 drivers/net/ethernet/socionext/sni_ave.c return readl(priv->base + AVE_MDIORDR) & GENMASK(15, 0); base 530 drivers/net/ethernet/socionext/sni_ave.c writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR); base 533 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_MDIOWDR); base 536 drivers/net/ethernet/socionext/sni_ave.c mdioctl = readl(priv->base + AVE_MDIOCTR); base 538 drivers/net/ethernet/socionext/sni_ave.c priv->base + AVE_MDIOCTR); base 540 drivers/net/ethernet/socionext/sni_ave.c ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr, base 639 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_DESCC_TD | AVE_DESCC_RD0, priv->base + AVE_DESCC); base 643 drivers/net/ethernet/socionext/sni_ave.c writel(0, priv->base + AVE_DESCC); base 644 drivers/net/ethernet/socionext/sni_ave.c if (readl_poll_timeout(priv->base + AVE_DESCC, val, !val, base 652 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_DESCC); base 655 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_DESCC); base 656 drivers/net/ethernet/socionext/sni_ave.c if (readl_poll_timeout(priv->base + AVE_DESCC, val, base 665 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_DESCC); base 668 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_DESCC); base 863 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_CFGR); base 866 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_RSTCTRL); base 868 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_RSTCTRL); base 871 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->base + AVE_GRR); base 875 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_GRR_GRST, priv->base + AVE_GRR); base 879 drivers/net/ethernet/socionext/sni_ave.c writel(0, priv->base + AVE_GRR); base 883 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_RSTCTRL); base 885 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_RSTCTRL); base 896 drivers/net/ethernet/socionext/sni_ave.c rxcr_org = readl(priv->base + AVE_RXCR); base 897 drivers/net/ethernet/socionext/sni_ave.c writel(rxcr_org & (~AVE_RXCR_RXEN), priv->base + AVE_RXCR); base 906 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_GRR_RXFFR, priv->base + AVE_GRR); base 910 drivers/net/ethernet/socionext/sni_ave.c writel(0, priv->base + AVE_GRR); base 914 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_GI_RXOVF, priv->base + AVE_GISR); base 920 drivers/net/ethernet/socionext/sni_ave.c writel(rxcr_org, priv->base + AVE_RXCR); base 932 drivers/net/ethernet/socionext/sni_ave.c gisr_val = readl(priv->base + AVE_GISR); base 936 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_GI_PHY, priv->base + AVE_GISR); base 940 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_GI_RXERR, priv->base + AVE_GISR); base 958 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_GI_RXDROP, priv->base + AVE_GISR); base 989 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_PFEN); base 990 drivers/net/ethernet/socionext/sni_ave.c writel(val | BIT(entry), priv->base + AVE_PFEN); base 1003 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_PFEN); base 1004 drivers/net/ethernet/socionext/sni_ave.c writel(val & ~BIT(entry), priv->base + AVE_PFEN); base 1029 drivers/net/ethernet/socionext/sni_ave.c priv->base + AVE_PFMBYTE(entry)); base 1030 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); base 1033 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); base 1036 drivers/net/ethernet/socionext/sni_ave.c writel(0, priv->base + AVE_PFSEL(entry)); base 1055 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_PFMBYTE_MASK0, priv->base + AVE_PFMBYTE(entry)); base 1056 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4); base 1059 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry)); base 1062 drivers/net/ethernet/socionext/sni_ave.c writel(rxring, priv->base + AVE_PFSEL(entry)); base 1096 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_TXCR); base 1104 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_TXCR); base 1108 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_LINKSEL); base 1113 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_LINKSEL); base 1117 drivers/net/ethernet/socionext/sni_ave.c rxcr = readl(priv->base + AVE_RXCR); base 1118 drivers/net/ethernet/socionext/sni_ave.c txcr = readl(priv->base + AVE_TXCR); base 1147 drivers/net/ethernet/socionext/sni_ave.c writel(rxcr & ~AVE_RXCR_RXEN, priv->base + AVE_RXCR); base 1149 drivers/net/ethernet/socionext/sni_ave.c writel(txcr, priv->base + AVE_TXCR); base 1150 drivers/net/ethernet/socionext/sni_ave.c writel(rxcr, priv->base + AVE_RXCR); base 1299 drivers/net/ethernet/socionext/sni_ave.c priv->base + AVE_TXDC); base 1310 drivers/net/ethernet/socionext/sni_ave.c priv->base + AVE_RXDC0); base 1321 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_RXCR); base 1325 drivers/net/ethernet/socionext/sni_ave.c writel(AVE_TXCR_FLOCTR, priv->base + AVE_TXCR); base 1328 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_IIRQC) & AVE_IIRQC_BSCK; base 1330 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_IIRQC); base 1472 drivers/net/ethernet/socionext/sni_ave.c val = readl(priv->base + AVE_RXCR); base 1477 drivers/net/ethernet/socionext/sni_ave.c writel(val, priv->base + AVE_RXCR); base 1563 drivers/net/ethernet/socionext/sni_ave.c void __iomem *base; base 1584 drivers/net/ethernet/socionext/sni_ave.c base = devm_platform_ioremap_resource(pdev, 0); base 1585 drivers/net/ethernet/socionext/sni_ave.c if (IS_ERR(base)) base 1586 drivers/net/ethernet/socionext/sni_ave.c return PTR_ERR(base); base 1615 drivers/net/ethernet/socionext/sni_ave.c priv->base = base; base 1715 drivers/net/ethernet/socionext/sni_ave.c ave_id = readl(priv->base + AVE_IDR); base 66 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c static int tse_pcs_reset(void __iomem *base, struct tse_pcs *pcs) base 71 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(base + TSE_PCS_CONTROL_REG); base 73 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(val, base + TSE_PCS_CONTROL_REG); base 76 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c val = readw(base + TSE_PCS_CONTROL_REG); base 91 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs) base 95 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(TSE_PCS_IF_USE_SGMII, base + TSE_PCS_IF_MODE_REG); base 97 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(TSE_PCS_CTRL_AUTONEG_SGMII, base + TSE_PCS_CONTROL_REG); base 99 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(TSE_PCS_SGMII_LINK_TIMER_0, base + TSE_PCS_LINK_TIMER_0_REG); base 100 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c writew(TSE_PCS_SGMII_LINK_TIMER_1, base + TSE_PCS_LINK_TIMER_1_REG); base 102 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c ret = tse_pcs_reset(base, pcs); base 21 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.h int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs); base 285 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c cmd->base.speed = SPEED_UNKNOWN; base 286 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c cmd->base.duplex = DUPLEX_UNKNOWN; base 289 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c cmd->base.duplex = priv->xstats.pcs_duplex; base 291 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c cmd->base.speed = priv->xstats.pcs_speed; base 316 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c cmd->base.autoneg = ADVERTISED_Autoneg; base 344 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c cmd->base.port = PORT_OTHER; base 370 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c if (cmd->base.autoneg != AUTONEG_ENABLE) base 696 drivers/net/ethernet/sun/cassini.c if (ep->base.autoneg == AUTONEG_ENABLE) { base 699 drivers/net/ethernet/sun/cassini.c u32 speed = ep->base.speed; base 705 drivers/net/ethernet/sun/cassini.c if (ep->base.duplex == DUPLEX_FULL) base 3180 drivers/net/ethernet/sun/cassini.c void __iomem *base, *kstart; base 3202 drivers/net/ethernet/sun/cassini.c base = NULL; base 3209 drivers/net/ethernet/sun/cassini.c base = p + (readb(p + i + 8) | base 3215 drivers/net/ethernet/sun/cassini.c if (!base || (readb(base) != 0x82)) base 3218 drivers/net/ethernet/sun/cassini.c i = (readb(base + 1) | (readb(base + 2) << 8)) + 3; base 3220 drivers/net/ethernet/sun/cassini.c if (readb(base + i) != 0x90) /* no vpd found */ base 3224 drivers/net/ethernet/sun/cassini.c len = readb(base + i + 1) | (readb(base + i + 2) << 8); base 3227 drivers/net/ethernet/sun/cassini.c kstart = base + i + 3; base 4542 drivers/net/ethernet/sun/cassini.c cmd->base.port = PORT_MII; base 4543 drivers/net/ethernet/sun/cassini.c cmd->base.phy_address = cp->phy_addr; base 4566 drivers/net/ethernet/sun/cassini.c cmd->base.port = PORT_FIBRE; base 4567 drivers/net/ethernet/sun/cassini.c cmd->base.phy_address = 0; base 4582 drivers/net/ethernet/sun/cassini.c cmd->base.autoneg = AUTONEG_ENABLE; base 4583 drivers/net/ethernet/sun/cassini.c cmd->base.speed = ((speed == 10) ? base 4587 drivers/net/ethernet/sun/cassini.c cmd->base.duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF; base 4589 drivers/net/ethernet/sun/cassini.c cmd->base.autoneg = AUTONEG_DISABLE; base 4590 drivers/net/ethernet/sun/cassini.c cmd->base.speed = ((bmcr & CAS_BMCR_SPEED1000) ? base 4594 drivers/net/ethernet/sun/cassini.c cmd->base.duplex = (bmcr & BMCR_FULLDPLX) ? base 4609 drivers/net/ethernet/sun/cassini.c cmd->base.speed = 0; base 4610 drivers/net/ethernet/sun/cassini.c cmd->base.duplex = 0xff; base 4612 drivers/net/ethernet/sun/cassini.c cmd->base.speed = SPEED_10; base 4614 drivers/net/ethernet/sun/cassini.c cmd->base.speed = SPEED_100; base 4616 drivers/net/ethernet/sun/cassini.c cmd->base.speed = SPEED_1000; base 4618 drivers/net/ethernet/sun/cassini.c cmd->base.duplex = (cp->link_cntl & BMCR_FULLDPLX) ? base 4636 drivers/net/ethernet/sun/cassini.c u32 speed = cmd->base.speed; base 4639 drivers/net/ethernet/sun/cassini.c if (cmd->base.autoneg != AUTONEG_ENABLE && base 4640 drivers/net/ethernet/sun/cassini.c cmd->base.autoneg != AUTONEG_DISABLE) base 4643 drivers/net/ethernet/sun/cassini.c if (cmd->base.autoneg == AUTONEG_DISABLE && base 4647 drivers/net/ethernet/sun/cassini.c (cmd->base.duplex != DUPLEX_HALF && base 4648 drivers/net/ethernet/sun/cassini.c cmd->base.duplex != DUPLEX_FULL))) base 3086 drivers/net/ethernet/sun/niu.c u64 mask, u64 base, int enable) base 3093 drivers/net/ethernet/sun/niu.c (base & ~(u64)0x1f) != 0) base 3101 drivers/net/ethernet/sun/niu.c val |= (base << FLW_PRT_SEL_BASE_SHIFT); base 3298 drivers/net/ethernet/sun/niu.c static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base) base 3300 drivers/net/ethernet/sun/niu.c unsigned int h = niu_hash_rxaddr(rp, base); base 3302 drivers/net/ethernet/sun/niu.c page->index = base; base 3522 drivers/net/ethernet/sun/niu.c u64 base = page->index; base 3524 drivers/net/ethernet/sun/niu.c np->ops->unmap_page(np->device, base, PAGE_SIZE, base 6447 drivers/net/ethernet/sun/niu.c u64 base = page->index; base 6448 drivers/net/ethernet/sun/niu.c base = base >> RBR_DESCR_ADDR_SHIFT; base 6449 drivers/net/ethernet/sun/niu.c rp->rbr[k++] = cpu_to_le32(base); base 6803 drivers/net/ethernet/sun/niu.c cmd->base.phy_address = np->phy_addr; base 6808 drivers/net/ethernet/sun/niu.c cmd->base.autoneg = lp->active_autoneg; base 6809 drivers/net/ethernet/sun/niu.c cmd->base.speed = lp->active_speed; base 6810 drivers/net/ethernet/sun/niu.c cmd->base.duplex = lp->active_duplex; base 6811 drivers/net/ethernet/sun/niu.c cmd->base.port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP; base 6824 drivers/net/ethernet/sun/niu.c lp->speed = cmd->base.speed; base 6825 drivers/net/ethernet/sun/niu.c lp->duplex = cmd->base.duplex; base 6826 drivers/net/ethernet/sun/niu.c lp->autoneg = cmd->base.autoneg; base 1290 drivers/net/ethernet/sun/sungem.c if (ep->base.autoneg == AUTONEG_ENABLE) { base 1295 drivers/net/ethernet/sun/sungem.c speed = ep->base.speed; base 1296 drivers/net/ethernet/sun/sungem.c duplex = ep->base.duplex; base 2542 drivers/net/ethernet/sun/sungem.c cmd->base.port = PORT_MII; base 2543 drivers/net/ethernet/sun/sungem.c cmd->base.phy_address = 0; /* XXX fixed PHYAD */ base 2546 drivers/net/ethernet/sun/sungem.c cmd->base.autoneg = gp->want_autoneg; base 2547 drivers/net/ethernet/sun/sungem.c cmd->base.speed = gp->phy_mii.speed; base 2548 drivers/net/ethernet/sun/sungem.c cmd->base.duplex = gp->phy_mii.duplex; base 2563 drivers/net/ethernet/sun/sungem.c cmd->base.speed = 0; base 2564 drivers/net/ethernet/sun/sungem.c cmd->base.duplex = 0; base 2565 drivers/net/ethernet/sun/sungem.c cmd->base.port = 0; base 2566 drivers/net/ethernet/sun/sungem.c cmd->base.phy_address = 0; base 2567 drivers/net/ethernet/sun/sungem.c cmd->base.autoneg = 0; base 2571 drivers/net/ethernet/sun/sungem.c cmd->base.port = PORT_FIBRE; base 2578 drivers/net/ethernet/sun/sungem.c cmd->base.speed = SPEED_1000; base 2579 drivers/net/ethernet/sun/sungem.c cmd->base.duplex = DUPLEX_FULL; base 2580 drivers/net/ethernet/sun/sungem.c cmd->base.autoneg = 1; base 2596 drivers/net/ethernet/sun/sungem.c u32 speed = cmd->base.speed; base 2603 drivers/net/ethernet/sun/sungem.c if (cmd->base.autoneg != AUTONEG_ENABLE && base 2604 drivers/net/ethernet/sun/sungem.c cmd->base.autoneg != AUTONEG_DISABLE) base 2607 drivers/net/ethernet/sun/sungem.c if (cmd->base.autoneg == AUTONEG_ENABLE && base 2611 drivers/net/ethernet/sun/sungem.c if (cmd->base.autoneg == AUTONEG_DISABLE && base 2615 drivers/net/ethernet/sun/sungem.c (cmd->base.duplex != DUPLEX_HALF && base 2616 drivers/net/ethernet/sun/sungem.c cmd->base.duplex != DUPLEX_FULL))) base 1314 drivers/net/ethernet/sun/sunhme.c if (!ep || ep->base.autoneg == AUTONEG_ENABLE) { base 1389 drivers/net/ethernet/sun/sunhme.c if (!ep || ep->base.autoneg == AUTONEG_ENABLE) { base 1392 drivers/net/ethernet/sun/sunhme.c if (ep->base.speed == SPEED_100) base 1396 drivers/net/ethernet/sun/sunhme.c if (ep->base.duplex == DUPLEX_FULL) base 2450 drivers/net/ethernet/sun/sunhme.c cmd->base.port = PORT_TP; /* XXX no MII support */ base 2451 drivers/net/ethernet/sun/sunhme.c cmd->base.phy_address = 0; /* XXX fixed PHYAD */ base 2460 drivers/net/ethernet/sun/sunhme.c cmd->base.autoneg = AUTONEG_ENABLE; base 2464 drivers/net/ethernet/sun/sunhme.c cmd->base.duplex = base 2468 drivers/net/ethernet/sun/sunhme.c cmd->base.duplex = base 2472 drivers/net/ethernet/sun/sunhme.c cmd->base.autoneg = AUTONEG_DISABLE; base 2474 drivers/net/ethernet/sun/sunhme.c cmd->base.duplex = base 2478 drivers/net/ethernet/sun/sunhme.c cmd->base.speed = speed; base 2491 drivers/net/ethernet/sun/sunhme.c if (cmd->base.autoneg != AUTONEG_ENABLE && base 2492 drivers/net/ethernet/sun/sunhme.c cmd->base.autoneg != AUTONEG_DISABLE) base 2494 drivers/net/ethernet/sun/sunhme.c if (cmd->base.autoneg == AUTONEG_DISABLE && base 2495 drivers/net/ethernet/sun/sunhme.c ((cmd->base.speed != SPEED_100 && base 2496 drivers/net/ethernet/sun/sunhme.c cmd->base.speed != SPEED_10) || base 2497 drivers/net/ethernet/sun/sunhme.c (cmd->base.duplex != DUPLEX_HALF && base 2498 drivers/net/ethernet/sun/sunhme.c cmd->base.duplex != DUPLEX_FULL))) base 1695 drivers/net/ethernet/sun/sunvnet_common.c if (!dr->base) base 1714 drivers/net/ethernet/sun/sunvnet_common.c ldc_free_exp_dring(port->vio.lp, dr->base, base 1717 drivers/net/ethernet/sun/sunvnet_common.c dr->base = NULL; base 1761 drivers/net/ethernet/sun/sunvnet_common.c dr->base = dring; base 2139 drivers/net/ethernet/tehuti/tehuti.c ecmd->base.speed = SPEED_10000; base 2140 drivers/net/ethernet/tehuti/tehuti.c ecmd->base.duplex = DUPLEX_FULL; base 2141 drivers/net/ethernet/tehuti/tehuti.c ecmd->base.port = PORT_FIBRE; base 2142 drivers/net/ethernet/tehuti/tehuti.c ecmd->base.autoneg = AUTONEG_DISABLE; base 143 drivers/net/ethernet/ti/cpmac.c #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg))) base 144 drivers/net/ethernet/ti/cpmac.c #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \ base 1819 drivers/net/ethernet/ti/netcp_ethss.c void __iomem *base = gbe_dev->hw_stats_regs[stats_mod]; base 1825 drivers/net/ethernet/ti/netcp_ethss.c p_stats_entry = base + gbe_dev->et_stats[i].offset; base 1835 drivers/net/ethernet/ti/netcp_ethss.c void __iomem *base = NULL; base 1842 drivers/net/ethernet/ti/netcp_ethss.c base = gbe_dev->hw_stats_regs[gbe_dev->et_stats[et_stats_entry].type]; base 1843 drivers/net/ethernet/ti/netcp_ethss.c p_stats_entry = base + gbe_dev->et_stats[et_stats_entry].offset; base 1951 drivers/net/ethernet/ti/netcp_ethss.c cmd->base.port = gbe_intf->slave->phy_port_t; base 1962 drivers/net/ethernet/ti/netcp_ethss.c u8 port = cmd->base.port; base 31 drivers/net/ethernet/ti/netcp_sgmii.c static void sgmii_write_reg(void __iomem *base, int reg, u32 val) base 33 drivers/net/ethernet/ti/netcp_sgmii.c writel(val, base + reg); base 36 drivers/net/ethernet/ti/netcp_sgmii.c static u32 sgmii_read_reg(void __iomem *base, int reg) base 38 drivers/net/ethernet/ti/netcp_sgmii.c return readl(base + reg); base 41 drivers/net/ethernet/ti/netcp_sgmii.c static void sgmii_write_reg_bit(void __iomem *base, int reg, u32 val) base 43 drivers/net/ethernet/ti/netcp_sgmii.c writel((readl(base + reg) | val), base + reg); base 1205 drivers/net/ethernet/toshiba/ps3_gelic_net.c cmd->base.duplex = DUPLEX_FULL; base 1207 drivers/net/ethernet/toshiba/ps3_gelic_net.c cmd->base.duplex = DUPLEX_HALF; base 1211 drivers/net/ethernet/toshiba/ps3_gelic_net.c cmd->base.speed = SPEED_10; base 1214 drivers/net/ethernet/toshiba/ps3_gelic_net.c cmd->base.speed = SPEED_100; base 1217 drivers/net/ethernet/toshiba/ps3_gelic_net.c cmd->base.speed = SPEED_1000; base 1221 drivers/net/ethernet/toshiba/ps3_gelic_net.c cmd->base.speed = SPEED_10; base 1231 drivers/net/ethernet/toshiba/ps3_gelic_net.c cmd->base.autoneg = AUTONEG_ENABLE; base 1233 drivers/net/ethernet/toshiba/ps3_gelic_net.c cmd->base.autoneg = AUTONEG_DISABLE; base 1236 drivers/net/ethernet/toshiba/ps3_gelic_net.c cmd->base.port = PORT_TP; base 1254 drivers/net/ethernet/toshiba/ps3_gelic_net.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 1257 drivers/net/ethernet/toshiba/ps3_gelic_net.c switch (cmd->base.speed) { base 1270 drivers/net/ethernet/toshiba/ps3_gelic_net.c if (cmd->base.duplex == DUPLEX_FULL) { base 1272 drivers/net/ethernet/toshiba/ps3_gelic_net.c } else if (cmd->base.speed == SPEED_1000) { base 51 drivers/net/ethernet/toshiba/spider_net_ethtool.c cmd->base.port = PORT_FIBRE; base 52 drivers/net/ethernet/toshiba/spider_net_ethtool.c cmd->base.speed = card->phy.speed; base 53 drivers/net/ethernet/toshiba/spider_net_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 484 drivers/net/ethernet/via/via-rhine.c void __iomem *base; base 529 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 557 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 569 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 583 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 639 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 709 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 748 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 785 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 826 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 928 drivers/net/ethernet/via/via-rhine.c rp->base = ioaddr; base 1364 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 1505 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 1525 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 1564 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 1597 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 1611 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 1638 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 1657 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 1691 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 1767 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 1786 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 1891 drivers/net/ethernet/via/via-rhine.c iowrite16(0x0000, rp->base + IntrEnable); base 2157 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 2213 drivers/net/ethernet/via/via-rhine.c iowrite16(RHINE_EVENT & 0xffff, rp->base + IntrEnable); base 2247 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 2419 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 2452 drivers/net/ethernet/via/via-rhine.c pci_iounmap(pdev, rp->base); base 2466 drivers/net/ethernet/via/via-rhine.c iounmap(rp->base); base 2477 drivers/net/ethernet/via/via-rhine.c void __iomem *ioaddr = rp->base; base 3335 drivers/net/ethernet/via/via-velocity.c cmd->base.speed = SPEED_1000; base 3337 drivers/net/ethernet/via/via-velocity.c cmd->base.speed = SPEED_100; base 3339 drivers/net/ethernet/via/via-velocity.c cmd->base.speed = SPEED_10; base 3341 drivers/net/ethernet/via/via-velocity.c cmd->base.autoneg = (status & VELOCITY_AUTONEG_ENABLE) ? base 3343 drivers/net/ethernet/via/via-velocity.c cmd->base.port = PORT_TP; base 3344 drivers/net/ethernet/via/via-velocity.c cmd->base.phy_address = readb(®s->MIIADR) & 0x1F; base 3347 drivers/net/ethernet/via/via-velocity.c cmd->base.duplex = DUPLEX_FULL; base 3349 drivers/net/ethernet/via/via-velocity.c cmd->base.duplex = DUPLEX_HALF; base 3363 drivers/net/ethernet/via/via-velocity.c u32 speed = cmd->base.speed; base 3371 drivers/net/ethernet/via/via-velocity.c new_status |= ((cmd->base.autoneg) ? VELOCITY_AUTONEG_ENABLE : 0); base 3375 drivers/net/ethernet/via/via-velocity.c new_status |= ((cmd->base.duplex == DUPLEX_FULL) ? base 182 drivers/net/ethernet/wiznet/w5100.c void __iomem *base; base 196 drivers/net/ethernet/wiznet/w5100.c return mmio_priv->base; base 273 drivers/net/ethernet/wiznet/w5100.c mmio_priv->base = devm_ioremap_resource(&pdev->dev, mem); base 274 drivers/net/ethernet/wiznet/w5100.c if (IS_ERR(mmio_priv->base)) base 275 drivers/net/ethernet/wiznet/w5100.c return PTR_ERR(mmio_priv->base); base 87 drivers/net/ethernet/wiznet/w5300.c void __iomem *base; base 116 drivers/net/ethernet/wiznet/w5300.c return ioread16(priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT)); base 122 drivers/net/ethernet/wiznet/w5300.c iowrite16(data, priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT)); base 543 drivers/net/ethernet/wiznet/w5300.c priv->base = devm_ioremap_resource(&pdev->dev, mem); base 544 drivers/net/ethernet/wiznet/w5300.c if (IS_ERR(priv->base)) base 545 drivers/net/ethernet/wiznet/w5300.c return PTR_ERR(priv->base); base 365 drivers/net/fddi/defxx.c writel(data, bp->base.mem + offset); base 371 drivers/net/fddi/defxx.c outl(data, bp->base.port + offset); base 390 drivers/net/fddi/defxx.c *data = readl(bp->base.mem + offset); base 395 drivers/net/fddi/defxx.c *data = inl(bp->base.port + offset); base 617 drivers/net/fddi/defxx.c bp->base.mem = ioremap_nocache(bar_start[0], bar_len[0]); base 618 drivers/net/fddi/defxx.c if (!bp->base.mem) { base 624 drivers/net/fddi/defxx.c bp->base.port = bar_start[0]; base 660 drivers/net/fddi/defxx.c iounmap(bp->base.mem); base 3725 drivers/net/fddi/defxx.c iounmap(bp->base.mem); base 1777 drivers/net/fddi/defxx.h } base; /* base address */ base 168 drivers/net/fjes/fjes_ethtool.c ecmd->base.duplex = DUPLEX_FULL; base 169 drivers/net/fjes/fjes_ethtool.c ecmd->base.autoneg = AUTONEG_DISABLE; base 170 drivers/net/fjes/fjes_ethtool.c ecmd->base.port = PORT_NONE; base 171 drivers/net/fjes/fjes_ethtool.c ecmd->base.speed = 20000; /* 20Gb/s */ base 25 drivers/net/fjes/fjes_hw.c u8 *base = hw->base; base 28 drivers/net/fjes/fjes_hw.c value = readl(&base[reg]); base 35 drivers/net/fjes/fjes_hw.c u8 *base; base 43 drivers/net/fjes/fjes_hw.c base = (u8 *)ioremap_nocache(hw->hw_res.start, hw->hw_res.size); base 45 drivers/net/fjes/fjes_hw.c return base; base 50 drivers/net/fjes/fjes_hw.c iounmap(hw->base); base 307 drivers/net/fjes/fjes_hw.c hw->base = fjes_hw_iomap(hw); base 308 drivers/net/fjes/fjes_hw.c if (!hw->base) base 341 drivers/net/fjes/fjes_hw.c if (hw->base) { base 359 drivers/net/fjes/fjes_hw.c hw->base = NULL; base 592 drivers/net/fjes/fjes_hw.c if (!hw->base) base 315 drivers/net/fjes/fjes_hw.h u8 *base; base 121 drivers/net/fjes/fjes_regs.h u8 *base = hw->base; \ base 122 drivers/net/fjes/fjes_regs.h writel((val), &base[(reg)]); \ base 309 drivers/net/hamradio/baycom_epp.c sprintf(portarg, "%ld", bc->pdev->port->base); base 837 drivers/net/hamradio/baycom_epp.c printk(KERN_ERR "%s: parport at 0x%lx has no irq\n", bc_drvname, pp->base); base 844 drivers/net/hamradio/baycom_epp.c bc_drvname, pp->base); base 866 drivers/net/hamradio/baycom_epp.c printk(KERN_ERR "%s: cannot register parport at 0x%lx\n", bc_drvname, pp->base); base 870 drivers/net/hamradio/baycom_epp.c printk(KERN_ERR "%s: parport at 0x%lx busy\n", bc_drvname, pp->base); base 310 drivers/net/hamradio/baycom_par.c printk(KERN_ERR "baycom_par: parport at 0x%lx has no irq\n", pp->base); base 315 drivers/net/hamradio/baycom_par.c printk(KERN_ERR "baycom_par: parport at 0x%lx cannot be used\n", pp->base); base 342 drivers/net/hamradio/baycom_par.c printk(KERN_ERR "baycom_par: parport at 0x%lx busy\n", pp->base); base 298 drivers/net/hamradio/dmascc.c int base[MAX_NUM_DEVS], tcmd[MAX_NUM_DEVS], t0[MAX_NUM_DEVS], base 318 drivers/net/hamradio/dmascc.c base[i] = 0; base 325 drivers/net/hamradio/dmascc.c base[j] = io[i]; base 331 drivers/net/hamradio/dmascc.c base[i] = base 338 drivers/net/hamradio/dmascc.c if (base[i]) { base 340 drivers/net/hamradio/dmascc.c (base[i], hw[h].io_size, "dmascc")) base 341 drivers/net/hamradio/dmascc.c base[i] = 0; base 344 drivers/net/hamradio/dmascc.c base[i] + hw[h].tmr_offset + base 347 drivers/net/hamradio/dmascc.c base[i] + hw[h].tmr_offset + base 350 drivers/net/hamradio/dmascc.c base[i] + hw[h].tmr_offset + base 357 drivers/net/hamradio/dmascc.c if (base[i]) { base 381 drivers/net/hamradio/dmascc.c if (base[i] && counting[i]) { base 396 drivers/net/hamradio/dmascc.c if (base[i]) { base 399 drivers/net/hamradio/dmascc.c (setup_adapter(base[i], h, n) == 0)) base 402 drivers/net/hamradio/dmascc.c release_region(base[i], base 1056 drivers/net/hyperv/netvsc_drv.c diff1.base.speed = 0; base 1057 drivers/net/hyperv/netvsc_drv.c diff1.base.duplex = 0; base 1060 drivers/net/hyperv/netvsc_drv.c diff1.base.cmd = 0; base 1062 drivers/net/hyperv/netvsc_drv.c diff2.base.port = PORT_OTHER; base 1084 drivers/net/hyperv/netvsc_drv.c cmd->base.speed = ndc->speed; base 1085 drivers/net/hyperv/netvsc_drv.c cmd->base.duplex = ndc->duplex; base 1086 drivers/net/hyperv/netvsc_drv.c cmd->base.port = PORT_OTHER; base 1097 drivers/net/hyperv/netvsc_drv.c speed = cmd->base.speed; base 1099 drivers/net/hyperv/netvsc_drv.c !ethtool_validate_duplex(cmd->base.duplex) || base 1104 drivers/net/hyperv/netvsc_drv.c ndc->duplex = cmd->base.duplex; base 594 drivers/net/macsec.c static void macsec_encrypt_done(struct crypto_async_request *base, int err) base 596 drivers/net/macsec.c struct sk_buff *skb = base->data; base 884 drivers/net/macsec.c static void macsec_decrypt_done(struct crypto_async_request *base, int err) base 886 drivers/net/macsec.c struct sk_buff *skb = base->data; base 365 drivers/net/mdio.c cmd->base.phy_address = mdio->prtad; base 366 drivers/net/mdio.c cmd->base.mdio_support = base 376 drivers/net/mdio.c cmd->base.port = PORT_TP; base 395 drivers/net/mdio.c cmd->base.port = PORT_OTHER; base 403 drivers/net/mdio.c cmd->base.port = PORT_OTHER; base 422 drivers/net/mdio.c cmd->base.port = PORT_FIBRE; base 433 drivers/net/mdio.c cmd->base.autoneg = AUTONEG_ENABLE; base 439 drivers/net/mdio.c cmd->base.autoneg = AUTONEG_DISABLE; base 442 drivers/net/mdio.c cmd->base.autoneg = AUTONEG_DISABLE; base 445 drivers/net/mdio.c if (cmd->base.autoneg) { base 467 drivers/net/mdio.c cmd->base.duplex = DUPLEX_FULL; base 472 drivers/net/mdio.c cmd->base.duplex = !(modes & ADVERTISED_1000baseT_Half); base 476 drivers/net/mdio.c cmd->base.duplex = !!(modes & ADVERTISED_100baseT_Full); base 479 drivers/net/mdio.c cmd->base.duplex = !!(modes & ADVERTISED_10baseT_Full); base 487 drivers/net/mdio.c cmd->base.duplex = (reg & MDIO_CTRL1_FULLDPLX || base 491 drivers/net/mdio.c cmd->base.speed = speed; base 501 drivers/net/mdio.c if (cmd->base.port == PORT_TP && (cmd->base.speed == SPEED_10000)) { base 505 drivers/net/mdio.c cmd->base.eth_tp_mdix = ETH_TP_MDI; base 508 drivers/net/mdio.c cmd->base.eth_tp_mdix = ETH_TP_MDI_X; base 512 drivers/net/mdio.c cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; base 160 drivers/net/mii.c cmd->base.port = PORT_MII; base 163 drivers/net/mii.c cmd->base.phy_address = mii->phy_id; base 164 drivers/net/mii.c cmd->base.mdio_support = ETH_MDIO_SUPPORTS_C22; base 176 drivers/net/mii.c cmd->base.autoneg = AUTONEG_ENABLE; base 194 drivers/net/mii.c cmd->base.speed = SPEED_1000; base 195 drivers/net/mii.c cmd->base.duplex = !!(nego & ADVERTISED_1000baseT_Full); base 198 drivers/net/mii.c cmd->base.speed = SPEED_100; base 199 drivers/net/mii.c cmd->base.duplex = !!(nego & ADVERTISED_100baseT_Full); base 201 drivers/net/mii.c cmd->base.speed = SPEED_10; base 202 drivers/net/mii.c cmd->base.duplex = !!(nego & ADVERTISED_10baseT_Full); base 205 drivers/net/mii.c cmd->base.autoneg = AUTONEG_DISABLE; base 207 drivers/net/mii.c cmd->base.speed = ((bmcr & BMCR_SPEED1000 && base 212 drivers/net/mii.c cmd->base.duplex = (bmcr & BMCR_FULLDPLX) ? base 218 drivers/net/mii.c mii->full_duplex = cmd->base.duplex; base 333 drivers/net/mii.c u32 speed = cmd->base.speed; base 339 drivers/net/mii.c if (cmd->base.duplex != DUPLEX_HALF && cmd->base.duplex != DUPLEX_FULL) base 341 drivers/net/mii.c if (cmd->base.port != PORT_MII) base 343 drivers/net/mii.c if (cmd->base.phy_address != mii->phy_id) base 345 drivers/net/mii.c if (cmd->base.autoneg != AUTONEG_DISABLE && base 346 drivers/net/mii.c cmd->base.autoneg != AUTONEG_ENABLE) base 353 drivers/net/mii.c if (cmd->base.autoneg == AUTONEG_ENABLE) { base 406 drivers/net/mii.c if (cmd->base.duplex == DUPLEX_FULL) { base 341 drivers/net/net_failover.c cmd->base.duplex = DUPLEX_UNKNOWN; base 342 drivers/net/net_failover.c cmd->base.port = PORT_OTHER; base 343 drivers/net/net_failover.c cmd->base.speed = SPEED_UNKNOWN; base 380 drivers/net/ntb_netdev.c cmd->base.speed = SPEED_UNKNOWN; base 381 drivers/net/ntb_netdev.c cmd->base.duplex = DUPLEX_FULL; base 382 drivers/net/ntb_netdev.c cmd->base.port = PORT_OTHER; base 383 drivers/net/ntb_netdev.c cmd->base.phy_address = 0; base 384 drivers/net/ntb_netdev.c cmd->base.autoneg = AUTONEG_ENABLE; base 13 drivers/net/phy/bcm-phy-lib.h #define MISC_ADDR(base, channel) base, channel base 39 drivers/net/phy/mdio-aspeed.c void __iomem *base; base 62 drivers/net/phy/mdio-aspeed.c iowrite32(ctrl, ctx->base + ASPEED_MDIO_CTRL); base 64 drivers/net/phy/mdio-aspeed.c rc = readl_poll_timeout(ctx->base + ASPEED_MDIO_DATA, data, base 93 drivers/net/phy/mdio-aspeed.c iowrite32(ctrl, ctx->base + ASPEED_MDIO_CTRL); base 95 drivers/net/phy/mdio-aspeed.c return readl_poll_timeout(ctx->base + ASPEED_MDIO_CTRL, ctrl, base 112 drivers/net/phy/mdio-aspeed.c ctx->base = devm_platform_ioremap_resource(pdev, 0); base 113 drivers/net/phy/mdio-aspeed.c if (IS_ERR(ctx->base)) base 114 drivers/net/phy/mdio-aspeed.c return PTR_ERR(ctx->base); base 38 drivers/net/phy/mdio-bcm-iproc.c void __iomem *base; base 41 drivers/net/phy/mdio-bcm-iproc.c static inline int iproc_mdio_wait_for_idle(void __iomem *base) base 47 drivers/net/phy/mdio-bcm-iproc.c val = readl(base + MII_CTRL_OFFSET); base 57 drivers/net/phy/mdio-bcm-iproc.c static inline void iproc_mdio_config_clk(void __iomem *base) base 63 drivers/net/phy/mdio-bcm-iproc.c writel(val, base + MII_CTRL_OFFSET); base 72 drivers/net/phy/mdio-bcm-iproc.c rc = iproc_mdio_wait_for_idle(priv->base); base 83 drivers/net/phy/mdio-bcm-iproc.c writel(cmd, priv->base + MII_DATA_OFFSET); base 85 drivers/net/phy/mdio-bcm-iproc.c rc = iproc_mdio_wait_for_idle(priv->base); base 89 drivers/net/phy/mdio-bcm-iproc.c cmd = readl(priv->base + MII_DATA_OFFSET) & MII_DATA_MASK; base 101 drivers/net/phy/mdio-bcm-iproc.c rc = iproc_mdio_wait_for_idle(priv->base); base 113 drivers/net/phy/mdio-bcm-iproc.c writel(cmd, priv->base + MII_DATA_OFFSET); base 115 drivers/net/phy/mdio-bcm-iproc.c rc = iproc_mdio_wait_for_idle(priv->base); base 132 drivers/net/phy/mdio-bcm-iproc.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 133 drivers/net/phy/mdio-bcm-iproc.c if (IS_ERR(priv->base)) { base 135 drivers/net/phy/mdio-bcm-iproc.c return PTR_ERR(priv->base); base 152 drivers/net/phy/mdio-bcm-iproc.c iproc_mdio_config_clk(priv->base); base 162 drivers/net/phy/mdio-bcm-iproc.c dev_info(&pdev->dev, "Broadcom iProc MDIO bus at 0x%p\n", priv->base); base 188 drivers/net/phy/mdio-bcm-iproc.c iproc_mdio_config_clk(priv->base); base 42 drivers/net/phy/mdio-bcm-unimac.c void __iomem *base; base 55 drivers/net/phy/mdio-bcm-unimac.c return __raw_readl(priv->base + offset); base 57 drivers/net/phy/mdio-bcm-unimac.c return readl_relaxed(priv->base + offset); base 64 drivers/net/phy/mdio-bcm-unimac.c __raw_writel(val, priv->base + offset); base 66 drivers/net/phy/mdio-bcm-unimac.c writel_relaxed(val, priv->base + offset); base 239 drivers/net/phy/mdio-bcm-unimac.c priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); base 240 drivers/net/phy/mdio-bcm-unimac.c if (!priv->base) { base 31 drivers/net/phy/mdio-moxart.c void __iomem *base; base 45 drivers/net/phy/mdio-moxart.c writel(ctrl, data->base + REG_PHY_CTRL); base 48 drivers/net/phy/mdio-moxart.c ctrl = readl(data->base + REG_PHY_CTRL); base 76 drivers/net/phy/mdio-moxart.c writel(value, data->base + REG_PHY_WRITE_DATA); base 77 drivers/net/phy/mdio-moxart.c writel(ctrl, data->base + REG_PHY_CTRL); base 80 drivers/net/phy/mdio-moxart.c ctrl = readl(data->base + REG_PHY_CTRL); base 140 drivers/net/phy/mdio-moxart.c data->base = devm_platform_ioremap_resource(pdev, 0); base 141 drivers/net/phy/mdio-moxart.c if (IS_ERR(data->base)) { base 142 drivers/net/phy/mdio-moxart.c ret = PTR_ERR(data->base); base 50 drivers/net/phy/mdio-mux-bcm-iproc.c void __iomem *base; base 62 drivers/net/phy/mdio-mux-bcm-iproc.c val = readl(md->base + MDIO_SCAN_CTRL_OFFSET); base 64 drivers/net/phy/mdio-mux-bcm-iproc.c writel(val, md->base + MDIO_SCAN_CTRL_OFFSET); base 74 drivers/net/phy/mdio-mux-bcm-iproc.c writel(val, md->base + MDIO_RATE_ADJ_EXT_OFFSET); base 75 drivers/net/phy/mdio-mux-bcm-iproc.c writel(val, md->base + MDIO_RATE_ADJ_INT_OFFSET); base 79 drivers/net/phy/mdio-mux-bcm-iproc.c static int iproc_mdio_wait_for_idle(void __iomem *base, bool result) base 85 drivers/net/phy/mdio-mux-bcm-iproc.c val = readl(base + MDIO_STAT_OFFSET); base 107 drivers/net/phy/mdio-mux-bcm-iproc.c static int start_miim_ops(void __iomem *base, base 113 drivers/net/phy/mdio-mux-bcm-iproc.c writel(0, base + MDIO_CTRL_OFFSET); base 114 drivers/net/phy/mdio-mux-bcm-iproc.c ret = iproc_mdio_wait_for_idle(base, 0); base 118 drivers/net/phy/mdio-mux-bcm-iproc.c param = readl(base + MDIO_PARAM_OFFSET); base 124 drivers/net/phy/mdio-mux-bcm-iproc.c writel(param, base + MDIO_PARAM_OFFSET); base 126 drivers/net/phy/mdio-mux-bcm-iproc.c writel(reg, base + MDIO_ADDR_OFFSET); base 128 drivers/net/phy/mdio-mux-bcm-iproc.c writel(op, base + MDIO_CTRL_OFFSET); base 130 drivers/net/phy/mdio-mux-bcm-iproc.c ret = iproc_mdio_wait_for_idle(base, 1); base 135 drivers/net/phy/mdio-mux-bcm-iproc.c ret = readl(base + MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK; base 145 drivers/net/phy/mdio-mux-bcm-iproc.c ret = start_miim_ops(md->base, phyid, reg, 0, MDIO_CTRL_READ_OP); base 159 drivers/net/phy/mdio-mux-bcm-iproc.c ret = start_miim_ops(md->base, phyid, reg, val, MDIO_CTRL_WRITE_OP); base 180 drivers/net/phy/mdio-mux-bcm-iproc.c writel(param, md->base + MDIO_PARAM_OFFSET); base 205 drivers/net/phy/mdio-mux-bcm-iproc.c md->base = devm_ioremap_resource(&pdev->dev, res); base 206 drivers/net/phy/mdio-mux-bcm-iproc.c if (IS_ERR(md->base)) { base 208 drivers/net/phy/mdio-mux-bcm-iproc.c return PTR_ERR(md->base); base 63 drivers/net/phy/mdio-mux-meson-g12a.c void __iomem *base; base 76 drivers/net/phy/mdio-mux-meson-g12a.c val = readl(pll->base + ETH_PLL_CTL0); base 86 drivers/net/phy/mdio-mux-meson-g12a.c u32 val = readl(pll->base + ETH_PLL_CTL0); base 90 drivers/net/phy/mdio-mux-meson-g12a.c writel(val, pll->base + ETH_PLL_CTL0); base 94 drivers/net/phy/mdio-mux-meson-g12a.c writel(val, pll->base + ETH_PLL_CTL0); base 101 drivers/net/phy/mdio-mux-meson-g12a.c return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val, base 110 drivers/net/phy/mdio-mux-meson-g12a.c val = readl(pll->base + ETH_PLL_CTL0); base 113 drivers/net/phy/mdio-mux-meson-g12a.c writel(val, pll->base + ETH_PLL_CTL0); base 121 drivers/net/phy/mdio-mux-meson-g12a.c val = readl(pll->base + ETH_PLL_CTL0); base 131 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x29c0040a, pll->base + ETH_PLL_CTL0); base 132 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x927e0000, pll->base + ETH_PLL_CTL1); base 133 drivers/net/phy/mdio-mux-meson-g12a.c writel(0xac5f49e5, pll->base + ETH_PLL_CTL2); base 134 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x00000000, pll->base + ETH_PLL_CTL3); base 135 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x00000000, pll->base + ETH_PLL_CTL4); base 136 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x20200000, pll->base + ETH_PLL_CTL5); base 137 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x0000c002, pll->base + ETH_PLL_CTL6); base 138 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x00000023, pll->base + ETH_PLL_CTL7); base 286 drivers/net/phy/mdio-mux-meson-g12a.c pll->base = priv->regs; base 319 drivers/net/phy/phy.c u8 autoneg = cmd->base.autoneg; base 320 drivers/net/phy/phy.c u8 duplex = cmd->base.duplex; base 321 drivers/net/phy/phy.c u32 speed = cmd->base.speed; base 323 drivers/net/phy/phy.c if (cmd->base.phy_address != phydev->mdio.addr) base 357 drivers/net/phy/phy.c phydev->mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; base 373 drivers/net/phy/phy.c cmd->base.speed = phydev->speed; base 374 drivers/net/phy/phy.c cmd->base.duplex = phydev->duplex; base 376 drivers/net/phy/phy.c cmd->base.port = PORT_BNC; base 378 drivers/net/phy/phy.c cmd->base.port = PORT_MII; base 379 drivers/net/phy/phy.c cmd->base.transceiver = phy_is_internal(phydev) ? base 381 drivers/net/phy/phy.c cmd->base.phy_address = phydev->mdio.addr; base 382 drivers/net/phy/phy.c cmd->base.autoneg = phydev->autoneg; base 383 drivers/net/phy/phy.c cmd->base.eth_tp_mdix_ctrl = phydev->mdix_ctrl; base 384 drivers/net/phy/phy.c cmd->base.eth_tp_mdix = phydev->mdix; base 1109 drivers/net/phy/phylink.c kset->base.speed = state->speed; base 1110 drivers/net/phy/phylink.c kset->base.duplex = state->duplex; base 1111 drivers/net/phy/phylink.c kset->base.autoneg = state->an_enabled ? AUTONEG_ENABLE : base 1134 drivers/net/phy/phylink.c kset->base.port = pl->link_port; base 1185 drivers/net/phy/phylink.c if (kset->base.autoneg != AUTONEG_DISABLE && base 1186 drivers/net/phy/phylink.c kset->base.autoneg != AUTONEG_ENABLE) base 1197 drivers/net/phy/phylink.c if (kset->base.autoneg == AUTONEG_DISABLE) { base 1203 drivers/net/phy/phylink.c s = phy_lookup_setting(kset->base.speed, kset->base.duplex, base 1242 drivers/net/phy/phylink.c our_kset.base.speed = config.speed; base 1243 drivers/net/phy/phylink.c our_kset.base.duplex = config.duplex; base 1256 drivers/net/phy/phylink.c pl->link_config.speed = our_kset.base.speed; base 1257 drivers/net/phy/phylink.c pl->link_config.duplex = our_kset.base.duplex; base 1258 drivers/net/phy/phylink.c pl->link_config.an_enabled = our_kset.base.autoneg != AUTONEG_DISABLE; base 53 drivers/net/phy/sfp-bus.c switch (id->base.connector) { base 72 drivers/net/phy/sfp-bus.c if (id->base.e1000_base_t) { base 87 drivers/net/phy/sfp-bus.c id->base.connector); base 125 drivers/net/phy/sfp-bus.c if (id->base.br_nominal) { base 126 drivers/net/phy/sfp-bus.c if (id->base.br_nominal != 255) { base 127 drivers/net/phy/sfp-bus.c br_nom = id->base.br_nominal * 100; base 128 drivers/net/phy/sfp-bus.c br_min = br_nom - id->base.br_nominal * id->ext.br_min; base 129 drivers/net/phy/sfp-bus.c br_max = br_nom + id->base.br_nominal * id->ext.br_max; base 140 drivers/net/phy/sfp-bus.c if (br_min == br_max && id->base.sfp_ct_passive) base 145 drivers/net/phy/sfp-bus.c if (id->base.e10g_base_sr) base 147 drivers/net/phy/sfp-bus.c if (id->base.e10g_base_lr) base 149 drivers/net/phy/sfp-bus.c if (id->base.e10g_base_lrm) base 151 drivers/net/phy/sfp-bus.c if (id->base.e10g_base_er) base 153 drivers/net/phy/sfp-bus.c if (id->base.e1000_base_sx || base 154 drivers/net/phy/sfp-bus.c id->base.e1000_base_lx || base 155 drivers/net/phy/sfp-bus.c id->base.e1000_base_cx) base 157 drivers/net/phy/sfp-bus.c if (id->base.e1000_base_t) { base 163 drivers/net/phy/sfp-bus.c if ((id->base.e_base_px || id->base.e_base_bx10) && base 170 drivers/net/phy/sfp-bus.c if ((id->base.sfp_ct_passive || id->base.sfp_ct_active) && br_nom) { base 179 drivers/net/phy/sfp-bus.c if (id->base.sfp_ct_passive) { base 180 drivers/net/phy/sfp-bus.c if (id->base.passive.sff8431_app_e) base 183 drivers/net/phy/sfp-bus.c if (id->base.sfp_ct_active) { base 184 drivers/net/phy/sfp-bus.c if (id->base.active.sff8431_app_e || base 185 drivers/net/phy/sfp-bus.c id->base.active.sff8431_lim) { base 190 drivers/net/phy/sfp-bus.c switch (id->base.extended_cc) { base 210 drivers/net/phy/sfp-bus.c id->base.extended_cc); base 215 drivers/net/phy/sfp-bus.c if (id->base.fc_speed_100 || base 216 drivers/net/phy/sfp-bus.c id->base.fc_speed_200 || base 217 drivers/net/phy/sfp-bus.c id->base.fc_speed_400) { base 218 drivers/net/phy/sfp-bus.c if (id->base.br_nominal >= 31) base 220 drivers/net/phy/sfp-bus.c if (id->base.br_nominal >= 12) base 231 drivers/net/phy/sfp-bus.c if (id->base.encoding == SFP_ENCODING_8B10B && br_nom && base 269 drivers/net/phy/sfp-bus.c if (id->base.e1000_base_t || base 270 drivers/net/phy/sfp-bus.c id->base.e100_base_lx || base 271 drivers/net/phy/sfp-bus.c id->base.e100_base_fx) base 212 drivers/net/phy/sfp.c return id->base.phys_id == SFP_PHYS_ID_SFF && base 213 drivers/net/phy/sfp.c id->base.phys_ext_id == SFP_PHYS_EXT_ID_SFP; base 223 drivers/net/phy/sfp.c return id->base.phys_id == SFP_PHYS_ID_SFP && base 224 drivers/net/phy/sfp.c id->base.phys_ext_id == SFP_PHYS_EXT_ID_SFP; base 1372 drivers/net/phy/sfp.c if (sfp->id.base.e1000_base_t || base 1373 drivers/net/phy/sfp.c sfp->id.base.e100_base_lx || base 1374 drivers/net/phy/sfp.c sfp->id.base.e100_base_fx) base 1463 drivers/net/phy/sfp.c cotsworks = !memcmp(id.base.vendor_name, "COTSWORKS ", 16); base 1466 drivers/net/phy/sfp.c check = sfp_check(&id.base, sizeof(id.base) - 1); base 1467 drivers/net/phy/sfp.c if (check != id.base.cc_base) { base 1471 drivers/net/phy/sfp.c check, id.base.cc_base); base 1475 drivers/net/phy/sfp.c check, id.base.cc_base); base 1501 drivers/net/phy/sfp.c (int)sizeof(id.base.vendor_name), id.base.vendor_name, base 1502 drivers/net/phy/sfp.c (int)sizeof(id.base.vendor_pn), id.base.vendor_pn, base 1503 drivers/net/phy/sfp.c (int)sizeof(id.base.vendor_rev), id.base.vendor_rev, base 1511 drivers/net/phy/sfp.c sfp->id.base.phys_id, sfp->id.base.phys_ext_id); base 1277 drivers/net/plip/plip.c dev->base_addr = port->base; base 2078 drivers/net/team/team.c cmd->base.duplex = DUPLEX_UNKNOWN; base 2079 drivers/net/team/team.c cmd->base.port = PORT_OTHER; base 2086 drivers/net/team/team.c if (cmd->base.duplex == DUPLEX_UNKNOWN && base 2088 drivers/net/team/team.c cmd->base.duplex = port->state.duplex; base 2093 drivers/net/team/team.c cmd->base.speed = speed ? : SPEED_UNKNOWN; base 2906 drivers/net/team/team.c port->state.speed = ecmd.base.speed; base 2907 drivers/net/team/team.c port->state.duplex = ecmd.base.duplex; base 3520 drivers/net/tun.c cmd->base.speed = SPEED_10; base 3521 drivers/net/tun.c cmd->base.duplex = DUPLEX_FULL; base 3522 drivers/net/tun.c cmd->base.port = PORT_TP; base 3523 drivers/net/tun.c cmd->base.phy_address = 0; base 3524 drivers/net/tun.c cmd->base.autoneg = AUTONEG_DISABLE; base 287 drivers/net/usb/aqc111.c elk->base.port = PORT_TP; base 288 drivers/net/usb/aqc111.c elk->base.transceiver = XCVR_INTERNAL; base 290 drivers/net/usb/aqc111.c elk->base.mdio_support = 0x00; /*Not supported*/ base 298 drivers/net/usb/aqc111.c elk->base.autoneg = aqc111_data->autoneg; base 314 drivers/net/usb/aqc111.c elk->base.duplex = DUPLEX_FULL; base 315 drivers/net/usb/aqc111.c elk->base.speed = speed; base 373 drivers/net/usb/aqc111.c u8 autoneg = elk->base.autoneg; base 374 drivers/net/usb/aqc111.c u32 speed = elk->base.speed; base 393 drivers/net/usb/aqc111.c if (elk->base.duplex != DUPLEX_FULL) base 695 drivers/net/usb/catc.c cmd->base.speed = SPEED_10; base 696 drivers/net/usb/catc.c cmd->base.duplex = DUPLEX_HALF; base 697 drivers/net/usb/catc.c cmd->base.port = PORT_TP; base 698 drivers/net/usb/catc.c cmd->base.phy_address = 0; base 699 drivers/net/usb/catc.c cmd->base.autoneg = AUTONEG_DISABLE; base 1195 drivers/net/usb/lan78xx.c if (ecmd.base.speed == 1000) { base 1223 drivers/net/usb/lan78xx.c ecmd.base.speed, ecmd.base.duplex, ladv, radv); base 1225 drivers/net/usb/lan78xx.c ret = lan78xx_update_flowcontrol(dev, ecmd.base.duplex, ladv, base 1539 drivers/net/usb/lan78xx.c if (!cmd->base.autoneg) { base 1580 drivers/net/usb/lan78xx.c if (pause->autoneg && !ecmd.base.autoneg) { base 1592 drivers/net/usb/lan78xx.c if (ecmd.base.autoneg) { base 5016 drivers/net/usb/r8152.c ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, base 5017 drivers/net/usb/r8152.c cmd->base.duplex, advertising); base 5019 drivers/net/usb/r8152.c tp->autoneg = cmd->base.autoneg; base 5020 drivers/net/usb/r8152.c tp->speed = cmd->base.speed; base 5021 drivers/net/usb/r8152.c tp->duplex = cmd->base.duplex; base 802 drivers/net/usb/rtl8150.c ecmd->base.port = PORT_TP; base 803 drivers/net/usb/rtl8150.c ecmd->base.phy_address = dev->phy; base 809 drivers/net/usb/rtl8150.c ecmd->base.speed = speed; base 810 drivers/net/usb/rtl8150.c ecmd->base.autoneg = AUTONEG_ENABLE; base 812 drivers/net/usb/rtl8150.c ecmd->base.duplex = (lpa & LPA_100FULL) ? base 815 drivers/net/usb/rtl8150.c ecmd->base.duplex = (lpa & LPA_10FULL) ? base 818 drivers/net/usb/rtl8150.c ecmd->base.autoneg = AUTONEG_DISABLE; base 819 drivers/net/usb/rtl8150.c ecmd->base.speed = ((bmcr & BMCR_SPEED100) ? base 821 drivers/net/usb/rtl8150.c ecmd->base.duplex = (bmcr & BMCR_FULLDPLX) ? base 853 drivers/net/usb/smsc95xx.c cmd->base.eth_tp_mdix = pdata->mdix_ctrl; base 854 drivers/net/usb/smsc95xx.c cmd->base.eth_tp_mdix_ctrl = pdata->mdix_ctrl; base 866 drivers/net/usb/smsc95xx.c if (pdata->mdix_ctrl != cmd->base.eth_tp_mdix_ctrl) base 867 drivers/net/usb/smsc95xx.c set_mdix_status(net, cmd->base.eth_tp_mdix_ctrl); base 102 drivers/net/veth.c cmd->base.speed = SPEED_10000; base 103 drivers/net/veth.c cmd->base.duplex = DUPLEX_FULL; base 104 drivers/net/veth.c cmd->base.port = PORT_TP; base 105 drivers/net/veth.c cmd->base.autoneg = AUTONEG_DISABLE; base 2181 drivers/net/virtio_net.c diff1.base.speed = 0; base 2182 drivers/net/virtio_net.c diff2.base.port = PORT_OTHER; base 2184 drivers/net/virtio_net.c diff1.base.duplex = 0; base 2185 drivers/net/virtio_net.c diff1.base.cmd = 0; base 2186 drivers/net/virtio_net.c diff1.base.link_mode_masks_nwords = 0; base 2188 drivers/net/virtio_net.c return !memcmp(&diff1.base, &diff2.base, sizeof(diff1.base)) && base 2203 drivers/net/virtio_net.c speed = cmd->base.speed; base 2206 drivers/net/virtio_net.c !ethtool_validate_duplex(cmd->base.duplex) || base 2210 drivers/net/virtio_net.c vi->duplex = cmd->base.duplex; base 2220 drivers/net/virtio_net.c cmd->base.speed = vi->speed; base 2221 drivers/net/virtio_net.c cmd->base.duplex = vi->duplex; base 2222 drivers/net/virtio_net.c cmd->base.port = PORT_OTHER; base 337 drivers/net/vmxnet3/vmxnet3_drv.c BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1); base 370 drivers/net/vmxnet3/vmxnet3_drv.c gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; base 382 drivers/net/vmxnet3/vmxnet3_drv.c gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; base 436 drivers/net/vmxnet3/vmxnet3_drv.c if (tq->tx_ring.base) { base 439 drivers/net/vmxnet3/vmxnet3_drv.c tq->tx_ring.base, tq->tx_ring.basePA); base 440 drivers/net/vmxnet3/vmxnet3_drv.c tq->tx_ring.base = NULL; base 442 drivers/net/vmxnet3/vmxnet3_drv.c if (tq->data_ring.base) { base 445 drivers/net/vmxnet3/vmxnet3_drv.c tq->data_ring.base, tq->data_ring.basePA); base 446 drivers/net/vmxnet3/vmxnet3_drv.c tq->data_ring.base = NULL; base 448 drivers/net/vmxnet3/vmxnet3_drv.c if (tq->comp_ring.base) { base 451 drivers/net/vmxnet3/vmxnet3_drv.c tq->comp_ring.base, tq->comp_ring.basePA); base 452 drivers/net/vmxnet3/vmxnet3_drv.c tq->comp_ring.base = NULL; base 481 drivers/net/vmxnet3/vmxnet3_drv.c memset(tq->tx_ring.base, 0, tq->tx_ring.size * base 486 drivers/net/vmxnet3/vmxnet3_drv.c memset(tq->data_ring.base, 0, base 490 drivers/net/vmxnet3/vmxnet3_drv.c memset(tq->comp_ring.base, 0, tq->comp_ring.size * base 510 drivers/net/vmxnet3/vmxnet3_drv.c BUG_ON(tq->tx_ring.base || tq->data_ring.base || base 511 drivers/net/vmxnet3/vmxnet3_drv.c tq->comp_ring.base || tq->buf_info); base 513 drivers/net/vmxnet3/vmxnet3_drv.c tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev, base 516 drivers/net/vmxnet3/vmxnet3_drv.c if (!tq->tx_ring.base) { base 521 drivers/net/vmxnet3/vmxnet3_drv.c tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev, base 524 drivers/net/vmxnet3/vmxnet3_drv.c if (!tq->data_ring.base) { base 529 drivers/net/vmxnet3/vmxnet3_drv.c tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, base 532 drivers/net/vmxnet3/vmxnet3_drv.c if (!tq->comp_ring.base) { base 579 drivers/net/vmxnet3/vmxnet3_drv.c gd = ring->base + ring->next2fill; base 689 drivers/net/vmxnet3/vmxnet3_drv.c ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill; base 738 drivers/net/vmxnet3/vmxnet3_drv.c gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; base 780 drivers/net/vmxnet3/vmxnet3_drv.c gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; base 803 drivers/net/vmxnet3/vmxnet3_drv.c tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base; base 921 drivers/net/vmxnet3/vmxnet3_drv.c tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base + base 1129 drivers/net/vmxnet3/vmxnet3_drv.c tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr), base 1293 drivers/net/vmxnet3/vmxnet3_drv.c vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, base 1321 drivers/net/vmxnet3/vmxnet3_drv.c vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd, base 1380 drivers/net/vmxnet3/vmxnet3_drv.c &rq->data_ring.base[sz], rcd->len); base 1553 drivers/net/vmxnet3/vmxnet3_drv.c vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd, base 1572 drivers/net/vmxnet3/vmxnet3_drv.c &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp); base 1592 drivers/net/vmxnet3/vmxnet3_drv.c &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc); base 1645 drivers/net/vmxnet3/vmxnet3_drv.c if (rq->rx_ring[i].base) { base 1649 drivers/net/vmxnet3/vmxnet3_drv.c rq->rx_ring[i].base, base 1651 drivers/net/vmxnet3/vmxnet3_drv.c rq->rx_ring[i].base = NULL; base 1655 drivers/net/vmxnet3/vmxnet3_drv.c if (rq->data_ring.base) { base 1658 drivers/net/vmxnet3/vmxnet3_drv.c rq->data_ring.base, rq->data_ring.basePA); base 1659 drivers/net/vmxnet3/vmxnet3_drv.c rq->data_ring.base = NULL; base 1662 drivers/net/vmxnet3/vmxnet3_drv.c if (rq->comp_ring.base) { base 1665 drivers/net/vmxnet3/vmxnet3_drv.c rq->comp_ring.base, rq->comp_ring.basePA); base 1666 drivers/net/vmxnet3/vmxnet3_drv.c rq->comp_ring.base = NULL; base 1686 drivers/net/vmxnet3/vmxnet3_drv.c if (rq->data_ring.base) { base 1690 drivers/net/vmxnet3/vmxnet3_drv.c rq->data_ring.base, base 1692 drivers/net/vmxnet3/vmxnet3_drv.c rq->data_ring.base = NULL; base 1725 drivers/net/vmxnet3/vmxnet3_drv.c memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size * base 1738 drivers/net/vmxnet3/vmxnet3_drv.c memset(rq->comp_ring.base, 0, rq->comp_ring.size * base 1779 drivers/net/vmxnet3/vmxnet3_drv.c rq->rx_ring[i].base = dma_alloc_coherent( base 1783 drivers/net/vmxnet3/vmxnet3_drv.c if (!rq->rx_ring[i].base) { base 1792 drivers/net/vmxnet3/vmxnet3_drv.c rq->data_ring.base = base 1796 drivers/net/vmxnet3/vmxnet3_drv.c if (!rq->data_ring.base) { base 1802 drivers/net/vmxnet3/vmxnet3_drv.c rq->data_ring.base = NULL; base 1807 drivers/net/vmxnet3/vmxnet3_drv.c rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz, base 1810 drivers/net/vmxnet3/vmxnet3_drv.c if (!rq->comp_ring.base) { base 2445 drivers/net/vmxnet3/vmxnet3_drv.c BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL); base 314 drivers/net/vmxnet3/vmxnet3_ethtool.c u8 *base; base 324 drivers/net/vmxnet3/vmxnet3_ethtool.c base = (u8 *)&adapter->tqd_start[j].stats; base 327 drivers/net/vmxnet3/vmxnet3_ethtool.c *buf++ = *(u64 *)(base + base 330 drivers/net/vmxnet3/vmxnet3_ethtool.c base = (u8 *)&adapter->tx_queue[j].stats; base 332 drivers/net/vmxnet3/vmxnet3_ethtool.c *buf++ = *(u64 *)(base + base 337 drivers/net/vmxnet3/vmxnet3_ethtool.c base = (u8 *)&adapter->rqd_start[j].stats; base 340 drivers/net/vmxnet3/vmxnet3_ethtool.c *buf++ = *(u64 *)(base + base 343 drivers/net/vmxnet3/vmxnet3_ethtool.c base = (u8 *)&adapter->rx_queue[j].stats; base 345 drivers/net/vmxnet3/vmxnet3_ethtool.c *buf++ = *(u64 *)(base + base 349 drivers/net/vmxnet3/vmxnet3_ethtool.c base = (u8 *)adapter; base 351 drivers/net/vmxnet3/vmxnet3_ethtool.c *buf++ = *(u64 *)(base + vmxnet3_global_stats[i].offset); base 495 drivers/net/vmxnet3/vmxnet3_ethtool.c ecmd->base.port = PORT_TP; base 498 drivers/net/vmxnet3/vmxnet3_ethtool.c ecmd->base.speed = adapter->link_speed; base 499 drivers/net/vmxnet3/vmxnet3_ethtool.c ecmd->base.duplex = DUPLEX_FULL; base 501 drivers/net/vmxnet3/vmxnet3_ethtool.c ecmd->base.speed = SPEED_UNKNOWN; base 502 drivers/net/vmxnet3/vmxnet3_ethtool.c ecmd->base.duplex = DUPLEX_UNKNOWN; base 130 drivers/net/vmxnet3/vmxnet3_int.h union Vmxnet3_GenericDesc *base; base 162 drivers/net/vmxnet3/vmxnet3_int.h union Vmxnet3_GenericDesc *base; base 181 drivers/net/vmxnet3/vmxnet3_int.h struct Vmxnet3_TxDataDesc *base; base 277 drivers/net/vmxnet3/vmxnet3_int.h Vmxnet3_RxDataDesc *base; base 427 drivers/net/wan/cosa.c static int cosa_probe(int base, int irq, int dma) base 442 drivers/net/wan/cosa.c if (base < 0x100 || base > 0x3ff || base & 0x7) { base 443 drivers/net/wan/cosa.c pr_info("invalid I/O address 0x%x\n", base); base 453 drivers/net/wan/cosa.c if (((base & 0x8) && dma < 4) || (!(base & 0x8) && dma > 3)) { base 455 drivers/net/wan/cosa.c base, dma); base 460 drivers/net/wan/cosa.c cosa->datareg = base; base 461 drivers/net/wan/cosa.c cosa->statusreg = is_8bit(cosa)?base+1:base+2; base 464 drivers/net/wan/cosa.c if (!request_region(base, is_8bit(cosa)?2:4,"cosa")) base 468 drivers/net/wan/cosa.c printk(KERN_DEBUG "probe at 0x%x failed.\n", base); base 481 drivers/net/wan/cosa.c pr_info("valid signature not found at 0x%x\n", base); base 487 drivers/net/wan/cosa.c release_region(base, is_8bit(cosa)?2:4); base 488 drivers/net/wan/cosa.c if (!request_region(base, is_8bit(cosa)?2:4, cosa->type)) { base 489 drivers/net/wan/cosa.c printk(KERN_DEBUG "changing name at 0x%x failed.\n", base); base 81 drivers/net/wan/sdla.c const void *base; base 89 drivers/net/wan/sdla.c base = (const void *) (dev->mem_start + offset); base 92 drivers/net/wan/sdla.c memcpy(temp, base, bytes); base 112 drivers/net/wan/sdla.c void *base; base 120 drivers/net/wan/sdla.c base = (void *) (dev->mem_start + offset); base 123 drivers/net/wan/sdla.c memcpy(base, temp, bytes); base 145 drivers/net/wan/sdla.c char *base; base 151 drivers/net/wan/sdla.c base = (void *) dev->mem_start; base 157 drivers/net/wan/sdla.c memset(base, 0, bytes); base 1331 drivers/net/wan/sdla.c unsigned base; base 1350 drivers/net/wan/sdla.c base = map->base_addr; base 1358 drivers/net/wan/sdla.c if (inb(base + i) != 0xFF) base 1362 drivers/net/wan/sdla.c outb(SDLA_HALT, base + SDLA_REG_Z80_CONTROL); base 1363 drivers/net/wan/sdla.c if ((inb(base + SDLA_S502_STS) & 0x0F) == 0x08) { base 1364 drivers/net/wan/sdla.c outb(SDLA_S502E_INTACK, base + SDLA_REG_CONTROL); base 1365 drivers/net/wan/sdla.c if ((inb(base + SDLA_S502_STS) & 0x0F) == 0x0C) { base 1366 drivers/net/wan/sdla.c outb(SDLA_HALT, base + SDLA_REG_CONTROL); base 1373 drivers/net/wan/sdla.c for(byte=inb(base),i=0;i<SDLA_IO_EXTENTS;i++) base 1374 drivers/net/wan/sdla.c if (inb(base + i) != byte) base 1378 drivers/net/wan/sdla.c outb(SDLA_HALT, base + SDLA_REG_CONTROL); base 1379 drivers/net/wan/sdla.c if ((inb(base + SDLA_S502_STS) & 0x7E) == 0x30) { base 1380 drivers/net/wan/sdla.c outb(SDLA_S507_ENABLE, base + SDLA_REG_CONTROL); base 1381 drivers/net/wan/sdla.c if ((inb(base + SDLA_S502_STS) & 0x7E) == 0x32) { base 1382 drivers/net/wan/sdla.c outb(SDLA_HALT, base + SDLA_REG_CONTROL); base 1389 drivers/net/wan/sdla.c outb(SDLA_HALT, base + SDLA_REG_CONTROL); base 1390 drivers/net/wan/sdla.c if ((inb(base + SDLA_S508_STS) & 0x3F) == 0x00) { base 1391 drivers/net/wan/sdla.c outb(SDLA_S508_INTEN, base + SDLA_REG_CONTROL); base 1392 drivers/net/wan/sdla.c if ((inb(base + SDLA_S508_STS) & 0x3F) == 0x10) { base 1393 drivers/net/wan/sdla.c outb(SDLA_HALT, base + SDLA_REG_CONTROL); base 1399 drivers/net/wan/sdla.c outb(SDLA_S502A_HALT, base + SDLA_REG_CONTROL); base 1400 drivers/net/wan/sdla.c if (inb(base + SDLA_S502_STS) == 0x40) { base 1401 drivers/net/wan/sdla.c outb(SDLA_S502A_START, base + SDLA_REG_CONTROL); base 1402 drivers/net/wan/sdla.c if (inb(base + SDLA_S502_STS) == 0x40) { base 1403 drivers/net/wan/sdla.c outb(SDLA_S502A_INTEN, base + SDLA_REG_CONTROL); base 1404 drivers/net/wan/sdla.c if (inb(base + SDLA_S502_STS) == 0x44) { base 1405 drivers/net/wan/sdla.c outb(SDLA_S502A_START, base + SDLA_REG_CONTROL); base 1417 drivers/net/wan/sdla.c switch(base) { base 1556 drivers/net/wan/sdla.c outb(byte, base + SDLA_REG_PC_WINDOW); base 1570 drivers/net/wan/sdla.c outb(flp->state, base + SDLA_REG_CONTROL); base 1573 drivers/net/wan/sdla.c dev->base_addr = base; base 1582 drivers/net/wan/sdla.c release_region(base, SDLA_IO_EXTENTS); base 726 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc *base = dest_ring->base_addr_owner_space; base 727 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index); base 757 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc_64 *base = dest_ring->base_addr_owner_space; base 759 drivers/net/wireless/ath/ath10k/ce.c CE_DEST_RING_TO_DESC_64(base, write_index); base 829 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc *base = dest_ring->base_addr_owner_space; base 830 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index); base 878 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc_64 *base = dest_ring->base_addr_owner_space; base 880 drivers/net/wireless/ath/ath10k/ce.c CE_DEST_RING_TO_DESC_64(base, sw_index); base 974 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc *base = dest_ring->base_addr_owner_space; base 975 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index); base 1027 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc_64 *base = dest_ring->base_addr_owner_space; base 1029 drivers/net/wireless/ath/ath10k/ce.c CE_DEST_RING_TO_DESC_64(base, sw_index); base 1190 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc *base = src_ring->base_addr_owner_space; base 1191 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc *desc = CE_SRC_RING_TO_DESC(base, sw_index); base 1207 drivers/net/wireless/ath/ath10k/ce.c struct ce_desc_64 *base = src_ring->base_addr_owner_space; base 1209 drivers/net/wireless/ath/ath10k/ce.c CE_SRC_RING_TO_DESC_64(base, sw_index); base 126 drivers/net/wireless/ath/ath10k/htc.h struct ath10k_htc_ready base; base 1389 drivers/net/wireless/ath/ath10k/wmi-tlv.c ath10k_wmi_pull_pdev_stats_base(&src->base, dst); base 2951 drivers/net/wireless/ath/ath10k/wmi.c ath10k_wmi_pull_pdev_stats_base(&src->base, dst); base 3005 drivers/net/wireless/ath/ath10k/wmi.c ath10k_wmi_pull_pdev_stats_base(&src->base, dst); base 3066 drivers/net/wireless/ath/ath10k/wmi.c ath10k_wmi_pull_pdev_stats_base(&src->base, dst); base 3143 drivers/net/wireless/ath/ath10k/wmi.c ath10k_wmi_pull_pdev_stats_base(&src->base, dst); base 3235 drivers/net/wireless/ath/ath10k/wmi.c ath10k_wmi_pull_pdev_stats_base(&src->base, dst); base 4638 drivers/net/wireless/ath/ath10k/wmi.h struct wmi_pdev_stats_base base; base 4654 drivers/net/wireless/ath/ath10k/wmi.h struct wmi_pdev_stats_base base; base 4667 drivers/net/wireless/ath/ath10k/wmi.h struct wmi_pdev_stats_base base; base 4678 drivers/net/wireless/ath/ath10k/wmi.h struct wmi_pdev_stats_base base; base 305 drivers/net/wireless/ath/wil6210/debugfs.c seq_printf(s, " base = 0x%08x\n", r.base); base 317 drivers/net/wireless/ath/wil6210/debugfs.c if (!wmi_addr(wil, r.base) || base 328 drivers/net/wireless/ath/wil6210/debugfs.c void __iomem *x = wil->csr + HOSTADDR(r.base) + delta; base 334 drivers/net/wireless/ath/wil6210/debugfs.c (r.tail - r.base == delta) ? "t" : " ", base 335 drivers/net/wireless/ath/wil6210/debugfs.c (r.head - r.base == delta) ? "h" : " ", base 465 drivers/net/wireless/ath/wil6210/debugfs.c struct dentry *dbg, void *base, base 474 drivers/net/wireless/ath/wil6210/debugfs.c base + tbl[i].off); base 478 drivers/net/wireless/ath/wil6210/debugfs.c base + tbl[i].off); base 482 drivers/net/wireless/ath/wil6210/debugfs.c dbg, base + tbl[i].off, base 487 drivers/net/wireless/ath/wil6210/debugfs.c dbg, base + tbl[i].off, base 492 drivers/net/wireless/ath/wil6210/debugfs.c base + tbl[i].off); base 1293 drivers/net/wireless/ath/wil6210/main.c le32_to_cpus(&r->base); base 466 drivers/net/wireless/ath/wil6210/wil6210.h u32 base; base 711 drivers/net/wireless/ath/wil6210/wmi.c next_head = r->base + ((r->head - r->base + sizeof(d_head)) % r->size); base 2000 drivers/net/wireless/ath/wil6210/wmi.c r->tail = r->base + ((r->tail - r->base + base 253 drivers/net/wireless/broadcom/b43/phy_ht.c static const u16 base[] = { 0x40, 0x60, 0x80 }; base 255 drivers/net/wireless/broadcom/b43/phy_ht.c for (i = 0; i < ARRAY_SIZE(base); i++) { base 257 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0); base 260 drivers/net/wireless/broadcom/b43/phy_ht.c for (i = 0; i < ARRAY_SIZE(base); i++) base 261 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0); base 576 drivers/net/wireless/broadcom/b43/phy_ht.c static const u16 base[] = { 0x840, 0x860, 0x880 }; base 582 drivers/net/wireless/broadcom/b43/phy_ht.c save_regs[core][1] = b43_phy_read(dev, base[core] + 6); base 583 drivers/net/wireless/broadcom/b43/phy_ht.c save_regs[core][2] = b43_phy_read(dev, base[core] + 7); base 584 drivers/net/wireless/broadcom/b43/phy_ht.c save_regs[core][0] = b43_phy_read(dev, base[core] + 0); base 586 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_write(dev, base[core] + 6, 0); base 587 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */ base 588 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_set(dev, base[core] + 0, 0x0400); base 589 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_set(dev, base[core] + 0, 0x1000); base 603 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_write(dev, base[core] + 0, save_regs[core][0]); base 604 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_write(dev, base[core] + 6, save_regs[core][1]); base 605 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_write(dev, base[core] + 7, save_regs[core][2]); base 73 drivers/net/wireless/broadcom/b43/xmit.c int base = ghz5 ? 0 : 4; base 77 drivers/net/wireless/broadcom/b43/xmit.c return base + 0; base 79 drivers/net/wireless/broadcom/b43/xmit.c return base + 1; base 81 drivers/net/wireless/broadcom/b43/xmit.c return base + 2; base 83 drivers/net/wireless/broadcom/b43/xmit.c return base + 3; base 85 drivers/net/wireless/broadcom/b43/xmit.c return base + 4; base 87 drivers/net/wireless/broadcom/b43/xmit.c return base + 5; base 89 drivers/net/wireless/broadcom/b43/xmit.c return base + 6; base 91 drivers/net/wireless/broadcom/b43/xmit.c return base + 7; base 1374 drivers/net/wireless/broadcom/b43legacy/main.c u16 base, int queueidx) base 1378 drivers/net/wireless/broadcom/b43legacy/main.c rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL); base 1868 drivers/net/wireless/broadcom/b43legacy/radio.c u16 base; base 1879 drivers/net/wireless/broadcom/b43legacy/radio.c base = b43legacy_get_txgain_base_band(txpower); base 1880 drivers/net/wireless/broadcom/b43legacy/radio.c base &= 0x000F; base 1881 drivers/net/wireless/broadcom/b43legacy/radio.c b43legacy_phy_write(dev, 0x0017, base | 0x0020); base 47 drivers/net/wireless/broadcom/b43legacy/xmit.c int base = aphy ? 0 : 4; base 51 drivers/net/wireless/broadcom/b43legacy/xmit.c return base + 0; base 53 drivers/net/wireless/broadcom/b43legacy/xmit.c return base + 1; base 55 drivers/net/wireless/broadcom/b43legacy/xmit.c return base + 2; base 57 drivers/net/wireless/broadcom/b43legacy/xmit.c return base + 3; base 59 drivers/net/wireless/broadcom/b43legacy/xmit.c return base + 4; base 61 drivers/net/wireless/broadcom/b43legacy/xmit.c return base + 5; base 63 drivers/net/wireless/broadcom/b43legacy/xmit.c return base + 6; base 65 drivers/net/wireless/broadcom/b43legacy/xmit.c return base + 7; base 541 drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c u32 addr = sdiodev->cc_core->base; base 564 drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c u32 addr = sdiodev->cc_core->base; base 605 drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c u32 addr = sdiodev->cc_core->base; base 636 drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c u32 addr = sdiodev->cc_core->base; base 96 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c #define CORE_SB(base, field) \ base 97 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c (base + SBCONFIGOFF + offsetof(struct sbconfig, field)) base 243 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh)); base 254 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c address = CORE_SB(core->pub.base, sbtmstatelow); base 281 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 val, base; base 284 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c base = core->pub.base; base 285 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); base 289 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); base 295 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); base 296 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), base 299 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); base 301 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)) base 304 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)); base 308 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); base 311 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c CORE_SB(base, sbimstate)); base 314 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c CORE_SB(base, sbimstate), val); base 316 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c CORE_SB(base, sbimstate)); base 319 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c CORE_SB(base, sbimstate)) & base 326 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val); base 327 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); base 331 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); base 334 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c CORE_SB(base, sbimstate)); base 337 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c CORE_SB(base, sbimstate), val); base 342 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), base 386 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 base; base 389 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c base = core->pub.base; base 401 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), base 404 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); base 408 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)); base 410 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0); base 412 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate)); base 415 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata); base 419 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), base 421 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); base 425 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), base 427 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); base 467 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u16 coreid, u32 base, base 477 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c core->pub.base = base; base 496 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c idx++, core->pub.id, core->pub.rev, core->pub.base, base 532 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg); base 538 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val); base 858 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 base, wrap; base 896 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap); base 901 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c core = brcmf_chip_add_core(ci, id, base, wrap); base 1023 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 base; base 1029 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c base = cc->pub.base; base 1033 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c CORE_CC_REG(base, capabilities)); base 1035 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c CORE_CC_REG(base, base 1042 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c CORE_CC_REG(pmu->base, pmucapabilities)); base 1326 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 base, addr, reg, pmu_cc3_mask = ~0; base 1336 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c base = brcmf_chip_get_chipcommon(pub)->base; base 1350 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c addr = CORE_CC_REG(pmu->base, chipcontrol_addr); base 1352 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c addr = CORE_CC_REG(pmu->base, chipcontrol_data); base 1356 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c addr = CORE_CC_REG(base, sr_control1); base 1361 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c addr = CORE_CC_REG(base, sr_control0); base 1365 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c addr = CORE_CC_REG(pmu->base, retention_ctl); base 1370 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c addr = CORE_CC_REG(pmu->base, pmucapabilities_ext); base 1375 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c addr = CORE_CC_REG(pmu->base, retention_ctl); base 10 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.h #define CORE_CC_REG(base, field) \ base 11 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.h (base + offsetof(struct chipcregs, field)) base 50 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.h u32 base; base 243 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c u32 base; base 543 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c bar0_win = core->base; base 547 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c if (bar0_win != core->base) { base 548 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c bar0_win = core->base; base 1084 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c core->base + SD_REG(tohostmailboxdata), base 1088 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), base 1209 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), base 2298 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); base 2454 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c brcmf_sdiod_writel(sdiodev, core->base + SD_REG(hostintmask), base 2480 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c brcmf_sdiod_writel(sdiodev, core->base + SD_REG(intstatus), base 2526 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c addr = core->base + SD_REG(intstatus); base 2550 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); base 3778 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c addr = CORE_CC_REG(pmu->base, chipcontrol_addr); base 3844 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c reg_addr = core->base + SD_REG(intstatus); base 4001 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol); base 4171 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailboxdata), base 4182 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c brcmf_sdiod_writel(sdiod, core->base + SD_REG(hostintmask), base 71 drivers/net/wireless/broadcom/brcm80211/brcmsmac/led.c if (!bcma_gpio || !gpio_is_valid(bcma_gpio->base)) base 78 drivers/net/wireless/broadcom/brcm80211/brcmsmac/led.c gpio = bcma_gpio->base + i; base 7457 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c u16 base = M_SSID; base 7464 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN); base 4387 drivers/net/wireless/intel/ipw2x00/ipw2100.c struct ipw2100_bd_queue *q, u32 base, u32 size, base 4395 drivers/net/wireless/intel/ipw2x00/ipw2100.c write_register(priv->net_dev, base, q->nic); base 1221 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 base; base 1224 drivers/net/wireless/intel/ipw2x00/ipw2200.c base = ipw_read32(priv, IPW_EVENT_LOG); base 1225 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_read_indirect(priv, base + sizeof(base) + sizeof(u32), base 1234 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 base = ipw_read32(priv, IPW_ERROR_LOG); base 1235 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 elem_len = ipw_read_reg32(priv, base); base 1256 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_read_indirect(priv, base + sizeof(base), (u8 *) error->elem, base 3742 drivers/net/wireless/intel/ipw2x00/ipw2200.c int count, u32 read, u32 write, u32 base, u32 size) base 3758 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_write32(priv, base, q->dma_addr); base 3768 drivers/net/wireless/intel/ipw2x00/ipw2200.c int count, u32 read, u32 write, u32 base, u32 size) base 3788 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_queue_init(priv, &q->q, count, read, write, base, size); base 11605 drivers/net/wireless/intel/ipw2x00/ipw2200.c void __iomem *base; base 11658 drivers/net/wireless/intel/ipw2x00/ipw2200.c base = pci_ioremap_bar(pdev, 0); base 11659 drivers/net/wireless/intel/ipw2x00/ipw2200.c if (!base) { base 11664 drivers/net/wireless/intel/ipw2x00/ipw2200.c priv->hw_base = base; base 11666 drivers/net/wireless/intel/ipw2x00/ipw2200.c IPW_DEBUG_INFO("pci_resource_base = %p\n", base); base 1342 drivers/net/wireless/intel/iwlegacy/3945-mac.c u32 desc, time, count, base, data1; base 1345 drivers/net/wireless/intel/iwlegacy/3945-mac.c base = le32_to_cpu(il->card_alive.error_event_table_ptr); base 1347 drivers/net/wireless/intel/iwlegacy/3945-mac.c if (!il3945_hw_valid_rtc_data_addr(base)) { base 1348 drivers/net/wireless/intel/iwlegacy/3945-mac.c IL_ERR("Not valid error log pointer 0x%08X\n", base); base 1352 drivers/net/wireless/intel/iwlegacy/3945-mac.c count = il_read_targ_mem(il, base); base 1364 drivers/net/wireless/intel/iwlegacy/3945-mac.c desc = il_read_targ_mem(il, base + i); base 1365 drivers/net/wireless/intel/iwlegacy/3945-mac.c time = il_read_targ_mem(il, base + i + 1 * sizeof(u32)); base 1366 drivers/net/wireless/intel/iwlegacy/3945-mac.c blink1 = il_read_targ_mem(il, base + i + 2 * sizeof(u32)); base 1367 drivers/net/wireless/intel/iwlegacy/3945-mac.c blink2 = il_read_targ_mem(il, base + i + 3 * sizeof(u32)); base 1368 drivers/net/wireless/intel/iwlegacy/3945-mac.c ilink1 = il_read_targ_mem(il, base + i + 4 * sizeof(u32)); base 1369 drivers/net/wireless/intel/iwlegacy/3945-mac.c ilink2 = il_read_targ_mem(il, base + i + 5 * sizeof(u32)); base 1370 drivers/net/wireless/intel/iwlegacy/3945-mac.c data1 = il_read_targ_mem(il, base + i + 6 * sizeof(u32)); base 106 drivers/net/wireless/intel/iwlegacy/3945.c u32 base; /* SRAM address of event log header */ base 159 drivers/net/wireless/intel/iwlegacy/3945.c base = le32_to_cpu(il->card_alive.log_event_table_ptr); base 160 drivers/net/wireless/intel/iwlegacy/3945.c if (!il3945_hw_valid_rtc_data_addr(base)) { base 161 drivers/net/wireless/intel/iwlegacy/3945.c IL_ERR("Invalid event log pointer 0x%08X\n", base); base 165 drivers/net/wireless/intel/iwlegacy/3945.c disable_ptr = il_read_targ_mem(il, base + (4 * sizeof(u32))); base 166 drivers/net/wireless/intel/iwlegacy/3945.c array_size = il_read_targ_mem(il, base + (5 * sizeof(u32))); base 5082 drivers/net/wireless/intel/iwlegacy/4965-mac.c u32 desc, time, count, base, data1; base 5087 drivers/net/wireless/intel/iwlegacy/4965-mac.c base = le32_to_cpu(il->card_alive_init.error_event_table_ptr); base 5089 drivers/net/wireless/intel/iwlegacy/4965-mac.c base = le32_to_cpu(il->card_alive.error_event_table_ptr); base 5091 drivers/net/wireless/intel/iwlegacy/4965-mac.c if (!il->ops->is_valid_rtc_data_addr(base)) { base 5093 drivers/net/wireless/intel/iwlegacy/4965-mac.c base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT"); base 5097 drivers/net/wireless/intel/iwlegacy/4965-mac.c count = il_read_targ_mem(il, base); base 5104 drivers/net/wireless/intel/iwlegacy/4965-mac.c desc = il_read_targ_mem(il, base + 1 * sizeof(u32)); base 5106 drivers/net/wireless/intel/iwlegacy/4965-mac.c pc = il_read_targ_mem(il, base + 2 * sizeof(u32)); base 5107 drivers/net/wireless/intel/iwlegacy/4965-mac.c blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32)); base 5108 drivers/net/wireless/intel/iwlegacy/4965-mac.c blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32)); base 5109 drivers/net/wireless/intel/iwlegacy/4965-mac.c ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32)); base 5110 drivers/net/wireless/intel/iwlegacy/4965-mac.c ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32)); base 5111 drivers/net/wireless/intel/iwlegacy/4965-mac.c data1 = il_read_targ_mem(il, base + 7 * sizeof(u32)); base 5112 drivers/net/wireless/intel/iwlegacy/4965-mac.c data2 = il_read_targ_mem(il, base + 8 * sizeof(u32)); base 5113 drivers/net/wireless/intel/iwlegacy/4965-mac.c line = il_read_targ_mem(il, base + 9 * sizeof(u32)); base 5114 drivers/net/wireless/intel/iwlegacy/4965-mac.c time = il_read_targ_mem(il, base + 11 * sizeof(u32)); base 5115 drivers/net/wireless/intel/iwlegacy/4965-mac.c hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32)); base 4911 drivers/net/wireless/intel/iwlegacy/common.c il_add_beacon_time(struct il_priv *il, u32 base, u32 addon, base 4914 drivers/net/wireless/intel/iwlegacy/common.c u32 base_low = base & il_beacon_time_mask_low(il, base 4921 drivers/net/wireless/intel/iwlegacy/common.c u32 res = (base & il_beacon_time_mask_high(il, base 1822 drivers/net/wireless/intel/iwlegacy/common.h __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon, base 107 drivers/net/wireless/intel/iwlwifi/dvm/devices.c static __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base, base 110 drivers/net/wireless/intel/iwlwifi/dvm/devices.c u32 base_low = base & iwl_beacon_time_mask_low(priv, base 115 drivers/net/wireless/intel/iwlwifi/dvm/devices.c u32 res = (base & iwl_beacon_time_mask_high(priv, base 429 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c u32 base; base 473 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c base = priv->device_pointers.error_event_table; base 474 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c if (!iwlagn_hw_valid_rtc_data_addr(base)) { base 479 drivers/net/wireless/intel/iwlwifi/dvm/mac80211.c iwl_trans_read_mem_bytes(priv->trans, base, base 403 drivers/net/wireless/intel/iwlwifi/dvm/main.c static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, base 413 drivers/net/wireless/intel/iwlwifi/dvm/main.c ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32)); base 415 drivers/net/wireless/intel/iwlwifi/dvm/main.c ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); base 462 drivers/net/wireless/intel/iwlwifi/dvm/main.c u32 base; /* SRAM byte address of event log header */ base 467 drivers/net/wireless/intel/iwlwifi/dvm/main.c base = priv->device_pointers.log_event_table; base 468 drivers/net/wireless/intel/iwlwifi/dvm/main.c if (iwlagn_hw_valid_rtc_data_addr(base)) { base 469 drivers/net/wireless/intel/iwlwifi/dvm/main.c iwl_trans_read_mem_bytes(priv->trans, base, base 499 drivers/net/wireless/intel/iwlwifi/dvm/main.c priv, base, priv->event_log.next_entry, base 516 drivers/net/wireless/intel/iwlwifi/dvm/main.c priv, base, priv->event_log.next_entry, base 521 drivers/net/wireless/intel/iwlwifi/dvm/main.c priv, base, 0, next_entry, capacity, mode); base 524 drivers/net/wireless/intel/iwlwifi/dvm/main.c priv, base, next_entry, base 529 drivers/net/wireless/intel/iwlwifi/dvm/main.c priv, base, 0, next_entry, capacity, mode); base 1624 drivers/net/wireless/intel/iwlwifi/dvm/main.c u32 base; base 1627 drivers/net/wireless/intel/iwlwifi/dvm/main.c base = priv->device_pointers.error_event_table; base 1629 drivers/net/wireless/intel/iwlwifi/dvm/main.c if (!base) base 1630 drivers/net/wireless/intel/iwlwifi/dvm/main.c base = priv->fw->init_errlog_ptr; base 1632 drivers/net/wireless/intel/iwlwifi/dvm/main.c if (!base) base 1633 drivers/net/wireless/intel/iwlwifi/dvm/main.c base = priv->fw->inst_errlog_ptr; base 1636 drivers/net/wireless/intel/iwlwifi/dvm/main.c if (!iwlagn_hw_valid_rtc_data_addr(base)) { base 1639 drivers/net/wireless/intel/iwlwifi/dvm/main.c base, base 1646 drivers/net/wireless/intel/iwlwifi/dvm/main.c iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table)); base 1701 drivers/net/wireless/intel/iwlwifi/dvm/main.c u32 base; /* SRAM byte address of event log header */ base 1712 drivers/net/wireless/intel/iwlwifi/dvm/main.c base = priv->device_pointers.log_event_table; base 1714 drivers/net/wireless/intel/iwlwifi/dvm/main.c if (!base) base 1715 drivers/net/wireless/intel/iwlwifi/dvm/main.c base = priv->fw->init_evtlog_ptr; base 1717 drivers/net/wireless/intel/iwlwifi/dvm/main.c if (!base) base 1718 drivers/net/wireless/intel/iwlwifi/dvm/main.c base = priv->fw->inst_evtlog_ptr; base 1726 drivers/net/wireless/intel/iwlwifi/dvm/main.c ptr = base + EVENT_START_OFFSET + (start_idx * event_size); base 1813 drivers/net/wireless/intel/iwlwifi/dvm/main.c u32 base; /* SRAM byte address of event log header */ base 1824 drivers/net/wireless/intel/iwlwifi/dvm/main.c base = priv->device_pointers.log_event_table; base 1827 drivers/net/wireless/intel/iwlwifi/dvm/main.c if (!base) base 1828 drivers/net/wireless/intel/iwlwifi/dvm/main.c base = priv->fw->init_evtlog_ptr; base 1831 drivers/net/wireless/intel/iwlwifi/dvm/main.c if (!base) base 1832 drivers/net/wireless/intel/iwlwifi/dvm/main.c base = priv->fw->inst_evtlog_ptr; base 1835 drivers/net/wireless/intel/iwlwifi/dvm/main.c if (!iwlagn_hw_valid_rtc_data_addr(base)) { base 1838 drivers/net/wireless/intel/iwlwifi/dvm/main.c base, base 1845 drivers/net/wireless/intel/iwlwifi/dvm/main.c capacity = iwl_trans_read_mem32(trans, base); base 1846 drivers/net/wireless/intel/iwlwifi/dvm/main.c mode = iwl_trans_read_mem32(trans, base + (1 * sizeof(u32))); base 1847 drivers/net/wireless/intel/iwlwifi/dvm/main.c num_wraps = iwl_trans_read_mem32(trans, base + (2 * sizeof(u32))); base 1848 drivers/net/wireless/intel/iwlwifi/dvm/main.c next_entry = iwl_trans_read_mem32(trans, base + (3 * sizeof(u32))); base 1899 drivers/net/wireless/intel/iwlwifi/mvm/d3.c u32 base = mvm->trans->dbg.lmac_error_event_table[0]; base 1906 drivers/net/wireless/intel/iwlwifi/mvm/d3.c iwl_trans_read_mem_bytes(mvm->trans, base, base 466 drivers/net/wireless/intel/iwlwifi/mvm/utils.c u32 base = mvm->trans->dbg.umac_error_event_table; base 473 drivers/net/wireless/intel/iwlwifi/mvm/utils.c iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table)); base 505 drivers/net/wireless/intel/iwlwifi/mvm/utils.c u32 val, base = mvm->trans->dbg.lmac_error_event_table[lmac_num]; base 508 drivers/net/wireless/intel/iwlwifi/mvm/utils.c if (!base) base 509 drivers/net/wireless/intel/iwlwifi/mvm/utils.c base = mvm->fw->init_errlog_ptr; base 511 drivers/net/wireless/intel/iwlwifi/mvm/utils.c if (!base) base 512 drivers/net/wireless/intel/iwlwifi/mvm/utils.c base = mvm->fw->inst_errlog_ptr; base 515 drivers/net/wireless/intel/iwlwifi/mvm/utils.c if (base < 0x400000) { base 518 drivers/net/wireless/intel/iwlwifi/mvm/utils.c base, base 525 drivers/net/wireless/intel/iwlwifi/mvm/utils.c val = iwl_trans_read_mem32(trans, base); base 539 drivers/net/wireless/intel/iwlwifi/mvm/utils.c iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table)); base 3086 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; base 3089 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; base 3096 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); base 3098 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base = MON_BUFF_BASE_ADDR; base 3107 drivers/net/wireless/intel/iwlwifi/pcie/trans.c cpu_to_le32(iwl_read_prph(trans, base)); base 3142 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); base 3148 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base = (iwl_read_prph(trans, base) & base 3151 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base *= IWL_M2S_UNIT_SIZE; base 3152 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base += trans->cfg->smem_offset; base 3154 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base = iwl_read_prph(trans, base) << base 3158 drivers/net/wireless/intel/iwlwifi/pcie/trans.c iwl_trans_read_mem(trans, base, fw_mon_data->data, base 3185 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 base, end, cfg_reg, monitor_len; base 3190 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << base 3192 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base *= IWL_M2S_UNIT_SIZE; base 3193 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base += trans->cfg->smem_offset; base 3200 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); base 3203 drivers/net/wireless/intel/iwlwifi/pcie/trans.c base = iwl_read_prph(trans, base) << base 3213 drivers/net/wireless/intel/iwlwifi/pcie/trans.c monitor_len = end - base; base 134 drivers/net/wireless/intersil/p54/p54spi.c static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base, base 147 drivers/net/wireless/intersil/p54/p54spi.c p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base); base 63 drivers/net/wireless/intersil/prism54/isl_38xx.h isl38xx_w32_flush(void __iomem *base, u32 val, unsigned long offset) base 65 drivers/net/wireless/intersil/prism54/isl_38xx.h writel(val, base + offset); base 66 drivers/net/wireless/intersil/prism54/isl_38xx.h (void) readl(base + ISL38XX_PCI_POSTING_FLUSH); base 44 drivers/net/wireless/mediatek/mt76/mmio.c static int mt76_mmio_wr_rp(struct mt76_dev *dev, u32 base, base 56 drivers/net/wireless/mediatek/mt76/mmio.c static int mt76_mmio_rd_rp(struct mt76_dev *dev, u32 base, base 45 drivers/net/wireless/mediatek/mt76/mt76.h int (*wr_rp)(struct mt76_dev *dev, u32 base, base 47 drivers/net/wireless/mediatek/mt76/mt76.h int (*rd_rp)(struct mt76_dev *dev, u32 base, base 141 drivers/net/wireless/mediatek/mt76/mt76.h int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, base 143 drivers/net/wireless/mediatek/mt76/mt76.h int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, base 405 drivers/net/wireless/mediatek/mt76/mt76.h u32 base; base 56 drivers/net/wireless/mediatek/mt76/mt7603/core.c u32 base = addr & MT_MCU_PCIE_REMAP_2_BASE; base 59 drivers/net/wireless/mediatek/mt76/mt7603/core.c dev->bus_ops->wr(&dev->mt76, MT_MCU_PCIE_REMAP_2, base); base 7 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c mt7603_efuse_read(struct mt7603_dev *dev, u32 base, u16 addr, u8 *data) base 12 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_CTRL); base 17 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c mt76_wr(dev, base + MT_EFUSE_CTRL, val); base 19 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c if (!mt76_poll(dev, base + MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000)) base 24 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_CTRL); base 32 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_RDATA(i)); base 42 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c u32 base = mt7603_reg_map(dev, MT_EFUSE_BASE); base 47 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c if (mt76_rr(dev, base + MT_EFUSE_BASE_CTRL) & MT_EFUSE_BASE_CTRL_EMPTY) base 57 drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c ret = mt7603_efuse_read(dev, base, i, buf + i); base 99 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 base = mt7603_wtbl2_addr(MT7603_WTBL_SIZE); base 101 drivers/net/wireless/mediatek/mt76/mt7603/mac.c return base + idx * MT_WTBL3_SIZE; base 107 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 base = mt7603_wtbl3_addr(MT7603_WTBL_SIZE); base 109 drivers/net/wireless/mediatek/mt76/mt7603/mac.c return base + idx * MT_WTBL4_SIZE; base 11 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c static int mt7615_efuse_read(struct mt7615_dev *dev, u32 base, base 17 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_CTRL); base 21 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c mt76_wr(dev, base + MT_EFUSE_CTRL, val); base 23 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c if (!mt76_poll(dev, base + MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000)) base 28 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_CTRL); base 36 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_RDATA(i)); base 45 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c u32 val, base = mt7615_reg_map(dev, MT_EFUSE_BASE); base 49 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c val = mt76_rr(dev, base + MT_EFUSE_BASE_CTRL); base 62 drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c ret = mt7615_efuse_read(dev, base, i, buf + i); base 22 drivers/net/wireless/mediatek/mt76/mt7615/pci.c u32 base = addr & MT_MCU_PCIE_REMAP_2_BASE; base 25 drivers/net/wireless/mediatek/mt76/mt7615/pci.c mt76_wr(dev, MT_MCU_PCIE_REMAP_2, base); base 57 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c int mt76x02_get_efuse_data(struct mt76x02_dev *dev, u16 base, void *buf, base 63 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c ret = mt76x02_efuse_read(dev, base + i, buf + i, mode); base 175 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h int mt76x02_get_efuse_data(struct mt76x02_dev *dev, u16 base, void *buf, base 30 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c reg = usb->mcu.rp[0].reg - usb->mcu.base; base 41 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c usb->mcu.base; base 143 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c mt76x02u_mcu_wr_rp(struct mt76_dev *dev, u32 base, base 163 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c skb_put_le32(skb, base + data[i].reg); base 173 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c return mt76x02u_mcu_wr_rp(dev, base, data + cnt, n - cnt); base 177 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c mt76x02u_mcu_rd_rp(struct mt76_dev *dev, u32 base, base 199 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c skb_put_le32(skb, base + data[i].reg); base 207 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c usb->mcu.base = base; base 184 drivers/net/wireless/mediatek/mt76/usb.c mt76u_req_wr_rp(struct mt76_dev *dev, u32 base, base 191 drivers/net/wireless/mediatek/mt76/usb.c __mt76u_wr(dev, base + data->reg, data->value); base 201 drivers/net/wireless/mediatek/mt76/usb.c mt76u_wr_rp(struct mt76_dev *dev, u32 base, base 205 drivers/net/wireless/mediatek/mt76/usb.c return dev->mcu_ops->mcu_wr_rp(dev, base, data, n); base 207 drivers/net/wireless/mediatek/mt76/usb.c return mt76u_req_wr_rp(dev, base, data, n); base 211 drivers/net/wireless/mediatek/mt76/usb.c mt76u_req_rd_rp(struct mt76_dev *dev, u32 base, struct mt76_reg_pair *data, base 218 drivers/net/wireless/mediatek/mt76/usb.c data->value = __mt76u_rr(dev, base + data->reg); base 228 drivers/net/wireless/mediatek/mt76/usb.c mt76u_rd_rp(struct mt76_dev *dev, u32 base, base 232 drivers/net/wireless/mediatek/mt76/usb.c return dev->mcu_ops->mcu_rd_rp(dev, base, data, n); base 234 drivers/net/wireless/mediatek/mt76/usb.c return mt76u_req_rd_rp(dev, base, data, n); base 138 drivers/net/wireless/mediatek/mt7601u/init.c u16 base = MT_BEACON_BASE; base 145 drivers/net/wireless/mediatek/mt7601u/init.c regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4)); base 208 drivers/net/wireless/mediatek/mt7601u/mcu.c int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base, base 226 drivers/net/wireless/mediatek/mt7601u/mcu.c skb_put_le32(skb, base + data[i].reg); base 234 drivers/net/wireless/mediatek/mt7601u/mcu.c return mt7601u_write_reg_pairs(dev, base, data + cnt, n - cnt); base 326 drivers/net/wireless/mediatek/mt7601u/mt7601u.h int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base, base 76 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct qtnf_pcie_bus_priv base; base 168 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c void __iomem *reg = ps->base.sysctl_bar + PEARL_PCIE_CFG0_OFFSET; base 179 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c void __iomem *reg = ps->base.sysctl_bar + base 184 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c pci_restore_state(ps->base.pdev); base 191 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c void __iomem *reg = ps->base.sysctl_bar + base 233 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct qtnf_pcie_bus_priv *priv = &ps->base; base 285 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct qtnf_pcie_bus_priv *priv = &ps->base; base 333 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c ps->base.rx_bd_num * sizeof(struct qtnf_pearl_rx_bd)); base 335 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c for (i = 0; i < ps->base.rx_bd_num; i++) { base 347 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct qtnf_pcie_bus_priv *priv = &ps->base; base 396 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c writel(ps->base.rx_bd_num, PCIE_HHBM_Q_LIMIT_REG(ps->pcie_reg_base)); base 404 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct qtnf_pcie_bus_priv *priv = &ps->base; base 465 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct qtnf_pcie_bus_priv *priv = &ps->base; base 517 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct qtnf_pcie_bus_priv *priv = &ps->base; base 537 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct qtnf_pcie_bus_priv *priv = &ps->base; base 614 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct qtnf_pcie_bus_priv *priv = &ps->base; base 657 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c u16 index = ps->base.rx_bd_r_index; base 674 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct qtnf_pcie_bus_priv *priv = &ps->base; base 779 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c tasklet_hi_schedule(&ps->base.reclaim_tq); base 816 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c seq_printf(s, "pcie_irq_count(%u)\n", ps->base.pcie_irq_count); base 837 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct qtnf_pcie_bus_priv *priv = &ps->base; base 930 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c len = qtnf_ep_fw_send(ps->base.pdev, fw_size, blk, pblk, fw); base 985 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct pci_dev *pdev = ps->base.pdev; base 989 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c if (ps->base.flashboot) { base 1005 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c if (!ps->base.flashboot) base 1013 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c if (ps->base.flashboot) { base 1073 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c struct pci_dev *pdev = ps->base.pdev; base 1080 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c ps->pcie_reg_base = ps->base.dmareg_bar; base 1081 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c ps->bda = ps->base.epmem_bar; base 1082 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c writel(ps->base.msi_enabled, &ps->bda->bda_rc_msi_enabled); base 1105 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c tasklet_init(&ps->base.reclaim_tq, qtnf_pearl_reclaim_tasklet_fn, base 1112 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c qtnf_pcie_init_shm_ipc(&ps->base, &ps->bda->bda_shm_reg1, base 1148 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c ps->base.probe_cb = qtnf_pcie_pearl_probe; base 1149 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c ps->base.remove_cb = qtnf_pcie_pearl_remove; base 1150 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c ps->base.dma_mask_get_cb = qtnf_pearl_dma_mask_get; base 1152 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c ps->base.resume_cb = qtnf_pcie_pearl_resume; base 1153 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c ps->base.suspend_cb = qtnf_pcie_pearl_suspend; base 8 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CTRL(base) ((base) + 0x2c00) base 9 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04) base 10 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10) base 11 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14) base 12 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_HOST_WR_DESC1(base) ((base) + 0x2c18) base 13 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_HOST_WR_DESC1_H(base) ((base) + 0x2c1c) base 14 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_HOST_WR_DESC2(base) ((base) + 0x2c20) base 15 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_HOST_WR_DESC2_H(base) ((base) + 0x2c24) base 16 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_HOST_WR_DESC3(base) ((base) + 0x2c28) base 17 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_HOST_WR_DESC4_H(base) ((base) + 0x2c2c) base 18 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX_INT_CTRL(base) ((base) + 0x2c30) base 19 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX_INT_CTRL(base) ((base) + 0x2c34) base 20 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_INT_STATUS(base) ((base) + 0x2c38) base 21 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_INT_EN(base) ((base) + 0x2c3c) base 22 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX_DESC0_PTR(base) ((base) + 0x2c40) base 23 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX_DESC0_NOE(base) ((base) + 0x2c44) base 24 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX_DESC1_PTR(base) ((base) + 0x2c48) base 25 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX_DESC1_NOE(base) ((base) + 0x2c4c) base 26 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX_DESC2_PTR(base) ((base) + 0x2c50) base 27 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX_DESC2_NOE(base) ((base) + 0x2c54) base 28 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX_DESC3_PTR(base) ((base) + 0x2c58) base 29 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX_DESC3_NOE(base) ((base) + 0x2c5c) base 31 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX0_BASE_ADDR(base) ((base) + 0x2c60) base 32 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX1_BASE_ADDR(base) ((base) + 0x2c64) base 33 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX0_Q_CTRL(base) ((base) + 0x2c70) base 34 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX1_Q_CTRL(base) ((base) + 0x2c74) base 35 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG0(base) ((base) + 0x2c80) base 36 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG1(base) ((base) + 0x2c84) base 37 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG2(base) ((base) + 0x2c88) base 38 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG3(base) ((base) + 0x2c8c) base 39 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG4(base) ((base) + 0x2c90) base 40 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG5(base) ((base) + 0x2c94) base 41 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG6(base) ((base) + 0x2c98) base 42 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG7(base) ((base) + 0x2c9c) base 43 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG8(base) ((base) + 0x2ca0) base 44 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG9(base) ((base) + 0x2ca4) base 45 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG10(base) ((base) + 0x2ca8) base 46 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CFG11(base) ((base) + 0x2cac) base 47 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_INT(base) ((base) + 0x2cb0) base 48 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_INT_MASK(base) ((base) + 0x2cb4) base 49 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_MSI_MASK(base) ((base) + 0x2cb8) base 50 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_MSI_PNDG(base) ((base) + 0x2cbc) base 51 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_PRI_CFG(base) ((base) + 0x2cc0) base 52 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_PHY_CR(base) ((base) + 0x2cc4) base 53 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_CTAG_CTRL(base) ((base) + 0x2cf4) base 54 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_HHBM_BUF_PTR(base) ((base) + 0x2d00) base 55 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_HHBM_BUF_PTR_H(base) ((base) + 0x2d04) base 56 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_HHBM_BUF_FIFO_NOE(base) ((base) + 0x2d04) base 57 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX0DMA_CNT(base) ((base) + 0x2d10) base 58 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX1DMA_CNT(base) ((base) + 0x2d14) base 59 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX2DMA_CNT(base) ((base) + 0x2d18) base 60 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RX3DMA_CNT(base) ((base) + 0x2d1c) base 61 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX0DMA_CNT(base) ((base) + 0x2d20) base 62 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX1DMA_CNT(base) ((base) + 0x2d24) base 63 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_RXDMA_CTRL(base) ((base) + 0x2d28) base 64 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX_HOST_Q_SZ_CTRL(base) ((base) + 0x2d2c) base 65 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX_HOST_Q_BASE_L(base) ((base) + 0x2d30) base 66 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX_HOST_Q_BASE_H(base) ((base) + 0x2d34) base 67 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX_HOST_Q_WR_PTR(base) ((base) + 0x2d38) base 68 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX_HOST_Q_RD_PTR(base) ((base) + 0x2d3c) base 69 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HDP_TX_HOST_Q_STS(base) ((base) + 0x2d40) base 72 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_CSR_REG(base) ((base) + 0x2e00) base 73 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_Q_BASE_REG(base) ((base) + 0x2e04) base 74 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_Q_LIMIT_REG(base) ((base) + 0x2e08) base 75 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_Q_WR_REG(base) ((base) + 0x2e0c) base 76 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_Q_RD_REG(base) ((base) + 0x2e10) base 77 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_POOL_DATA_0_H(base) ((base) + 0x2e90) base 78 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_CONFIG(base) ((base) + 0x2f9c) base 79 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_POOL_REQ_0(base) ((base) + 0x2f10) base 80 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_POOL_DATA_0(base) ((base) + 0x2f40) base 81 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_WATERMARK_MASKED_INT(base) ((base) + 0x2f68) base 82 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_WATERMARK_INT(base) ((base) + 0x2f6c) base 83 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_POOL_WATERMARK(base) ((base) + 0x2f70) base 84 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_POOL_OVERFLOW_CNT(base) ((base) + 0x2f90) base 85 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_POOL_UNDERFLOW_CNT(base) ((base) + 0x2f94) base 86 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define HBM_INT_STATUS(base) ((base) + 0x2f9c) base 87 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h #define PCIE_HHBM_POOL_CNFIG(base) ((base) + 0x2f9c) base 86 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct qtnf_pcie_bus_priv base; base 104 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c void __iomem *reg = ts->base.sysctl_bar + TOPAZ_PCIE_CFG0_OFFSET; base 114 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c void __iomem *reg = ts->base.sysctl_bar + TOPAZ_PCIE_CFG0_OFFSET; base 123 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c TOPAZ_LH_IPC4_INT(ts->base.sysctl_bar)); base 125 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c pci_restore_state(ts->base.pdev); base 130 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c void __iomem *reg = PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(ts->base.dmareg_bar); base 137 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c void __iomem *reg = PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(ts->base.dmareg_bar); base 144 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c void __iomem *reg = PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(ts->base.dmareg_bar); base 154 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c TOPAZ_CTL_M2L_INT(ts->base.sysctl_bar)); base 186 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct qtnf_pcie_bus_priv *priv = &ts->base; base 253 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->base.rx_skb[index] = NULL; base 257 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->base.rx_skb[index] = skb; base 259 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c paddr = pci_map_single(ts->base.pdev, skb->data, base 261 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c if (pci_dma_mapping_error(ts->base.pdev, paddr)) { base 269 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->base.rx_bd_w_index = index; base 280 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->base.rx_bd_num * sizeof(struct qtnf_topaz_rx_bd)); base 282 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c for (i = 0; i < ts->base.rx_bd_num; i++) { base 288 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->rx_bd_vbase[ts->base.rx_bd_num - 1].info |= base 297 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct qtnf_pcie_bus_priv *priv = &ts->base; base 339 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct qtnf_pcie_bus_priv *priv = &ts->base; base 382 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct qtnf_pcie_bus_priv *priv = &ts->base; base 440 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->base.tx_stopped = 1; base 450 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c TOPAZ_LH_IPC4_INT(ts->base.sysctl_bar)); base 453 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c tasklet_hi_schedule(&ts->base.reclaim_tq); base 467 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c TOPAZ_LH_IPC4_INT(ts->base.sysctl_bar)); base 473 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct qtnf_pcie_bus_priv *priv = &ts->base; base 492 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct qtnf_pcie_bus_priv *priv = &ts->base; base 564 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct qtnf_pcie_bus_priv *priv = &ts->base; base 589 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c u16 index = ts->base.rx_bd_r_index; base 606 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct qtnf_pcie_bus_priv *priv = &ts->base; base 720 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c tasklet_hi_schedule(&ts->base.reclaim_tq); base 755 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c seq_printf(s, "pcie_irq_count(%u)\n", ts->base.pcie_irq_count); base 764 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct qtnf_pcie_bus_priv *priv = &ts->base; base 859 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c writeb(ts->base.msi_enabled, &ts->bda->bda_rc_msi_enabled); base 865 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c if (ts->base.flashboot) base 884 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct pci_dev *pdev = ts->base.pdev; base 901 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct pci_dev *pdev = ts->base.pdev; base 915 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c blksize = ts->base.fw_blksize; base 1003 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct pci_dev *pdev = ts->base.pdev; base 1035 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct pci_dev *pdev = ts->base.pdev; base 1053 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c if (ts->base.flashboot) { base 1119 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct pci_dev *pdev = ts->base.pdev; base 1126 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->bda = ts->base.epmem_bar; base 1129 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c if (ts->base.msi_enabled) base 1156 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c tasklet_init(&ts->base.reclaim_tq, qtnf_reclaim_tasklet_fn, base 1163 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c qtnf_pcie_init_shm_ipc(&ts->base, &ts->bda->bda_shm_reg1, base 1181 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct pci_dev *pdev = ts->base.pdev; base 1186 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c TOPAZ_LH_IPC4_INT(ts->base.sysctl_bar)); base 1198 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c struct pci_dev *pdev = ts->base.pdev; base 1207 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c TOPAZ_LH_IPC4_INT(ts->base.sysctl_bar)); base 1223 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->base.probe_cb = qtnf_pcie_topaz_probe; base 1224 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->base.remove_cb = qtnf_pcie_topaz_remove; base 1225 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->base.dma_mask_get_cb = qtnf_topaz_dma_mask_get; base 1227 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->base.resume_cb = qtnf_pcie_topaz_resume; base 1228 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->base.suspend_cb = qtnf_pcie_topaz_suspend; base 8 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc) base 9 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4) base 10 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8) base 11 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc) base 12 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0) base 13 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4) base 15 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310) base 16 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319) base 17 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c) base 18 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324) base 19 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_RD_ERR_STATUS_HIGH(base) ((base) + 0x328) base 20 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_RD_DONE_IMWR_ADDR_LOW(base) ((base) + 0x33c) base 21 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define PCIE_DMA_RD_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x340) base 24 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define TOPAZ_LH_IPC4_INT(base) ((base) + 0x13C) base 25 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define TOPAZ_LH_IPC4_INT_MASK(base) ((base) + 0x140) base 34 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define TOPAZ_CTL_M2L_INT(base) ((base) + 0x2C) base 35 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie_regs.h #define TOPAZ_CTL_M2L_INT_MASK(base) ((base) + 0x30) base 819 drivers/net/wireless/ralink/rt2x00/rt2x00.h void __iomem *base; base 24 drivers/net/wireless/ralink/rt2x00/rt2x00mmio.h return readl(rt2x00dev->csr.base + offset); base 31 drivers/net/wireless/ralink/rt2x00/rt2x00mmio.h memcpy_fromio(value, rt2x00dev->csr.base + offset, length); base 38 drivers/net/wireless/ralink/rt2x00/rt2x00mmio.h writel(value, rt2x00dev->csr.base + offset); base 46 drivers/net/wireless/ralink/rt2x00/rt2x00mmio.h __iowrite32_copy(rt2x00dev->csr.base + offset, value, length >> 2); base 33 drivers/net/wireless/ralink/rt2x00/rt2x00pci.c if (rt2x00dev->csr.base) { base 34 drivers/net/wireless/ralink/rt2x00/rt2x00pci.c iounmap(rt2x00dev->csr.base); base 35 drivers/net/wireless/ralink/rt2x00/rt2x00pci.c rt2x00dev->csr.base = NULL; base 43 drivers/net/wireless/ralink/rt2x00/rt2x00pci.c rt2x00dev->csr.base = pci_ioremap_bar(pci_dev, 0); base 44 drivers/net/wireless/ralink/rt2x00/rt2x00pci.c if (!rt2x00dev->csr.base) base 31 drivers/net/wireless/ralink/rt2x00/rt2x00soc.c iounmap(rt2x00dev->csr.base); base 43 drivers/net/wireless/ralink/rt2x00/rt2x00soc.c rt2x00dev->csr.base = ioremap(res->start, resource_size(res)); base 44 drivers/net/wireless/ralink/rt2x00/rt2x00soc.c if (!rt2x00dev->csr.base) base 349 drivers/net/wireless/realtek/rtlwifi/efuse.c u8 section_idx, i, base; base 354 drivers/net/wireless/realtek/rtlwifi/efuse.c base = section_idx * 8; base 358 drivers/net/wireless/realtek/rtlwifi/efuse.c if (rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] != base 359 drivers/net/wireless/realtek/rtlwifi/efuse.c rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i] || base 360 drivers/net/wireless/realtek/rtlwifi/efuse.c rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i + 1] != base 361 drivers/net/wireless/realtek/rtlwifi/efuse.c rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i + base 415 drivers/net/wireless/realtek/rtlwifi/efuse.c u16 i, offset, base; base 436 drivers/net/wireless/realtek/rtlwifi/efuse.c base = offset * 8; base 442 drivers/net/wireless/realtek/rtlwifi/efuse.c rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] = base 443 drivers/net/wireless/realtek/rtlwifi/efuse.c rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i]; base 446 drivers/net/wireless/realtek/rtlwifi/efuse.c if (rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] != base 447 drivers/net/wireless/realtek/rtlwifi/efuse.c rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i]) { base 450 drivers/net/wireless/realtek/rtlwifi/efuse.c rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] = base 451 drivers/net/wireless/realtek/rtlwifi/efuse.c rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i]; base 460 drivers/net/wireless/realtek/rtlwifi/efuse.c &rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base], base 53 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h u8 base:4; base 63 drivers/net/wireless/realtek/rtlwifi/pwrseqcmd.h #define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base) base 483 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c u8 base = 0, path = 0; base 490 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base = (raw >> 4) * 10 + (raw & 0xF); base 493 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base); base 498 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base = (raw >> 4) * 10 + (raw & 0xF); base 501 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base); base 505 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base = (raw >> 4) * 10 + (raw & 0xF); base 507 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c OFDM, RF_1TX, base); base 511 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base = (raw >> 4) * 10 + (raw & 0xF); base 514 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base); base 518 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base = (raw >> 4) * 10 + (raw & 0xF); base 521 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base); base 526 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c u8 end, u8 base) base 539 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c tmp = (tmp > base) ? tmp - base : base - tmp; base 553 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c u8 base = 0, rf = 0, band = BAND_ON_2_4G; base 557 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, base 563 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c 1, 1, base); base 567 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c 1, 3, base); base 569 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, base 575 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c 0, 0, base); base 579 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c 1, 3, base); base 581 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, base 585 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c 0, 3, base); base 588 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c 0, 3, base); base 590 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, base 595 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c 0, 3, base); base 598 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c 0, 3, base); base 600 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, base 605 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c 0, 3, base); base 609 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c 0, 3, base); base 370 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c u8 base = 0, path = 0; base 376 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 378 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c BAND_ON_2_4G, path, CCK, RF_1TX, base); base 382 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 386 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c RF_1TX, base); base 390 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 393 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c base); base 397 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 400 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c RF_1TX, base); base 404 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 407 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c RF_2TX, base); base 442 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c u8 base = 0, rfpath = RF90_PATH_A; base 444 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c base = _rtl8723be_phy_get_txpower_by_rate_base(hw, base 448 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c 1, 1, base); base 451 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c 1, 3, base); base 453 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, base 457 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c 0, 3, base); base 460 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c 0, 3, base); base 462 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, base 466 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c 0, 3, base); base 469 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c 0, 3, base); base 471 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c base = _rtl8723be_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, base 476 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c 0, 3, base); base 480 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c 0, 3, base); base 1060 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c u8 base = 0, path = 0; base 1064 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 1065 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, CCK, RF_1TX, base); base 1068 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 1069 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, OFDM, RF_1TX, base); base 1072 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 1073 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base); base 1076 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 1077 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base); base 1080 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 1081 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base); base 1084 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 1085 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base); base 1088 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 1089 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, OFDM, RF_1TX, base); base 1092 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 1093 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base); base 1096 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 1097 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base); base 1100 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 1101 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base); base 1104 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); base 1105 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base); base 1476 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c u8 base = 0, rfpath = 0; base 1479 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, CCK); base 1482 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1484 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, OFDM); base 1487 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1490 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1492 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, HT_MCS0_MCS7); base 1495 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1498 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1500 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, HT_MCS8_MCS15); base 1504 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1508 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1510 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9); base 1513 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1516 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1519 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 1, base); base 1521 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9); base 1524 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 2, 3, base); base 1527 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1530 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1532 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, OFDM); base 1535 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1538 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1540 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, HT_MCS0_MCS7); base 1543 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1546 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1548 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, HT_MCS8_MCS15); base 1551 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1554 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1556 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9); base 1559 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1562 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1565 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 1, base); base 1567 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9); base 1570 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 2, 3, base); base 1573 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 1576 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c 0, 3, base); base 109 drivers/net/wireless/realtek/rtw88/mac.c if (cmd->base == RTW_PWR_ADDR_SDIO) base 155 drivers/net/wireless/realtek/rtw88/mac.c if (cur_cmd->base == RTW_PWR_ADDR_SDIO) base 695 drivers/net/wireless/realtek/rtw88/main.h u8 base:4; base 1742 drivers/net/wireless/realtek/rtw88/phy.c u8 *base = &pwr_param->pwr_base; base 1752 drivers/net/wireless/realtek/rtw88/phy.c *base = rtw_phy_get_2g_tx_power_index(rtwdev, base 1758 drivers/net/wireless/realtek/rtw88/phy.c *base = rtw_phy_get_5g_tx_power_index(rtwdev, base 1907 drivers/net/wireless/realtek/rtw88/phy.c s8 base; base 1911 drivers/net/wireless/realtek/rtw88/phy.c base = hal->tx_pwr_by_rate_base_2g[0][rs]; base 1912 drivers/net/wireless/realtek/rtw88/phy.c hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base; base 1916 drivers/net/wireless/realtek/rtw88/phy.c base = hal->tx_pwr_by_rate_base_5g[0][rs]; base 1917 drivers/net/wireless/realtek/rtw88/phy.c hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base; base 301 drivers/ntb/hw/amd/ntb_hw_amd.c phys_addr_t *base, resource_size_t *size) base 310 drivers/ntb/hw/amd/ntb_hw_amd.c if (base) base 311 drivers/ntb/hw/amd/ntb_hw_amd.c *base = pci_resource_start(ndev->ntb.pdev, bar); base 1253 drivers/ntb/hw/idt/ntb_hw_idt.c phys_addr_t *base, resource_size_t *size) base 1261 drivers/ntb/hw/idt/ntb_hw_idt.c if (base != NULL) base 1262 drivers/ntb/hw/idt/ntb_hw_idt.c *base = pci_resource_start(ntb->pdev, ndev->mws[widx].bar) + base 73 drivers/ntb/hw/intel/ntb_hw_gen1.c #define bar0_off(base, bar) ((base) + ((bar) << 2)) base 74 drivers/ntb/hw/intel/ntb_hw_gen1.c #define bar2_off(base, bar) bar0_off(base, (bar) - 2) base 846 drivers/ntb/hw/intel/ntb_hw_gen1.c u64 base, limit, reg_val; base 880 drivers/ntb/hw/intel/ntb_hw_gen1.c base = ioread64(mmio + base_reg) & NTB_BAR_MASK_64; base 884 drivers/ntb/hw/intel/ntb_hw_gen1.c limit = base + size; base 900 drivers/ntb/hw/intel/ntb_hw_gen1.c iowrite64(base, mmio + limit_reg); base 911 drivers/ntb/hw/intel/ntb_hw_gen1.c base = ioread32(mmio + base_reg) & NTB_BAR_MASK_32; base 915 drivers/ntb/hw/intel/ntb_hw_gen1.c limit = base + size; base 931 drivers/ntb/hw/intel/ntb_hw_gen1.c iowrite32(base, mmio + limit_reg); base 1024 drivers/ntb/hw/intel/ntb_hw_gen1.c phys_addr_t *base, resource_size_t *size) base 1036 drivers/ntb/hw/intel/ntb_hw_gen1.c if (base) base 1037 drivers/ntb/hw/intel/ntb_hw_gen1.c *base = pci_resource_start(ndev->ntb.pdev, bar) + base 163 drivers/ntb/hw/intel/ntb_hw_gen1.h phys_addr_t *base, resource_size_t *size); base 451 drivers/ntb/hw/intel/ntb_hw_gen3.c u64 base, limit, reg_val; base 482 drivers/ntb/hw/intel/ntb_hw_gen3.c base = pci_resource_start(ndev->ntb.pdev, bar); base 486 drivers/ntb/hw/intel/ntb_hw_gen3.c limit = base + size; base 488 drivers/ntb/hw/intel/ntb_hw_gen3.c limit = base + mw_size; base 504 drivers/ntb/hw/intel/ntb_hw_gen3.c iowrite64(base, mmio + limit_reg); base 513 drivers/ntb/hw/intel/ntb_hw_gen3.c base = ioread64(mmio + GEN3_EMBAR1_OFFSET + (8 * idx)); base 514 drivers/ntb/hw/intel/ntb_hw_gen3.c base &= ~0xf; base 517 drivers/ntb/hw/intel/ntb_hw_gen3.c limit = base + size; base 519 drivers/ntb/hw/intel/ntb_hw_gen3.c limit = base + mw_size; base 525 drivers/ntb/hw/intel/ntb_hw_gen3.c iowrite64(base, mmio + limit_reg); base 350 drivers/ntb/hw/mscc/ntb_hw_switchtec.c int idx, phys_addr_t *base, base 369 drivers/ntb/hw/mscc/ntb_hw_switchtec.c if (base) base 370 drivers/ntb/hw/mscc/ntb_hw_switchtec.c *base = pci_resource_start(sndev->ntb.pdev, bar) + offset; base 385 drivers/ntb/hw/mscc/ntb_hw_switchtec.c int idx, phys_addr_t *base, base 393 drivers/ntb/hw/mscc/ntb_hw_switchtec.c if (base) base 394 drivers/ntb/hw/mscc/ntb_hw_switchtec.c *base = pci_resource_start(sndev->ntb.pdev, bar) + offset; base 403 drivers/ntb/hw/mscc/ntb_hw_switchtec.c phys_addr_t *base, base 409 drivers/ntb/hw/mscc/ntb_hw_switchtec.c return switchtec_ntb_direct_get_addr(sndev, idx, base, size); base 411 drivers/ntb/hw/mscc/ntb_hw_switchtec.c return switchtec_ntb_lut_get_addr(sndev, idx, base, size); base 151 drivers/nubus/nubus.c unsigned char *p = nd->base; base 222 drivers/nubus/nubus.c dir->ptr = dir->base = board->directory; base 232 drivers/nubus/nubus.c dir->ptr = dir->base = fres->directory; base 244 drivers/nubus/nubus.c dir->ptr = dir->base = board->directory; base 261 drivers/nubus/nubus.c dir->ptr = dir->base = nubus_dirptr(ent); base 276 drivers/nubus/nubus.c ent->base = nd->ptr; base 299 drivers/nubus/nubus.c dir->ptr = dir->base; base 506 drivers/nubus/nubus.c fres->directory = dir.base; base 127 drivers/nubus/proc.c ent.base = pde_data->res_ptr; base 268 drivers/nvdimm/label.c void *base = to_namespace_index(ndd, 0); base 270 drivers/nvdimm/label.c return base + 2 * sizeof_namespace_index(ndd); base 276 drivers/nvdimm/label.c unsigned long label, base; base 279 drivers/nvdimm/label.c base = (unsigned long) nd_label_base(ndd); base 281 drivers/nvdimm/label.c return (label - base) / sizeof_namespace_label(ndd); base 286 drivers/nvdimm/label.c unsigned long label, base; base 288 drivers/nvdimm/label.c base = (unsigned long) nd_label_base(ndd); base 289 drivers/nvdimm/label.c label = base + sizeof_namespace_label(ndd) * slot; base 647 drivers/nvdimm/pfn_devs.c static unsigned long init_altmap_base(resource_size_t base) base 649 drivers/nvdimm/pfn_devs.c unsigned long base_pfn = PHYS_PFN(base); base 654 drivers/nvdimm/pfn_devs.c static unsigned long init_altmap_reserve(resource_size_t base) base 657 drivers/nvdimm/pfn_devs.c unsigned long base_pfn = PHYS_PFN(base); base 674 drivers/nvdimm/pfn_devs.c resource_size_t base = nsio->res.start + start_pad; base 677 drivers/nvdimm/pfn_devs.c .base_pfn = init_altmap_base(base), base 678 drivers/nvdimm/pfn_devs.c .reserve = init_altmap_reserve(base), base 442 drivers/nvme/host/multipath.c void *base = ctrl->ana_log_buf; base 449 drivers/nvme/host/multipath.c struct nvme_ana_group_desc *desc = base + offset; base 83 drivers/nvmem/bcm-ocotp.c void __iomem *base; base 88 drivers/nvmem/bcm-ocotp.c static inline void set_command(void __iomem *base, u32 command) base 90 drivers/nvmem/bcm-ocotp.c writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET); base 93 drivers/nvmem/bcm-ocotp.c static inline void set_cpu_address(void __iomem *base, u32 addr) base 95 drivers/nvmem/bcm-ocotp.c writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET); base 98 drivers/nvmem/bcm-ocotp.c static inline void set_start_bit(void __iomem *base) base 100 drivers/nvmem/bcm-ocotp.c writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET); base 103 drivers/nvmem/bcm-ocotp.c static inline void reset_start_bit(void __iomem *base) base 105 drivers/nvmem/bcm-ocotp.c writel(0, base + OTPC_CMD_START_OFFSET); base 108 drivers/nvmem/bcm-ocotp.c static inline void write_cpu_data(void __iomem *base, u32 value) base 110 drivers/nvmem/bcm-ocotp.c writel(value, base + OTPC_CPU_WRITE_REG_OFFSET); base 113 drivers/nvmem/bcm-ocotp.c static int poll_cpu_status(void __iomem *base, u32 value) base 119 drivers/nvmem/bcm-ocotp.c status = readl(base + OTPC_CPU_STATUS_OFFSET); base 130 drivers/nvmem/bcm-ocotp.c static int enable_ocotp_program(void __iomem *base) base 137 drivers/nvmem/bcm-ocotp.c set_command(base, OTPC_CMD_OTP_PROG_ENABLE); base 139 drivers/nvmem/bcm-ocotp.c write_cpu_data(base, vals[i]); base 140 drivers/nvmem/bcm-ocotp.c set_start_bit(base); base 141 drivers/nvmem/bcm-ocotp.c ret = poll_cpu_status(base, OTPC_STAT_CMD_DONE); base 142 drivers/nvmem/bcm-ocotp.c reset_start_bit(base); base 147 drivers/nvmem/bcm-ocotp.c return poll_cpu_status(base, OTPC_STAT_PROG_OK); base 150 drivers/nvmem/bcm-ocotp.c static int disable_ocotp_program(void __iomem *base) base 154 drivers/nvmem/bcm-ocotp.c set_command(base, OTPC_CMD_OTP_PROG_DISABLE); base 155 drivers/nvmem/bcm-ocotp.c set_start_bit(base); base 156 drivers/nvmem/bcm-ocotp.c ret = poll_cpu_status(base, OTPC_STAT_PROG_OK); base 157 drivers/nvmem/bcm-ocotp.c reset_start_bit(base); base 172 drivers/nvmem/bcm-ocotp.c set_command(priv->base, OTPC_CMD_READ); base 173 drivers/nvmem/bcm-ocotp.c set_cpu_address(priv->base, address++); base 174 drivers/nvmem/bcm-ocotp.c set_start_bit(priv->base); base 175 drivers/nvmem/bcm-ocotp.c ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE); base 182 drivers/nvmem/bcm-ocotp.c *buf++ = readl(priv->base + base 187 drivers/nvmem/bcm-ocotp.c reset_start_bit(priv->base); base 205 drivers/nvmem/bcm-ocotp.c ret = enable_ocotp_program(priv->base); base 210 drivers/nvmem/bcm-ocotp.c set_command(priv->base, OTPC_CMD_PROGRAM); base 211 drivers/nvmem/bcm-ocotp.c set_cpu_address(priv->base, address++); base 213 drivers/nvmem/bcm-ocotp.c writel(*buf, priv->base + priv->map->data_w_offset[i]); base 217 drivers/nvmem/bcm-ocotp.c set_start_bit(priv->base); base 218 drivers/nvmem/bcm-ocotp.c ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE); base 219 drivers/nvmem/bcm-ocotp.c reset_start_bit(priv->base); base 226 drivers/nvmem/bcm-ocotp.c disable_ocotp_program(priv->base); base 273 drivers/nvmem/bcm-ocotp.c priv->base = devm_ioremap_resource(dev, res); base 274 drivers/nvmem/bcm-ocotp.c if (IS_ERR(priv->base)) { base 276 drivers/nvmem/bcm-ocotp.c return PTR_ERR(priv->base); base 280 drivers/nvmem/bcm-ocotp.c writel(readl(priv->base + OTPC_MODE_REG_OFFSET) | base 282 drivers/nvmem/bcm-ocotp.c priv->base + OTPC_MODE_REG_OFFSET); base 283 drivers/nvmem/bcm-ocotp.c reset_start_bit(priv->base); base 29 drivers/nvmem/imx-iim.c void __iomem *base; base 48 drivers/nvmem/imx-iim.c *buf8++ = readl(iim->base + IIM_BANK_BASE(bank) + reg * 4); base 110 drivers/nvmem/imx-iim.c iim->base = devm_platform_ioremap_resource(pdev, 0); base 111 drivers/nvmem/imx-iim.c if (IS_ERR(iim->base)) base 112 drivers/nvmem/imx-iim.c return PTR_ERR(iim->base); base 60 drivers/nvmem/imx-ocotp.c void __iomem *base; base 71 drivers/nvmem/imx-ocotp.c static int imx_ocotp_wait_for_busy(void __iomem *base, u32 flags) base 79 drivers/nvmem/imx-ocotp.c c = readl(base + IMX_OCOTP_ADDR_CTRL); base 108 drivers/nvmem/imx-ocotp.c static void imx_ocotp_clr_err_if_set(void __iomem *base) base 112 drivers/nvmem/imx-ocotp.c c = readl(base + IMX_OCOTP_ADDR_CTRL); base 116 drivers/nvmem/imx-ocotp.c writel(IMX_OCOTP_BM_CTRL_ERROR, base + IMX_OCOTP_ADDR_CTRL_CLR); base 143 drivers/nvmem/imx-ocotp.c ret = imx_ocotp_wait_for_busy(priv->base, 0); base 150 drivers/nvmem/imx-ocotp.c *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 + base 160 drivers/nvmem/imx-ocotp.c imx_ocotp_clr_err_if_set(priv->base); base 214 drivers/nvmem/imx-ocotp.c timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000; base 219 drivers/nvmem/imx-ocotp.c writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); base 240 drivers/nvmem/imx-ocotp.c writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); base 277 drivers/nvmem/imx-ocotp.c ret = imx_ocotp_wait_for_busy(priv->base, 0); base 308 drivers/nvmem/imx-ocotp.c ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL); base 313 drivers/nvmem/imx-ocotp.c writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL); base 341 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); base 342 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); base 343 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); base 344 drivers/nvmem/imx-ocotp.c writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); base 347 drivers/nvmem/imx-ocotp.c writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1); base 348 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); base 349 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); base 350 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); base 353 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); base 354 drivers/nvmem/imx-ocotp.c writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2); base 355 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); base 356 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); base 359 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); base 360 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); base 361 drivers/nvmem/imx-ocotp.c writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3); base 362 drivers/nvmem/imx-ocotp.c writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); base 367 drivers/nvmem/imx-ocotp.c writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); base 377 drivers/nvmem/imx-ocotp.c ret = imx_ocotp_wait_for_busy(priv->base, 0); base 381 drivers/nvmem/imx-ocotp.c imx_ocotp_clr_err_if_set(priv->base); base 398 drivers/nvmem/imx-ocotp.c priv->base + IMX_OCOTP_ADDR_CTRL_SET); base 399 drivers/nvmem/imx-ocotp.c ret = imx_ocotp_wait_for_busy(priv->base, base 516 drivers/nvmem/imx-ocotp.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 517 drivers/nvmem/imx-ocotp.c if (IS_ERR(priv->base)) base 518 drivers/nvmem/imx-ocotp.c return PTR_ERR(priv->base); base 525 drivers/nvmem/imx-ocotp.c imx_ocotp_clr_err_if_set(priv->base); base 38 drivers/nvmem/lpc18xx_otp.c void __iomem *base; base 54 drivers/nvmem/lpc18xx_otp.c *buf++ = readl(otp->base + i * LPC18XX_OTP_WORD_SIZE); base 78 drivers/nvmem/lpc18xx_otp.c otp->base = devm_ioremap_resource(&pdev->dev, res); base 79 drivers/nvmem/lpc18xx_otp.c if (IS_ERR(otp->base)) base 80 drivers/nvmem/lpc18xx_otp.c return PTR_ERR(otp->base); base 45 drivers/nvmem/meson-mx-efuse.c void __iomem *base; base 56 drivers/nvmem/meson-mx-efuse.c data = readl(efuse->base + reg); base 60 drivers/nvmem/meson-mx-efuse.c writel(data, efuse->base + reg); base 119 drivers/nvmem/meson-mx-efuse.c readl(efuse->base + MESON_MX_EFUSE_CNTL1); base 121 drivers/nvmem/meson-mx-efuse.c err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1, base 131 drivers/nvmem/meson-mx-efuse.c *value = readl(efuse->base + MESON_MX_EFUSE_CNTL2); base 208 drivers/nvmem/meson-mx-efuse.c efuse->base = devm_ioremap_resource(&pdev->dev, res); base 209 drivers/nvmem/meson-mx-efuse.c if (IS_ERR(efuse->base)) base 210 drivers/nvmem/meson-mx-efuse.c return PTR_ERR(efuse->base); base 15 drivers/nvmem/mtk-efuse.c void __iomem *base; base 26 drivers/nvmem/mtk-efuse.c *val++ = readl(priv->base + reg + (i++ * 4)); base 39 drivers/nvmem/mtk-efuse.c writel(*val++, priv->base + reg + (i++ * 4)); base 57 drivers/nvmem/mtk-efuse.c priv->base = devm_ioremap_resource(dev, res); base 58 drivers/nvmem/mtk-efuse.c if (IS_ERR(priv->base)) base 59 drivers/nvmem/mtk-efuse.c return PTR_ERR(priv->base); base 32 drivers/nvmem/mxs-ocotp.c void __iomem *base; base 42 drivers/nvmem/mxs-ocotp.c status = readl(otp->base); base 69 drivers/nvmem/mxs-ocotp.c writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR); base 76 drivers/nvmem/mxs-ocotp.c writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET); base 90 drivers/nvmem/mxs-ocotp.c *buf++ = readl(otp->base + offset); base 99 drivers/nvmem/mxs-ocotp.c writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_CLR); base 149 drivers/nvmem/mxs-ocotp.c otp->base = devm_platform_ioremap_resource(pdev, 0); base 150 drivers/nvmem/mxs-ocotp.c if (IS_ERR(otp->base)) base 151 drivers/nvmem/mxs-ocotp.c return PTR_ERR(otp->base); base 14 drivers/nvmem/qfprom.c void __iomem *base; base 25 drivers/nvmem/qfprom.c *val++ = readb(priv->base + reg + i++); base 49 drivers/nvmem/qfprom.c priv->base = devm_ioremap_resource(dev, res); base 50 drivers/nvmem/qfprom.c if (IS_ERR(priv->base)) base 51 drivers/nvmem/qfprom.c return PTR_ERR(priv->base); base 51 drivers/nvmem/rockchip-efuse.c void __iomem *base; base 68 drivers/nvmem/rockchip-efuse.c writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); base 71 drivers/nvmem/rockchip-efuse.c writel(readl(efuse->base + REG_EFUSE_CTRL) & base 73 drivers/nvmem/rockchip-efuse.c efuse->base + REG_EFUSE_CTRL); base 74 drivers/nvmem/rockchip-efuse.c writel(readl(efuse->base + REG_EFUSE_CTRL) | base 76 drivers/nvmem/rockchip-efuse.c efuse->base + REG_EFUSE_CTRL); base 78 drivers/nvmem/rockchip-efuse.c writel(readl(efuse->base + REG_EFUSE_CTRL) | base 79 drivers/nvmem/rockchip-efuse.c RK3288_STROBE, efuse->base + REG_EFUSE_CTRL); base 81 drivers/nvmem/rockchip-efuse.c *buf++ = readb(efuse->base + REG_EFUSE_DOUT); base 82 drivers/nvmem/rockchip-efuse.c writel(readl(efuse->base + REG_EFUSE_CTRL) & base 83 drivers/nvmem/rockchip-efuse.c (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL); base 88 drivers/nvmem/rockchip-efuse.c writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL); base 127 drivers/nvmem/rockchip-efuse.c efuse->base + RK3328_AUTO_CTRL); base 129 drivers/nvmem/rockchip-efuse.c status = readl(efuse->base + RK3328_INT_STATUS); base 134 drivers/nvmem/rockchip-efuse.c out_value = readl(efuse->base + RK3328_DOUT); base 135 drivers/nvmem/rockchip-efuse.c writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS); base 178 drivers/nvmem/rockchip-efuse.c efuse->base + REG_EFUSE_CTRL); base 181 drivers/nvmem/rockchip-efuse.c writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE | base 183 drivers/nvmem/rockchip-efuse.c efuse->base + REG_EFUSE_CTRL); base 185 drivers/nvmem/rockchip-efuse.c out_value = readl(efuse->base + REG_EFUSE_DOUT); base 186 drivers/nvmem/rockchip-efuse.c writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE), base 187 drivers/nvmem/rockchip-efuse.c efuse->base + REG_EFUSE_CTRL); base 195 drivers/nvmem/rockchip-efuse.c writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL); base 271 drivers/nvmem/rockchip-efuse.c efuse->base = devm_ioremap_resource(dev, res); base 272 drivers/nvmem/rockchip-efuse.c if (IS_ERR(efuse->base)) base 273 drivers/nvmem/rockchip-efuse.c return PTR_ERR(efuse->base); base 57 drivers/nvmem/sc27xx-efuse.c u32 base; base 94 drivers/nvmem/sc27xx-efuse.c efuse->base + SC27XX_EFUSE_STATUS, base 137 drivers/nvmem/sc27xx-efuse.c efuse->base + SC27XX_EFUSE_BLOCK_INDEX, base 144 drivers/nvmem/sc27xx-efuse.c efuse->base + SC27XX_EFUSE_MODE_CTRL, base 159 drivers/nvmem/sc27xx-efuse.c ret = regmap_read(efuse->regmap, efuse->base + SC27XX_EFUSE_DATA_RD, base 166 drivers/nvmem/sc27xx-efuse.c efuse->base + SC27XX_EFUSE_MODE_CTRL, base 202 drivers/nvmem/sc27xx-efuse.c ret = of_property_read_u32(np, "reg", &efuse->base); base 33 drivers/nvmem/stm32-romem.c void __iomem *base; base 45 drivers/nvmem/stm32-romem.c *buf8++ = readb_relaxed(priv->base + i); base 91 drivers/nvmem/stm32-romem.c priv->base + STM32MP15_BSEC_DATA0 + i); base 151 drivers/nvmem/stm32-romem.c priv->base = devm_ioremap_resource(dev, res); base 152 drivers/nvmem/stm32-romem.c if (IS_ERR(priv->base)) base 153 drivers/nvmem/stm32-romem.c return PTR_ERR(priv->base); base 36 drivers/nvmem/sunxi_sid.c void __iomem *base; base 45 drivers/nvmem/sunxi_sid.c memcpy_fromio(val, sid->base + sid->value_offset + offset, bytes); base 61 drivers/nvmem/sunxi_sid.c writel(reg_val, sid->base + SUN8I_SID_PRCTL); base 63 drivers/nvmem/sunxi_sid.c ret = readl_poll_timeout(sid->base + SUN8I_SID_PRCTL, reg_val, base 69 drivers/nvmem/sunxi_sid.c *out = readl(sid->base + SUN8I_SID_RDKEY); base 71 drivers/nvmem/sunxi_sid.c writel(0, sid->base + SUN8I_SID_PRCTL); base 133 drivers/nvmem/sunxi_sid.c sid->base = devm_ioremap_resource(dev, res); base 134 drivers/nvmem/sunxi_sid.c if (IS_ERR(sid->base)) base 135 drivers/nvmem/sunxi_sid.c return PTR_ERR(sid->base); base 16 drivers/nvmem/uniphier-efuse.c void __iomem *base; base 27 drivers/nvmem/uniphier-efuse.c *val++ = readb(priv->base + reg + offs); base 45 drivers/nvmem/uniphier-efuse.c priv->base = devm_ioremap_resource(dev, res); base 46 drivers/nvmem/uniphier-efuse.c if (IS_ERR(priv->base)) base 47 drivers/nvmem/uniphier-efuse.c return PTR_ERR(priv->base); base 90 drivers/nvmem/vf610-ocotp.c void __iomem *base; base 97 drivers/nvmem/vf610-ocotp.c static int vf610_ocotp_wait_busy(void __iomem *base) base 101 drivers/nvmem/vf610-ocotp.c while ((readl(base) & OCOTP_CTRL_BUSY) && --timeout) base 105 drivers/nvmem/vf610-ocotp.c writel(OCOTP_CTRL_ERR, base + OCOTP_CTRL_CLR); base 150 drivers/nvmem/vf610-ocotp.c void __iomem *base = ocotp->base; base 158 drivers/nvmem/vf610-ocotp.c writel(ocotp->timing, base + OCOTP_TIMING); base 159 drivers/nvmem/vf610-ocotp.c ret = vf610_ocotp_wait_busy(base + OCOTP_CTRL_REG); base 163 drivers/nvmem/vf610-ocotp.c reg = readl(base + OCOTP_CTRL_REG); base 167 drivers/nvmem/vf610-ocotp.c writel(reg, base + OCOTP_CTRL_REG); base 170 drivers/nvmem/vf610-ocotp.c base + OCOTP_READ_CTRL_REG); base 171 drivers/nvmem/vf610-ocotp.c ret = vf610_ocotp_wait_busy(base + OCOTP_CTRL_REG); base 175 drivers/nvmem/vf610-ocotp.c if (readl(base) & OCOTP_CTRL_ERR) { base 178 drivers/nvmem/vf610-ocotp.c writel(OCOTP_CTRL_ERR, base + OCOTP_CTRL_CLR); base 186 drivers/nvmem/vf610-ocotp.c *buf = readl(base + OCOTP_READ_FUSE_DATA); base 223 drivers/nvmem/vf610-ocotp.c ocotp_dev->base = devm_ioremap_resource(dev, res); base 224 drivers/nvmem/vf610-ocotp.c if (IS_ERR(ocotp_dev->base)) base 225 drivers/nvmem/vf610-ocotp.c return PTR_ERR(ocotp_dev->base); base 296 drivers/of/fdt.c void *base = mem; base 297 drivers/of/fdt.c bool dryrun = !base; base 327 drivers/of/fdt.c return mem - base; base 347 drivers/of/fdt.c return mem - base; base 480 drivers/of/fdt.c phys_addr_t base, size; base 499 drivers/of/fdt.c base = dt_mem_next_cell(dt_root_addr_cells, &prop); base 503 drivers/of/fdt.c early_init_dt_reserve_memory_arch(base, size, nomap) == 0) base 505 drivers/of/fdt.c uname, &base, (unsigned long)size / SZ_1M); base 508 drivers/of/fdt.c uname, &base, (unsigned long)size / SZ_1M); base 512 drivers/of/fdt.c fdt_reserved_mem_save_node(node, uname, base, size); base 589 drivers/of/fdt.c u64 base, size; base 596 drivers/of/fdt.c fdt_get_mem_rsv(initial_boot_params, n, &base, &size); base 599 drivers/of/fdt.c early_init_dt_reserve_memory_arch(base, size, false); base 1020 drivers/of/fdt.c u64 base, size; base 1022 drivers/of/fdt.c base = dt_mem_next_cell(dt_root_addr_cells, ®); base 1027 drivers/of/fdt.c pr_debug(" - %llx , %llx\n", (unsigned long long)base, base 1030 drivers/of/fdt.c early_init_dt_add_memory_arch(base, size); base 1035 drivers/of/fdt.c if (early_init_dt_mark_hotplug_memory_arch(base, size)) base 1037 drivers/of/fdt.c base, base + size); base 1106 drivers/of/fdt.c void __init __weak early_init_dt_add_memory_arch(u64 base, u64 size) base 1110 drivers/of/fdt.c if (size < PAGE_SIZE - (base & ~PAGE_MASK)) { base 1112 drivers/of/fdt.c base, base + size); base 1116 drivers/of/fdt.c if (!PAGE_ALIGNED(base)) { base 1117 drivers/of/fdt.c size -= PAGE_SIZE - (base & ~PAGE_MASK); base 1118 drivers/of/fdt.c base = PAGE_ALIGN(base); base 1122 drivers/of/fdt.c if (base > MAX_MEMBLOCK_ADDR) { base 1124 drivers/of/fdt.c base, base + size); base 1128 drivers/of/fdt.c if (base + size - 1 > MAX_MEMBLOCK_ADDR) { base 1130 drivers/of/fdt.c ((u64)MAX_MEMBLOCK_ADDR) + 1, base + size); base 1131 drivers/of/fdt.c size = MAX_MEMBLOCK_ADDR - base + 1; base 1134 drivers/of/fdt.c if (base + size < phys_offset) { base 1136 drivers/of/fdt.c base, base + size); base 1139 drivers/of/fdt.c if (base < phys_offset) { base 1141 drivers/of/fdt.c base, phys_offset); base 1142 drivers/of/fdt.c size -= phys_offset - base; base 1143 drivers/of/fdt.c base = phys_offset; base 1145 drivers/of/fdt.c memblock_add(base, size); base 1148 drivers/of/fdt.c int __init __weak early_init_dt_mark_hotplug_memory_arch(u64 base, u64 size) base 1150 drivers/of/fdt.c return memblock_mark_hotplug(base, size); base 1153 drivers/of/fdt.c int __init __weak early_init_dt_reserve_memory_arch(phys_addr_t base, base 1157 drivers/of/fdt.c return memblock_remove(base, size); base 1158 drivers/of/fdt.c return memblock_reserve(base, size); base 33 drivers/of/of_reserved_mem.c phys_addr_t base; base 37 drivers/of/of_reserved_mem.c base = memblock_find_in_range(start, end, size, align); base 38 drivers/of/of_reserved_mem.c if (!base) base 41 drivers/of/of_reserved_mem.c *res_base = base; base 43 drivers/of/of_reserved_mem.c return memblock_remove(base, size); base 45 drivers/of/of_reserved_mem.c return memblock_reserve(base, size); base 52 drivers/of/of_reserved_mem.c phys_addr_t base, phys_addr_t size) base 63 drivers/of/of_reserved_mem.c rmem->base = base; base 79 drivers/of/of_reserved_mem.c phys_addr_t base = 0, align = 0, size; base 127 drivers/of/of_reserved_mem.c base = 0; base 135 drivers/of/of_reserved_mem.c align, start, end, nomap, &base); base 138 drivers/of/of_reserved_mem.c uname, &base, base 147 drivers/of/of_reserved_mem.c 0, 0, nomap, &base); base 150 drivers/of/of_reserved_mem.c uname, &base, (unsigned long)size / SZ_1M); base 153 drivers/of/of_reserved_mem.c if (base == 0) { base 158 drivers/of/of_reserved_mem.c *res_base = base; base 197 drivers/of/of_reserved_mem.c if (ra->base < rb->base) base 200 drivers/of/of_reserved_mem.c if (ra->base > rb->base) base 220 drivers/of/of_reserved_mem.c if (!(this->base && next->base)) base 222 drivers/of/of_reserved_mem.c if (this->base + this->size > next->base) { base 225 drivers/of/of_reserved_mem.c this_end = this->base + this->size; base 226 drivers/of/of_reserved_mem.c next_end = next->base + next->size; base 228 drivers/of/of_reserved_mem.c this->name, &this->base, &this_end, base 229 drivers/of/of_reserved_mem.c next->name, &next->base, &next_end); base 261 drivers/of/of_reserved_mem.c &rmem->base, &rmem->size); base 267 drivers/of/of_reserved_mem.c memblock_free(rmem->base, rmem->size); base 269 drivers/of/of_reserved_mem.c memblock_add(rmem->base, rmem->size); base 1384 drivers/of/unittest.c const char *base; base 1389 drivers/of/unittest.c base = "/testcase-data/overlay-node/test-bus"; base 1392 drivers/of/unittest.c base = "/testcase-data/overlay-node/test-bus/i2c-test-bus"; base 1398 drivers/of/unittest.c snprintf(buf, sizeof(buf) - 1, "%s/test-unittest%d", base, nr); base 76 drivers/opp/ti-opp-supply.c void __iomem *base; base 93 drivers/opp/ti-opp-supply.c base = ioremap_nocache(res->start, resource_size(res)); base 94 drivers/opp/ti-opp-supply.c if (!base) { base 141 drivers/opp/ti-opp-supply.c tmp = readl(base + efuse_offset); base 164 drivers/opp/ti-opp-supply.c iounmap(base); base 283 drivers/parisc/lba_pci.c #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \ base 289 drivers/parisc/lba_pci.c WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \ base 290 drivers/parisc/lba_pci.c error_status = READ_REG32(base + LBA_ERROR_STATUS); \ base 301 drivers/parisc/lba_pci.c WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \ base 319 drivers/parisc/lba_pci.c #define LBA_CFG_RESTORE(d, base) { \ base 323 drivers/parisc/lba_pci.c WRITE_REG32(status_control, base + LBA_STAT_CTL); \ base 327 drivers/parisc/lba_pci.c WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \ base 331 drivers/parisc/lba_pci.c WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \ base 2026 drivers/parisc/sba_iommu.c int base, size; base 2029 drivers/parisc/sba_iommu.c base = READ_REG32(reg + LMMIO_DIRECT0_BASE); base 2030 drivers/parisc/sba_iommu.c if ((base & 1) == 0) base 2038 drivers/parisc/sba_iommu.c r->start = (base & ~1UL) | PCI_F_EXTEND; base 2060 drivers/parisc/sba_iommu.c int base, size; base 2067 drivers/parisc/sba_iommu.c base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE); base 2068 drivers/parisc/sba_iommu.c if ((base & 1) == 0) { base 2073 drivers/parisc/sba_iommu.c r->start = (base & ~1UL) | PCI_F_EXTEND; base 50 drivers/parisc/wax.c unsigned long base = wax->hpa; base 53 drivers/parisc/wax.c gsc_writel(0x00000000, base+OFFSET_IMR); base 56 drivers/parisc/wax.c gsc_readl(base+OFFSET_IRR); base 76 drivers/parport/daisy.c struct parport *extra = parport_register_port(real->base, base 40 drivers/parport/parport_ax88796.c void __iomem *base; base 300 drivers/parport/parport_ax88796.c dd->base = ioremap(res->start, size); base 301 drivers/parport/parport_ax88796.c if (dd->base == NULL) { base 311 drivers/parport/parport_ax88796.c pp = parport_register_port((unsigned long)dd->base, irq, base 325 drivers/parport/parport_ax88796.c dd->spp_data = dd->base; base 326 drivers/parport/parport_ax88796.c dd->spp_spr = dd->base + (spacing * 1); base 327 drivers/parport/parport_ax88796.c dd->spp_cpr = dd->base + (spacing * 2); base 353 drivers/parport/parport_ax88796.c iounmap(dd->base); base 368 drivers/parport/parport_ax88796.c iounmap(dd->base); base 230 drivers/parport/parport_gsc.c struct parport *parport_gsc_probe_port(unsigned long base, base 241 drivers/parport/parport_gsc.c printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base); base 248 drivers/parport/parport_gsc.c base); base 256 drivers/parport/parport_gsc.c p->base = base; base 272 drivers/parport/parport_gsc.c if (!(p = parport_register_port(base, PARPORT_IRQ_NONE, base 285 drivers/parport/parport_gsc.c printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); base 45 drivers/parport/parport_gsc.h #define EPPDATA(p) ((p)->base + 0x4) base 46 drivers/parport/parport_gsc.h #define EPPADDR(p) ((p)->base + 0x3) base 47 drivers/parport/parport_gsc.h #define CONTROL(p) ((p)->base + 0x2) base 48 drivers/parport/parport_gsc.h #define STATUS(p) ((p)->base + 0x1) base 49 drivers/parport/parport_gsc.h #define DATA(p) ((p)->base + 0x0) base 203 drivers/parport/parport_gsc.h extern struct parport *parport_gsc_probe_port(unsigned long base, base 304 drivers/parport/parport_ip32.c __pr_probe(KERN_INFO PPIP32 "0x%lx: " fmt, (p)->base , ##__VA_ARGS__) base 1993 drivers/parport/parport_ip32.c void __iomem *base, void __iomem *base_hi, base 1996 drivers/parport/parport_ip32.c #define r_base(offset) ((u8 __iomem *)base + ((offset) << regshift)) base 2041 drivers/parport/parport_ip32.c p->base = MACE_BASE + offsetof(struct sgi_mace, isa.parallel); base 2138 drivers/parport/parport_ip32.c p->name, p->base, p->base_hi); base 82 drivers/parport/parport_mfc3.c #define pia(dev) ((struct pia *)(dev->base)) base 1381 drivers/parport/parport_pc.c if (superios[i].io == p->base) base 1449 drivers/parport/parport_pc.c "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); base 1468 drivers/parport/parport_pc.c "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); base 1471 drivers/parport/parport_pc.c pb->base); base 1608 drivers/parport/parport_pc.c printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); base 1623 drivers/parport/parport_pc.c pb->base, i); base 1646 drivers/parport/parport_pc.c pb->base, i); base 1661 drivers/parport/parport_pc.c pb->base); base 1666 drivers/parport/parport_pc.c pb->base); base 1670 drivers/parport/parport_pc.c pb->base); base 1679 drivers/parport/parport_pc.c pb->base, 8 * pword); base 1681 drivers/parport/parport_pc.c printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base, base 1686 drivers/parport/parport_pc.c pb->base, config, configb); base 1687 drivers/parport/parport_pc.c printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); base 2024 drivers/parport/parport_pc.c struct parport *parport_pc_probe_port(unsigned long int base, base 2044 drivers/parport/parport_pc.c base, NULL, 0); base 2065 drivers/parport/parport_pc.c p = parport_register_port(base, irq, dma, ops); base 2069 drivers/parport/parport_pc.c base_res = request_region(base, 3, p->name); base 2094 drivers/parport/parport_pc.c if (base != 0x3bc) { base 2095 drivers/parport/parport_pc.c EPP_res = request_region(base+0x3, 5, p->name); base 2110 drivers/parport/parport_pc.c printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); base 2190 drivers/parport/parport_pc.c release_region(base+3, 5); base 2256 drivers/parport/parport_pc.c release_region(base+0x3, 5); base 2257 drivers/parport/parport_pc.c release_region(base, 3); base 2286 drivers/parport/parport_pc.c release_region(p->base, 3); base 2288 drivers/parport/parport_pc.c release_region(p->base + 3, p->size - 3); base 53 drivers/parport/parport_sunbpp.c struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; base 63 drivers/parport/parport_sunbpp.c struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; base 73 drivers/parport/parport_sunbpp.c struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; base 81 drivers/parport/parport_sunbpp.c struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; base 88 drivers/parport/parport_sunbpp.c struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; base 111 drivers/parport/parport_sunbpp.c struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; base 139 drivers/parport/parport_sunbpp.c struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; base 198 drivers/parport/parport_sunbpp.c struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; base 208 drivers/parport/parport_sunbpp.c struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; base 275 drivers/parport/parport_sunbpp.c void __iomem *base; base 279 drivers/parport/parport_sunbpp.c base = of_ioremap(&op->resource[0], 0, base 282 drivers/parport/parport_sunbpp.c if (!base) base 296 drivers/parport/parport_sunbpp.c if (!(p = parport_register_port((unsigned long)base, irq, dma, ops))) { base 311 drivers/parport/parport_sunbpp.c regs = (struct bpp_regs __iomem *)p->base; base 317 drivers/parport/parport_sunbpp.c printk(KERN_INFO "%s: sunbpp at 0x%lx\n", p->name, p->base); base 332 drivers/parport/parport_sunbpp.c of_iounmap(&op->resource[0], base, size); base 349 drivers/parport/parport_sunbpp.c of_iounmap(&op->resource[0], (void __iomem *) p->base, p->size); base 131 drivers/parport/procfs.c len += sprintf (buffer, "%lu\t%lu\n", port->base, port->base_hi); base 457 drivers/parport/share.c struct parport *parport_register_port(unsigned long base, int irq, int dma, base 472 drivers/parport/share.c tmp->base = base; base 1103 drivers/parport/share.c struct parport *parport_find_base(unsigned long base) base 1112 drivers/parport/share.c if (port->base == base) { base 91 drivers/pci/controller/dwc/pci-dra7xx.c void __iomem *base; /* DT ti_conf */ base 108 drivers/pci/controller/dwc/pci-dra7xx.c return readl(pcie->base + offset); base 114 drivers/pci/controller/dwc/pci-dra7xx.c writel(value, pcie->base + offset); base 683 drivers/pci/controller/dwc/pci-dra7xx.c void __iomem *base; base 722 drivers/pci/controller/dwc/pci-dra7xx.c base = devm_ioremap_nocache(dev, res->start, resource_size(res)); base 723 drivers/pci/controller/dwc/pci-dra7xx.c if (!base) base 753 drivers/pci/controller/dwc/pci-dra7xx.c dra7xx->base = base; base 164 drivers/pci/controller/dwc/pci-exynos.c static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) base 166 drivers/pci/controller/dwc/pci-exynos.c writel(val, base + reg); base 169 drivers/pci/controller/dwc/pci-exynos.c static u32 exynos_pcie_readl(void __iomem *base, u32 reg) base 171 drivers/pci/controller/dwc/pci-exynos.c return readl(base + reg); base 319 drivers/pci/controller/dwc/pci-exynos.c static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, base 326 drivers/pci/controller/dwc/pci-exynos.c dw_pcie_read(base + reg, size, &val); base 331 drivers/pci/controller/dwc/pci-exynos.c static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, base 337 drivers/pci/controller/dwc/pci-exynos.c dw_pcie_write(base + reg, size, val); base 889 drivers/pci/controller/dwc/pci-keystone.c static u32 ks_pcie_am654_read_dbi2(struct dw_pcie *pci, void __iomem *base, base 896 drivers/pci/controller/dwc/pci-keystone.c dw_pcie_read(base + reg, size, &val); base 901 drivers/pci/controller/dwc/pci-keystone.c static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, base 907 drivers/pci/controller/dwc/pci-keystone.c dw_pcie_write(base + reg, size, val); base 1200 drivers/pci/controller/dwc/pci-keystone.c void __iomem *base; base 1236 drivers/pci/controller/dwc/pci-keystone.c base = devm_pci_remap_cfg_resource(dev, res); base 1237 drivers/pci/controller/dwc/pci-keystone.c if (IS_ERR(base)) base 1238 drivers/pci/controller/dwc/pci-keystone.c return PTR_ERR(base); base 1243 drivers/pci/controller/dwc/pci-keystone.c pci->dbi_base = base; base 1244 drivers/pci/controller/dwc/pci-keystone.c pci->dbi_base2 = base; base 281 drivers/pci/controller/dwc/pcie-armada8k.c struct resource *base; base 317 drivers/pci/controller/dwc/pcie-armada8k.c base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); base 318 drivers/pci/controller/dwc/pcie-armada8k.c pci->dbi_base = devm_pci_remap_cfg_resource(dev, base); base 320 drivers/pci/controller/dwc/pcie-armada8k.c dev_err(dev, "couldn't remap regs base %p\n", base); base 231 drivers/pci/controller/dwc/pcie-designware.h u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, base 233 drivers/pci/controller/dwc/pcie-designware.h void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, base 235 drivers/pci/controller/dwc/pcie-designware.h u32 (*read_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, base 237 drivers/pci/controller/dwc/pcie-designware.h void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, base 105 drivers/pci/controller/dwc/pcie-histb.c static u32 histb_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, base 111 drivers/pci/controller/dwc/pcie-histb.c dw_pcie_read(base + reg, size, &val); base 117 drivers/pci/controller/dwc/pcie-histb.c static void histb_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, base 121 drivers/pci/controller/dwc/pcie-histb.c dw_pcie_write(base + reg, size, val); base 366 drivers/pci/controller/dwc/pcie-kirin.c static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, base 373 drivers/pci/controller/dwc/pcie-kirin.c dw_pcie_read(base + reg, size, &ret); base 379 drivers/pci/controller/dwc/pcie-kirin.c static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, base 385 drivers/pci/controller/dwc/pcie-kirin.c dw_pcie_write(base + reg, size, val); base 61 drivers/pci/controller/dwc/pcie-uniphier.c void __iomem *base; base 76 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_APP_READY_CTRL); base 81 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_APP_READY_CTRL); base 89 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_APP_PM0); base 91 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_APP_PM0); base 94 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_PINCTRL0); base 99 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_PINCTRL0); base 106 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_PINCTRL0); base 108 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_PINCTRL0); base 117 drivers/pci/controller/dwc/pcie-uniphier.c ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status, base 133 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_STATUS_LINK); base 160 drivers/pci/controller/dwc/pcie-uniphier.c writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT); base 161 drivers/pci/controller/dwc/pcie-uniphier.c writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX); base 166 drivers/pci/controller/dwc/pcie-uniphier.c writel(0, priv->base + PCL_RCV_INT); base 167 drivers/pci/controller/dwc/pcie-uniphier.c writel(0, priv->base + PCL_RCV_INTX); base 177 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_RCV_INTX); base 180 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_RCV_INTX); base 190 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_RCV_INTX); base 193 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_RCV_INTX); base 203 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_RCV_INTX); base 206 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_RCV_INTX); base 240 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_RCV_INT); base 251 drivers/pci/controller/dwc/pcie-uniphier.c writel(val, priv->base + PCL_RCV_INT); base 256 drivers/pci/controller/dwc/pcie-uniphier.c val = readl(priv->base + PCL_RCV_INTX); base 424 drivers/pci/controller/dwc/pcie-uniphier.c priv->base = devm_ioremap_resource(dev, res); base 425 drivers/pci/controller/dwc/pcie-uniphier.c if (IS_ERR(priv->base)) base 426 drivers/pci/controller/dwc/pcie-uniphier.c return PTR_ERR(priv->base); base 190 drivers/pci/controller/pci-aardvark.c void __iomem *base; base 208 drivers/pci/controller/pci-aardvark.c writel(val, pcie->base + reg); base 213 drivers/pci/controller/pci-aardvark.c return readl(pcie->base + reg); base 1013 drivers/pci/controller/pci-aardvark.c pcie->base = devm_ioremap_resource(dev, res); base 1014 drivers/pci/controller/pci-aardvark.c if (IS_ERR(pcie->base)) base 1015 drivers/pci/controller/pci-aardvark.c return PTR_ERR(pcie->base); base 124 drivers/pci/controller/pci-ftpci100.c void __iomem *base; base 198 drivers/pci/controller/pci-ftpci100.c p->base + PCI_CONFIG); base 200 drivers/pci/controller/pci-ftpci100.c *value = readl(p->base + PCI_DATA); base 233 drivers/pci/controller/pci-ftpci100.c p->base + PCI_CONFIG); base 237 drivers/pci/controller/pci-ftpci100.c writel(value, p->base + PCI_DATA); base 240 drivers/pci/controller/pci-ftpci100.c writew(value, p->base + PCI_DATA + (config & 3)); base 243 drivers/pci/controller/pci-ftpci100.c writeb(value, p->base + PCI_DATA + (config & 3)); base 479 drivers/pci/controller/pci-ftpci100.c p->base = devm_ioremap_resource(dev, regs); base 480 drivers/pci/controller/pci-ftpci100.c if (IS_ERR(p->base)) base 481 drivers/pci/controller/pci-ftpci100.c return PTR_ERR(p->base); base 501 drivers/pci/controller/pci-ftpci100.c writel(val, p->base + PCI_IOSIZE); base 525 drivers/pci/controller/pci-ftpci100.c val = readl(p->base + PCI_CTRL); base 529 drivers/pci/controller/pci-ftpci100.c writel(val, p->base + PCI_CTRL); base 83 drivers/pci/controller/pci-mvebu.c phys_addr_t base; base 91 drivers/pci/controller/pci-mvebu.c void __iomem *base; base 112 drivers/pci/controller/pci-mvebu.c writel(val, port->base + reg); base 117 drivers/pci/controller/pci-mvebu.c return readl(port->base + reg); base 185 drivers/pci/controller/pci-mvebu.c mvebu_writel(port, cs->base & 0xffff0000, base 202 drivers/pci/controller/pci-mvebu.c mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); base 232 drivers/pci/controller/pci-mvebu.c void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; base 256 drivers/pci/controller/pci-mvebu.c void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; base 283 drivers/pci/controller/pci-mvebu.c phys_addr_t base, size_t size) base 288 drivers/pci/controller/pci-mvebu.c mvebu_mbus_del_window(base, sz); base 289 drivers/pci/controller/pci-mvebu.c base += sz; base 302 drivers/pci/controller/pci-mvebu.c phys_addr_t base, size_t size, base 311 drivers/pci/controller/pci-mvebu.c ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base, base 314 drivers/pci/controller/pci-mvebu.c phys_addr_t end = base + sz - 1; base 318 drivers/pci/controller/pci-mvebu.c &base, &end, ret); base 319 drivers/pci/controller/pci-mvebu.c mvebu_pcie_del_windows(port, base - size_mapped, base 326 drivers/pci/controller/pci-mvebu.c base += sz; base 337 drivers/pci/controller/pci-mvebu.c if (desired->base == cur->base && desired->remap == cur->remap && base 342 drivers/pci/controller/pci-mvebu.c mvebu_pcie_del_windows(port, cur->base, cur->size); base 344 drivers/pci/controller/pci-mvebu.c cur->base = 0; base 356 drivers/pci/controller/pci-mvebu.c mvebu_pcie_add_windows(port, target, attribute, desired->base, base 390 drivers/pci/controller/pci-mvebu.c desired.base = port->pcie->io.start + desired.remap; base 419 drivers/pci/controller/pci-mvebu.c desired.base = ((conf->membase & 0xFFF0) << 16); base 421 drivers/pci/controller/pci-mvebu.c desired.base + 1; base 1106 drivers/pci/controller/pci-mvebu.c port->base = mvebu_pcie_map_registers(pdev, child, port); base 1107 drivers/pci/controller/pci-mvebu.c if (IS_ERR(port->base)) { base 1109 drivers/pci/controller/pci-mvebu.c port->base = NULL; base 398 drivers/pci/controller/pci-tegra.c void __iomem *base; base 475 drivers/pci/controller/pci-tegra.c addr = port->base + (where & ~3); base 481 drivers/pci/controller/pci-tegra.c u32 base; base 486 drivers/pci/controller/pci-tegra.c base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8); base 487 drivers/pci/controller/pci-tegra.c afi_writel(pcie, base, AFI_FPCI_BAR0); base 575 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_VEND_CTL1); base 577 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_VEND_CTL1); base 580 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_VEND_XP); base 583 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_VEND_XP); base 589 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_VEND_XP_BIST); base 591 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_VEND_XP_BIST); base 593 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_PRIV_MISC); base 604 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_PRIV_MISC); base 612 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_ECTL_2_R1); base 615 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_ECTL_2_R1); base 617 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_ECTL_4_R1); base 621 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_ECTL_4_R1); base 623 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_ECTL_5_R1); base 626 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_ECTL_5_R1); base 628 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_ECTL_6_R1); base 631 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_ECTL_6_R1); base 633 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_ECTL_2_R2); base 636 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_ECTL_2_R2); base 638 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_ECTL_4_R2); base 642 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_ECTL_4_R2); base 644 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_ECTL_5_R2); base 647 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_ECTL_5_R2); base 649 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_ECTL_6_R2); base 652 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_ECTL_6_R2); base 666 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_VEND_CTL0); base 669 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_VEND_CTL0); base 674 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_RX_HDR_LIMIT); base 677 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_RX_HDR_LIMIT); base 679 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_PRIV_XP_DL); base 681 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_PRIV_XP_DL); base 683 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_VEND_XP); base 686 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_VEND_XP); base 690 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_VEND_XP); base 693 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_VEND_XP); base 702 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_LINK_CONTROL_STATUS_2); base 705 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_LINK_CONTROL_STATUS_2); base 728 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_VEND_CTL2); base 730 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_VEND_CTL2); base 773 drivers/pci/controller/pci-tegra.c devm_iounmap(dev, port->base); base 2294 drivers/pci/controller/pci-tegra.c rp->base = devm_pci_remap_cfg_resource(dev, &rp->regs); base 2295 drivers/pci/controller/pci-tegra.c if (IS_ERR(rp->base)) base 2296 drivers/pci/controller/pci-tegra.c return PTR_ERR(rp->base); base 2356 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_PRIV_MISC); base 2359 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_PRIV_MISC); base 2365 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_VEND_XP); base 2381 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_LINK_CONTROL_STATUS); base 2410 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_LINK_CONTROL_STATUS_2); base 2413 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_LINK_CONTROL_STATUS_2); base 2422 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_LINK_CONTROL_STATUS); base 2434 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_LINK_CONTROL_STATUS); base 2436 drivers/pci/controller/pci-tegra.c writel(value, port->base + RP_LINK_CONTROL_STATUS); base 2441 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_LINK_CONTROL_STATUS); base 2680 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_VEND_XP); base 2685 drivers/pci/controller/pci-tegra.c value = readl(port->base + RP_LINK_CONTROL_STATUS); base 240 drivers/pci/controller/pci-v3-semi.c void __iomem *base; base 372 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE0); base 380 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE1); base 381 drivers/pci/controller/pci-v3-semi.c writew(mapaddress, v3->base + V3_LB_MAP1); base 394 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE1); base 397 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_MAP1); base 404 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE0); base 447 drivers/pci/controller/pci-v3-semi.c status = readw(v3->base + V3_PCI_STAT); base 456 drivers/pci/controller/pci-v3-semi.c writew(status, v3->base + V3_PCI_STAT); base 458 drivers/pci/controller/pci-v3-semi.c status = readb(v3->base + V3_LB_ISTAT); base 476 drivers/pci/controller/pci-v3-semi.c writeb(0, v3->base + V3_LB_ISTAT); base 507 drivers/pci/controller/pci-v3-semi.c writel(0x6200, v3->base + V3_LB_IO_BASE); base 511 drivers/pci/controller/pci-v3-semi.c writeb(0xaa, v3->base + V3_MAIL_DATA); base 512 drivers/pci/controller/pci-v3-semi.c writeb(0x55, v3->base + V3_MAIL_DATA + 4); base 513 drivers/pci/controller/pci-v3-semi.c } while (readb(v3->base + V3_MAIL_DATA) != 0xaa && base 514 drivers/pci/controller/pci-v3-semi.c readb(v3->base + V3_MAIL_DATA) != 0x55); base 550 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE2); base 552 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_MAP2); base 577 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE1); base 580 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_MAP1); base 596 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_BASE0); base 599 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_MAP0); base 717 drivers/pci/controller/pci-v3-semi.c writel(pci_base, v3->base + V3_PCI_BASE0); base 718 drivers/pci/controller/pci-v3-semi.c writel(pci_map, v3->base + V3_PCI_MAP0); base 720 drivers/pci/controller/pci-v3-semi.c writel(pci_base, v3->base + V3_PCI_BASE1); base 721 drivers/pci/controller/pci-v3-semi.c writel(pci_map, v3->base + V3_PCI_MAP1); base 773 drivers/pci/controller/pci-v3-semi.c v3->base = devm_ioremap_resource(dev, regs); base 774 drivers/pci/controller/pci-v3-semi.c if (IS_ERR(v3->base)) base 775 drivers/pci/controller/pci-v3-semi.c return PTR_ERR(v3->base); base 781 drivers/pci/controller/pci-v3-semi.c if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16)) base 783 drivers/pci/controller/pci-v3-semi.c readl(v3->base + V3_LB_IO_BASE), regs); base 823 drivers/pci/controller/pci-v3-semi.c if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK) base 824 drivers/pci/controller/pci-v3-semi.c writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM); base 827 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CMD); base 829 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CMD); base 832 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_SYSTEM); base 834 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_SYSTEM); base 837 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CFG); base 839 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CFG); base 842 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_LB_CFG); base 847 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_LB_CFG); base 850 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CMD); base 852 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CMD); base 871 drivers/pci/controller/pci-v3-semi.c writel(0x00000000, v3->base + V3_PCI_IO_BASE); base 879 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CFG); base 890 drivers/pci/controller/pci-v3-semi.c v3->base + V3_FIFO_PRIORITY); base 897 drivers/pci/controller/pci-v3-semi.c writeb(0, v3->base + V3_LB_ISTAT); base 898 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_LB_CFG); base 900 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_LB_CFG); base 902 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_IMASK); base 912 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_PCI_CMD); base 914 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_PCI_CMD); base 917 drivers/pci/controller/pci-v3-semi.c writeb(0, v3->base + V3_LB_ISTAT); base 920 drivers/pci/controller/pci-v3-semi.c v3->base + V3_LB_IMASK); base 923 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_SYSTEM); base 925 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_SYSTEM); base 930 drivers/pci/controller/pci-v3-semi.c val = readw(v3->base + V3_SYSTEM); base 932 drivers/pci/controller/pci-v3-semi.c writew(val, v3->base + V3_SYSTEM); base 51 drivers/pci/controller/pcie-iproc-bcma.c pcie->base = bdev->io_addr; base 52 drivers/pci/controller/pcie-iproc-bcma.c if (!pcie->base) { base 134 drivers/pci/controller/pcie-iproc-msi.c return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); base 143 drivers/pci/controller/pcie-iproc-msi.c writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); base 66 drivers/pci/controller/pcie-iproc-platform.c pcie->base = devm_pci_remap_cfgspace(dev, reg.start, base 68 drivers/pci/controller/pcie-iproc-platform.c if (!pcie->base) { base 424 drivers/pci/controller/pcie-iproc.c return readl(pcie->base + offset); base 435 drivers/pci/controller/pcie-iproc.c writel(val, pcie->base + offset); base 482 drivers/pci/controller/pcie-iproc.c return (pcie->base + offset); base 649 drivers/pci/controller/pcie-iproc.c return (pcie->base + offset); base 887 drivers/pci/controller/pcie-iproc.c OARR_VALID, pcie->base + oarr_offset); base 888 drivers/pci/controller/pcie-iproc.c writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); base 891 drivers/pci/controller/pcie-iproc.c writel(lower_32_bits(pci_addr), pcie->base + omap_offset); base 892 drivers/pci/controller/pcie-iproc.c writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); base 897 drivers/pci/controller/pcie-iproc.c readl(pcie->base + oarr_offset), base 898 drivers/pci/controller/pcie-iproc.c readl(pcie->base + oarr_offset + 4)); base 900 drivers/pci/controller/pcie-iproc.c readl(pcie->base + omap_offset), base 901 drivers/pci/controller/pcie-iproc.c readl(pcie->base + omap_offset + 4)); base 1093 drivers/pci/controller/pcie-iproc.c pcie->base + iarr_offset); base 1094 drivers/pci/controller/pcie-iproc.c writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4); base 1097 drivers/pci/controller/pcie-iproc.c readl(pcie->base + iarr_offset), base 1098 drivers/pci/controller/pcie-iproc.c readl(pcie->base + iarr_offset + 4)); base 1106 drivers/pci/controller/pcie-iproc.c val = readl(pcie->base + imap_offset); base 1108 drivers/pci/controller/pcie-iproc.c writel(val, pcie->base + imap_offset); base 1110 drivers/pci/controller/pcie-iproc.c pcie->base + imap_offset + ib_map->imap_addr_offset); base 1113 drivers/pci/controller/pcie-iproc.c window_idx, readl(pcie->base + imap_offset), base 1114 drivers/pci/controller/pcie-iproc.c readl(pcie->base + imap_offset + base 85 drivers/pci/controller/pcie-iproc.h void __iomem *base; base 184 drivers/pci/controller/pcie-mediatek.c void __iomem *base; base 216 drivers/pci/controller/pcie-mediatek.c void __iomem *base; base 240 drivers/pci/controller/pcie-mediatek.c devm_iounmap(dev, port->base); base 269 drivers/pci/controller/pcie-mediatek.c err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, base 275 drivers/pci/controller/pcie-mediatek.c if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) base 288 drivers/pci/controller/pcie-mediatek.c port->base + PCIE_CFG_HEADER0); base 289 drivers/pci/controller/pcie-mediatek.c writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); base 291 drivers/pci/controller/pcie-mediatek.c port->base + PCIE_CFG_HEADER2); base 294 drivers/pci/controller/pcie-mediatek.c tmp = readl(port->base + PCIE_APP_TLP_REQ); base 296 drivers/pci/controller/pcie-mediatek.c writel(tmp, port->base + PCIE_APP_TLP_REQ); base 303 drivers/pci/controller/pcie-mediatek.c *val = readl(port->base + PCIE_CFG_RDATA); base 318 drivers/pci/controller/pcie-mediatek.c port->base + PCIE_CFG_HEADER0); base 319 drivers/pci/controller/pcie-mediatek.c writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); base 321 drivers/pci/controller/pcie-mediatek.c port->base + PCIE_CFG_HEADER2); base 325 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_CFG_WDATA); base 328 drivers/pci/controller/pcie-mediatek.c val = readl(port->base + PCIE_APP_TLP_REQ); base 330 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_APP_TLP_REQ); base 404 drivers/pci/controller/pcie-mediatek.c addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); base 425 drivers/pci/controller/pcie-mediatek.c writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); base 527 drivers/pci/controller/pcie-mediatek.c msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); base 529 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_IMSI_ADDR); base 531 drivers/pci/controller/pcie-mediatek.c val = readl(port->base + PCIE_INT_MASK); base 533 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_INT_MASK); base 611 drivers/pci/controller/pcie-mediatek.c status = readl(port->base + PCIE_INT_STATUS); base 615 drivers/pci/controller/pcie-mediatek.c writel(1 << bit, port->base + PCIE_INT_STATUS); base 626 drivers/pci/controller/pcie-mediatek.c while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { base 633 drivers/pci/controller/pcie-mediatek.c writel(MSI_STATUS, port->base + PCIE_INT_STATUS); base 670 drivers/pci/controller/pcie-mediatek.c if (pcie->base) { base 671 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_SYS_CFG_V2); base 674 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_SYS_CFG_V2); base 678 drivers/pci/controller/pcie-mediatek.c writel(0, port->base + PCIE_RST_CTRL); base 685 drivers/pci/controller/pcie-mediatek.c writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); base 688 drivers/pci/controller/pcie-mediatek.c val = readl(port->base + PCIE_RST_CTRL); base 691 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_RST_CTRL); base 696 drivers/pci/controller/pcie-mediatek.c writew(val, port->base + PCIE_CONF_VEND_ID); base 699 drivers/pci/controller/pcie-mediatek.c writew(val, port->base + PCIE_CONF_CLASS_ID); base 703 drivers/pci/controller/pcie-mediatek.c writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); base 706 drivers/pci/controller/pcie-mediatek.c err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, base 713 drivers/pci/controller/pcie-mediatek.c val = readl(port->base + PCIE_INT_MASK); base 715 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_INT_MASK); base 723 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); base 726 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); base 730 drivers/pci/controller/pcie-mediatek.c writel(val, port->base + PCIE_AXI_WINDOW0); base 741 drivers/pci/controller/pcie-mediatek.c bus->number), pcie->base + PCIE_CFG_ADDR); base 743 drivers/pci/controller/pcie-mediatek.c return pcie->base + PCIE_CFG_DATA + (where & 3); base 761 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_SYS_CFG); base 763 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_SYS_CFG); base 766 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_SYS_CFG); base 768 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_SYS_CFG); base 771 drivers/pci/controller/pcie-mediatek.c err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, base 778 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_INT_ENABLE); base 780 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_INT_ENABLE); base 784 drivers/pci/controller/pcie-mediatek.c port->base + PCIE_BAR0_SETUP); base 787 drivers/pci/controller/pcie-mediatek.c writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); base 791 drivers/pci/controller/pcie-mediatek.c pcie->base + PCIE_CFG_ADDR); base 792 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_CFG_DATA); base 796 drivers/pci/controller/pcie-mediatek.c pcie->base + PCIE_CFG_ADDR); base 797 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_CFG_DATA); base 801 drivers/pci/controller/pcie-mediatek.c pcie->base + PCIE_CFG_ADDR); base 802 drivers/pci/controller/pcie-mediatek.c val = readl(pcie->base + PCIE_CFG_DATA); base 806 drivers/pci/controller/pcie-mediatek.c pcie->base + PCIE_CFG_ADDR); base 807 drivers/pci/controller/pcie-mediatek.c writel(val, pcie->base + PCIE_CFG_DATA); base 910 drivers/pci/controller/pcie-mediatek.c port->base = devm_ioremap_resource(dev, regs); base 911 drivers/pci/controller/pcie-mediatek.c if (IS_ERR(port->base)) { base 913 drivers/pci/controller/pcie-mediatek.c return PTR_ERR(port->base); base 985 drivers/pci/controller/pcie-mediatek.c pcie->base = devm_ioremap_resource(dev, regs); base 986 drivers/pci/controller/pcie-mediatek.c if (IS_ERR(pcie->base)) { base 988 drivers/pci/controller/pcie-mediatek.c return PTR_ERR(pcie->base); base 153 drivers/pci/controller/pcie-rcar.c void __iomem *base; base 163 drivers/pci/controller/pcie-rcar.c writel(val, pcie->base + reg); base 168 drivers/pci/controller/pcie-rcar.c return readl(pcie->base + reg); base 900 drivers/pci/controller/pcie-rcar.c phys_addr_t base; base 943 drivers/pci/controller/pcie-rcar.c base = virt_to_phys((void *)msi->pages); base 945 drivers/pci/controller/pcie-rcar.c rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR); base 946 drivers/pci/controller/pcie-rcar.c rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR); base 987 drivers/pci/controller/pcie-rcar.c pcie->base = devm_ioremap_resource(dev, &res); base 988 drivers/pci/controller/pcie-rcar.c if (IS_ERR(pcie->base)) base 989 drivers/pci/controller/pcie-rcar.c return PTR_ERR(pcie->base); base 21 drivers/pci/controller/pcie-tango.c void __iomem *base; base 29 drivers/pci/controller/pcie-tango.c unsigned long status, base, virq, idx, pos = 0; base 35 drivers/pci/controller/pcie-tango.c base = round_down(pos, 32); base 36 drivers/pci/controller/pcie-tango.c status = readl_relaxed(pcie->base + SMP8759_STATUS + base / 8); base 38 drivers/pci/controller/pcie-tango.c virq = irq_find_mapping(pcie->dom, base + idx); base 41 drivers/pci/controller/pcie-tango.c pos = base + 32; base 54 drivers/pci/controller/pcie-tango.c writel_relaxed(bit, pcie->base + SMP8759_STATUS + offset); base 66 drivers/pci/controller/pcie-tango.c val = readl_relaxed(pcie->base + SMP8759_ENABLE + offset); base 68 drivers/pci/controller/pcie-tango.c writel_relaxed(val, pcie->base + SMP8759_ENABLE + offset); base 189 drivers/pci/controller/pcie-tango.c writel_relaxed(1, pcie->base + SMP8759_MUX); base 191 drivers/pci/controller/pcie-tango.c writel_relaxed(0, pcie->base + SMP8759_MUX); base 203 drivers/pci/controller/pcie-tango.c writel_relaxed(1, pcie->base + SMP8759_MUX); base 205 drivers/pci/controller/pcie-tango.c writel_relaxed(0, pcie->base + SMP8759_MUX); base 221 drivers/pci/controller/pcie-tango.c void __iomem *test_out = pcie->base + SMP8759_TEST_OUT; base 254 drivers/pci/controller/pcie-tango.c pcie->base = devm_ioremap_resource(dev, res); base 255 drivers/pci/controller/pcie-tango.c if (IS_ERR(pcie->base)) base 256 drivers/pci/controller/pcie-tango.c return PTR_ERR(pcie->base); base 273 drivers/pci/controller/pcie-tango.c writel_relaxed(0, pcie->base + SMP8759_ENABLE + offset); base 576 drivers/pci/controller/pcie-xilinx-nwl.c unsigned long base; base 625 drivers/pci/controller/pcie-xilinx-nwl.c base = pcie->phys_pcie_reg_base; base 626 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); base 627 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); base 134 drivers/pci/ecam.c void __iomem *base; base 141 drivers/pci/ecam.c base = cfg->winp[busn]; base 143 drivers/pci/ecam.c base = cfg->win + (busn << cfg->ops->bus_shift); base 144 drivers/pci/ecam.c return base + (devfn << devfn_shift) + where; base 432 drivers/pci/endpoint/functions/pci-epf-test.c void *base; base 445 drivers/pci/endpoint/functions/pci-epf-test.c base = pci_epf_alloc_space(epf, test_reg_size, base 447 drivers/pci/endpoint/functions/pci-epf-test.c if (!base) { base 451 drivers/pci/endpoint/functions/pci-epf-test.c epf_test->reg[test_reg_bar] = base; base 463 drivers/pci/endpoint/functions/pci-epf-test.c base = pci_epf_alloc_space(epf, bar_size[bar], bar, base 465 drivers/pci/endpoint/functions/pci-epf-test.c if (!base) base 468 drivers/pci/endpoint/functions/pci-epf-test.c epf_test->reg[bar] = base; base 268 drivers/pci/hotplug/cpqphp.h u32 base; base 414 drivers/pci/hotplug/cpqphp_ctrl.c if ((*head)->base != (*orig_head)->base) base 438 drivers/pci/hotplug/cpqphp_ctrl.c split_node->base = node->base; base 442 drivers/pci/hotplug/cpqphp_ctrl.c node->base += split_node->length; base 496 drivers/pci/hotplug/cpqphp_ctrl.c if (node->base & (alignment - 1)) { base 498 drivers/pci/hotplug/cpqphp_ctrl.c temp_dword = (node->base | (alignment-1)) + 1; base 499 drivers/pci/hotplug/cpqphp_ctrl.c if ((node->length - (temp_dword - node->base)) < alignment) base 502 drivers/pci/hotplug/cpqphp_ctrl.c node->length -= (temp_dword - node->base); base 503 drivers/pci/hotplug/cpqphp_ctrl.c node->base = temp_dword; base 546 drivers/pci/hotplug/cpqphp_ctrl.c if (node->base & (size - 1)) { base 550 drivers/pci/hotplug/cpqphp_ctrl.c temp_dword = (node->base | (size-1)) + 1; base 553 drivers/pci/hotplug/cpqphp_ctrl.c if ((node->length - (temp_dword - node->base)) < size) base 561 drivers/pci/hotplug/cpqphp_ctrl.c split_node->base = node->base; base 562 drivers/pci/hotplug/cpqphp_ctrl.c split_node->length = temp_dword - node->base; base 563 drivers/pci/hotplug/cpqphp_ctrl.c node->base = temp_dword; base 581 drivers/pci/hotplug/cpqphp_ctrl.c split_node->base = node->base + size; base 591 drivers/pci/hotplug/cpqphp_ctrl.c if (node->base & 0x300L) base 643 drivers/pci/hotplug/cpqphp_ctrl.c if (max->base & (size - 1)) { base 647 drivers/pci/hotplug/cpqphp_ctrl.c temp_dword = (max->base | (size-1)) + 1; base 650 drivers/pci/hotplug/cpqphp_ctrl.c if ((max->length - (temp_dword - max->base)) < size) base 658 drivers/pci/hotplug/cpqphp_ctrl.c split_node->base = max->base; base 659 drivers/pci/hotplug/cpqphp_ctrl.c split_node->length = temp_dword - max->base; base 660 drivers/pci/hotplug/cpqphp_ctrl.c max->base = temp_dword; base 667 drivers/pci/hotplug/cpqphp_ctrl.c if ((max->base + max->length) & (size - 1)) { base 675 drivers/pci/hotplug/cpqphp_ctrl.c temp_dword = ((max->base + max->length) & ~(size - 1)); base 676 drivers/pci/hotplug/cpqphp_ctrl.c split_node->base = temp_dword; base 677 drivers/pci/hotplug/cpqphp_ctrl.c split_node->length = max->length + max->base base 678 drivers/pci/hotplug/cpqphp_ctrl.c - split_node->base; base 735 drivers/pci/hotplug/cpqphp_ctrl.c __func__, size, node, node->base, node->length); base 739 drivers/pci/hotplug/cpqphp_ctrl.c if (node->base & (size - 1)) { base 744 drivers/pci/hotplug/cpqphp_ctrl.c temp_dword = (node->base | (size-1)) + 1; base 747 drivers/pci/hotplug/cpqphp_ctrl.c if ((node->length - (temp_dword - node->base)) < size) base 755 drivers/pci/hotplug/cpqphp_ctrl.c split_node->base = node->base; base 756 drivers/pci/hotplug/cpqphp_ctrl.c split_node->length = temp_dword - node->base; base 757 drivers/pci/hotplug/cpqphp_ctrl.c node->base = temp_dword; base 775 drivers/pci/hotplug/cpqphp_ctrl.c split_node->base = node->base + size; base 829 drivers/pci/hotplug/cpqphp_ctrl.c dbg("*head->base = 0x%x\n", (*head)->base); base 830 drivers/pci/hotplug/cpqphp_ctrl.c dbg("*head->next->base = 0x%x\n", (*head)->next->base); base 836 drivers/pci/hotplug/cpqphp_ctrl.c ((*head)->base > (*head)->next->base)) { base 847 drivers/pci/hotplug/cpqphp_ctrl.c if (node1->next->base > node1->next->next->base) { base 862 drivers/pci/hotplug/cpqphp_ctrl.c if ((node1->base + node1->length) == node1->next->base) { base 2332 drivers/pci/hotplug/cpqphp_ctrl.c u32 base; base 2373 drivers/pci/hotplug/cpqphp_ctrl.c temp_byte = bus_node->base; base 2374 drivers/pci/hotplug/cpqphp_ctrl.c dbg("set Secondary bus = %d\n", bus_node->base); base 2380 drivers/pci/hotplug/cpqphp_ctrl.c temp_byte = bus_node->base + bus_node->length - 1; base 2381 drivers/pci/hotplug/cpqphp_ctrl.c dbg("set subordinate bus = %d\n", bus_node->base + bus_node->length - 1); base 2413 drivers/pci/hotplug/cpqphp_ctrl.c dbg("(base, len, next) (%x, %x, %p)\n", io_node->base, base 2416 drivers/pci/hotplug/cpqphp_ctrl.c dbg("(base, len, next) (%x, %x, %p)\n", mem_node->base, base 2419 drivers/pci/hotplug/cpqphp_ctrl.c dbg("(base, len, next) (%x, %x, %p)\n", p_mem_node->base, base 2466 drivers/pci/hotplug/cpqphp_ctrl.c bus_node->base += 1; base 2476 drivers/pci/hotplug/cpqphp_ctrl.c temp_byte = io_node->base >> 8; base 2479 drivers/pci/hotplug/cpqphp_ctrl.c temp_byte = (io_node->base + io_node->length - 1) >> 8; base 2489 drivers/pci/hotplug/cpqphp_ctrl.c temp_word = mem_node->base >> 16; base 2492 drivers/pci/hotplug/cpqphp_ctrl.c temp_word = (mem_node->base + mem_node->length - 1) >> 16; base 2499 drivers/pci/hotplug/cpqphp_ctrl.c temp_word = p_mem_node->base >> 16; base 2502 drivers/pci/hotplug/cpqphp_ctrl.c temp_word = (p_mem_node->base + p_mem_node->length - 1) >> 16; base 2516 drivers/pci/hotplug/cpqphp_ctrl.c pci_bus->number = hold_bus_node->base; base 2522 drivers/pci/hotplug/cpqphp_ctrl.c new_slot = cpqhp_slot_create(hold_bus_node->base); base 2529 drivers/pci/hotplug/cpqphp_ctrl.c new_slot->bus = hold_bus_node->base; base 2564 drivers/pci/hotplug/cpqphp_ctrl.c hold_bus_node->length = bus_node->base - hold_bus_node->base; base 2569 drivers/pci/hotplug/cpqphp_ctrl.c temp_byte = temp_resources.bus_head->base - 1; base 2590 drivers/pci/hotplug/cpqphp_ctrl.c hold_IO_node->base = io_node->base + io_node->length; base 2592 drivers/pci/hotplug/cpqphp_ctrl.c temp_byte = (hold_IO_node->base) >> 8; base 2604 drivers/pci/hotplug/cpqphp_ctrl.c hold_IO_node->length = io_node->base - hold_IO_node->base; base 2611 drivers/pci/hotplug/cpqphp_ctrl.c temp_byte = (io_node->base - 1) >> 8; base 2641 drivers/pci/hotplug/cpqphp_ctrl.c hold_mem_node->base = mem_node->base + mem_node->length; base 2643 drivers/pci/hotplug/cpqphp_ctrl.c temp_word = (hold_mem_node->base) >> 16; base 2655 drivers/pci/hotplug/cpqphp_ctrl.c hold_mem_node->length = mem_node->base - hold_mem_node->base; base 2662 drivers/pci/hotplug/cpqphp_ctrl.c temp_word = (mem_node->base - 1) >> 16; base 2693 drivers/pci/hotplug/cpqphp_ctrl.c hold_p_mem_node->base = p_mem_node->base + p_mem_node->length; base 2695 drivers/pci/hotplug/cpqphp_ctrl.c temp_word = (hold_p_mem_node->base) >> 16; base 2707 drivers/pci/hotplug/cpqphp_ctrl.c hold_p_mem_node->length = p_mem_node->base - hold_p_mem_node->base; base 2714 drivers/pci/hotplug/cpqphp_ctrl.c temp_word = (p_mem_node->base - 1) >> 16; base 2777 drivers/pci/hotplug/cpqphp_ctrl.c base = temp_register & 0xFFFFFFFC; base 2778 drivers/pci/hotplug/cpqphp_ctrl.c base = ~base + 1; base 2780 drivers/pci/hotplug/cpqphp_ctrl.c dbg("CND: length = 0x%x\n", base); base 2781 drivers/pci/hotplug/cpqphp_ctrl.c io_node = get_io_resource(&(resources->io_head), base); base 2785 drivers/pci/hotplug/cpqphp_ctrl.c io_node->base, io_node->length, io_node->next); base 2789 drivers/pci/hotplug/cpqphp_ctrl.c base = io_node->base; base 2794 drivers/pci/hotplug/cpqphp_ctrl.c base = temp_register & 0xFFFFFFF0; base 2795 drivers/pci/hotplug/cpqphp_ctrl.c base = ~base + 1; base 2797 drivers/pci/hotplug/cpqphp_ctrl.c dbg("CND: length = 0x%x\n", base); base 2798 drivers/pci/hotplug/cpqphp_ctrl.c p_mem_node = get_resource(&(resources->p_mem_head), base); base 2802 drivers/pci/hotplug/cpqphp_ctrl.c base = p_mem_node->base; base 2810 drivers/pci/hotplug/cpqphp_ctrl.c base = temp_register & 0xFFFFFFF0; base 2811 drivers/pci/hotplug/cpqphp_ctrl.c base = ~base + 1; base 2813 drivers/pci/hotplug/cpqphp_ctrl.c dbg("CND: length = 0x%x\n", base); base 2814 drivers/pci/hotplug/cpqphp_ctrl.c mem_node = get_resource(&(resources->mem_head), base); base 2818 drivers/pci/hotplug/cpqphp_ctrl.c base = mem_node->base; base 2829 drivers/pci/hotplug/cpqphp_ctrl.c rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, base); base 2839 drivers/pci/hotplug/cpqphp_ctrl.c base = 0; base 2840 drivers/pci/hotplug/cpqphp_ctrl.c rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, base); base 298 drivers/pci/hotplug/cpqphp_nvram.c rc = add_dword(&pFill, resNode->base, &usedbytes, &available); base 323 drivers/pci/hotplug/cpqphp_nvram.c rc = add_dword(&pFill, resNode->base, &usedbytes, &available); base 348 drivers/pci/hotplug/cpqphp_nvram.c rc = add_dword(&pFill, resNode->base, &usedbytes, &available); base 373 drivers/pci/hotplug/cpqphp_nvram.c rc = add_dword(&pFill, resNode->base, &usedbytes, &available); base 515 drivers/pci/hotplug/cpqphp_nvram.c mem_node->base = *(u32 *)p_byte; base 516 drivers/pci/hotplug/cpqphp_nvram.c dbg("mem base = %8.8x\n", mem_node->base); base 543 drivers/pci/hotplug/cpqphp_nvram.c p_mem_node->base = *(u32 *)p_byte; base 544 drivers/pci/hotplug/cpqphp_nvram.c dbg("pre-mem base = %8.8x\n", p_mem_node->base); base 571 drivers/pci/hotplug/cpqphp_nvram.c io_node->base = *(u32 *)p_byte; base 572 drivers/pci/hotplug/cpqphp_nvram.c dbg("io base = %8.8x\n", io_node->base); base 599 drivers/pci/hotplug/cpqphp_nvram.c bus_node->base = *(u32 *)p_byte; base 556 drivers/pci/hotplug/cpqphp_pci.c u32 base; base 595 drivers/pci/hotplug/cpqphp_pci.c pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); base 597 drivers/pci/hotplug/cpqphp_pci.c if (base) { base 598 drivers/pci/hotplug/cpqphp_pci.c if (base & 0x01L) { base 603 drivers/pci/hotplug/cpqphp_pci.c base = base & 0xFFFFFFFE; base 604 drivers/pci/hotplug/cpqphp_pci.c base = (~base) + 1; base 609 drivers/pci/hotplug/cpqphp_pci.c base = base & 0xFFFFFFF0; base 610 drivers/pci/hotplug/cpqphp_pci.c base = (~base) + 1; base 615 drivers/pci/hotplug/cpqphp_pci.c base = 0x0L; base 621 drivers/pci/hotplug/cpqphp_pci.c base; base 631 drivers/pci/hotplug/cpqphp_pci.c pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); base 634 drivers/pci/hotplug/cpqphp_pci.c if (base) { base 635 drivers/pci/hotplug/cpqphp_pci.c if (base & 0x01L) { base 640 drivers/pci/hotplug/cpqphp_pci.c base = base & 0xFFFFFFFE; base 641 drivers/pci/hotplug/cpqphp_pci.c base = (~base) + 1; base 649 drivers/pci/hotplug/cpqphp_pci.c base = base & 0xFFFFFFF0; base 650 drivers/pci/hotplug/cpqphp_pci.c base = (~base) + 1; base 655 drivers/pci/hotplug/cpqphp_pci.c base = 0x0L; base 660 drivers/pci/hotplug/cpqphp_pci.c func->base_length[(cloop - 0x10) >> 2] = base; base 699 drivers/pci/hotplug/cpqphp_pci.c u32 base; base 735 drivers/pci/hotplug/cpqphp_pci.c bus_node->base = secondary_bus; base 750 drivers/pci/hotplug/cpqphp_pci.c io_node->base = (b_base & 0xF0) << 8; base 766 drivers/pci/hotplug/cpqphp_pci.c mem_node->base = w_base << 16; base 782 drivers/pci/hotplug/cpqphp_pci.c p_mem_node->base = w_base << 16; base 794 drivers/pci/hotplug/cpqphp_pci.c pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); base 796 drivers/pci/hotplug/cpqphp_pci.c temp_register = base; base 799 drivers/pci/hotplug/cpqphp_pci.c if (base) { base 800 drivers/pci/hotplug/cpqphp_pci.c if (((base & 0x03L) == 0x01) base 806 drivers/pci/hotplug/cpqphp_pci.c temp_register = base & 0xFFFFFFFE; base 814 drivers/pci/hotplug/cpqphp_pci.c io_node->base = base 821 drivers/pci/hotplug/cpqphp_pci.c if (((base & 0x0BL) == 0x08) base 824 drivers/pci/hotplug/cpqphp_pci.c temp_register = base & 0xFFFFFFF0; base 832 drivers/pci/hotplug/cpqphp_pci.c p_mem_node->base = save_base & (~0x0FL); base 838 drivers/pci/hotplug/cpqphp_pci.c if (((base & 0x0BL) == 0x00) base 841 drivers/pci/hotplug/cpqphp_pci.c temp_register = base & 0xFFFFFFF0; base 849 drivers/pci/hotplug/cpqphp_pci.c mem_node->base = save_base & (~0x0FL); base 866 drivers/pci/hotplug/cpqphp_pci.c pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); base 868 drivers/pci/hotplug/cpqphp_pci.c temp_register = base; base 871 drivers/pci/hotplug/cpqphp_pci.c if (base) { base 872 drivers/pci/hotplug/cpqphp_pci.c if (((base & 0x03L) == 0x01) base 878 drivers/pci/hotplug/cpqphp_pci.c temp_register = base & 0xFFFFFFFE; base 886 drivers/pci/hotplug/cpqphp_pci.c io_node->base = save_base & (~0x01L); base 892 drivers/pci/hotplug/cpqphp_pci.c if (((base & 0x0BL) == 0x08) base 895 drivers/pci/hotplug/cpqphp_pci.c temp_register = base & 0xFFFFFFF0; base 903 drivers/pci/hotplug/cpqphp_pci.c p_mem_node->base = save_base & (~0x0FL); base 909 drivers/pci/hotplug/cpqphp_pci.c if (((base & 0x0BL) == 0x00) base 912 drivers/pci/hotplug/cpqphp_pci.c temp_register = base & 0xFFFFFFF0; base 920 drivers/pci/hotplug/cpqphp_pci.c mem_node->base = save_base & (~0x0FL); base 1033 drivers/pci/hotplug/cpqphp_pci.c u32 base; base 1108 drivers/pci/hotplug/cpqphp_pci.c pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); base 1111 drivers/pci/hotplug/cpqphp_pci.c if (base) { base 1112 drivers/pci/hotplug/cpqphp_pci.c if (base & 0x01L) { base 1117 drivers/pci/hotplug/cpqphp_pci.c base = base & 0xFFFFFFFE; base 1118 drivers/pci/hotplug/cpqphp_pci.c base = (~base) + 1; base 1123 drivers/pci/hotplug/cpqphp_pci.c base = base & 0xFFFFFFF0; base 1124 drivers/pci/hotplug/cpqphp_pci.c base = (~base) + 1; base 1129 drivers/pci/hotplug/cpqphp_pci.c base = 0x0L; base 1134 drivers/pci/hotplug/cpqphp_pci.c if (func->base_length[(cloop - 0x10) >> 2] != base) base 1307 drivers/pci/hotplug/cpqphp_pci.c io_node->base = io_base; base 1311 drivers/pci/hotplug/cpqphp_pci.c io_node->base, io_node->length); base 1329 drivers/pci/hotplug/cpqphp_pci.c mem_node->base = mem_base << 16; base 1334 drivers/pci/hotplug/cpqphp_pci.c mem_node->base, mem_node->length); base 1354 drivers/pci/hotplug/cpqphp_pci.c p_mem_node->base = pre_mem_base << 16; base 1358 drivers/pci/hotplug/cpqphp_pci.c p_mem_node->base, p_mem_node->length); base 1379 drivers/pci/hotplug/cpqphp_pci.c bus_node->base = secondary_bus; base 1382 drivers/pci/hotplug/cpqphp_pci.c bus_node->base, bus_node->length); base 38 drivers/pci/hotplug/cpqphp_sysfs.c out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length); base 45 drivers/pci/hotplug/cpqphp_sysfs.c out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length); base 52 drivers/pci/hotplug/cpqphp_sysfs.c out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length); base 59 drivers/pci/hotplug/cpqphp_sysfs.c out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length); base 84 drivers/pci/hotplug/cpqphp_sysfs.c out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length); base 91 drivers/pci/hotplug/cpqphp_sysfs.c out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length); base 98 drivers/pci/hotplug/cpqphp_sysfs.c out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length); base 105 drivers/pci/hotplug/cpqphp_sysfs.c out += sprintf(out, "start = %8.8x, length = %8.8x\n", res->base, res->length); base 234 drivers/pci/hotplug/ibmphp_ebda.c u16 ebda_seg, num_entries, next_offset, offset, blk_id, sub_addr, re, rc_id, re_id, base; base 292 drivers/pci/hotplug/ibmphp_ebda.c base = offset; base 294 drivers/pci/hotplug/ibmphp_ebda.c sub_addr = base; base 320 drivers/pci/hotplug/ibmphp_ebda.c sub_addr = base + re; /* re sub blk */ base 370 drivers/pci/hotplug/ibmphp_hpc.c static u8 ctrl_read(struct controller *ctlr, void __iomem *base, u8 offset) base 382 drivers/pci/hotplug/ibmphp_hpc.c rc = i2c_ctrl_read(ctlr, base, offset); base 390 drivers/pci/hotplug/ibmphp_hpc.c static u8 ctrl_write(struct controller *ctlr, void __iomem *base, u8 offset, u8 data) base 402 drivers/pci/hotplug/ibmphp_hpc.c rc = i2c_ctrl_write(ctlr, base, offset, data); base 283 drivers/pci/msi.c void __iomem *base = pci_msix_desc_addr(entry); base 285 drivers/pci/msi.c if (!base) { base 290 drivers/pci/msi.c msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); base 291 drivers/pci/msi.c msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); base 292 drivers/pci/msi.c msg->data = readl(base + PCI_MSIX_ENTRY_DATA); base 318 drivers/pci/msi.c void __iomem *base = pci_msix_desc_addr(entry); base 320 drivers/pci/msi.c if (!base) base 323 drivers/pci/msi.c writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); base 324 drivers/pci/msi.c writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); base 325 drivers/pci/msi.c writel(msg->data, base + PCI_MSIX_ENTRY_DATA); base 694 drivers/pci/msi.c static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, base 710 drivers/pci/msi.c iounmap(base); base 729 drivers/pci/msi.c entry->mask_base = base; base 779 drivers/pci/msi.c void __iomem *base; base 786 drivers/pci/msi.c base = msix_map_region(dev, msix_table_size(control)); base 787 drivers/pci/msi.c if (!base) base 790 drivers/pci/msi.c ret = msix_setup_entries(dev, base, entries, nvec, affd); base 2901 drivers/pci/pci.c u32 dw0, bei, base, max_offset; base 2939 drivers/pci/pci.c pci_read_config_dword(dev, ent_offset, &base); base 2940 drivers/pci/pci.c start = (base & PCI_EA_FIELD_MASK); base 2948 drivers/pci/pci.c if (base & PCI_EA_IS_64) { base 109 drivers/pci/probe.c static u64 pci_size(u64 base, u64 maxbase, u64 mask) base 125 drivers/pci/probe.c if (base == maxbase && ((base | (size - 1)) & mask) != mask) base 401 drivers/pci/probe.c unsigned long io_mask, io_granularity, base, limit; base 416 drivers/pci/probe.c base = (io_base_lo & io_mask) << 8; base 424 drivers/pci/probe.c base |= ((unsigned long) io_base_hi << 16); base 428 drivers/pci/probe.c if (base <= limit) { base 430 drivers/pci/probe.c region.start = base; base 441 drivers/pci/probe.c unsigned long base, limit; base 448 drivers/pci/probe.c base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; base 450 drivers/pci/probe.c if (base <= limit) { base 452 drivers/pci/probe.c region.start = base; base 464 drivers/pci/probe.c pci_bus_addr_t base, limit; base 491 drivers/pci/probe.c base = (pci_bus_addr_t) base64; base 494 drivers/pci/probe.c if (base != base64) { base 500 drivers/pci/probe.c if (base <= limit) { base 505 drivers/pci/probe.c region.start = base; base 664 drivers/pci/quirks.c u32 mask, size, base; base 670 drivers/pci/quirks.c base = devres & 0xffff; base 683 drivers/pci/quirks.c base &= -size; base 684 drivers/pci/quirks.c pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); base 690 drivers/pci/quirks.c u32 mask, size, base; base 695 drivers/pci/quirks.c base = devres & 0xffff0000; base 709 drivers/pci/quirks.c base &= -size; base 710 drivers/pci/quirks.c pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); base 817 drivers/pci/quirks.c u32 size, base; base 824 drivers/pci/quirks.c base = val & 0xfffc; base 836 drivers/pci/quirks.c base &= ~(size-1); base 842 drivers/pci/quirks.c pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); base 861 drivers/pci/quirks.c u32 mask, base; base 870 drivers/pci/quirks.c base = val & 0xfffc; base 878 drivers/pci/quirks.c pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); base 36 drivers/pcmcia/bcm63xx_pcmcia.c return bcm_readl(skt->base + off); base 42 drivers/pcmcia/bcm63xx_pcmcia.c bcm_writel(val, skt->base + off); base 361 drivers/pcmcia/bcm63xx_pcmcia.c skt->base = ioremap(res->start, regmem_size); base 362 drivers/pcmcia/bcm63xx_pcmcia.c if (!skt->base) { base 431 drivers/pcmcia/bcm63xx_pcmcia.c if (skt->base) base 432 drivers/pcmcia/bcm63xx_pcmcia.c iounmap(skt->base); base 446 drivers/pcmcia/bcm63xx_pcmcia.c iounmap(skt->base); base 35 drivers/pcmcia/bcm63xx_pcmcia.h void __iomem *base; base 889 drivers/pcmcia/cistpl.c config->base = 0; base 891 drivers/pcmcia/cistpl.c config->base += p[i] << (8*i); base 987 drivers/pcmcia/cistpl.c io->win[0].base = 0; base 1004 drivers/pcmcia/cistpl.c io->win[i].base = 0; base 1009 drivers/pcmcia/cistpl.c io->win[i].base += *p << (j*8); base 50 drivers/pcmcia/cs_internal.h unsigned int *base, base 54 drivers/pcmcia/cs_internal.h struct resource* (*find_mem) (unsigned long base, unsigned long num, base 142 drivers/pcmcia/cs_internal.h extern struct resource *pcmcia_find_mem_region(u_long base, base 279 drivers/pcmcia/ds.c p_dev->config_base = cis_config.base; base 607 drivers/pcmcia/i82092.c unsigned short base, i; base 641 drivers/pcmcia/i82092.c base = I365_MEM(map); base 647 drivers/pcmcia/i82092.c indirect_write16(sock,base+I365_W_START,i); base 666 drivers/pcmcia/i82092.c indirect_write16(sock,base+I365_W_STOP,i); base 679 drivers/pcmcia/i82092.c indirect_write16(sock,base+I365_W_OFF,i); base 675 drivers/pcmcia/i82365.c u_int mask = 0, i, base; base 679 drivers/pcmcia/i82365.c base = sockets-ns; base 680 drivers/pcmcia/i82365.c if (base == 0) printk("\n"); base 692 drivers/pcmcia/i82365.c mask &= I365_MASK & set_bridge_opts(base, ns); base 694 drivers/pcmcia/i82365.c mask = isa_scan(base, mask); base 1063 drivers/pcmcia/i82365.c u_short base, i; base 1082 drivers/pcmcia/i82365.c base = I365_MEM(map); base 1086 drivers/pcmcia/i82365.c i365_set_pair(sock, base+I365_W_START, i); base 1095 drivers/pcmcia/i82365.c i365_set_pair(sock, base+I365_W_STOP, i); base 1100 drivers/pcmcia/i82365.c i365_set_pair(sock, base+I365_W_OFF, i); base 214 drivers/pcmcia/pcmcia_cis.c p_dev->resource[1]->start = io->win[1-i].base; base 217 drivers/pcmcia/pcmcia_cis.c p_dev->resource[0]->start = io->win[i].base; base 45 drivers/pcmcia/pcmcia_resource.c struct resource *pcmcia_find_mem_region(u_long base, u_long num, u_long align, base 49 drivers/pcmcia/pcmcia_resource.c return s->resource_ops->find_mem(base, num, align, low, s); base 100 drivers/pcmcia/pcmcia_resource.c unsigned int base = res->start; base 109 drivers/pcmcia/pcmcia_resource.c align = base ? (lines ? 1<<lines : 0) : 1; base 111 drivers/pcmcia/pcmcia_resource.c if (base) { base 118 drivers/pcmcia/pcmcia_resource.c if (base & ~(align-1)) { base 123 drivers/pcmcia/pcmcia_resource.c ret = s->resource_ops->find_io(s, res->flags, &base, num, align, base 130 drivers/pcmcia/pcmcia_resource.c res->start = base; base 483 drivers/pcmcia/pcmcia_resource.c unsigned int base; base 542 drivers/pcmcia/pcmcia_resource.c base = p_dev->config_base; base 546 drivers/pcmcia/pcmcia_resource.c pcmcia_write_cis_mem(s, 1, (base + CISREG_SCR)>>1, 1, &tmp); base 551 drivers/pcmcia/pcmcia_resource.c pcmcia_write_cis_mem(s, 1, (base + CISREG_PRR)>>1, 1, &tmp); base 565 drivers/pcmcia/pcmcia_resource.c pcmcia_write_cis_mem(s, 1, (base + CISREG_COR)>>1, 1, &option); base 569 drivers/pcmcia/pcmcia_resource.c pcmcia_write_cis_mem(s, 1, (base + CISREG_CCSR)>>1, 1, &status); base 572 drivers/pcmcia/pcmcia_resource.c pcmcia_write_cis_mem(s, 1, (base + CISREG_ESR)>>1, 1, base 577 drivers/pcmcia/pcmcia_resource.c pcmcia_write_cis_mem(s, 1, (base + CISREG_IOBASE_0)>>1, 1, &b); base 579 drivers/pcmcia/pcmcia_resource.c pcmcia_write_cis_mem(s, 1, (base + CISREG_IOBASE_1)>>1, 1, &b); base 583 drivers/pcmcia/pcmcia_resource.c pcmcia_write_cis_mem(s, 1, (base + CISREG_IOSIZE)>>1, 1, &b); base 471 drivers/pcmcia/pd6729.c unsigned short base, i; base 490 drivers/pcmcia/pd6729.c base = I365_MEM(map); base 496 drivers/pcmcia/pd6729.c indirect_write16(socket, base + I365_W_START, i); base 515 drivers/pcmcia/pd6729.c indirect_write16(socket, base + I365_W_STOP, i); base 534 drivers/pcmcia/pd6729.c indirect_write16(socket, base + I365_W_OFF, i); base 56 drivers/pcmcia/rsrc_iodyn.c unsigned long base, int num, base 62 drivers/pcmcia/rsrc_iodyn.c unsigned long min = base; base 66 drivers/pcmcia/rsrc_iodyn.c data.offset = base & data.mask; base 85 drivers/pcmcia/rsrc_iodyn.c unsigned int *base, unsigned int num, base 98 drivers/pcmcia/rsrc_iodyn.c if (!*base) base 101 drivers/pcmcia/rsrc_iodyn.c if ((s->io[i].res->start & (align-1)) == *base) base 117 drivers/pcmcia/rsrc_iodyn.c res = s->io[i].res = __iodyn_find_io_region(s, *base, base 122 drivers/pcmcia/rsrc_iodyn.c *base = res->start; base 133 drivers/pcmcia/rsrc_iodyn.c if ((*base == 0) || (*base == try)) { base 137 drivers/pcmcia/rsrc_iodyn.c *base = try; base 145 drivers/pcmcia/rsrc_iodyn.c if ((*base == 0) || (*base == try)) { base 150 drivers/pcmcia/rsrc_iodyn.c *base = try; base 46 drivers/pcmcia/rsrc_mgr.c unsigned int *base, unsigned int num, base 51 drivers/pcmcia/rsrc_mgr.c *base = s->io_offset | (*base & 0x0fff); base 49 drivers/pcmcia/rsrc_nonstatic.c u_long base, num; base 73 drivers/pcmcia/rsrc_nonstatic.c claim_region(struct pcmcia_socket *s, resource_size_t base, base 79 drivers/pcmcia/rsrc_nonstatic.c res = pcmcia_make_resource(base, size, type | IORESOURCE_BUSY, name); base 108 drivers/pcmcia/rsrc_nonstatic.c static int add_interval(struct resource_map *map, u_long base, u_long num) base 113 drivers/pcmcia/rsrc_nonstatic.c if ((p != map) && (p->base+p->num >= base)) { base 114 drivers/pcmcia/rsrc_nonstatic.c p->num = max(num + base - p->base, p->num); base 117 drivers/pcmcia/rsrc_nonstatic.c if ((p->next == map) || (p->next->base > base+num-1)) base 125 drivers/pcmcia/rsrc_nonstatic.c q->base = base; q->num = num; base 132 drivers/pcmcia/rsrc_nonstatic.c static int sub_interval(struct resource_map *map, u_long base, u_long num) base 140 drivers/pcmcia/rsrc_nonstatic.c if ((q->base+q->num > base) && (base+num > q->base)) { base 141 drivers/pcmcia/rsrc_nonstatic.c if (q->base >= base) { base 142 drivers/pcmcia/rsrc_nonstatic.c if (q->base+q->num <= base+num) { base 150 drivers/pcmcia/rsrc_nonstatic.c q->num = q->base + q->num - base - num; base 151 drivers/pcmcia/rsrc_nonstatic.c q->base = base + num; base 153 drivers/pcmcia/rsrc_nonstatic.c } else if (q->base+q->num <= base+num) { base 155 drivers/pcmcia/rsrc_nonstatic.c q->num = base - q->base; base 164 drivers/pcmcia/rsrc_nonstatic.c p->base = base+num; base 165 drivers/pcmcia/rsrc_nonstatic.c p->num = q->base+q->num - p->base; base 166 drivers/pcmcia/rsrc_nonstatic.c q->num = base - q->base; base 182 drivers/pcmcia/rsrc_nonstatic.c static void do_io_probe(struct pcmcia_socket *s, unsigned int base, base 191 drivers/pcmcia/rsrc_nonstatic.c dev_info(&s->dev, "cs: IO port probe %#x-%#x:", base, base+num-1); base 200 drivers/pcmcia/rsrc_nonstatic.c for (i = base, most = 0; i < base+num; i += 8) { base 217 drivers/pcmcia/rsrc_nonstatic.c for (i = base; i < base+num; i += 8) { base 244 drivers/pcmcia/rsrc_nonstatic.c if ((num > 16) && (bad == base) && (i == base+num)) { base 345 drivers/pcmcia/rsrc_nonstatic.c unsigned long base, unsigned long size, base 355 drivers/pcmcia/rsrc_nonstatic.c res1 = claim_region(s, base, size/2, IORESOURCE_MEM, "PCMCIA memprobe"); base 356 drivers/pcmcia/rsrc_nonstatic.c res2 = claim_region(s, base + size/2, size/2, IORESOURCE_MEM, base 368 drivers/pcmcia/rsrc_nonstatic.c base, base+size-1, res1, res2, ret, info1, info2); base 378 drivers/pcmcia/rsrc_nonstatic.c add_interval(&s_data->mem_db_valid, base, size); base 379 drivers/pcmcia/rsrc_nonstatic.c sub_interval(&s_data->mem_db, base, size); base 400 drivers/pcmcia/rsrc_nonstatic.c static int do_mem_probe(struct pcmcia_socket *s, u_long base, u_long num, base 412 drivers/pcmcia/rsrc_nonstatic.c base, base+num-1); base 421 drivers/pcmcia/rsrc_nonstatic.c for (i = j = base; i < base+num; i = j + step) { base 423 drivers/pcmcia/rsrc_nonstatic.c for (j = i; j < base+num; j += step) { base 427 drivers/pcmcia/rsrc_nonstatic.c fail = ((i == base) && (j == base+num)); base 430 drivers/pcmcia/rsrc_nonstatic.c for (j = i; j < base+num; j += step) base 462 drivers/pcmcia/rsrc_nonstatic.c if (m->base >= 0x100000) base 463 drivers/pcmcia/rsrc_nonstatic.c sub_interval(&s_data->mem_db, m->base, m->num); base 466 drivers/pcmcia/rsrc_nonstatic.c if (m->base < 0x100000) base 468 drivers/pcmcia/rsrc_nonstatic.c return do_mem_probe(s, m->base, m->num, readable, checksum); base 501 drivers/pcmcia/rsrc_nonstatic.c if (mm.base >= 0x100000) base 503 drivers/pcmcia/rsrc_nonstatic.c if ((mm.base | mm.num) & 0xffff) { base 504 drivers/pcmcia/rsrc_nonstatic.c ok += do_mem_probe(s, mm.base, mm.num, readable, base 511 drivers/pcmcia/rsrc_nonstatic.c if ((b >= mm.base) && (b+0x10000 <= mm.base+mm.num)) { base 544 drivers/pcmcia/rsrc_nonstatic.c ok += do_mem_probe(s, mm.base, mm.num, readable, checksum); base 613 drivers/pcmcia/rsrc_nonstatic.c unsigned long map_start = m->base; base 614 drivers/pcmcia/rsrc_nonstatic.c unsigned long map_end = m->base + m->num - 1; base 657 drivers/pcmcia/rsrc_nonstatic.c unsigned long start = m->base; base 658 drivers/pcmcia/rsrc_nonstatic.c unsigned long end = m->base + m->num - 1; base 683 drivers/pcmcia/rsrc_nonstatic.c unsigned long base, int num, base 690 drivers/pcmcia/rsrc_nonstatic.c unsigned long min = base; base 694 drivers/pcmcia/rsrc_nonstatic.c data.offset = base & data.mask; base 714 drivers/pcmcia/rsrc_nonstatic.c unsigned int *base, unsigned int num, base 727 drivers/pcmcia/rsrc_nonstatic.c if (!*base) base 730 drivers/pcmcia/rsrc_nonstatic.c if ((s->io[i].res->start & (align-1)) == *base) base 747 drivers/pcmcia/rsrc_nonstatic.c *base, num, base 752 drivers/pcmcia/rsrc_nonstatic.c *base = res->start; base 763 drivers/pcmcia/rsrc_nonstatic.c if ((*base == 0) || (*base == try)) { base 771 drivers/pcmcia/rsrc_nonstatic.c *base = try; base 780 drivers/pcmcia/rsrc_nonstatic.c if ((*base == 0) || (*base == try)) { base 790 drivers/pcmcia/rsrc_nonstatic.c *base = try; base 802 drivers/pcmcia/rsrc_nonstatic.c static struct resource *nonstatic_find_mem_region(u_long base, u_long num, base 815 drivers/pcmcia/rsrc_nonstatic.c data.offset = base & data.mask; base 821 drivers/pcmcia/rsrc_nonstatic.c min = base < max ? base : 0; base 824 drivers/pcmcia/rsrc_nonstatic.c min = 0x100000UL + base; base 1081 drivers/pcmcia/rsrc_nonstatic.c ((unsigned long) p->base), base 1082 drivers/pcmcia/rsrc_nonstatic.c ((unsigned long) p->base + p->num - 1)); base 1138 drivers/pcmcia/rsrc_nonstatic.c ((unsigned long) p->base), base 1139 drivers/pcmcia/rsrc_nonstatic.c ((unsigned long) p->base + p->num - 1)); base 1147 drivers/pcmcia/rsrc_nonstatic.c ((unsigned long) p->base), base 1148 drivers/pcmcia/rsrc_nonstatic.c ((unsigned long) p->base + p->num - 1)); base 193 drivers/pcmcia/sa1111_generic.c void __iomem *base; base 207 drivers/pcmcia/sa1111_generic.c base = dev->mapbase; base 212 drivers/pcmcia/sa1111_generic.c writel_relaxed(PCSSR_S0_SLEEP | PCSSR_S1_SLEEP, base + PCSSR); base 213 drivers/pcmcia/sa1111_generic.c writel_relaxed(PCCR_S0_FLT | PCCR_S1_FLT, base + PCCR); base 296 drivers/pcmcia/tcic.c u_short scf1, ioctl, base, num; base 307 drivers/pcmcia/tcic.c base = tcic_getw(TCIC_DATA); base 314 drivers/pcmcia/tcic.c num = (base ^ (base-1)); base 315 drivers/pcmcia/tcic.c base = base & (base-1); base 320 drivers/pcmcia/tcic.c ((base & 0xfeef) != 0x02e8)) { base 321 drivers/pcmcia/tcic.c struct resource *res = request_region(base, num, "tcic-2"); base 324 drivers/pcmcia/tcic.c release_region(base, num); base 698 drivers/pcmcia/tcic.c u_short base, len, ioctl; base 708 drivers/pcmcia/tcic.c base = io->start; len = io->stop - io->start; base 710 drivers/pcmcia/tcic.c if ((len & (len+1)) || (base & len)) return -EINVAL; base 711 drivers/pcmcia/tcic.c base |= (len+1)>>1; base 713 drivers/pcmcia/tcic.c tcic_setw(TCIC_DATA, base); base 735 drivers/pcmcia/tcic.c u_long base, len, mmap; base 748 drivers/pcmcia/tcic.c base = mem->res->start; len = mem->res->end - mem->res->start; base 749 drivers/pcmcia/tcic.c if ((len & (len+1)) || (base & len)) return -EINVAL; base 751 drivers/pcmcia/tcic.c base = (base >> TCIC_MBASE_HA_SHFT) | TCIC_MBASE_4K_BIT; base 753 drivers/pcmcia/tcic.c base = (base | (len+1)>>1) >> TCIC_MBASE_HA_SHFT; base 755 drivers/pcmcia/tcic.c tcic_setw(TCIC_DATA, base); base 58 drivers/pcmcia/vrc4173_cardu.c return readb(socket->base + EXCA_REGS_BASE + offset); base 65 drivers/pcmcia/vrc4173_cardu.c val = readb(socket->base + EXCA_REGS_BASE + offset); base 66 drivers/pcmcia/vrc4173_cardu.c val |= (u16)readb(socket->base + EXCA_REGS_BASE + offset + 1) << 8; base 73 drivers/pcmcia/vrc4173_cardu.c writeb(val, socket->base + EXCA_REGS_BASE + offset); base 78 drivers/pcmcia/vrc4173_cardu.c writeb((u8)val, socket->base + EXCA_REGS_BASE + offset); base 79 drivers/pcmcia/vrc4173_cardu.c writeb((u8)(val >> 8), socket->base + EXCA_REGS_BASE + offset + 1); base 84 drivers/pcmcia/vrc4173_cardu.c return readl(socket->base + CARDBUS_SOCKET_REGS_BASE + offset); base 89 drivers/pcmcia/vrc4173_cardu.c writel(val, socket->base + CARDBUS_SOCKET_REGS_BASE + offset); base 383 drivers/pcmcia/vrc4173_cardu.c static void cardu_proc_setup(unsigned int sock, struct proc_dir_entry *base) base 500 drivers/pcmcia/vrc4173_cardu.c socket->base = ioremap(start, len); base 501 drivers/pcmcia/vrc4173_cardu.c if (socket->base == NULL) { base 527 drivers/pcmcia/vrc4173_cardu.c iounmap(socket->base); base 528 drivers/pcmcia/vrc4173_cardu.c socket->base = NULL; base 236 drivers/pcmcia/vrc4173_cardu.h void *base; base 86 drivers/pcmcia/yenta_socket.c u32 val = readl(socket->base + reg); base 94 drivers/pcmcia/yenta_socket.c writel(val, socket->base + reg); base 95 drivers/pcmcia/yenta_socket.c readl(socket->base + reg); /* avoid problems with PCI write posting */ base 142 drivers/pcmcia/yenta_socket.c u8 val = readb(socket->base + 0x800 + reg); base 150 drivers/pcmcia/yenta_socket.c val = readb(socket->base + 0x800 + reg); base 151 drivers/pcmcia/yenta_socket.c val |= readb(socket->base + 0x800 + reg + 1) << 8; base 159 drivers/pcmcia/yenta_socket.c writeb(val, socket->base + 0x800 + reg); base 160 drivers/pcmcia/yenta_socket.c readb(socket->base + 0x800 + reg); /* PCI write posting... */ base 166 drivers/pcmcia/yenta_socket.c writeb(val, socket->base + 0x800 + reg); base 167 drivers/pcmcia/yenta_socket.c writeb(val >> 8, socket->base + 0x800 + reg + 1); base 170 drivers/pcmcia/yenta_socket.c readb(socket->base + 0x800 + reg); base 171 drivers/pcmcia/yenta_socket.c readb(socket->base + 0x800 + reg + 1); base 806 drivers/pcmcia/yenta_socket.c iounmap(sock->base); base 1200 drivers/pcmcia/yenta_socket.c socket->base = ioremap(pci_resource_start(dev, 0), 0x1000); base 1201 drivers/pcmcia/yenta_socket.c if (!socket->base) { base 1277 drivers/pcmcia/yenta_socket.c iounmap(socket->base); base 117 drivers/pcmcia/yenta_socket.h void __iomem *base; base 100 drivers/perf/arm-cci.c void __iomem *base; base 719 drivers/perf/arm-cci.c return readl_relaxed(cci_pmu->base + base 726 drivers/perf/arm-cci.c writel_relaxed(value, cci_pmu->base + base 1654 drivers/perf/arm-cci.c cci_pmu->base = devm_ioremap_resource(&pdev->dev, res); base 1655 drivers/perf/arm-cci.c if (IS_ERR(cci_pmu->base)) base 131 drivers/perf/arm-ccn.c void __iomem *base; base 147 drivers/perf/arm-ccn.c void __iomem *base; base 171 drivers/perf/arm-ccn.c void __iomem *base; base 855 drivers/perf/arm-ccn.c res = readq(ccn->dt.base + CCN_DT_PMCCNTR); base 858 drivers/perf/arm-ccn.c writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ); base 859 drivers/perf/arm-ccn.c while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1)) base 861 drivers/perf/arm-ccn.c writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); base 862 drivers/perf/arm-ccn.c res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff; base 864 drivers/perf/arm-ccn.c res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR); base 867 drivers/perf/arm-ccn.c res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx)); base 913 drivers/perf/arm-ccn.c val = readl(xp->base + CCN_XP_DT_CONFIG); base 917 drivers/perf/arm-ccn.c writel(val, xp->base + CCN_XP_DT_CONFIG); base 964 drivers/perf/arm-ccn.c val = readl(source->base + CCN_XP_DT_INTERFACE_SEL); base 977 drivers/perf/arm-ccn.c writel(val, source->base + CCN_XP_DT_INTERFACE_SEL); base 980 drivers/perf/arm-ccn.c writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp)); base 982 drivers/perf/arm-ccn.c source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4); base 983 drivers/perf/arm-ccn.c writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp)); base 985 drivers/perf/arm-ccn.c source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4); base 988 drivers/perf/arm-ccn.c writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp)); base 990 drivers/perf/arm-ccn.c source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4); base 991 drivers/perf/arm-ccn.c writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp)); base 993 drivers/perf/arm-ccn.c source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4); base 1010 drivers/perf/arm-ccn.c val = readl(source->base + CCN_XP_PMU_EVENT_SEL); base 1014 drivers/perf/arm-ccn.c writel(val, source->base + CCN_XP_PMU_EVENT_SEL); base 1046 drivers/perf/arm-ccn.c val = readl(source->base + CCN_HNF_PMU_EVENT_SEL); base 1051 drivers/perf/arm-ccn.c writel(val, source->base + CCN_HNF_PMU_EVENT_SEL); base 1073 drivers/perf/arm-ccn.c val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); base 1077 drivers/perf/arm-ccn.c writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); base 1148 drivers/perf/arm-ccn.c u32 val = readl(ccn->dt.base + CCN_DT_PMCR); base 1150 drivers/perf/arm-ccn.c writel(val, ccn->dt.base + CCN_DT_PMCR); base 1157 drivers/perf/arm-ccn.c u32 val = readl(ccn->dt.base + CCN_DT_PMCR); base 1159 drivers/perf/arm-ccn.c writel(val, ccn->dt.base + CCN_DT_PMCR); base 1164 drivers/perf/arm-ccn.c u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR); base 1170 drivers/perf/arm-ccn.c writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR); base 1232 drivers/perf/arm-ccn.c ccn->dt.base = ccn->base + CCN_REGION_SIZE; base 1234 drivers/perf/arm-ccn.c writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR); base 1235 drivers/perf/arm-ccn.c writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL); base 1237 drivers/perf/arm-ccn.c ccn->dt.base + CCN_DT_PMCR); base 1238 drivers/perf/arm-ccn.c writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); base 1240 drivers/perf/arm-ccn.c writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG); base 1246 drivers/perf/arm-ccn.c ccn->xp[i].base + CCN_XP_DT_CONTROL); base 1322 drivers/perf/arm-ccn.c writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); base 1323 drivers/perf/arm-ccn.c writel(0, ccn->dt.base + CCN_DT_PMCR); base 1336 drivers/perf/arm-ccn.c writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); base 1337 drivers/perf/arm-ccn.c writel(0, ccn->dt.base + CCN_DT_PMCR); base 1344 drivers/perf/arm-ccn.c void __iomem *base, u32 type, u32 id)) base 1350 drivers/perf/arm-ccn.c void __iomem *base; base 1353 drivers/perf/arm-ccn.c val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 + base 1358 drivers/perf/arm-ccn.c base = ccn->base + region * CCN_REGION_SIZE; base 1359 drivers/perf/arm-ccn.c val = readl(base + CCN_ALL_OLY_ID); base 1365 drivers/perf/arm-ccn.c err = callback(ccn, region, base, type, id); base 1374 drivers/perf/arm-ccn.c void __iomem *base, u32 type, u32 id) base 1386 drivers/perf/arm-ccn.c void __iomem *base, u32 type, u32 id) base 1413 drivers/perf/arm-ccn.c component->base = base; base 1429 drivers/perf/arm-ccn.c ccn->base + CCN_MN_ERRINT_STATUS); base 1444 drivers/perf/arm-ccn.c err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0); base 1452 drivers/perf/arm-ccn.c err_sig_val[i] = readl(ccn->base + base 1461 drivers/perf/arm-ccn.c ccn->base + CCN_MN_ERRINT_STATUS); base 1481 drivers/perf/arm-ccn.c ccn->base = devm_ioremap_resource(ccn->dev, res); base 1482 drivers/perf/arm-ccn.c if (IS_ERR(ccn->base)) base 1483 drivers/perf/arm-ccn.c return PTR_ERR(ccn->base); base 1492 drivers/perf/arm-ccn.c ccn->base + CCN_MN_ERRINT_STATUS); base 1493 drivers/perf/arm-ccn.c if (readl(ccn->base + CCN_MN_ERRINT_STATUS) & base 1497 drivers/perf/arm-ccn.c ccn->base + CCN_MN_ERRINT_STATUS); base 47 drivers/perf/arm_spe_pmu.c void *base; base 352 drivers/perf/arm_spe_pmu.c memset(buf->base + head, ARM_SPE_BUF_PAD_BYTE, len); base 478 drivers/perf/arm_spe_pmu.c u64 base, limit; base 498 drivers/perf/arm_spe_pmu.c limit += (u64)buf->base; base 499 drivers/perf/arm_spe_pmu.c base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf); base 500 drivers/perf/arm_spe_pmu.c write_sysreg_s(base, SYS_PMBPTR_EL1); base 511 drivers/perf/arm_spe_pmu.c offset = read_sysreg_s(SYS_PMBPTR_EL1) - (u64)buf->base; base 851 drivers/perf/arm_spe_pmu.c buf->base = vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL); base 852 drivers/perf/arm_spe_pmu.c if (!buf->base) base 872 drivers/perf/arm_spe_pmu.c vunmap(buf->base); base 70 drivers/perf/fsl_imx8_ddr_perf.c void __iomem *base; base 244 drivers/perf/fsl_imx8_ddr_perf.c void __iomem *base = pmu->base; base 251 drivers/perf/fsl_imx8_ddr_perf.c base += ddr_perf_is_enhanced_filtered(event) ? COUNTER_DPCR1 : base 253 drivers/perf/fsl_imx8_ddr_perf.c return readl_relaxed(base + counter * 4); base 335 drivers/perf/fsl_imx8_ddr_perf.c writel(0, pmu->base + reg); base 338 drivers/perf/fsl_imx8_ddr_perf.c writel(val, pmu->base + reg); base 341 drivers/perf/fsl_imx8_ddr_perf.c val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; base 342 drivers/perf/fsl_imx8_ddr_perf.c writel(val, pmu->base + reg); base 379 drivers/perf/fsl_imx8_ddr_perf.c writel(cfg1, pmu->base + COUNTER_DPCR1); base 449 drivers/perf/fsl_imx8_ddr_perf.c static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, base 466 drivers/perf/fsl_imx8_ddr_perf.c .base = base, base 542 drivers/perf/fsl_imx8_ddr_perf.c void __iomem *base; base 548 drivers/perf/fsl_imx8_ddr_perf.c base = devm_platform_ioremap_resource(pdev, 0); base 549 drivers/perf/fsl_imx8_ddr_perf.c if (IS_ERR(base)) base 550 drivers/perf/fsl_imx8_ddr_perf.c return PTR_ERR(base); base 558 drivers/perf/fsl_imx8_ddr_perf.c num = ddr_perf_init(pmu, base, &pdev->dev); base 75 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c return readl(ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx)); base 89 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx)); base 106 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_PERF_CTRL); base 108 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_PERF_CTRL); base 116 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_PERF_CTRL); base 118 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_PERF_CTRL); base 127 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL); base 129 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL); base 138 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL); base 140 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL); base 165 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_INT_MASK); base 167 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_INT_MASK); base 176 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c val = readl(ddrc_pmu->base + DDRC_INT_MASK); base 178 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel(val, ddrc_pmu->base + DDRC_INT_MASK); base 189 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c overflown = readl(ddrc_pmu->base + DDRC_INT_STATUS); base 199 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c writel((1 << idx), ddrc_pmu->base + DDRC_INT_CLEAR); base 267 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c ddrc_pmu->base = devm_ioremap_resource(&pdev->dev, res); base 268 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c if (IS_ERR(ddrc_pmu->base)) { base 270 drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c return PTR_ERR(ddrc_pmu->base); base 61 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c return readq(hha_pmu->base + hisi_hha_pmu_get_counter_offset(idx)); base 75 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writeq(val, hha_pmu->base + hisi_hha_pmu_get_counter_offset(idx)); base 95 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + reg); base 98 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + reg); base 109 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_PERF_CTRL); base 111 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_PERF_CTRL); base 122 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_PERF_CTRL); base 124 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_PERF_CTRL); base 133 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_EVENT_CTRL); base 135 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_EVENT_CTRL); base 144 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_EVENT_CTRL); base 146 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_EVENT_CTRL); base 155 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_INT_MASK); base 157 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_INT_MASK); base 166 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + HHA_INT_MASK); base 168 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + HHA_INT_MASK); base 179 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c overflown = readl(hha_pmu->base + HHA_INT_STATUS); base 189 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel((1 << idx), hha_pmu->base + HHA_INT_CLEAR); base 260 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c hha_pmu->base = devm_ioremap_resource(&pdev->dev, res); base 261 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c if (IS_ERR(hha_pmu->base)) { base 263 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c return PTR_ERR(hha_pmu->base); base 60 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c return readq(l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(idx)); base 74 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writeq(val, l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(idx)); base 94 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + reg); base 97 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + reg); base 108 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_PERF_CTRL); base 110 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_PERF_CTRL); base 121 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_PERF_CTRL); base 123 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_PERF_CTRL); base 132 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_EVENT_CTRL); base 134 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_EVENT_CTRL); base 143 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_EVENT_CTRL); base 145 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_EVENT_CTRL); base 153 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_INT_MASK); base 156 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_INT_MASK); base 164 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + L3C_INT_MASK); base 167 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + L3C_INT_MASK); base 178 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c overflown = readl(l3c_pmu->base + L3C_INT_STATUS); base 188 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel((1 << idx), l3c_pmu->base + L3C_INT_CLEAR); base 263 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c l3c_pmu->base = devm_ioremap_resource(&pdev->dev, res); base 264 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c if (IS_ERR(l3c_pmu->base)) { base 266 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c return PTR_ERR(l3c_pmu->base); base 70 drivers/perf/hisilicon/hisi_uncore_pmu.h void __iomem *base; base 75 drivers/perf/thunderx2_pmu.c void __iomem *base; base 250 drivers/perf/thunderx2_pmu.c hwc->config_base = (unsigned long)tx2_pmu->base base 252 drivers/perf/thunderx2_pmu.c hwc->event_base = (unsigned long)tx2_pmu->base base 261 drivers/perf/thunderx2_pmu.c hwc->config_base = (unsigned long)tx2_pmu->base base 264 drivers/perf/thunderx2_pmu.c hwc->event_base = (unsigned long)tx2_pmu->base base 614 drivers/perf/thunderx2_pmu.c void __iomem *base; base 638 drivers/perf/thunderx2_pmu.c base = devm_ioremap_resource(dev, &res); base 639 drivers/perf/thunderx2_pmu.c if (IS_ERR(base)) { base 650 drivers/perf/thunderx2_pmu.c tx2_pmu->base = base; base 125 drivers/phy/allwinner/phy-sun4i-usb.c void __iomem *base; base 164 drivers/phy/allwinner/phy-sun4i-usb.c iscr = readl(data->base + REG_ISCR); base 167 drivers/phy/allwinner/phy-sun4i-usb.c writel(iscr, data->base + REG_ISCR); base 195 drivers/phy/allwinner/phy-sun4i-usb.c void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset; base 293 drivers/phy/allwinner/phy-sun4i-usb.c val = readl(data->base + data->cfg->phyctl_offset); base 296 drivers/phy/allwinner/phy-sun4i-usb.c writel(val, data->base + data->cfg->phyctl_offset); base 342 drivers/phy/allwinner/phy-sun4i-usb.c void __iomem *phyctl = data->base + base 532 drivers/phy/allwinner/phy-sun4i-usb.c regval = readl(data->base + REG_PHY_OTGCTL); base 540 drivers/phy/allwinner/phy-sun4i-usb.c writel(regval, data->base + REG_PHY_OTGCTL); base 702 drivers/phy/allwinner/phy-sun4i-usb.c data->base = devm_ioremap_resource(dev, res); base 703 drivers/phy/allwinner/phy-sun4i-usb.c if (IS_ERR(data->base)) base 704 drivers/phy/allwinner/phy-sun4i-usb.c return PTR_ERR(data->base); base 274 drivers/phy/amlogic/phy-meson-g12a-usb2.c void __iomem *base; base 285 drivers/phy/amlogic/phy-meson-g12a-usb2.c base = devm_ioremap_resource(dev, res); base 286 drivers/phy/amlogic/phy-meson-g12a-usb2.c if (IS_ERR(base)) base 287 drivers/phy/amlogic/phy-meson-g12a-usb2.c return PTR_ERR(base); base 289 drivers/phy/amlogic/phy-meson-g12a-usb2.c priv->regmap = devm_regmap_init_mmio(dev, base, base 339 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c void __iomem *base; base 347 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c base = devm_ioremap_resource(dev, res); base 348 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c if (IS_ERR(base)) base 349 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c return PTR_ERR(base); base 351 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c priv->regmap = devm_regmap_init_mmio(dev, base, base 236 drivers/phy/amlogic/phy-meson-gxl-usb2.c void __iomem *base; base 246 drivers/phy/amlogic/phy-meson-gxl-usb2.c base = devm_ioremap_resource(dev, res); base 247 drivers/phy/amlogic/phy-meson-gxl-usb2.c if (IS_ERR(base)) base 248 drivers/phy/amlogic/phy-meson-gxl-usb2.c return PTR_ERR(base); base 253 drivers/phy/amlogic/phy-meson-gxl-usb2.c priv->regmap = devm_regmap_init_mmio(dev, base, base 213 drivers/phy/amlogic/phy-meson-gxl-usb3.c void __iomem *base; base 221 drivers/phy/amlogic/phy-meson-gxl-usb3.c base = devm_ioremap_resource(dev, res); base 222 drivers/phy/amlogic/phy-meson-gxl-usb3.c if (IS_ERR(base)) base 223 drivers/phy/amlogic/phy-meson-gxl-usb3.c return PTR_ERR(base); base 225 drivers/phy/amlogic/phy-meson-gxl-usb3.c priv->regmap = devm_regmap_init_mmio(dev, base, base 54 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c void __iomem *base; base 83 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c val = readl(core->base + PCIE_CFG_OFFSET); base 85 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c writel(val, core->base + PCIE_CFG_OFFSET); base 92 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c val = readl(core->base + PCIE_CFG_OFFSET); base 94 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c writel(val, core->base + PCIE_CFG_OFFSET); base 145 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c core->base = devm_ioremap_resource(dev, res); base 146 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c if (IS_ERR(core->base)) base 147 drivers/phy/broadcom/phy-bcm-cygnus-pcie.c return PTR_ERR(core->base); base 64 drivers/phy/broadcom/phy-bcm-sr-pcie.c void __iomem *base; base 130 drivers/phy/broadcom/phy-bcm-sr-pcie.c pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET); base 231 drivers/phy/broadcom/phy-bcm-sr-pcie.c core->base = devm_ioremap_resource(core->dev, res); base 232 drivers/phy/broadcom/phy-bcm-sr-pcie.c if (IS_ERR(core->base)) base 233 drivers/phy/broadcom/phy-bcm-sr-pcie.c return PTR_ERR(core->base); base 226 drivers/phy/broadcom/phy-brcm-sata.c void __iomem *base = brcm_sata_pcb_base(port); base 232 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp); base 235 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2, base 247 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3, base 256 drivers/phy/broadcom/phy-brcm-sata.c void __iomem *base = brcm_sata_pcb_base(port); base 277 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, reg, ~tmp, tmp); base 278 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, reg, ~tmp, tmp); base 299 drivers/phy/broadcom/phy-brcm-sata.c void __iomem *base = brcm_sata_pcb_base(port); base 309 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val); base 314 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val); base 318 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); base 320 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); base 322 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); base 326 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE, base 339 drivers/phy/broadcom/phy-brcm-sata.c val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, base 361 drivers/phy/broadcom/phy-brcm-sata.c void __iomem *base = priv->phy_base; base 378 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val); base 384 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val); base 387 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2, base 391 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL, base 395 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, base 398 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, base 401 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, base 407 drivers/phy/broadcom/phy-brcm-sata.c val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, base 436 drivers/phy/broadcom/phy-brcm-sata.c void __iomem *base = priv->phy_base; base 441 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); base 443 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); base 445 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); base 449 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val); base 454 drivers/phy/broadcom/phy-brcm-sata.c val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, base 469 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL0, base 477 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val); base 481 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val); base 488 drivers/phy/broadcom/phy-brcm-sata.c void __iomem *base = brcm_sata_pcb_base(port); base 493 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873); base 495 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000); base 497 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, base 501 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, base 505 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0, base 508 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0, base 512 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32); base 514 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa); base 516 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64); base 522 drivers/phy/broadcom/phy-brcm-sata.c tmp = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, base 572 drivers/phy/broadcom/phy-brcm-sata.c void __iomem *base = brcm_sata_pcb_base(port); base 575 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1, base 129 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_CTRL_REG(base, reg) ((void *)base + USB_CTRL_##reg) base 130 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_XHCI_EC_REG(base, reg) ((void *)base + USB_XHCI_EC_##reg) base 143 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_CTRL_SET(base, reg, field) \ base 144 drivers/phy/broadcom/phy-brcm-usb-init.c usb_ctrl_set(USB_CTRL_REG(base, reg), \ base 146 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_CTRL_UNSET(base, reg, field) \ base 147 drivers/phy/broadcom/phy-brcm-usb-init.c usb_ctrl_unset(USB_CTRL_REG(base, reg), \ base 105 drivers/phy/cadence/phy-cadence-dp.c void __iomem *base; /* DPTX registers base */ base 138 drivers/phy/cadence/phy-cadence-dp.c writel(0x0003, cdns_phy->base + PHY_AUX_CTRL); /* enable AUX */ base 188 drivers/phy/cadence/phy-cadence-dp.c cdns_phy->base + PHY_RESET); base 191 drivers/phy/cadence/phy-cadence-dp.c writel(0x0001, cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN); base 210 drivers/phy/cadence/phy-cadence-dp.c ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_CMN_READY, reg, base 376 drivers/phy/cadence/phy-cadence-dp.c ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN_ACK, base 403 drivers/phy/cadence/phy-cadence-dp.c writel(write_val1, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ); base 405 drivers/phy/cadence/phy-cadence-dp.c ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK, base 412 drivers/phy/cadence/phy-cadence-dp.c writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ); base 415 drivers/phy/cadence/phy-cadence-dp.c writel(write_val2, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ); base 417 drivers/phy/cadence/phy-cadence-dp.c ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK, base 424 drivers/phy/cadence/phy-cadence-dp.c writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ); base 436 drivers/phy/cadence/phy-cadence-dp.c read_val = readl(cdns_phy->base + offset); base 438 drivers/phy/cadence/phy-cadence-dp.c start_bit))), cdns_phy->base + offset); base 463 drivers/phy/cadence/phy-cadence-dp.c cdns_phy->base = devm_ioremap_resource(&pdev->dev, regs); base 464 drivers/phy/cadence/phy-cadence-dp.c if (IS_ERR(cdns_phy->base)) base 465 drivers/phy/cadence/phy-cadence-dp.c return PTR_ERR(cdns_phy->base); base 91 drivers/phy/cadence/phy-cadence-sierra.c void __iomem *base; base 120 drivers/phy/cadence/phy-cadence-sierra.c writel(vals[j].val, phy->base + base 182 drivers/phy/cadence/phy-cadence-sierra.c sp->base = devm_ioremap_resource(dev, res); base 183 drivers/phy/cadence/phy-cadence-sierra.c if (IS_ERR(sp->base)) { base 185 drivers/phy/cadence/phy-cadence-sierra.c return PTR_ERR(sp->base); base 222 drivers/phy/cadence/phy-cadence-sierra.c if (sp->init_data->id_value != readl(sp->base)) { base 270 drivers/phy/cadence/phy-cadence-sierra.c writel(2, sp->base + SIERRA_PHY_PLL_CFG); base 439 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c void __iomem *base; base 453 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c base = devm_ioremap_resource(dev, res); base 454 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c if (IS_ERR(base)) base 455 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c return PTR_ERR(base); base 457 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 27 drivers/phy/freescale/phy-fsl-imx8mq-usb.c void __iomem *base; base 36 drivers/phy/freescale/phy-fsl-imx8mq-usb.c value = readl(imx_phy->base + PHY_CTRL1); base 40 drivers/phy/freescale/phy-fsl-imx8mq-usb.c writel(value, imx_phy->base + PHY_CTRL1); base 42 drivers/phy/freescale/phy-fsl-imx8mq-usb.c value = readl(imx_phy->base + PHY_CTRL0); base 44 drivers/phy/freescale/phy-fsl-imx8mq-usb.c writel(value, imx_phy->base + PHY_CTRL0); base 46 drivers/phy/freescale/phy-fsl-imx8mq-usb.c value = readl(imx_phy->base + PHY_CTRL2); base 48 drivers/phy/freescale/phy-fsl-imx8mq-usb.c writel(value, imx_phy->base + PHY_CTRL2); base 50 drivers/phy/freescale/phy-fsl-imx8mq-usb.c value = readl(imx_phy->base + PHY_CTRL1); base 52 drivers/phy/freescale/phy-fsl-imx8mq-usb.c writel(value, imx_phy->base + PHY_CTRL1); base 104 drivers/phy/freescale/phy-fsl-imx8mq-usb.c imx_phy->base = devm_ioremap_resource(dev, res); base 105 drivers/phy/freescale/phy-fsl-imx8mq-usb.c if (IS_ERR(imx_phy->base)) base 106 drivers/phy/freescale/phy-fsl-imx8mq-usb.c return PTR_ERR(imx_phy->base); base 51 drivers/phy/hisilicon/phy-hix5hd2-sata.c void __iomem *base; base 81 drivers/phy/hisilicon/phy-hix5hd2-sata.c val = readl_relaxed(priv->base + SATA_PHY0_CTLL); base 85 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PHY0_CTLL); base 88 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PHY0_CTLL); base 90 drivers/phy/hisilicon/phy-hix5hd2-sata.c val = readl_relaxed(priv->base + SATA_PORT_PHYCTL1); base 95 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PORT_PHYCTL1); base 97 drivers/phy/hisilicon/phy-hix5hd2-sata.c val = readl_relaxed(priv->base + SATA_PORT_PHYCTL2); base 102 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PORT_PHYCTL2); base 105 drivers/phy/hisilicon/phy-hix5hd2-sata.c val = readl_relaxed(priv->base + SATA_PORT_PHYCTL); base 110 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); base 117 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); base 123 drivers/phy/hisilicon/phy-hix5hd2-sata.c writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); base 149 drivers/phy/hisilicon/phy-hix5hd2-sata.c priv->base = devm_ioremap(dev, res->start, resource_size(res)); base 150 drivers/phy/hisilicon/phy-hix5hd2-sata.c if (!priv->base) base 406 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c void __iomem *base; base 414 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c base = devm_ioremap_resource(dev, res); base 415 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c if (IS_ERR(base)) base 416 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c return PTR_ERR(base); base 418 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c priv->phy_regmap = devm_regmap_init_mmio(dev, base, ®map_config); base 35 drivers/phy/marvell/phy-armada38x-comphy.c void __iomem *base; base 43 drivers/phy/marvell/phy-armada38x-comphy.c void __iomem *base; base 62 drivers/phy/marvell/phy-armada38x-comphy.c val = readl_relaxed(lane->base + offset) & ~mask; base 63 drivers/phy/marvell/phy-armada38x-comphy.c writel(val | value, lane->base + offset); base 81 drivers/phy/marvell/phy-armada38x-comphy.c ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val, base 152 drivers/phy/marvell/phy-armada38x-comphy.c val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR); base 171 drivers/phy/marvell/phy-armada38x-comphy.c void __iomem *base; base 178 drivers/phy/marvell/phy-armada38x-comphy.c base = devm_ioremap_resource(&pdev->dev, res); base 179 drivers/phy/marvell/phy-armada38x-comphy.c if (IS_ERR(base)) base 180 drivers/phy/marvell/phy-armada38x-comphy.c return PTR_ERR(base); base 183 drivers/phy/marvell/phy-armada38x-comphy.c priv->base = base; base 197 drivers/phy/marvell/phy-armada38x-comphy.c if (val >= MAX_A38X_COMPHY || priv->lane[val].base) { base 208 drivers/phy/marvell/phy-armada38x-comphy.c priv->lane[val].base = base + 0x28 * val; base 57 drivers/phy/marvell/phy-berlin-sata.c void __iomem *base; base 84 drivers/phy/marvell/phy-berlin-sata.c void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); base 92 drivers/phy/marvell/phy-berlin-sata.c writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR); base 93 drivers/phy/marvell/phy-berlin-sata.c regval = readl(priv->base + HOST_VSA_DATA); base 95 drivers/phy/marvell/phy-berlin-sata.c writel(regval, priv->base + HOST_VSA_DATA); base 98 drivers/phy/marvell/phy-berlin-sata.c writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR); base 99 drivers/phy/marvell/phy-berlin-sata.c regval = readl(priv->base + HOST_VSA_DATA); base 101 drivers/phy/marvell/phy-berlin-sata.c writel(regval, priv->base + HOST_VSA_DATA); base 144 drivers/phy/marvell/phy-berlin-sata.c writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR); base 145 drivers/phy/marvell/phy-berlin-sata.c regval = readl(priv->base + HOST_VSA_DATA); base 147 drivers/phy/marvell/phy-berlin-sata.c writel(regval, priv->base + HOST_VSA_DATA); base 206 drivers/phy/marvell/phy-berlin-sata.c priv->base = devm_ioremap(dev, res->start, resource_size(res)); base 207 drivers/phy/marvell/phy-berlin-sata.c if (!priv->base) base 109 drivers/phy/marvell/phy-berlin-usb.c void __iomem *base; base 121 drivers/phy/marvell/phy-berlin-usb.c priv->base + USB_PHY_PLL); base 123 drivers/phy/marvell/phy-berlin-usb.c CLK_BLK_EN, priv->base + USB_PHY_PLL_CONTROL); base 125 drivers/phy/marvell/phy-berlin-usb.c priv->base + USB_PHY_ANALOG); base 128 drivers/phy/marvell/phy-berlin-usb.c INTPL_CUR_30, priv->base + USB_PHY_RX_CTRL); base 130 drivers/phy/marvell/phy-berlin-usb.c writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1); base 132 drivers/phy/marvell/phy-berlin-usb.c priv->base + USB_PHY_TX_CTRL0); base 135 drivers/phy/marvell/phy-berlin-usb.c EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0); base 138 drivers/phy/marvell/phy-berlin-usb.c priv->base + USB_PHY_TX_CTRL0); base 140 drivers/phy/marvell/phy-berlin-usb.c FS_DRV_EN_MASK(0xd), priv->base + USB_PHY_TX_CTRL2); base 177 drivers/phy/marvell/phy-berlin-usb.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 178 drivers/phy/marvell/phy-berlin-usb.c if (IS_ERR(priv->base)) base 179 drivers/phy/marvell/phy-berlin-usb.c return PTR_ERR(priv->base); base 255 drivers/phy/marvell/phy-mvebu-cp110-comphy.c void __iomem *base; base 335 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); base 372 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); base 397 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 401 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 404 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 407 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 418 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); base 422 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); base 425 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); base 430 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); base 432 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); base 435 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); base 446 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); base 450 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); base 453 drivers/phy/marvell/phy-mvebu-cp110-comphy.c readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), base 463 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 465 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 468 drivers/phy/marvell/phy-mvebu-cp110-comphy.c readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), base 474 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 476 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 492 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); base 495 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); base 497 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); base 499 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); base 506 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); base 509 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); base 525 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); base 528 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); base 530 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); base 532 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); base 534 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); base 536 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); base 538 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); base 540 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); base 542 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); base 545 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); base 547 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); base 553 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); base 555 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); base 557 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); base 559 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); base 562 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); base 578 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); base 581 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); base 583 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); base 585 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); base 588 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); base 590 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); base 592 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); base 594 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); base 597 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); base 599 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); base 601 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); base 606 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); base 608 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); base 611 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); base 613 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); base 616 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); base 619 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); base 623 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); base 625 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); base 627 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); base 629 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); base 639 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); base 641 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); base 643 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); base 645 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); base 648 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); base 650 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); base 652 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); base 655 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); base 658 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); base 661 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); base 663 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); base 665 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); base 668 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); base 670 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); base 672 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); base 674 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); base 677 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); base 679 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); base 682 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); base 684 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DME(lane->id)); base 686 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DME(lane->id)); base 688 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); base 690 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); base 692 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_SP_CALIB(lane->id)); base 696 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); base 698 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); base 701 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); base 704 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); base 746 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 748 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 862 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 866 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); base 998 drivers/phy/marvell/phy-mvebu-cp110-comphy.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 999 drivers/phy/marvell/phy-mvebu-cp110-comphy.c if (IS_ERR(priv->base)) base 1000 drivers/phy/marvell/phy-mvebu-cp110-comphy.c return PTR_ERR(priv->base); base 17 drivers/phy/marvell/phy-mvebu-sata.c void __iomem *base; base 36 drivers/phy/marvell/phy-mvebu-sata.c reg = readl(priv->base + SATA_PHY_MODE_2); base 39 drivers/phy/marvell/phy-mvebu-sata.c writel(reg , priv->base + SATA_PHY_MODE_2); base 42 drivers/phy/marvell/phy-mvebu-sata.c reg = readl(priv->base + SATA_IF_CTRL); base 44 drivers/phy/marvell/phy-mvebu-sata.c writel(reg, priv->base + SATA_IF_CTRL); base 59 drivers/phy/marvell/phy-mvebu-sata.c reg = readl(priv->base + SATA_PHY_MODE_2); base 62 drivers/phy/marvell/phy-mvebu-sata.c writel(reg, priv->base + SATA_PHY_MODE_2); base 65 drivers/phy/marvell/phy-mvebu-sata.c reg = readl(priv->base + SATA_IF_CTRL); base 67 drivers/phy/marvell/phy-mvebu-sata.c writel(reg, priv->base + SATA_IF_CTRL); base 92 drivers/phy/marvell/phy-mvebu-sata.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 93 drivers/phy/marvell/phy-mvebu-sata.c if (IS_ERR(priv->base)) base 94 drivers/phy/marvell/phy-mvebu-sata.c return PTR_ERR(priv->base); base 43 drivers/phy/marvell/phy-pxa-28nm-hsic.c void __iomem *base; base 62 drivers/phy/marvell/phy-pxa-28nm-hsic.c void __iomem *base = mv_phy->base; base 70 drivers/phy/marvell/phy-pxa-28nm-hsic.c base + PHY_28NM_HSIC_PLL_CTRL01); base 73 drivers/phy/marvell/phy-pxa-28nm-hsic.c writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) | base 75 drivers/phy/marvell/phy-pxa-28nm-hsic.c base + PHY_28NM_HSIC_PLL_CTRL2); base 78 drivers/phy/marvell/phy-pxa-28nm-hsic.c if (!wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2, base 92 drivers/phy/marvell/phy-pxa-28nm-hsic.c void __iomem *base = mv_phy->base; base 95 drivers/phy/marvell/phy-pxa-28nm-hsic.c reg = readl(base + PHY_28NM_HSIC_CTRL); base 99 drivers/phy/marvell/phy-pxa-28nm-hsic.c writel(reg, base + PHY_28NM_HSIC_CTRL); base 111 drivers/phy/marvell/phy-pxa-28nm-hsic.c if (!wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL, base 118 drivers/phy/marvell/phy-pxa-28nm-hsic.c if (!wait_for_reg(base + PHY_28NM_HSIC_INT, base 130 drivers/phy/marvell/phy-pxa-28nm-hsic.c void __iomem *base = mv_phy->base; base 132 drivers/phy/marvell/phy-pxa-28nm-hsic.c writel(readl(base + PHY_28NM_HSIC_CTRL) & ~PHY_28NM_HSIC_S2H_HSIC_EN, base 133 drivers/phy/marvell/phy-pxa-28nm-hsic.c base + PHY_28NM_HSIC_CTRL); base 141 drivers/phy/marvell/phy-pxa-28nm-hsic.c void __iomem *base = mv_phy->base; base 144 drivers/phy/marvell/phy-pxa-28nm-hsic.c writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) & base 146 drivers/phy/marvell/phy-pxa-28nm-hsic.c base + PHY_28NM_HSIC_PLL_CTRL2); base 180 drivers/phy/marvell/phy-pxa-28nm-hsic.c mv_phy->base = devm_ioremap_resource(&pdev->dev, r); base 181 drivers/phy/marvell/phy-pxa-28nm-hsic.c if (IS_ERR(mv_phy->base)) base 182 drivers/phy/marvell/phy-pxa-28nm-hsic.c return PTR_ERR(mv_phy->base); base 137 drivers/phy/marvell/phy-pxa-28nm-usb2.c void __iomem *base; base 156 drivers/phy/marvell/phy-pxa-28nm-usb2.c void __iomem *base = mv_phy->base; base 163 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_PLL_REG0) & base 170 drivers/phy/marvell/phy-pxa-28nm-usb2.c base + PHY_28NM_PLL_REG0); base 173 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_PLL_REG1); base 175 drivers/phy/marvell/phy-pxa-28nm-usb2.c base + PHY_28NM_PLL_REG1); base 178 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_TX_REG0) & ~PHY_28NM_TX_AMP_MASK; base 181 drivers/phy/marvell/phy-pxa-28nm-usb2.c base + PHY_28NM_TX_REG0); base 184 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_RX_REG0) & ~PHY_28NM_RX_SQ_THRESH_MASK; base 186 drivers/phy/marvell/phy-pxa-28nm-usb2.c base + PHY_28NM_RX_REG0); base 189 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_DIG_REG0) & base 195 drivers/phy/marvell/phy-pxa-28nm-usb2.c base + PHY_28NM_DIG_REG0); base 198 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_OTG_REG) | PHY_28NM_OTG_PU_OTG; base 199 drivers/phy/marvell/phy-pxa-28nm-usb2.c writel(reg & ~PHY_28NM_OTG_CONTROL_BY_PIN, base + PHY_28NM_OTG_REG); base 211 drivers/phy/marvell/phy-pxa-28nm-usb2.c if (!wait_for_reg(base + PHY_28NM_CAL_REG, base 218 drivers/phy/marvell/phy-pxa-28nm-usb2.c if (!wait_for_reg(base + PHY_28NM_RX_REG1, base 225 drivers/phy/marvell/phy-pxa-28nm-usb2.c if (!wait_for_reg(base + PHY_28NM_PLL_REG0, base 241 drivers/phy/marvell/phy-pxa-28nm-usb2.c void __iomem *base = mv_phy->base; base 243 drivers/phy/marvell/phy-pxa-28nm-usb2.c writel(readl(base + PHY_28NM_CTRL_REG3) | base 246 drivers/phy/marvell/phy-pxa-28nm-usb2.c base + PHY_28NM_CTRL_REG3); base 254 drivers/phy/marvell/phy-pxa-28nm-usb2.c void __iomem *base = mv_phy->base; base 256 drivers/phy/marvell/phy-pxa-28nm-usb2.c writel(readl(base + PHY_28NM_CTRL_REG3) | base 259 drivers/phy/marvell/phy-pxa-28nm-usb2.c base + PHY_28NM_CTRL_REG3); base 267 drivers/phy/marvell/phy-pxa-28nm-usb2.c void __iomem *base = mv_phy->base; base 270 drivers/phy/marvell/phy-pxa-28nm-usb2.c val = readw(base + PHY_28NM_PLL_REG1); base 272 drivers/phy/marvell/phy-pxa-28nm-usb2.c writew(val, base + PHY_28NM_PLL_REG1); base 275 drivers/phy/marvell/phy-pxa-28nm-usb2.c val = readw(base + PHY_28NM_TX_REG0); base 277 drivers/phy/marvell/phy-pxa-28nm-usb2.c writew(val, base + PHY_28NM_TX_REG0); base 280 drivers/phy/marvell/phy-pxa-28nm-usb2.c val = readw(base + PHY_28NM_OTG_REG); base 282 drivers/phy/marvell/phy-pxa-28nm-usb2.c writew(val, base + PHY_28NM_OTG_REG); base 315 drivers/phy/marvell/phy-pxa-28nm-usb2.c mv_phy->base = devm_ioremap_resource(&pdev->dev, r); base 316 drivers/phy/marvell/phy-pxa-28nm-usb2.c if (IS_ERR(mv_phy->base)) base 317 drivers/phy/marvell/phy-pxa-28nm-usb2.c return PTR_ERR(mv_phy->base); base 117 drivers/phy/marvell/phy-pxa-usb.c void __iomem *base; base 125 drivers/phy/marvell/phy-pxa-usb.c static unsigned int u2o_get(void __iomem *base, unsigned int offset) base 127 drivers/phy/marvell/phy-pxa-usb.c return readl_relaxed(base + offset); base 130 drivers/phy/marvell/phy-pxa-usb.c static void u2o_set(void __iomem *base, unsigned int offset, base 135 drivers/phy/marvell/phy-pxa-usb.c reg = readl_relaxed(base + offset); base 137 drivers/phy/marvell/phy-pxa-usb.c writel_relaxed(reg, base + offset); base 138 drivers/phy/marvell/phy-pxa-usb.c readl_relaxed(base + offset); base 141 drivers/phy/marvell/phy-pxa-usb.c static void u2o_clear(void __iomem *base, unsigned int offset, base 146 drivers/phy/marvell/phy-pxa-usb.c reg = readl_relaxed(base + offset); base 148 drivers/phy/marvell/phy-pxa-usb.c writel_relaxed(reg, base + offset); base 149 drivers/phy/marvell/phy-pxa-usb.c readl_relaxed(base + offset); base 152 drivers/phy/marvell/phy-pxa-usb.c static void u2o_write(void __iomem *base, unsigned int offset, base 155 drivers/phy/marvell/phy-pxa-usb.c writel_relaxed(value, base + offset); base 156 drivers/phy/marvell/phy-pxa-usb.c readl_relaxed(base + offset); base 162 drivers/phy/marvell/phy-pxa-usb.c void __iomem *base = pxa_usb_phy->base; base 169 drivers/phy/marvell/phy-pxa-usb.c u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT) base 173 drivers/phy/marvell/phy-pxa-usb.c u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); base 174 drivers/phy/marvell/phy-pxa-usb.c u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); base 177 drivers/phy/marvell/phy-pxa-usb.c u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK base 182 drivers/phy/marvell/phy-pxa-usb.c u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT base 188 drivers/phy/marvell/phy-pxa-usb.c u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK base 192 drivers/phy/marvell/phy-pxa-usb.c u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT base 197 drivers/phy/marvell/phy-pxa-usb.c u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK base 199 drivers/phy/marvell/phy-pxa-usb.c u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT base 208 drivers/phy/marvell/phy-pxa-usb.c u2o_write(base, UTMI_IVREF, 0x4bf); base 213 drivers/phy/marvell/phy-pxa-usb.c u2o_set(base, UTMI_PLL, VCOCAL_START); base 215 drivers/phy/marvell/phy-pxa-usb.c u2o_clear(base, UTMI_PLL, VCOCAL_START); base 219 drivers/phy/marvell/phy-pxa-usb.c u2o_set(base, UTMI_TX, REG_RCAL_START); base 221 drivers/phy/marvell/phy-pxa-usb.c u2o_clear(base, UTMI_TX, REG_RCAL_START); base 226 drivers/phy/marvell/phy-pxa-usb.c while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) { base 231 drivers/phy/marvell/phy-pxa-usb.c u2o_get(base, UTMI_PLL)); base 237 drivers/phy/marvell/phy-pxa-usb.c u2o_set(base, UTMI_RESERVE, 1 << 5); base 239 drivers/phy/marvell/phy-pxa-usb.c u2o_write(base, UTMI_OTG_ADDON, 1); base 249 drivers/phy/marvell/phy-pxa-usb.c void __iomem *base = pxa_usb_phy->base; base 254 drivers/phy/marvell/phy-pxa-usb.c u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON); base 256 drivers/phy/marvell/phy-pxa-usb.c u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN); base 257 drivers/phy/marvell/phy-pxa-usb.c u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN); base 258 drivers/phy/marvell/phy-pxa-usb.c u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN); base 259 drivers/phy/marvell/phy-pxa-usb.c u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); base 260 drivers/phy/marvell/phy-pxa-usb.c u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); base 305 drivers/phy/marvell/phy-pxa-usb.c pxa_usb_phy->base = devm_ioremap_resource(dev, resource); base 306 drivers/phy/marvell/phy-pxa-usb.c if (IS_ERR(pxa_usb_phy->base)) { base 308 drivers/phy/marvell/phy-pxa-usb.c return PTR_ERR(pxa_usb_phy->base); base 92 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c void __iomem *base = phy->mmio; base 96 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x01, base + SATA_PHY_SER_CTRL); base 97 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0); base 102 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); base 103 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); base 104 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); base 105 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); base 106 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2); base 109 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG); base 110 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG); base 112 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0); base 113 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8); base 114 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9); base 115 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10); base 116 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11); base 118 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0); base 119 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1); base 120 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2); base 121 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3); base 122 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4); base 124 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0); base 125 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1); base 126 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2); base 127 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3); base 129 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0); base 130 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1); base 132 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG); base 136 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG); base 137 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2); base 140 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK); base 147 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL); base 154 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL); base 161 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); base 162 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); base 163 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); base 165 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1); base 166 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0); base 167 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1); base 168 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2); base 169 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0); base 170 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3); base 171 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); base 173 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL); base 174 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x43, base + SATA_PHY_ALIGNP); base 175 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x04, base + SATA_PHY_OOB_TERM); base 177 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x01, base + SATA_PHY_EQUAL); base 178 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0); base 179 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1); base 187 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c void __iomem *base = phy->mmio; base 190 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0); base 191 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1); base 194 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG); base 41 drivers/phy/qualcomm/phy-qcom-pcie2.c void __iomem *base; base 75 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); base 77 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); base 82 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); base 84 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); base 87 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); base 89 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); base 94 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); base 96 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); base 99 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1); base 102 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1); base 104 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2); base 107 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2); base 110 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1); base 113 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1); base 115 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2); base 118 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2); base 120 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3); base 123 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3); base 126 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_CONFIGBITS); base 129 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_CONFIGBITS); base 132 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3); base 135 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3); base 138 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE20_PARF_PCS_CTRL); base 140 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE20_PARF_PCS_CTRL); base 143 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); base 145 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); base 163 drivers/phy/qualcomm/phy-qcom-pcie2.c ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val, base 177 drivers/phy/qualcomm/phy-qcom-pcie2.c val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); base 179 drivers/phy/qualcomm/phy-qcom-pcie2.c writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); base 265 drivers/phy/qualcomm/phy-qcom-pcie2.c qphy->base = devm_ioremap_resource(dev, res); base 266 drivers/phy/qualcomm/phy-qcom-pcie2.c if (IS_ERR(qphy->base)) base 267 drivers/phy/qualcomm/phy-qcom-pcie2.c return PTR_ERR(qphy->base); base 1004 drivers/phy/qualcomm/phy-qcom-qmp.c static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) base 1008 drivers/phy/qualcomm/phy-qcom-qmp.c reg = readl(base + offset); base 1010 drivers/phy/qualcomm/phy-qcom-qmp.c writel(reg, base + offset); base 1013 drivers/phy/qualcomm/phy-qcom-qmp.c readl(base + offset); base 1016 drivers/phy/qualcomm/phy-qcom-qmp.c static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) base 1020 drivers/phy/qualcomm/phy-qcom-qmp.c reg = readl(base + offset); base 1022 drivers/phy/qualcomm/phy-qcom-qmp.c writel(reg, base + offset); base 1025 drivers/phy/qualcomm/phy-qcom-qmp.c readl(base + offset); base 1279 drivers/phy/qualcomm/phy-qcom-qmp.c static void qcom_qmp_phy_configure(void __iomem *base, base 1292 drivers/phy/qualcomm/phy-qcom-qmp.c writel(t->val, base + regs[t->offset]); base 1294 drivers/phy/qualcomm/phy-qcom-qmp.c writel(t->val, base + t->offset); base 2018 drivers/phy/qualcomm/phy-qcom-qmp.c void __iomem *base; base 2035 drivers/phy/qualcomm/phy-qcom-qmp.c base = devm_ioremap_resource(dev, res); base 2036 drivers/phy/qualcomm/phy-qcom-qmp.c if (IS_ERR(base)) base 2037 drivers/phy/qualcomm/phy-qcom-qmp.c return PTR_ERR(base); base 2040 drivers/phy/qualcomm/phy-qcom-qmp.c qmp->serdes = base; base 2046 drivers/phy/qualcomm/phy-qcom-qmp.c base = devm_ioremap_resource(dev, res); base 2047 drivers/phy/qualcomm/phy-qcom-qmp.c if (IS_ERR(base)) base 2048 drivers/phy/qualcomm/phy-qcom-qmp.c return PTR_ERR(base); base 2050 drivers/phy/qualcomm/phy-qcom-qmp.c qmp->dp_com = base; base 311 drivers/phy/qualcomm/phy-qcom-qusb2.c void __iomem *base; base 337 drivers/phy/qualcomm/phy-qcom-qusb2.c static inline void qusb2_write_mask(void __iomem *base, u32 offset, base 342 drivers/phy/qualcomm/phy-qcom-qusb2.c reg = readl(base + offset); base 345 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(reg, base + offset); base 348 drivers/phy/qualcomm/phy-qcom-qusb2.c readl(base + offset); base 351 drivers/phy/qualcomm/phy-qcom-qusb2.c static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) base 355 drivers/phy/qualcomm/phy-qcom-qusb2.c reg = readl(base + offset); base 357 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(reg, base + offset); base 360 drivers/phy/qualcomm/phy-qcom-qusb2.c readl(base + offset); base 363 drivers/phy/qualcomm/phy-qcom-qusb2.c static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val) base 367 drivers/phy/qualcomm/phy-qcom-qusb2.c reg = readl(base + offset); base 369 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(reg, base + offset); base 372 drivers/phy/qualcomm/phy-qcom-qusb2.c readl(base + offset); base 376 drivers/phy/qualcomm/phy-qcom-qusb2.c void qcom_qusb2_phy_configure(void __iomem *base, base 384 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(tbl[i].val, base + regs[tbl[i].offset]); base 386 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(tbl[i].val, base + tbl[i].offset); base 399 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, base 404 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], base 409 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], base 416 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_setbits(qphy->base, base 420 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_clrbits(qphy->base, base 456 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], base 460 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], base 513 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); base 517 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_setbits(qphy->base, base 525 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], base 528 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], base 574 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); base 578 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_clrbits(qphy->base, base 638 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], base 643 drivers/phy/qualcomm/phy-qcom-qusb2.c val = readl(qphy->base + QUSB2PHY_PLL_TEST); base 646 drivers/phy/qualcomm/phy-qcom-qusb2.c qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, base 656 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], base 704 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(val, qphy->base + QUSB2PHY_PLL_TEST); base 707 drivers/phy/qualcomm/phy-qcom-qusb2.c readl(qphy->base + QUSB2PHY_PLL_TEST); base 713 drivers/phy/qualcomm/phy-qcom-qusb2.c val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); base 744 drivers/phy/qualcomm/phy-qcom-qusb2.c qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], base 805 drivers/phy/qualcomm/phy-qcom-qusb2.c qphy->base = devm_ioremap_resource(dev, res); base 806 drivers/phy/qualcomm/phy-qcom-qusb2.c if (IS_ERR(qphy->base)) base 807 drivers/phy/qualcomm/phy-qcom-qusb2.c return PTR_ERR(qphy->base); base 57 drivers/phy/ralink/phy-ralink-usb.c void __iomem *base; base 63 drivers/phy/ralink/phy-ralink-usb.c writel(val, phy->base + reg); base 68 drivers/phy/ralink/phy-ralink-usb.c return readl(phy->base + reg); base 115 drivers/phy/ralink/phy-ralink-usb.c if (phy->base) base 187 drivers/phy/ralink/phy-ralink-usb.c phy->base = NULL; base 198 drivers/phy/ralink/phy-ralink-usb.c phy->base = devm_ioremap_resource(&pdev->dev, res); base 199 drivers/phy/ralink/phy-ralink-usb.c if (IS_ERR(phy->base)) { base 201 drivers/phy/ralink/phy-ralink-usb.c return PTR_ERR(phy->base); base 64 drivers/phy/renesas/phy-rcar-gen2.c void __iomem *base; base 97 drivers/phy/renesas/phy-rcar-gen2.c ugctrl2 = readl(drv->base + USBHS_UGCTRL2); base 100 drivers/phy/renesas/phy-rcar-gen2.c writel(ugctrl2, drv->base + USBHS_UGCTRL2); base 121 drivers/phy/renesas/phy-rcar-gen2.c void __iomem *base = drv->base; base 133 drivers/phy/renesas/phy-rcar-gen2.c value = readl(base + USBHS_UGCTRL); base 135 drivers/phy/renesas/phy-rcar-gen2.c writel(value, base + USBHS_UGCTRL); base 137 drivers/phy/renesas/phy-rcar-gen2.c value = readw(base + USBHS_LPSTS); base 139 drivers/phy/renesas/phy-rcar-gen2.c writew(value, base + USBHS_LPSTS); base 142 drivers/phy/renesas/phy-rcar-gen2.c value = readl(base + USBHS_UGSTS); base 144 drivers/phy/renesas/phy-rcar-gen2.c value = readl(base + USBHS_UGCTRL); base 146 drivers/phy/renesas/phy-rcar-gen2.c writel(value, base + USBHS_UGCTRL); base 165 drivers/phy/renesas/phy-rcar-gen2.c void __iomem *base = drv->base; base 176 drivers/phy/renesas/phy-rcar-gen2.c value = readl(base + USBHS_UGCTRL); base 178 drivers/phy/renesas/phy-rcar-gen2.c writel(value, base + USBHS_UGCTRL); base 180 drivers/phy/renesas/phy-rcar-gen2.c value = readw(base + USBHS_LPSTS); base 182 drivers/phy/renesas/phy-rcar-gen2.c writew(value, base + USBHS_LPSTS); base 184 drivers/phy/renesas/phy-rcar-gen2.c value = readl(base + USBHS_UGCTRL); base 186 drivers/phy/renesas/phy-rcar-gen2.c writel(value, base + USBHS_UGCTRL); base 197 drivers/phy/renesas/phy-rcar-gen2.c void __iomem *base = drv->base; base 204 drivers/phy/renesas/phy-rcar-gen2.c value = readl(base + USBHS_UGCTRL); base 206 drivers/phy/renesas/phy-rcar-gen2.c writel(value, base + USBHS_UGCTRL); base 212 drivers/phy/renesas/phy-rcar-gen2.c value = readw(base + USBHS_LPSTS); base 214 drivers/phy/renesas/phy-rcar-gen2.c writew(value, base + USBHS_LPSTS); base 226 drivers/phy/renesas/phy-rcar-gen2.c void __iomem *base = drv->base; base 233 drivers/phy/renesas/phy-rcar-gen2.c value = readw(base + USBHS_LPSTS); base 235 drivers/phy/renesas/phy-rcar-gen2.c writew(value, base + USBHS_LPSTS); base 238 drivers/phy/renesas/phy-rcar-gen2.c value = readl(base + USBHS_UGCTRL); base 240 drivers/phy/renesas/phy-rcar-gen2.c writel(value, base + USBHS_UGCTRL); base 343 drivers/phy/renesas/phy-rcar-gen2.c void __iomem *base; base 361 drivers/phy/renesas/phy-rcar-gen2.c base = devm_ioremap_resource(dev, res); base 362 drivers/phy/renesas/phy-rcar-gen2.c if (IS_ERR(base)) base 363 drivers/phy/renesas/phy-rcar-gen2.c return PTR_ERR(base); base 372 drivers/phy/renesas/phy-rcar-gen2.c drv->base = base; base 25 drivers/phy/renesas/phy-rcar-gen3-pcie.c void __iomem *base; base 32 drivers/phy/renesas/phy-rcar-gen3-pcie.c void __iomem *base = phy->base; base 38 drivers/phy/renesas/phy-rcar-gen3-pcie.c value = readl(base + reg); base 41 drivers/phy/renesas/phy-rcar-gen3-pcie.c writel(value, base + reg); base 80 drivers/phy/renesas/phy-rcar-gen3-pcie.c void __iomem *base; base 90 drivers/phy/renesas/phy-rcar-gen3-pcie.c base = devm_ioremap_resource(dev, res); base 91 drivers/phy/renesas/phy-rcar-gen3-pcie.c if (IS_ERR(base)) base 92 drivers/phy/renesas/phy-rcar-gen3-pcie.c return PTR_ERR(base); base 100 drivers/phy/renesas/phy-rcar-gen3-pcie.c phy->base = base; base 106 drivers/phy/renesas/phy-rcar-gen3-usb2.c void __iomem *base; base 146 drivers/phy/renesas/phy-rcar-gen3-usb2.c void __iomem *usb2_base = ch->base; base 159 drivers/phy/renesas/phy-rcar-gen3-usb2.c void __iomem *usb2_base = ch->base; base 173 drivers/phy/renesas/phy-rcar-gen3-usb2.c void __iomem *usb2_base = ch->base; base 186 drivers/phy/renesas/phy-rcar-gen3-usb2.c void __iomem *usb2_base = ch->base; base 218 drivers/phy/renesas/phy-rcar-gen3-usb2.c void __iomem *usb2_base = ch->base; base 254 drivers/phy/renesas/phy-rcar-gen3-usb2.c return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG); base 267 drivers/phy/renesas/phy-rcar-gen3-usb2.c return !(readl(ch->base + USB2_COMMCTRL) & USB2_COMMCTRL_OTG_PERI); base 369 drivers/phy/renesas/phy-rcar-gen3-usb2.c void __iomem *usb2_base = ch->base; base 396 drivers/phy/renesas/phy-rcar-gen3-usb2.c void __iomem *usb2_base = channel->base; base 422 drivers/phy/renesas/phy-rcar-gen3-usb2.c void __iomem *usb2_base = channel->base; base 443 drivers/phy/renesas/phy-rcar-gen3-usb2.c void __iomem *usb2_base = channel->base; base 509 drivers/phy/renesas/phy-rcar-gen3-usb2.c void __iomem *usb2_base = ch->base; base 613 drivers/phy/renesas/phy-rcar-gen3-usb2.c channel->base = devm_ioremap_resource(dev, res); base 614 drivers/phy/renesas/phy-rcar-gen3-usb2.c if (IS_ERR(channel->base)) base 615 drivers/phy/renesas/phy-rcar-gen3-usb2.c return PTR_ERR(channel->base); base 50 drivers/phy/renesas/phy-rcar-gen3-usb3.c void __iomem *base; base 65 drivers/phy/renesas/phy-rcar-gen3-usb3.c writew(val, r->base + USB30_CLKSET1); base 88 drivers/phy/renesas/phy-rcar-gen3-usb3.c writew(val, r->base + USB30_SSC_SET); base 97 drivers/phy/renesas/phy-rcar-gen3-usb3.c r->base + USB30_CLKSET0); base 98 drivers/phy/renesas/phy-rcar-gen3-usb3.c writew(PHY_ENABLE_RESET_EN, r->base + USB30_PHY_ENABLE); base 115 drivers/phy/renesas/phy-rcar-gen3-usb3.c writew(VBUS_EN_VBUS_EN, r->base + USB30_VBUS_EN); base 150 drivers/phy/renesas/phy-rcar-gen3-usb3.c r->base = devm_ioremap_resource(dev, res); base 151 drivers/phy/renesas/phy-rcar-gen3-usb3.c if (IS_ERR(r->base)) base 152 drivers/phy/renesas/phy-rcar-gen3-usb3.c return PTR_ERR(r->base); base 230 drivers/phy/rockchip/phy-rockchip-inno-usb2.c static inline int property_enable(struct regmap *base, base 239 drivers/phy/rockchip/phy-rockchip-inno-usb2.c return regmap_write(base, reg->offset, val); base 242 drivers/phy/rockchip/phy-rockchip-inno-usb2.c static inline bool property_enabled(struct regmap *base, base 249 drivers/phy/rockchip/phy-rockchip-inno-usb2.c ret = regmap_read(base, reg->offset, &orig); base 261 drivers/phy/rockchip/phy-rockchip-inno-usb2.c struct regmap *base = get_reg_base(rphy); base 265 drivers/phy/rockchip/phy-rockchip-inno-usb2.c if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) { base 266 drivers/phy/rockchip/phy-rockchip-inno-usb2.c ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true); base 281 drivers/phy/rockchip/phy-rockchip-inno-usb2.c struct regmap *base = get_reg_base(rphy); base 284 drivers/phy/rockchip/phy-rockchip-inno-usb2.c property_enable(base, &rphy->phy_cfg->clkout_ctl, false); base 291 drivers/phy/rockchip/phy-rockchip-inno-usb2.c struct regmap *base = get_reg_base(rphy); base 293 drivers/phy/rockchip/phy-rockchip-inno-usb2.c return property_enabled(base, &rphy->phy_cfg->clkout_ctl); base 457 drivers/phy/rockchip/phy-rockchip-inno-usb2.c struct regmap *base = get_reg_base(rphy); base 469 drivers/phy/rockchip/phy-rockchip-inno-usb2.c ret = property_enable(base, &rport->port_cfg->phy_sus, false); base 484 drivers/phy/rockchip/phy-rockchip-inno-usb2.c struct regmap *base = get_reg_base(rphy); base 492 drivers/phy/rockchip/phy-rockchip-inno-usb2.c ret = property_enable(base, &rport->port_cfg->phy_sus, true); base 656 drivers/phy/rockchip/phy-rockchip-inno-usb2.c struct regmap *base = get_reg_base(rphy); base 658 drivers/phy/rockchip/phy-rockchip-inno-usb2.c property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); base 659 drivers/phy/rockchip/phy-rockchip-inno-usb2.c property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); base 665 drivers/phy/rockchip/phy-rockchip-inno-usb2.c struct regmap *base = get_reg_base(rphy); base 667 drivers/phy/rockchip/phy-rockchip-inno-usb2.c property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); base 668 drivers/phy/rockchip/phy-rockchip-inno-usb2.c property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); base 674 drivers/phy/rockchip/phy-rockchip-inno-usb2.c struct regmap *base = get_reg_base(rphy); base 676 drivers/phy/rockchip/phy-rockchip-inno-usb2.c property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); base 677 drivers/phy/rockchip/phy-rockchip-inno-usb2.c property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); base 689 drivers/phy/rockchip/phy-rockchip-inno-usb2.c struct regmap *base = get_reg_base(rphy); base 700 drivers/phy/rockchip/phy-rockchip-inno-usb2.c property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); base 764 drivers/phy/rockchip/phy-rockchip-inno-usb2.c property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); base 373 drivers/phy/rockchip/phy-rockchip-typec.c void __iomem *base; base 465 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x830, tcphy->base + PMA_CMN_CTRL1); base 471 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x90, tcphy->base + XCVR_DIAG_LANE_FCM_EN_MGN(i)); base 472 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x960, tcphy->base + TX_RCVDET_EN_TMR(i)); base 473 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x30, tcphy->base + TX_RCVDET_ST_TMR(i)); base 476 drivers/phy/rockchip/phy-rockchip-typec.c rdata = readl(tcphy->base + CMN_DIAG_HSCLK_SEL); base 479 drivers/phy/rockchip/phy-rockchip-typec.c writel(rdata, tcphy->base + CMN_DIAG_HSCLK_SEL); base 489 drivers/phy/rockchip/phy-rockchip-typec.c tcphy->base + usb3_pll_cfg[i].addr); base 498 drivers/phy/rockchip/phy-rockchip-typec.c tcphy->base + DP_CLK_CTL); base 502 drivers/phy/rockchip/phy-rockchip-typec.c writel(dp_pll_cfg[i].value, tcphy->base + dp_pll_cfg[i].addr); base 507 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x7799, tcphy->base + TX_PSC_A0(lane)); base 508 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x7798, tcphy->base + TX_PSC_A1(lane)); base 509 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x5098, tcphy->base + TX_PSC_A2(lane)); base 510 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x5098, tcphy->base + TX_PSC_A3(lane)); base 511 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); base 512 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); base 517 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); base 518 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xa6fd, tcphy->base + RX_PSC_A1(lane)); base 519 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xa410, tcphy->base + RX_PSC_A2(lane)); base 520 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x2410, tcphy->base + RX_PSC_A3(lane)); base 521 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x23ff, tcphy->base + RX_PSC_CAL(lane)); base 522 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x13, tcphy->base + RX_SIGDET_HL_FILT_TMR(lane)); base 523 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x03e7, tcphy->base + RX_REE_CTRL_DATA_MASK(lane)); base 524 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x1004, tcphy->base + RX_DIAG_SIGDET_TUNE(lane)); base 525 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x2010, tcphy->base + RX_PSC_RDY(lane)); base 526 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xfb, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); base 533 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xbefc, tcphy->base + XCVR_PSM_RCTRL(lane)); base 534 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x6799, tcphy->base + TX_PSC_A0(lane)); base 535 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x6798, tcphy->base + TX_PSC_A1(lane)); base 536 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x98, tcphy->base + TX_PSC_A2(lane)); base 537 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x98, tcphy->base + TX_PSC_A3(lane)); base 539 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); base 540 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_001(lane)); base 541 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_010(lane)); base 542 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_011(lane)); base 543 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_100(lane)); base 544 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_101(lane)); base 545 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_110(lane)); base 546 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_111(lane)); base 547 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_CPOST_MULT_10(lane)); base 548 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_CPOST_MULT_01(lane)); base 549 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_CPOST_MULT_00(lane)); base 550 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_CPOST_MULT_11(lane)); base 552 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x128, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane)); base 553 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x400, tcphy->base + TX_DIAG_TX_DRV(lane)); base 555 drivers/phy/rockchip/phy-rockchip-typec.c rdata = readl(tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane)); base 557 drivers/phy/rockchip/phy-rockchip-typec.c writel(rdata, tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane)); base 580 drivers/phy/rockchip/phy-rockchip-typec.c tx_ana_ctrl_reg_1 = readl(tcphy->base + TX_ANA_CTRL_REG_1); base 585 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); base 601 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + CMN_TXPUCAL_CTRL); base 603 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + CMN_TXPDCAL_CTRL); base 605 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + CMN_TXPU_ADJ_CTRL); base 607 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + CMN_TXPD_ADJ_CTRL); base 612 drivers/phy/rockchip/phy-rockchip-typec.c tx_ana_ctrl_reg_1 = readl(tcphy->base + TX_ANA_CTRL_REG_1); base 614 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); base 617 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + TX_DIG_CTRL_REG_2); base 620 drivers/phy/rockchip/phy-rockchip-typec.c writel(val, tcphy->base + TX_DIG_CTRL_REG_2); base 629 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); base 633 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + PHY_DP_TX_CTL); base 637 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_2, tcphy->base + TX_ANA_CTRL_REG_2); base 640 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_2, tcphy->base + TX_ANA_CTRL_REG_2); base 642 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_ANA_CTRL_REG_3); base 645 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); base 648 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); base 650 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_ANA_CTRL_REG_5); base 656 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x1001, tcphy->base + TX_ANA_CTRL_REG_4); base 660 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); base 663 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); base 670 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_2, tcphy->base + TX_ANA_CTRL_REG_2); base 673 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_2, tcphy->base + TX_ANA_CTRL_REG_2); base 690 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); base 693 drivers/phy/rockchip/phy-rockchip-typec.c writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); base 700 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_ANA_CTRL_REG_4); base 703 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TXDA_COEFF_CALC_CTRL); base 706 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TXDA_CYA_AUXDA_CYA); base 717 drivers/phy/rockchip/phy-rockchip-typec.c val = readl(tcphy->base + TX_DIG_CTRL_REG_2); base 719 drivers/phy/rockchip/phy-rockchip-typec.c writel(val, tcphy->base + TX_DIG_CTRL_REG_2); base 752 drivers/phy/rockchip/phy-rockchip-typec.c writel(PIN_ASSIGN_C_E, tcphy->base + PMA_LANE_CFG); base 768 drivers/phy/rockchip/phy-rockchip-typec.c writel(PIN_ASSIGN_D_F, tcphy->base + PMA_LANE_CFG); base 771 drivers/phy/rockchip/phy-rockchip-typec.c writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL); base 775 drivers/phy/rockchip/phy-rockchip-typec.c ret = readx_poll_timeout(readl, tcphy->base + PMA_CMN_CTRL1, base 983 drivers/phy/rockchip/phy-rockchip-typec.c ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL, base 993 drivers/phy/rockchip/phy-rockchip-typec.c writel(DP_MODE_ENTER_A0, tcphy->base + DP_MODE_CTL); base 995 drivers/phy/rockchip/phy-rockchip-typec.c ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL, base 999 drivers/phy/rockchip/phy-rockchip-typec.c writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL); base 1025 drivers/phy/rockchip/phy-rockchip-typec.c writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL); base 1122 drivers/phy/rockchip/phy-rockchip-typec.c tcphy->base = devm_ioremap_resource(dev, res); base 1123 drivers/phy/rockchip/phy-rockchip-typec.c if (IS_ERR(tcphy->base)) base 1124 drivers/phy/rockchip/phy-rockchip-typec.c return PTR_ERR(tcphy->base); base 68 drivers/phy/rockchip/phy-rockchip-usb.c struct rockchip_usb_phy_base *base; base 85 drivers/phy/rockchip/phy-rockchip-usb.c return regmap_write(phy->base->reg_base, phy->reg_offset, val); base 125 drivers/phy/rockchip/phy-rockchip-usb.c ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val); base 202 drivers/phy/rockchip/phy-rockchip-usb.c static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base, base 211 drivers/phy/rockchip/phy-rockchip-usb.c rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL); base 215 drivers/phy/rockchip/phy-rockchip-usb.c rk_phy->base = base; base 219 drivers/phy/rockchip/phy-rockchip-usb.c dev_err(base->dev, "missing reg property in node %pOFn\n", base 236 drivers/phy/rockchip/phy-rockchip-usb.c while (base->pdata->phys[i].reg) { base 237 drivers/phy/rockchip/phy-rockchip-usb.c if (base->pdata->phys[i].reg == reg_offset) { base 238 drivers/phy/rockchip/phy-rockchip-usb.c init.name = base->pdata->phys[i].pll_name; base 245 drivers/phy/rockchip/phy-rockchip-usb.c dev_err(base->dev, "phy data not found\n"); base 249 drivers/phy/rockchip/phy-rockchip-usb.c if (enable_usb_uart && base->pdata->usb_uart_phy == i) { base 250 drivers/phy/rockchip/phy-rockchip-usb.c dev_dbg(base->dev, "phy%d used as uart output\n", i); base 267 drivers/phy/rockchip/phy-rockchip-usb.c rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw); base 279 drivers/phy/rockchip/phy-rockchip-usb.c err = devm_add_action_or_reset(base->dev, rockchip_usb_phy_action, base 284 drivers/phy/rockchip/phy-rockchip-usb.c rk_phy->phy = devm_phy_create(base->dev, child, &ops); base 286 drivers/phy/rockchip/phy-rockchip-usb.c dev_err(base->dev, "failed to create PHY\n"); base 73 drivers/phy/samsung/phy-exynos-pcie.c static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset) base 75 drivers/phy/samsung/phy-exynos-pcie.c writel(val, base + offset); base 78 drivers/phy/samsung/phy-exynos-pcie.c static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset) base 80 drivers/phy/samsung/phy-exynos-pcie.c return readl(base + offset); base 56 drivers/phy/samsung/phy-exynos5250-sata.c static int wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit, base 62 drivers/phy/samsung/phy-exynos5250-sata.c if ((readl(base + reg) & checkbit) == status) base 46 drivers/phy/socionext/phy-uniphier-pcie.c void __iomem *base; base 61 drivers/phy/socionext/phy-uniphier-pcie.c writel(data, priv->base + PCL_PHY_TEST_I); base 62 drivers/phy/socionext/phy-uniphier-pcie.c readl(priv->base + PCL_PHY_TEST_O); base 63 drivers/phy/socionext/phy-uniphier-pcie.c readl(priv->base + PCL_PHY_TEST_O); base 75 drivers/phy/socionext/phy-uniphier-pcie.c val = readl(priv->base + PCL_PHY_TEST_O); base 89 drivers/phy/socionext/phy-uniphier-pcie.c readl(priv->base + PCL_PHY_TEST_O); base 96 drivers/phy/socionext/phy-uniphier-pcie.c val = readl(priv->base + PCL_PHY_RESET); base 99 drivers/phy/socionext/phy-uniphier-pcie.c writel(val, priv->base + PCL_PHY_RESET); base 106 drivers/phy/socionext/phy-uniphier-pcie.c val = readl(priv->base + PCL_PHY_RESET); base 108 drivers/phy/socionext/phy-uniphier-pcie.c writel(val, priv->base + PCL_PHY_RESET); base 180 drivers/phy/socionext/phy-uniphier-pcie.c priv->base = devm_ioremap_resource(dev, res); base 181 drivers/phy/socionext/phy-uniphier-pcie.c if (IS_ERR(priv->base)) base 182 drivers/phy/socionext/phy-uniphier-pcie.c return PTR_ERR(priv->base); base 68 drivers/phy/socionext/phy-uniphier-usb3hs.c void __iomem *base; base 179 drivers/phy/socionext/phy-uniphier-usb3hs.c val = readl(priv->base + HSPHY_CFG1); base 183 drivers/phy/socionext/phy-uniphier-usb3hs.c writel(val, priv->base + HSPHY_CFG1); base 185 drivers/phy/socionext/phy-uniphier-usb3hs.c val = readl(priv->base + HSPHY_CFG1); base 187 drivers/phy/socionext/phy-uniphier-usb3hs.c writel(val, priv->base + HSPHY_CFG1); base 189 drivers/phy/socionext/phy-uniphier-usb3hs.c val = readl(priv->base + HSPHY_CFG1); base 193 drivers/phy/socionext/phy-uniphier-usb3hs.c writel(val, priv->base + HSPHY_CFG1); base 195 drivers/phy/socionext/phy-uniphier-usb3hs.c val = readl(priv->base + HSPHY_CFG1); base 197 drivers/phy/socionext/phy-uniphier-usb3hs.c writel(val, priv->base + HSPHY_CFG1); base 273 drivers/phy/socionext/phy-uniphier-usb3hs.c writel(config0, priv->base + HSPHY_CFG0); base 274 drivers/phy/socionext/phy-uniphier-usb3hs.c writel(config1, priv->base + HSPHY_CFG1); base 326 drivers/phy/socionext/phy-uniphier-usb3hs.c priv->base = devm_ioremap_resource(dev, res); base 327 drivers/phy/socionext/phy-uniphier-usb3hs.c if (IS_ERR(priv->base)) base 328 drivers/phy/socionext/phy-uniphier-usb3hs.c return PTR_ERR(priv->base); base 54 drivers/phy/socionext/phy-uniphier-usb3ss.c void __iomem *base; base 71 drivers/phy/socionext/phy-uniphier-usb3ss.c writel(data, priv->base + SSPHY_TESTI); base 72 drivers/phy/socionext/phy-uniphier-usb3ss.c readl(priv->base + SSPHY_TESTO); base 73 drivers/phy/socionext/phy-uniphier-usb3ss.c readl(priv->base + SSPHY_TESTO); base 87 drivers/phy/socionext/phy-uniphier-usb3ss.c val = readl(priv->base + SSPHY_TESTO); base 102 drivers/phy/socionext/phy-uniphier-usb3ss.c readl(priv->base + SSPHY_TESTO); base 232 drivers/phy/socionext/phy-uniphier-usb3ss.c priv->base = devm_ioremap_resource(dev, res); base 233 drivers/phy/socionext/phy-uniphier-usb3ss.c if (IS_ERR(priv->base)) base 234 drivers/phy/socionext/phy-uniphier-usb3ss.c return PTR_ERR(priv->base); base 204 drivers/phy/st/phy-miphy28lp.c void __iomem *base; base 366 drivers/phy/st/phy-miphy28lp.c void __iomem *base = miphy_phy->base; base 370 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); base 373 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_CONF_RESET); base 375 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); base 380 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_CONTROL); base 383 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_CONTROL); base 390 drivers/phy/st/phy-miphy28lp.c void __iomem *base = miphy_phy->base; base 394 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN); base 395 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); base 398 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1); base 399 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2); base 400 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3); base 401 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4); base 402 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL); base 404 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL); base 407 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_TX_CAL_MAN); base 414 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); base 417 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_CONF); base 418 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP); base 419 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA); base 420 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL); base 421 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL); base 424 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL); base 431 drivers/phy/st/phy-miphy28lp.c void __iomem *base = miphy_phy->base; base 438 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->bank, base + MIPHY_CONF); base 439 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->speed, base + MIPHY_SPEED); base 440 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); base 441 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); base 444 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); base 445 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); base 448 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); base 449 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); base 450 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); base 451 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); base 452 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3); base 458 drivers/phy/st/phy-miphy28lp.c void __iomem *base = miphy_phy->base; base 465 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->bank, base + MIPHY_CONF); base 466 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->speed, base + MIPHY_SPEED); base 467 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); base 468 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); base 471 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1); base 472 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); base 473 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); base 475 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN); base 478 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); base 479 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); base 480 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); base 481 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); base 492 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6); base 506 drivers/phy/st/phy-miphy28lp.c void __iomem *base = miphy_phy->base; base 510 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET); base 512 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); base 513 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); base 514 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); base 517 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); base 519 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_RESET); base 520 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); base 521 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); base 524 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_COMP_POSTP); base 534 drivers/phy/st/phy-miphy28lp.c void __iomem *base = miphy_phy->base; base 538 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); base 539 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_CONF_RESET); base 540 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET); base 543 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_RESET); base 545 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); base 546 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ); base 547 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); base 548 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); base 549 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_RESET); base 550 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); base 551 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_CONF); base 552 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1); base 553 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2); base 554 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_CONF); base 555 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); base 556 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS); base 557 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_CONF); base 562 drivers/phy/st/phy-miphy28lp.c void __iomem *base = miphy_phy->base; base 570 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(base + MIPHY_BOUNDARY_2); base 572 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_BOUNDARY_2); base 574 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(base + MIPHY_BOUNDARY_SEL); base 576 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); base 579 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_CONF); base 583 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); base 584 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3); base 585 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4); base 588 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); base 591 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); base 594 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); base 600 drivers/phy/st/phy-miphy28lp.c void __iomem *base = miphy_phy->base; base 608 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(base + MIPHY_BOUNDARY_2); base 610 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_BOUNDARY_2); base 612 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(base + MIPHY_BOUNDARY_SEL); base 614 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); base 617 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_CONF); base 620 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3); base 621 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); base 624 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); base 625 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); base 628 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); base 631 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); base 634 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); base 641 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP); base 646 drivers/phy/st/phy-miphy28lp.c void __iomem *base = miphy_phy->base; base 661 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); base 664 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_CONF_RESET); base 674 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL); base 676 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL); base 690 drivers/phy/st/phy-miphy28lp.c void __iomem *base = miphy_phy->base; base 704 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); base 707 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_CONF_RESET); base 727 drivers/phy/st/phy-miphy28lp.c void __iomem *base = miphy_phy->base; base 737 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_CONF); base 740 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_SPEED); base 743 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT); base 744 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1); base 745 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2); base 749 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); base 750 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP); base 751 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH); base 754 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL); base 755 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1); base 756 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL); base 759 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x02, base + MIPHY_COMP_POSTP); base 764 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); base 767 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1); base 768 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2); base 771 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2); base 774 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_CONF); base 777 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3); base 778 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4); base 781 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); base 782 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4); base 785 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); base 788 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1); base 791 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); base 794 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN); base 798 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); base 799 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1); base 800 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2); base 820 drivers/phy/st/phy-miphy28lp.c val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1); base 869 drivers/phy/st/phy-miphy28lp.c void __iomem **base) base 876 drivers/phy/st/phy-miphy28lp.c *base = devm_ioremap(dev, res.start, resource_size(&res)); base 877 drivers/phy/st/phy-miphy28lp.c if (!*base) { base 925 drivers/phy/st/phy-miphy28lp.c (!miphy_phy->base)) base 928 drivers/phy/st/phy-miphy28lp.c dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base); base 961 drivers/phy/st/phy-miphy28lp.c || (!miphy_phy->base) || (!miphy_phy->pipebase)) base 964 drivers/phy/st/phy-miphy28lp.c dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base); base 1004 drivers/phy/st/phy-miphy28lp.c if ((!miphy_phy->base) || (!miphy_phy->pipebase)) base 1007 drivers/phy/st/phy-miphy28lp.c dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base); base 1083 drivers/phy/st/phy-miphy28lp.c &miphy_phy->base); base 68 drivers/phy/st/phy-stm32-usbphyc.c void __iomem *base; base 136 drivers/phy/st/phy-stm32-usbphyc.c writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL); base 158 drivers/phy/st/phy-stm32-usbphyc.c void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL; base 191 drivers/phy/st/phy-stm32-usbphyc.c void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL; base 260 drivers/phy/st/phy-stm32-usbphyc.c stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC, base 263 drivers/phy/st/phy-stm32-usbphyc.c stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC, base 326 drivers/phy/st/phy-stm32-usbphyc.c usbphyc->base = devm_ioremap_resource(dev, res); base 327 drivers/phy/st/phy-stm32-usbphyc.c if (IS_ERR(usbphyc->base)) base 328 drivers/phy/st/phy-stm32-usbphyc.c return PTR_ERR(usbphyc->base); base 419 drivers/phy/st/phy-stm32-usbphyc.c version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION); base 28 drivers/phy/tegra/phy-tegra194-p2u.c void __iomem *base; base 34 drivers/phy/tegra/phy-tegra194-p2u.c writel_relaxed(value, phy->base + reg); base 39 drivers/phy/tegra/phy-tegra194-p2u.c return readl_relaxed(phy->base + reg); base 82 drivers/phy/tegra/phy-tegra194-p2u.c phy->base = devm_ioremap_resource(dev, res); base 83 drivers/phy/tegra/phy-tegra194-p2u.c if (IS_ERR(phy->base)) base 84 drivers/phy/tegra/phy-tegra194-p2u.c return PTR_ERR(phy->base); base 214 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_padctl base; base 222 drivers/phy/tegra/xusb-tegra124.c return container_of(padctl, struct tegra124_xusb_padctl, base); base 300 drivers/phy/tegra/xusb-tegra124.c lane = port->base.lane; base 437 drivers/phy/tegra/xusb-tegra124.c INIT_LIST_HEAD(&usb2->base.list); base 438 drivers/phy/tegra/xusb-tegra124.c usb2->base.soc = &pad->soc->lanes[index]; base 439 drivers/phy/tegra/xusb-tegra124.c usb2->base.index = index; base 440 drivers/phy/tegra/xusb-tegra124.c usb2->base.pad = pad; base 441 drivers/phy/tegra/xusb-tegra124.c usb2->base.np = np; base 443 drivers/phy/tegra/xusb-tegra124.c err = tegra_xusb_lane_parse_dt(&usb2->base, np); base 449 drivers/phy/tegra/xusb-tegra124.c return &usb2->base; base 623 drivers/phy/tegra/xusb-tegra124.c pad = &usb2->base; base 686 drivers/phy/tegra/xusb-tegra124.c INIT_LIST_HEAD(&ulpi->base.list); base 687 drivers/phy/tegra/xusb-tegra124.c ulpi->base.soc = &pad->soc->lanes[index]; base 688 drivers/phy/tegra/xusb-tegra124.c ulpi->base.index = index; base 689 drivers/phy/tegra/xusb-tegra124.c ulpi->base.pad = pad; base 690 drivers/phy/tegra/xusb-tegra124.c ulpi->base.np = np; base 692 drivers/phy/tegra/xusb-tegra124.c err = tegra_xusb_lane_parse_dt(&ulpi->base, np); base 698 drivers/phy/tegra/xusb-tegra124.c return &ulpi->base; base 758 drivers/phy/tegra/xusb-tegra124.c pad = &ulpi->base; base 822 drivers/phy/tegra/xusb-tegra124.c INIT_LIST_HEAD(&hsic->base.list); base 823 drivers/phy/tegra/xusb-tegra124.c hsic->base.soc = &pad->soc->lanes[index]; base 824 drivers/phy/tegra/xusb-tegra124.c hsic->base.index = index; base 825 drivers/phy/tegra/xusb-tegra124.c hsic->base.pad = pad; base 826 drivers/phy/tegra/xusb-tegra124.c hsic->base.np = np; base 828 drivers/phy/tegra/xusb-tegra124.c err = tegra_xusb_lane_parse_dt(&hsic->base, np); base 834 drivers/phy/tegra/xusb-tegra124.c return &hsic->base; base 974 drivers/phy/tegra/xusb-tegra124.c pad = &hsic->base; base 1042 drivers/phy/tegra/xusb-tegra124.c INIT_LIST_HEAD(&pcie->base.list); base 1043 drivers/phy/tegra/xusb-tegra124.c pcie->base.soc = &pad->soc->lanes[index]; base 1044 drivers/phy/tegra/xusb-tegra124.c pcie->base.index = index; base 1045 drivers/phy/tegra/xusb-tegra124.c pcie->base.pad = pad; base 1046 drivers/phy/tegra/xusb-tegra124.c pcie->base.np = np; base 1048 drivers/phy/tegra/xusb-tegra124.c err = tegra_xusb_lane_parse_dt(&pcie->base, np); base 1054 drivers/phy/tegra/xusb-tegra124.c return &pcie->base; base 1162 drivers/phy/tegra/xusb-tegra124.c pad = &pcie->base; base 1220 drivers/phy/tegra/xusb-tegra124.c INIT_LIST_HEAD(&sata->base.list); base 1221 drivers/phy/tegra/xusb-tegra124.c sata->base.soc = &pad->soc->lanes[index]; base 1222 drivers/phy/tegra/xusb-tegra124.c sata->base.index = index; base 1223 drivers/phy/tegra/xusb-tegra124.c sata->base.pad = pad; base 1224 drivers/phy/tegra/xusb-tegra124.c sata->base.np = np; base 1226 drivers/phy/tegra/xusb-tegra124.c err = tegra_xusb_lane_parse_dt(&sata->base, np); base 1232 drivers/phy/tegra/xusb-tegra124.c return &sata->base; base 1358 drivers/phy/tegra/xusb-tegra124.c pad = &sata->base; base 1476 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = usb3->base.lane; base 1695 drivers/phy/tegra/xusb-tegra124.c padctl->base.dev = dev; base 1696 drivers/phy/tegra/xusb-tegra124.c padctl->base.soc = soc; base 1702 drivers/phy/tegra/xusb-tegra124.c return &padctl->base; base 130 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_padctl base; base 142 drivers/phy/tegra/xusb-tegra186.c return container_of(padctl, struct tegra186_xusb_padctl, base); base 157 drivers/phy/tegra/xusb-tegra186.c INIT_LIST_HEAD(&usb2->base.list); base 158 drivers/phy/tegra/xusb-tegra186.c usb2->base.soc = &pad->soc->lanes[index]; base 159 drivers/phy/tegra/xusb-tegra186.c usb2->base.index = index; base 160 drivers/phy/tegra/xusb-tegra186.c usb2->base.pad = pad; base 161 drivers/phy/tegra/xusb-tegra186.c usb2->base.np = np; base 163 drivers/phy/tegra/xusb-tegra186.c err = tegra_xusb_lane_parse_dt(&usb2->base, np); base 169 drivers/phy/tegra/xusb-tegra186.c return &usb2->base; base 459 drivers/phy/tegra/xusb-tegra186.c pad = &usb2->base; base 552 drivers/phy/tegra/xusb-tegra186.c INIT_LIST_HEAD(&usb3->base.list); base 553 drivers/phy/tegra/xusb-tegra186.c usb3->base.soc = &pad->soc->lanes[index]; base 554 drivers/phy/tegra/xusb-tegra186.c usb3->base.index = index; base 555 drivers/phy/tegra/xusb-tegra186.c usb3->base.pad = pad; base 556 drivers/phy/tegra/xusb-tegra186.c usb3->base.np = np; base 558 drivers/phy/tegra/xusb-tegra186.c err = tegra_xusb_lane_parse_dt(&usb3->base, np); base 564 drivers/phy/tegra/xusb-tegra186.c return &usb3->base; base 728 drivers/phy/tegra/xusb-tegra186.c pad = &usb3->base; base 792 drivers/phy/tegra/xusb-tegra186.c struct device *dev = padctl->base.dev; base 797 drivers/phy/tegra/xusb-tegra186.c count = padctl->base.soc->ports.usb2.count; base 846 drivers/phy/tegra/xusb-tegra186.c priv->base.dev = dev; base 847 drivers/phy/tegra/xusb-tegra186.c priv->base.soc = soc; base 853 drivers/phy/tegra/xusb-tegra186.c return &priv->base; base 232 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_padctl base; base 240 drivers/phy/tegra/xusb-tegra210.c return container_of(padctl, struct tegra210_xusb_padctl, base); base 873 drivers/phy/tegra/xusb-tegra210.c INIT_LIST_HEAD(&usb2->base.list); base 874 drivers/phy/tegra/xusb-tegra210.c usb2->base.soc = &pad->soc->lanes[index]; base 875 drivers/phy/tegra/xusb-tegra210.c usb2->base.index = index; base 876 drivers/phy/tegra/xusb-tegra210.c usb2->base.pad = pad; base 877 drivers/phy/tegra/xusb-tegra210.c usb2->base.np = np; base 879 drivers/phy/tegra/xusb-tegra210.c err = tegra_xusb_lane_parse_dt(&usb2->base, np); base 885 drivers/phy/tegra/xusb-tegra210.c return &usb2->base; base 1102 drivers/phy/tegra/xusb-tegra210.c pad = &usb2->base; base 1172 drivers/phy/tegra/xusb-tegra210.c INIT_LIST_HEAD(&hsic->base.list); base 1173 drivers/phy/tegra/xusb-tegra210.c hsic->base.soc = &pad->soc->lanes[index]; base 1174 drivers/phy/tegra/xusb-tegra210.c hsic->base.index = index; base 1175 drivers/phy/tegra/xusb-tegra210.c hsic->base.pad = pad; base 1176 drivers/phy/tegra/xusb-tegra210.c hsic->base.np = np; base 1178 drivers/phy/tegra/xusb-tegra210.c err = tegra_xusb_lane_parse_dt(&hsic->base, np); base 1184 drivers/phy/tegra/xusb-tegra210.c return &hsic->base; base 1356 drivers/phy/tegra/xusb-tegra210.c pad = &hsic->base; base 1434 drivers/phy/tegra/xusb-tegra210.c INIT_LIST_HEAD(&pcie->base.list); base 1435 drivers/phy/tegra/xusb-tegra210.c pcie->base.soc = &pad->soc->lanes[index]; base 1436 drivers/phy/tegra/xusb-tegra210.c pcie->base.index = index; base 1437 drivers/phy/tegra/xusb-tegra210.c pcie->base.pad = pad; base 1438 drivers/phy/tegra/xusb-tegra210.c pcie->base.np = np; base 1440 drivers/phy/tegra/xusb-tegra210.c err = tegra_xusb_lane_parse_dt(&pcie->base, np); base 1446 drivers/phy/tegra/xusb-tegra210.c return &pcie->base; base 1533 drivers/phy/tegra/xusb-tegra210.c pad = &pcie->base; base 1605 drivers/phy/tegra/xusb-tegra210.c INIT_LIST_HEAD(&sata->base.list); base 1606 drivers/phy/tegra/xusb-tegra210.c sata->base.soc = &pad->soc->lanes[index]; base 1607 drivers/phy/tegra/xusb-tegra210.c sata->base.index = index; base 1608 drivers/phy/tegra/xusb-tegra210.c sata->base.pad = pad; base 1609 drivers/phy/tegra/xusb-tegra210.c sata->base.np = np; base 1611 drivers/phy/tegra/xusb-tegra210.c err = tegra_xusb_lane_parse_dt(&sata->base, np); base 1617 drivers/phy/tegra/xusb-tegra210.c return &sata->base; base 1704 drivers/phy/tegra/xusb-tegra210.c pad = &sata->base; base 1807 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = usb3->base.lane; base 1991 drivers/phy/tegra/xusb-tegra210.c padctl->base.dev = dev; base 1992 drivers/phy/tegra/xusb-tegra210.c padctl->base.soc = soc; base 1998 drivers/phy/tegra/xusb-tegra210.c return &padctl->base; base 556 drivers/phy/tegra/xusb.c struct tegra_xusb_port *port = &usb2->base; base 600 drivers/phy/tegra/xusb.c err = tegra_xusb_port_init(&usb2->base, padctl, np, "usb2", index); base 604 drivers/phy/tegra/xusb.c usb2->base.ops = padctl->soc->ports.usb2.ops; base 606 drivers/phy/tegra/xusb.c usb2->base.lane = usb2->base.ops->map(&usb2->base); base 607 drivers/phy/tegra/xusb.c if (IS_ERR(usb2->base.lane)) { base 608 drivers/phy/tegra/xusb.c err = PTR_ERR(usb2->base.lane); base 614 drivers/phy/tegra/xusb.c tegra_xusb_port_unregister(&usb2->base); base 618 drivers/phy/tegra/xusb.c list_add_tail(&usb2->base.list, &padctl->ports); base 627 drivers/phy/tegra/xusb.c struct tegra_xusb_port *port = &ulpi->base; base 652 drivers/phy/tegra/xusb.c err = tegra_xusb_port_init(&ulpi->base, padctl, np, "ulpi", index); base 656 drivers/phy/tegra/xusb.c ulpi->base.ops = padctl->soc->ports.ulpi.ops; base 658 drivers/phy/tegra/xusb.c ulpi->base.lane = ulpi->base.ops->map(&ulpi->base); base 659 drivers/phy/tegra/xusb.c if (IS_ERR(ulpi->base.lane)) { base 660 drivers/phy/tegra/xusb.c err = PTR_ERR(ulpi->base.lane); base 666 drivers/phy/tegra/xusb.c tegra_xusb_port_unregister(&ulpi->base); base 670 drivers/phy/tegra/xusb.c list_add_tail(&ulpi->base.list, &padctl->ports); base 700 drivers/phy/tegra/xusb.c err = tegra_xusb_port_init(&hsic->base, padctl, np, "hsic", index); base 704 drivers/phy/tegra/xusb.c hsic->base.ops = padctl->soc->ports.hsic.ops; base 706 drivers/phy/tegra/xusb.c hsic->base.lane = hsic->base.ops->map(&hsic->base); base 707 drivers/phy/tegra/xusb.c if (IS_ERR(hsic->base.lane)) { base 708 drivers/phy/tegra/xusb.c err = PTR_ERR(hsic->base.lane); base 714 drivers/phy/tegra/xusb.c tegra_xusb_port_unregister(&hsic->base); base 718 drivers/phy/tegra/xusb.c list_add_tail(&hsic->base.list, &padctl->ports); base 727 drivers/phy/tegra/xusb.c struct tegra_xusb_port *port = &usb3->base; base 768 drivers/phy/tegra/xusb.c err = tegra_xusb_port_init(&usb3->base, padctl, np, "usb3", index); base 772 drivers/phy/tegra/xusb.c usb3->base.ops = padctl->soc->ports.usb3.ops; base 774 drivers/phy/tegra/xusb.c usb3->base.lane = usb3->base.ops->map(&usb3->base); base 775 drivers/phy/tegra/xusb.c if (IS_ERR(usb3->base.lane)) { base 776 drivers/phy/tegra/xusb.c err = PTR_ERR(usb3->base.lane); base 782 drivers/phy/tegra/xusb.c tegra_xusb_port_unregister(&usb3->base); base 786 drivers/phy/tegra/xusb.c list_add_tail(&usb3->base.list, &padctl->ports); base 52 drivers/phy/tegra/xusb.h struct tegra_xusb_lane base; base 58 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_usb3_lane, base); base 62 drivers/phy/tegra/xusb.h struct tegra_xusb_lane base; base 71 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_usb2_lane, base); base 75 drivers/phy/tegra/xusb.h struct tegra_xusb_lane base; base 81 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_ulpi_lane, base); base 85 drivers/phy/tegra/xusb.h struct tegra_xusb_lane base; base 100 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_hsic_lane, base); base 104 drivers/phy/tegra/xusb.h struct tegra_xusb_lane base; base 110 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_pcie_lane, base); base 114 drivers/phy/tegra/xusb.h struct tegra_xusb_lane base; base 120 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_sata_lane, base); base 177 drivers/phy/tegra/xusb.h struct tegra_xusb_pad base; base 186 drivers/phy/tegra/xusb.h return container_of(pad, struct tegra_xusb_usb3_pad, base); base 190 drivers/phy/tegra/xusb.h struct tegra_xusb_pad base; base 200 drivers/phy/tegra/xusb.h return container_of(pad, struct tegra_xusb_usb2_pad, base); base 204 drivers/phy/tegra/xusb.h struct tegra_xusb_pad base; base 210 drivers/phy/tegra/xusb.h return container_of(pad, struct tegra_xusb_ulpi_pad, base); base 214 drivers/phy/tegra/xusb.h struct tegra_xusb_pad base; base 223 drivers/phy/tegra/xusb.h return container_of(pad, struct tegra_xusb_hsic_pad, base); base 227 drivers/phy/tegra/xusb.h struct tegra_xusb_pad base; base 238 drivers/phy/tegra/xusb.h return container_of(pad, struct tegra_xusb_pcie_pad, base); base 242 drivers/phy/tegra/xusb.h struct tegra_xusb_pad base; base 253 drivers/phy/tegra/xusb.h return container_of(pad, struct tegra_xusb_sata_pad, base); base 289 drivers/phy/tegra/xusb.h struct tegra_xusb_port base; base 299 drivers/phy/tegra/xusb.h return container_of(port, struct tegra_xusb_usb2_port, base); base 307 drivers/phy/tegra/xusb.h struct tegra_xusb_port base; base 316 drivers/phy/tegra/xusb.h return container_of(port, struct tegra_xusb_ulpi_port, base); base 320 drivers/phy/tegra/xusb.h struct tegra_xusb_port base; base 326 drivers/phy/tegra/xusb.h return container_of(port, struct tegra_xusb_hsic_port, base); base 330 drivers/phy/tegra/xusb.h struct tegra_xusb_port base; base 345 drivers/phy/tegra/xusb.h return container_of(port, struct tegra_xusb_usb3_port, base); base 565 drivers/phy/ti/phy-am654-serdes.c void __iomem *base; base 574 drivers/phy/ti/phy-am654-serdes.c base = devm_platform_ioremap_resource(pdev, 0); base 575 drivers/phy/ti/phy-am654-serdes.c if (IS_ERR(base)) base 576 drivers/phy/ti/phy-am654-serdes.c return PTR_ERR(base); base 578 drivers/phy/ti/phy-am654-serdes.c regmap = devm_regmap_init_mmio(dev, base, &serdes_am654_regmap_config); base 48 drivers/pinctrl/actions/pinctrl-owl.c void __iomem *base; base 54 drivers/pinctrl/actions/pinctrl-owl.c static void owl_update_bits(void __iomem *base, u32 mask, u32 val) base 58 drivers/pinctrl/actions/pinctrl-owl.c reg_val = readl_relaxed(base); base 62 drivers/pinctrl/actions/pinctrl-owl.c writel_relaxed(reg_val, base); base 70 drivers/pinctrl/actions/pinctrl-owl.c tmp = readl_relaxed(pctrl->base + reg); base 84 drivers/pinctrl/actions/pinctrl-owl.c owl_update_bits(pctrl->base + reg, mask, (arg << bit)); base 204 drivers/pinctrl/actions/pinctrl-owl.c owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val); base 517 drivers/pinctrl/actions/pinctrl-owl.c static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag) base 521 drivers/pinctrl/actions/pinctrl-owl.c val = readl_relaxed(base); base 528 drivers/pinctrl/actions/pinctrl-owl.c writel_relaxed(val, base); base 542 drivers/pinctrl/actions/pinctrl-owl.c gpio_base = pctrl->base + port->offset; base 566 drivers/pinctrl/actions/pinctrl-owl.c gpio_base = pctrl->base + port->offset; base 589 drivers/pinctrl/actions/pinctrl-owl.c gpio_base = pctrl->base + port->offset; base 609 drivers/pinctrl/actions/pinctrl-owl.c gpio_base = pctrl->base + port->offset; base 627 drivers/pinctrl/actions/pinctrl-owl.c gpio_base = pctrl->base + port->offset; base 649 drivers/pinctrl/actions/pinctrl-owl.c gpio_base = pctrl->base + port->offset; base 705 drivers/pinctrl/actions/pinctrl-owl.c gpio_base = pctrl->base + port->offset; base 732 drivers/pinctrl/actions/pinctrl-owl.c gpio_base = pctrl->base + port->offset; base 761 drivers/pinctrl/actions/pinctrl-owl.c gpio_base = pctrl->base + port->offset; base 800 drivers/pinctrl/actions/pinctrl-owl.c gpio_base = pctrl->base + port->offset; base 832 drivers/pinctrl/actions/pinctrl-owl.c void __iomem *base; base 840 drivers/pinctrl/actions/pinctrl-owl.c base = pctrl->base + port->offset; base 846 drivers/pinctrl/actions/pinctrl-owl.c pending_irq = readl_relaxed(base + port->intc_pd); base 853 drivers/pinctrl/actions/pinctrl-owl.c owl_gpio_update_reg(base + port->intc_pd, pin, true); base 870 drivers/pinctrl/actions/pinctrl-owl.c chip->base = -1; base 927 drivers/pinctrl/actions/pinctrl-owl.c pctrl->base = devm_ioremap_resource(&pdev->dev, res); base 928 drivers/pinctrl/actions/pinctrl-owl.c if (IS_ERR(pctrl->base)) base 929 drivers/pinctrl/actions/pinctrl-owl.c return PTR_ERR(pctrl->base); base 133 drivers/pinctrl/actions/pinctrl-owl.h #define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, _intc_ctl,\ base 136 drivers/pinctrl/actions/pinctrl-owl.h .offset = base, \ base 80 drivers/pinctrl/bcm/pinctrl-bcm2835.c void __iomem *base; base 237 drivers/pinctrl/bcm/pinctrl-bcm2835.c return readl(pc->base + reg); base 243 drivers/pinctrl/bcm/pinctrl-bcm2835.c writel(val, pc->base + reg); base 306 drivers/pinctrl/bcm/pinctrl-bcm2835.c return pinctrl_gpio_direction_input(chip->base + offset); base 339 drivers/pinctrl/bcm/pinctrl-bcm2835.c return pinctrl_gpio_direction_output(chip->base + offset); base 353 drivers/pinctrl/bcm/pinctrl-bcm2835.c .base = -1, base 1110 drivers/pinctrl/bcm/pinctrl-bcm2835.c pc->base = devm_ioremap_resource(dev, &iomem); base 1111 drivers/pinctrl/bcm/pinctrl-bcm2835.c if (IS_ERR(pc->base)) base 1112 drivers/pinctrl/bcm/pinctrl-bcm2835.c return PTR_ERR(pc->base); base 1178 drivers/pinctrl/bcm/pinctrl-bcm2835.c pc->gpio_range.base = pc->gpio_chip.base; base 103 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c void __iomem *base; base 146 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val = readl(chip->base + offset); base 151 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c writel(val, chip->base + offset); base 160 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c return !!(readl(chip->base + offset) & BIT(shift)); base 174 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + base 185 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + base 206 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c writel(val, chip->base + offset); base 304 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c unsigned gpio = gc->base + offset; base 316 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c unsigned gpio = gc->base + offset; base 360 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c return !(readl(chip->base + offset) & BIT(shift)); base 382 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c return !!(readl(chip->base + offset) & BIT(shift)); base 469 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c void __iomem *base; base 476 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c base = chip->io_ctrl; base 479 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET); base 480 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET); base 492 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET); base 493 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET); base 515 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c void __iomem *base; base 522 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c base = chip->io_ctrl; base 525 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift); base 526 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift); base 547 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c void __iomem *base; base 557 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c base = chip->io_ctrl; base 559 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c base = chip->base; base 571 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val = readl(base + offset); base 574 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c writel(val, base + offset); base 584 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c void __iomem *base; base 590 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c base = chip->io_ctrl; base 592 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c base = chip->base; base 601 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c val = readl(base + offset) & BIT(shift); base 799 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c chip->base = devm_ioremap_resource(dev, res); base 800 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c if (IS_ERR(chip->base)) { base 802 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c return PTR_ERR(chip->base); base 829 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c gc->base = -1; base 57 drivers/pinctrl/bcm/pinctrl-ns2-mux.c unsigned int base; base 149 drivers/pinctrl/bcm/pinctrl-ns2-mux.c unsigned int base; base 175 drivers/pinctrl/bcm/pinctrl-ns2-mux.c .base = b, \ base 378 drivers/pinctrl/bcm/pinctrl-ns2-mux.c .base = ba, \ base 584 drivers/pinctrl/bcm/pinctrl-ns2-mux.c (mux->base != mux_log[i].mux.base) || base 613 drivers/pinctrl/bcm/pinctrl-ns2-mux.c switch (mux->base) { base 850 drivers/pinctrl/bcm/pinctrl-ns2-mux.c if (pin_data->pin_conf.base == -1) base 910 drivers/pinctrl/bcm/pinctrl-ns2-mux.c if (pin_data->pin_conf.base == -1) base 997 drivers/pinctrl/bcm/pinctrl-ns2-mux.c log->mux.base = NS2_PIN_MUX_BASE0; base 1009 drivers/pinctrl/bcm/pinctrl-ns2-mux.c log->mux.base = NS2_PIN_MUX_BASE0; base 1021 drivers/pinctrl/bcm/pinctrl-ns2-mux.c log->mux.base = NS2_PIN_MUX_BASE1; base 72 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c void __iomem *base; base 113 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c base_address = chip->base; base 134 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c return !!(readl(chip->base + reg) & BIT(gpio)); base 146 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS); base 151 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) & base 152 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c readl(chip->base + NSP_GPIO_EVENT); base 153 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c level = readl(chip->base + NSP_GPIO_DATA_IN) ^ base 154 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c readl(chip->base + NSP_GPIO_INT_POLARITY); base 155 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c level &= readl(chip->base + NSP_GPIO_INT_MASK); base 163 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c writel(BIT(bit), chip->base + NSP_GPIO_EVENT); base 322 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio)); base 635 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c chip->base = devm_ioremap_resource(dev, res); base 636 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c if (IS_ERR(chip->base)) { base 638 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c return PTR_ERR(chip->base); base 650 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c gc->base = -1; base 694 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val = readl(chip->base + NSP_CHIP_A_INT_MASK); base 696 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c writel(val, (chip->base + NSP_CHIP_A_INT_MASK)); base 53 drivers/pinctrl/bcm/pinctrl-nsp-mux.c unsigned int base; base 233 drivers/pinctrl/bcm/pinctrl-nsp-mux.c .base = ba, \ base 401 drivers/pinctrl/bcm/pinctrl-nsp-mux.c (mux->base != mux_log[i].mux.base)) base 429 drivers/pinctrl/bcm/pinctrl-nsp-mux.c switch (mux->base) { base 550 drivers/pinctrl/bcm/pinctrl-nsp-mux.c log->mux.base = nsp_pin_groups[i].mux.base; base 457 drivers/pinctrl/berlin/berlin-bg4ct.c void __iomem *base; base 464 drivers/pinctrl/berlin/berlin-bg4ct.c base = devm_ioremap_resource(&pdev->dev, res); base 465 drivers/pinctrl/berlin/berlin-bg4ct.c if (IS_ERR(base)) base 466 drivers/pinctrl/berlin/berlin-bg4ct.c return PTR_ERR(base); base 473 drivers/pinctrl/berlin/berlin-bg4ct.c regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig); base 338 drivers/pinctrl/berlin/pinctrl-as370.c void __iomem *base; base 345 drivers/pinctrl/berlin/pinctrl-as370.c base = devm_ioremap_resource(&pdev->dev, res); base 346 drivers/pinctrl/berlin/pinctrl-as370.c if (IS_ERR(base)) base 347 drivers/pinctrl/berlin/pinctrl-as370.c return PTR_ERR(base); base 354 drivers/pinctrl/berlin/pinctrl-as370.c regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig); base 1099 drivers/pinctrl/cirrus/pinctrl-lochnagar.c return pinctrl_gpio_direction_output(chip->base + offset); base 1163 drivers/pinctrl/cirrus/pinctrl-lochnagar.c priv->gpio_chip.base = -1; base 273 drivers/pinctrl/core.c unsigned int offset = gpio - range->base; base 297 drivers/pinctrl/core.c if (gpio >= range->base && base 298 drivers/pinctrl/core.c gpio < range->base + range->npins) { base 338 drivers/pinctrl/core.c if (range->base + range->npins - 1 < chip->base || base 339 drivers/pinctrl/core.c range->base > chip->base + chip->ngpio - 1) base 1698 drivers/pinctrl/core.c range->base, (range->base + range->npins - 1)); base 1706 drivers/pinctrl/core.c range->base, (range->base + range->npins - 1), base 182 drivers/pinctrl/freescale/pinctrl-imx.c reg = readl(ipctl->base + pin_reg->mux_reg); base 185 drivers/pinctrl/freescale/pinctrl-imx.c writel(reg, ipctl->base + pin_reg->mux_reg); base 189 drivers/pinctrl/freescale/pinctrl-imx.c writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); base 217 drivers/pinctrl/freescale/pinctrl-imx.c val = readl(ipctl->base + pin_mmio->input_reg); base 220 drivers/pinctrl/freescale/pinctrl-imx.c writel(val, ipctl->base + pin_mmio->input_reg); base 230 drivers/pinctrl/freescale/pinctrl-imx.c writel(pin_mmio->input_val, ipctl->base + base 361 drivers/pinctrl/freescale/pinctrl-imx.c *config = readl(ipctl->base + pin_reg->conf_reg); base 402 drivers/pinctrl/freescale/pinctrl-imx.c reg = readl(ipctl->base + pin_reg->conf_reg); base 405 drivers/pinctrl/freescale/pinctrl-imx.c writel(reg, ipctl->base + pin_reg->conf_reg); base 409 drivers/pinctrl/freescale/pinctrl-imx.c writel(configs[i], ipctl->base + pin_reg->conf_reg); base 457 drivers/pinctrl/freescale/pinctrl-imx.c config = readl(ipctl->base + pin_reg->conf_reg); base 826 drivers/pinctrl/freescale/pinctrl-imx.c ipctl->base = devm_platform_ioremap_resource(pdev, 0); base 827 drivers/pinctrl/freescale/pinctrl-imx.c if (IS_ERR(ipctl->base)) base 828 drivers/pinctrl/freescale/pinctrl-imx.c return PTR_ERR(ipctl->base); base 110 drivers/pinctrl/freescale/pinctrl-imx.h void __iomem *base; base 31 drivers/pinctrl/freescale/pinctrl-imx1-core.c void __iomem *base; base 78 drivers/pinctrl/freescale/pinctrl-imx1-core.c return ipctl->base + port * MX1_PORT_STRIDE; base 614 drivers/pinctrl/freescale/pinctrl-imx1-core.c ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start, base 616 drivers/pinctrl/freescale/pinctrl-imx1-core.c if (!ipctl->base) base 274 drivers/pinctrl/freescale/pinctrl-imx7ulp.c reg = readl(ipctl->base + pin_reg->mux_reg); base 279 drivers/pinctrl/freescale/pinctrl-imx7ulp.c writel(reg, ipctl->base + pin_reg->mux_reg); base 24 drivers/pinctrl/freescale/pinctrl-mxs.c void __iomem *base; base 213 drivers/pinctrl/freescale/pinctrl-mxs.c reg = d->base + d->soc->regs->muxsel; base 278 drivers/pinctrl/freescale/pinctrl-mxs.c reg = d->base + d->soc->regs->drive; base 298 drivers/pinctrl/freescale/pinctrl-mxs.c reg = d->base + d->soc->regs->pull; base 536 drivers/pinctrl/freescale/pinctrl-mxs.c d->base = of_iomap(np, 0); base 537 drivers/pinctrl/freescale/pinctrl-mxs.c if (!d->base) base 562 drivers/pinctrl/freescale/pinctrl-mxs.c iounmap(d->base); base 306 drivers/pinctrl/freescale/pinctrl-vf610.c reg = readl(ipctl->base + pin_reg->mux_reg); base 311 drivers/pinctrl/freescale/pinctrl-vf610.c writel(reg, ipctl->base + pin_reg->mux_reg); base 1179 drivers/pinctrl/intel/pinctrl-baytrail.c return pinctrl_gpio_direction_input(chip->base + offset); base 1185 drivers/pinctrl/intel/pinctrl-baytrail.c int ret = pinctrl_gpio_direction_output(chip->base + offset); base 1420 drivers/pinctrl/intel/pinctrl-baytrail.c u32 base, pin; base 1426 drivers/pinctrl/intel/pinctrl-baytrail.c for (base = 0; base < vg->chip.ngpio; base += 32) { base 1427 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); base 1432 drivers/pinctrl/intel/pinctrl-baytrail.c base); base 1440 drivers/pinctrl/intel/pinctrl-baytrail.c virq = irq_find_mapping(vg->chip.irq.domain, base + pin); base 1466 drivers/pinctrl/intel/pinctrl-baytrail.c u32 base, value; base 1496 drivers/pinctrl/intel/pinctrl-baytrail.c for (base = 0; base < vg->soc_data->npins; base += 32) { base 1497 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); base 1502 drivers/pinctrl/intel/pinctrl-baytrail.c base); base 1513 drivers/pinctrl/intel/pinctrl-baytrail.c base / 32, value); base 1527 drivers/pinctrl/intel/pinctrl-baytrail.c gc->base = -1; base 28 drivers/pinctrl/intel/pinctrl-cannonlake.c .base = (s), \ base 26 drivers/pinctrl/intel/pinctrl-cedarfork.c .base = (s), \ base 107 drivers/pinctrl/intel/pinctrl-cherryview.c unsigned int base; base 203 drivers/pinctrl/intel/pinctrl-cherryview.c .base = (start), \ base 1295 drivers/pinctrl/intel/pinctrl-cherryview.c return pinctrl_gpio_direction_input(chip->base + offset); base 1302 drivers/pinctrl/intel/pinctrl-cherryview.c return pinctrl_gpio_direction_output(chip->base + offset); base 1575 drivers/pinctrl/intel/pinctrl-cherryview.c chip->base = -1; base 1588 drivers/pinctrl/intel/pinctrl-cherryview.c range->base, range->base, base 1644 drivers/pinctrl/intel/pinctrl-cherryview.c range->base, range->npins); base 26 drivers/pinctrl/intel/pinctrl-denverton.c .base = (s), \ base 27 drivers/pinctrl/intel/pinctrl-icelake.c .base = (s), \ base 122 drivers/pinctrl/intel/pinctrl-intel.c #define padgroup_offset(g, p) ((p) - (g)->base) base 150 drivers/pinctrl/intel/pinctrl-intel.c if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) base 841 drivers/pinctrl/intel/pinctrl-intel.c pin = pgrp->base + offset - pgrp->gpio_base; base 875 drivers/pinctrl/intel/pinctrl-intel.c return pin - padgrp->base + padgrp->gpio_base; base 952 drivers/pinctrl/intel/pinctrl-intel.c return pinctrl_gpio_direction_input(chip->base + offset); base 959 drivers/pinctrl/intel/pinctrl-intel.c return pinctrl_gpio_direction_output(chip->base + offset); base 1175 drivers/pinctrl/intel/pinctrl-intel.c gpp->gpio_base, gpp->base, base 1216 drivers/pinctrl/intel/pinctrl-intel.c pctrl->chip.base = -1; base 1292 drivers/pinctrl/intel/pinctrl-intel.c gpps[i].base = community->pin_base + i * gpp_size; base 1301 drivers/pinctrl/intel/pinctrl-intel.c gpps[i].gpio_base = gpps[i].base; base 1549 drivers/pinctrl/intel/pinctrl-intel.c void __iomem *base; base 1552 drivers/pinctrl/intel/pinctrl-intel.c base = community->regs + community->ie_offset; base 1554 drivers/pinctrl/intel/pinctrl-intel.c communities[i].intmask[gpp] = readl(base + gpp * 4); base 1556 drivers/pinctrl/intel/pinctrl-intel.c base = community->regs + community->hostown_offset; base 1558 drivers/pinctrl/intel/pinctrl-intel.c communities[i].hostown[gpp] = readl(base + gpp * 4); base 1571 drivers/pinctrl/intel/pinctrl-intel.c void __iomem *base; base 1575 drivers/pinctrl/intel/pinctrl-intel.c base = community->regs; base 1579 drivers/pinctrl/intel/pinctrl-intel.c writel(0, base + community->ie_offset + gpp * 4); base 1580 drivers/pinctrl/intel/pinctrl-intel.c writel(0xffff, base + community->is_offset + gpp * 4); base 1586 drivers/pinctrl/intel/pinctrl-intel.c intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size) base 1592 drivers/pinctrl/intel/pinctrl-intel.c if (gpiochip_is_requested(chip, base + i)) base 1659 drivers/pinctrl/intel/pinctrl-intel.c void __iomem *base; base 1662 drivers/pinctrl/intel/pinctrl-intel.c base = community->regs + community->ie_offset; base 1664 drivers/pinctrl/intel/pinctrl-intel.c writel(communities[i].intmask[gpp], base + gpp * 4); base 1666 drivers/pinctrl/intel/pinctrl-intel.c readl(base + gpp * 4)); base 1669 drivers/pinctrl/intel/pinctrl-intel.c base = community->regs + community->hostown_offset; base 1680 drivers/pinctrl/intel/pinctrl-intel.c value = intel_gpio_update_pad_mode(base + gpp * 4, base 62 drivers/pinctrl/intel/pinctrl-intel.h unsigned int base; base 42 drivers/pinctrl/intel/pinctrl-sunrisepoint.c .base = (s), \ base 60 drivers/pinctrl/mediatek/mtk-eint.c reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4; base 90 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg = eint->base + (port << 2); base 212 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *base, u32 *buf) base 218 drivers/pinctrl/mediatek/mtk-eint.c reg = base + (port << 2); base 280 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg = eint->base + eint->regs->dom_en; base 298 drivers/pinctrl/mediatek/mtk-eint.c dbnc = readl(eint->base + ctrl_offset); base 303 drivers/pinctrl/mediatek/mtk-eint.c writel(rst, eint->base + ctrl_offset); base 378 drivers/pinctrl/mediatek/mtk-eint.c mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask); base 385 drivers/pinctrl/mediatek/mtk-eint.c mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask); base 426 drivers/pinctrl/mediatek/mtk-eint.c writel(clr_bit, eint->base + clr_offset); base 431 drivers/pinctrl/mediatek/mtk-eint.c writel(rst | bit, eint->base + set_offset); base 54 drivers/pinctrl/mediatek/mtk-eint.h void __iomem *base; base 458 drivers/pinctrl/mediatek/pinctrl-moore.c return pinctrl_gpio_direction_input(chip->base + gpio); base 466 drivers/pinctrl/mediatek/pinctrl-moore.c return pinctrl_gpio_direction_output(chip->base + gpio); base 519 drivers/pinctrl/mediatek/pinctrl-moore.c chip->base = -1; base 609 drivers/pinctrl/mediatek/pinctrl-moore.c hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names, base 610 drivers/pinctrl/mediatek/pinctrl-moore.c sizeof(*hw->base), GFP_KERNEL); base 611 drivers/pinctrl/mediatek/pinctrl-moore.c if (!hw->base) base 622 drivers/pinctrl/mediatek/pinctrl-moore.c hw->base[i] = devm_ioremap_resource(&pdev->dev, res); base 623 drivers/pinctrl/mediatek/pinctrl-moore.c if (IS_ERR(hw->base[i])) base 624 drivers/pinctrl/mediatek/pinctrl-moore.c return PTR_ERR(hw->base[i]); base 47 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c writel_relaxed(val, pctl->base[i] + reg); base 52 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c return readl_relaxed(pctl->base[i] + reg); base 332 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c hw->eint->base = devm_ioremap_resource(&pdev->dev, res); base 333 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c if (IS_ERR(hw->eint->base)) base 334 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c return PTR_ERR(hw->eint->base); base 241 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h void __iomem **base; base 782 drivers/pinctrl/mediatek/pinctrl-mtk-common.c return pinctrl_gpio_direction_input(chip->base + offset); base 789 drivers/pinctrl/mediatek/pinctrl-mtk-common.c return pinctrl_gpio_direction_output(chip->base + offset); base 995 drivers/pinctrl/mediatek/pinctrl-mtk-common.c pctl->eint->base = devm_ioremap_resource(&pdev->dev, res); base 996 drivers/pinctrl/mediatek/pinctrl-mtk-common.c if (IS_ERR(pctl->eint->base)) base 997 drivers/pinctrl/mediatek/pinctrl-mtk-common.c return PTR_ERR(pctl->eint->base); base 1097 drivers/pinctrl/mediatek/pinctrl-mtk-common.c pctl->chip->base = -1; base 732 drivers/pinctrl/mediatek/pinctrl-paris.c return pinctrl_gpio_direction_input(chip->base + gpio); base 740 drivers/pinctrl/mediatek/pinctrl-paris.c return pinctrl_gpio_direction_output(chip->base + gpio); base 794 drivers/pinctrl/mediatek/pinctrl-paris.c chip->base = -1; base 858 drivers/pinctrl/mediatek/pinctrl-paris.c hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names, base 859 drivers/pinctrl/mediatek/pinctrl-paris.c sizeof(*hw->base), GFP_KERNEL); base 860 drivers/pinctrl/mediatek/pinctrl-paris.c if (!hw->base) base 871 drivers/pinctrl/mediatek/pinctrl-paris.c hw->base[i] = devm_ioremap_resource(&pdev->dev, res); base 872 drivers/pinctrl/mediatek/pinctrl-paris.c if (IS_ERR(hw->base[i])) base 873 drivers/pinctrl/mediatek/pinctrl-paris.c return PTR_ERR(hw->base[i]); base 598 drivers/pinctrl/meson/pinctrl-meson.c pc->chip.base = -1; base 624 drivers/pinctrl/meson/pinctrl-meson.c void __iomem *base; base 631 drivers/pinctrl/meson/pinctrl-meson.c base = devm_ioremap_resource(pc->dev, &res); base 632 drivers/pinctrl/meson/pinctrl-meson.c if (IS_ERR(base)) base 633 drivers/pinctrl/meson/pinctrl-meson.c return ERR_CAST(base); base 642 drivers/pinctrl/meson/pinctrl-meson.c return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); base 97 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c void __iomem *base; base 522 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(d->mask, info->base + reg); base 535 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); base 536 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val & ~d->mask, info->base + reg); base 549 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); base 550 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val | d->mask, info->base + reg); base 563 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); base 568 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val, info->base + reg); base 583 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); base 608 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val, info->base + reg); base 625 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c p = readl(info->base + IRQ_POL + 4 * reg_idx); base 638 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(p, info->base + IRQ_POL + 4 * reg_idx); base 663 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); base 665 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c status &= readl_relaxed(info->base + IRQ_EN + 4 * i); base 683 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c info->base + base 694 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c status = readl_relaxed(info->base + base 697 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c status &= readl_relaxed(info->base + IRQ_EN + 4 * i); base 751 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c info->base = devm_ioremap_resource(info->dev, &res); base 752 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c if (IS_ERR(info->base)) base 753 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c return PTR_ERR(info->base); base 808 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c gc->base = -1; base 1027 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c info->pm.irq_en_l = readl(info->base + IRQ_EN); base 1028 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32)); base 1029 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c info->pm.irq_pol_l = readl(info->base + IRQ_POL); base 1030 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32)); base 1094 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(info->pm.irq_en_l, info->base + IRQ_EN); base 1095 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32)); base 1096 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(info->pm.irq_pol_l, info->base + IRQ_POL); base 1097 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32)); base 549 drivers/pinctrl/mvebu/pinctrl-armada-xp.c mpp_saved_regs[i] = readl(soc->control_data[0].base + i * 4); base 563 drivers/pinctrl/mvebu/pinctrl-armada-xp.c writel(mpp_saved_regs[i], soc->control_data[0].base + i * 4); base 68 drivers/pinctrl/mvebu/pinctrl-dove.c unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL); base 86 drivers/pinctrl/mvebu/pinctrl-dove.c unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL); base 90 drivers/pinctrl/mvebu/pinctrl-dove.c writel(pmu & ~BIT(pid), data->base + PMU_MPP_GENERAL_CTRL); base 94 drivers/pinctrl/mvebu/pinctrl-dove.c writel(pmu | BIT(pid), data->base + PMU_MPP_GENERAL_CTRL); base 192 drivers/pinctrl/mvebu/pinctrl-dove.c unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL); base 202 drivers/pinctrl/mvebu/pinctrl-dove.c unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL); base 207 drivers/pinctrl/mvebu/pinctrl-dove.c writel(pmu, data->base + PMU_MPP_GENERAL_CTRL); base 771 drivers/pinctrl/mvebu/pinctrl-dove.c void __iomem *base; base 788 drivers/pinctrl/mvebu/pinctrl-dove.c base = devm_ioremap_resource(&pdev->dev, mpp_res); base 789 drivers/pinctrl/mvebu/pinctrl-dove.c if (IS_ERR(base)) base 790 drivers/pinctrl/mvebu/pinctrl-dove.c return PTR_ERR(base); base 799 drivers/pinctrl/mvebu/pinctrl-dove.c mpp_data[i].base = base; base 64 drivers/pinctrl/mvebu/pinctrl-mvebu.c *config = (readl(data->base + off) >> shift) & MVEBU_MPP_MASK; base 76 drivers/pinctrl/mvebu/pinctrl-mvebu.c reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift); base 77 drivers/pinctrl/mvebu/pinctrl-mvebu.c writel(reg | (config << shift), data->base + off); base 763 drivers/pinctrl/mvebu/pinctrl-mvebu.c void __iomem *base; base 767 drivers/pinctrl/mvebu/pinctrl-mvebu.c base = devm_ioremap_resource(&pdev->dev, res); base 768 drivers/pinctrl/mvebu/pinctrl-mvebu.c if (IS_ERR(base)) base 769 drivers/pinctrl/mvebu/pinctrl-mvebu.c return PTR_ERR(base); base 777 drivers/pinctrl/mvebu/pinctrl-mvebu.c mpp_data[i].base = base; base 20 drivers/pinctrl/mvebu/pinctrl-mvebu.h void __iomem *base; base 189 drivers/pinctrl/mvebu/pinctrl-mvebu.h .base = _gpiobase, \ base 505 drivers/pinctrl/nomadik/pinctrl-abx500.c unsigned gpio = chip->base; base 682 drivers/pinctrl/nomadik/pinctrl-abx500.c chip->base + offset - 1); base 1005 drivers/pinctrl/nomadik/pinctrl-abx500.c pct->chip.base = -1; /* Dynamic allocation */ base 412 drivers/pinctrl/nomadik/pinctrl-nomadik.c int gpio = nmk_chip->chip.base + offset; base 1014 drivers/pinctrl/nomadik/pinctrl-nomadik.c unsigned gpio = chip->base; base 1046 drivers/pinctrl/nomadik/pinctrl-nomadik.c void __iomem *base; base 1075 drivers/pinctrl/nomadik/pinctrl-nomadik.c chip->base = id * NMK_GPIO_PER_CHIP; base 1081 drivers/pinctrl/nomadik/pinctrl-nomadik.c base = devm_ioremap_resource(&pdev->dev, res); base 1082 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (IS_ERR(base)) { base 1084 drivers/pinctrl/nomadik/pinctrl-nomadik.c return ERR_CAST(base); base 1086 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->addr = base; base 1163 drivers/pinctrl/nomadik/pinctrl-nomadik.c chip->base, base 1164 drivers/pinctrl/nomadik/pinctrl-nomadik.c chip->base + chip->ngpio - 1); base 1243 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (pin >= nmk_gpio->chip.base && base 1244 drivers/pinctrl/nomadik/pinctrl-nomadik.c pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio) base 1268 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); base 77 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c void __iomem *base; base 135 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c bank->gc.base / bank->gc.ngpio, base 136 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c bank->gc.base, base 137 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c bank->gc.base + bank->gc.ngpio); base 139 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_DIN), base 140 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_DOUT), base 141 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_IEM), base 142 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OE)); base 144 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_PU), base 145 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_PD), base 146 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_DBNC), base 147 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_POL)); base 149 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_EVTYP), base 150 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_EVBE), base 151 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_EVEN), base 152 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_EVST)); base 154 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OTYP), base 155 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OSRC), base 156 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_ODSC)); base 158 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OBL0), base 159 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OBL1), base 160 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OBL2), base 161 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OBL3)); base 163 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_SPLCK), base 164 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_MPLCK)); base 172 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ret = pinctrl_gpio_direction_input(offset + chip->base); base 189 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ret = pinctrl_gpio_direction_output(offset + chip->base); base 202 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ret = pinctrl_gpio_request(offset + chip->base); base 212 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c pinctrl_gpio_free(offset + chip->base); base 227 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); base 228 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); base 249 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); base 250 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); base 254 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); base 255 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); base 259 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); base 263 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); base 267 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); base 275 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); base 279 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); base 293 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); base 305 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); base 317 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); base 1449 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c return ioread32(bank->base + NPCM7XX_GP_N_OSRC) base 1470 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, base 1474 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, base 1515 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c val = ioread32(bank->base + NPCM7XX_GP_N_ODSC) base 1541 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); base 1546 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); base 1697 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); base 1699 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); base 1731 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask; base 1732 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask; base 1742 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask; base 1743 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask; base 1750 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask); base 1753 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask; base 1756 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask; base 1790 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); base 1791 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); base 1794 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); base 1795 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); base 1798 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); base 1799 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); base 1802 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); base 1806 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); base 1810 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); base 1813 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); base 1816 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio); base 1879 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c pctrl->gpio_bank[id].base = base 1892 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c pctrl->gpio_bank[id].base + base 1894 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c pctrl->gpio_bank[id].base + base 1898 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c pctrl->gpio_bank[id].base + base 1922 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c pctrl->gpio_bank[id].gc.base = pinspec.args[1]; base 1968 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c pctrl->gpio_bank[id].gc.base, base 46 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + offset * 4); base 59 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + offset * 4); base 61 drivers/pinctrl/pinctrl-amd.c writel(pin_reg, gpio_dev->base + offset * 4); base 75 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + offset * 4); base 81 drivers/pinctrl/pinctrl-amd.c writel(pin_reg, gpio_dev->base + offset * 4); base 94 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + offset * 4); base 107 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + offset * 4); base 112 drivers/pinctrl/pinctrl-amd.c writel(pin_reg, gpio_dev->base + offset * 4); base 126 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + offset * 4); base 175 drivers/pinctrl/pinctrl-amd.c writel(pin_reg, gpio_dev->base + offset * 4); base 242 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + i * 4); base 349 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + (d->hwirq)*4); base 352 drivers/pinctrl/pinctrl-amd.c writel(pin_reg, gpio_dev->base + (d->hwirq)*4); base 364 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + (d->hwirq)*4); base 367 drivers/pinctrl/pinctrl-amd.c writel(pin_reg, gpio_dev->base + (d->hwirq)*4); base 379 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + (d->hwirq)*4); base 381 drivers/pinctrl/pinctrl-amd.c writel(pin_reg, gpio_dev->base + (d->hwirq)*4); base 393 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + (d->hwirq)*4); base 395 drivers/pinctrl/pinctrl-amd.c writel(pin_reg, gpio_dev->base + (d->hwirq)*4); base 407 drivers/pinctrl/pinctrl-amd.c reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); base 409 drivers/pinctrl/pinctrl-amd.c writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); base 422 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + (d->hwirq)*4); base 504 drivers/pinctrl/pinctrl-amd.c writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); base 505 drivers/pinctrl/pinctrl-amd.c while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) base 507 drivers/pinctrl/pinctrl-amd.c writel(pin_reg, gpio_dev->base + (d->hwirq)*4); base 549 drivers/pinctrl/pinctrl-amd.c status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); base 551 drivers/pinctrl/pinctrl-amd.c status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); base 556 drivers/pinctrl/pinctrl-amd.c regs = gpio_dev->base; base 596 drivers/pinctrl/pinctrl-amd.c regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); base 598 drivers/pinctrl/pinctrl-amd.c writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); base 652 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + pin*4); base 697 drivers/pinctrl/pinctrl-amd.c pin_reg = readl(gpio_dev->base + pin*4); base 730 drivers/pinctrl/pinctrl-amd.c writel(pin_reg, gpio_dev->base + pin*4); base 811 drivers/pinctrl/pinctrl-amd.c gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); base 829 drivers/pinctrl/pinctrl-amd.c writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); base 869 drivers/pinctrl/pinctrl-amd.c gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, base 871 drivers/pinctrl/pinctrl-amd.c if (!gpio_dev->base) base 895 drivers/pinctrl/pinctrl-amd.c gpio_dev->gc.base = -1; base 91 drivers/pinctrl/pinctrl-amd.h void __iomem *base; base 58 drivers/pinctrl/pinctrl-artpec6.c void __iomem *base; base 684 drivers/pinctrl/pinctrl-artpec6.c regval = readl(pmx->base + reg); base 687 drivers/pinctrl/pinctrl-artpec6.c writel(regval, pmx->base + reg); base 717 drivers/pinctrl/pinctrl-artpec6.c val = readl_relaxed(pmx->base + reg); base 720 drivers/pinctrl/pinctrl-artpec6.c writel_relaxed(val, pmx->base + reg); base 751 drivers/pinctrl/pinctrl-artpec6.c regval = readl(pmx->base + artpec6_pmx_reg_offset(pin)); base 814 drivers/pinctrl/pinctrl-artpec6.c reg = pmx->base + artpec6_pmx_reg_offset(pin); base 923 drivers/pinctrl/pinctrl-artpec6.c void __iomem *base = pmx->base; base 929 drivers/pinctrl/pinctrl-artpec6.c val = readl_relaxed(base + artpec6_pmx_reg_offset(i)); base 932 drivers/pinctrl/pinctrl-artpec6.c writel_relaxed(val, base + artpec6_pmx_reg_offset(i)); base 948 drivers/pinctrl/pinctrl-artpec6.c pmx->base = devm_ioremap_resource(&pdev->dev, res); base 950 drivers/pinctrl/pinctrl-artpec6.c if (IS_ERR(pmx->base)) base 951 drivers/pinctrl/pinctrl-artpec6.c return PTR_ERR(pmx->base); base 517 drivers/pinctrl/pinctrl-as3722.c return pinctrl_gpio_direction_input(chip->base + offset); base 524 drivers/pinctrl/pinctrl-as3722.c return pinctrl_gpio_direction_output(chip->base + offset); base 546 drivers/pinctrl/pinctrl-as3722.c .base = -1, base 367 drivers/pinctrl/pinctrl-at91-pio4.c .base = 0, base 930 drivers/pinctrl/pinctrl-at91.c mask = 1 << (offset - chip->base); base 933 drivers/pinctrl/pinctrl-at91.c offset, 'A' + range->id, offset - chip->base, mask); base 1875 drivers/pinctrl/pinctrl-at91.c chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; base 1901 drivers/pinctrl/pinctrl-at91.c range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; base 115 drivers/pinctrl/pinctrl-axp209.c return pinctrl_gpio_direction_input(chip->base + offset); base 413 drivers/pinctrl/pinctrl-axp209.c pctl->chip.base = -1; base 33 drivers/pinctrl/pinctrl-bm1880.c void __iomem *base; base 993 drivers/pinctrl/pinctrl-bm1880.c u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + base 999 drivers/pinctrl/pinctrl-bm1880.c writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset); base 1159 drivers/pinctrl/pinctrl-bm1880.c regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); base 1210 drivers/pinctrl/pinctrl-bm1880.c regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); base 1259 drivers/pinctrl/pinctrl-bm1880.c writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset); base 1319 drivers/pinctrl/pinctrl-bm1880.c pctrl->base = devm_ioremap_resource(&pdev->dev, res); base 1320 drivers/pinctrl/pinctrl-bm1880.c if (IS_ERR(pctrl->base)) base 1321 drivers/pinctrl/pinctrl-bm1880.c return PTR_ERR(pctrl->base); base 73 drivers/pinctrl/pinctrl-coh901.c void __iomem *base; base 94 drivers/pinctrl/pinctrl-coh901.c (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) base 501 drivers/pinctrl/pinctrl-coh901.c struct u300_gpio_port *port = &gpio->ports[irq - chip->base]; base 632 drivers/pinctrl/pinctrl-coh901.c gpio->chip.base = 0; base 636 drivers/pinctrl/pinctrl-coh901.c gpio->base = devm_ioremap_resource(&pdev->dev, memres); base 637 drivers/pinctrl/pinctrl-coh901.c if (IS_ERR(gpio->base)) base 638 drivers/pinctrl/pinctrl-coh901.c return PTR_ERR(gpio->base); base 665 drivers/pinctrl/pinctrl-coh901.c val = readl(gpio->base + U300_GPIO_CR); base 672 drivers/pinctrl/pinctrl-coh901.c gpio->base + U300_GPIO_CR); base 710 drivers/pinctrl/pinctrl-coh901.c writel(0x0, gpio->base + portno * gpio->stride + ifr); base 745 drivers/pinctrl/pinctrl-coh901.c writel(0x00000000U, gpio->base + U300_GPIO_CR); base 23 drivers/pinctrl/pinctrl-da850-pupd.c void __iomem *base; base 73 drivers/pinctrl/pinctrl-da850-pupd.c val = readl(data->base + DA850_PUPD_ENA); base 86 drivers/pinctrl/pinctrl-da850-pupd.c val = readl(data->base + DA850_PUPD_SEL); base 110 drivers/pinctrl/pinctrl-da850-pupd.c ena = readl(data->base + DA850_PUPD_ENA); base 111 drivers/pinctrl/pinctrl-da850-pupd.c sel = readl(data->base + DA850_PUPD_SEL); base 133 drivers/pinctrl/pinctrl-da850-pupd.c writel(sel, data->base + DA850_PUPD_SEL); base 134 drivers/pinctrl/pinctrl-da850-pupd.c writel(ena, data->base + DA850_PUPD_ENA); base 156 drivers/pinctrl/pinctrl-da850-pupd.c data->base = devm_ioremap_resource(dev, res); base 157 drivers/pinctrl/pinctrl-da850-pupd.c if (IS_ERR(data->base)) { base 159 drivers/pinctrl/pinctrl-da850-pupd.c return PTR_ERR(data->base); base 249 drivers/pinctrl/pinctrl-digicolor.c chip->base = -1; base 95 drivers/pinctrl/pinctrl-falcon.c int base = bank * PINS; base 99 drivers/pinctrl/pinctrl-falcon.c d[i].number = base + i; base 100 drivers/pinctrl/pinctrl-falcon.c d[i].name = kasprintf(GFP_KERNEL, "io%d", base + i); base 1367 drivers/pinctrl/pinctrl-ingenic.c jzgc->gc.base / PINS_PER_GPIO_CHIP); base 1593 drivers/pinctrl/pinctrl-ingenic.c return pinctrl_gpio_direction_input(gc->base + offset); base 1600 drivers/pinctrl/pinctrl-ingenic.c return pinctrl_gpio_direction_output(gc->base + offset); base 1644 drivers/pinctrl/pinctrl-ingenic.c unsigned int pin = gc->base + offset; base 1967 drivers/pinctrl/pinctrl-ingenic.c jzgc->gc.base = bank * 32; base 2018 drivers/pinctrl/pinctrl-ingenic.c void __iomem *base; base 2031 drivers/pinctrl/pinctrl-ingenic.c base = devm_ioremap_resource(dev, base 2033 drivers/pinctrl/pinctrl-ingenic.c if (IS_ERR(base)) base 2034 drivers/pinctrl/pinctrl-ingenic.c return PTR_ERR(base); base 2036 drivers/pinctrl/pinctrl-ingenic.c jzpc->map = devm_regmap_init_mmio(dev, base, base 188 drivers/pinctrl/pinctrl-lpc18xx.c void __iomem *base; base 729 drivers/pinctrl/pinctrl-lpc18xx.c return pin - range->pin_base + range->base; base 777 drivers/pinctrl/pinctrl-lpc18xx.c ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg); base 781 drivers/pinctrl/pinctrl-lpc18xx.c return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg); base 885 drivers/pinctrl/pinctrl-lpc18xx.c reg = readl(scu->base + pin_cap->offset); base 999 drivers/pinctrl/pinctrl-lpc18xx.c reg_val = readl(scu->base + reg_offset); base 1002 drivers/pinctrl/pinctrl-lpc18xx.c writel(reg_val, scu->base + reg_offset); base 1100 drivers/pinctrl/pinctrl-lpc18xx.c reg = readl(scu->base + pin_cap->offset); base 1117 drivers/pinctrl/pinctrl-lpc18xx.c writel(reg, scu->base + pin_cap->offset); base 1178 drivers/pinctrl/pinctrl-lpc18xx.c writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset); base 1185 drivers/pinctrl/pinctrl-lpc18xx.c reg = readl(scu->base + offset); base 1187 drivers/pinctrl/pinctrl-lpc18xx.c writel(reg, scu->base + offset); base 1193 drivers/pinctrl/pinctrl-lpc18xx.c writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset); base 1195 drivers/pinctrl/pinctrl-lpc18xx.c reg = readl(scu->base + LPC18XX_SCU_REG_ENAIO2); base 1197 drivers/pinctrl/pinctrl-lpc18xx.c writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2); base 1210 drivers/pinctrl/pinctrl-lpc18xx.c reg = readl(scu->base + pin->offset); base 1212 drivers/pinctrl/pinctrl-lpc18xx.c writel(reg | func, scu->base + pin->offset); base 1335 drivers/pinctrl/pinctrl-lpc18xx.c scu->base = devm_ioremap_resource(&pdev->dev, res); base 1336 drivers/pinctrl/pinctrl-lpc18xx.c if (IS_ERR(scu->base)) base 1337 drivers/pinctrl/pinctrl-lpc18xx.c return PTR_ERR(scu->base); base 661 drivers/pinctrl/pinctrl-mcp23s08.c unsigned int base, int cs) base 761 drivers/pinctrl/pinctrl-mcp23s08.c mcp->chip.base = base; base 924 drivers/pinctrl/pinctrl-mcp23s08.c pdata->base = -1; base 940 drivers/pinctrl/pinctrl-mcp23s08.c id->driver_data, pdata->base, 0); base 1006 drivers/pinctrl/pinctrl-mcp23s08.c pdata->base = -1; base 1057 drivers/pinctrl/pinctrl-mcp23s08.c pdata->base, addr); base 1061 drivers/pinctrl/pinctrl-mcp23s08.c if (pdata->base != -1) base 1062 drivers/pinctrl/pinctrl-mcp23s08.c pdata->base += data->mcp[addr]->chip.ngpio; base 613 drivers/pinctrl/pinctrl-ocelot.c return pinctrl_gpio_direction_input(chip->base + offset); base 629 drivers/pinctrl/pinctrl-ocelot.c return pinctrl_gpio_direction_output(chip->base + offset); base 746 drivers/pinctrl/pinctrl-ocelot.c gc->base = 0; base 779 drivers/pinctrl/pinctrl-ocelot.c void __iomem *base; base 793 drivers/pinctrl/pinctrl-ocelot.c base = devm_ioremap_resource(dev, base 795 drivers/pinctrl/pinctrl-ocelot.c if (IS_ERR(base)) { base 797 drivers/pinctrl/pinctrl-ocelot.c return PTR_ERR(base); base 803 drivers/pinctrl/pinctrl-ocelot.c info->map = devm_regmap_init_mmio(dev, base, ®map_config); base 698 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset - bank->gpio_chip.base); base 701 drivers/pinctrl/pinctrl-oxnas.c offset, bank->gpio_chip.base, bank->id, mask); base 729 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset - bank->gpio_chip.base); base 732 drivers/pinctrl/pinctrl-oxnas.c offset, bank->gpio_chip.base, bank->id, mask); base 843 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pin - bank->gpio_chip.base); base 875 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pin - bank->gpio_chip.base); base 906 drivers/pinctrl/pinctrl-oxnas.c u32 offset = pin - bank->gpio_chip.base; base 910 drivers/pinctrl/pinctrl-oxnas.c pin, bank->gpio_chip.base, mask); base 943 drivers/pinctrl/pinctrl-oxnas.c u32 offset = pin - bank->gpio_chip.base; base 947 drivers/pinctrl/pinctrl-oxnas.c pin, bank->gpio_chip.base, mask); base 1072 drivers/pinctrl/pinctrl-oxnas.c .base = GPIO_BANK_START(_bank), \ base 506 drivers/pinctrl/pinctrl-palmas.c #define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \ base 511 drivers/pinctrl/pinctrl-palmas.c .mux_reg_base = PALMAS_##base##_BASE, \ base 758 drivers/pinctrl/pinctrl-palmas.c int base, add; base 792 drivers/pinctrl/pinctrl-palmas.c base = opt->pud_info->pullup_dn_reg_base; base 794 drivers/pinctrl/pinctrl-palmas.c ret = palmas_read(pci->palmas, base, add, &val); base 824 drivers/pinctrl/pinctrl-palmas.c base = opt->od_info->od_reg_base; base 826 drivers/pinctrl/pinctrl-palmas.c ret = palmas_read(pci->palmas, base, add, &val); base 867 drivers/pinctrl/pinctrl-palmas.c int base, add, mask; base 905 drivers/pinctrl/pinctrl-palmas.c base = opt->pud_info->pullup_dn_reg_base; base 931 drivers/pinctrl/pinctrl-palmas.c base = opt->od_info->od_reg_base; base 951 drivers/pinctrl/pinctrl-palmas.c __func__, base, add, mask, rval); base 952 drivers/pinctrl/pinctrl-palmas.c ret = palmas_update_bits(pci->palmas, base, add, mask, rval); base 1803 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset - bank->gpio_chip.base); base 1806 drivers/pinctrl/pinctrl-pic32.c offset, bank->gpio_chip.base, mask); base 1884 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(pin - bank->gpio_chip.base); base 1927 drivers/pinctrl/pinctrl-pic32.c u32 offset = pin - bank->gpio_chip.base; base 1931 drivers/pinctrl/pinctrl-pic32.c pin, bank->gpio_chip.base, mask); base 2118 drivers/pinctrl/pinctrl-pic32.c .base = GPIO_BANK_START(_bank), \ base 95 drivers/pinctrl/pinctrl-pistachio.c void __iomem *base; base 104 drivers/pinctrl/pinctrl-pistachio.c void __iomem *base; base 833 drivers/pinctrl/pinctrl-pistachio.c return readl(pctl->base + reg); base 838 drivers/pinctrl/pinctrl-pistachio.c writel(val, pctl->base + reg); base 848 drivers/pinctrl/pinctrl-pistachio.c return readl(bank->base + reg); base 854 drivers/pinctrl/pinctrl-pistachio.c writel(val, bank->base + reg); base 1323 drivers/pinctrl/pinctrl-pistachio.c .base = _pin_base, \ base 1382 drivers/pinctrl/pinctrl-pistachio.c bank->base = pctl->base + GPIO_BANK_BASE(i); base 1441 drivers/pinctrl/pinctrl-pistachio.c pctl->base = devm_ioremap_resource(&pdev->dev, res); base 1442 drivers/pinctrl/pinctrl-pistachio.c if (IS_ERR(pctl->base)) base 1443 drivers/pinctrl/pinctrl-pistachio.c return PTR_ERR(pctl->base); base 169 drivers/pinctrl/pinctrl-rk805.c return pinctrl_gpio_direction_input(chip->base + offset); base 176 drivers/pinctrl/pinctrl-rk805.c return pinctrl_gpio_direction_output(chip->base + offset); base 210 drivers/pinctrl/pinctrl-rk805.c .base = -1, base 2262 drivers/pinctrl/pinctrl-rockchip.c pin = offset - chip->base; base 2266 drivers/pinctrl/pinctrl-rockchip.c return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, base 2677 drivers/pinctrl/pinctrl-rockchip.c pin_bank->grange.base = pin_bank->gpio_chip.base; base 2734 drivers/pinctrl/pinctrl-rockchip.c return pinctrl_gpio_direction_input(gc->base + offset); base 2746 drivers/pinctrl/pinctrl-rockchip.c return pinctrl_gpio_direction_output(gc->base + offset); base 3123 drivers/pinctrl/pinctrl-rockchip.c gc->base = bank->pin_base; base 3170 drivers/pinctrl/pinctrl-rockchip.c void __iomem *base; base 3197 drivers/pinctrl/pinctrl-rockchip.c base = devm_ioremap_resource(info->dev, &res); base 3198 drivers/pinctrl/pinctrl-rockchip.c if (IS_ERR(base)) base 3199 drivers/pinctrl/pinctrl-rockchip.c return PTR_ERR(base); base 3205 drivers/pinctrl/pinctrl-rockchip.c base, base 3406 drivers/pinctrl/pinctrl-rockchip.c void __iomem *base; base 3434 drivers/pinctrl/pinctrl-rockchip.c base = devm_ioremap_resource(&pdev->dev, res); base 3435 drivers/pinctrl/pinctrl-rockchip.c if (IS_ERR(base)) base 3436 drivers/pinctrl/pinctrl-rockchip.c return PTR_ERR(base); base 3440 drivers/pinctrl/pinctrl-rockchip.c info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, base 3449 drivers/pinctrl/pinctrl-rockchip.c base = devm_ioremap_resource(&pdev->dev, res); base 3450 drivers/pinctrl/pinctrl-rockchip.c if (IS_ERR(base)) base 3451 drivers/pinctrl/pinctrl-rockchip.c return PTR_ERR(base); base 3457 drivers/pinctrl/pinctrl-rockchip.c base, base 465 drivers/pinctrl/pinctrl-rza1.c void __iomem *base; base 487 drivers/pinctrl/pinctrl-rza1.c void __iomem *base; base 576 drivers/pinctrl/pinctrl-rza1.c void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); base 590 drivers/pinctrl/pinctrl-rza1.c void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); base 1215 drivers/pinctrl/pinctrl-rza1.c chip->base = -1; base 1227 drivers/pinctrl/pinctrl-rza1.c range->pin_base = range->base = pinctrl_base; base 1335 drivers/pinctrl/pinctrl-rza1.c ports[port_id].base = rza1_pctl->base; base 1376 drivers/pinctrl/pinctrl-rza1.c rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0); base 1377 drivers/pinctrl/pinctrl-rza1.c if (IS_ERR(rza1_pctl->base)) base 1378 drivers/pinctrl/pinctrl-rza1.c return PTR_ERR(rza1_pctl->base); base 42 drivers/pinctrl/pinctrl-rza2.c void __iomem *base; base 134 drivers/pinctrl/pinctrl-rza2.c reg16 = readw(priv->base + RZA2_PDR(port)); base 147 drivers/pinctrl/pinctrl-rza2.c rza2_pin_to_gpio(priv->base, offset, 1); base 157 drivers/pinctrl/pinctrl-rza2.c rza2_pin_to_gpio(priv->base, offset, 1); base 168 drivers/pinctrl/pinctrl-rza2.c return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin)); base 179 drivers/pinctrl/pinctrl-rza2.c new_value = readb(priv->base + RZA2_PODR(port)); base 186 drivers/pinctrl/pinctrl-rza2.c writeb(new_value, priv->base + RZA2_PODR(port)); base 195 drivers/pinctrl/pinctrl-rza2.c rza2_pin_to_gpio(priv->base, offset, 0); base 228 drivers/pinctrl/pinctrl-rza2.c .base = -1, base 261 drivers/pinctrl/pinctrl-rza2.c priv->gpio_range.pin_base = priv->gpio_range.base = 0; base 445 drivers/pinctrl/pinctrl-rza2.c priv->base, base 475 drivers/pinctrl/pinctrl-rza2.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 476 drivers/pinctrl/pinctrl-rza2.c if (IS_ERR(priv->base)) base 477 drivers/pinctrl/pinctrl-rza2.c return PTR_ERR(priv->base); base 175 drivers/pinctrl/pinctrl-single.c void __iomem *base; base 283 drivers/pinctrl/pinctrl-single.c val = pcs->read(pcs->base + offset); base 406 drivers/pinctrl/pinctrl-single.c data = pcs->read(pcs->base + offset); base 409 drivers/pinctrl/pinctrl-single.c pcs->write(data, pcs->base + offset); base 411 drivers/pinctrl/pinctrl-single.c data = pcs->read(pcs->base + pin * mux_bytes); base 414 drivers/pinctrl/pinctrl-single.c pcs->write(data, pcs->base + pin * mux_bytes); base 485 drivers/pinctrl/pinctrl-single.c data = pcs->read(pcs->base + offset) & func->conf[i].mask; base 543 drivers/pinctrl/pinctrl-single.c data = pcs->read(pcs->base + offset); base 574 drivers/pinctrl/pinctrl-single.c pcs->write(data, pcs->base + offset); base 674 drivers/pinctrl/pinctrl-single.c val = pcs->read(pcs->base + offset); base 679 drivers/pinctrl/pinctrl-single.c pcs->write(val, pcs->base + offset); base 1022 drivers/pinctrl/pinctrl-single.c vals[found].reg = pcs->base + offset; base 1166 drivers/pinctrl/pinctrl-single.c vals[found].reg = pcs->base + offset; base 1519 drivers/pinctrl/pinctrl-single.c pcswi->reg = pcs->base + hwirq; base 1622 drivers/pinctrl/pinctrl-single.c *regsl++ = pcs->read(pcs->base + i); base 1627 drivers/pinctrl/pinctrl-single.c *regsw++ = pcs->read(pcs->base + i); base 1632 drivers/pinctrl/pinctrl-single.c *regshw++ = pcs->read(pcs->base + i); base 1652 drivers/pinctrl/pinctrl-single.c pcs->write(*regsl++, pcs->base + i); base 1657 drivers/pinctrl/pinctrl-single.c pcs->write(*regsw++, pcs->base + i); base 1662 drivers/pinctrl/pinctrl-single.c pcs->write(*regshw++, pcs->base + i); base 1825 drivers/pinctrl/pinctrl-single.c pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); base 1826 drivers/pinctrl/pinctrl-single.c if (!pcs->base) { base 315 drivers/pinctrl/pinctrl-st.c void __iomem *base; base 669 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_SET_POUT); base 671 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); base 698 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); base 700 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); base 708 drivers/pinctrl/pinctrl-st.c return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); base 719 drivers/pinctrl/pinctrl-st.c pinctrl_gpio_direction_input(chip->base + offset); base 730 drivers/pinctrl/pinctrl-st.c pinctrl_gpio_direction_output(chip->base + offset); base 757 drivers/pinctrl/pinctrl-st.c value = readl(bank->base + REG_PIO_PC(i)); base 1282 drivers/pinctrl/pinctrl-st.c writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); base 1290 drivers/pinctrl/pinctrl-st.c writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); base 1347 drivers/pinctrl/pinctrl-st.c val = readl(bank->base + REG_PIO_PCOMP); base 1350 drivers/pinctrl/pinctrl-st.c writel(val, bank->base + REG_PIO_PCOMP); base 1390 drivers/pinctrl/pinctrl-st.c port_in = readl(bank->base + REG_PIO_PIN); base 1391 drivers/pinctrl/pinctrl-st.c port_comp = readl(bank->base + REG_PIO_PCOMP); base 1392 drivers/pinctrl/pinctrl-st.c port_mask = readl(bank->base + REG_PIO_PMASK); base 1408 drivers/pinctrl/pinctrl-st.c val ? bank->base + REG_PIO_SET_PCOMP : base 1409 drivers/pinctrl/pinctrl-st.c bank->base + REG_PIO_CLR_PCOMP); base 1485 drivers/pinctrl/pinctrl-st.c bank->base = devm_ioremap_resource(dev, &res); base 1486 drivers/pinctrl/pinctrl-st.c if (IS_ERR(bank->base)) base 1487 drivers/pinctrl/pinctrl-st.c return PTR_ERR(bank->base); base 1490 drivers/pinctrl/pinctrl-st.c bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; base 1500 drivers/pinctrl/pinctrl-st.c range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; base 646 drivers/pinctrl/pinctrl-stmfx.c pctl->gpio_chip.base = -1; base 1161 drivers/pinctrl/pinctrl-sx150x.c pctl->gpio.base = -1; base 482 drivers/pinctrl/pinctrl-tb10x.c void *base; base 502 drivers/pinctrl/pinctrl-tb10x.c pcfg = ioread32(state->base) & ~(PCFG_PORT_MASK(port)); base 504 drivers/pinctrl/pinctrl-tb10x.c iowrite32(pcfg, state->base); base 511 drivers/pinctrl/pinctrl-tb10x.c return (ioread32(state->base) & PCFG_PORT_MASK(port)) base 772 drivers/pinctrl/pinctrl-tb10x.c state->base = devm_ioremap_resource(dev, mem); base 773 drivers/pinctrl/pinctrl-tb10x.c if (IS_ERR(state->base)) { base 774 drivers/pinctrl/pinctrl-tb10x.c ret = PTR_ERR(state->base); base 1013 drivers/pinctrl/pinctrl-u300.c (pin - range->pin_base + range->base), base 1030 drivers/pinctrl/pinctrl-u300.c (pin - range->pin_base + range->base), base 1598 drivers/pinctrl/pinctrl-xway.c .base = -1, base 1788 drivers/pinctrl/pinctrl-xway.c xway_gpio_range.base = xway_chip.base; base 585 drivers/pinctrl/qcom/pinctrl-msm.c unsigned gpio = chip->base; base 1012 drivers/pinctrl/qcom/pinctrl-msm.c chip->base = -1; base 24 drivers/pinctrl/qcom/pinctrl-msm8998.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ base 42 drivers/pinctrl/qcom/pinctrl-msm8998.c .ctl_reg = base + 0x1000 * id, \ base 43 drivers/pinctrl/qcom/pinctrl-msm8998.c .io_reg = base + 0x4 + 0x1000 * id, \ base 44 drivers/pinctrl/qcom/pinctrl-msm8998.c .intr_cfg_reg = base + 0x8 + 0x1000 * id, \ base 45 drivers/pinctrl/qcom/pinctrl-msm8998.c .intr_status_reg = base + 0xc + 0x1000 * id, \ base 46 drivers/pinctrl/qcom/pinctrl-msm8998.c .intr_target_reg = base + 0x8 + 0x1000 * id, \ base 25 drivers/pinctrl/qcom/pinctrl-sdm845.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ base 44 drivers/pinctrl/qcom/pinctrl-sdm845.c .ctl_reg = base + REG_SIZE * id, \ base 45 drivers/pinctrl/qcom/pinctrl-sdm845.c .io_reg = base + 0x4 + REG_SIZE * id, \ base 46 drivers/pinctrl/qcom/pinctrl-sdm845.c .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ base 47 drivers/pinctrl/qcom/pinctrl-sdm845.c .intr_status_reg = base + 0xc + REG_SIZE * id, \ base 48 drivers/pinctrl/qcom/pinctrl-sdm845.c .intr_target_reg = base + 0x8 + REG_SIZE * id, \ base 150 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c u16 base; base 220 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = regmap_read(state->map, pad->base + addr, &val); base 235 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = regmap_write(state->map, pad->base + addr, val); base 785 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c type, pad->base); base 1028 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE; base 1037 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c state->chip.base = -1; base 123 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c u16 base; base 182 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c ret = regmap_read(state->map, pad->base + addr, &val); base 197 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c ret = regmap_write(state->map, pad->base + addr, val); base 670 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c type, pad->base); base 691 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c subtype, pad->base); base 868 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; base 877 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c state->chip.base = -1; base 613 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c unsigned gpio = chip->base; base 828 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pctrl->chip.base = -1; base 625 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c unsigned gpio = chip->base; base 820 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c pctrl->chip.base = -1; base 920 drivers/pinctrl/samsung/pinctrl-samsung.c pin_bank->grange.base = pin_bank->grange.pin_base; base 966 drivers/pinctrl/samsung/pinctrl-samsung.c gc->base = bank->grange.base; base 245 drivers/pinctrl/sh-pfc/gpio.c gc->base = 0; base 285 drivers/pinctrl/sh-pfc/gpio.c gc->base = pfc->nr_gpio_pins; base 319 drivers/pinctrl/sh-pfc/gpio.c chip->gpio_chip.label, chip->gpio_chip.base, base 320 drivers/pinctrl/sh-pfc/gpio.c chip->gpio_chip.base + chip->gpio_chip.ngpio - 1); base 697 drivers/pinctrl/sh-pfc/sh_pfc.h #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ base 698 drivers/pinctrl/sh-pfc/sh_pfc.h [gpio - (base)] = { \ base 325 drivers/pinctrl/sirf/pinctrl-atlas7.c #define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i)) base 326 drivers/pinctrl/sirf/pinctrl-atlas7.c #define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C) base 341 drivers/pinctrl/sirf/pinctrl-atlas7.c void __iomem *base; base 5857 drivers/pinctrl/sirf/pinctrl-atlas7.c if (pinctrl_gpio_request(chip->base + gpio)) base 5887 drivers/pinctrl/sirf/pinctrl-atlas7.c pinctrl_gpio_free(chip->base + gpio); base 6043 drivers/pinctrl/sirf/pinctrl-atlas7.c chip->base = -1; base 6074 drivers/pinctrl/sirf/pinctrl-atlas7.c bank->base = ATLAS7_GPIO_BASE(a7gc, idx); base 616 drivers/pinctrl/sirf/pinctrl-sirf.c if (pinctrl_gpio_request(chip->base + offset)) base 646 drivers/pinctrl/sirf/pinctrl-sirf.c pinctrl_gpio_free(chip->base + offset); base 810 drivers/pinctrl/sirf/pinctrl-sirf.c sgpio->chip.gc.base = 0; base 26 drivers/pinctrl/spear/pinctrl-plgpio.c #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ base 67 drivers/pinctrl/spear/pinctrl-plgpio.c void __iomem *base; base 80 drivers/pinctrl/spear/pinctrl-plgpio.c static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg) base 83 drivers/pinctrl/spear/pinctrl-plgpio.c void __iomem *reg_off = REG_OFFSET(base, reg, pin); base 89 drivers/pinctrl/spear/pinctrl-plgpio.c static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg) base 92 drivers/pinctrl/spear/pinctrl-plgpio.c void __iomem *reg_off = REG_OFFSET(base, reg, pin); base 98 drivers/pinctrl/spear/pinctrl-plgpio.c static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg) base 101 drivers/pinctrl/spear/pinctrl-plgpio.c void __iomem *reg_off = REG_OFFSET(base, reg, pin); base 121 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir); base 148 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_reg_set(plgpio->base, wdata_offset, base 151 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_reg_reset(plgpio->base, wdata_offset, base 154 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir); base 174 drivers/pinctrl/spear/pinctrl-plgpio.c return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata); base 192 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata); base 194 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata); base 200 drivers/pinctrl/spear/pinctrl-plgpio.c int gpio = chip->base + offset; base 237 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb); base 252 drivers/pinctrl/spear/pinctrl-plgpio.c int gpio = chip->base + offset; base 269 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb); base 295 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie); base 314 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie); base 340 drivers/pinctrl/spear/pinctrl-plgpio.c reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); base 373 drivers/pinctrl/spear/pinctrl-plgpio.c pending = readl_relaxed(plgpio->base + plgpio->regs.mis + base 379 drivers/pinctrl/spear/pinctrl-plgpio.c writel_relaxed(~pending, plgpio->base + plgpio->regs.mis + base 526 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio->base = devm_ioremap_resource(&pdev->dev, res); base 527 drivers/pinctrl/spear/pinctrl-plgpio.c if (IS_ERR(plgpio->base)) base 528 drivers/pinctrl/spear/pinctrl-plgpio.c return PTR_ERR(plgpio->base); base 552 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio->chip.base = -1; base 621 drivers/pinctrl/spear/pinctrl-plgpio.c off = plgpio->base + i * sizeof(int *); base 661 drivers/pinctrl/spear/pinctrl-plgpio.c off = plgpio->base + i * sizeof(int *); base 150 drivers/pinctrl/sprd/pinctrl-sprd.c void __iomem *base; base 979 drivers/pinctrl/sprd/pinctrl-sprd.c pin->reg = (unsigned long)sprd_pctl->base + base 985 drivers/pinctrl/sprd/pinctrl-sprd.c pin->reg = (unsigned long)sprd_pctl->base + base 990 drivers/pinctrl/sprd/pinctrl-sprd.c pin->reg = (unsigned long)sprd_pctl->base + base 1020 drivers/pinctrl/sprd/pinctrl-sprd.c sprd_pctl->base = devm_platform_ioremap_resource(pdev, 0); base 1021 drivers/pinctrl/sprd/pinctrl-sprd.c if (IS_ERR(sprd_pctl->base)) base 1022 drivers/pinctrl/sprd/pinctrl-sprd.c return PTR_ERR(sprd_pctl->base); base 85 drivers/pinctrl/stm32/pinctrl-stm32.c void __iomem *base; base 200 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); base 218 drivers/pinctrl/stm32/pinctrl-stm32.c return pinctrl_gpio_request(chip->base + offset); base 223 drivers/pinctrl/stm32/pinctrl-stm32.c pinctrl_gpio_free(chip->base + offset); base 233 drivers/pinctrl/stm32/pinctrl-stm32.c ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); base 249 drivers/pinctrl/stm32/pinctrl-stm32.c return pinctrl_gpio_direction_input(chip->base + offset); base 258 drivers/pinctrl/stm32/pinctrl-stm32.c pinctrl_gpio_direction_output(chip->base + offset); base 710 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + alt_offset); base 713 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + alt_offset); base 715 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_MODER); base 718 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_MODER); base 743 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + alt_offset); base 747 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_MODER); base 829 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_TYPER); base 832 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_TYPER); base 855 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_TYPER); base 883 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); base 886 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); base 909 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); base 937 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); base 940 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); base 963 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); base 982 drivers/pinctrl/stm32/pinctrl-stm32.c val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & base 985 drivers/pinctrl/stm32/pinctrl-stm32.c val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & base 1165 drivers/pinctrl/stm32/pinctrl-stm32.c bank->base = devm_ioremap_resource(dev, &res); base 1166 drivers/pinctrl/stm32/pinctrl-stm32.c if (IS_ERR(bank->base)) base 1167 drivers/pinctrl/stm32/pinctrl-stm32.c return PTR_ERR(bank->base); base 1187 drivers/pinctrl/stm32/pinctrl-stm32.c bank->gpio_chip.base = args.args[1]; base 1190 drivers/pinctrl/stm32/pinctrl-stm32.c bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; base 1194 drivers/pinctrl/stm32/pinctrl-stm32.c range->base = range->id * STM32_GPIO_PINS_PER_BANK; base 1204 drivers/pinctrl/stm32/pinctrl-stm32.c bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; base 837 drivers/pinctrl/sunxi/pinctrl-sunxi.c return pinctrl_gpio_direction_input(chip->base + offset); base 847 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 pin = offset + chip->base; base 888 drivers/pinctrl/sunxi/pinctrl-sunxi.c return pinctrl_gpio_direction_output(chip->base + offset); base 895 drivers/pinctrl/sunxi/pinctrl-sunxi.c int pin, base; base 897 drivers/pinctrl/sunxi/pinctrl-sunxi.c base = PINS_PER_BANK * gpiospec->args[0]; base 898 drivers/pinctrl/sunxi/pinctrl-sunxi.c pin = base + gpiospec->args[1]; base 926 drivers/pinctrl/sunxi/pinctrl-sunxi.c chip->label, offset + chip->base, irqnum); base 1097 drivers/pinctrl/sunxi/pinctrl-sunxi.c int pin, base; base 1102 drivers/pinctrl/sunxi/pinctrl-sunxi.c base = PINS_PER_BANK * intspec[0]; base 1103 drivers/pinctrl/sunxi/pinctrl-sunxi.c pin = pctl->desc->pin_base + base + intspec[1]; base 1486 drivers/pinctrl/sunxi/pinctrl-sunxi.c pctl->chip->base = pctl->desc->pin_base; base 600 drivers/pinctrl/tegra/pinctrl-tegra.c .base = 0, base 30 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int base; base 156 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int base = 0; base 164 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c base = UNIPHIER_PINCTRL_DRVCTRL_BASE; base 170 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c base = UNIPHIER_PINCTRL_DRV2CTRL_BASE; base 176 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c base = UNIPHIER_PINCTRL_DRV3CTRL_BASE; base 197 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c *reg = base + drvctrl / 32 * 4; base 706 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c ret = regmap_bulk_read(priv->regmap, r->base, r->vals, base 722 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c ret = regmap_bulk_write(priv->regmap, r->base, r->vals, base 740 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int base, base 757 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c region->base = base; base 31 drivers/pinctrl/vt8500/pinctrl-wmt.c val = readl_relaxed(data->base + reg); base 33 drivers/pinctrl/vt8500/pinctrl-wmt.c writel_relaxed(val, data->base + reg); base 41 drivers/pinctrl/vt8500/pinctrl-wmt.c val = readl_relaxed(data->base + reg); base 43 drivers/pinctrl/vt8500/pinctrl-wmt.c writel_relaxed(val, data->base + reg); base 488 drivers/pinctrl/vt8500/pinctrl-wmt.c val = readl_relaxed(data->base + reg_dir); base 505 drivers/pinctrl/vt8500/pinctrl-wmt.c return !!(readl_relaxed(data->base + reg_data_in) & BIT(bit)); base 529 drivers/pinctrl/vt8500/pinctrl-wmt.c return pinctrl_gpio_direction_input(chip->base + offset); base 536 drivers/pinctrl/vt8500/pinctrl-wmt.c return pinctrl_gpio_direction_output(chip->base + offset); base 559 drivers/pinctrl/vt8500/pinctrl-wmt.c data->base = devm_ioremap_resource(&pdev->dev, res); base 560 drivers/pinctrl/vt8500/pinctrl-wmt.c if (IS_ERR(data->base)) base 561 drivers/pinctrl/vt8500/pinctrl-wmt.c return PTR_ERR(data->base); base 56 drivers/pinctrl/vt8500/pinctrl-wmt.h void __iomem *base; base 33 drivers/pinctrl/zte/pinctrl-zx.c void __iomem *base; base 117 drivers/pinctrl/zte/pinctrl-zx.c val = readl(zpctl->base + offset); base 120 drivers/pinctrl/zte/pinctrl-zx.c writel(val, zpctl->base + offset); base 137 drivers/pinctrl/zte/pinctrl-zx.c val = readl(zpctl->base + offset); base 140 drivers/pinctrl/zte/pinctrl-zx.c writel(val, zpctl->base + offset); base 400 drivers/pinctrl/zte/pinctrl-zx.c zpctl->base = devm_ioremap_resource(&pdev->dev, res); base 401 drivers/pinctrl/zte/pinctrl-zx.c if (IS_ERR(zpctl->base)) base 402 drivers/pinctrl/zte/pinctrl-zx.c return PTR_ERR(zpctl->base); base 143 drivers/platform/chrome/cros_ec_lpc_mec.c void cros_ec_lpc_mec_init(unsigned int base, unsigned int end) base 146 drivers/platform/chrome/cros_ec_lpc_mec.c mec_emi_base = base; base 46 drivers/platform/chrome/cros_ec_lpc_mec.h void cros_ec_lpc_mec_init(unsigned int base, unsigned int end); base 213 drivers/platform/goldfish/goldfish_pipe.c unsigned char __iomem *base; base 227 drivers/platform/goldfish/goldfish_pipe.c writel(pipe->id, pipe->dev->base + PIPE_REG_CMD); base 644 drivers/platform/goldfish/goldfish_pipe.c count = readl(dev->base + PIPE_REG_GET_SIGNALLED); base 870 drivers/platform/goldfish/goldfish_pipe.c dev->base + PIPE_REG_SIGNAL_BUFFER, base 871 drivers/platform/goldfish/goldfish_pipe.c dev->base + PIPE_REG_SIGNAL_BUFFER_HIGH); base 874 drivers/platform/goldfish/goldfish_pipe.c dev->base + PIPE_REG_SIGNAL_BUFFER_COUNT); base 877 drivers/platform/goldfish/goldfish_pipe.c dev->base + PIPE_REG_OPEN_BUFFER, base 878 drivers/platform/goldfish/goldfish_pipe.c dev->base + PIPE_REG_OPEN_BUFFER_HIGH); base 910 drivers/platform/goldfish/goldfish_pipe.c dev->base = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE); base 911 drivers/platform/goldfish/goldfish_pipe.c if (!dev->base) { base 929 drivers/platform/goldfish/goldfish_pipe.c writel(PIPE_DRIVER_VERSION, dev->base + PIPE_REG_VERSION); base 930 drivers/platform/goldfish/goldfish_pipe.c dev->version = readl(dev->base + PIPE_REG_VERSION); base 199 drivers/platform/x86/intel_int0002_vgpio.c chip->base = -1; base 46 drivers/platform/x86/intel_punit_ipc.c void __iomem *base[RESERVED_IPC][BASE_MAX]; base 54 drivers/platform/x86/intel_punit_ipc.c return readl(ipcdev->base[type][BASE_IFACE]); base 59 drivers/platform/x86/intel_punit_ipc.c writel(cmd, ipcdev->base[type][BASE_IFACE]); base 64 drivers/platform/x86/intel_punit_ipc.c return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW); base 69 drivers/platform/x86/intel_punit_ipc.c return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH); base 74 drivers/platform/x86/intel_punit_ipc.c writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW); base 79 drivers/platform/x86/intel_punit_ipc.c writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH); base 239 drivers/platform/x86/intel_punit_ipc.c punit_ipcdev->base[BIOS_IPC][BASE_DATA] = addr; base 245 drivers/platform/x86/intel_punit_ipc.c punit_ipcdev->base[BIOS_IPC][BASE_IFACE] = addr; base 258 drivers/platform/x86/intel_punit_ipc.c punit_ipcdev->base[ISPDRIVER_IPC][BASE_DATA] = addr; base 265 drivers/platform/x86/intel_punit_ipc.c punit_ipcdev->base[ISPDRIVER_IPC][BASE_IFACE] = addr; base 272 drivers/platform/x86/intel_punit_ipc.c punit_ipcdev->base[GTDRIVER_IPC][BASE_DATA] = addr; base 279 drivers/platform/x86/intel_punit_ipc.c punit_ipcdev->base[GTDRIVER_IPC][BASE_IFACE] = addr; base 1755 drivers/platform/x86/mlx-platform.c void __iomem *base; base 1765 drivers/platform/x86/mlx-platform.c *val = ioread8(ctx->base + reg); base 1774 drivers/platform/x86/mlx-platform.c iowrite8(val, ctx->base + reg); base 2099 drivers/platform/x86/mlx-platform.c mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, base 2101 drivers/platform/x86/mlx-platform.c if (!mlxplat_mlxcpld_regmap_ctx.base) { base 462 drivers/platform/x86/pmc_atom.c clk_data->base = pmc_regmap; /* offset is added by client */ base 1766 drivers/platform/x86/sony-laptop.c unsigned int base; base 1784 drivers/platform/x86/sony-laptop.c (value << 0x10) | (kbdbl_ctl->base), &result)) base 1790 drivers/platform/x86/sony-laptop.c (value << 0x0f) | (kbdbl_ctl->base + 0x100), base 1834 drivers/platform/x86/sony-laptop.c (kbdbl_ctl->base + 0x200), &result)) base 1919 drivers/platform/x86/sony-laptop.c kbdbl_ctl->base = ctl_base; base 472 drivers/pnp/isapnp/core.c resource_size_t base, len; base 475 drivers/pnp/isapnp/core.c base = (tmp[1] << 8) | tmp[0]; base 477 drivers/pnp/isapnp/core.c pnp_register_port_resource(dev, option_flags, base, base, 0, len, base 531 drivers/pnp/isapnp/core.c resource_size_t base, len; base 535 drivers/pnp/isapnp/core.c base = (tmp[4] << 24) | (tmp[3] << 16) | (tmp[2] << 8) | tmp[1]; base 538 drivers/pnp/isapnp/core.c pnp_register_mem_resource(dev, option_flags, base, base, 0, len, flags); base 253 drivers/pnp/pnpbios/rsparser.c resource_size_t base, len; base 256 drivers/pnp/pnpbios/rsparser.c base = (p[7] << 24) | (p[6] << 16) | (p[5] << 8) | p[4]; base 259 drivers/pnp/pnpbios/rsparser.c pnp_register_mem_resource(dev, option_flags, base, base, 0, len, flags); base 308 drivers/pnp/pnpbios/rsparser.c resource_size_t base, len; base 310 drivers/pnp/pnpbios/rsparser.c base = (p[2] << 8) | p[1]; base 312 drivers/pnp/pnpbios/rsparser.c pnp_register_port_resource(dev, option_flags, base, base, 0, len, base 504 drivers/pnp/pnpbios/rsparser.c unsigned long base; base 508 drivers/pnp/pnpbios/rsparser.c base = res->start; base 511 drivers/pnp/pnpbios/rsparser.c base = 0; base 515 drivers/pnp/pnpbios/rsparser.c p[4] = (base >> 8) & 0xff; base 516 drivers/pnp/pnpbios/rsparser.c p[5] = ((base >> 8) >> 8) & 0xff; base 517 drivers/pnp/pnpbios/rsparser.c p[6] = (base >> 8) & 0xff; base 518 drivers/pnp/pnpbios/rsparser.c p[7] = ((base >> 8) >> 8) & 0xff; base 522 drivers/pnp/pnpbios/rsparser.c pnp_dbg(&dev->dev, " encode mem %#lx-%#lx\n", base, base + len - 1); base 528 drivers/pnp/pnpbios/rsparser.c unsigned long base; base 532 drivers/pnp/pnpbios/rsparser.c base = res->start; base 535 drivers/pnp/pnpbios/rsparser.c base = 0; base 539 drivers/pnp/pnpbios/rsparser.c p[4] = base & 0xff; base 540 drivers/pnp/pnpbios/rsparser.c p[5] = (base >> 8) & 0xff; base 541 drivers/pnp/pnpbios/rsparser.c p[6] = (base >> 16) & 0xff; base 542 drivers/pnp/pnpbios/rsparser.c p[7] = (base >> 24) & 0xff; base 543 drivers/pnp/pnpbios/rsparser.c p[8] = base & 0xff; base 544 drivers/pnp/pnpbios/rsparser.c p[9] = (base >> 8) & 0xff; base 545 drivers/pnp/pnpbios/rsparser.c p[10] = (base >> 16) & 0xff; base 546 drivers/pnp/pnpbios/rsparser.c p[11] = (base >> 24) & 0xff; base 552 drivers/pnp/pnpbios/rsparser.c pnp_dbg(&dev->dev, " encode mem32 %#lx-%#lx\n", base, base + len - 1); base 558 drivers/pnp/pnpbios/rsparser.c unsigned long base; base 562 drivers/pnp/pnpbios/rsparser.c base = res->start; base 565 drivers/pnp/pnpbios/rsparser.c base = 0; base 569 drivers/pnp/pnpbios/rsparser.c p[4] = base & 0xff; base 570 drivers/pnp/pnpbios/rsparser.c p[5] = (base >> 8) & 0xff; base 571 drivers/pnp/pnpbios/rsparser.c p[6] = (base >> 16) & 0xff; base 572 drivers/pnp/pnpbios/rsparser.c p[7] = (base >> 24) & 0xff; base 578 drivers/pnp/pnpbios/rsparser.c pnp_dbg(&dev->dev, " encode fixed_mem32 %#lx-%#lx\n", base, base 579 drivers/pnp/pnpbios/rsparser.c base + len - 1); base 616 drivers/pnp/pnpbios/rsparser.c unsigned long base; base 620 drivers/pnp/pnpbios/rsparser.c base = res->start; base 623 drivers/pnp/pnpbios/rsparser.c base = 0; base 627 drivers/pnp/pnpbios/rsparser.c p[2] = base & 0xff; base 628 drivers/pnp/pnpbios/rsparser.c p[3] = (base >> 8) & 0xff; base 629 drivers/pnp/pnpbios/rsparser.c p[4] = base & 0xff; base 630 drivers/pnp/pnpbios/rsparser.c p[5] = (base >> 8) & 0xff; base 633 drivers/pnp/pnpbios/rsparser.c pnp_dbg(&dev->dev, " encode io %#lx-%#lx\n", base, base + len - 1); base 639 drivers/pnp/pnpbios/rsparser.c unsigned long base = res->start; base 643 drivers/pnp/pnpbios/rsparser.c base = res->start; base 646 drivers/pnp/pnpbios/rsparser.c base = 0; base 650 drivers/pnp/pnpbios/rsparser.c p[1] = base & 0xff; base 651 drivers/pnp/pnpbios/rsparser.c p[2] = (base >> 8) & 0xff; base 654 drivers/pnp/pnpbios/rsparser.c pnp_dbg(&dev->dev, " encode fixed_io %#lx-%#lx\n", base, base 655 drivers/pnp/pnpbios/rsparser.c base + len - 1); base 41 drivers/power/avs/smartreflex.c __raw_writel(value, (sr->base + offset)); base 63 drivers/power/avs/smartreflex.c reg_val = __raw_readl(sr->base + offset); base 70 drivers/power/avs/smartreflex.c __raw_writel(reg_val, (sr->base + offset)); base 75 drivers/power/avs/smartreflex.c return __raw_readl(sr->base + offset); base 848 drivers/power/avs/smartreflex.c sr_info->base = devm_ioremap_resource(&pdev->dev, mem); base 849 drivers/power/avs/smartreflex.c if (IS_ERR(sr_info->base)) { base 851 drivers/power/avs/smartreflex.c return PTR_ERR(sr_info->base); base 33 drivers/power/reset/gemini-poweroff.c void __iomem *base; base 42 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_CTRLREG); base 44 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); base 46 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_STATREG); base 82 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_CTRLREG); base 84 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); base 88 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); base 105 drivers/power/reset/gemini-poweroff.c gpw->base = devm_ioremap_resource(dev, res); base 106 drivers/power/reset/gemini-poweroff.c if (IS_ERR(gpw->base)) base 107 drivers/power/reset/gemini-poweroff.c return PTR_ERR(gpw->base); base 115 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_IDREG); base 129 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_CTRLREG); base 131 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); base 134 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_CTRLREG); base 136 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); base 139 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_STATREG); base 141 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_STATREG); base 144 drivers/power/reset/gemini-poweroff.c val = readl(gpw->base + GEMINI_PWC_CTRLREG); base 146 drivers/power/reset/gemini-poweroff.c writel(val, gpw->base + GEMINI_PWC_CTRLREG); base 21 drivers/power/reset/hisi-reboot.c static void __iomem *base; base 27 drivers/power/reset/hisi-reboot.c writel_relaxed(0xdeadbeef, base + reboot_offset); base 45 drivers/power/reset/hisi-reboot.c base = of_iomap(np, 0); base 46 drivers/power/reset/hisi-reboot.c if (!base) { base 53 drivers/power/reset/hisi-reboot.c iounmap(base); base 61 drivers/power/reset/hisi-reboot.c iounmap(base); base 19 drivers/power/reset/ocelot-reset.c void __iomem *base; base 52 drivers/power/reset/ocelot-reset.c writel(SOFT_CHIP_RST, ctx->base); base 71 drivers/power/reset/ocelot-reset.c ctx->base = devm_ioremap_resource(dev, res); base 72 drivers/power/reset/ocelot-reset.c if (IS_ERR(ctx->base)) base 73 drivers/power/reset/ocelot-reset.c return PTR_ERR(ctx->base); base 22 drivers/power/reset/qnap-poweroff.c #define UART1_REG(x) (base + ((UART_##x) << 2)) base 50 drivers/power/reset/qnap-poweroff.c static void __iomem *base; base 90 drivers/power/reset/qnap-poweroff.c base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); base 91 drivers/power/reset/qnap-poweroff.c if (!base) { base 18 drivers/power/reset/zx-reboot.c static void __iomem *base; base 24 drivers/power/reset/zx-reboot.c writel_relaxed(1, base + 0xb0); base 43 drivers/power/reset/zx-reboot.c base = of_iomap(np, 0); base 44 drivers/power/reset/zx-reboot.c if (!base) { base 53 drivers/power/reset/zx-reboot.c iounmap(base); base 60 drivers/power/reset/zx-reboot.c iounmap(base); base 290 drivers/power/supply/sbs-manager.c gc->base = -1; base 63 drivers/power/supply/sc2731_charger.c u32 base; base 69 drivers/power/supply/sc2731_charger.c regmap_update_bits(info->regmap, info->base + SC2731_CHG_CFG0, base 72 drivers/power/supply/sc2731_charger.c regmap_update_bits(info->regmap, info->base + SC2731_CHG_CFG0, base 81 drivers/power/supply/sc2731_charger.c ret = regmap_update_bits(info->regmap, info->base + SC2731_CHG_CFG0, base 87 drivers/power/supply/sc2731_charger.c return regmap_update_bits(info->regmap, info->base + SC2731_CHG_CFG0, base 105 drivers/power/supply/sc2731_charger.c return regmap_update_bits(info->regmap, info->base + SC2731_CHG_CFG5, base 124 drivers/power/supply/sc2731_charger.c ret = regmap_update_bits(info->regmap, info->base + SC2731_CHG_CFG0, base 130 drivers/power/supply/sc2731_charger.c return regmap_update_bits(info->regmap, info->base + SC2731_CHG_CFG1, base 155 drivers/power/supply/sc2731_charger.c ret = regmap_read(info->regmap, info->base + SC2731_CHG_CFG1, &val); base 171 drivers/power/supply/sc2731_charger.c ret = regmap_read(info->regmap, info->base + SC2731_CHG_CFG5, &val); base 416 drivers/power/supply/sc2731_charger.c ret = regmap_update_bits(info->regmap, info->base + SC2731_CHG_CFG2, base 422 drivers/power/supply/sc2731_charger.c ret = regmap_update_bits(info->regmap, info->base + SC2731_CHG_CFG0, base 476 drivers/power/supply/sc2731_charger.c ret = of_property_read_u32(np, "reg", &info->base); base 92 drivers/power/supply/sc27xx_fuel_gauge.c u32 base; base 143 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_USER_AREA_STATUS, &status); base 171 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_USER_AREA_CLEAR, base 186 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_USER_AREA_SET, base 206 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_USER_AREA_CLEAR, base 215 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_USER_AREA_CLEAR, base 230 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_USER_AREA_SET, base 249 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_USER_AREA_CLEAR, base 258 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_USER_AREA_STATUS, &value); base 294 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_read(data->regmap, data->base + SC27XX_FGU_CLBCNT_QMAXL, base 307 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_read(data->regmap, data->base + SC27XX_FGU_POCV, &volt); base 333 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_CLBCNT_SETL, base 339 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_CLBCNT_SETH, base 345 drivers/power/supply/sc27xx_fuel_gauge.c return regmap_update_bits(data->regmap, data->base + SC27XX_FGU_START, base 354 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_read(data->regmap, data->base + SC27XX_FGU_CLBCNT_VALL, base 359 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_read(data->regmap, data->base + SC27XX_FGU_CLBCNT_VALH, base 405 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_read(data->regmap, data->base + SC27XX_FGU_VOLTAGE, &vol); base 422 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_read(data->regmap, data->base + SC27XX_FGU_CURRENT, &cur); base 773 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_LOW_OVERLOAD, base 786 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_read(data->regmap, data->base + SC27XX_FGU_INT_STS, base 791 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_INT_CLR, base 954 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_INT_CLR, base 967 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_LOW_OVERLOAD, base 983 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_CLBCNT_DELTL, base 990 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_CLBCNT_DELTH, base 1048 drivers/power/supply/sc27xx_fuel_gauge.c ret = device_property_read_u32(dev, "reg", &data->base); base 1144 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_INT_EN, base 1172 drivers/power/supply/sc27xx_fuel_gauge.c ret = regmap_update_bits(data->regmap, data->base + SC27XX_FGU_INT_EN, base 1191 drivers/power/supply/sc27xx_fuel_gauge.c data->base + SC27XX_FGU_INT_EN, base 1204 drivers/power/supply/sc27xx_fuel_gauge.c regmap_update_bits(data->regmap, data->base + SC27XX_FGU_INT_EN, base 448 drivers/ptp/ptp_qoriq.c int ptp_qoriq_init(struct ptp_qoriq *ptp_qoriq, void __iomem *base, base 460 drivers/ptp/ptp_qoriq.c ptp_qoriq->base = base; base 499 drivers/ptp/ptp_qoriq.c ptp_qoriq->regs.ctrl_regs = base + ETSEC_CTRL_REGS_OFFSET; base 500 drivers/ptp/ptp_qoriq.c ptp_qoriq->regs.alarm_regs = base + ETSEC_ALARM_REGS_OFFSET; base 501 drivers/ptp/ptp_qoriq.c ptp_qoriq->regs.fiper_regs = base + ETSEC_FIPER_REGS_OFFSET; base 502 drivers/ptp/ptp_qoriq.c ptp_qoriq->regs.etts_regs = base + ETSEC_ETTS_REGS_OFFSET; base 504 drivers/ptp/ptp_qoriq.c ptp_qoriq->regs.ctrl_regs = base + CTRL_REGS_OFFSET; base 505 drivers/ptp/ptp_qoriq.c ptp_qoriq->regs.alarm_regs = base + ALARM_REGS_OFFSET; base 506 drivers/ptp/ptp_qoriq.c ptp_qoriq->regs.fiper_regs = base + FIPER_REGS_OFFSET; base 507 drivers/ptp/ptp_qoriq.c ptp_qoriq->regs.etts_regs = base + ETTS_REGS_OFFSET; base 552 drivers/ptp/ptp_qoriq.c iounmap(ptp_qoriq->base); base 561 drivers/ptp/ptp_qoriq.c void __iomem *base; base 592 drivers/ptp/ptp_qoriq.c base = ioremap(ptp_qoriq->rsrc->start, base 594 drivers/ptp/ptp_qoriq.c if (!base) { base 599 drivers/ptp/ptp_qoriq.c err = ptp_qoriq_init(ptp_qoriq, base, &ptp_qoriq_caps); base 607 drivers/ptp/ptp_qoriq.c iounmap(ptp_qoriq->base); base 70 drivers/pwm/core.c bitmap_clear(allocated_pwms, chip->base, chip->npwm); base 266 drivers/pwm/core.c ret = alloc_pwms(chip->base, chip->npwm); base 276 drivers/pwm/core.c chip->base = ret; base 282 drivers/pwm/core.c pwm->pwm = chip->base + i; base 292 drivers/pwm/core.c bitmap_set(allocated_pwms, chip->base, chip->npwm); base 45 drivers/pwm/pwm-ab8500.c reg = AB8500_PWM_OUT_CTRL1_REG + ((chip->base - 1) * 2); base 63 drivers/pwm/pwm-ab8500.c 1 << (chip->base - 1), 1 << (chip->base - 1)); base 76 drivers/pwm/pwm-ab8500.c 1 << (chip->base - 1), 0); base 104 drivers/pwm/pwm-ab8500.c ab8500->chip.base = pdev->id; base 268 drivers/pwm/pwm-atmel-hlcdc.c chip->chip.base = -1; base 411 drivers/pwm/pwm-atmel-tcb.c tcbpwm->chip.base = -1; base 464 drivers/pwm/pwm-atmel-tcb.c void __iomem *base = tcbpwm->tc->regs; base 470 drivers/pwm/pwm-atmel-tcb.c chan->cmr = readl(base + ATMEL_TC_REG(i, CMR)); base 471 drivers/pwm/pwm-atmel-tcb.c chan->ra = readl(base + ATMEL_TC_REG(i, RA)); base 472 drivers/pwm/pwm-atmel-tcb.c chan->rb = readl(base + ATMEL_TC_REG(i, RB)); base 473 drivers/pwm/pwm-atmel-tcb.c chan->rc = readl(base + ATMEL_TC_REG(i, RC)); base 481 drivers/pwm/pwm-atmel-tcb.c void __iomem *base = tcbpwm->tc->regs; base 487 drivers/pwm/pwm-atmel-tcb.c writel(chan->cmr, base + ATMEL_TC_REG(i, CMR)); base 488 drivers/pwm/pwm-atmel-tcb.c writel(chan->ra, base + ATMEL_TC_REG(i, RA)); base 489 drivers/pwm/pwm-atmel-tcb.c writel(chan->rb, base + ATMEL_TC_REG(i, RB)); base 490 drivers/pwm/pwm-atmel-tcb.c writel(chan->rc, base + ATMEL_TC_REG(i, RC)); base 493 drivers/pwm/pwm-atmel-tcb.c base + ATMEL_TC_REG(i, CCR)); base 70 drivers/pwm/pwm-atmel.c void __iomem *base; base 86 drivers/pwm/pwm-atmel.c return readl_relaxed(chip->base + offset); base 92 drivers/pwm/pwm-atmel.c writel_relaxed(val, chip->base + offset); base 98 drivers/pwm/pwm-atmel.c unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE; base 100 drivers/pwm/pwm-atmel.c return readl_relaxed(chip->base + base + offset); base 107 drivers/pwm/pwm-atmel.c unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE; base 109 drivers/pwm/pwm-atmel.c writel_relaxed(val, chip->base + base + offset); base 355 drivers/pwm/pwm-atmel.c atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res); base 356 drivers/pwm/pwm-atmel.c if (IS_ERR(atmel_pwm->base)) base 357 drivers/pwm/pwm-atmel.c return PTR_ERR(atmel_pwm->base); base 373 drivers/pwm/pwm-atmel.c atmel_pwm->chip.base = -1; base 48 drivers/pwm/pwm-bcm-iproc.c void __iomem *base; base 61 drivers/pwm/pwm-bcm-iproc.c value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); base 63 drivers/pwm/pwm-bcm-iproc.c writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); base 73 drivers/pwm/pwm-bcm-iproc.c value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); base 75 drivers/pwm/pwm-bcm-iproc.c writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); base 90 drivers/pwm/pwm-bcm-iproc.c value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); base 102 drivers/pwm/pwm-bcm-iproc.c value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET); base 108 drivers/pwm/pwm-bcm-iproc.c value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); base 112 drivers/pwm/pwm-bcm-iproc.c value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); base 162 drivers/pwm/pwm-bcm-iproc.c value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET); base 165 drivers/pwm/pwm-bcm-iproc.c writel(value, ip->base + IPROC_PWM_PRESCALE_OFFSET); base 168 drivers/pwm/pwm-bcm-iproc.c writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); base 169 drivers/pwm/pwm-bcm-iproc.c writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); base 172 drivers/pwm/pwm-bcm-iproc.c value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); base 179 drivers/pwm/pwm-bcm-iproc.c writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); base 209 drivers/pwm/pwm-bcm-iproc.c ip->chip.base = -1; base 215 drivers/pwm/pwm-bcm-iproc.c ip->base = devm_ioremap_resource(&pdev->dev, res); base 216 drivers/pwm/pwm-bcm-iproc.c if (IS_ERR(ip->base)) base 217 drivers/pwm/pwm-bcm-iproc.c return PTR_ERR(ip->base); base 233 drivers/pwm/pwm-bcm-iproc.c value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); base 240 drivers/pwm/pwm-bcm-iproc.c writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); base 70 drivers/pwm/pwm-bcm-kona.c void __iomem *base; base 85 drivers/pwm/pwm-bcm-kona.c unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); base 89 drivers/pwm/pwm-bcm-kona.c writel(value, kp->base + PWM_CONTROL_OFFSET); base 100 drivers/pwm/pwm-bcm-kona.c unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); base 105 drivers/pwm/pwm-bcm-kona.c writel(value, kp->base + PWM_CONTROL_OFFSET); base 161 drivers/pwm/pwm-bcm-kona.c value = readl(kp->base + PRESCALE_OFFSET); base 164 drivers/pwm/pwm-bcm-kona.c writel(value, kp->base + PRESCALE_OFFSET); base 166 drivers/pwm/pwm-bcm-kona.c writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan)); base 168 drivers/pwm/pwm-bcm-kona.c writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan)); base 192 drivers/pwm/pwm-bcm-kona.c value = readl(kp->base + PWM_CONTROL_OFFSET); base 199 drivers/pwm/pwm-bcm-kona.c writel(value, kp->base + PWM_CONTROL_OFFSET); base 238 drivers/pwm/pwm-bcm-kona.c writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan)); base 239 drivers/pwm/pwm-bcm-kona.c writel(0, kp->base + PERIOD_COUNT_OFFSET(chan)); base 242 drivers/pwm/pwm-bcm-kona.c value = readl(kp->base + PRESCALE_OFFSET); base 244 drivers/pwm/pwm-bcm-kona.c writel(value, kp->base + PRESCALE_OFFSET); base 275 drivers/pwm/pwm-bcm-kona.c kp->chip.base = -1; base 281 drivers/pwm/pwm-bcm-kona.c kp->base = devm_ioremap_resource(&pdev->dev, res); base 282 drivers/pwm/pwm-bcm-kona.c if (IS_ERR(kp->base)) base 283 drivers/pwm/pwm-bcm-kona.c return PTR_ERR(kp->base); base 302 drivers/pwm/pwm-bcm-kona.c writel(value, kp->base + PWM_CONTROL_OFFSET); base 29 drivers/pwm/pwm-bcm2835.c void __iomem *base; base 43 drivers/pwm/pwm-bcm2835.c value = readl(pc->base + PWM_CONTROL); base 46 drivers/pwm/pwm-bcm2835.c writel(value, pc->base + PWM_CONTROL); base 56 drivers/pwm/pwm-bcm2835.c value = readl(pc->base + PWM_CONTROL); base 58 drivers/pwm/pwm-bcm2835.c writel(value, pc->base + PWM_CONTROL); base 81 drivers/pwm/pwm-bcm2835.c pc->base + DUTY(pwm->hwpwm)); base 82 drivers/pwm/pwm-bcm2835.c writel(period, pc->base + PERIOD(pwm->hwpwm)); base 92 drivers/pwm/pwm-bcm2835.c value = readl(pc->base + PWM_CONTROL); base 94 drivers/pwm/pwm-bcm2835.c writel(value, pc->base + PWM_CONTROL); base 104 drivers/pwm/pwm-bcm2835.c value = readl(pc->base + PWM_CONTROL); base 106 drivers/pwm/pwm-bcm2835.c writel(value, pc->base + PWM_CONTROL); base 115 drivers/pwm/pwm-bcm2835.c value = readl(pc->base + PWM_CONTROL); base 122 drivers/pwm/pwm-bcm2835.c writel(value, pc->base + PWM_CONTROL); base 150 drivers/pwm/pwm-bcm2835.c pc->base = devm_ioremap_resource(&pdev->dev, res); base 151 drivers/pwm/pwm-bcm2835.c if (IS_ERR(pc->base)) base 152 drivers/pwm/pwm-bcm2835.c return PTR_ERR(pc->base); base 169 drivers/pwm/pwm-bcm2835.c pc->chip.base = -1; base 51 drivers/pwm/pwm-berlin.c void __iomem *base; base 62 drivers/pwm/pwm-berlin.c return readl_relaxed(chip->base + channel * 0x10 + offset); base 69 drivers/pwm/pwm-berlin.c writel_relaxed(value, chip->base + channel * 0x10 + offset); base 197 drivers/pwm/pwm-berlin.c pwm->base = devm_ioremap_resource(&pdev->dev, res); base 198 drivers/pwm/pwm-berlin.c if (IS_ERR(pwm->base)) base 199 drivers/pwm/pwm-berlin.c return PTR_ERR(pwm->base); base 211 drivers/pwm/pwm-berlin.c pwm->chip.base = -1; base 55 drivers/pwm/pwm-brcmstb.c void __iomem *base; base 65 drivers/pwm/pwm-brcmstb.c return __raw_readl(p->base + offset); base 67 drivers/pwm/pwm-brcmstb.c return readl_relaxed(p->base + offset); base 74 drivers/pwm/pwm-brcmstb.c __raw_writel(value, p->base + offset); base 76 drivers/pwm/pwm-brcmstb.c writel_relaxed(value, p->base + offset); base 262 drivers/pwm/pwm-brcmstb.c p->chip.base = -1; base 266 drivers/pwm/pwm-brcmstb.c p->base = devm_ioremap_resource(&pdev->dev, res); base 267 drivers/pwm/pwm-brcmstb.c if (IS_ERR(p->base)) { base 268 drivers/pwm/pwm-brcmstb.c ret = PTR_ERR(p->base); base 133 drivers/pwm/pwm-clps711x.c priv->chip.base = -1; base 109 drivers/pwm/pwm-crc.c pwm->chip.base = -1; base 209 drivers/pwm/pwm-cros-ec.c chip->base = -1; base 37 drivers/pwm/pwm-ep93xx.c void __iomem *base; base 65 drivers/pwm/pwm-ep93xx.c void __iomem *base = ep93xx_pwm->base; base 93 drivers/pwm/pwm-ep93xx.c term = readw(base + EP93XX_PWMx_TERM_COUNT); base 97 drivers/pwm/pwm-ep93xx.c writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT); base 98 drivers/pwm/pwm-ep93xx.c writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE); base 100 drivers/pwm/pwm-ep93xx.c writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE); base 101 drivers/pwm/pwm-ep93xx.c writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT); base 128 drivers/pwm/pwm-ep93xx.c writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_INVERT); base 130 drivers/pwm/pwm-ep93xx.c writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_INVERT); base 146 drivers/pwm/pwm-ep93xx.c writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_ENABLE); base 155 drivers/pwm/pwm-ep93xx.c writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE); base 180 drivers/pwm/pwm-ep93xx.c ep93xx_pwm->base = devm_ioremap_resource(&pdev->dev, res); base 181 drivers/pwm/pwm-ep93xx.c if (IS_ERR(ep93xx_pwm->base)) base 182 drivers/pwm/pwm-ep93xx.c return PTR_ERR(ep93xx_pwm->base); base 190 drivers/pwm/pwm-ep93xx.c ep93xx_pwm->chip.base = -1; base 403 drivers/pwm/pwm-fsl-ftm.c void __iomem *base; base 416 drivers/pwm/pwm-fsl-ftm.c base = devm_ioremap_resource(&pdev->dev, res); base 417 drivers/pwm/pwm-fsl-ftm.c if (IS_ERR(base)) base 418 drivers/pwm/pwm-fsl-ftm.c return PTR_ERR(base); base 420 drivers/pwm/pwm-fsl-ftm.c fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base, base 458 drivers/pwm/pwm-fsl-ftm.c fpc->chip.base = -1; base 38 drivers/pwm/pwm-hibvt.c void __iomem *base; base 71 drivers/pwm/pwm-hibvt.c static void hibvt_pwm_set_bits(void __iomem *base, u32 offset, base 74 drivers/pwm/pwm-hibvt.c void __iomem *address = base + offset; base 87 drivers/pwm/pwm-hibvt.c hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), base 95 drivers/pwm/pwm-hibvt.c hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), base 110 drivers/pwm/pwm-hibvt.c hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), base 113 drivers/pwm/pwm-hibvt.c hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), base 124 drivers/pwm/pwm-hibvt.c hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), base 127 drivers/pwm/pwm-hibvt.c hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), base 135 drivers/pwm/pwm-hibvt.c void __iomem *base; base 139 drivers/pwm/pwm-hibvt.c base = hi_pwm_chip->base; base 141 drivers/pwm/pwm-hibvt.c value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm)); base 144 drivers/pwm/pwm-hibvt.c value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm)); base 147 drivers/pwm/pwm-hibvt.c value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm)); base 210 drivers/pwm/pwm-hibvt.c pwm_chip->chip.base = -1; base 217 drivers/pwm/pwm-hibvt.c pwm_chip->base = devm_ioremap_resource(&pdev->dev, res); base 218 drivers/pwm/pwm-hibvt.c if (IS_ERR(pwm_chip->base)) base 219 drivers/pwm/pwm-hibvt.c return PTR_ERR(pwm_chip->base); base 242 drivers/pwm/pwm-hibvt.c hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i), base 66 drivers/pwm/pwm-img.c void __iomem *base; base 83 drivers/pwm/pwm-img.c writel(val, chip->base + reg); base 89 drivers/pwm/pwm-img.c return readl(chip->base + reg); base 252 drivers/pwm/pwm-img.c pwm->base = devm_ioremap_resource(&pdev->dev, res); base 253 drivers/pwm/pwm-img.c if (IS_ERR(pwm->base)) base 254 drivers/pwm/pwm-img.c return PTR_ERR(pwm->base); base 305 drivers/pwm/pwm-img.c pwm->chip.base = -1; base 64 drivers/pwm/pwm-imx-tpm.c void __iomem *base; base 150 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_SC); base 152 drivers/pwm/pwm-imx-tpm.c tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); base 157 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); base 194 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_SC); base 203 drivers/pwm/pwm-imx-tpm.c writel(val, tpm->base + PWM_IMX_TPM_SC); base 213 drivers/pwm/pwm-imx-tpm.c writel(p->mod, tpm->base + PWM_IMX_TPM_MOD); base 233 drivers/pwm/pwm-imx-tpm.c writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); base 241 drivers/pwm/pwm-imx-tpm.c while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod base 242 drivers/pwm/pwm-imx-tpm.c || readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)) base 256 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); base 272 drivers/pwm/pwm-imx-tpm.c writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); base 276 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_SC); base 284 drivers/pwm/pwm-imx-tpm.c writel(val, tpm->base + PWM_IMX_TPM_SC); base 350 drivers/pwm/pwm-imx-tpm.c tpm->base = devm_platform_ioremap_resource(pdev, 0); base 351 drivers/pwm/pwm-imx-tpm.c if (IS_ERR(tpm->base)) base 352 drivers/pwm/pwm-imx-tpm.c return PTR_ERR(tpm->base); base 372 drivers/pwm/pwm-imx-tpm.c tpm->chip.base = -1; base 377 drivers/pwm/pwm-imx-tpm.c val = readl(tpm->base + PWM_IMX_TPM_PARAM); base 168 drivers/pwm/pwm-imx1.c imx->chip.base = -1; base 326 drivers/pwm/pwm-imx27.c imx->chip.base = -1; base 168 drivers/pwm/pwm-jz4740.c jz4740->chip.base = -1; base 94 drivers/pwm/pwm-lpc18xx-sct.c void __iomem *base; base 115 drivers/pwm/pwm-lpc18xx-sct.c writel(val, lpc18xx_pwm->base + reg); base 121 drivers/pwm/pwm-lpc18xx-sct.c return readl(lpc18xx_pwm->base + reg); base 340 drivers/pwm/pwm-lpc18xx-sct.c lpc18xx_pwm->base = devm_ioremap_resource(&pdev->dev, res); base 341 drivers/pwm/pwm-lpc18xx-sct.c if (IS_ERR(lpc18xx_pwm->base)) base 342 drivers/pwm/pwm-lpc18xx-sct.c return PTR_ERR(lpc18xx_pwm->base); base 375 drivers/pwm/pwm-lpc18xx-sct.c lpc18xx_pwm->chip.base = -1; base 20 drivers/pwm/pwm-lpc32xx.c void __iomem *base; base 54 drivers/pwm/pwm-lpc32xx.c val = readl(lpc32xx->base + (pwm->hwpwm << 2)); base 57 drivers/pwm/pwm-lpc32xx.c writel(val, lpc32xx->base + (pwm->hwpwm << 2)); base 72 drivers/pwm/pwm-lpc32xx.c val = readl(lpc32xx->base + (pwm->hwpwm << 2)); base 74 drivers/pwm/pwm-lpc32xx.c writel(val, lpc32xx->base + (pwm->hwpwm << 2)); base 84 drivers/pwm/pwm-lpc32xx.c val = readl(lpc32xx->base + (pwm->hwpwm << 2)); base 86 drivers/pwm/pwm-lpc32xx.c writel(val, lpc32xx->base + (pwm->hwpwm << 2)); base 110 drivers/pwm/pwm-lpc32xx.c lpc32xx->base = devm_ioremap_resource(&pdev->dev, res); base 111 drivers/pwm/pwm-lpc32xx.c if (IS_ERR(lpc32xx->base)) base 112 drivers/pwm/pwm-lpc32xx.c return PTR_ERR(lpc32xx->base); base 121 drivers/pwm/pwm-lpc32xx.c lpc32xx->chip.base = -1; base 130 drivers/pwm/pwm-lpc32xx.c val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); base 132 drivers/pwm/pwm-lpc32xx.c writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); base 226 drivers/pwm/pwm-lpss.c lpwm->chip.base = -1; base 261 drivers/pwm/pwm-mediatek.c pc->chip.base = -1; base 107 drivers/pwm/pwm-meson.c void __iomem *base; base 236 drivers/pwm/pwm-meson.c value = readl(meson->base + REG_MISC_AB); base 240 drivers/pwm/pwm-meson.c writel(value, meson->base + REG_MISC_AB); base 244 drivers/pwm/pwm-meson.c writel(value, meson->base + channel_data->reg_offset); base 246 drivers/pwm/pwm-meson.c value = readl(meson->base + REG_MISC_AB); base 248 drivers/pwm/pwm-meson.c writel(value, meson->base + REG_MISC_AB); base 260 drivers/pwm/pwm-meson.c value = readl(meson->base + REG_MISC_AB); base 262 drivers/pwm/pwm-meson.c writel(value, meson->base + REG_MISC_AB); base 344 drivers/pwm/pwm-meson.c value = readl(meson->base + REG_MISC_AB); base 352 drivers/pwm/pwm-meson.c value = readl(meson->base + channel_data->reg_offset); base 511 drivers/pwm/pwm-meson.c channel->mux.reg = meson->base + REG_MISC_AB; base 548 drivers/pwm/pwm-meson.c meson->base = devm_ioremap_resource(&pdev->dev, regs); base 549 drivers/pwm/pwm-meson.c if (IS_ERR(meson->base)) base 550 drivers/pwm/pwm-meson.c return PTR_ERR(meson->base); base 555 drivers/pwm/pwm-meson.c meson->chip.base = -1; base 49 drivers/pwm/pwm-mtk-disp.c void __iomem *base; base 60 drivers/pwm/pwm-mtk-disp.c void __iomem *address = mdp->base + offset; base 185 drivers/pwm/pwm-mtk-disp.c mdp->base = devm_ioremap_resource(&pdev->dev, r); base 186 drivers/pwm/pwm-mtk-disp.c if (IS_ERR(mdp->base)) base 187 drivers/pwm/pwm-mtk-disp.c return PTR_ERR(mdp->base); base 207 drivers/pwm/pwm-mtk-disp.c mdp->chip.base = -1; base 39 drivers/pwm/pwm-mxs.c void __iomem *base; base 81 drivers/pwm/pwm-mxs.c mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20); base 84 drivers/pwm/pwm-mxs.c mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20); base 104 drivers/pwm/pwm-mxs.c writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET); base 113 drivers/pwm/pwm-mxs.c writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR); base 135 drivers/pwm/pwm-mxs.c mxs->base = devm_platform_ioremap_resource(pdev, 0); base 136 drivers/pwm/pwm-mxs.c if (IS_ERR(mxs->base)) base 137 drivers/pwm/pwm-mxs.c return PTR_ERR(mxs->base); base 145 drivers/pwm/pwm-mxs.c mxs->chip.base = -1; base 161 drivers/pwm/pwm-mxs.c ret = stmp_reset_block(mxs->base); base 327 drivers/pwm/pwm-omap-dmtimer.c omap->chip.base = -1; base 212 drivers/pwm/pwm-pca9685.c pca->gpio.base = -1; base 491 drivers/pwm/pwm-pca9685.c pca->chip.base = -1; base 25 drivers/pwm/pwm-puv3.c void __iomem *base; base 70 drivers/pwm/pwm-puv3.c writel(prescale, puv3->base + OST_PWM_PWCR); base 71 drivers/pwm/pwm-puv3.c writel(pv - dc, puv3->base + OST_PWM_DCCR); base 72 drivers/pwm/pwm-puv3.c writel(pv, puv3->base + OST_PWM_PCR); base 115 drivers/pwm/pwm-puv3.c puv3->base = devm_ioremap_resource(&pdev->dev, r); base 116 drivers/pwm/pwm-puv3.c if (IS_ERR(puv3->base)) base 117 drivers/pwm/pwm-puv3.c return PTR_ERR(puv3->base); base 121 drivers/pwm/pwm-puv3.c puv3->chip.base = -1; base 188 drivers/pwm/pwm-pxa.c pwm->chip.base = -1; base 39 drivers/pwm/pwm-rcar.c void __iomem *base; base 51 drivers/pwm/pwm-rcar.c writel(data, rp->base + offset); base 56 drivers/pwm/pwm-rcar.c return readl(rp->base + offset); base 214 drivers/pwm/pwm-rcar.c rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res); base 215 drivers/pwm/pwm-rcar.c if (IS_ERR(rcar_pwm->base)) base 216 drivers/pwm/pwm-rcar.c return PTR_ERR(rcar_pwm->base); base 228 drivers/pwm/pwm-rcar.c rcar_pwm->chip.base = -1; base 86 drivers/pwm/pwm-renesas-tpu.c void __iomem *base; base 94 drivers/pwm/pwm-renesas-tpu.c void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET base 97 drivers/pwm/pwm-renesas-tpu.c iowrite16(value, base + reg_nr); base 133 drivers/pwm/pwm-renesas-tpu.c value = ioread16(pwm->tpu->base + TPU_TSTR); base 140 drivers/pwm/pwm-renesas-tpu.c iowrite16(value, pwm->tpu->base + TPU_TSTR); base 398 drivers/pwm/pwm-renesas-tpu.c tpu->base = devm_ioremap_resource(&pdev->dev, res); base 399 drivers/pwm/pwm-renesas-tpu.c if (IS_ERR(tpu->base)) base 400 drivers/pwm/pwm-renesas-tpu.c return PTR_ERR(tpu->base); base 415 drivers/pwm/pwm-renesas-tpu.c tpu->chip.base = -1; base 37 drivers/pwm/pwm-rockchip.c void __iomem *base; base 77 drivers/pwm/pwm-rockchip.c tmp = readl_relaxed(pc->base + pc->data->regs.period); base 81 drivers/pwm/pwm-rockchip.c tmp = readl_relaxed(pc->base + pc->data->regs.duty); base 85 drivers/pwm/pwm-rockchip.c val = readl_relaxed(pc->base + pc->data->regs.ctrl); base 127 drivers/pwm/pwm-rockchip.c ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); base 130 drivers/pwm/pwm-rockchip.c writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl); base 133 drivers/pwm/pwm-rockchip.c writel(period, pc->base + pc->data->regs.period); base 134 drivers/pwm/pwm-rockchip.c writel(duty, pc->base + pc->data->regs.duty); base 152 drivers/pwm/pwm-rockchip.c writel(ctrl, pc->base + pc->data->regs.ctrl); base 170 drivers/pwm/pwm-rockchip.c val = readl_relaxed(pc->base + pc->data->regs.ctrl); base 177 drivers/pwm/pwm-rockchip.c writel_relaxed(val, pc->base + pc->data->regs.ctrl); base 307 drivers/pwm/pwm-rockchip.c pc->base = devm_ioremap_resource(&pdev->dev, r); base 308 drivers/pwm/pwm-rockchip.c if (IS_ERR(pc->base)) base 309 drivers/pwm/pwm-rockchip.c return PTR_ERR(pc->base); base 354 drivers/pwm/pwm-rockchip.c pc->chip.base = -1; base 87 drivers/pwm/pwm-samsung.c void __iomem *base; base 132 drivers/pwm/pwm-samsung.c reg = readl(pwm->base + REG_TCFG1); base 135 drivers/pwm/pwm-samsung.c writel(reg, pwm->base + REG_TCFG1); base 145 drivers/pwm/pwm-samsung.c reg = readl(chip->base + REG_TCFG1); base 160 drivers/pwm/pwm-samsung.c reg = readl(chip->base + REG_TCFG0); base 249 drivers/pwm/pwm-samsung.c tcon = readl(our_chip->base + REG_TCON); base 253 drivers/pwm/pwm-samsung.c writel(tcon, our_chip->base + REG_TCON); base 257 drivers/pwm/pwm-samsung.c writel(tcon, our_chip->base + REG_TCON); base 275 drivers/pwm/pwm-samsung.c tcon = readl(our_chip->base + REG_TCON); base 277 drivers/pwm/pwm-samsung.c writel(tcon, our_chip->base + REG_TCON); base 293 drivers/pwm/pwm-samsung.c tcon = readl(chip->base + REG_TCON); base 295 drivers/pwm/pwm-samsung.c writel(tcon, chip->base + REG_TCON); base 298 drivers/pwm/pwm-samsung.c writel(tcon, chip->base + REG_TCON); base 318 drivers/pwm/pwm-samsung.c tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm)); base 319 drivers/pwm/pwm-samsung.c oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm)); base 364 drivers/pwm/pwm-samsung.c writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm)); base 365 drivers/pwm/pwm-samsung.c writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm)); base 399 drivers/pwm/pwm-samsung.c tcon = readl(chip->base + REG_TCON); base 409 drivers/pwm/pwm-samsung.c writel(tcon, chip->base + REG_TCON); base 523 drivers/pwm/pwm-samsung.c chip->chip.base = -1; base 545 drivers/pwm/pwm-samsung.c chip->base = devm_ioremap_resource(&pdev->dev, res); base 546 drivers/pwm/pwm-samsung.c if (IS_ERR(chip->base)) base 547 drivers/pwm/pwm-samsung.c return PTR_ERR(chip->base); base 248 drivers/pwm/pwm-sifive.c chip->base = -1; base 198 drivers/pwm/pwm-spear.c pc->chip.base = -1; base 35 drivers/pwm/pwm-sprd.c void __iomem *base; base 57 drivers/pwm/pwm-sprd.c return readl_relaxed(spc->base + offset); base 65 drivers/pwm/pwm-sprd.c writel_relaxed(val, spc->base + offset); base 261 drivers/pwm/pwm-sprd.c spc->base = devm_platform_ioremap_resource(pdev, 0); base 262 drivers/pwm/pwm-sprd.c if (IS_ERR(spc->base)) base 263 drivers/pwm/pwm-sprd.c return PTR_ERR(spc->base); base 274 drivers/pwm/pwm-sprd.c spc->chip.base = -1; base 630 drivers/pwm/pwm-sti.c pc->chip.base = -1; base 208 drivers/pwm/pwm-stm32-lp.c priv->chip.base = -1; base 623 drivers/pwm/pwm-stm32.c priv->chip.base = -1; base 281 drivers/pwm/pwm-stmpe.c pwm->chip.base = -1; base 81 drivers/pwm/pwm-sun4i.c void __iomem *base; base 96 drivers/pwm/pwm-sun4i.c return readl(chip->base + offset); base 102 drivers/pwm/pwm-sun4i.c writel(val, chip->base + offset); base 360 drivers/pwm/pwm-sun4i.c pwm->base = devm_ioremap_resource(&pdev->dev, res); base 361 drivers/pwm/pwm-sun4i.c if (IS_ERR(pwm->base)) base 362 drivers/pwm/pwm-sun4i.c return PTR_ERR(pwm->base); base 370 drivers/pwm/pwm-sun4i.c pwm->chip.base = -1; base 219 drivers/pwm/pwm-tegra.c pwm->chip.base = -1; base 230 drivers/pwm/pwm-tiecap.c pc->chip.base = -1; base 122 drivers/pwm/pwm-tiehrpwm.c static inline u16 ehrpwm_read(void __iomem *base, unsigned int offset) base 124 drivers/pwm/pwm-tiehrpwm.c return readw(base + offset); base 127 drivers/pwm/pwm-tiehrpwm.c static inline void ehrpwm_write(void __iomem *base, unsigned int offset, base 130 drivers/pwm/pwm-tiehrpwm.c writew(value, base + offset); base 133 drivers/pwm/pwm-tiehrpwm.c static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask, base 138 drivers/pwm/pwm-tiehrpwm.c val = readw(base + offset); base 141 drivers/pwm/pwm-tiehrpwm.c writew(val, base + offset); base 455 drivers/pwm/pwm-tiehrpwm.c pc->chip.base = -1; base 63 drivers/pwm/pwm-twl-led.c int base, ret; base 81 drivers/pwm/pwm-twl-led.c base = pwm->hwpwm * 2 + TWL4030_PWMA_REG; base 85 drivers/pwm/pwm-twl-led.c ret = twl_i2c_write(TWL4030_MODULE_LED, pwm_config, base, 2); base 294 drivers/pwm/pwm-twl-led.c twl->chip.base = -1; base 65 drivers/pwm/pwm-twl.c int base, ret; base 83 drivers/pwm/pwm-twl.c base = pwm->hwpwm * 3; base 87 drivers/pwm/pwm-twl.c ret = twl_i2c_write(TWL_MODULE_PWM, pwm_config, base, 2); base 313 drivers/pwm/pwm-twl.c twl->chip.base = -1; base 52 drivers/pwm/pwm-vt8500.c void __iomem *base; base 64 drivers/pwm/pwm-vt8500.c while ((readl(vt8500->base + REG_STATUS) & mask) && --loops) base 108 drivers/pwm/pwm-vt8500.c writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); base 111 drivers/pwm/pwm-vt8500.c writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); base 114 drivers/pwm/pwm-vt8500.c writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); base 117 drivers/pwm/pwm-vt8500.c val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); base 119 drivers/pwm/pwm-vt8500.c writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); base 138 drivers/pwm/pwm-vt8500.c val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); base 140 drivers/pwm/pwm-vt8500.c writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); base 151 drivers/pwm/pwm-vt8500.c val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); base 153 drivers/pwm/pwm-vt8500.c writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); base 166 drivers/pwm/pwm-vt8500.c val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); base 173 drivers/pwm/pwm-vt8500.c writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); base 213 drivers/pwm/pwm-vt8500.c chip->chip.base = -1; base 223 drivers/pwm/pwm-vt8500.c chip->base = devm_ioremap_resource(&pdev->dev, r); base 224 drivers/pwm/pwm-vt8500.c if (IS_ERR(chip->base)) base 225 drivers/pwm/pwm-vt8500.c return PTR_ERR(chip->base); base 33 drivers/pwm/pwm-zx.c void __iomem *base; base 44 drivers/pwm/pwm-zx.c return readl(zpc->base + (hwpwm + 1) * 0x10 + offset); base 50 drivers/pwm/pwm-zx.c writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset); base 208 drivers/pwm/pwm-zx.c zpc->base = devm_ioremap_resource(&pdev->dev, res); base 209 drivers/pwm/pwm-zx.c if (IS_ERR(zpc->base)) base 210 drivers/pwm/pwm-zx.c return PTR_ERR(zpc->base); base 226 drivers/pwm/pwm-zx.c zpc->chip.base = -1; base 497 drivers/pwm/sysfs.c "pwmchip%d", chip->base); base 868 drivers/rapidio/devices/tsi721.c bar_base = pbar->base; base 889 drivers/rapidio/devices/tsi721.c if (win->base >= bar_base && win->base < bar_end) { base 890 drivers/rapidio/devices/tsi721.c if (win_base < (win->base + win->size) && base 891 drivers/rapidio/devices/tsi721.c (win_base + size) > win->base) { base 893 drivers/rapidio/devices/tsi721.c win_base = win->base + win->size; base 910 drivers/rapidio/devices/tsi721.c new_win->base = win_base; base 958 drivers/rapidio/devices/tsi721.c "allocated OBW%d @%llx", obw, ob_win->base); base 994 drivers/rapidio/devices/tsi721.c iowrite32((u32)(ob_win->base >> 32), priv->regs + TSI721_OBWINUB(obw)); base 995 drivers/rapidio/devices/tsi721.c iowrite32((u32)(ob_win->base & TSI721_OBWINLB_BA) | TSI721_OBWINLB_WEN, base 998 drivers/rapidio/devices/tsi721.c *laddr = ob_win->base; base 1017 drivers/rapidio/devices/tsi721.c "free OBW%d @%llx", i, ob_win->base); base 2801 drivers/rapidio/devices/tsi721.c priv->p2r_bar[0].base = pci_resource_start(pdev, BAR_2); base 2811 drivers/rapidio/devices/tsi721.c priv->p2r_bar[1].base = pci_resource_start(pdev, BAR_4); base 853 drivers/rapidio/devices/tsi721.h u64 base; base 859 drivers/rapidio/devices/tsi721.h u64 base; base 2436 drivers/regulator/core.c lockdep_assert_held_once(&rdev->mutex.base); base 2457 drivers/regulator/core.c lockdep_assert_held_once(&rdev->mutex.base); base 2477 drivers/regulator/core.c lockdep_assert_held_once(&rdev->mutex.base); base 2595 drivers/regulator/core.c lockdep_assert_held_once(&rdev->mutex.base); base 2673 drivers/regulator/core.c lockdep_assert_held_once(&rdev->mutex.base); base 3543 drivers/regulator/core.c lockdep_assert_held_once(&c_rdevs[i]->mutex.base); base 4600 drivers/regulator/core.c lockdep_assert_held_once(&rdev->mutex.base); base 46 drivers/regulator/max8907-regulator.c #define REG_LDO(ids, supply, base, min, max, step) \ base 57 drivers/regulator/max8907-regulator.c .vsel_reg = (base) + MAX8907_VOUT, \ base 59 drivers/regulator/max8907-regulator.c .enable_reg = (base) + MAX8907_CTL, \ base 75 drivers/regulator/max8907-regulator.c #define REG_OUT5V(ids, supply, base, voltage) \ base 85 drivers/regulator/max8907-regulator.c .enable_reg = (base), \ base 89 drivers/regulator/max8907-regulator.c #define REG_BBAT(ids, supply, base, min, max, step) \ base 100 drivers/regulator/max8907-regulator.c .vsel_reg = (base), \ base 104 drivers/regulator/max8907-regulator.c #define LDO_750_50(id, supply, base) REG_LDO(id, supply, (base), \ base 106 drivers/regulator/max8907-regulator.c #define LDO_650_25(id, supply, base) REG_LDO(id, supply, (base), \ base 212 drivers/regulator/pfuze100-regulator.c #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \ base 222 drivers/regulator/pfuze100-regulator.c .enable_reg = (base), \ base 227 drivers/regulator/pfuze100-regulator.c #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \ base 238 drivers/regulator/pfuze100-regulator.c .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ base 240 drivers/regulator/pfuze100-regulator.c .enable_reg = (base) + PFUZE100_MODE_OFFSET, \ base 243 drivers/regulator/pfuze100-regulator.c .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ base 248 drivers/regulator/pfuze100-regulator.c #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \ base 258 drivers/regulator/pfuze100-regulator.c .vsel_reg = (base), \ base 260 drivers/regulator/pfuze100-regulator.c .enable_reg = (base), \ base 265 drivers/regulator/pfuze100-regulator.c #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \ base 276 drivers/regulator/pfuze100-regulator.c .vsel_reg = (base), \ base 278 drivers/regulator/pfuze100-regulator.c .enable_reg = (base), \ base 281 drivers/regulator/pfuze100-regulator.c .stby_reg = (base), \ base 285 drivers/regulator/pfuze100-regulator.c #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \ base 295 drivers/regulator/pfuze100-regulator.c .vsel_reg = (base), \ base 297 drivers/regulator/pfuze100-regulator.c .enable_reg = (base), \ base 302 drivers/regulator/pfuze100-regulator.c #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \ base 312 drivers/regulator/pfuze100-regulator.c .vsel_reg = (base), \ base 314 drivers/regulator/pfuze100-regulator.c .enable_reg = (base), \ base 317 drivers/regulator/pfuze100-regulator.c .stby_reg = (base), \ base 322 drivers/regulator/pfuze100-regulator.c #define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step) { \ base 332 drivers/regulator/pfuze100-regulator.c .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ base 335 drivers/regulator/pfuze100-regulator.c .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ base 339 drivers/regulator/pfuze100-regulator.c #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \ base 349 drivers/regulator/pfuze100-regulator.c .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ base 352 drivers/regulator/pfuze100-regulator.c .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ base 373 drivers/regulator/qcom_spmi-regulator.c u16 base; base 390 drivers/regulator/qcom_spmi-regulator.c u16 base; base 538 drivers/regulator/qcom_spmi-regulator.c return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len); base 544 drivers/regulator/qcom_spmi-regulator.c return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len); base 550 drivers/regulator/qcom_spmi-regulator.c return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val); base 2010 drivers/regulator/qcom_spmi-regulator.c vreg->base = reg->base; base 2022 drivers/regulator/qcom_spmi-regulator.c vreg->desc.enable_reg = reg->base + SPMI_COMMON_REG_ENABLE; base 42 drivers/regulator/stm32-pwr.c void __iomem *base; base 51 drivers/regulator/stm32-pwr.c val = readl_relaxed(priv->base + REG_PWR_CR3); base 61 drivers/regulator/stm32-pwr.c val = readl_relaxed(priv->base + REG_PWR_CR3); base 72 drivers/regulator/stm32-pwr.c val = readl_relaxed(priv->base + REG_PWR_CR3); base 74 drivers/regulator/stm32-pwr.c writel_relaxed(val, priv->base + REG_PWR_CR3); base 91 drivers/regulator/stm32-pwr.c val = readl_relaxed(priv->base + REG_PWR_CR3); base 93 drivers/regulator/stm32-pwr.c writel_relaxed(val, priv->base + REG_PWR_CR3); base 134 drivers/regulator/stm32-pwr.c void __iomem *base; base 139 drivers/regulator/stm32-pwr.c base = of_iomap(np, 0); base 140 drivers/regulator/stm32-pwr.c if (!base) { base 152 drivers/regulator/stm32-pwr.c priv->base = base; base 31 drivers/regulator/stm32-vrefbuf.c void __iomem *base; base 53 drivers/regulator/stm32-vrefbuf.c val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); base 55 drivers/regulator/stm32-vrefbuf.c writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); base 63 drivers/regulator/stm32-vrefbuf.c ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, base 67 drivers/regulator/stm32-vrefbuf.c val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); base 69 drivers/regulator/stm32-vrefbuf.c writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); base 90 drivers/regulator/stm32-vrefbuf.c val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); base 92 drivers/regulator/stm32-vrefbuf.c writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); base 111 drivers/regulator/stm32-vrefbuf.c ret = readl_relaxed(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR; base 132 drivers/regulator/stm32-vrefbuf.c val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); base 134 drivers/regulator/stm32-vrefbuf.c writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); base 154 drivers/regulator/stm32-vrefbuf.c val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); base 197 drivers/regulator/stm32-vrefbuf.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 198 drivers/regulator/stm32-vrefbuf.c if (IS_ERR(priv->base)) base 199 drivers/regulator/stm32-vrefbuf.c return PTR_ERR(priv->base); base 195 drivers/regulator/stpmic1_regulator.c #define REG_LDO(ids, base) { \ base 200 drivers/regulator/stpmic1_regulator.c .linear_ranges = base ## _ranges, \ base 201 drivers/regulator/stpmic1_regulator.c .n_linear_ranges = ARRAY_SIZE(base ## _ranges), \ base 211 drivers/regulator/stpmic1_regulator.c .supply_name = #base, \ base 214 drivers/regulator/stpmic1_regulator.c #define REG_LDO3(ids, base) { \ base 234 drivers/regulator/stpmic1_regulator.c .supply_name = #base, \ base 237 drivers/regulator/stpmic1_regulator.c #define REG_LDO4(ids, base) { \ base 251 drivers/regulator/stpmic1_regulator.c .supply_name = #base, \ base 254 drivers/regulator/stpmic1_regulator.c #define REG_BUCK(ids, base) { \ base 259 drivers/regulator/stpmic1_regulator.c .linear_ranges = base ## _ranges, \ base 260 drivers/regulator/stpmic1_regulator.c .n_linear_ranges = ARRAY_SIZE(base ## _ranges), \ base 273 drivers/regulator/stpmic1_regulator.c .supply_name = #base, \ base 276 drivers/regulator/stpmic1_regulator.c #define REG_VREF_DDR(ids, base) { \ base 290 drivers/regulator/stpmic1_regulator.c .supply_name = #base, \ base 293 drivers/regulator/stpmic1_regulator.c #define REG_BOOST(ids, base) { \ base 307 drivers/regulator/stpmic1_regulator.c .supply_name = #base, \ base 310 drivers/regulator/stpmic1_regulator.c #define REG_VBUS_OTG(ids, base) { \ base 324 drivers/regulator/stpmic1_regulator.c .supply_name = #base, \ base 330 drivers/regulator/stpmic1_regulator.c #define REG_SW_OUT(ids, base) { \ base 344 drivers/regulator/stpmic1_regulator.c .supply_name = #base, \ base 103 drivers/regulator/ti-abb-regulator.c void __iomem *base; base 720 drivers/regulator/ti-abb-regulator.c abb->base = devm_ioremap_resource(dev, res); base 721 drivers/regulator/ti-abb-regulator.c if (IS_ERR(abb->base)) base 722 drivers/regulator/ti-abb-regulator.c return PTR_ERR(abb->base); base 724 drivers/regulator/ti-abb-regulator.c abb->setup_reg = abb->base + abb->regs->setup_off; base 725 drivers/regulator/ti-abb-regulator.c abb->control_reg = abb->base + abb->regs->control_off; base 35 drivers/regulator/twl-regulator.c u8 base; base 82 drivers/regulator/twl-regulator.c &value, info->base + offset); base 91 drivers/regulator/twl-regulator.c value, info->base + offset); base 465 drivers/regulator/twl-regulator.c .base = offset, \ base 485 drivers/regulator/twl-regulator.c .base = offset, \ base 505 drivers/regulator/twl-regulator.c .base = offset, \ base 25 drivers/regulator/twl6030-regulator.c u8 base; base 93 drivers/regulator/twl6030-regulator.c &value, info->base + offset); base 102 drivers/regulator/twl6030-regulator.c value, info->base + offset); base 517 drivers/regulator/twl6030-regulator.c .base = offset, \ base 532 drivers/regulator/twl6030-regulator.c .base = offset, \ base 547 drivers/regulator/twl6030-regulator.c .base = offset, \ base 564 drivers/regulator/twl6030-regulator.c .base = offset, \ base 49 drivers/regulator/uniphier-regulator.c void __iomem *base; base 62 drivers/regulator/uniphier-regulator.c base = devm_ioremap_resource(dev, res); base 63 drivers/regulator/uniphier-regulator.c if (IS_ERR(base)) base 64 drivers/regulator/uniphier-regulator.c return PTR_ERR(base); base 89 drivers/regulator/uniphier-regulator.c regmap = devm_regmap_init_mmio(dev, base, priv->data->regconf); base 50 drivers/regulator/wm831x-dcdc.c int base; base 64 drivers/regulator/wm831x-dcdc.c u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG; base 118 drivers/regulator/wm831x-dcdc.c u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG; base 128 drivers/regulator/wm831x-dcdc.c u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL; base 235 drivers/regulator/wm831x-dcdc.c int on_reg = dcdc->base + WM831X_DCDC_ON_CONFIG; base 236 drivers/regulator/wm831x-dcdc.c int dvs_reg = dcdc->base + WM831X_DCDC_DVS_CONTROL; base 285 drivers/regulator/wm831x-dcdc.c u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL; base 374 drivers/regulator/wm831x-dcdc.c dcdc->base + WM831X_DCDC_DVS_CONTROL, base 383 drivers/regulator/wm831x-dcdc.c ret = wm831x_set_bits(wm831x, dcdc->base + WM831X_DCDC_DVS_CONTROL, base 422 drivers/regulator/wm831x-dcdc.c dcdc->base = res->start; base 440 drivers/regulator/wm831x-dcdc.c dcdc->desc.csel_reg = dcdc->base + WM831X_DCDC_CONTROL_2; base 445 drivers/regulator/wm831x-dcdc.c ret = wm831x_reg_read(wm831x, dcdc->base + WM831X_DCDC_ON_CONFIG); base 452 drivers/regulator/wm831x-dcdc.c ret = wm831x_reg_read(wm831x, dcdc->base + WM831X_DCDC_DVS_CONTROL); base 523 drivers/regulator/wm831x-dcdc.c u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL; base 580 drivers/regulator/wm831x-dcdc.c dcdc->base = res->start; base 594 drivers/regulator/wm831x-dcdc.c dcdc->desc.vsel_reg = dcdc->base + WM831X_DCDC_ON_CONFIG; base 707 drivers/regulator/wm831x-dcdc.c dcdc->base = res->start; base 36 drivers/regulator/wm831x-ldo.c int base; base 72 drivers/regulator/wm831x-ldo.c int sel, reg = ldo->base + WM831X_LDO_SLEEP_CONTROL; base 85 drivers/regulator/wm831x-ldo.c int ctrl_reg = ldo->base + WM831X_LDO_CONTROL; base 86 drivers/regulator/wm831x-ldo.c int on_reg = ldo->base + WM831X_LDO_ON_CONTROL; base 111 drivers/regulator/wm831x-ldo.c int ctrl_reg = ldo->base + WM831X_LDO_CONTROL; base 112 drivers/regulator/wm831x-ldo.c int on_reg = ldo->base + WM831X_LDO_ON_CONTROL; base 246 drivers/regulator/wm831x-ldo.c ldo->base = res->start; base 260 drivers/regulator/wm831x-ldo.c ldo->desc.vsel_reg = ldo->base + WM831X_LDO_ON_CONTROL; base 264 drivers/regulator/wm831x-ldo.c ldo->desc.bypass_reg = ldo->base; base 325 drivers/regulator/wm831x-ldo.c int sel, reg = ldo->base + WM831X_LDO_SLEEP_CONTROL; base 338 drivers/regulator/wm831x-ldo.c int on_reg = ldo->base + WM831X_LDO_ON_CONTROL; base 356 drivers/regulator/wm831x-ldo.c int on_reg = ldo->base + WM831X_LDO_ON_CONTROL; base 456 drivers/regulator/wm831x-ldo.c ldo->base = res->start; base 472 drivers/regulator/wm831x-ldo.c ldo->desc.vsel_reg = ldo->base + WM831X_LDO_ON_CONTROL; base 476 drivers/regulator/wm831x-ldo.c ldo->desc.bypass_reg = ldo->base; base 531 drivers/regulator/wm831x-ldo.c int sel, reg = ldo->base + WM831X_ALIVE_LDO_SLEEP_CONTROL; base 601 drivers/regulator/wm831x-ldo.c ldo->base = res->start; base 615 drivers/regulator/wm831x-ldo.c ldo->desc.vsel_reg = ldo->base + WM831X_ALIVE_LDO_ON_CONTROL; base 515 drivers/remoteproc/qcom_q6v5_wcss.c wcss->mem_phys = rmem->base; base 516 drivers/remoteproc/qcom_q6v5_wcss.c wcss->mem_reloc = rmem->base; base 521 drivers/remoteproc/qcom_q6v5_wcss.c &rmem->base, &rmem->size); base 140 drivers/remoteproc/st_remoteproc.c (dma_addr_t)rmem->base, base 141 drivers/remoteproc/st_remoteproc.c rmem->size, rmem->base, base 149 drivers/remoteproc/st_remoteproc.c rmem->base, base 218 drivers/remoteproc/stm32_rproc.c if (stm32_rproc_pa_to_da(rproc, rmem->base, &da) < 0) { base 220 drivers/remoteproc/stm32_rproc.c &rmem->base); base 228 drivers/remoteproc/stm32_rproc.c (dma_addr_t)rmem->base, base 241 drivers/remoteproc/stm32_rproc.c rmem->base, base 59 drivers/reset/core.c struct reset_control base; base 191 drivers/reset/core.c return container_of(rstc, struct reset_control_array, base); base 890 drivers/reset/core.c resets->base.array = true; base 892 drivers/reset/core.c return &resets->base; base 19 drivers/reset/reset-ath79.c void __iomem *base; base 34 drivers/reset/reset-ath79.c val = readl(ath79_reset->base); base 39 drivers/reset/reset-ath79.c writel(val, ath79_reset->base); base 64 drivers/reset/reset-ath79.c val = readl(ath79_reset->base); base 100 drivers/reset/reset-ath79.c ath79_reset->base = devm_ioremap_resource(&pdev->dev, res); base 101 drivers/reset/reset-ath79.c if (IS_ERR(ath79_reset->base)) base 102 drivers/reset/reset-ath79.c return PTR_ERR(ath79_reset->base); base 18 drivers/reset/reset-brcmstb.c void __iomem *base; base 46 drivers/reset/reset-brcmstb.c writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET); base 57 drivers/reset/reset-brcmstb.c writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR); base 73 drivers/reset/reset-brcmstb.c return readl_relaxed(priv->base + off + SW_INIT_STATUS) & base 94 drivers/reset/reset-brcmstb.c priv->base = devm_ioremap_resource(kdev, res); base 95 drivers/reset/reset-brcmstb.c if (IS_ERR(priv->base)) base 96 drivers/reset/reset-brcmstb.c return PTR_ERR(priv->base); base 37 drivers/reset/reset-lpc18xx.c void __iomem *base; base 50 drivers/reset/reset-lpc18xx.c writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0); base 80 drivers/reset/reset-lpc18xx.c stat = ~readl(rc->base + stat_offset); base 82 drivers/reset/reset-lpc18xx.c writel(stat | rst_bit, rc->base + ctrl_offset); base 84 drivers/reset/reset-lpc18xx.c writel(stat & ~rst_bit, rc->base + ctrl_offset); base 129 drivers/reset/reset-lpc18xx.c return !(readl(rc->base + offset) & bit); base 151 drivers/reset/reset-lpc18xx.c rc->base = devm_ioremap_resource(&pdev->dev, res); base 152 drivers/reset/reset-lpc18xx.c if (IS_ERR(rc->base)) base 153 drivers/reset/reset-lpc18xx.c return PTR_ERR(rc->base); base 25 drivers/reset/reset-qcom-aoss.c void __iomem *base; base 56 drivers/reset/reset-qcom-aoss.c writel(1, data->base + map->reg); base 68 drivers/reset/reset-qcom-aoss.c writel(0, data->base + map->reg); base 105 drivers/reset/reset-qcom-aoss.c data->base = devm_ioremap_resource(dev, res); base 106 drivers/reset/reset-qcom-aoss.c if (IS_ERR(data->base)) base 107 drivers/reset/reset-qcom-aoss.c return PTR_ERR(data->base); base 81 drivers/reset/reset-qcom-pdc.c void __iomem *base; base 89 drivers/reset/reset-qcom-pdc.c base = devm_ioremap_resource(dev, res); base 90 drivers/reset/reset-qcom-pdc.c if (IS_ERR(base)) base 91 drivers/reset/reset-qcom-pdc.c return PTR_ERR(base); base 93 drivers/reset/reset-qcom-pdc.c data->regmap = devm_regmap_init_mmio(dev, base, base 103 drivers/rtc/rtc-88pm80x.c unsigned long ticks, base, data; base 105 drivers/rtc/rtc-88pm80x.c base = ((unsigned long)buf[3] << 24) | (buf[2] << 16) | base 113 drivers/rtc/rtc-88pm80x.c ticks = base + data; base 115 drivers/rtc/rtc-88pm80x.c base, data, ticks); base 124 drivers/rtc/rtc-88pm80x.c unsigned long ticks, base, data; base 132 drivers/rtc/rtc-88pm80x.c base = ticks - data; base 134 drivers/rtc/rtc-88pm80x.c base, data, ticks); base 135 drivers/rtc/rtc-88pm80x.c buf[0] = base & 0xFF; base 136 drivers/rtc/rtc-88pm80x.c buf[1] = (base >> 8) & 0xFF; base 137 drivers/rtc/rtc-88pm80x.c buf[2] = (base >> 16) & 0xFF; base 138 drivers/rtc/rtc-88pm80x.c buf[3] = (base >> 24) & 0xFF; base 148 drivers/rtc/rtc-88pm80x.c unsigned long ticks, base, data; base 152 drivers/rtc/rtc-88pm80x.c base = ((unsigned long)buf[3] << 24) | (buf[2] << 16) | base 159 drivers/rtc/rtc-88pm80x.c ticks = base + data; base 161 drivers/rtc/rtc-88pm80x.c base, data, ticks); base 174 drivers/rtc/rtc-88pm80x.c unsigned long ticks, base, data; base 181 drivers/rtc/rtc-88pm80x.c base = ((unsigned long)buf[3] << 24) | (buf[2] << 16) | base 189 drivers/rtc/rtc-88pm80x.c ticks = base + data; base 191 drivers/rtc/rtc-88pm80x.c base, data, ticks); base 199 drivers/rtc/rtc-88pm80x.c data = ticks - base; base 110 drivers/rtc/rtc-88pm860x.c unsigned long ticks, base, data; base 115 drivers/rtc/rtc-88pm860x.c base = ((unsigned long)buf[1] << 24) | (buf[3] << 16) | base 122 drivers/rtc/rtc-88pm860x.c ticks = base + data; base 124 drivers/rtc/rtc-88pm860x.c base, data, ticks); base 135 drivers/rtc/rtc-88pm860x.c unsigned long ticks, base, data; base 149 drivers/rtc/rtc-88pm860x.c base = ticks - data; base 151 drivers/rtc/rtc-88pm860x.c base, data, ticks); base 153 drivers/rtc/rtc-88pm860x.c pm860x_page_reg_write(info->i2c, REG0_DATA, (base >> 24) & 0xFF); base 154 drivers/rtc/rtc-88pm860x.c pm860x_page_reg_write(info->i2c, REG1_DATA, (base >> 16) & 0xFF); base 155 drivers/rtc/rtc-88pm860x.c pm860x_page_reg_write(info->i2c, REG2_DATA, (base >> 8) & 0xFF); base 156 drivers/rtc/rtc-88pm860x.c pm860x_page_reg_write(info->i2c, REG3_DATA, base & 0xFF); base 167 drivers/rtc/rtc-88pm860x.c unsigned long ticks, base, data; base 173 drivers/rtc/rtc-88pm860x.c base = ((unsigned long)buf[1] << 24) | (buf[3] << 16) | base 179 drivers/rtc/rtc-88pm860x.c ticks = base + data; base 181 drivers/rtc/rtc-88pm860x.c base, data, ticks); base 194 drivers/rtc/rtc-88pm860x.c unsigned long ticks, base, data; base 203 drivers/rtc/rtc-88pm860x.c base = ((unsigned long)buf[1] << 24) | (buf[3] << 16) | base 210 drivers/rtc/rtc-88pm860x.c ticks = base + data; base 212 drivers/rtc/rtc-88pm860x.c base, data, ticks); base 218 drivers/rtc/rtc-88pm860x.c data = ticks - base; base 83 drivers/rtc/rtc-armada38x.c #define ALARM_REG(base, alarm) ((base) + (alarm) * sizeof(u32)) base 12 drivers/rtc/rtc-aspeed.c void __iomem *base; base 28 drivers/rtc/rtc-aspeed.c if (!(readl(rtc->base + RTC_CTRL) & RTC_ENABLE)) { base 34 drivers/rtc/rtc-aspeed.c reg2 = readl(rtc->base + RTC_YEAR); base 35 drivers/rtc/rtc-aspeed.c reg1 = readl(rtc->base + RTC_TIME); base 36 drivers/rtc/rtc-aspeed.c } while (reg2 != readl(rtc->base + RTC_YEAR)); base 68 drivers/rtc/rtc-aspeed.c ctrl = readl(rtc->base + RTC_CTRL); base 69 drivers/rtc/rtc-aspeed.c writel(ctrl | RTC_UNLOCK, rtc->base + RTC_CTRL); base 71 drivers/rtc/rtc-aspeed.c writel(reg1, rtc->base + RTC_TIME); base 72 drivers/rtc/rtc-aspeed.c writel(reg2, rtc->base + RTC_YEAR); base 75 drivers/rtc/rtc-aspeed.c writel(ctrl | RTC_ENABLE, rtc->base + RTC_CTRL); base 95 drivers/rtc/rtc-aspeed.c rtc->base = devm_ioremap_resource(&pdev->dev, res); base 96 drivers/rtc/rtc-aspeed.c if (IS_ERR(rtc->base)) base 97 drivers/rtc/rtc-aspeed.c return PTR_ERR(rtc->base); base 29 drivers/rtc/rtc-brcmstb-waketimer.c void __iomem *base; base 46 drivers/rtc/rtc-brcmstb-waketimer.c writel_relaxed(1, timer->base + BRCMSTB_WKTMR_EVENT); base 47 drivers/rtc/rtc-brcmstb-waketimer.c (void)readl_relaxed(timer->base + BRCMSTB_WKTMR_EVENT); base 56 drivers/rtc/rtc-brcmstb-waketimer.c writel_relaxed(timer->rate, timer->base + BRCMSTB_WKTMR_PRESCALER); base 58 drivers/rtc/rtc-brcmstb-waketimer.c writel_relaxed(secs + 1, timer->base + BRCMSTB_WKTMR_ALARM); base 81 drivers/rtc/rtc-brcmstb-waketimer.c t->sec = readl_relaxed(timer->base + BRCMSTB_WKTMR_COUNTER); base 82 drivers/rtc/rtc-brcmstb-waketimer.c tmp = readl_relaxed(timer->base + BRCMSTB_WKTMR_PRESCALER_VAL); base 140 drivers/rtc/rtc-brcmstb-waketimer.c writel_relaxed(sec, timer->base + BRCMSTB_WKTMR_COUNTER); base 152 drivers/rtc/rtc-brcmstb-waketimer.c sec = readl_relaxed(timer->base + BRCMSTB_WKTMR_ALARM); base 159 drivers/rtc/rtc-brcmstb-waketimer.c reg = readl_relaxed(timer->base + BRCMSTB_WKTMR_EVENT); base 214 drivers/rtc/rtc-brcmstb-waketimer.c timer->base = devm_ioremap_resource(dev, res); base 215 drivers/rtc/rtc-brcmstb-waketimer.c if (IS_ERR(timer->base)) base 216 drivers/rtc/rtc-brcmstb-waketimer.c return PTR_ERR(timer->base); base 108 drivers/rtc/rtc-davinci.c void __iomem *base; base 115 drivers/rtc/rtc-davinci.c writel(val, davinci_rtc->base + addr); base 120 drivers/rtc/rtc-davinci.c return readl(davinci_rtc->base + addr); base 484 drivers/rtc/rtc-davinci.c davinci_rtc->base = devm_ioremap_resource(dev, res); base 485 drivers/rtc/rtc-davinci.c if (IS_ERR(davinci_rtc->base)) base 486 drivers/rtc/rtc-davinci.c return PTR_ERR(davinci_rtc->base); base 41 drivers/rtc/rtc-fsl-ftm-alarm.c void __iomem *base; base 49 drivers/rtc/rtc-fsl-ftm-alarm.c return ioread32be(dev->base + reg); base 51 drivers/rtc/rtc-fsl-ftm-alarm.c return ioread32(dev->base + reg); base 57 drivers/rtc/rtc-fsl-ftm-alarm.c iowrite32be(val, dev->base + reg); base 59 drivers/rtc/rtc-fsl-ftm-alarm.c iowrite32(val, dev->base + reg); base 274 drivers/rtc/rtc-fsl-ftm-alarm.c rtc->base = devm_ioremap_resource(&pdev->dev, r); base 275 drivers/rtc/rtc-fsl-ftm-alarm.c if (IS_ERR(rtc->base)) { base 277 drivers/rtc/rtc-fsl-ftm-alarm.c return PTR_ERR(rtc->base); base 27 drivers/rtc/rtc-goldfish.c void __iomem *base; base 38 drivers/rtc/rtc-goldfish.c void __iomem *base; base 42 drivers/rtc/rtc-goldfish.c base = rtcdrv->base; base 44 drivers/rtc/rtc-goldfish.c rtc_alarm_low = readl(base + TIMER_ALARM_LOW); base 45 drivers/rtc/rtc-goldfish.c rtc_alarm_high = readl(base + TIMER_ALARM_HIGH); base 53 drivers/rtc/rtc-goldfish.c if (readl(base + TIMER_ALARM_STATUS)) base 67 drivers/rtc/rtc-goldfish.c void __iomem *base; base 70 drivers/rtc/rtc-goldfish.c base = rtcdrv->base; base 74 drivers/rtc/rtc-goldfish.c writel((rtc_alarm64 >> 32), base + TIMER_ALARM_HIGH); base 75 drivers/rtc/rtc-goldfish.c writel(rtc_alarm64, base + TIMER_ALARM_LOW); base 82 drivers/rtc/rtc-goldfish.c rtc_status_reg = readl(base + TIMER_ALARM_STATUS); base 84 drivers/rtc/rtc-goldfish.c writel(1, base + TIMER_CLEAR_ALARM); base 93 drivers/rtc/rtc-goldfish.c void __iomem *base; base 97 drivers/rtc/rtc-goldfish.c base = rtcdrv->base; base 100 drivers/rtc/rtc-goldfish.c writel(1, base + TIMER_IRQ_ENABLED); base 102 drivers/rtc/rtc-goldfish.c writel(0, base + TIMER_IRQ_ENABLED); base 110 drivers/rtc/rtc-goldfish.c void __iomem *base = rtcdrv->base; base 112 drivers/rtc/rtc-goldfish.c writel(1, base + TIMER_CLEAR_INTERRUPT); base 122 drivers/rtc/rtc-goldfish.c void __iomem *base; base 128 drivers/rtc/rtc-goldfish.c base = rtcdrv->base; base 130 drivers/rtc/rtc-goldfish.c time_low = readl(base + TIMER_TIME_LOW); base 131 drivers/rtc/rtc-goldfish.c time_high = readl(base + TIMER_TIME_HIGH); base 144 drivers/rtc/rtc-goldfish.c void __iomem *base; base 148 drivers/rtc/rtc-goldfish.c base = rtcdrv->base; base 151 drivers/rtc/rtc-goldfish.c writel((now64 >> 32), base + TIMER_TIME_HIGH); base 152 drivers/rtc/rtc-goldfish.c writel(now64, base + TIMER_TIME_LOW); base 181 drivers/rtc/rtc-goldfish.c rtcdrv->base = devm_ioremap_resource(&pdev->dev, r); base 182 drivers/rtc/rtc-goldfish.c if (IS_ERR(rtcdrv->base)) base 53 drivers/rtc/rtc-jz4740.c void __iomem *base; base 71 drivers/rtc/rtc-jz4740.c return readl(rtc->base + reg); base 95 drivers/rtc/rtc-jz4740.c writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); base 98 drivers/rtc/rtc-jz4740.c ctrl = readl(rtc->base + JZ_REG_RTC_WENR); base 114 drivers/rtc/rtc-jz4740.c writel(val, rtc->base + reg); base 330 drivers/rtc/rtc-jz4740.c rtc->base = devm_ioremap_resource(&pdev->dev, mem); base 331 drivers/rtc/rtc-jz4740.c if (IS_ERR(rtc->base)) base 332 drivers/rtc/rtc-jz4740.c return PTR_ERR(rtc->base); base 296 drivers/rtc/rtc-meson.c void __iomem *base; base 316 drivers/rtc/rtc-meson.c base = devm_ioremap_resource(dev, res); base 317 drivers/rtc/rtc-meson.c if (IS_ERR(base)) base 318 drivers/rtc/rtc-meson.c return PTR_ERR(base); base 320 drivers/rtc/rtc-meson.c rtc->peripheral = devm_regmap_init_mmio(dev, base, base 103 drivers/rtc/rtc-mt7622.c void __iomem *base; base 110 drivers/rtc/rtc-mt7622.c writel_relaxed(val, rtc->base + reg); base 115 drivers/rtc/rtc-mt7622.c return readl_relaxed(rtc->base + reg); base 316 drivers/rtc/rtc-mt7622.c hw->base = devm_ioremap_resource(&pdev->dev, res); base 317 drivers/rtc/rtc-mt7622.c if (IS_ERR(hw->base)) base 318 drivers/rtc/rtc-mt7622.c return PTR_ERR(hw->base); base 143 drivers/rtc/rtc-omap.c void __iomem *base; base 157 drivers/rtc/rtc-omap.c return readb(rtc->base + reg); base 162 drivers/rtc/rtc-omap.c return readl(rtc->base + reg); base 167 drivers/rtc/rtc-omap.c writeb(val, rtc->base + reg); base 172 drivers/rtc/rtc-omap.c writel(val, rtc->base + reg); base 768 drivers/rtc/rtc-omap.c rtc->base = devm_ioremap_resource(&pdev->dev, res); base 769 drivers/rtc/rtc-omap.c if (IS_ERR(rtc->base)) { base 771 drivers/rtc/rtc-omap.c return PTR_ERR(rtc->base); base 101 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; base 106 drivers/rtc/rtc-pic32.c base + (enabled ? PIC32_SET(PIC32_RTCALRM) : base 119 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; base 123 drivers/rtc/rtc-pic32.c writel(PIC32_RTCALRM_AMASK, base + PIC32_CLR(PIC32_RTCALRM)); base 124 drivers/rtc/rtc-pic32.c writel(freq << 8, base + PIC32_SET(PIC32_RTCALRM)); base 125 drivers/rtc/rtc-pic32.c writel(PIC32_RTCALRM_CHIME, base + PIC32_SET(PIC32_RTCALRM)); base 135 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; base 141 drivers/rtc/rtc-pic32.c rtc_tm->tm_hour = readb(base + PIC32_RTCHOUR); base 142 drivers/rtc/rtc-pic32.c rtc_tm->tm_min = readb(base + PIC32_RTCMIN); base 143 drivers/rtc/rtc-pic32.c rtc_tm->tm_mon = readb(base + PIC32_RTCMON); base 144 drivers/rtc/rtc-pic32.c rtc_tm->tm_mday = readb(base + PIC32_RTCDAY); base 145 drivers/rtc/rtc-pic32.c rtc_tm->tm_year = readb(base + PIC32_RTCYEAR); base 146 drivers/rtc/rtc-pic32.c rtc_tm->tm_sec = readb(base + PIC32_RTCSEC); base 174 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; base 179 drivers/rtc/rtc-pic32.c writeb(bin2bcd(tm->tm_sec), base + PIC32_RTCSEC); base 180 drivers/rtc/rtc-pic32.c writeb(bin2bcd(tm->tm_min), base + PIC32_RTCMIN); base 181 drivers/rtc/rtc-pic32.c writeb(bin2bcd(tm->tm_hour), base + PIC32_RTCHOUR); base 182 drivers/rtc/rtc-pic32.c writeb(bin2bcd(tm->tm_mday), base + PIC32_RTCDAY); base 183 drivers/rtc/rtc-pic32.c writeb(bin2bcd(tm->tm_mon + 1), base + PIC32_RTCMON); base 184 drivers/rtc/rtc-pic32.c writeb(bin2bcd(tm->tm_year - 100), base + PIC32_RTCYEAR); base 194 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; base 198 drivers/rtc/rtc-pic32.c alm_tm->tm_sec = readb(base + PIC32_ALRMSEC); base 199 drivers/rtc/rtc-pic32.c alm_tm->tm_min = readb(base + PIC32_ALRMMIN); base 200 drivers/rtc/rtc-pic32.c alm_tm->tm_hour = readb(base + PIC32_ALRMHOUR); base 201 drivers/rtc/rtc-pic32.c alm_tm->tm_mon = readb(base + PIC32_ALRMMON); base 202 drivers/rtc/rtc-pic32.c alm_tm->tm_mday = readb(base + PIC32_ALRMDAY); base 203 drivers/rtc/rtc-pic32.c alm_tm->tm_year = readb(base + PIC32_ALRMYEAR); base 205 drivers/rtc/rtc-pic32.c alm_en = readb(base + PIC32_RTCALRM); base 226 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; base 231 drivers/rtc/rtc-pic32.c writel(0x00, base + PIC32_ALRMTIME); base 232 drivers/rtc/rtc-pic32.c writel(0x00, base + PIC32_ALRMDATE); base 243 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; base 248 drivers/rtc/rtc-pic32.c repeat = readw(base + PIC32_RTCALRM); base 267 drivers/rtc/rtc-pic32.c void __iomem *base = pdata->reg_base; base 269 drivers/rtc/rtc-pic32.c if (!base) base 274 drivers/rtc/rtc-pic32.c writel(PIC32_RTCCON_ON, base + PIC32_CLR(PIC32_RTCCON)); base 278 drivers/rtc/rtc-pic32.c writel(PIC32_RTCCON_RTCWREN, base + PIC32_SET(PIC32_RTCCON)); base 279 drivers/rtc/rtc-pic32.c writel(3 << 9, base + PIC32_CLR(PIC32_RTCCON)); base 281 drivers/rtc/rtc-pic32.c if (!(readl(base + PIC32_RTCCON) & PIC32_RTCCON_ON)) base 282 drivers/rtc/rtc-pic32.c writel(PIC32_RTCCON_ON, base + PIC32_SET(PIC32_RTCCON)); base 25 drivers/rtc/rtc-pl030.c void __iomem *base; base 31 drivers/rtc/rtc-pl030.c writel(0, rtc->base + RTC_EOI); base 39 drivers/rtc/rtc-pl030.c rtc_time_to_tm(readl(rtc->base + RTC_MR), &alrm->time); base 56 drivers/rtc/rtc-pl030.c writel(time, rtc->base + RTC_MR); base 64 drivers/rtc/rtc-pl030.c rtc_time_to_tm(readl(rtc->base + RTC_DR), tm); base 85 drivers/rtc/rtc-pl030.c writel(time + 1, rtc->base + RTC_LR); base 119 drivers/rtc/rtc-pl030.c rtc->base = ioremap(dev->res.start, resource_size(&dev->res)); base 120 drivers/rtc/rtc-pl030.c if (!rtc->base) { base 125 drivers/rtc/rtc-pl030.c __raw_writel(0, rtc->base + RTC_CR); base 126 drivers/rtc/rtc-pl030.c __raw_writel(0, rtc->base + RTC_EOI); base 144 drivers/rtc/rtc-pl030.c iounmap(rtc->base); base 155 drivers/rtc/rtc-pl030.c writel(0, rtc->base + RTC_CR); base 158 drivers/rtc/rtc-pl030.c iounmap(rtc->base); base 88 drivers/rtc/rtc-pl031.c void __iomem *base; base 98 drivers/rtc/rtc-pl031.c writel(RTC_BIT_AI, ldata->base + RTC_ICR); base 100 drivers/rtc/rtc-pl031.c imsc = readl(ldata->base + RTC_IMSC); base 103 drivers/rtc/rtc-pl031.c writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC); base 105 drivers/rtc/rtc-pl031.c writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC); base 170 drivers/rtc/rtc-pl031.c pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR), base 171 drivers/rtc/rtc-pl031.c readl(ldata->base + RTC_YDR), tm); base 185 drivers/rtc/rtc-pl031.c writel(bcd_year, ldata->base + RTC_YLR); base 186 drivers/rtc/rtc-pl031.c writel(time, ldata->base + RTC_LR); base 197 drivers/rtc/rtc-pl031.c ret = pl031_stv2_time_to_tm(readl(ldata->base + RTC_MR), base 198 drivers/rtc/rtc-pl031.c readl(ldata->base + RTC_YMR), &alarm->time); base 200 drivers/rtc/rtc-pl031.c alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI; base 201 drivers/rtc/rtc-pl031.c alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI; base 219 drivers/rtc/rtc-pl031.c writel(bcd_year, ldata->base + RTC_YMR); base 220 drivers/rtc/rtc-pl031.c writel(time, ldata->base + RTC_MR); base 235 drivers/rtc/rtc-pl031.c rtcmis = readl(ldata->base + RTC_MIS); base 237 drivers/rtc/rtc-pl031.c writel(RTC_BIT_AI, ldata->base + RTC_ICR); base 251 drivers/rtc/rtc-pl031.c rtc_time_to_tm(readl(ldata->base + RTC_DR), tm); base 265 drivers/rtc/rtc-pl031.c writel(time, ldata->base + RTC_LR); base 274 drivers/rtc/rtc-pl031.c rtc_time_to_tm(readl(ldata->base + RTC_MR), &alarm->time); base 276 drivers/rtc/rtc-pl031.c alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI; base 277 drivers/rtc/rtc-pl031.c alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI; base 293 drivers/rtc/rtc-pl031.c writel(time, ldata->base + RTC_MR); base 336 drivers/rtc/rtc-pl031.c ldata->base = devm_ioremap(&adev->dev, adev->res.start, base 338 drivers/rtc/rtc-pl031.c if (!ldata->base) { base 348 drivers/rtc/rtc-pl031.c data = readl(ldata->base + RTC_CR); base 354 drivers/rtc/rtc-pl031.c writel(data, ldata->base + RTC_CR); base 361 drivers/rtc/rtc-pl031.c if (readl(ldata->base + RTC_YDR) == 0x2000) { base 362 drivers/rtc/rtc-pl031.c time = readl(ldata->base + RTC_DR); base 367 drivers/rtc/rtc-pl031.c writel(0x2000, ldata->base + RTC_YLR); base 368 drivers/rtc/rtc-pl031.c writel(time, ldata->base + RTC_LR); base 72 drivers/rtc/rtc-pxa.c __raw_readl((pxa_rtc)->base + (reg)) base 74 drivers/rtc/rtc-pxa.c __raw_writel((value), (pxa_rtc)->base + (reg)) base 79 drivers/rtc/rtc-pxa.c void __iomem *base; base 333 drivers/rtc/rtc-pxa.c pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start, base 335 drivers/rtc/rtc-pxa.c if (!pxa_rtc->base) { base 342 drivers/rtc/rtc-pxa.c sa1100_rtc->rcnr = pxa_rtc->base + 0x0; base 343 drivers/rtc/rtc-pxa.c sa1100_rtc->rtsr = pxa_rtc->base + 0x8; base 344 drivers/rtc/rtc-pxa.c sa1100_rtc->rtar = pxa_rtc->base + 0x4; base 345 drivers/rtc/rtc-pxa.c sa1100_rtc->rttr = pxa_rtc->base + 0xc; base 44 drivers/rtc/rtc-rtd119x.c void __iomem *base; base 60 drivers/rtc/rtc-rtd119x.c val = readl_relaxed(data->base + RTD_RTCCR); base 62 drivers/rtc/rtc-rtd119x.c writel_relaxed(val, data->base + RTD_RTCCR); base 65 drivers/rtc/rtc-rtd119x.c writel(val, data->base + RTD_RTCCR); base 73 drivers/rtc/rtc-rtd119x.c val = readl_relaxed(data->base + RTD_RTCEN); base 77 drivers/rtc/rtc-rtd119x.c writel_relaxed(0x5a, data->base + RTD_RTCEN); base 79 drivers/rtc/rtc-rtd119x.c writel_relaxed(0, data->base + RTD_RTCEN); base 92 drivers/rtc/rtc-rtd119x.c tm->tm_sec = (readl_relaxed(data->base + RTD_RTCSEC) & RTD_RTCSEC_RTCSEC_MASK) >> 1; base 93 drivers/rtc/rtc-rtd119x.c tm->tm_min = readl_relaxed(data->base + RTD_RTCMIN) & RTD_RTCMIN_RTCMIN_MASK; base 94 drivers/rtc/rtc-rtd119x.c tm->tm_hour = readl_relaxed(data->base + RTD_RTCHR) & RTD_RTCHR_RTCHR_MASK; base 95 drivers/rtc/rtc-rtd119x.c day = readl_relaxed(data->base + RTD_RTCDATE1) & RTD_RTCDATE1_RTCDATE1_MASK; base 96 drivers/rtc/rtc-rtd119x.c day |= (readl_relaxed(data->base + RTD_RTCDATE2) & RTD_RTCDATE2_RTCDATE2_MASK) << 8; base 97 drivers/rtc/rtc-rtd119x.c sec = (readl_relaxed(data->base + RTD_RTCSEC) & RTD_RTCSEC_RTCSEC_MASK) >> 1; base 146 drivers/rtc/rtc-rtd119x.c writel_relaxed((tm->tm_sec << 1) & RTD_RTCSEC_RTCSEC_MASK, data->base + RTD_RTCSEC); base 147 drivers/rtc/rtc-rtd119x.c writel_relaxed(tm->tm_min & RTD_RTCMIN_RTCMIN_MASK, data->base + RTD_RTCMIN); base 148 drivers/rtc/rtc-rtd119x.c writel_relaxed(tm->tm_hour & RTD_RTCHR_RTCHR_MASK, data->base + RTD_RTCHR); base 149 drivers/rtc/rtc-rtd119x.c writel_relaxed(day & RTD_RTCDATE1_RTCDATE1_MASK, data->base + RTD_RTCDATE1); base 150 drivers/rtc/rtc-rtd119x.c writel_relaxed((day >> 8) & RTD_RTCDATE2_RTCDATE2_MASK, data->base + RTD_RTCDATE2); base 182 drivers/rtc/rtc-rtd119x.c data->base = devm_ioremap_resource(&pdev->dev, res); base 183 drivers/rtc/rtc-rtd119x.c if (IS_ERR(data->base)) base 184 drivers/rtc/rtc-rtd119x.c return PTR_ERR(data->base); base 196 drivers/rtc/rtc-rtd119x.c val = readl_relaxed(data->base + RTD_RTCACR); base 198 drivers/rtc/rtc-rtd119x.c writel_relaxed(RTD_RTCACR_RTCPWR, data->base + RTD_RTCACR); base 202 drivers/rtc/rtc-rtd119x.c writel_relaxed(0, data->base + RTD_RTCMIN); base 203 drivers/rtc/rtc-rtd119x.c writel_relaxed(0, data->base + RTD_RTCHR); base 204 drivers/rtc/rtc-rtd119x.c writel_relaxed(0, data->base + RTD_RTCDATE1); base 205 drivers/rtc/rtc-rtd119x.c writel_relaxed(0, data->base + RTD_RTCDATE2); base 37 drivers/rtc/rtc-s3c.c void __iomem *base; base 129 drivers/rtc/rtc-s3c.c tmp = readb(info->base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN; base 134 drivers/rtc/rtc-s3c.c writeb(tmp, info->base + S3C2410_RTCALM); base 185 drivers/rtc/rtc-s3c.c rtc_tm->tm_min = readb(info->base + S3C2410_RTCMIN); base 186 drivers/rtc/rtc-s3c.c rtc_tm->tm_hour = readb(info->base + S3C2410_RTCHOUR); base 187 drivers/rtc/rtc-s3c.c rtc_tm->tm_mday = readb(info->base + S3C2410_RTCDATE); base 188 drivers/rtc/rtc-s3c.c rtc_tm->tm_mon = readb(info->base + S3C2410_RTCMON); base 189 drivers/rtc/rtc-s3c.c rtc_tm->tm_year = readb(info->base + S3C2410_RTCYEAR); base 190 drivers/rtc/rtc-s3c.c rtc_tm->tm_sec = readb(info->base + S3C2410_RTCSEC); base 237 drivers/rtc/rtc-s3c.c writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_RTCSEC); base 238 drivers/rtc/rtc-s3c.c writeb(bin2bcd(tm->tm_min), info->base + S3C2410_RTCMIN); base 239 drivers/rtc/rtc-s3c.c writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_RTCHOUR); base 240 drivers/rtc/rtc-s3c.c writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_RTCDATE); base 241 drivers/rtc/rtc-s3c.c writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_RTCMON); base 242 drivers/rtc/rtc-s3c.c writeb(bin2bcd(year), info->base + S3C2410_RTCYEAR); base 260 drivers/rtc/rtc-s3c.c alm_tm->tm_sec = readb(info->base + S3C2410_ALMSEC); base 261 drivers/rtc/rtc-s3c.c alm_tm->tm_min = readb(info->base + S3C2410_ALMMIN); base 262 drivers/rtc/rtc-s3c.c alm_tm->tm_hour = readb(info->base + S3C2410_ALMHOUR); base 263 drivers/rtc/rtc-s3c.c alm_tm->tm_mon = readb(info->base + S3C2410_ALMMON); base 264 drivers/rtc/rtc-s3c.c alm_tm->tm_mday = readb(info->base + S3C2410_ALMDATE); base 265 drivers/rtc/rtc-s3c.c alm_tm->tm_year = readb(info->base + S3C2410_ALMYEAR); base 267 drivers/rtc/rtc-s3c.c alm_en = readb(info->base + S3C2410_RTCALM); base 312 drivers/rtc/rtc-s3c.c alrm_en = readb(info->base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN; base 313 drivers/rtc/rtc-s3c.c writeb(0x00, info->base + S3C2410_RTCALM); base 317 drivers/rtc/rtc-s3c.c writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_ALMSEC); base 322 drivers/rtc/rtc-s3c.c writeb(bin2bcd(tm->tm_min), info->base + S3C2410_ALMMIN); base 327 drivers/rtc/rtc-s3c.c writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_ALMHOUR); base 332 drivers/rtc/rtc-s3c.c writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_ALMMON); base 337 drivers/rtc/rtc-s3c.c writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_ALMDATE); base 342 drivers/rtc/rtc-s3c.c writeb(alrm_en, info->base + S3C2410_RTCALM); base 381 drivers/rtc/rtc-s3c.c con = readw(info->base + S3C2410_RTCCON); base 386 drivers/rtc/rtc-s3c.c tmp = readw(info->base + S3C2410_RTCCON); base 387 drivers/rtc/rtc-s3c.c writew(tmp | S3C2410_RTCCON_RTCEN, info->base + S3C2410_RTCCON); base 393 drivers/rtc/rtc-s3c.c tmp = readw(info->base + S3C2410_RTCCON); base 395 drivers/rtc/rtc-s3c.c info->base + S3C2410_RTCCON); base 401 drivers/rtc/rtc-s3c.c tmp = readw(info->base + S3C2410_RTCCON); base 403 drivers/rtc/rtc-s3c.c info->base + S3C2410_RTCCON); base 411 drivers/rtc/rtc-s3c.c con = readw(info->base + S3C2410_RTCCON); base 413 drivers/rtc/rtc-s3c.c writew(con, info->base + S3C2410_RTCCON); base 415 drivers/rtc/rtc-s3c.c con = readb(info->base + S3C2410_TICNT); base 417 drivers/rtc/rtc-s3c.c writeb(con, info->base + S3C2410_TICNT); base 424 drivers/rtc/rtc-s3c.c con = readw(info->base + S3C2410_RTCCON); base 427 drivers/rtc/rtc-s3c.c writew(con, info->base + S3C2410_RTCCON); base 479 drivers/rtc/rtc-s3c.c info->base = devm_ioremap_resource(&pdev->dev, res); base 480 drivers/rtc/rtc-s3c.c if (IS_ERR(info->base)) base 481 drivers/rtc/rtc-s3c.c return PTR_ERR(info->base); base 518 drivers/rtc/rtc-s3c.c readw(info->base + S3C2410_RTCCON)); base 638 drivers/rtc/rtc-s3c.c writeb(mask, info->base + S3C2410_INTP); base 646 drivers/rtc/rtc-s3c.c tmp = readb(info->base + S3C2410_TICNT); base 652 drivers/rtc/rtc-s3c.c writel(tmp, info->base + S3C2410_TICNT); base 660 drivers/rtc/rtc-s3c.c tmp = readb(info->base + S3C2410_TICNT); base 666 drivers/rtc/rtc-s3c.c writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); base 668 drivers/rtc/rtc-s3c.c writel(S3C2416_TICNT2_PART(val), info->base + S3C2416_TICNT2); base 670 drivers/rtc/rtc-s3c.c writel(tmp, info->base + S3C2410_TICNT); base 678 drivers/rtc/rtc-s3c.c tmp = readb(info->base + S3C2410_TICNT); base 684 drivers/rtc/rtc-s3c.c writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); base 686 drivers/rtc/rtc-s3c.c writel(tmp, info->base + S3C2410_TICNT); base 694 drivers/rtc/rtc-s3c.c writel(val, info->base + S3C2410_TICNT); base 701 drivers/rtc/rtc-s3c.c ticnt = readb(info->base + S3C2410_TICNT); base 711 drivers/rtc/rtc-s3c.c con = readw(info->base + S3C2410_RTCCON); base 713 drivers/rtc/rtc-s3c.c writew(con, info->base + S3C2410_RTCCON); base 720 drivers/rtc/rtc-s3c.c ticnt = readw(info->base + S3C2410_RTCCON); base 728 drivers/rtc/rtc-s3c.c info->ticnt_save = readb(info->base + S3C2410_TICNT); base 733 drivers/rtc/rtc-s3c.c writeb(info->ticnt_save, info->base + S3C2410_TICNT); base 738 drivers/rtc/rtc-s3c.c info->ticnt_en_save = readw(info->base + S3C2410_RTCCON); base 740 drivers/rtc/rtc-s3c.c info->ticnt_save = readl(info->base + S3C2410_TICNT); base 747 drivers/rtc/rtc-s3c.c writel(info->ticnt_save, info->base + S3C2410_TICNT); base 749 drivers/rtc/rtc-s3c.c con = readw(info->base + S3C2410_RTCCON); base 750 drivers/rtc/rtc-s3c.c writew(con | info->ticnt_en_save, info->base + S3C2410_RTCCON); base 256 drivers/rtc/rtc-sa1100.c void __iomem *base; base 285 drivers/rtc/rtc-sa1100.c base = devm_ioremap_resource(&pdev->dev, iores); base 286 drivers/rtc/rtc-sa1100.c if (IS_ERR(base)) base 287 drivers/rtc/rtc-sa1100.c return PTR_ERR(base); base 291 drivers/rtc/rtc-sa1100.c info->rcnr = base + 0x04; base 292 drivers/rtc/rtc-sa1100.c info->rtsr = base + 0x10; base 293 drivers/rtc/rtc-sa1100.c info->rtar = base + 0x00; base 294 drivers/rtc/rtc-sa1100.c info->rttr = base + 0x08; base 296 drivers/rtc/rtc-sa1100.c info->rcnr = base + 0x0; base 297 drivers/rtc/rtc-sa1100.c info->rtsr = base + 0x8; base 298 drivers/rtc/rtc-sa1100.c info->rtar = base + 0x4; base 299 drivers/rtc/rtc-sa1100.c info->rttr = base + 0xc; base 107 drivers/rtc/rtc-sc27xx.c u32 base; base 128 drivers/rtc/rtc-sc27xx.c return regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR, base 137 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_SPG_VALUE, &val); base 147 drivers/rtc/rtc-sc27xx.c ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_SPG_UPD, val); base 153 drivers/rtc/rtc-sc27xx.c rtc->base + SPRD_RTC_INT_RAW_STS, val, base 162 drivers/rtc/rtc-sc27xx.c return regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR, base 196 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + sec_reg, &val); base 202 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + min_reg, &val); base 208 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + hour_reg, &val); base 214 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + day_reg, &val); base 263 drivers/rtc/rtc-sc27xx.c ret = regmap_write(rtc->regmap, rtc->base + sec_reg, sec); base 267 drivers/rtc/rtc-sc27xx.c ret = regmap_write(rtc->regmap, rtc->base + min_reg, min); base 271 drivers/rtc/rtc-sc27xx.c ret = regmap_write(rtc->regmap, rtc->base + hour_reg, hour); base 275 drivers/rtc/rtc-sc27xx.c ret = regmap_write(rtc->regmap, rtc->base + day_reg, day); base 289 drivers/rtc/rtc-sc27xx.c rtc->base + SPRD_RTC_INT_RAW_STS, val, base 298 drivers/rtc/rtc-sc27xx.c return regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR, base 315 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_EN, &val); base 321 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_RAW_STS, &val); base 336 drivers/rtc/rtc-sc27xx.c ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR, base 347 drivers/rtc/rtc-sc27xx.c rtc->base + SPRD_RTC_INT_EN, base 352 drivers/rtc/rtc-sc27xx.c rtc->base + SPRD_RTC_INT_EN, base 390 drivers/rtc/rtc-sc27xx.c ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_PWR_CTRL, base 399 drivers/rtc/rtc-sc27xx.c ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_PWR_CTRL, base 434 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_EN, &val); base 440 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_INT_RAW_STS, &val); base 473 drivers/rtc/rtc-sc27xx.c ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR, base 484 drivers/rtc/rtc-sc27xx.c rtc->base + SPRD_RTC_INT_EN, base 494 drivers/rtc/rtc-sc27xx.c rtc->base + SPRD_RTC_INT_EN, base 514 drivers/rtc/rtc-sc27xx.c rtc->base + SPRD_RTC_INT_EN, base 522 drivers/rtc/rtc-sc27xx.c regmap_update_bits(rtc->regmap, rtc->base + SPRD_RTC_INT_EN, base 557 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_PWR_STS, &val); base 575 drivers/rtc/rtc-sc27xx.c ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_SPG_VALUE, &val); base 592 drivers/rtc/rtc-sc27xx.c return regmap_update_bits(rtc->regmap, rtc->base + SPRD_RTC_INT_EN, base 610 drivers/rtc/rtc-sc27xx.c ret = of_property_read_u32(node, "reg", &rtc->base); base 122 drivers/rtc/rtc-stm32.c void __iomem *base; base 137 drivers/rtc/rtc-stm32.c writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr); base 138 drivers/rtc/rtc-stm32.c writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr); base 145 drivers/rtc/rtc-stm32.c writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr); base 151 drivers/rtc/rtc-stm32.c unsigned int isr = readl_relaxed(rtc->base + regs->isr); base 155 drivers/rtc/rtc-stm32.c writel_relaxed(isr, rtc->base + regs->isr); base 164 drivers/rtc/rtc-stm32.c rtc->base + regs->isr, base 175 drivers/rtc/rtc-stm32.c unsigned int isr = readl_relaxed(rtc->base + regs->isr); base 178 drivers/rtc/rtc-stm32.c writel_relaxed(isr, rtc->base + regs->isr); base 184 drivers/rtc/rtc-stm32.c unsigned int isr = readl_relaxed(rtc->base + regs->isr); base 187 drivers/rtc/rtc-stm32.c writel_relaxed(isr, rtc->base + regs->isr); base 193 drivers/rtc/rtc-stm32.c return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, base 214 drivers/rtc/rtc-stm32.c status = readl_relaxed(rtc->base + regs->sr); base 215 drivers/rtc/rtc-stm32.c cr = readl_relaxed(rtc->base + regs->cr); base 277 drivers/rtc/rtc-stm32.c tr = readl_relaxed(rtc->base + regs->tr); base 278 drivers/rtc/rtc-stm32.c dr = readl_relaxed(rtc->base + regs->dr); base 324 drivers/rtc/rtc-stm32.c writel_relaxed(tr, rtc->base + regs->tr); base 325 drivers/rtc/rtc-stm32.c writel_relaxed(dr, rtc->base + regs->dr); base 344 drivers/rtc/rtc-stm32.c alrmar = readl_relaxed(rtc->base + regs->alrmar); base 345 drivers/rtc/rtc-stm32.c cr = readl_relaxed(rtc->base + regs->cr); base 346 drivers/rtc/rtc-stm32.c status = readl_relaxed(rtc->base + regs->sr); base 411 drivers/rtc/rtc-stm32.c cr = readl_relaxed(rtc->base + regs->cr); base 420 drivers/rtc/rtc-stm32.c writel_relaxed(cr, rtc->base + regs->cr); base 434 drivers/rtc/rtc-stm32.c unsigned int dr = readl_relaxed(rtc->base + regs->dr); base 435 drivers/rtc/rtc-stm32.c unsigned int tr = readl_relaxed(rtc->base + regs->tr); base 501 drivers/rtc/rtc-stm32.c cr = readl_relaxed(rtc->base + regs->cr); base 503 drivers/rtc/rtc-stm32.c writel_relaxed(cr, rtc->base + regs->cr); base 509 drivers/rtc/rtc-stm32.c ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, base 520 drivers/rtc/rtc-stm32.c writel_relaxed(alrmar, rtc->base + regs->alrmar); base 543 drivers/rtc/rtc-stm32.c writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags, base 544 drivers/rtc/rtc-stm32.c rtc->base + regs->isr); base 597 drivers/rtc/rtc-stm32.c writel_relaxed(flags, rtc->base + regs.scr); base 674 drivers/rtc/rtc-stm32.c writel_relaxed(prer, rtc->base + regs->prer); base 676 drivers/rtc/rtc-stm32.c writel_relaxed(prer, rtc->base + regs->prer); base 679 drivers/rtc/rtc-stm32.c cr = readl_relaxed(rtc->base + regs->cr); base 681 drivers/rtc/rtc-stm32.c writel_relaxed(cr, rtc->base + regs->cr); base 704 drivers/rtc/rtc-stm32.c rtc->base = devm_ioremap_resource(&pdev->dev, res); base 705 drivers/rtc/rtc-stm32.c if (IS_ERR(rtc->base)) base 706 drivers/rtc/rtc-stm32.c return PTR_ERR(rtc->base); base 823 drivers/rtc/rtc-stm32.c if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS)) base 827 drivers/rtc/rtc-stm32.c u32 ver = readl_relaxed(rtc->base + regs->verr); base 857 drivers/rtc/rtc-stm32.c cr = readl_relaxed(rtc->base + regs->cr); base 859 drivers/rtc/rtc-stm32.c writel_relaxed(cr, rtc->base + regs->cr); base 141 drivers/rtc/rtc-sun6i.c void __iomem *base; base 161 drivers/rtc/rtc-sun6i.c val = readl(rtc->base + SUN6I_LOSC_CTRL); base 169 drivers/rtc/rtc-sun6i.c val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); base 180 drivers/rtc/rtc-sun6i.c return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; base 193 drivers/rtc/rtc-sun6i.c val = readl(rtc->base + SUN6I_LOSC_CTRL); base 201 drivers/rtc/rtc-sun6i.c writel(val, rtc->base + SUN6I_LOSC_CTRL); base 241 drivers/rtc/rtc-sun6i.c rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); base 242 drivers/rtc/rtc-sun6i.c if (IS_ERR(rtc->base)) { base 251 drivers/rtc/rtc-sun6i.c writel(reg, rtc->base + SUN6I_LOSC_CTRL); base 258 drivers/rtc/rtc-sun6i.c writel(reg, rtc->base + SUN6I_LOSC_CTRL); base 301 drivers/rtc/rtc-sun6i.c 0, rtc->base + SUN6I_LOSC_OUT_GATING, base 418 drivers/rtc/rtc-sun6i.c val = readl(chip->base + SUN6I_ALRM_IRQ_STA); base 422 drivers/rtc/rtc-sun6i.c writel(val, chip->base + SUN6I_ALRM_IRQ_STA); base 446 drivers/rtc/rtc-sun6i.c chip->base + SUN6I_ALRM_IRQ_STA); base 450 drivers/rtc/rtc-sun6i.c writel(alrm_val, chip->base + SUN6I_ALRM_EN); base 451 drivers/rtc/rtc-sun6i.c writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); base 452 drivers/rtc/rtc-sun6i.c writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); base 465 drivers/rtc/rtc-sun6i.c date = readl(chip->base + SUN6I_RTC_YMD); base 466 drivers/rtc/rtc-sun6i.c time = readl(chip->base + SUN6I_RTC_HMS); base 467 drivers/rtc/rtc-sun6i.c } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || base 468 drivers/rtc/rtc-sun6i.c (time != readl(chip->base + SUN6I_RTC_HMS))); base 497 drivers/rtc/rtc-sun6i.c alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); base 498 drivers/rtc/rtc-sun6i.c alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); base 539 drivers/rtc/rtc-sun6i.c writel(0, chip->base + SUN6I_ALRM_COUNTER); base 542 drivers/rtc/rtc-sun6i.c writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); base 557 drivers/rtc/rtc-sun6i.c reg = readl(chip->base + offset); base 603 drivers/rtc/rtc-sun6i.c writel(time, chip->base + SUN6I_RTC_HMS); base 617 drivers/rtc/rtc-sun6i.c writel(date, chip->base + SUN6I_RTC_YMD); base 702 drivers/rtc/rtc-sun6i.c writel(0, chip->base + SUN6I_ALRM_COUNTER); base 705 drivers/rtc/rtc-sun6i.c writel(0, chip->base + SUN6I_ALRM_EN); base 708 drivers/rtc/rtc-sun6i.c writel(0, chip->base + SUN6I_ALRM_IRQ_EN); base 711 drivers/rtc/rtc-sun6i.c writel(0, chip->base + SUN6I_ALRM1_EN); base 714 drivers/rtc/rtc-sun6i.c writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); base 718 drivers/rtc/rtc-sun6i.c chip->base + SUN6I_ALRM_IRQ_STA); base 722 drivers/rtc/rtc-sun6i.c chip->base + SUN6I_ALRM1_IRQ_STA); base 725 drivers/rtc/rtc-sun6i.c writel(0, chip->base + SUN6I_ALARM_CONFIG); base 142 drivers/rtc/rtc-sunxi.c void __iomem *base; base 151 drivers/rtc/rtc-sunxi.c val = readl(chip->base + SUNXI_ALRM_IRQ_STA); base 155 drivers/rtc/rtc-sunxi.c writel(val, chip->base + SUNXI_ALRM_IRQ_STA); base 171 drivers/rtc/rtc-sunxi.c alrm_val = readl(chip->base + SUNXI_ALRM_EN); base 174 drivers/rtc/rtc-sunxi.c alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN); base 178 drivers/rtc/rtc-sunxi.c chip->base + SUNXI_ALRM_IRQ_STA); base 181 drivers/rtc/rtc-sunxi.c writel(alrm_val, chip->base + SUNXI_ALRM_EN); base 182 drivers/rtc/rtc-sunxi.c writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN); base 193 drivers/rtc/rtc-sunxi.c alrm = readl(chip->base + SUNXI_ALRM_DHMS); base 194 drivers/rtc/rtc-sunxi.c date = readl(chip->base + SUNXI_RTC_YMD); base 213 drivers/rtc/rtc-sunxi.c alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN); base 229 drivers/rtc/rtc-sunxi.c date = readl(chip->base + SUNXI_RTC_YMD); base 230 drivers/rtc/rtc-sunxi.c time = readl(chip->base + SUNXI_RTC_HMS); base 231 drivers/rtc/rtc-sunxi.c } while ((date != readl(chip->base + SUNXI_RTC_YMD)) || base 232 drivers/rtc/rtc-sunxi.c (time != readl(chip->base + SUNXI_RTC_HMS))); base 293 drivers/rtc/rtc-sunxi.c writel(0, chip->base + SUNXI_ALRM_DHMS); base 300 drivers/rtc/rtc-sunxi.c writel(alrm, chip->base + SUNXI_ALRM_DHMS); base 302 drivers/rtc/rtc-sunxi.c writel(0, chip->base + SUNXI_ALRM_IRQ_EN); base 303 drivers/rtc/rtc-sunxi.c writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN); base 317 drivers/rtc/rtc-sunxi.c reg = readl(chip->base + offset); base 363 drivers/rtc/rtc-sunxi.c writel(0, chip->base + SUNXI_RTC_HMS); base 364 drivers/rtc/rtc-sunxi.c writel(0, chip->base + SUNXI_RTC_YMD); base 366 drivers/rtc/rtc-sunxi.c writel(time, chip->base + SUNXI_RTC_HMS); base 380 drivers/rtc/rtc-sunxi.c writel(date, chip->base + SUNXI_RTC_YMD); base 440 drivers/rtc/rtc-sunxi.c chip->base = devm_ioremap_resource(&pdev->dev, res); base 441 drivers/rtc/rtc-sunxi.c if (IS_ERR(chip->base)) base 442 drivers/rtc/rtc-sunxi.c return PTR_ERR(chip->base); base 461 drivers/rtc/rtc-sunxi.c writel(0, chip->base + SUNXI_ALRM_DHMS); base 464 drivers/rtc/rtc-sunxi.c writel(0, chip->base + SUNXI_ALRM_EN); base 467 drivers/rtc/rtc-sunxi.c writel(0, chip->base + SUNXI_ALRM_IRQ_EN); base 470 drivers/rtc/rtc-sunxi.c writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base + base 51 drivers/rtc/rtc-tegra.c void __iomem *base; /* NULL if not initialized */ base 64 drivers/rtc/rtc-tegra.c return readl(info->base + TEGRA_RTC_REG_BUSY) & 1; base 114 drivers/rtc/rtc-tegra.c msec = readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS); base 115 drivers/rtc/rtc-tegra.c sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS); base 140 drivers/rtc/rtc-tegra.c writel(sec, info->base + TEGRA_RTC_REG_SECONDS); base 143 drivers/rtc/rtc-tegra.c readl(info->base + TEGRA_RTC_REG_SECONDS)); base 153 drivers/rtc/rtc-tegra.c sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0); base 164 drivers/rtc/rtc-tegra.c value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS); base 180 drivers/rtc/rtc-tegra.c status = readl(info->base + TEGRA_RTC_REG_INTR_MASK); base 186 drivers/rtc/rtc-tegra.c writel(status, info->base + TEGRA_RTC_REG_INTR_MASK); base 204 drivers/rtc/rtc-tegra.c writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0); base 206 drivers/rtc/rtc-tegra.c readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0)); base 238 drivers/rtc/rtc-tegra.c status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS); base 244 drivers/rtc/rtc-tegra.c writel(0, info->base + TEGRA_RTC_REG_INTR_MASK); base 245 drivers/rtc/rtc-tegra.c writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS); base 288 drivers/rtc/rtc-tegra.c info->base = devm_ioremap_resource(&pdev->dev, res); base 289 drivers/rtc/rtc-tegra.c if (IS_ERR(info->base)) base 290 drivers/rtc/rtc-tegra.c return PTR_ERR(info->base); base 320 drivers/rtc/rtc-tegra.c writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0); base 321 drivers/rtc/rtc-tegra.c writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS); base 322 drivers/rtc/rtc-tegra.c writel(0, info->base + TEGRA_RTC_REG_INTR_MASK); base 364 drivers/rtc/rtc-tegra.c writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS); base 366 drivers/rtc/rtc-tegra.c info->base + TEGRA_RTC_REG_INTR_MASK); base 369 drivers/rtc/rtc-tegra.c readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0)); base 350 drivers/s390/block/dasd.c if (block->base->discipline->do_analysis != NULL) base 351 drivers/s390/block/dasd.c rc = block->base->discipline->do_analysis(block); base 858 drivers/s390/block/dasd.c cqr->startdev != block->base, base 876 drivers/s390/block/dasd.c cqr->startdev != block->base, base 894 drivers/s390/block/dasd.c cqr->startdev != block->base, base 1440 drivers/s390/block/dasd.c test_bit(DASD_FLAG_LOCK_STOLEN, &cqr->block->base->flags)) || base 1649 drivers/s390/block/dasd.c device = block->base; base 2710 drivers/s390/block/dasd.c spin_lock_irqsave(get_ccwdev_lock(block->base->cdev), flags); base 2712 drivers/s390/block/dasd.c dasd_device_remove_stop_bits(block->base, DASD_STOPPED_PENDING); base 2713 drivers/s390/block/dasd.c spin_unlock_irqrestore(get_ccwdev_lock(block->base->cdev), flags); base 2766 drivers/s390/block/dasd.c status = cqr->block->base->discipline->free_cp(cqr, req); base 2821 drivers/s390/block/dasd.c struct dasd_device *base = block->base; base 2834 drivers/s390/block/dasd.c base->discipline->handle_terminated_request(cqr); base 2840 drivers/s390/block/dasd.c erp_fn = base->discipline->erp_action(cqr); base 2852 drivers/s390/block/dasd.c if (dasd_eer_enabled(base) && base 2854 drivers/s390/block/dasd.c dasd_eer_write(base, cqr, DASD_EER_FATALERROR); base 2859 drivers/s390/block/dasd.c spin_lock_irqsave(get_ccwdev_lock(base->cdev), flags); base 2860 drivers/s390/block/dasd.c dasd_device_set_stop_bits(base, DASD_STOPPED_QUIESCE); base 2861 drivers/s390/block/dasd.c spin_unlock_irqrestore(get_ccwdev_lock(base->cdev), base 2868 drivers/s390/block/dasd.c __dasd_process_erp(base, cqr); base 2896 drivers/s390/block/dasd.c if (test_bit(DASD_FLAG_LOCK_STOLEN, &block->base->flags) && base 2904 drivers/s390/block/dasd.c if (block->base->stopped & ~DASD_STOPPED_PENDING && base 2906 drivers/s390/block/dasd.c (!dasd_eer_enabled(block->base))) { base 2913 drivers/s390/block/dasd.c if (block->base->stopped) base 2918 drivers/s390/block/dasd.c cqr->startdev = block->base; base 2964 drivers/s390/block/dasd.c dasd_put_device(block->base); base 3033 drivers/s390/block/dasd.c __dasd_process_erp(block->base, cqr); base 3058 drivers/s390/block/dasd.c dasd_get_device(block->base); base 3082 drivers/s390/block/dasd.c basedev = block->base; base 3176 drivers/s390/block/dasd.c device = cqr->startdev ? cqr->startdev : block->base; base 3306 drivers/s390/block/dasd.c struct dasd_device *base; base 3309 drivers/s390/block/dasd.c base = dasd_device_from_gendisk(bdev->bd_disk); base 3310 drivers/s390/block/dasd.c if (!base) base 3313 drivers/s390/block/dasd.c atomic_inc(&base->block->open_count); base 3314 drivers/s390/block/dasd.c if (test_bit(DASD_FLAG_OFFLINE, &base->flags)) { base 3319 drivers/s390/block/dasd.c if (!try_module_get(base->discipline->owner)) { base 3325 drivers/s390/block/dasd.c dev_info(&base->cdev->dev, base 3332 drivers/s390/block/dasd.c if (base->state <= DASD_STATE_BASIC) { base 3333 drivers/s390/block/dasd.c DBF_DEV_EVENT(DBF_ERR, base, " %s", base 3340 drivers/s390/block/dasd.c (test_bit(DASD_FLAG_DEVICE_RO, &base->flags) || base 3341 drivers/s390/block/dasd.c (base->features & DASD_FEATURE_READONLY))) { base 3346 drivers/s390/block/dasd.c dasd_put_device(base); base 3350 drivers/s390/block/dasd.c module_put(base->discipline->owner); base 3352 drivers/s390/block/dasd.c atomic_dec(&base->block->open_count); base 3353 drivers/s390/block/dasd.c dasd_put_device(base); base 3359 drivers/s390/block/dasd.c struct dasd_device *base = dasd_device_from_gendisk(disk); base 3360 drivers/s390/block/dasd.c if (base) { base 3361 drivers/s390/block/dasd.c atomic_dec(&base->block->open_count); base 3362 drivers/s390/block/dasd.c module_put(base->discipline->owner); base 3363 drivers/s390/block/dasd.c dasd_put_device(base); base 3372 drivers/s390/block/dasd.c struct dasd_device *base; base 3374 drivers/s390/block/dasd.c base = dasd_device_from_gendisk(bdev->bd_disk); base 3375 drivers/s390/block/dasd.c if (!base) base 3378 drivers/s390/block/dasd.c if (!base->discipline || base 3379 drivers/s390/block/dasd.c !base->discipline->fill_geometry) { base 3380 drivers/s390/block/dasd.c dasd_put_device(base); base 3383 drivers/s390/block/dasd.c base->discipline->fill_geometry(base->block, geo); base 3384 drivers/s390/block/dasd.c geo->start = get_start_sect(bdev) >> base->block->s2b_shift; base 3385 drivers/s390/block/dasd.c dasd_put_device(base); base 4017 drivers/s390/block/dasd.c cqr->block->base->discipline->free_cp( base 1439 drivers/s390/block/dasd_3990_erp.c (cqr->block->base != cqr->startdev)) { base 1463 drivers/s390/block/dasd_3990_erp.c dev_name(&cqr->block->base->cdev->dev)); base 1466 drivers/s390/block/dasd_3990_erp.c erp->startdev = cqr->block->base; base 347 drivers/s390/block/dasd_diag.c block->base = device; base 563 drivers/s390/block/dasd_diag.c block->base->features & DASD_FEATURE_FAILFAST) base 102 drivers/s390/block/dasd_eckd.c struct dasd_device *base; base 1662 drivers/s390/block/dasd_eckd.c struct dasd_device *base; base 1666 drivers/s390/block/dasd_eckd.c base = data->base; base 1668 drivers/s390/block/dasd_eckd.c if (!base) base 1669 drivers/s390/block/dasd_eckd.c base = device; base 1670 drivers/s390/block/dasd_eckd.c if (dasd_eckd_space_configured(base) != 0) { base 1694 drivers/s390/block/dasd_eckd.c data->base = cqr->block->base; base 1696 drivers/s390/block/dasd_eckd.c data->base = cqr->basedev; base 1698 drivers/s390/block/dasd_eckd.c data->base = NULL; base 2044 drivers/s390/block/dasd_eckd.c block->base = device; base 2237 drivers/s390/block/dasd_eckd.c init_cqr = dasd_eckd_analysis_ccw(block->base); base 2254 drivers/s390/block/dasd_eckd.c struct dasd_device *device = block->base; base 2358 drivers/s390/block/dasd_eckd.c struct dasd_eckd_private *private = block->base->private; base 2389 drivers/s390/block/dasd_eckd.c struct dasd_eckd_private *private = block->base->private; base 2404 drivers/s390/block/dasd_eckd.c dasd_eckd_build_check_tcw(struct dasd_device *base, struct format_data_t *fdata, base 2419 drivers/s390/block/dasd_eckd.c startdev = dasd_alias_get_start_dev(base); base 2422 drivers/s390/block/dasd_eckd.c startdev = base; base 2448 drivers/s390/block/dasd_eckd.c DASD_ECKD_CCW_READ_COUNT_MT, base, startdev, 0, count, base 2469 drivers/s390/block/dasd_eckd.c cqr->basedev = base; base 2490 drivers/s390/block/dasd_eckd.c dasd_eckd_build_check(struct dasd_device *base, struct format_data_t *fdata, base 2505 drivers/s390/block/dasd_eckd.c startdev = dasd_alias_get_start_dev(base); base 2508 drivers/s390/block/dasd_eckd.c startdev = base; base 2511 drivers/s390/block/dasd_eckd.c base_priv = base->private; base 2537 drivers/s390/block/dasd_eckd.c DASD_ECKD_CCW_READ_COUNT, base, startdev, 1, 0, base 2547 drivers/s390/block/dasd_eckd.c DASD_ECKD_CCW_READ_COUNT, base, 0); base 2562 drivers/s390/block/dasd_eckd.c cqr->basedev = base; base 2574 drivers/s390/block/dasd_eckd.c dasd_eckd_build_format(struct dasd_device *base, struct dasd_device *startdev, base 2593 drivers/s390/block/dasd_eckd.c startdev = dasd_alias_get_start_dev(base); base 2596 drivers/s390/block/dasd_eckd.c startdev = base; base 2599 drivers/s390/block/dasd_eckd.c base_priv = base->private; base 2683 drivers/s390/block/dasd_eckd.c DASD_ECKD_CCW_WRITE_CKD, base, startdev); base 2702 drivers/s390/block/dasd_eckd.c DASD_ECKD_CCW_WRITE_CKD, base, base 2711 drivers/s390/block/dasd_eckd.c base, startdev); base 2722 drivers/s390/block/dasd_eckd.c DASD_ECKD_CCW_WRITE_RECORD_ZERO, base, base 2723 drivers/s390/block/dasd_eckd.c base->block->bp_block); base 2730 drivers/s390/block/dasd_eckd.c DASD_ECKD_CCW_WRITE_CKD, base, startdev); base 2741 drivers/s390/block/dasd_eckd.c DASD_ECKD_CCW_WRITE_CKD, base, 8); base 2823 drivers/s390/block/dasd_eckd.c fcp->basedev = base; base 2836 drivers/s390/block/dasd_eckd.c dasd_eckd_format_build_ccw_req(struct dasd_device *base, base 2843 drivers/s390/block/dasd_eckd.c ccw_req = dasd_eckd_build_format(base, NULL, fdata, enable_pav); base 2846 drivers/s390/block/dasd_eckd.c ccw_req = dasd_eckd_build_check_tcw(base, fdata, base 2850 drivers/s390/block/dasd_eckd.c ccw_req = dasd_eckd_build_check(base, fdata, enable_pav, base 2860 drivers/s390/block/dasd_eckd.c static int dasd_eckd_format_sanity_checks(struct dasd_device *base, base 2863 drivers/s390/block/dasd_eckd.c struct dasd_eckd_private *private = base->private; base 2867 drivers/s390/block/dasd_eckd.c dev_warn(&base->cdev->dev, base 2874 drivers/s390/block/dasd_eckd.c dev_warn(&base->cdev->dev, base 2880 drivers/s390/block/dasd_eckd.c dev_warn(&base->cdev->dev, base 2886 drivers/s390/block/dasd_eckd.c dev_warn(&base->cdev->dev, base 2897 drivers/s390/block/dasd_eckd.c static int dasd_eckd_format_process_data(struct dasd_device *base, base 2903 drivers/s390/block/dasd_eckd.c struct dasd_eckd_private *private = base->private; base 2912 drivers/s390/block/dasd_eckd.c rc = dasd_eckd_format_sanity_checks(base, fdata); base 2942 drivers/s390/block/dasd_eckd.c cqr = dasd_eckd_format_build_ccw_req(base, fdata, base 3021 drivers/s390/block/dasd_eckd.c static int dasd_eckd_format_device(struct dasd_device *base, base 3024 drivers/s390/block/dasd_eckd.c return dasd_eckd_format_process_data(base, fdata, enable_pav, 0, NULL, base 3082 drivers/s390/block/dasd_eckd.c struct dasd_device *base; base 3093 drivers/s390/block/dasd_eckd.c base = block->base; base 3094 drivers/s390/block/dasd_eckd.c private = base->private; base 3104 drivers/s390/block/dasd_eckd.c rc = dasd_eckd_track_from_irb(irb, base, &curr_trk); base 3124 drivers/s390/block/dasd_eckd.c rc = dasd_eckd_format_sanity_checks(base, &fdata); base 3132 drivers/s390/block/dasd_eckd.c fcqr = dasd_eckd_build_format(base, startdev, &fdata, 0); base 3161 drivers/s390/block/dasd_eckd.c struct dasd_device *base; base 3174 drivers/s390/block/dasd_eckd.c base = cqr->block->base; base 3175 drivers/s390/block/dasd_eckd.c blksize = base->block->bp_block; base 3177 drivers/s390/block/dasd_eckd.c private = base->private; base 3187 drivers/s390/block/dasd_eckd.c rc = dasd_eckd_track_from_irb(irb, base, &curr_trk); base 3193 drivers/s390/block/dasd_eckd.c DBF_DEV_EVENT(DBF_WARNING, base, base 3374 drivers/s390/block/dasd_eckd.c static int dasd_eckd_check_device_format(struct dasd_device *base, base 3378 drivers/s390/block/dasd_eckd.c struct dasd_eckd_private *private = base->private; base 3413 drivers/s390/block/dasd_eckd.c rc = dasd_eckd_format_process_data(base, &cdata->expect, enable_pav, base 3425 drivers/s390/block/dasd_eckd.c rc = dasd_eckd_format_process_data(base, &cdata->expect, base 3452 drivers/s390/block/dasd_eckd.c if (cqr->block && (cqr->startdev != cqr->block->base)) { base 3454 drivers/s390/block/dasd_eckd.c cqr->startdev = cqr->block->base; base 3455 drivers/s390/block/dasd_eckd.c cqr->lpm = dasd_path_get_opm(cqr->block->base); base 3854 drivers/s390/block/dasd_eckd.c basedev = block->base; base 3997 drivers/s390/block/dasd_eckd.c block->base->features & DASD_FEATURE_FAILFAST) base 4048 drivers/s390/block/dasd_eckd.c basedev = block->base; base 4176 drivers/s390/block/dasd_eckd.c block->base->features & DASD_FEATURE_FAILFAST) base 4383 drivers/s390/block/dasd_eckd.c basedev = block->base; base 4499 drivers/s390/block/dasd_eckd.c block->base->features & DASD_FEATURE_FAILFAST) base 4541 drivers/s390/block/dasd_eckd.c basedev = block->base; base 4637 drivers/s390/block/dasd_eckd.c basedev = block->base; base 4743 drivers/s390/block/dasd_eckd.c block->base->features & DASD_FEATURE_FAILFAST) base 4772 drivers/s390/block/dasd_eckd.c private = cqr->block->base->private; base 4844 drivers/s390/block/dasd_eckd.c static struct dasd_ccw_req *dasd_eckd_build_alias_cp(struct dasd_device *base, base 4853 drivers/s390/block/dasd_eckd.c startdev = dasd_alias_get_start_dev(base); base 4855 drivers/s390/block/dasd_eckd.c startdev = base; base 4862 drivers/s390/block/dasd_eckd.c if ((base->features & DASD_FEATURE_USERAW)) base 5366 drivers/s390/block/dasd_eckd.c struct dasd_device *device = block->base; base 6633 drivers/s390/block/dasd_eckd.c struct dasd_device *device = block->base; base 155 drivers/s390/block/dasd_fba.c block->base = device; base 197 drivers/s390/block/dasd_fba.c struct dasd_fba_private *private = block->base->private; base 202 drivers/s390/block/dasd_fba.c DBF_DEV_EVENT(DBF_WARNING, block->base, "unknown blocksize %d", base 423 drivers/s390/block/dasd_fba.c block->base->features & DASD_FEATURE_FAILFAST) base 442 drivers/s390/block/dasd_fba.c struct dasd_fba_private *private = block->base->private; base 552 drivers/s390/block/dasd_fba.c block->base->features & DASD_FEATURE_FAILFAST) base 577 drivers/s390/block/dasd_fba.c struct dasd_fba_private *private = cqr->block->base->private; base 33 drivers/s390/block/dasd_genhd.c struct dasd_device *base; base 37 drivers/s390/block/dasd_genhd.c base = block->base; base 38 drivers/s390/block/dasd_genhd.c if (base->devindex >= DASD_PER_MAJOR) base 47 drivers/s390/block/dasd_genhd.c gdp->first_minor = base->devindex << DASD_PARTN_BITS; base 58 drivers/s390/block/dasd_genhd.c if (base->devindex > 25) { base 59 drivers/s390/block/dasd_genhd.c if (base->devindex > 701) { base 60 drivers/s390/block/dasd_genhd.c if (base->devindex > 18277) base 62 drivers/s390/block/dasd_genhd.c 'a'+(((base->devindex-18278) base 65 drivers/s390/block/dasd_genhd.c 'a'+(((base->devindex-702)/676)%26)); base 68 drivers/s390/block/dasd_genhd.c 'a'+(((base->devindex-26)/26)%26)); base 70 drivers/s390/block/dasd_genhd.c len += sprintf(gdp->disk_name + len, "%c", 'a'+(base->devindex%26)); base 72 drivers/s390/block/dasd_genhd.c if (base->features & DASD_FEATURE_READONLY || base 73 drivers/s390/block/dasd_genhd.c test_bit(DASD_FLAG_DEVICE_RO, &base->flags)) base 75 drivers/s390/block/dasd_genhd.c dasd_add_link_to_gendisk(gdp, base); base 79 drivers/s390/block/dasd_genhd.c device_add_disk(&base->cdev->dev, block->gdp, NULL); base 106 drivers/s390/block/dasd_genhd.c DBF_DEV_EVENT(DBF_ERR, block->base, "%s", base 113 drivers/s390/block/dasd_genhd.c DBF_DEV_EVENT(DBF_ERR, block->base, base 121 drivers/s390/block/dasd_genhd.c DBF_DEV_EVENT(DBF_ERR, block->base, base 565 drivers/s390/block/dasd_int.h struct dasd_device *base; base 46 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 51 drivers/s390/block/dasd_ioctl.c base = dasd_device_from_gendisk(bdev->bd_disk); base 52 drivers/s390/block/dasd_ioctl.c if (!base) base 55 drivers/s390/block/dasd_ioctl.c dasd_enable_device(base); base 59 drivers/s390/block/dasd_ioctl.c (loff_t)get_capacity(base->block->gdp) << 9); base 61 drivers/s390/block/dasd_ioctl.c dasd_put_device(base); base 72 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 77 drivers/s390/block/dasd_ioctl.c base = dasd_device_from_gendisk(bdev->bd_disk); base 78 drivers/s390/block/dasd_ioctl.c if (!base) base 88 drivers/s390/block/dasd_ioctl.c dasd_set_target_state(base, DASD_STATE_BASIC); base 96 drivers/s390/block/dasd_ioctl.c dasd_put_device(base); base 106 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 108 drivers/s390/block/dasd_ioctl.c base = block->base; base 113 drivers/s390/block/dasd_ioctl.c "state\n", dev_name(&base->cdev->dev)); base 114 drivers/s390/block/dasd_ioctl.c spin_lock_irqsave(get_ccwdev_lock(base->cdev), flags); base 115 drivers/s390/block/dasd_ioctl.c dasd_device_set_stop_bits(base, DASD_STOPPED_QUIESCE); base 116 drivers/s390/block/dasd_ioctl.c spin_unlock_irqrestore(get_ccwdev_lock(base->cdev), flags); base 127 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 129 drivers/s390/block/dasd_ioctl.c base = block->base; base 134 drivers/s390/block/dasd_ioctl.c "on the DASD\n", dev_name(&base->cdev->dev)); base 135 drivers/s390/block/dasd_ioctl.c spin_lock_irqsave(get_ccwdev_lock(base->cdev), flags); base 136 drivers/s390/block/dasd_ioctl.c dasd_device_remove_stop_bits(base, DASD_STOPPED_QUIESCE); base 137 drivers/s390/block/dasd_ioctl.c spin_unlock_irqrestore(get_ccwdev_lock(base->cdev), flags); base 149 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 152 drivers/s390/block/dasd_ioctl.c base = block->base; base 156 drivers/s390/block/dasd_ioctl.c if (test_and_set_bit(DASD_FLAG_ABORTALL, &base->flags)) base 158 drivers/s390/block/dasd_ioctl.c DBF_DEV_EVENT(DBF_NOTICE, base, "%s", "abortall flag set"); base 184 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 186 drivers/s390/block/dasd_ioctl.c base = block->base; base 190 drivers/s390/block/dasd_ioctl.c if (test_and_clear_bit(DASD_FLAG_ABORTALL, &base->flags)) base 191 drivers/s390/block/dasd_ioctl.c DBF_DEV_EVENT(DBF_NOTICE, base, "%s", "abortall flag unset"); base 205 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 208 drivers/s390/block/dasd_ioctl.c base = block->base; base 209 drivers/s390/block/dasd_ioctl.c if (base->discipline->format_device == NULL) base 212 drivers/s390/block/dasd_ioctl.c if (base->state != DASD_STATE_BASIC) { base 214 drivers/s390/block/dasd_ioctl.c dev_name(&base->cdev->dev)); base 218 drivers/s390/block/dasd_ioctl.c DBF_DEV_EVENT(DBF_NOTICE, base, base 234 drivers/s390/block/dasd_ioctl.c rc = base->discipline->format_device(base, fdata, 1); base 236 drivers/s390/block/dasd_ioctl.c rc = base->discipline->format_device(base, fdata, 0); base 244 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 247 drivers/s390/block/dasd_ioctl.c base = block->base; base 248 drivers/s390/block/dasd_ioctl.c if (!base->discipline->check_device_format) base 251 drivers/s390/block/dasd_ioctl.c rc = base->discipline->check_device_format(base, cdata, 1); base 253 drivers/s390/block/dasd_ioctl.c rc = base->discipline->check_device_format(base, cdata, 0); base 264 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 272 drivers/s390/block/dasd_ioctl.c base = dasd_device_from_gendisk(bdev->bd_disk); base 273 drivers/s390/block/dasd_ioctl.c if (!base) base 275 drivers/s390/block/dasd_ioctl.c if (base->features & DASD_FEATURE_READONLY || base 276 drivers/s390/block/dasd_ioctl.c test_bit(DASD_FLAG_DEVICE_RO, &base->flags)) { base 277 drivers/s390/block/dasd_ioctl.c dasd_put_device(base); base 281 drivers/s390/block/dasd_ioctl.c dasd_put_device(base); base 286 drivers/s390/block/dasd_ioctl.c dev_name(&base->cdev->dev)); base 287 drivers/s390/block/dasd_ioctl.c dasd_put_device(base); base 290 drivers/s390/block/dasd_ioctl.c rc = dasd_format(base->block, &fdata); base 291 drivers/s390/block/dasd_ioctl.c dasd_put_device(base); base 302 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 308 drivers/s390/block/dasd_ioctl.c base = dasd_device_from_gendisk(bdev->bd_disk); base 309 drivers/s390/block/dasd_ioctl.c if (!base) base 313 drivers/s390/block/dasd_ioctl.c dev_name(&base->cdev->dev)); base 323 drivers/s390/block/dasd_ioctl.c rc = dasd_check_format(base->block, &cdata); base 331 drivers/s390/block/dasd_ioctl.c dasd_put_device(base); base 353 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 361 drivers/s390/block/dasd_ioctl.c base = dasd_device_from_gendisk(bdev->bd_disk); base 362 drivers/s390/block/dasd_ioctl.c if (!base) base 364 drivers/s390/block/dasd_ioctl.c if (base->features & DASD_FEATURE_READONLY || base 365 drivers/s390/block/dasd_ioctl.c test_bit(DASD_FLAG_DEVICE_RO, &base->flags)) { base 371 drivers/s390/block/dasd_ioctl.c dev_name(&base->cdev->dev)); base 381 drivers/s390/block/dasd_ioctl.c rc = dasd_release_space(base, &rdata); base 384 drivers/s390/block/dasd_ioctl.c dasd_put_device(base); base 466 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 472 drivers/s390/block/dasd_ioctl.c base = block->base; base 473 drivers/s390/block/dasd_ioctl.c if (!base->discipline || !base->discipline->fill_info) base 480 drivers/s390/block/dasd_ioctl.c rc = base->discipline->fill_info(base, dasd_info); base 486 drivers/s390/block/dasd_ioctl.c cdev = base->cdev; base 496 drivers/s390/block/dasd_ioctl.c dasd_info->status = base->state; base 510 drivers/s390/block/dasd_ioctl.c if ((base->state < DASD_STATE_READY) || base 515 drivers/s390/block/dasd_ioctl.c ((base->features & DASD_FEATURE_READONLY) != 0); base 517 drivers/s390/block/dasd_ioctl.c memcpy(dasd_info->type, base->discipline->name, 4); base 520 drivers/s390/block/dasd_ioctl.c list_for_each(l, &base->ccw_queue) base 540 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 550 drivers/s390/block/dasd_ioctl.c base = dasd_device_from_gendisk(bdev->bd_disk); base 551 drivers/s390/block/dasd_ioctl.c if (!base) base 553 drivers/s390/block/dasd_ioctl.c if (!intval && test_bit(DASD_FLAG_DEVICE_RO, &base->flags)) { base 554 drivers/s390/block/dasd_ioctl.c dasd_put_device(base); base 558 drivers/s390/block/dasd_ioctl.c rc = dasd_set_feature(base->cdev, DASD_FEATURE_READONLY, intval); base 559 drivers/s390/block/dasd_ioctl.c dasd_put_device(base); base 570 drivers/s390/block/dasd_ioctl.c ret = cmf_readall(block->base->cdev, &data); base 580 drivers/s390/block/dasd_ioctl.c struct dasd_device *base; base 594 drivers/s390/block/dasd_ioctl.c base = dasd_device_from_gendisk(bdev->bd_disk); base 595 drivers/s390/block/dasd_ioctl.c if (!base) base 597 drivers/s390/block/dasd_ioctl.c block = base->block; base 643 drivers/s390/block/dasd_ioctl.c rc = enable_cmf(base->cdev); base 646 drivers/s390/block/dasd_ioctl.c rc = disable_cmf(base->cdev); base 657 drivers/s390/block/dasd_ioctl.c if (base->discipline->ioctl) base 658 drivers/s390/block/dasd_ioctl.c rc = base->discipline->ioctl(block, cmd, argp); base 660 drivers/s390/block/dasd_ioctl.c dasd_put_device(base); base 221 drivers/s390/char/keyboard.c kbd->accent_table[i].base == ch) base 513 drivers/s390/char/keyboard.c diacr.base = kbd->accent_table[i].base; base 549 drivers/s390/char/keyboard.c kbd->accent_table[i].base = diacr.base; base 161 drivers/s390/char/zcore.c (unsigned long long) reg->base, base 275 drivers/s390/net/qeth_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 276 drivers/s390/net/qeth_ethtool.c cmd->base.autoneg = AUTONEG_ENABLE; base 277 drivers/s390/net/qeth_ethtool.c cmd->base.phy_address = 0; base 278 drivers/s390/net/qeth_ethtool.c cmd->base.mdio_support = 0; base 279 drivers/s390/net/qeth_ethtool.c cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; base 280 drivers/s390/net/qeth_ethtool.c cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_INVALID; base 285 drivers/s390/net/qeth_ethtool.c cmd->base.speed = SPEED_100; base 286 drivers/s390/net/qeth_ethtool.c cmd->base.port = PORT_TP; base 290 drivers/s390/net/qeth_ethtool.c cmd->base.speed = SPEED_1000; base 291 drivers/s390/net/qeth_ethtool.c cmd->base.port = PORT_FIBRE; base 294 drivers/s390/net/qeth_ethtool.c cmd->base.speed = SPEED_10000; base 295 drivers/s390/net/qeth_ethtool.c cmd->base.port = PORT_FIBRE; base 298 drivers/s390/net/qeth_ethtool.c cmd->base.speed = SPEED_25000; base 299 drivers/s390/net/qeth_ethtool.c cmd->base.port = PORT_FIBRE; base 302 drivers/s390/net/qeth_ethtool.c cmd->base.speed = SPEED_10; base 303 drivers/s390/net/qeth_ethtool.c cmd->base.port = PORT_TP; base 305 drivers/s390/net/qeth_ethtool.c qeth_set_cmd_adv_sup(cmd, cmd->base.speed, cmd->base.port); base 328 drivers/s390/net/qeth_ethtool.c cmd->base.port = PORT_TP; base 329 drivers/s390/net/qeth_ethtool.c qeth_set_cmd_adv_sup(cmd, SPEED_1000, cmd->base.port); base 333 drivers/s390/net/qeth_ethtool.c cmd->base.port = PORT_FIBRE; base 334 drivers/s390/net/qeth_ethtool.c qeth_set_cmd_adv_sup(cmd, SPEED_1000, cmd->base.port); base 338 drivers/s390/net/qeth_ethtool.c cmd->base.port = PORT_FIBRE; base 339 drivers/s390/net/qeth_ethtool.c qeth_set_cmd_adv_sup(cmd, SPEED_10000, cmd->base.port); base 345 drivers/s390/net/qeth_ethtool.c cmd->base.duplex = DUPLEX_FULL; base 348 drivers/s390/net/qeth_ethtool.c cmd->base.duplex = DUPLEX_HALF; base 354 drivers/s390/net/qeth_ethtool.c cmd->base.speed = SPEED_10; base 357 drivers/s390/net/qeth_ethtool.c cmd->base.speed = SPEED_100; base 360 drivers/s390/net/qeth_ethtool.c cmd->base.speed = SPEED_1000; base 363 drivers/s390/net/qeth_ethtool.c cmd->base.speed = SPEED_10000; base 366 drivers/s390/net/qeth_ethtool.c cmd->base.speed = SPEED_25000; base 358 drivers/scsi/53c700.c host->unique_id = (unsigned long)hostdata->base; base 199 drivers/scsi/53c700.h void __iomem *base; /* the base for the port (copied to host) */ base 486 drivers/scsi/53c700.h return ioread8(hostdata->base + (reg^bE)); base 494 drivers/scsi/53c700.h __u32 value = bEBus ? ioread32be(hostdata->base + reg) : base 495 drivers/scsi/53c700.h ioread32(hostdata->base + reg); base 510 drivers/scsi/53c700.h iowrite8(value, hostdata->base + (reg^bE)); base 524 drivers/scsi/53c700.h bEBus ? iowrite32be(value, hostdata->base + reg): base 525 drivers/scsi/53c700.h iowrite32(value, hostdata->base + reg); base 417 drivers/scsi/NCR5380.c hostdata->base, instance->can_queue, instance->cmd_per_lun, base 215 drivers/scsi/NCR5380.h unsigned long base; /* Device base address */ base 144 drivers/scsi/a100u2w.c if (inb(host->base + ORC_HCTRL) & HOSTSTOP) /* Wait HOSTSTOP set */ base 156 drivers/scsi/a100u2w.c if (inb(host->base + ORC_HSTUS) & RREADY) /* Wait READY set */ base 169 drivers/scsi/a100u2w.c if (!(inb(host->base + ORC_HCTRL) & SCSIRST)) /* Wait SCSIRST done */ base 182 drivers/scsi/a100u2w.c if (!(inb(host->base + ORC_HCTRL) & HDO)) /* Wait HDO off */ base 195 drivers/scsi/a100u2w.c if ((*data = inb(host->base + ORC_HSTUS)) & HDI) base 208 drivers/scsi/a100u2w.c outb(ORC_CMD_VERSION, host->base + ORC_HDATA); base 209 drivers/scsi/a100u2w.c outb(HDO, host->base + ORC_HCTRL); base 215 drivers/scsi/a100u2w.c version = inb(host->base + ORC_HDATA); base 216 drivers/scsi/a100u2w.c outb(data, host->base + ORC_HSTUS); /* Clear HDI */ base 220 drivers/scsi/a100u2w.c version |= inb(host->base + ORC_HDATA) << 8; base 221 drivers/scsi/a100u2w.c outb(data, host->base + ORC_HSTUS); /* Clear HDI */ base 229 drivers/scsi/a100u2w.c outb(ORC_CMD_SET_NVM, host->base + ORC_HDATA); /* Write command */ base 230 drivers/scsi/a100u2w.c outb(HDO, host->base + ORC_HCTRL); base 234 drivers/scsi/a100u2w.c outb(address, host->base + ORC_HDATA); /* Write address */ base 235 drivers/scsi/a100u2w.c outb(HDO, host->base + ORC_HCTRL); base 239 drivers/scsi/a100u2w.c outb(value, host->base + ORC_HDATA); /* Write value */ base 240 drivers/scsi/a100u2w.c outb(HDO, host->base + ORC_HCTRL); base 252 drivers/scsi/a100u2w.c outb(ORC_CMD_GET_NVM, host->base + ORC_HDATA); /* Write command */ base 253 drivers/scsi/a100u2w.c outb(HDO, host->base + ORC_HCTRL); base 257 drivers/scsi/a100u2w.c outb(address, host->base + ORC_HDATA); /* Write address */ base 258 drivers/scsi/a100u2w.c outb(HDO, host->base + ORC_HCTRL); base 264 drivers/scsi/a100u2w.c *ptr = inb(host->base + ORC_HDATA); base 265 drivers/scsi/a100u2w.c outb(data, host->base + ORC_HSTUS); /* Clear HDI */ base 280 drivers/scsi/a100u2w.c outb(scb->scbidx, host->base + ORC_PQUEUE); base 375 drivers/scsi/a100u2w.c data = inb(host->base + ORC_GCFG); base 376 drivers/scsi/a100u2w.c outb(data | EEPRG, host->base + ORC_GCFG); /* Enable EEPROM programming */ base 377 drivers/scsi/a100u2w.c outb(0x00, host->base + ORC_EBIOSADR2); base 378 drivers/scsi/a100u2w.c outw(0x0000, host->base + ORC_EBIOSADR0); base 379 drivers/scsi/a100u2w.c if (inb(host->base + ORC_EBIOSDATA) != 0x55) { base 380 drivers/scsi/a100u2w.c outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ base 383 drivers/scsi/a100u2w.c outw(0x0001, host->base + ORC_EBIOSADR0); base 384 drivers/scsi/a100u2w.c if (inb(host->base + ORC_EBIOSDATA) != 0xAA) { base 385 drivers/scsi/a100u2w.c outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ base 389 drivers/scsi/a100u2w.c outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Enable SRAM programming */ base 392 drivers/scsi/a100u2w.c outw(0x0010, host->base + ORC_EBIOSADR0); base 393 drivers/scsi/a100u2w.c *data32_ptr = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ base 394 drivers/scsi/a100u2w.c outw(0x0011, host->base + ORC_EBIOSADR0); base 395 drivers/scsi/a100u2w.c *(data32_ptr + 1) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ base 396 drivers/scsi/a100u2w.c outw(0x0012, host->base + ORC_EBIOSADR0); base 397 drivers/scsi/a100u2w.c *(data32_ptr + 2) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ base 398 drivers/scsi/a100u2w.c outw(*(data32_ptr + 2), host->base + ORC_EBIOSADR2); base 399 drivers/scsi/a100u2w.c outl(le32_to_cpu(data32), host->base + ORC_FWBASEADR); /* Write FW address */ base 408 drivers/scsi/a100u2w.c outw(bios_addr, host->base + ORC_EBIOSADR0); base 409 drivers/scsi/a100u2w.c *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ base 411 drivers/scsi/a100u2w.c outl(le32_to_cpu(data32), host->base + ORC_RISCRAM); /* Write every 4 bytes */ base 418 drivers/scsi/a100u2w.c outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Reset program count 0 */ base 423 drivers/scsi/a100u2w.c outw(bios_addr, host->base + ORC_EBIOSADR0); base 424 drivers/scsi/a100u2w.c *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ base 426 drivers/scsi/a100u2w.c if (inl(host->base + ORC_RISCRAM) != le32_to_cpu(data32)) { base 427 drivers/scsi/a100u2w.c outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ base 428 drivers/scsi/a100u2w.c outb(data, host->base + ORC_GCFG); /*Disable EEPROM programming */ base 436 drivers/scsi/a100u2w.c outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ base 437 drivers/scsi/a100u2w.c outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ base 450 drivers/scsi/a100u2w.c outb(ORC_MAXQUEUE, host->base + ORC_SCBSIZE); /* Total number of SCBs */ base 452 drivers/scsi/a100u2w.c outl(host->scb_phys, host->base + ORC_SCBBASE0); base 454 drivers/scsi/a100u2w.c outl(host->scb_phys, host->base + ORC_SCBBASE1); base 506 drivers/scsi/a100u2w.c outb(0xFF, host->base + ORC_GIMSK); /* Disable all interrupts */ base 508 drivers/scsi/a100u2w.c if (inb(host->base + ORC_HSTUS) & RREADY) { /* Orchid is ready */ base 511 drivers/scsi/a100u2w.c outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */ base 516 drivers/scsi/a100u2w.c outb(0x00, host->base + ORC_HCTRL); /* clear HOSTSTOP */ base 524 drivers/scsi/a100u2w.c outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */ base 529 drivers/scsi/a100u2w.c outb(HDO, host->base + ORC_HCTRL); /* Do Hardware Reset & */ base 554 drivers/scsi/a100u2w.c outb(0xFB, host->base + ORC_GIMSK); /* enable RP FIFO interrupt */ base 573 drivers/scsi/a100u2w.c outb(SCSIRST, host->base + ORC_HCTRL); base 742 drivers/scsi/a100u2w.c outb(ORC_CMD_ABORT_SCB, host->base + ORC_HDATA); /* Write command */ base 743 drivers/scsi/a100u2w.c outb(HDO, host->base + ORC_HCTRL); base 747 drivers/scsi/a100u2w.c outb(scb->scbidx, host->base + ORC_HDATA); /* Write address */ base 748 drivers/scsi/a100u2w.c outb(HDO, host->base + ORC_HCTRL); base 754 drivers/scsi/a100u2w.c status = inb(host->base + ORC_HDATA); base 755 drivers/scsi/a100u2w.c outb(data, host->base + ORC_HSTUS); /* Clear HDI */ base 817 drivers/scsi/a100u2w.c if (inb(host->base + ORC_RQUEUECNT) == 0) base 822 drivers/scsi/a100u2w.c scb_index = inb(host->base + ORC_RQUEUE); base 829 drivers/scsi/a100u2w.c } while (inb(host->base + ORC_RQUEUECNT)); base 875 drivers/scsi/a100u2w.c sgent->base = cpu_to_le32((u32) sg_dma_address(sg)); base 881 drivers/scsi/a100u2w.c sgent->base = cpu_to_le32(0); base 1120 drivers/scsi/a100u2w.c host->base = port; base 1150 drivers/scsi/a100u2w.c shost->io_port = host->base; base 62 drivers/scsi/a100u2w.h u32 base; /* Data Pointer */ base 230 drivers/scsi/a100u2w.h unsigned long base; /* Base address */ base 60 drivers/scsi/a4000t.c hostdata->base = ZTWO_VADDR(scsi_addr); base 76 drivers/scsi/a4000t.c host->base = scsi_addr; base 988 drivers/scsi/aacraid/aacraid.h struct aac_entry *base; /*system virtual address */ base 1631 drivers/scsi/aacraid/aacraid.h volatile void __iomem *base, *dbg_base_mapped; base 57 drivers/scsi/aacraid/comminit.c unsigned char *base; base 87 drivers/scsi/aacraid/comminit.c base = dma_alloc_coherent(&dev->pdev->dev, size, &phys, GFP_KERNEL); base 88 drivers/scsi/aacraid/comminit.c if (base == NULL) { base 93 drivers/scsi/aacraid/comminit.c dev->comm_addr = (void *)base; base 100 drivers/scsi/aacraid/comminit.c dev->host_rrq = (u32 *)(base + fibsize); base 105 drivers/scsi/aacraid/comminit.c dev->init = (union aac_init *)(base + fibsize + host_rrq_size); base 155 drivers/scsi/aacraid/comminit.c dev->aif_base_va = (struct hw_fib *)base; base 226 drivers/scsi/aacraid/comminit.c base = base + fibsize + host_rrq_size + aac_init_size; base 233 drivers/scsi/aacraid/comminit.c align = (commalign - ((uintptr_t)(base) & (commalign - 1))); base 234 drivers/scsi/aacraid/comminit.c base = base + align; base 239 drivers/scsi/aacraid/comminit.c *commaddr = base; base 245 drivers/scsi/aacraid/comminit.c base = base + commsize; base 250 drivers/scsi/aacraid/comminit.c dev->printfbuf = (void *)base; base 255 drivers/scsi/aacraid/comminit.c memset(base, 0, printfbufsiz); base 398 drivers/scsi/aacraid/comminit.c comm->queue[HostNormCmdQueue].base = queues; base 404 drivers/scsi/aacraid/comminit.c comm->queue[HostHighCmdQueue].base = queues; base 411 drivers/scsi/aacraid/comminit.c comm->queue[AdapNormCmdQueue].base = queues; base 418 drivers/scsi/aacraid/comminit.c comm->queue[AdapHighCmdQueue].base = queues; base 425 drivers/scsi/aacraid/comminit.c comm->queue[HostNormRespQueue].base = queues; base 431 drivers/scsi/aacraid/comminit.c comm->queue[HostHighRespQueue].base = queues; base 438 drivers/scsi/aacraid/comminit.c comm->queue[AdapNormRespQueue].base = queues; base 445 drivers/scsi/aacraid/comminit.c comm->queue[AdapHighRespQueue].base = queues; base 398 drivers/scsi/aacraid/commsup.c *entry = q->base + *index; base 814 drivers/scsi/aacraid/commsup.c *entry = q->base + index; base 35 drivers/scsi/aacraid/nark.c iounmap(dev->base); base 36 drivers/scsi/aacraid/nark.c dev->base = NULL; base 43 drivers/scsi/aacraid/nark.c dev->base = NULL; base 46 drivers/scsi/aacraid/nark.c dev->base = ioremap(dev->base_start, size); base 47 drivers/scsi/aacraid/nark.c if (dev->base == NULL) { base 52 drivers/scsi/aacraid/nark.c dev->IndexRegs = &((struct rx_registers __iomem *)dev->base)->IndexRegs; base 69 drivers/scsi/aacraid/rkt.c dev->base = dev->regs.rkt = ioremap(dev->base_start, size); base 70 drivers/scsi/aacraid/rkt.c if (dev->base == NULL) base 433 drivers/scsi/aacraid/rx.c device = dev->base + Index; base 455 drivers/scsi/aacraid/rx.c dev->base = dev->regs.rx = ioremap(dev->base_start, size); base 456 drivers/scsi/aacraid/rx.c if (dev->base == NULL) base 647 drivers/scsi/aacraid/rx.c dev->dbg_base_mapped = dev->base; base 295 drivers/scsi/aacraid/sa.c dev->base = dev->regs.sa = ioremap(dev->base_start, size); base 296 drivers/scsi/aacraid/sa.c return (dev->base == NULL) ? -1 : 0; base 384 drivers/scsi/aacraid/sa.c dev->dbg_base_mapped = dev->base; base 614 drivers/scsi/aacraid/src.c dev->base = dev->regs.src.bar0 = NULL; base 619 drivers/scsi/aacraid/src.c dev->base = NULL; base 622 drivers/scsi/aacraid/src.c dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size); base 623 drivers/scsi/aacraid/src.c if (dev->base == NULL) { base 629 drivers/scsi/aacraid/src.c dev->base)->u.tupelo.IndexRegs; base 642 drivers/scsi/aacraid/src.c dev->base = dev->regs.src.bar0 = NULL; base 648 drivers/scsi/aacraid/src.c dev->base = NULL; base 651 drivers/scsi/aacraid/src.c dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size); base 652 drivers/scsi/aacraid/src.c if (dev->base == NULL) { base 658 drivers/scsi/aacraid/src.c dev->base)->u.denali.IndexRegs; base 762 drivers/scsi/aacraid/src.c val = readl(((char *)(dev->base) + IBW_SWR_OFFSET)); base 764 drivers/scsi/aacraid/src.c writel(val, ((char *)(dev->base) + IBW_SWR_OFFSET)); base 2419 drivers/scsi/advansys.c (ulong)s->base, (ulong)s->io_port, boardp->irq); base 11234 drivers/scsi/advansys.c shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base, base 11265 drivers/scsi/advansys.c shost->base = ((ulong)boardp->bios_codeseg << 4); base 11267 drivers/scsi/advansys.c shost->base = 0; base 73 drivers/scsi/aha1542.c static inline void aha1542_intr_reset(u16 base) base 75 drivers/scsi/aha1542.c outb(IRST, CONTROL(base)); base 100 drivers/scsi/aha1542.c static int aha1542_outb(unsigned int base, u8 val) base 102 drivers/scsi/aha1542.c if (!wait_mask(STATUS(base), CDF, 0, CDF, 0)) base 104 drivers/scsi/aha1542.c outb(val, DATA(base)); base 109 drivers/scsi/aha1542.c static int aha1542_out(unsigned int base, u8 *buf, int len) base 112 drivers/scsi/aha1542.c if (!wait_mask(STATUS(base), CDF, 0, CDF, 0)) base 114 drivers/scsi/aha1542.c outb(*buf++, DATA(base)); base 116 drivers/scsi/aha1542.c if (!wait_mask(INTRFLAGS(base), INTRMASK, HACC, 0, 0)) base 125 drivers/scsi/aha1542.c static int aha1542_in(unsigned int base, u8 *buf, int len, int timeout) base 128 drivers/scsi/aha1542.c if (!wait_mask(STATUS(base), DF, DF, 0, timeout)) base 130 drivers/scsi/aha1542.c *buf++ = inb(DATA(base)); base 9 drivers/scsi/aha1542.h #define STATUS(base) base base 20 drivers/scsi/aha1542.h #define INTRFLAGS(base) (STATUS(base)+2) base 29 drivers/scsi/aha1542.h #define CONTROL(base) STATUS(base) base 36 drivers/scsi/aha1542.h #define DATA(base) (STATUS(base)+1) base 197 drivers/scsi/aha1740.c static int aha1740_test_port(unsigned int base) base 199 drivers/scsi/aha1740.c if ( inb(PORTADR(base)) & PORTADDR_ENH ) base 215 drivers/scsi/aha1740.c unsigned int base; base 224 drivers/scsi/aha1740.c base = host->io_port; base 228 drivers/scsi/aha1740.c while(inb(G2STAT(base)) & G2STAT_INTPEND) { base 231 drivers/scsi/aha1740.c adapstat = inb(G2INTST(base)); base 232 drivers/scsi/aha1740.c ecbptr = ecb_dma_to_cpu (host, inl(MBOXIN0(base))); base 233 drivers/scsi/aha1740.c outb(G2CNTRL_IRST,G2CNTRL(base)); /* interrupt reset */ base 240 drivers/scsi/aha1740.c outb(G2CNTRL_HRDY,G2CNTRL(base)); base 243 drivers/scsi/aha1740.c inb(G2STAT(base)),adapstat, base 244 drivers/scsi/aha1740.c inb(G2INTST(base)), number_serviced++); base 250 drivers/scsi/aha1740.c inb(G2STAT(base)),adapstat, base 251 drivers/scsi/aha1740.c inb(G2INTST(base)), number_serviced++); base 291 drivers/scsi/aha1740.c inb(MBOXIN0(base)), base 292 drivers/scsi/aha1740.c inb(MBOXIN1(base)), base 293 drivers/scsi/aha1740.c inb(MBOXIN2(base)), base 294 drivers/scsi/aha1740.c inb(MBOXIN3(base))); /* Say What? */ base 296 drivers/scsi/aha1740.c outb(G2CNTRL_HRDY,G2CNTRL(base)); base 457 drivers/scsi/aha1740.c unsigned int base = SCpnt->device->host->io_port; base 462 drivers/scsi/aha1740.c if (inb(G2STAT(base)) & G2STAT_MBXOUT) break; base 470 drivers/scsi/aha1740.c MBOXOUT0(base)); base 472 drivers/scsi/aha1740.c if (! (inb(G2STAT(base)) & G2STAT_BUSY)) break; base 479 drivers/scsi/aha1740.c outb(ATTN_START | (target & 7), ATTN(base)); /* Start it up */ base 492 drivers/scsi/aha1740.c static void aha1740_getconfig(unsigned int base, unsigned int *irq_level, base 498 drivers/scsi/aha1740.c *irq_level = intab[inb(INTDEF(base)) & 0x7]; base 499 drivers/scsi/aha1740.c *irq_type = (inb(INTDEF(base)) & 0x8) >> 3; base 500 drivers/scsi/aha1740.c *translation = inb(RESV1(base)) & 0x1; base 501 drivers/scsi/aha1740.c outb(inb(INTDEF(base)) | 0x10, INTDEF(base)); base 582 drivers/scsi/aha1740.c shpnt->base = 0; base 19 drivers/scsi/aha1740.h #define HID0(base) (base + 0x0) base 20 drivers/scsi/aha1740.h #define HID1(base) (base + 0x1) base 21 drivers/scsi/aha1740.h #define HID2(base) (base + 0x2) base 22 drivers/scsi/aha1740.h #define HID3(base) (base + 0x3) base 23 drivers/scsi/aha1740.h #define EBCNTRL(base) (base + 0x4) base 24 drivers/scsi/aha1740.h #define PORTADR(base) (base + 0x40) base 25 drivers/scsi/aha1740.h #define BIOSADR(base) (base + 0x41) base 26 drivers/scsi/aha1740.h #define INTDEF(base) (base + 0x42) base 27 drivers/scsi/aha1740.h #define SCSIDEF(base) (base + 0x43) base 28 drivers/scsi/aha1740.h #define BUSDEF(base) (base + 0x44) base 29 drivers/scsi/aha1740.h #define RESV0(base) (base + 0x45) base 30 drivers/scsi/aha1740.h #define RESV1(base) (base + 0x46) base 31 drivers/scsi/aha1740.h #define RESV2(base) (base + 0x47) base 39 drivers/scsi/aha1740.h #define G2INTST(base) (base + 0x56) base 40 drivers/scsi/aha1740.h #define G2STAT(base) (base + 0x57) base 41 drivers/scsi/aha1740.h #define MBOXIN0(base) (base + 0x58) base 42 drivers/scsi/aha1740.h #define MBOXIN1(base) (base + 0x59) base 43 drivers/scsi/aha1740.h #define MBOXIN2(base) (base + 0x5a) base 44 drivers/scsi/aha1740.h #define MBOXIN3(base) (base + 0x5b) base 45 drivers/scsi/aha1740.h #define G2STAT2(base) (base + 0x5c) base 63 drivers/scsi/aha1740.h #define MBOXOUT0(base) (base + 0x50) base 64 drivers/scsi/aha1740.h #define MBOXOUT1(base) (base + 0x51) base 65 drivers/scsi/aha1740.h #define MBOXOUT2(base) (base + 0x52) base 66 drivers/scsi/aha1740.h #define MBOXOUT3(base) (base + 0x53) base 67 drivers/scsi/aha1740.h #define ATTN(base) (base + 0x54) base 68 drivers/scsi/aha1740.h #define G2CNTRL(base) (base + 0x55) base 251 drivers/scsi/aic7xxx/aic79xx_osm_pci.c ahd_linux_pci_reserve_io_regions(struct ahd_softc *ahd, resource_size_t *base, base 254 drivers/scsi/aic7xxx/aic79xx_osm_pci.c *base = pci_resource_start(ahd->dev_softc, 0); base 261 drivers/scsi/aic7xxx/aic79xx_osm_pci.c if (*base == 0 || *base2 == 0) base 263 drivers/scsi/aic7xxx/aic79xx_osm_pci.c if (!request_region(*base, 256, "aic79xx")) base 266 drivers/scsi/aic7xxx/aic79xx_osm_pci.c release_region(*base, 256); base 312 drivers/scsi/aic7xxx/aic79xx_osm_pci.c resource_size_t base; base 321 drivers/scsi/aic7xxx/aic79xx_osm_pci.c base = 0; base 323 drivers/scsi/aic7xxx/aic79xx_osm_pci.c error = ahd_linux_pci_reserve_mem_region(ahd, &base, &maddr); base 325 drivers/scsi/aic7xxx/aic79xx_osm_pci.c ahd->platform_data->mem_busaddr = base; base 353 drivers/scsi/aic7xxx/aic79xx_osm_pci.c (unsigned long long)base); base 359 drivers/scsi/aic7xxx/aic79xx_osm_pci.c error = ahd_linux_pci_reserve_io_regions(ahd, &base, &base2); base 363 drivers/scsi/aic7xxx/aic79xx_osm_pci.c ahd->bshs[0].ioport = (u_long)base; base 372 drivers/scsi/aic7xxx/aic79xx_osm_pci.c (unsigned long long)base, base 347 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, resource_size_t *base) base 352 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c *base = pci_resource_start(ahc->dev_softc, 0); base 353 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c if (*base == 0) base 355 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c if (!request_region(*base, 256, "aic7xxx")) base 390 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c resource_size_t base; base 399 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c base = 0; base 401 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c error = ahc_linux_pci_reserve_mem_region(ahc, &base, &maddr); base 403 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c ahc->platform_data->mem_busaddr = base; base 433 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c (unsigned long long)base); base 441 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c error = ahc_linux_pci_reserve_io_region(ahc, &base); base 444 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c ahc->bsh.ioport = (u_long)base; base 452 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c (unsigned long long)base); base 172 drivers/scsi/aic94xx/aic94xx_reg.c u32 base = reg & ~(MBAR0_SWB_SIZE-1); base 173 drivers/scsi/aic94xx/aic94xx_reg.c pci_write_config_dword(asd_ha->pcidev, PCI_CONF_MBAR0_SWB, base); base 174 drivers/scsi/aic94xx/aic94xx_reg.c asd_ha->io_handle[0].swb_base = base; base 129 drivers/scsi/aic94xx/aic94xx_reg.h u16 base = offs & ~1; base 130 drivers/scsi/aic94xx/aic94xx_reg.h u16 rval = asd_ddbsite_read_word(asd_ha, ddb_site_no, base); base 135 drivers/scsi/aic94xx/aic94xx_reg.h asd_ddbsite_write_word(asd_ha, ddb_site_no, base, rval); base 182 drivers/scsi/aic94xx/aic94xx_reg.h u16 base = offs & ~1; base 183 drivers/scsi/aic94xx/aic94xx_reg.h u16 rval = asd_scbsite_read_word(asd_ha, scb_site_no, base); base 188 drivers/scsi/aic94xx/aic94xx_reg.h asd_scbsite_write_word(asd_ha, scb_site_no, base, rval); base 231 drivers/scsi/aic94xx/aic94xx_reg.h u16 base = offs & ~1; base 233 drivers/scsi/aic94xx/aic94xx_reg.h u16 nval = asd_ddbsite_read_word(asd_ha, ddb_site_no, base); base 245 drivers/scsi/aic94xx/aic94xx_reg.h return asd_ddbsite_update_word(asd_ha, ddb_site_no, base, oval, nval); base 246 drivers/scsi/am53c974.c u32 base, end; base 261 drivers/scsi/am53c974.c base = dma_addr & ((1U << 24) - 1U); base 262 drivers/scsi/am53c974.c end = base + dma_len; base 265 drivers/scsi/am53c974.c dma_len = end - base; base 197 drivers/scsi/arm/acornscsi.c writeb(reg, host->base + SBIC_REGIDX); base 198 drivers/scsi/arm/acornscsi.c writeb(value, host->base + SBIC_REGVAL); base 204 drivers/scsi/arm/acornscsi.c return readl(host->base + SBIC_REGIDX) & 255; base 205 drivers/scsi/arm/acornscsi.c writeb(reg, host->base + SBIC_REGIDX); base 206 drivers/scsi/arm/acornscsi.c return readl(host->base + SBIC_REGVAL) & 255; base 209 drivers/scsi/arm/acornscsi.c #define sbic_arm_writenext(host, val) writeb((val), (host)->base + SBIC_REGVAL) base 210 drivers/scsi/arm/acornscsi.c #define sbic_arm_readnext(host) readb((host)->base + SBIC_REGVAL) base 214 drivers/scsi/arm/acornscsi.c readb((host)->base + DMAC_OFFSET + ((reg) << 2)) base 217 drivers/scsi/arm/acornscsi.c ({ writeb((value), (host)->base + DMAC_OFFSET + ((reg) << 2)); }) base 922 drivers/scsi/arm/acornscsi.c __acornscsi_in(host->base + (offset << 1), ptr, this_len); base 967 drivers/scsi/arm/acornscsi.c __acornscsi_out(host->base + (offset << 1), ptr, this_len); base 2813 drivers/scsi/arm/acornscsi.c host->base + SBIC_REGIDX, host->scsi.irq); base 2816 drivers/scsi/arm/acornscsi.c host->base + DMAC_OFFSET, host->scsi.irq); base 2912 drivers/scsi/arm/acornscsi.c ashost->base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); base 2914 drivers/scsi/arm/acornscsi.c if (!ashost->base || !ashost->fast) base 2952 drivers/scsi/arm/acornscsi.c ecardm_iounmap(ec, ashost->base); base 2979 drivers/scsi/arm/acornscsi.c ecardm_iounmap(ec, ashost->base); base 278 drivers/scsi/arm/acornscsi.h void __iomem *base; /* memc base address */ base 45 drivers/scsi/arm/arxescsi.c void __iomem *base; base 76 drivers/scsi/arm/arxescsi.c static void arxescsi_pseudo_dma_write(unsigned char *addr, void __iomem *base) base 101 drivers/scsi/arm/arxescsi.c : "r" (addr), "r" (base)); base 118 drivers/scsi/arm/arxescsi.c void __iomem *base = info->info.scsi.io_base; base 127 drivers/scsi/arm/arxescsi.c if (readb(base + 0x80) & STAT_INT) { base 131 drivers/scsi/arm/arxescsi.c arxescsi_pseudo_dma_write(addr, base); base 138 drivers/scsi/arm/arxescsi.c if (readb(base + 0x80) & STAT_INT) base 141 drivers/scsi/arm/arxescsi.c if (!(readb(base + DMASTAT_OFFSET) & DMASTAT_DRQ)) base 146 drivers/scsi/arm/arxescsi.c writew(word, base + DMADATA_OFFSET); base 159 drivers/scsi/arm/arxescsi.c if (readb(base + 0x80) & STAT_INT) { base 164 drivers/scsi/arm/arxescsi.c if (!(readb(base + DMASTAT_OFFSET) & DMASTAT_DRQ)) base 167 drivers/scsi/arm/arxescsi.c readsw(base + DMADATA_OFFSET, addr, 256 >> 1); base 177 drivers/scsi/arm/arxescsi.c if (readb(base + 0x80) & STAT_INT) base 180 drivers/scsi/arm/arxescsi.c if (!(readb(base + DMASTAT_OFFSET) & DMASTAT_DRQ)) base 183 drivers/scsi/arm/arxescsi.c word = readw(base + DMADATA_OFFSET); base 257 drivers/scsi/arm/arxescsi.c void __iomem *base; base 264 drivers/scsi/arm/arxescsi.c base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); base 265 drivers/scsi/arm/arxescsi.c if (!base) { base 278 drivers/scsi/arm/arxescsi.c info->base = base; base 280 drivers/scsi/arm/arxescsi.c info->info.scsi.io_base = base + 0x2000; base 296 drivers/scsi/arm/arxescsi.c ec->irqaddr = base; base 48 drivers/scsi/arm/cumana_1.c u8 __iomem *base = hostdata->io; base 53 drivers/scsi/arm/cumana_1.c writeb(0x02, base + CTRL); base 59 drivers/scsi/arm/cumana_1.c status = readb(base + STAT); base 78 drivers/scsi/arm/cumana_1.c writeb(0x12, base + CTRL); base 83 drivers/scsi/arm/cumana_1.c status = readb(base + STAT); base 93 drivers/scsi/arm/cumana_1.c status = readb(base + STAT); base 104 drivers/scsi/arm/cumana_1.c writeb(hostdata->ctrl | 0x40, base + CTRL); base 115 drivers/scsi/arm/cumana_1.c u8 __iomem *base = hostdata->io; base 120 drivers/scsi/arm/cumana_1.c writeb(0x00, base + CTRL); base 125 drivers/scsi/arm/cumana_1.c status = readb(base + STAT); base 144 drivers/scsi/arm/cumana_1.c writeb(0x10, base + CTRL); base 149 drivers/scsi/arm/cumana_1.c status = readb(base + STAT); base 159 drivers/scsi/arm/cumana_1.c status = readb(base + STAT); base 170 drivers/scsi/arm/cumana_1.c writeb(hostdata->ctrl | 0x40, base + CTRL); base 186 drivers/scsi/arm/cumana_1.c u8 __iomem *base = hostdata->io; base 189 drivers/scsi/arm/cumana_1.c writeb(0, base + CTRL); base 191 drivers/scsi/arm/cumana_1.c val = readb(base + 0x2100 + (reg << 2)); base 194 drivers/scsi/arm/cumana_1.c writeb(0x40, base + CTRL); base 202 drivers/scsi/arm/cumana_1.c u8 __iomem *base = hostdata->io; base 204 drivers/scsi/arm/cumana_1.c writeb(0, base + CTRL); base 206 drivers/scsi/arm/cumana_1.c writeb(value, base + 0x2100 + (reg << 2)); base 209 drivers/scsi/arm/cumana_1.c writeb(0x40, base + CTRL); base 299 drivers/scsi/arm/cumana_1.c void __iomem *base = priv(host)->io; base 308 drivers/scsi/arm/cumana_1.c iounmap(base); base 76 drivers/scsi/arm/cumana_2.c void __iomem *base; base 93 drivers/scsi/arm/cumana_2.c writeb(ALATCH_ENA_INT, info->base + CUMANASCSI2_ALATCH); base 105 drivers/scsi/arm/cumana_2.c writeb(ALATCH_DIS_INT, info->base + CUMANASCSI2_ALATCH); base 125 drivers/scsi/arm/cumana_2.c writeb(ALATCH_ENA_TERM, info->base + CUMANASCSI2_ALATCH); base 128 drivers/scsi/arm/cumana_2.c writeb(ALATCH_DIS_TERM, info->base + CUMANASCSI2_ALATCH); base 161 drivers/scsi/arm/cumana_2.c writeb(ALATCH_DIS_DMA, info->base + CUMANASCSI2_ALATCH); base 182 drivers/scsi/arm/cumana_2.c writeb(alatch_dir, info->base + CUMANASCSI2_ALATCH); base 185 drivers/scsi/arm/cumana_2.c writeb(ALATCH_ENA_DMA, info->base + CUMANASCSI2_ALATCH); base 186 drivers/scsi/arm/cumana_2.c writeb(ALATCH_DIS_BIT32, info->base + CUMANASCSI2_ALATCH); base 220 drivers/scsi/arm/cumana_2.c unsigned int status = readb(info->base + CUMANASCSI2_STATUS); base 229 drivers/scsi/arm/cumana_2.c writew(word, info->base + CUMANASCSI2_PSEUDODMA); base 239 drivers/scsi/arm/cumana_2.c unsigned int status = readb(info->base + CUMANASCSI2_STATUS); base 247 drivers/scsi/arm/cumana_2.c readsw(info->base + CUMANASCSI2_PSEUDODMA, base 256 drivers/scsi/arm/cumana_2.c unsigned int status = readb(info->base + CUMANASCSI2_STATUS); base 264 drivers/scsi/arm/cumana_2.c word = readw(info->base + CUMANASCSI2_PSEUDODMA); base 284 drivers/scsi/arm/cumana_2.c writeb(ALATCH_DIS_DMA, info->base + CUMANASCSI2_ALATCH); base 375 drivers/scsi/arm/cumana_2.c void __iomem *base; base 382 drivers/scsi/arm/cumana_2.c base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); base 383 drivers/scsi/arm/cumana_2.c if (!base) { base 399 drivers/scsi/arm/cumana_2.c info->base = base; base 403 drivers/scsi/arm/cumana_2.c info->info.scsi.io_base = base + CUMANASCSI2_FAS216_OFFSET; base 419 drivers/scsi/arm/cumana_2.c ec->irqaddr = info->base + CUMANASCSI2_STATUS; base 71 drivers/scsi/arm/eesox.c void __iomem *base; base 191 drivers/scsi/arm/eesox.c static void eesoxscsi_buffer_in(void *buf, int length, void __iomem *base) base 193 drivers/scsi/arm/eesox.c const void __iomem *reg_fas = base + EESOX_FAS216_OFFSET; base 194 drivers/scsi/arm/eesox.c const void __iomem *reg_dmastat = base + EESOX_DMASTAT; base 195 drivers/scsi/arm/eesox.c const void __iomem *reg_dmadata = base + EESOX_DMADATA; base 269 drivers/scsi/arm/eesox.c static void eesoxscsi_buffer_out(void *buf, int length, void __iomem *base) base 271 drivers/scsi/arm/eesox.c const void __iomem *reg_fas = base + EESOX_FAS216_OFFSET; base 272 drivers/scsi/arm/eesox.c const void __iomem *reg_dmastat = base + EESOX_DMASTAT; base 273 drivers/scsi/arm/eesox.c void __iomem *reg_dmadata = base + EESOX_DMADATA; base 355 drivers/scsi/arm/eesox.c eesoxscsi_buffer_in(SCp->ptr, SCp->this_residual, info->base); base 357 drivers/scsi/arm/eesox.c eesoxscsi_buffer_out(SCp->ptr, SCp->this_residual, info->base); base 493 drivers/scsi/arm/eesox.c void __iomem *base; base 500 drivers/scsi/arm/eesox.c base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); base 501 drivers/scsi/arm/eesox.c if (!base) { base 517 drivers/scsi/arm/eesox.c info->base = base; base 518 drivers/scsi/arm/eesox.c info->ctl_port = base + EESOX_CONTROL; base 522 drivers/scsi/arm/eesox.c info->info.scsi.io_base = base + EESOX_FAS216_OFFSET; base 538 drivers/scsi/arm/eesox.c ec->irqaddr = base + EESOX_DMASTAT; base 44 drivers/scsi/arm/oak.c u8 __iomem *base = hostdata->io; base 51 drivers/scsi/arm/oak.c while (((status = readw(base + STAT)) & 0x100)==0); base 59 drivers/scsi/arm/oak.c u8 __iomem *base = hostdata->io; base 69 drivers/scsi/arm/oak.c while (((status = readw(base + STAT)) & 0x100)==0) base 81 drivers/scsi/arm/oak.c readsw(base + DATA, addr, 128); base 87 drivers/scsi/arm/oak.c b = (unsigned long) readw(base + DATA); base 172 drivers/scsi/arm/oak.c void __iomem *base = priv(host)->io; base 179 drivers/scsi/arm/oak.c iounmap(base); base 59 drivers/scsi/arm/powertec.c void __iomem *base; base 73 drivers/scsi/arm/powertec.c writeb(POWERTEC_INTR_ENABLE, info->base + POWERTEC_INTR_CONTROL); base 85 drivers/scsi/arm/powertec.c writeb(POWERTEC_INTR_DISABLE, info->base + POWERTEC_INTR_CONTROL); base 104 drivers/scsi/arm/powertec.c writeb(info->term_ctl, info->base + POWERTEC_TERM_CONTROL); base 302 drivers/scsi/arm/powertec.c void __iomem *base; base 309 drivers/scsi/arm/powertec.c base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); base 310 drivers/scsi/arm/powertec.c if (!base) { base 325 drivers/scsi/arm/powertec.c info->base = base; base 329 drivers/scsi/arm/powertec.c info->info.scsi.io_base = base + POWERTEC_FAS216_OFFSET; base 345 drivers/scsi/arm/powertec.c ec->irqaddr = base + POWERTEC_INTR_STATUS; base 55 drivers/scsi/bvme6000_scsi.c hostdata->base = (void __iomem *)BVME_NCR53C710_BASE; base 70 drivers/scsi/bvme6000_scsi.c host->base = BVME_NCR53C710_BASE; base 216 drivers/scsi/csiostor/csio_hw.c uint32_t base = hw->params.pci.vpd_cap_addr; base 221 drivers/scsi/csiostor/csio_hw.c pci_write_config_word(hw->pdev, base + PCI_VPD_ADDR, (uint16_t)addr); base 225 drivers/scsi/csiostor/csio_hw.c pci_read_config_word(hw->pdev, base + PCI_VPD_ADDR, &val); base 233 drivers/scsi/csiostor/csio_hw.c pci_read_config_dword(hw->pdev, base + PCI_VPD_DATA, data); base 75 drivers/scsi/cxgbi/libcxgbi.c int cxgbi_device_portmap_create(struct cxgbi_device *cdev, unsigned int base, base 89 drivers/scsi/cxgbi/libcxgbi.c pmap->sport_base = base; base 577 drivers/scsi/cxgbi/libcxgbi.h int cxgbi_device_portmap_create(struct cxgbi_device *cdev, unsigned int base, base 732 drivers/scsi/cxlflash/ocxl_hw.c u16 base, enabled, supported; base 751 drivers/scsi/cxlflash/ocxl_hw.c rc = ocxl_config_get_actag_info(pdev, &base, &enabled, &supported); base 758 drivers/scsi/cxlflash/ocxl_hw.c afu->fn_actag_base = base; base 761 drivers/scsi/cxlflash/ocxl_hw.c ocxl_config_set_actag(pdev, fcfg->dvsec_function_pos, base, enabled); base 763 drivers/scsi/cxlflash/ocxl_hw.c __func__, base, enabled); base 860 drivers/scsi/cxlflash/ocxl_hw.c int base; base 877 drivers/scsi/cxlflash/ocxl_hw.c base = afu->fn_actag_base; base 881 drivers/scsi/cxlflash/ocxl_hw.c ocxl_config_set_afu_actag(pdev, pos, base, count); base 882 drivers/scsi/cxlflash/ocxl_hw.c dev_dbg(dev, "%s: acTag base=%d enabled=%d\n", __func__, base, count); base 883 drivers/scsi/cxlflash/ocxl_hw.c afu->afu_actag_base = base; base 2173 drivers/scsi/dc395x.c unsigned char *virt, *base = NULL; base 2181 drivers/scsi/dc395x.c base = scsi_kmap_atomic_sg(scsi_sglist(srb->cmd), base 2183 drivers/scsi/dc395x.c virt = base + offset; base 2224 drivers/scsi/dc395x.c scsi_kunmap_atomic_sg(base); base 2391 drivers/scsi/dc395x.c unsigned char *virt, *base = NULL; base 2398 drivers/scsi/dc395x.c base = scsi_kmap_atomic_sg(scsi_sglist(srb->cmd), base 2400 drivers/scsi/dc395x.c virt = base + offset; base 2413 drivers/scsi/dc395x.c scsi_kunmap_atomic_sg(base); base 3357 drivers/scsi/dc395x.c unsigned char *base = NULL; base 3364 drivers/scsi/dc395x.c base = scsi_kmap_atomic_sg(sg, scsi_sg_count(cmd), &offset, &len); base 3365 drivers/scsi/dc395x.c ptr = (struct ScsiInqData *)(base + offset); base 3382 drivers/scsi/dc395x.c scsi_kunmap_atomic_sg(base); base 25 drivers/scsi/dmx3191d.c #define NCR5380_read(reg) inb(hostdata->base + (reg)) base 26 drivers/scsi/dmx3191d.c #define NCR5380_write(reg, value) outb(value, hostdata->base + (reg)) base 82 drivers/scsi/dmx3191d.c hostdata->base = io; base 120 drivers/scsi/dmx3191d.c unsigned long io = hostdata->base; base 85 drivers/scsi/dpt/dpti_ioctl.h int base; /* Base I/O address */ base 1262 drivers/scsi/esas2r/esas2r_main.c u32 base = addr_lo & -(signed int)MW_DATA_WINDOW_SIZE; base 1264 drivers/scsi/esas2r/esas2r_main.c if (a->window_base != base) { base 1266 drivers/scsi/esas2r/esas2r_main.c base | MVRPW1R_ENABLE); base 1268 drivers/scsi/esas2r/esas2r_main.c a->window_base = base; base 526 drivers/scsi/esp_scsi.c u32 base, end; base 540 drivers/scsi/esp_scsi.c base = dma_addr & ((1U << 24) - 1U); base 541 drivers/scsi/esp_scsi.c end = base + dma_len; base 544 drivers/scsi/esp_scsi.c dma_len = end - base; base 152 drivers/scsi/fcoe/fcoe_transport.c lport->link_speed = eth2fc_speed(ecmd.base.speed); base 112 drivers/scsi/fdomain.c int base; base 120 drivers/scsi/fdomain.c outb(0, fd->base + REG_BCTL); base 121 drivers/scsi/fdomain.c outb(0, fd->base + REG_MCTL); base 125 drivers/scsi/fdomain.c fd->base + REG_ACTL); base 127 drivers/scsi/fdomain.c outb(ACTL_RESET | PARITY_MASK, fd->base + REG_ACTL); base 154 drivers/scsi/fdomain.c static int fdomain_test_loopback(int base) base 159 drivers/scsi/fdomain.c outb(i, base + REG_LOOPBACK); base 160 drivers/scsi/fdomain.c if (inb(base + REG_LOOPBACK) != i) base 167 drivers/scsi/fdomain.c static void fdomain_reset(int base) base 169 drivers/scsi/fdomain.c outb(BCTL_RST, base + REG_BCTL); base 171 drivers/scsi/fdomain.c outb(0, base + REG_BCTL); base 173 drivers/scsi/fdomain.c outb(0, base + REG_MCTL); base 174 drivers/scsi/fdomain.c outb(PARITY_MASK, base + REG_ACTL); base 183 drivers/scsi/fdomain.c outb(BCTL_BUSEN | BCTL_SEL, fd->base + REG_BCTL); base 184 drivers/scsi/fdomain.c outb(BIT(sh->this_id) | BIT(target), fd->base + REG_SCSI_DATA_NOACK); base 187 drivers/scsi/fdomain.c outb(PARITY_MASK, fd->base + REG_ACTL); base 192 drivers/scsi/fdomain.c status = inb(fd->base + REG_BSTAT); base 196 drivers/scsi/fdomain.c outb(BCTL_BUSEN, fd->base + REG_BCTL); base 207 drivers/scsi/fdomain.c outb(0, fd->base + REG_ICTL); base 220 drivers/scsi/fdomain.c while ((len = inw(fd->base + REG_FIFO_COUNT)) > 0) { base 226 drivers/scsi/fdomain.c *ptr++ = inb(fd->base + REG_FIFO); base 228 drivers/scsi/fdomain.c insw(fd->base + REG_FIFO, ptr, len >> 1); base 242 drivers/scsi/fdomain.c while ((len = FIFO_Size - inw(fd->base + REG_FIFO_COUNT)) > 512) { base 253 drivers/scsi/fdomain.c outb(*ptr++, fd->base + REG_FIFO); base 255 drivers/scsi/fdomain.c outsw(fd->base + REG_FIFO, ptr, len >> 1); base 274 drivers/scsi/fdomain.c status = inb(fd->base + REG_ASTAT); base 281 drivers/scsi/fdomain.c outb(ICTL_SEL | FIFO_COUNT, fd->base + REG_ICTL); base 282 drivers/scsi/fdomain.c outb(BCTL_BUSEN | BCTL_SEL, fd->base + REG_BCTL); base 284 drivers/scsi/fdomain.c fd->base + REG_SCSI_DATA_NOACK); base 286 drivers/scsi/fdomain.c outb(ACTL_IRQEN | PARITY_MASK, fd->base + REG_ACTL); base 289 drivers/scsi/fdomain.c status = inb(fd->base + REG_BSTAT); base 297 drivers/scsi/fdomain.c outb(ACTL_IRQEN | PARITY_MASK, fd->base + REG_ACTL); base 300 drivers/scsi/fdomain.c outb(ICTL_FIFO | ICTL_REQ | FIFO_COUNT, fd->base + REG_ICTL); base 301 drivers/scsi/fdomain.c outb(BCTL_BUSEN, fd->base + REG_BCTL); base 306 drivers/scsi/fdomain.c status = inb(fd->base + REG_BSTAT); base 312 drivers/scsi/fdomain.c fd->base + REG_SCSI_DATA); base 318 drivers/scsi/fdomain.c PARITY_MASK, fd->base + REG_ACTL); base 325 drivers/scsi/fdomain.c fd->base + REG_ACTL); base 329 drivers/scsi/fdomain.c cmd->SCp.Status = inb(fd->base + REG_SCSI_DATA); base 332 drivers/scsi/fdomain.c outb(MESSAGE_REJECT, fd->base + REG_SCSI_DATA); base 335 drivers/scsi/fdomain.c cmd->SCp.Message = inb(fd->base + REG_SCSI_DATA); base 347 drivers/scsi/fdomain.c PARITY_MASK, fd->base + REG_ACTL); base 351 drivers/scsi/fdomain.c fd->base + REG_ACTL); base 368 drivers/scsi/fdomain.c fd->base + REG_ICTL); base 369 drivers/scsi/fdomain.c outb(0, fd->base + REG_BCTL); base 372 drivers/scsi/fdomain.c fd->base + REG_ICTL); base 383 drivers/scsi/fdomain.c if ((inb(fd->base + REG_ASTAT) & ASTAT_IRQ) == 0) base 386 drivers/scsi/fdomain.c outb(0, fd->base + REG_ICTL); base 416 drivers/scsi/fdomain.c outb(0, fd->base + REG_ICTL); base 417 drivers/scsi/fdomain.c outb(0, fd->base + REG_BCTL); /* Disable data drivers */ base 419 drivers/scsi/fdomain.c outb(BIT(cmd->device->host->this_id), fd->base + REG_SCSI_DATA_NOACK); base 420 drivers/scsi/fdomain.c outb(ICTL_ARB, fd->base + REG_ICTL); base 422 drivers/scsi/fdomain.c outb(ACTL_ARB | ACTL_IRQEN | PARITY_MASK, fd->base + REG_ACTL); base 457 drivers/scsi/fdomain.c fdomain_reset(fd->base); base 504 drivers/scsi/fdomain.c struct Scsi_Host *fdomain_create(int base, int irq, int this_id, base 515 drivers/scsi/fdomain.c chip = fdomain_identify(base); base 519 drivers/scsi/fdomain.c fdomain_reset(base); base 521 drivers/scsi/fdomain.c if (fdomain_test_loopback(base)) base 537 drivers/scsi/fdomain.c sh->io_port = base; base 541 drivers/scsi/fdomain.c fd->base = base; base 553 drivers/scsi/fdomain.c base, irq, sh->this_id); base 588 drivers/scsi/fdomain.c fdomain_reset(fd->base); base 112 drivers/scsi/fdomain.h struct Scsi_Host *fdomain_create(int base, int irq, int this_id, base 89 drivers/scsi/fdomain_isa.c int i, base = 0, irq = 0; base 111 drivers/scsi/fdomain_isa.c base = readb(p + sig->base_offset) + base 114 drivers/scsi/fdomain_isa.c if (base) base 116 drivers/scsi/fdomain_isa.c bios_base, base); base 119 drivers/scsi/fdomain_isa.c if (!base) { /* no I/O base in BIOS area */ base 125 drivers/scsi/fdomain_isa.c base = ports[ndev - ADDRESS_COUNT]; base 131 drivers/scsi/fdomain_isa.c if (!request_region(base, FDOMAIN_REGION_SIZE, "fdomain_isa")) base 134 drivers/scsi/fdomain_isa.c irq = irqs[(inb(base + REG_CFG1) & CFG1_IRQ_MASK) >> 1]; base 139 drivers/scsi/fdomain_isa.c sh = fdomain_create(base, irq, this_id, dev); base 141 drivers/scsi/fdomain_isa.c release_region(base, FDOMAIN_REGION_SIZE); base 182 drivers/scsi/fdomain_isa.c int base = sh->io_port; base 185 drivers/scsi/fdomain_isa.c release_region(base, FDOMAIN_REGION_SIZE); base 104 drivers/scsi/g_NCR5380.c static int base[] = { 0, 0, 0, 0, 0, 0, 0, 0 }; base 105 drivers/scsi/g_NCR5380.c module_param_hw_array(base, int, ioport, NULL, 0); base 106 drivers/scsi/g_NCR5380.c MODULE_PARM_DESC(base, "base address(es)"); base 223 drivers/scsi/g_NCR5380.c struct device *pdev, int base, int irq, int board) base 225 drivers/scsi/g_NCR5380.c bool is_pmio = base <= 0xffff; base 262 drivers/scsi/g_NCR5380.c if (base) base 264 drivers/scsi/g_NCR5380.c if (base == ports[i]) { /* index found */ base 284 drivers/scsi/g_NCR5380.c base = ports[i]; base 285 drivers/scsi/g_NCR5380.c outb(0xc0, base + 9); base 286 drivers/scsi/g_NCR5380.c if (inb(base + 9) != 0x80) { base 296 drivers/scsi/g_NCR5380.c if (!base || !request_region(base, region_size, "ncr5380")) base 300 drivers/scsi/g_NCR5380.c if (!request_mem_region(base, region_size, "ncr5380")) base 305 drivers/scsi/g_NCR5380.c iomem = ioport_map(base, region_size); base 307 drivers/scsi/g_NCR5380.c iomem = ioremap(base, region_size); base 326 drivers/scsi/g_NCR5380.c hostdata->io_port = base; base 352 drivers/scsi/g_NCR5380.c hostdata->base = base; base 460 drivers/scsi/g_NCR5380.c release_region(base, region_size); base 462 drivers/scsi/g_NCR5380.c release_mem_region(base, region_size); base 471 drivers/scsi/g_NCR5380.c unsigned long base = hostdata->base; base 483 drivers/scsi/g_NCR5380.c release_mem_region(base, region_size); base 711 drivers/scsi/g_NCR5380.c int ret = generic_NCR5380_init_one(&driver_template, pdev, base[ndev], base 714 drivers/scsi/g_NCR5380.c if (base[ndev]) base 716 drivers/scsi/g_NCR5380.c base[ndev]); base 749 drivers/scsi/g_NCR5380.c int base, irq; base 754 drivers/scsi/g_NCR5380.c base = pnp_port_start(pdev, 0); base 757 drivers/scsi/g_NCR5380.c return generic_NCR5380_init_one(&driver_template, &pdev->dev, base, irq, base 782 drivers/scsi/g_NCR5380.c if (irq[0] == -1 && base[0] == 0 && card[0] == -1) { base 784 drivers/scsi/g_NCR5380.c base[0] = ncr_addr; base 6875 drivers/scsi/hpsa.c static void __iomem *remap_pci_mem(ulong base, ulong size) base 6877 drivers/scsi/hpsa.c ulong page_base = ((ulong) base) & PAGE_MASK; base 6878 drivers/scsi/hpsa.c ulong page_offs = ((ulong) base) - page_base; base 37 drivers/scsi/imm.c int base; /* Actual port address */ base 53 drivers/scsi/imm.c static void imm_reset_pulse(unsigned int base); base 67 drivers/scsi/imm.c dev->base = dev->dev->port->base; base 176 drivers/scsi/imm.c unsigned short ppb = dev->base; base 232 drivers/scsi/imm.c unsigned short base = tmp->base; base 246 drivers/scsi/imm.c w_ctr(base, 0x04); base 248 drivers/scsi/imm.c w_dtr(base, mode); base 250 drivers/scsi/imm.c w_ctr(base, 0x06); base 252 drivers/scsi/imm.c a = (r_str(base) & 0x20) ? 0 : 1; base 254 drivers/scsi/imm.c w_ctr(base, 0x07); base 256 drivers/scsi/imm.c w_ctr(base, 0x06); base 298 drivers/scsi/imm.c static int imm_byte_out(unsigned short base, const char *buffer, int len) base 302 drivers/scsi/imm.c w_ctr(base, 0x4); /* apparently a sane mode */ base 304 drivers/scsi/imm.c w_dtr(base, *buffer++); base 305 drivers/scsi/imm.c w_ctr(base, 0x5); /* Drop STROBE low */ base 306 drivers/scsi/imm.c w_dtr(base, *buffer++); base 307 drivers/scsi/imm.c w_ctr(base, 0x0); /* STROBE high + INIT low */ base 309 drivers/scsi/imm.c w_ctr(base, 0x4); /* apparently a sane mode */ base 313 drivers/scsi/imm.c static int imm_nibble_in(unsigned short base, char *buffer, int len) base 321 drivers/scsi/imm.c w_ctr(base, 0x4); base 323 drivers/scsi/imm.c w_ctr(base, 0x6); base 324 drivers/scsi/imm.c l = (r_str(base) & 0xf0) >> 4; base 325 drivers/scsi/imm.c w_ctr(base, 0x5); base 326 drivers/scsi/imm.c *buffer++ = (r_str(base) & 0xf0) | l; base 327 drivers/scsi/imm.c w_ctr(base, 0x4); base 332 drivers/scsi/imm.c static int imm_byte_in(unsigned short base, char *buffer, int len) base 339 drivers/scsi/imm.c w_ctr(base, 0x4); base 341 drivers/scsi/imm.c w_ctr(base, 0x26); base 342 drivers/scsi/imm.c *buffer++ = r_dtr(base); base 343 drivers/scsi/imm.c w_ctr(base, 0x25); base 350 drivers/scsi/imm.c unsigned short ppb = dev->base; base 399 drivers/scsi/imm.c unsigned short ppb = dev->base; base 524 drivers/scsi/imm.c unsigned short ppb = dev->base; base 538 drivers/scsi/imm.c imm_cpp(dev->base, 0x30); /* Disconnect all devices */ base 544 drivers/scsi/imm.c unsigned short ppb = dev->base; base 594 drivers/scsi/imm.c imm_reset_pulse(dev->base); base 629 drivers/scsi/imm.c unsigned short ppb = dev->base; base 779 drivers/scsi/imm.c unsigned short ppb = dev->base; base 979 drivers/scsi/imm.c static void imm_reset_pulse(unsigned int base) base 981 drivers/scsi/imm.c w_ctr(base, 0x04); base 982 drivers/scsi/imm.c w_dtr(base, 0x40); base 984 drivers/scsi/imm.c w_ctr(base, 0x0c); base 985 drivers/scsi/imm.c w_ctr(base, 0x0d); base 987 drivers/scsi/imm.c w_ctr(base, 0x0c); base 988 drivers/scsi/imm.c w_ctr(base, 0x04); base 1000 drivers/scsi/imm.c imm_reset_pulse(dev->base); base 1013 drivers/scsi/imm.c int loop, old_mode, status, k, ppb = dev->base; base 1041 drivers/scsi/imm.c imm_reset_pulse(dev->base); base 1066 drivers/scsi/imm.c imm_reset_pulse(dev->base); base 1083 drivers/scsi/imm.c imm_reset_pulse(dev->base); base 1167 drivers/scsi/imm.c dev->base = -1; base 1203 drivers/scsi/imm.c ppb = dev->base = dev->dev->port->base; base 1237 drivers/scsi/imm.c host->io_port = pb->base; base 162 drivers/scsi/initio.c static void initio_se2_ew_en(unsigned long base); base 163 drivers/scsi/initio.c static void initio_se2_ew_ds(unsigned long base); base 164 drivers/scsi/initio.c static int initio_se2_rd_all(unsigned long base); base 165 drivers/scsi/initio.c static void initio_se2_update_all(unsigned long base); /* setup default pattern */ base 166 drivers/scsi/initio.c static void initio_read_eeprom(unsigned long base); base 276 drivers/scsi/initio.c static void initio_se2_instr(unsigned long base, u8 instr) base 281 drivers/scsi/initio.c outb(SE2CS | SE2DO, base + TUL_NVRAM); /* cs+start bit */ base 283 drivers/scsi/initio.c outb(SE2CS | SE2CLK | SE2DO, base + TUL_NVRAM); /* +CLK */ base 291 drivers/scsi/initio.c outb(b, base + TUL_NVRAM); base 293 drivers/scsi/initio.c outb(b | SE2CLK, base + TUL_NVRAM); /* +CLK */ base 297 drivers/scsi/initio.c outb(SE2CS, base + TUL_NVRAM); /* -CLK */ base 308 drivers/scsi/initio.c void initio_se2_ew_en(unsigned long base) base 310 drivers/scsi/initio.c initio_se2_instr(base, 0x30); /* EWEN */ base 311 drivers/scsi/initio.c outb(0, base + TUL_NVRAM); /* -CS */ base 322 drivers/scsi/initio.c void initio_se2_ew_ds(unsigned long base) base 324 drivers/scsi/initio.c initio_se2_instr(base, 0); /* EWDS */ base 325 drivers/scsi/initio.c outb(0, base + TUL_NVRAM); /* -CS */ base 337 drivers/scsi/initio.c static u16 initio_se2_rd(unsigned long base, u8 addr) base 344 drivers/scsi/initio.c initio_se2_instr(base, instr); /* READ INSTR */ base 347 drivers/scsi/initio.c outb(SE2CS | SE2CLK, base + TUL_NVRAM); /* +CLK */ base 349 drivers/scsi/initio.c outb(SE2CS, base + TUL_NVRAM); /* -CLK */ base 352 drivers/scsi/initio.c rb = inb(base + TUL_NVRAM); base 358 drivers/scsi/initio.c outb(0, base + TUL_NVRAM); /* no chip select */ base 372 drivers/scsi/initio.c static void initio_se2_wr(unsigned long base, u8 addr, u16 val) base 379 drivers/scsi/initio.c initio_se2_instr(base, instr); /* WRITE INSTR */ base 382 drivers/scsi/initio.c outb(SE2CS | SE2DO, base + TUL_NVRAM); /* -CLK+dataBit 1 */ base 384 drivers/scsi/initio.c outb(SE2CS, base + TUL_NVRAM); /* -CLK+dataBit 0 */ base 386 drivers/scsi/initio.c outb(SE2CS | SE2CLK, base + TUL_NVRAM); /* +CLK */ base 390 drivers/scsi/initio.c outb(SE2CS, base + TUL_NVRAM); /* -CLK */ base 392 drivers/scsi/initio.c outb(0, base + TUL_NVRAM); /* -CS */ base 395 drivers/scsi/initio.c outb(SE2CS, base + TUL_NVRAM); /* +CS */ base 399 drivers/scsi/initio.c outb(SE2CS | SE2CLK, base + TUL_NVRAM); /* +CLK */ base 401 drivers/scsi/initio.c outb(SE2CS, base + TUL_NVRAM); /* -CLK */ base 403 drivers/scsi/initio.c if ((rb = inb(base + TUL_NVRAM)) & SE2DI) base 406 drivers/scsi/initio.c outb(0, base + TUL_NVRAM); /* -CS */ base 417 drivers/scsi/initio.c static int initio_se2_rd_all(unsigned long base) base 426 drivers/scsi/initio.c *np++ = initio_se2_rd(base, i); base 447 drivers/scsi/initio.c static void initio_se2_update_all(unsigned long base) base 459 drivers/scsi/initio.c initio_se2_ew_en(base); /* Enable write */ base 465 drivers/scsi/initio.c initio_se2_wr(base, i, *np); base 467 drivers/scsi/initio.c initio_se2_ew_ds(base); /* Disable write */ base 483 drivers/scsi/initio.c static void initio_read_eeprom(unsigned long base) base 489 drivers/scsi/initio.c gctrl = inb(base + TUL_GCTRL); base 490 drivers/scsi/initio.c outb(gctrl | TUL_GCTRL_EEPROM_BIT, base + TUL_GCTRL); base 491 drivers/scsi/initio.c if (initio_se2_rd_all(base) != 1) { base 492 drivers/scsi/initio.c initio_se2_update_all(base); /* setup default pattern */ base 493 drivers/scsi/initio.c initio_se2_rd_all(base); /* load again */ base 496 drivers/scsi/initio.c gctrl = inb(base + TUL_GCTRL); base 497 drivers/scsi/initio.c outb(gctrl & ~TUL_GCTRL_EEPROM_BIT, base + TUL_GCTRL); base 2899 drivers/scsi/initio.c shost->base = host->addr; base 46 drivers/scsi/initio.h unsigned short base; base 9878 drivers/scsi/ipr.c void __iomem *base; base 9882 drivers/scsi/ipr.c base = ioa_cfg->hdw_dma_regs; base 9884 drivers/scsi/ipr.c t->set_interrupt_mask_reg = base + p->set_interrupt_mask_reg; base 9885 drivers/scsi/ipr.c t->clr_interrupt_mask_reg = base + p->clr_interrupt_mask_reg; base 9886 drivers/scsi/ipr.c t->clr_interrupt_mask_reg32 = base + p->clr_interrupt_mask_reg32; base 9887 drivers/scsi/ipr.c t->sense_interrupt_mask_reg = base + p->sense_interrupt_mask_reg; base 9888 drivers/scsi/ipr.c t->sense_interrupt_mask_reg32 = base + p->sense_interrupt_mask_reg32; base 9889 drivers/scsi/ipr.c t->clr_interrupt_reg = base + p->clr_interrupt_reg; base 9890 drivers/scsi/ipr.c t->clr_interrupt_reg32 = base + p->clr_interrupt_reg32; base 9891 drivers/scsi/ipr.c t->sense_interrupt_reg = base + p->sense_interrupt_reg; base 9892 drivers/scsi/ipr.c t->sense_interrupt_reg32 = base + p->sense_interrupt_reg32; base 9893 drivers/scsi/ipr.c t->ioarrin_reg = base + p->ioarrin_reg; base 9894 drivers/scsi/ipr.c t->sense_uproc_interrupt_reg = base + p->sense_uproc_interrupt_reg; base 9895 drivers/scsi/ipr.c t->sense_uproc_interrupt_reg32 = base + p->sense_uproc_interrupt_reg32; base 9896 drivers/scsi/ipr.c t->set_uproc_interrupt_reg = base + p->set_uproc_interrupt_reg; base 9897 drivers/scsi/ipr.c t->set_uproc_interrupt_reg32 = base + p->set_uproc_interrupt_reg32; base 9898 drivers/scsi/ipr.c t->clr_uproc_interrupt_reg = base + p->clr_uproc_interrupt_reg; base 9899 drivers/scsi/ipr.c t->clr_uproc_interrupt_reg32 = base + p->clr_uproc_interrupt_reg32; base 9902 drivers/scsi/ipr.c t->init_feedback_reg = base + p->init_feedback_reg; base 9903 drivers/scsi/ipr.c t->dump_addr_reg = base + p->dump_addr_reg; base 9904 drivers/scsi/ipr.c t->dump_data_reg = base + p->dump_data_reg; base 9905 drivers/scsi/ipr.c t->endian_swap_reg = base + p->endian_swap_reg; base 6884 drivers/scsi/ips.c uint32_t base; base 6887 drivers/scsi/ips.c base = mem_addr & PAGE_MASK; base 6888 drivers/scsi/ips.c offs = mem_addr - base; base 6889 drivers/scsi/ips.c ioremap_ptr = ioremap(base, PAGE_SIZE); base 89 drivers/scsi/lasi700.c unsigned long base = dev->hpa.start + LASI_SCSI_CORE_OFFSET; base 101 drivers/scsi/lasi700.c hostdata->base = ioremap_nocache(base, 0x100); base 119 drivers/scsi/lasi700.c host->base = base; base 134 drivers/scsi/lasi700.c iounmap(hostdata->base); base 149 drivers/scsi/lasi700.c iounmap(hostdata->base); base 4195 drivers/scsi/lpfc/lpfc_attr.c unsigned long base, step, bucket_type; base 4222 drivers/scsi/lpfc/lpfc_attr.c base = simple_strtoul(base_str, NULL, 0); base 4248 drivers/scsi/lpfc/lpfc_attr.c phba->bucket_base = base; base 6479 drivers/scsi/lpfc/lpfc_sli.c uint16_t count, base; base 6578 drivers/scsi/lpfc/lpfc_sli.c base = phba->sli4_hba.max_cfg_param.rpi_base; base 6595 drivers/scsi/lpfc/lpfc_sli.c phba->sli4_hba.rpi_ids[i] = base + i; base 6606 drivers/scsi/lpfc/lpfc_sli.c base = phba->sli4_hba.max_cfg_param.vpi_base; base 6622 drivers/scsi/lpfc/lpfc_sli.c phba->vpi_ids[i] = base + i; base 6633 drivers/scsi/lpfc/lpfc_sli.c base = phba->sli4_hba.max_cfg_param.xri_base; base 6651 drivers/scsi/lpfc/lpfc_sli.c phba->sli4_hba.xri_ids[i] = base + i; base 6662 drivers/scsi/lpfc/lpfc_sli.c base = phba->sli4_hba.max_cfg_param.vfi_base; base 6679 drivers/scsi/lpfc/lpfc_sli.c phba->sli4_hba.vfi_ids[i] = base + i; base 483 drivers/scsi/mac_scsi.c hostdata->base = pio_mem->start; base 2081 drivers/scsi/megaraid.c adapter->base, adapter->host->irq); base 4252 drivers/scsi/megaraid.c adapter->base = mega_baseport; base 4272 drivers/scsi/megaraid.c adapter->host->base = tbase; base 4429 drivers/scsi/megaraid.c mcontroller[i].base = mega_baseport; base 4557 drivers/scsi/megaraid.c iounmap((void *)adapter->base); base 4558 drivers/scsi/megaraid.c release_mem_region(adapter->host->base, 128); base 4560 drivers/scsi/megaraid.c release_region(adapter->base, 16); base 509 drivers/scsi/megaraid.h u64 base; base 770 drivers/scsi/megaraid.h unsigned long base; base 912 drivers/scsi/megaraid.h outb_p(ISSUE_BYTE, (adapter)->base + CMD_PORT) base 914 drivers/scsi/megaraid.h #define irq_state(adapter) inb_p((adapter)->base + INTR_PORT) base 917 drivers/scsi/megaraid.h outb_p((value), (adapter)->base + INTR_PORT) base 920 drivers/scsi/megaraid.h outb_p(ACK_BYTE, (adapter)->base + ACK_PORT) base 923 drivers/scsi/megaraid.h outb_p(ENABLE_INTR_BYTE, (adapter)->base + TOGGLE_PORT) base 926 drivers/scsi/megaraid.h outb_p(DISABLE_INTR_BYTE, (adapter)->base + TOGGLE_PORT) base 213 drivers/scsi/megaraid/megaraid_ioctl.h uint64_t base; base 885 drivers/scsi/megaraid/megaraid_mm.c cinfo->base = hinfo->baseport; base 1888 drivers/scsi/mesh.c mesh_host->base = macio_resource_start(mdev, 0); base 2771 drivers/scsi/mpt3sas/mpt3sas_base.c int base; base 2782 drivers/scsi/mpt3sas/mpt3sas_base.c base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); base 2783 drivers/scsi/mpt3sas/mpt3sas_base.c if (!base) { base 2799 drivers/scsi/mpt3sas/mpt3sas_base.c pci_read_config_word(ioc->pdev, base + 2, &message_control); base 98 drivers/scsi/mvme147.c mvme147_shost->base = 0xfffe4000; base 60 drivers/scsi/mvme16x_scsi.c hostdata->base = (void __iomem *)0xfff47000UL; base 76 drivers/scsi/mvme16x_scsi.c host->base = 0xfff47000UL; base 2189 drivers/scsi/mvumi.c void *base = NULL; base 2195 drivers/scsi/mvumi.c base = mhba->mmio; base 2204 drivers/scsi/mvumi.c regs->ctrl_sts_reg = base + 0x20104; base 2205 drivers/scsi/mvumi.c regs->rstoutn_mask_reg = base + 0x20108; base 2206 drivers/scsi/mvumi.c regs->sys_soft_rst_reg = base + 0x2010C; base 2207 drivers/scsi/mvumi.c regs->main_int_cause_reg = base + 0x20200; base 2208 drivers/scsi/mvumi.c regs->enpointa_mask_reg = base + 0x2020C; base 2209 drivers/scsi/mvumi.c regs->rstoutn_en_reg = base + 0xF1400; base 2211 drivers/scsi/mvumi.c regs->pciea_to_arm_drbl_reg = base + 0x20400; base 2212 drivers/scsi/mvumi.c regs->arm_to_pciea_drbl_reg = base + 0x20408; base 2213 drivers/scsi/mvumi.c regs->arm_to_pciea_mask_reg = base + 0x2040C; base 2214 drivers/scsi/mvumi.c regs->pciea_to_arm_msg0 = base + 0x20430; base 2215 drivers/scsi/mvumi.c regs->pciea_to_arm_msg1 = base + 0x20434; base 2216 drivers/scsi/mvumi.c regs->arm_to_pciea_msg0 = base + 0x20438; base 2217 drivers/scsi/mvumi.c regs->arm_to_pciea_msg1 = base + 0x2043C; base 2221 drivers/scsi/mvumi.c regs->inb_aval_count_basel = base + 0x508; base 2222 drivers/scsi/mvumi.c regs->inb_aval_count_baseh = base + 0x50C; base 2223 drivers/scsi/mvumi.c regs->inb_write_pointer = base + 0x518; base 2224 drivers/scsi/mvumi.c regs->inb_read_pointer = base + 0x51C; base 2225 drivers/scsi/mvumi.c regs->outb_coal_cfg = base + 0x568; base 2226 drivers/scsi/mvumi.c regs->outb_copy_basel = base + 0x5B0; base 2227 drivers/scsi/mvumi.c regs->outb_copy_baseh = base + 0x5B4; base 2228 drivers/scsi/mvumi.c regs->outb_copy_pointer = base + 0x544; base 2229 drivers/scsi/mvumi.c regs->outb_read_pointer = base + 0x548; base 2230 drivers/scsi/mvumi.c regs->outb_isr_cause = base + 0x560; base 2231 drivers/scsi/mvumi.c regs->outb_coal_cfg = base + 0x568; base 2247 drivers/scsi/mvumi.c base = mhba->mmio; base 2255 drivers/scsi/mvumi.c regs->ctrl_sts_reg = base + 0x20104; base 2256 drivers/scsi/mvumi.c regs->rstoutn_mask_reg = base + 0x1010C; base 2257 drivers/scsi/mvumi.c regs->sys_soft_rst_reg = base + 0x10108; base 2258 drivers/scsi/mvumi.c regs->main_int_cause_reg = base + 0x10200; base 2259 drivers/scsi/mvumi.c regs->enpointa_mask_reg = base + 0x1020C; base 2260 drivers/scsi/mvumi.c regs->rstoutn_en_reg = base + 0xF1400; base 2263 drivers/scsi/mvumi.c regs->pciea_to_arm_drbl_reg = base + 0x10460; base 2264 drivers/scsi/mvumi.c regs->arm_to_pciea_drbl_reg = base + 0x10480; base 2265 drivers/scsi/mvumi.c regs->arm_to_pciea_mask_reg = base + 0x10484; base 2266 drivers/scsi/mvumi.c regs->pciea_to_arm_msg0 = base + 0x10400; base 2267 drivers/scsi/mvumi.c regs->pciea_to_arm_msg1 = base + 0x10404; base 2268 drivers/scsi/mvumi.c regs->arm_to_pciea_msg0 = base + 0x10420; base 2269 drivers/scsi/mvumi.c regs->arm_to_pciea_msg1 = base + 0x10424; base 2272 drivers/scsi/mvumi.c regs->reset_request = base + 0x10108; base 2273 drivers/scsi/mvumi.c regs->reset_enable = base + 0x1010c; base 2276 drivers/scsi/mvumi.c regs->inb_aval_count_basel = base + 0x4008; base 2277 drivers/scsi/mvumi.c regs->inb_aval_count_baseh = base + 0x400C; base 2278 drivers/scsi/mvumi.c regs->inb_write_pointer = base + 0x4018; base 2279 drivers/scsi/mvumi.c regs->inb_read_pointer = base + 0x401C; base 2280 drivers/scsi/mvumi.c regs->outb_copy_basel = base + 0x4058; base 2281 drivers/scsi/mvumi.c regs->outb_copy_baseh = base + 0x405C; base 2282 drivers/scsi/mvumi.c regs->outb_copy_pointer = base + 0x406C; base 2283 drivers/scsi/mvumi.c regs->outb_read_pointer = base + 0x4070; base 2284 drivers/scsi/mvumi.c regs->outb_coal_cfg = base + 0x4080; base 2285 drivers/scsi/mvumi.c regs->outb_isr_cause = base + 0x4088; base 165 drivers/scsi/myrb.c void __iomem *base = cb->io_base; base 172 drivers/scsi/myrb.c cb->get_cmd_mbox(base); base 810 drivers/scsi/myrb.c void __iomem *base = cb->io_base; base 890 drivers/scsi/myrb.c status = mmio_init_fn(pdev, base, &mbox); base 894 drivers/scsi/myrb.c status = mmio_init_fn(pdev, base, &mbox); base 2547 drivers/scsi/myrb.c static inline void DAC960_LA_hw_mbox_new_cmd(void __iomem *base) base 2549 drivers/scsi/myrb.c writeb(DAC960_LA_IDB_HWMBOX_NEW_CMD, base + DAC960_LA_IDB_OFFSET); base 2552 drivers/scsi/myrb.c static inline void DAC960_LA_ack_hw_mbox_status(void __iomem *base) base 2554 drivers/scsi/myrb.c writeb(DAC960_LA_IDB_HWMBOX_ACK_STS, base + DAC960_LA_IDB_OFFSET); base 2557 drivers/scsi/myrb.c static inline void DAC960_LA_gen_intr(void __iomem *base) base 2559 drivers/scsi/myrb.c writeb(DAC960_LA_IDB_GEN_IRQ, base + DAC960_LA_IDB_OFFSET); base 2562 drivers/scsi/myrb.c static inline void DAC960_LA_reset_ctrl(void __iomem *base) base 2564 drivers/scsi/myrb.c writeb(DAC960_LA_IDB_CTRL_RESET, base + DAC960_LA_IDB_OFFSET); base 2567 drivers/scsi/myrb.c static inline void DAC960_LA_mem_mbox_new_cmd(void __iomem *base) base 2569 drivers/scsi/myrb.c writeb(DAC960_LA_IDB_MMBOX_NEW_CMD, base + DAC960_LA_IDB_OFFSET); base 2572 drivers/scsi/myrb.c static inline bool DAC960_LA_hw_mbox_is_full(void __iomem *base) base 2574 drivers/scsi/myrb.c unsigned char idb = readb(base + DAC960_LA_IDB_OFFSET); base 2579 drivers/scsi/myrb.c static inline bool DAC960_LA_init_in_progress(void __iomem *base) base 2581 drivers/scsi/myrb.c unsigned char idb = readb(base + DAC960_LA_IDB_OFFSET); base 2586 drivers/scsi/myrb.c static inline void DAC960_LA_ack_hw_mbox_intr(void __iomem *base) base 2588 drivers/scsi/myrb.c writeb(DAC960_LA_ODB_HWMBOX_ACK_IRQ, base + DAC960_LA_ODB_OFFSET); base 2591 drivers/scsi/myrb.c static inline void DAC960_LA_ack_mem_mbox_intr(void __iomem *base) base 2593 drivers/scsi/myrb.c writeb(DAC960_LA_ODB_MMBOX_ACK_IRQ, base + DAC960_LA_ODB_OFFSET); base 2596 drivers/scsi/myrb.c static inline void DAC960_LA_ack_intr(void __iomem *base) base 2599 drivers/scsi/myrb.c base + DAC960_LA_ODB_OFFSET); base 2602 drivers/scsi/myrb.c static inline bool DAC960_LA_hw_mbox_status_available(void __iomem *base) base 2604 drivers/scsi/myrb.c unsigned char odb = readb(base + DAC960_LA_ODB_OFFSET); base 2609 drivers/scsi/myrb.c static inline bool DAC960_LA_mem_mbox_status_available(void __iomem *base) base 2611 drivers/scsi/myrb.c unsigned char odb = readb(base + DAC960_LA_ODB_OFFSET); base 2616 drivers/scsi/myrb.c static inline void DAC960_LA_enable_intr(void __iomem *base) base 2621 drivers/scsi/myrb.c writeb(odb, base + DAC960_LA_IRQMASK_OFFSET); base 2624 drivers/scsi/myrb.c static inline void DAC960_LA_disable_intr(void __iomem *base) base 2629 drivers/scsi/myrb.c writeb(odb, base + DAC960_LA_IRQMASK_OFFSET); base 2632 drivers/scsi/myrb.c static inline bool DAC960_LA_intr_enabled(void __iomem *base) base 2634 drivers/scsi/myrb.c unsigned char imask = readb(base + DAC960_LA_IRQMASK_OFFSET); base 2652 drivers/scsi/myrb.c static inline void DAC960_LA_write_hw_mbox(void __iomem *base, base 2655 drivers/scsi/myrb.c writel(mbox->words[0], base + DAC960_LA_CMDOP_OFFSET); base 2656 drivers/scsi/myrb.c writel(mbox->words[1], base + DAC960_LA_MBOX4_OFFSET); base 2657 drivers/scsi/myrb.c writel(mbox->words[2], base + DAC960_LA_MBOX8_OFFSET); base 2658 drivers/scsi/myrb.c writeb(mbox->bytes[12], base + DAC960_LA_MBOX12_OFFSET); base 2661 drivers/scsi/myrb.c static inline unsigned char DAC960_LA_read_status_cmd_ident(void __iomem *base) base 2663 drivers/scsi/myrb.c return readb(base + DAC960_LA_STSID_OFFSET); base 2666 drivers/scsi/myrb.c static inline unsigned short DAC960_LA_read_status(void __iomem *base) base 2668 drivers/scsi/myrb.c return readw(base + DAC960_LA_STS_OFFSET); base 2672 drivers/scsi/myrb.c DAC960_LA_read_error_status(void __iomem *base, unsigned char *error, base 2675 drivers/scsi/myrb.c unsigned char errsts = readb(base + DAC960_LA_ERRSTS_OFFSET); base 2682 drivers/scsi/myrb.c *param0 = readb(base + DAC960_LA_CMDOP_OFFSET); base 2683 drivers/scsi/myrb.c *param1 = readb(base + DAC960_LA_CMDID_OFFSET); base 2684 drivers/scsi/myrb.c writeb(0xFF, base + DAC960_LA_ERRSTS_OFFSET); base 2689 drivers/scsi/myrb.c DAC960_LA_mbox_init(struct pci_dev *pdev, void __iomem *base, base 2696 drivers/scsi/myrb.c if (!DAC960_LA_hw_mbox_is_full(base)) base 2701 drivers/scsi/myrb.c if (DAC960_LA_hw_mbox_is_full(base)) { base 2706 drivers/scsi/myrb.c DAC960_LA_write_hw_mbox(base, mbox); base 2707 drivers/scsi/myrb.c DAC960_LA_hw_mbox_new_cmd(base); base 2710 drivers/scsi/myrb.c if (DAC960_LA_hw_mbox_status_available(base)) base 2715 drivers/scsi/myrb.c if (!DAC960_LA_hw_mbox_status_available(base)) { base 2719 drivers/scsi/myrb.c status = DAC960_LA_read_status(base); base 2720 drivers/scsi/myrb.c DAC960_LA_ack_hw_mbox_intr(base); base 2721 drivers/scsi/myrb.c DAC960_LA_ack_hw_mbox_status(base); base 2727 drivers/scsi/myrb.c struct myrb_hba *cb, void __iomem *base) base 2732 drivers/scsi/myrb.c DAC960_LA_disable_intr(base); base 2733 drivers/scsi/myrb.c DAC960_LA_ack_hw_mbox_status(base); base 2736 drivers/scsi/myrb.c while (DAC960_LA_init_in_progress(base) && base 2738 drivers/scsi/myrb.c if (DAC960_LA_read_error_status(base, &error, base 2753 drivers/scsi/myrb.c DAC960_LA_reset_ctrl(base); base 2756 drivers/scsi/myrb.c DAC960_LA_enable_intr(base); base 2772 drivers/scsi/myrb.c void __iomem *base = cb->io_base; base 2777 drivers/scsi/myrb.c DAC960_LA_ack_intr(base); base 2824 drivers/scsi/myrb.c static inline void DAC960_PG_hw_mbox_new_cmd(void __iomem *base) base 2826 drivers/scsi/myrb.c writel(DAC960_PG_IDB_HWMBOX_NEW_CMD, base + DAC960_PG_IDB_OFFSET); base 2829 drivers/scsi/myrb.c static inline void DAC960_PG_ack_hw_mbox_status(void __iomem *base) base 2831 drivers/scsi/myrb.c writel(DAC960_PG_IDB_HWMBOX_ACK_STS, base + DAC960_PG_IDB_OFFSET); base 2834 drivers/scsi/myrb.c static inline void DAC960_PG_gen_intr(void __iomem *base) base 2836 drivers/scsi/myrb.c writel(DAC960_PG_IDB_GEN_IRQ, base + DAC960_PG_IDB_OFFSET); base 2839 drivers/scsi/myrb.c static inline void DAC960_PG_reset_ctrl(void __iomem *base) base 2841 drivers/scsi/myrb.c writel(DAC960_PG_IDB_CTRL_RESET, base + DAC960_PG_IDB_OFFSET); base 2844 drivers/scsi/myrb.c static inline void DAC960_PG_mem_mbox_new_cmd(void __iomem *base) base 2846 drivers/scsi/myrb.c writel(DAC960_PG_IDB_MMBOX_NEW_CMD, base + DAC960_PG_IDB_OFFSET); base 2849 drivers/scsi/myrb.c static inline bool DAC960_PG_hw_mbox_is_full(void __iomem *base) base 2851 drivers/scsi/myrb.c unsigned char idb = readl(base + DAC960_PG_IDB_OFFSET); base 2856 drivers/scsi/myrb.c static inline bool DAC960_PG_init_in_progress(void __iomem *base) base 2858 drivers/scsi/myrb.c unsigned char idb = readl(base + DAC960_PG_IDB_OFFSET); base 2863 drivers/scsi/myrb.c static inline void DAC960_PG_ack_hw_mbox_intr(void __iomem *base) base 2865 drivers/scsi/myrb.c writel(DAC960_PG_ODB_HWMBOX_ACK_IRQ, base + DAC960_PG_ODB_OFFSET); base 2868 drivers/scsi/myrb.c static inline void DAC960_PG_ack_mem_mbox_intr(void __iomem *base) base 2870 drivers/scsi/myrb.c writel(DAC960_PG_ODB_MMBOX_ACK_IRQ, base + DAC960_PG_ODB_OFFSET); base 2873 drivers/scsi/myrb.c static inline void DAC960_PG_ack_intr(void __iomem *base) base 2876 drivers/scsi/myrb.c base + DAC960_PG_ODB_OFFSET); base 2879 drivers/scsi/myrb.c static inline bool DAC960_PG_hw_mbox_status_available(void __iomem *base) base 2881 drivers/scsi/myrb.c unsigned char odb = readl(base + DAC960_PG_ODB_OFFSET); base 2886 drivers/scsi/myrb.c static inline bool DAC960_PG_mem_mbox_status_available(void __iomem *base) base 2888 drivers/scsi/myrb.c unsigned char odb = readl(base + DAC960_PG_ODB_OFFSET); base 2893 drivers/scsi/myrb.c static inline void DAC960_PG_enable_intr(void __iomem *base) base 2898 drivers/scsi/myrb.c writel(imask, base + DAC960_PG_IRQMASK_OFFSET); base 2901 drivers/scsi/myrb.c static inline void DAC960_PG_disable_intr(void __iomem *base) base 2905 drivers/scsi/myrb.c writel(imask, base + DAC960_PG_IRQMASK_OFFSET); base 2908 drivers/scsi/myrb.c static inline bool DAC960_PG_intr_enabled(void __iomem *base) base 2910 drivers/scsi/myrb.c unsigned int imask = readl(base + DAC960_PG_IRQMASK_OFFSET); base 2928 drivers/scsi/myrb.c static inline void DAC960_PG_write_hw_mbox(void __iomem *base, base 2931 drivers/scsi/myrb.c writel(mbox->words[0], base + DAC960_PG_CMDOP_OFFSET); base 2932 drivers/scsi/myrb.c writel(mbox->words[1], base + DAC960_PG_MBOX4_OFFSET); base 2933 drivers/scsi/myrb.c writel(mbox->words[2], base + DAC960_PG_MBOX8_OFFSET); base 2934 drivers/scsi/myrb.c writeb(mbox->bytes[12], base + DAC960_PG_MBOX12_OFFSET); base 2938 drivers/scsi/myrb.c DAC960_PG_read_status_cmd_ident(void __iomem *base) base 2940 drivers/scsi/myrb.c return readb(base + DAC960_PG_STSID_OFFSET); base 2944 drivers/scsi/myrb.c DAC960_PG_read_status(void __iomem *base) base 2946 drivers/scsi/myrb.c return readw(base + DAC960_PG_STS_OFFSET); base 2950 drivers/scsi/myrb.c DAC960_PG_read_error_status(void __iomem *base, unsigned char *error, base 2953 drivers/scsi/myrb.c unsigned char errsts = readb(base + DAC960_PG_ERRSTS_OFFSET); base 2959 drivers/scsi/myrb.c *param0 = readb(base + DAC960_PG_CMDOP_OFFSET); base 2960 drivers/scsi/myrb.c *param1 = readb(base + DAC960_PG_CMDID_OFFSET); base 2961 drivers/scsi/myrb.c writeb(0, base + DAC960_PG_ERRSTS_OFFSET); base 2966 drivers/scsi/myrb.c DAC960_PG_mbox_init(struct pci_dev *pdev, void __iomem *base, base 2973 drivers/scsi/myrb.c if (!DAC960_PG_hw_mbox_is_full(base)) base 2978 drivers/scsi/myrb.c if (DAC960_PG_hw_mbox_is_full(base)) { base 2983 drivers/scsi/myrb.c DAC960_PG_write_hw_mbox(base, mbox); base 2984 drivers/scsi/myrb.c DAC960_PG_hw_mbox_new_cmd(base); base 2988 drivers/scsi/myrb.c if (DAC960_PG_hw_mbox_status_available(base)) base 2993 drivers/scsi/myrb.c if (!DAC960_PG_hw_mbox_status_available(base)) { base 2998 drivers/scsi/myrb.c status = DAC960_PG_read_status(base); base 2999 drivers/scsi/myrb.c DAC960_PG_ack_hw_mbox_intr(base); base 3000 drivers/scsi/myrb.c DAC960_PG_ack_hw_mbox_status(base); base 3006 drivers/scsi/myrb.c struct myrb_hba *cb, void __iomem *base) base 3011 drivers/scsi/myrb.c DAC960_PG_disable_intr(base); base 3012 drivers/scsi/myrb.c DAC960_PG_ack_hw_mbox_status(base); base 3014 drivers/scsi/myrb.c while (DAC960_PG_init_in_progress(base) && base 3016 drivers/scsi/myrb.c if (DAC960_PG_read_error_status(base, &error, base 3031 drivers/scsi/myrb.c DAC960_PG_reset_ctrl(base); base 3034 drivers/scsi/myrb.c DAC960_PG_enable_intr(base); base 3050 drivers/scsi/myrb.c void __iomem *base = cb->io_base; base 3055 drivers/scsi/myrb.c DAC960_PG_ack_intr(base); base 3102 drivers/scsi/myrb.c static inline void DAC960_PD_hw_mbox_new_cmd(void __iomem *base) base 3104 drivers/scsi/myrb.c writeb(DAC960_PD_IDB_HWMBOX_NEW_CMD, base + DAC960_PD_IDB_OFFSET); base 3107 drivers/scsi/myrb.c static inline void DAC960_PD_ack_hw_mbox_status(void __iomem *base) base 3109 drivers/scsi/myrb.c writeb(DAC960_PD_IDB_HWMBOX_ACK_STS, base + DAC960_PD_IDB_OFFSET); base 3112 drivers/scsi/myrb.c static inline void DAC960_PD_gen_intr(void __iomem *base) base 3114 drivers/scsi/myrb.c writeb(DAC960_PD_IDB_GEN_IRQ, base + DAC960_PD_IDB_OFFSET); base 3117 drivers/scsi/myrb.c static inline void DAC960_PD_reset_ctrl(void __iomem *base) base 3119 drivers/scsi/myrb.c writeb(DAC960_PD_IDB_CTRL_RESET, base + DAC960_PD_IDB_OFFSET); base 3122 drivers/scsi/myrb.c static inline bool DAC960_PD_hw_mbox_is_full(void __iomem *base) base 3124 drivers/scsi/myrb.c unsigned char idb = readb(base + DAC960_PD_IDB_OFFSET); base 3129 drivers/scsi/myrb.c static inline bool DAC960_PD_init_in_progress(void __iomem *base) base 3131 drivers/scsi/myrb.c unsigned char idb = readb(base + DAC960_PD_IDB_OFFSET); base 3136 drivers/scsi/myrb.c static inline void DAC960_PD_ack_intr(void __iomem *base) base 3138 drivers/scsi/myrb.c writeb(DAC960_PD_ODB_HWMBOX_ACK_IRQ, base + DAC960_PD_ODB_OFFSET); base 3141 drivers/scsi/myrb.c static inline bool DAC960_PD_hw_mbox_status_available(void __iomem *base) base 3143 drivers/scsi/myrb.c unsigned char odb = readb(base + DAC960_PD_ODB_OFFSET); base 3148 drivers/scsi/myrb.c static inline void DAC960_PD_enable_intr(void __iomem *base) base 3150 drivers/scsi/myrb.c writeb(DAC960_PD_IRQMASK_ENABLE_IRQ, base + DAC960_PD_IRQEN_OFFSET); base 3153 drivers/scsi/myrb.c static inline void DAC960_PD_disable_intr(void __iomem *base) base 3155 drivers/scsi/myrb.c writeb(0, base + DAC960_PD_IRQEN_OFFSET); base 3158 drivers/scsi/myrb.c static inline bool DAC960_PD_intr_enabled(void __iomem *base) base 3160 drivers/scsi/myrb.c unsigned char imask = readb(base + DAC960_PD_IRQEN_OFFSET); base 3165 drivers/scsi/myrb.c static inline void DAC960_PD_write_cmd_mbox(void __iomem *base, base 3168 drivers/scsi/myrb.c writel(mbox->words[0], base + DAC960_PD_CMDOP_OFFSET); base 3169 drivers/scsi/myrb.c writel(mbox->words[1], base + DAC960_PD_MBOX4_OFFSET); base 3170 drivers/scsi/myrb.c writel(mbox->words[2], base + DAC960_PD_MBOX8_OFFSET); base 3171 drivers/scsi/myrb.c writeb(mbox->bytes[12], base + DAC960_PD_MBOX12_OFFSET); base 3175 drivers/scsi/myrb.c DAC960_PD_read_status_cmd_ident(void __iomem *base) base 3177 drivers/scsi/myrb.c return readb(base + DAC960_PD_STSID_OFFSET); base 3181 drivers/scsi/myrb.c DAC960_PD_read_status(void __iomem *base) base 3183 drivers/scsi/myrb.c return readw(base + DAC960_PD_STS_OFFSET); base 3187 drivers/scsi/myrb.c DAC960_PD_read_error_status(void __iomem *base, unsigned char *error, base 3190 drivers/scsi/myrb.c unsigned char errsts = readb(base + DAC960_PD_ERRSTS_OFFSET); base 3196 drivers/scsi/myrb.c *param0 = readb(base + DAC960_PD_CMDOP_OFFSET); base 3197 drivers/scsi/myrb.c *param1 = readb(base + DAC960_PD_CMDID_OFFSET); base 3198 drivers/scsi/myrb.c writeb(0, base + DAC960_PD_ERRSTS_OFFSET); base 3204 drivers/scsi/myrb.c void __iomem *base = cb->io_base; base 3207 drivers/scsi/myrb.c while (DAC960_PD_hw_mbox_is_full(base)) base 3209 drivers/scsi/myrb.c DAC960_PD_write_cmd_mbox(base, mbox); base 3210 drivers/scsi/myrb.c DAC960_PD_hw_mbox_new_cmd(base); base 3214 drivers/scsi/myrb.c struct myrb_hba *cb, void __iomem *base) base 3224 drivers/scsi/myrb.c DAC960_PD_disable_intr(base); base 3225 drivers/scsi/myrb.c DAC960_PD_ack_hw_mbox_status(base); base 3227 drivers/scsi/myrb.c while (DAC960_PD_init_in_progress(base) && base 3229 drivers/scsi/myrb.c if (DAC960_PD_read_error_status(base, &error, base 3244 drivers/scsi/myrb.c DAC960_PD_reset_ctrl(base); base 3247 drivers/scsi/myrb.c DAC960_PD_enable_intr(base); base 3258 drivers/scsi/myrb.c void __iomem *base = cb->io_base; base 3262 drivers/scsi/myrb.c while (DAC960_PD_hw_mbox_status_available(base)) { base 3263 drivers/scsi/myrb.c unsigned char id = DAC960_PD_read_status_cmd_ident(base); base 3277 drivers/scsi/myrb.c cmd_blk->status = DAC960_PD_read_status(base); base 3282 drivers/scsi/myrb.c DAC960_PD_ack_intr(base); base 3283 drivers/scsi/myrb.c DAC960_PD_ack_hw_mbox_status(base); base 3343 drivers/scsi/myrb.c void __iomem *base = cb->io_base; base 3372 drivers/scsi/myrb.c while (DAC960_PD_hw_mbox_is_full(base)) base 3374 drivers/scsi/myrb.c DAC960_PD_write_cmd_mbox(base, mbox); base 3375 drivers/scsi/myrb.c DAC960_PD_hw_mbox_new_cmd(base); base 3380 drivers/scsi/myrb.c struct myrb_hba *cb, void __iomem *base) base 3390 drivers/scsi/myrb.c DAC960_PD_disable_intr(base); base 3391 drivers/scsi/myrb.c DAC960_PD_ack_hw_mbox_status(base); base 3393 drivers/scsi/myrb.c while (DAC960_PD_init_in_progress(base) && base 3395 drivers/scsi/myrb.c if (DAC960_PD_read_error_status(base, &error, base 3410 drivers/scsi/myrb.c DAC960_PD_reset_ctrl(base); base 3413 drivers/scsi/myrb.c DAC960_PD_enable_intr(base); base 3424 drivers/scsi/myrb.c void __iomem *base = cb->io_base; base 3428 drivers/scsi/myrb.c while (DAC960_PD_hw_mbox_status_available(base)) { base 3429 drivers/scsi/myrb.c unsigned char id = DAC960_PD_read_status_cmd_ident(base); base 3446 drivers/scsi/myrb.c cmd_blk->status = DAC960_PD_read_status(base); base 3451 drivers/scsi/myrb.c DAC960_PD_ack_intr(base); base 3452 drivers/scsi/myrb.c DAC960_PD_ack_hw_mbox_status(base); base 728 drivers/scsi/myrb.h void (*get_cmd_mbox)(void __iomem *base); base 729 drivers/scsi/myrb.h void (*disable_intr)(void __iomem *base); base 730 drivers/scsi/myrb.h void (*reset)(void __iomem *base); base 947 drivers/scsi/myrb.h struct myrb_hba *cb, void __iomem *base); base 949 drivers/scsi/myrb.h void __iomem *base, base 106 drivers/scsi/myrs.c void __iomem *base = cs->io_base; base 114 drivers/scsi/myrs.c cs->get_cmd_mbox(base); base 485 drivers/scsi/myrs.c void __iomem *base = cs->io_base; base 569 drivers/scsi/myrs.c status = enable_mbox_fn(base, mbox_addr); base 2402 drivers/scsi/myrs.c static inline void DAC960_GEM_hw_mbox_new_cmd(void __iomem *base) base 2406 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IDB_READ_OFFSET); base 2409 drivers/scsi/myrs.c static inline void DAC960_GEM_ack_hw_mbox_status(void __iomem *base) base 2413 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IDB_CLEAR_OFFSET); base 2416 drivers/scsi/myrs.c static inline void DAC960_GEM_gen_intr(void __iomem *base) base 2420 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IDB_READ_OFFSET); base 2423 drivers/scsi/myrs.c static inline void DAC960_GEM_reset_ctrl(void __iomem *base) base 2427 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IDB_READ_OFFSET); base 2430 drivers/scsi/myrs.c static inline void DAC960_GEM_mem_mbox_new_cmd(void __iomem *base) base 2434 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IDB_READ_OFFSET); base 2437 drivers/scsi/myrs.c static inline bool DAC960_GEM_hw_mbox_is_full(void __iomem *base) base 2441 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_IDB_READ_OFFSET); base 2445 drivers/scsi/myrs.c static inline bool DAC960_GEM_init_in_progress(void __iomem *base) base 2449 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_IDB_READ_OFFSET); base 2453 drivers/scsi/myrs.c static inline void DAC960_GEM_ack_hw_mbox_intr(void __iomem *base) base 2457 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_ODB_CLEAR_OFFSET); base 2460 drivers/scsi/myrs.c static inline void DAC960_GEM_ack_mem_mbox_intr(void __iomem *base) base 2464 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_ODB_CLEAR_OFFSET); base 2467 drivers/scsi/myrs.c static inline void DAC960_GEM_ack_intr(void __iomem *base) base 2472 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_ODB_CLEAR_OFFSET); base 2475 drivers/scsi/myrs.c static inline bool DAC960_GEM_hw_mbox_status_available(void __iomem *base) base 2479 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_ODB_READ_OFFSET); base 2483 drivers/scsi/myrs.c static inline bool DAC960_GEM_mem_mbox_status_available(void __iomem *base) base 2487 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_ODB_READ_OFFSET); base 2491 drivers/scsi/myrs.c static inline void DAC960_GEM_enable_intr(void __iomem *base) base 2495 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IRQMASK_CLEAR_OFFSET); base 2498 drivers/scsi/myrs.c static inline void DAC960_GEM_disable_intr(void __iomem *base) base 2502 drivers/scsi/myrs.c writel(val, base + DAC960_GEM_IRQMASK_READ_OFFSET); base 2505 drivers/scsi/myrs.c static inline bool DAC960_GEM_intr_enabled(void __iomem *base) base 2509 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_IRQMASK_READ_OFFSET); base 2527 drivers/scsi/myrs.c static inline void DAC960_GEM_write_hw_mbox(void __iomem *base, base 2530 drivers/scsi/myrs.c dma_addr_writeql(cmd_mbox_addr, base + DAC960_GEM_CMDMBX_OFFSET); base 2533 drivers/scsi/myrs.c static inline unsigned short DAC960_GEM_read_cmd_ident(void __iomem *base) base 2535 drivers/scsi/myrs.c return readw(base + DAC960_GEM_CMDSTS_OFFSET); base 2538 drivers/scsi/myrs.c static inline unsigned char DAC960_GEM_read_cmd_status(void __iomem *base) base 2540 drivers/scsi/myrs.c return readw(base + DAC960_GEM_CMDSTS_OFFSET + 2); base 2544 drivers/scsi/myrs.c DAC960_GEM_read_error_status(void __iomem *base, unsigned char *error, base 2549 drivers/scsi/myrs.c val = readl(base + DAC960_GEM_ERRSTS_READ_OFFSET); base 2553 drivers/scsi/myrs.c *param0 = readb(base + DAC960_GEM_CMDMBX_OFFSET + 0); base 2554 drivers/scsi/myrs.c *param1 = readb(base + DAC960_GEM_CMDMBX_OFFSET + 1); base 2555 drivers/scsi/myrs.c writel(0x03000000, base + DAC960_GEM_ERRSTS_CLEAR_OFFSET); base 2560 drivers/scsi/myrs.c DAC960_GEM_mbox_init(void __iomem *base, dma_addr_t mbox_addr) base 2564 drivers/scsi/myrs.c while (DAC960_GEM_hw_mbox_is_full(base)) base 2566 drivers/scsi/myrs.c DAC960_GEM_write_hw_mbox(base, mbox_addr); base 2567 drivers/scsi/myrs.c DAC960_GEM_hw_mbox_new_cmd(base); base 2568 drivers/scsi/myrs.c while (!DAC960_GEM_hw_mbox_status_available(base)) base 2570 drivers/scsi/myrs.c status = DAC960_GEM_read_cmd_status(base); base 2571 drivers/scsi/myrs.c DAC960_GEM_ack_hw_mbox_intr(base); base 2572 drivers/scsi/myrs.c DAC960_GEM_ack_hw_mbox_status(base); base 2578 drivers/scsi/myrs.c struct myrs_hba *cs, void __iomem *base) base 2583 drivers/scsi/myrs.c DAC960_GEM_disable_intr(base); base 2584 drivers/scsi/myrs.c DAC960_GEM_ack_hw_mbox_status(base); base 2586 drivers/scsi/myrs.c while (DAC960_GEM_init_in_progress(base) && base 2588 drivers/scsi/myrs.c if (DAC960_GEM_read_error_status(base, &status, base 2603 drivers/scsi/myrs.c DAC960_GEM_reset_ctrl(base); base 2606 drivers/scsi/myrs.c DAC960_GEM_enable_intr(base); base 2617 drivers/scsi/myrs.c void __iomem *base = cs->io_base; base 2622 drivers/scsi/myrs.c DAC960_GEM_ack_intr(base); base 2672 drivers/scsi/myrs.c static inline void DAC960_BA_hw_mbox_new_cmd(void __iomem *base) base 2674 drivers/scsi/myrs.c writeb(DAC960_BA_IDB_HWMBOX_NEW_CMD, base + DAC960_BA_IDB_OFFSET); base 2677 drivers/scsi/myrs.c static inline void DAC960_BA_ack_hw_mbox_status(void __iomem *base) base 2679 drivers/scsi/myrs.c writeb(DAC960_BA_IDB_HWMBOX_ACK_STS, base + DAC960_BA_IDB_OFFSET); base 2682 drivers/scsi/myrs.c static inline void DAC960_BA_gen_intr(void __iomem *base) base 2684 drivers/scsi/myrs.c writeb(DAC960_BA_IDB_GEN_IRQ, base + DAC960_BA_IDB_OFFSET); base 2687 drivers/scsi/myrs.c static inline void DAC960_BA_reset_ctrl(void __iomem *base) base 2689 drivers/scsi/myrs.c writeb(DAC960_BA_IDB_CTRL_RESET, base + DAC960_BA_IDB_OFFSET); base 2692 drivers/scsi/myrs.c static inline void DAC960_BA_mem_mbox_new_cmd(void __iomem *base) base 2694 drivers/scsi/myrs.c writeb(DAC960_BA_IDB_MMBOX_NEW_CMD, base + DAC960_BA_IDB_OFFSET); base 2697 drivers/scsi/myrs.c static inline bool DAC960_BA_hw_mbox_is_full(void __iomem *base) base 2701 drivers/scsi/myrs.c val = readb(base + DAC960_BA_IDB_OFFSET); base 2705 drivers/scsi/myrs.c static inline bool DAC960_BA_init_in_progress(void __iomem *base) base 2709 drivers/scsi/myrs.c val = readb(base + DAC960_BA_IDB_OFFSET); base 2713 drivers/scsi/myrs.c static inline void DAC960_BA_ack_hw_mbox_intr(void __iomem *base) base 2715 drivers/scsi/myrs.c writeb(DAC960_BA_ODB_HWMBOX_ACK_IRQ, base + DAC960_BA_ODB_OFFSET); base 2718 drivers/scsi/myrs.c static inline void DAC960_BA_ack_mem_mbox_intr(void __iomem *base) base 2720 drivers/scsi/myrs.c writeb(DAC960_BA_ODB_MMBOX_ACK_IRQ, base + DAC960_BA_ODB_OFFSET); base 2723 drivers/scsi/myrs.c static inline void DAC960_BA_ack_intr(void __iomem *base) base 2726 drivers/scsi/myrs.c base + DAC960_BA_ODB_OFFSET); base 2729 drivers/scsi/myrs.c static inline bool DAC960_BA_hw_mbox_status_available(void __iomem *base) base 2733 drivers/scsi/myrs.c val = readb(base + DAC960_BA_ODB_OFFSET); base 2737 drivers/scsi/myrs.c static inline bool DAC960_BA_mem_mbox_status_available(void __iomem *base) base 2741 drivers/scsi/myrs.c val = readb(base + DAC960_BA_ODB_OFFSET); base 2745 drivers/scsi/myrs.c static inline void DAC960_BA_enable_intr(void __iomem *base) base 2747 drivers/scsi/myrs.c writeb(~DAC960_BA_IRQMASK_DISABLE_IRQ, base + DAC960_BA_IRQMASK_OFFSET); base 2750 drivers/scsi/myrs.c static inline void DAC960_BA_disable_intr(void __iomem *base) base 2752 drivers/scsi/myrs.c writeb(0xFF, base + DAC960_BA_IRQMASK_OFFSET); base 2755 drivers/scsi/myrs.c static inline bool DAC960_BA_intr_enabled(void __iomem *base) base 2759 drivers/scsi/myrs.c val = readb(base + DAC960_BA_IRQMASK_OFFSET); base 2776 drivers/scsi/myrs.c static inline void DAC960_BA_write_hw_mbox(void __iomem *base, base 2779 drivers/scsi/myrs.c dma_addr_writeql(cmd_mbox_addr, base + DAC960_BA_CMDMBX_OFFSET); base 2782 drivers/scsi/myrs.c static inline unsigned short DAC960_BA_read_cmd_ident(void __iomem *base) base 2784 drivers/scsi/myrs.c return readw(base + DAC960_BA_CMDSTS_OFFSET); base 2787 drivers/scsi/myrs.c static inline unsigned char DAC960_BA_read_cmd_status(void __iomem *base) base 2789 drivers/scsi/myrs.c return readw(base + DAC960_BA_CMDSTS_OFFSET + 2); base 2793 drivers/scsi/myrs.c DAC960_BA_read_error_status(void __iomem *base, unsigned char *error, base 2798 drivers/scsi/myrs.c val = readb(base + DAC960_BA_ERRSTS_OFFSET); base 2803 drivers/scsi/myrs.c *param0 = readb(base + DAC960_BA_CMDMBX_OFFSET + 0); base 2804 drivers/scsi/myrs.c *param1 = readb(base + DAC960_BA_CMDMBX_OFFSET + 1); base 2805 drivers/scsi/myrs.c writeb(0xFF, base + DAC960_BA_ERRSTS_OFFSET); base 2810 drivers/scsi/myrs.c DAC960_BA_mbox_init(void __iomem *base, dma_addr_t mbox_addr) base 2814 drivers/scsi/myrs.c while (DAC960_BA_hw_mbox_is_full(base)) base 2816 drivers/scsi/myrs.c DAC960_BA_write_hw_mbox(base, mbox_addr); base 2817 drivers/scsi/myrs.c DAC960_BA_hw_mbox_new_cmd(base); base 2818 drivers/scsi/myrs.c while (!DAC960_BA_hw_mbox_status_available(base)) base 2820 drivers/scsi/myrs.c status = DAC960_BA_read_cmd_status(base); base 2821 drivers/scsi/myrs.c DAC960_BA_ack_hw_mbox_intr(base); base 2822 drivers/scsi/myrs.c DAC960_BA_ack_hw_mbox_status(base); base 2828 drivers/scsi/myrs.c struct myrs_hba *cs, void __iomem *base) base 2833 drivers/scsi/myrs.c DAC960_BA_disable_intr(base); base 2834 drivers/scsi/myrs.c DAC960_BA_ack_hw_mbox_status(base); base 2836 drivers/scsi/myrs.c while (DAC960_BA_init_in_progress(base) && base 2838 drivers/scsi/myrs.c if (DAC960_BA_read_error_status(base, &status, base 2853 drivers/scsi/myrs.c DAC960_BA_reset_ctrl(base); base 2856 drivers/scsi/myrs.c DAC960_BA_enable_intr(base); base 2867 drivers/scsi/myrs.c void __iomem *base = cs->io_base; base 2872 drivers/scsi/myrs.c DAC960_BA_ack_intr(base); base 2922 drivers/scsi/myrs.c static inline void DAC960_LP_hw_mbox_new_cmd(void __iomem *base) base 2924 drivers/scsi/myrs.c writeb(DAC960_LP_IDB_HWMBOX_NEW_CMD, base + DAC960_LP_IDB_OFFSET); base 2927 drivers/scsi/myrs.c static inline void DAC960_LP_ack_hw_mbox_status(void __iomem *base) base 2929 drivers/scsi/myrs.c writeb(DAC960_LP_IDB_HWMBOX_ACK_STS, base + DAC960_LP_IDB_OFFSET); base 2932 drivers/scsi/myrs.c static inline void DAC960_LP_gen_intr(void __iomem *base) base 2934 drivers/scsi/myrs.c writeb(DAC960_LP_IDB_GEN_IRQ, base + DAC960_LP_IDB_OFFSET); base 2937 drivers/scsi/myrs.c static inline void DAC960_LP_reset_ctrl(void __iomem *base) base 2939 drivers/scsi/myrs.c writeb(DAC960_LP_IDB_CTRL_RESET, base + DAC960_LP_IDB_OFFSET); base 2942 drivers/scsi/myrs.c static inline void DAC960_LP_mem_mbox_new_cmd(void __iomem *base) base 2944 drivers/scsi/myrs.c writeb(DAC960_LP_IDB_MMBOX_NEW_CMD, base + DAC960_LP_IDB_OFFSET); base 2947 drivers/scsi/myrs.c static inline bool DAC960_LP_hw_mbox_is_full(void __iomem *base) base 2951 drivers/scsi/myrs.c val = readb(base + DAC960_LP_IDB_OFFSET); base 2955 drivers/scsi/myrs.c static inline bool DAC960_LP_init_in_progress(void __iomem *base) base 2959 drivers/scsi/myrs.c val = readb(base + DAC960_LP_IDB_OFFSET); base 2963 drivers/scsi/myrs.c static inline void DAC960_LP_ack_hw_mbox_intr(void __iomem *base) base 2965 drivers/scsi/myrs.c writeb(DAC960_LP_ODB_HWMBOX_ACK_IRQ, base + DAC960_LP_ODB_OFFSET); base 2968 drivers/scsi/myrs.c static inline void DAC960_LP_ack_mem_mbox_intr(void __iomem *base) base 2970 drivers/scsi/myrs.c writeb(DAC960_LP_ODB_MMBOX_ACK_IRQ, base + DAC960_LP_ODB_OFFSET); base 2973 drivers/scsi/myrs.c static inline void DAC960_LP_ack_intr(void __iomem *base) base 2976 drivers/scsi/myrs.c base + DAC960_LP_ODB_OFFSET); base 2979 drivers/scsi/myrs.c static inline bool DAC960_LP_hw_mbox_status_available(void __iomem *base) base 2983 drivers/scsi/myrs.c val = readb(base + DAC960_LP_ODB_OFFSET); base 2987 drivers/scsi/myrs.c static inline bool DAC960_LP_mem_mbox_status_available(void __iomem *base) base 2991 drivers/scsi/myrs.c val = readb(base + DAC960_LP_ODB_OFFSET); base 2995 drivers/scsi/myrs.c static inline void DAC960_LP_enable_intr(void __iomem *base) base 2997 drivers/scsi/myrs.c writeb(~DAC960_LP_IRQMASK_DISABLE_IRQ, base + DAC960_LP_IRQMASK_OFFSET); base 3000 drivers/scsi/myrs.c static inline void DAC960_LP_disable_intr(void __iomem *base) base 3002 drivers/scsi/myrs.c writeb(0xFF, base + DAC960_LP_IRQMASK_OFFSET); base 3005 drivers/scsi/myrs.c static inline bool DAC960_LP_intr_enabled(void __iomem *base) base 3009 drivers/scsi/myrs.c val = readb(base + DAC960_LP_IRQMASK_OFFSET); base 3025 drivers/scsi/myrs.c static inline void DAC960_LP_write_hw_mbox(void __iomem *base, base 3028 drivers/scsi/myrs.c dma_addr_writeql(cmd_mbox_addr, base + DAC960_LP_CMDMBX_OFFSET); base 3031 drivers/scsi/myrs.c static inline unsigned short DAC960_LP_read_cmd_ident(void __iomem *base) base 3033 drivers/scsi/myrs.c return readw(base + DAC960_LP_CMDSTS_OFFSET); base 3036 drivers/scsi/myrs.c static inline unsigned char DAC960_LP_read_cmd_status(void __iomem *base) base 3038 drivers/scsi/myrs.c return readw(base + DAC960_LP_CMDSTS_OFFSET + 2); base 3042 drivers/scsi/myrs.c DAC960_LP_read_error_status(void __iomem *base, unsigned char *error, base 3047 drivers/scsi/myrs.c val = readb(base + DAC960_LP_ERRSTS_OFFSET); base 3052 drivers/scsi/myrs.c *param0 = readb(base + DAC960_LP_CMDMBX_OFFSET + 0); base 3053 drivers/scsi/myrs.c *param1 = readb(base + DAC960_LP_CMDMBX_OFFSET + 1); base 3054 drivers/scsi/myrs.c writeb(0xFF, base + DAC960_LP_ERRSTS_OFFSET); base 3059 drivers/scsi/myrs.c DAC960_LP_mbox_init(void __iomem *base, dma_addr_t mbox_addr) base 3063 drivers/scsi/myrs.c while (DAC960_LP_hw_mbox_is_full(base)) base 3065 drivers/scsi/myrs.c DAC960_LP_write_hw_mbox(base, mbox_addr); base 3066 drivers/scsi/myrs.c DAC960_LP_hw_mbox_new_cmd(base); base 3067 drivers/scsi/myrs.c while (!DAC960_LP_hw_mbox_status_available(base)) base 3069 drivers/scsi/myrs.c status = DAC960_LP_read_cmd_status(base); base 3070 drivers/scsi/myrs.c DAC960_LP_ack_hw_mbox_intr(base); base 3071 drivers/scsi/myrs.c DAC960_LP_ack_hw_mbox_status(base); base 3077 drivers/scsi/myrs.c struct myrs_hba *cs, void __iomem *base) base 3082 drivers/scsi/myrs.c DAC960_LP_disable_intr(base); base 3083 drivers/scsi/myrs.c DAC960_LP_ack_hw_mbox_status(base); base 3085 drivers/scsi/myrs.c while (DAC960_LP_init_in_progress(base) && base 3087 drivers/scsi/myrs.c if (DAC960_LP_read_error_status(base, &status, base 3102 drivers/scsi/myrs.c DAC960_LP_reset_ctrl(base); base 3105 drivers/scsi/myrs.c DAC960_LP_enable_intr(base); base 3117 drivers/scsi/myrs.c void __iomem *base = cs->io_base; base 3122 drivers/scsi/myrs.c DAC960_LP_ack_intr(base); base 920 drivers/scsi/myrs.h void (*get_cmd_mbox)(void __iomem *base); base 921 drivers/scsi/myrs.h void (*disable_intr)(void __iomem *base); base 922 drivers/scsi/myrs.h void (*reset)(void __iomem *base); base 951 drivers/scsi/myrs.h typedef unsigned char (*enable_mbox_t)(void __iomem *base, dma_addr_t addr); base 953 drivers/scsi/myrs.h struct myrs_hba *c, void __iomem *base); base 8355 drivers/scsi/ncr53c8xx.c np->paddr = device->slot.base; base 8392 drivers/scsi/ncr53c8xx.c instance->base = (unsigned long) np->reg; base 8394 drivers/scsi/ncr53c8xx.c instance->unique_id = device->slot.base; base 1281 drivers/scsi/ncr53c8xx.h u_long base; base 426 drivers/scsi/nsp32.c unsigned int base = SCpnt->host->io_port; base 434 drivers/scsi/nsp32.c nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK); base 445 drivers/scsi/nsp32.c unsigned int base = SCpnt->device->host->io_port; base 459 drivers/scsi/nsp32.c phase = nsp32_read1(base, SCSI_BUS_MONITOR); base 557 drivers/scsi/nsp32.c nsp32_write4(base, SGT_ADR, data->auto_paddr); base 558 drivers/scsi/nsp32.c nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER | base 564 drivers/scsi/nsp32.c ret = nsp32_arbitration(SCpnt, base); base 576 drivers/scsi/nsp32.c unsigned int base = SCpnt->device->host->io_port; base 591 drivers/scsi/nsp32.c nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); base 596 drivers/scsi/nsp32.c phase = nsp32_read1(base, SCSI_BUS_MONITOR); base 607 drivers/scsi/nsp32.c execph = nsp32_read2(base, SCSI_EXECUTE_PHASE); base 612 drivers/scsi/nsp32.c nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER); base 618 drivers/scsi/nsp32.c nsp32_write1(base, COMMAND_DATA, SCpnt->cmnd[i]); base 625 drivers/scsi/nsp32.c nsp32_write1(base, SCSI_OUT_LATCH_TARGET_ID, BIT(host_id) | BIT(target)); base 652 drivers/scsi/nsp32.c nsp32_write4(base, SCSI_MSG_OUT, msgout); base 655 drivers/scsi/nsp32.c nsp32_write4(base, SCSI_MSG_OUT, 0); base 661 drivers/scsi/nsp32.c nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME); base 669 drivers/scsi/nsp32.c nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg); base 674 drivers/scsi/nsp32.c nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR); base 680 drivers/scsi/nsp32.c nsp32_write1(base, SYNC_REG, data->cur_target->syncreg); base 685 drivers/scsi/nsp32.c nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth); base 689 drivers/scsi/nsp32.c nsp32_read1(base, SYNC_REG), nsp32_read1(base, ACK_WIDTH), base 690 drivers/scsi/nsp32.c nsp32_read4(base, SGT_ADR), nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID)); base 697 drivers/scsi/nsp32.c nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr); base 713 drivers/scsi/nsp32.c nsp32_write2(base, TRANSFER_CONTROL, command); base 723 drivers/scsi/nsp32.c nsp32_write2(base, COMMAND_CONTROL, command); base 728 drivers/scsi/nsp32.c status = nsp32_arbitration(SCpnt, base); base 734 drivers/scsi/nsp32.c nsp32_write2(base, IRQ_CONTROL, 0); base 748 drivers/scsi/nsp32.c static int nsp32_arbitration(struct scsi_cmnd *SCpnt, unsigned int base) base 755 drivers/scsi/nsp32.c arbit = nsp32_read1(base, ARBIT_STATUS); base 766 drivers/scsi/nsp32.c nsp32_index_write1(base, EXT_PORT, LED_ON); /* PCI LED on */ base 784 drivers/scsi/nsp32.c nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR); base 801 drivers/scsi/nsp32.c unsigned int base = SCpnt->device->host->io_port; base 809 drivers/scsi/nsp32.c tmpid = nsp32_read1(base, RESELECT_ID); base 839 drivers/scsi/nsp32.c nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK); base 1043 drivers/scsi/nsp32.c unsigned int base = data->BaseAddress; base 1048 drivers/scsi/nsp32.c lc_reg = nsp32_index_read4(base, CFG_LATE_CACHE); base 1051 drivers/scsi/nsp32.c nsp32_index_write2(base, CFG_LATE_CACHE, lc_reg & 0xffff); base 1054 drivers/scsi/nsp32.c nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); base 1055 drivers/scsi/nsp32.c nsp32_write2(base, TRANSFER_CONTROL, 0); base 1056 drivers/scsi/nsp32.c nsp32_write4(base, BM_CNT, 0); base 1057 drivers/scsi/nsp32.c nsp32_write2(base, SCSI_EXECUTE_PHASE, 0); base 1060 drivers/scsi/nsp32.c irq_stat = nsp32_read2(base, IRQ_STATUS); base 1070 drivers/scsi/nsp32.c nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x40); base 1071 drivers/scsi/nsp32.c nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x40); base 1073 drivers/scsi/nsp32.c nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x10); base 1074 drivers/scsi/nsp32.c nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x60); base 1080 drivers/scsi/nsp32.c nsp32_index_read1(base, FIFO_FULL_SHLD_COUNT), base 1081 drivers/scsi/nsp32.c nsp32_index_read1(base, FIFO_EMPTY_SHLD_COUNT)); base 1083 drivers/scsi/nsp32.c nsp32_index_write1(base, CLOCK_DIV, data->clock); base 1084 drivers/scsi/nsp32.c nsp32_index_write1(base, BM_CYCLE, MEMRD_CMD1 | SGT_AUTO_PARA_MEMED_CMD); base 1085 drivers/scsi/nsp32.c nsp32_write1(base, PARITY_CONTROL, 0); /* parity check is disable */ base 1102 drivers/scsi/nsp32.c nsp32_index_write2(base, MISC_WR, base 1110 drivers/scsi/nsp32.c nsp32_index_write1(base, TERM_PWR_CONTROL, 0); base 1111 drivers/scsi/nsp32.c power = nsp32_index_read1(base, TERM_PWR_CONTROL); base 1114 drivers/scsi/nsp32.c nsp32_index_write1(base, TERM_PWR_CONTROL, BPWR); base 1117 drivers/scsi/nsp32.c nsp32_write2(base, TIMER_SET, TIMER_STOP); base 1118 drivers/scsi/nsp32.c nsp32_write2(base, TIMER_SET, TIMER_STOP); /* Required 2 times */ base 1120 drivers/scsi/nsp32.c nsp32_write1(base, SYNC_REG, 0); base 1121 drivers/scsi/nsp32.c nsp32_write1(base, ACK_WIDTH, 0); base 1122 drivers/scsi/nsp32.c nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME); base 1128 drivers/scsi/nsp32.c nsp32_index_write2(base, IRQ_SELECT, IRQSELECT_TIMER_IRQ | base 1137 drivers/scsi/nsp32.c nsp32_write2(base, IRQ_CONTROL, 0); base 1140 drivers/scsi/nsp32.c nsp32_index_write1(base, EXT_PORT_DDR, LED_OFF); base 1141 drivers/scsi/nsp32.c nsp32_index_write1(base, EXT_PORT, LED_OFF); base 1151 drivers/scsi/nsp32.c unsigned int base = data->BaseAddress; base 1165 drivers/scsi/nsp32.c irq_stat = nsp32_read2(base, IRQ_STATUS); base 1174 drivers/scsi/nsp32.c nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); base 1176 drivers/scsi/nsp32.c busmon = nsp32_read1(base, SCSI_BUS_MONITOR); base 1179 drivers/scsi/nsp32.c trans_stat = nsp32_read2(base, TRANSFER_STATUS); base 1193 drivers/scsi/nsp32.c nsp32_write2(base, TIMER_SET, TIMER_STOP); base 1222 drivers/scsi/nsp32.c auto_stat = nsp32_read2(base, SCSI_EXECUTE_PHASE); base 1223 drivers/scsi/nsp32.c nsp32_write2(base, SCSI_EXECUTE_PHASE, 0); base 1257 drivers/scsi/nsp32.c ((nsp32_read2(base, FIFO_REST_CNT) & FIFO_REST_MASK) != 0)) { base 1269 drivers/scsi/nsp32.c nsp32_read4(base, BM_CNT)); base 1271 drivers/scsi/nsp32.c nsp32_read4(base, SGT_ADR)); base 1273 drivers/scsi/nsp32.c nsp32_read4(base, SACK_CNT)); base 1275 drivers/scsi/nsp32.c nsp32_read4(base, SAVED_SACK_CNT)); base 1312 drivers/scsi/nsp32.c SCpnt->result = (int)nsp32_read1(base, SCSI_CSB_IN); base 1365 drivers/scsi/nsp32.c SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN); base 1421 drivers/scsi/nsp32.c nsp32_write2(base, IRQ_CONTROL, 0); base 1437 drivers/scsi/nsp32.c unsigned int base; base 1444 drivers/scsi/nsp32.c base = host->io_port; base 1451 drivers/scsi/nsp32.c seq_printf(m, "MMIO(virtual address): 0x%lx-0x%lx\n", host->base, host->base + data->MmioLength - 1); base 1453 drivers/scsi/nsp32.c seq_printf(m, "Chip revision: 0x%x\n", (nsp32_read2(base, INDEX_REG) >> 8) & 0xff); base 1455 drivers/scsi/nsp32.c mode_reg = nsp32_index_read1(base, CHIP_MODE); base 1513 drivers/scsi/nsp32.c unsigned int base = SCpnt->device->host->io_port; base 1520 drivers/scsi/nsp32.c nsp32_write2(base, TRANSFER_CONTROL, 0); base 1521 drivers/scsi/nsp32.c nsp32_write4(base, BM_CNT, 0); base 1551 drivers/scsi/nsp32.c unsigned int base = SCpnt->device->host->io_port; base 1556 drivers/scsi/nsp32.c nsp32_write4(base, BM_CNT, 0); base 1557 drivers/scsi/nsp32.c nsp32_write2(base, TRANSFER_CONTROL, 0); base 1584 drivers/scsi/nsp32.c sacklen = nsp32_read4(base, SACK_CNT ); base 1585 drivers/scsi/nsp32.c s_sacklen = nsp32_read4(base, SAVED_SACK_CNT); base 1668 drivers/scsi/nsp32.c SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN); base 1681 drivers/scsi/nsp32.c SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN); base 1782 drivers/scsi/nsp32.c unsigned int base = SCpnt->device->host->io_port; base 1826 drivers/scsi/nsp32.c nsp32_write2(base, COMMAND_CONTROL, base 1837 drivers/scsi/nsp32.c nsp32_write1(base, SCSI_DATA_WITH_ACK, data->msgoutbuf[i]); base 1841 drivers/scsi/nsp32.c nsp32_read1(base, SCSI_BUS_MONITOR)); base 1858 drivers/scsi/nsp32.c unsigned int base = data->BaseAddress; base 1871 drivers/scsi/nsp32.c nsp32_write1(base, SYNC_REG, data->cur_target->syncreg); base 1876 drivers/scsi/nsp32.c nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth); base 1881 drivers/scsi/nsp32.c nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg); base 1886 drivers/scsi/nsp32.c nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr); base 1902 drivers/scsi/nsp32.c nsp32_write2(base, TRANSFER_CONTROL, transfer); base 1912 drivers/scsi/nsp32.c nsp32_write2(base, COMMAND_CONTROL, command); base 1926 drivers/scsi/nsp32.c unsigned int base = SCpnt->device->host->io_port; base 1940 drivers/scsi/nsp32.c msg = nsp32_read1(base, SCSI_DATA_IN); base 2001 drivers/scsi/nsp32.c s_sacklen = nsp32_read4(base, SAVED_SACK_CNT); base 2013 drivers/scsi/nsp32.c nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK); base 2020 drivers/scsi/nsp32.c nsp32_write4(base, SGT_ADR, new_sgtp); base 2164 drivers/scsi/nsp32.c nsp32_write4(base, SCSI_MSG_OUT, 0); base 2455 drivers/scsi/nsp32.c unsigned int base = data->BaseAddress; base 2466 drivers/scsi/nsp32.c bus = nsp32_read1(base, SCSI_BUS_MONITOR); base 2484 drivers/scsi/nsp32.c unsigned int base = data->BaseAddress; base 2495 drivers/scsi/nsp32.c bus = nsp32_read1(base, SCSI_BUS_MONITOR); base 2515 drivers/scsi/nsp32.c unsigned int base = data->BaseAddress; base 2518 drivers/scsi/nsp32.c busctrl = nsp32_read1(base, SCSI_BUS_CONTROL); base 2520 drivers/scsi/nsp32.c nsp32_write1(base, SCSI_BUS_CONTROL, busctrl); base 2528 drivers/scsi/nsp32.c unsigned int base = data->BaseAddress; base 2531 drivers/scsi/nsp32.c busctrl = nsp32_read1(base, SCSI_BUS_CONTROL); base 2533 drivers/scsi/nsp32.c nsp32_write1(base, SCSI_BUS_CONTROL, busctrl); base 2575 drivers/scsi/nsp32.c host->base = (unsigned long)data->MmioAddress; base 2812 drivers/scsi/nsp32.c unsigned int base = SCpnt->device->host->io_port; base 2827 drivers/scsi/nsp32.c nsp32_write2(base, TRANSFER_CONTROL, 0); base 2828 drivers/scsi/nsp32.c nsp32_write2(base, BM_CNT, 0); base 2839 drivers/scsi/nsp32.c unsigned int base = data->BaseAddress; base 2850 drivers/scsi/nsp32.c nsp32_write2(base, TRANSFER_CONTROL, 0); base 2851 drivers/scsi/nsp32.c nsp32_write4(base, BM_CNT, 0); base 2852 drivers/scsi/nsp32.c nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK); base 2868 drivers/scsi/nsp32.c nsp32_write1(base, SCSI_BUS_CONTROL, BUSCTL_RST); base 2870 drivers/scsi/nsp32.c nsp32_write1(base, SCSI_BUS_CONTROL, 0); base 2872 drivers/scsi/nsp32.c intrdat = nsp32_read2(base, IRQ_STATUS); /* dummy read */ base 2882 drivers/scsi/nsp32.c unsigned int base = SCpnt->device->host->io_port; base 2891 drivers/scsi/nsp32.c nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); base 2893 drivers/scsi/nsp32.c nsp32_write2(base, IRQ_CONTROL, 0); base 3185 drivers/scsi/nsp32.c int base = data->BaseAddress; base 3188 drivers/scsi/nsp32.c tmp = nsp32_index_read1(base, SERIAL_ROM_CTL); base 3196 drivers/scsi/nsp32.c nsp32_index_write1(base, SERIAL_ROM_CTL, tmp); base 3203 drivers/scsi/nsp32.c int base = data->BaseAddress; base 3212 drivers/scsi/nsp32.c tmp = nsp32_index_read1(base, SERIAL_ROM_CTL) & bit; base 228 drivers/scsi/nsp32_debug.c static void nsp32_print_register(int base) base 233 drivers/scsi/nsp32_debug.c printk("Phase=0x%x, ", nsp32_read1(base, SCSI_BUS_MONITOR)); base 234 drivers/scsi/nsp32_debug.c printk("OldPhase=0x%x, ", nsp32_index_read1(base, OLD_SCSI_PHASE)); base 235 drivers/scsi/nsp32_debug.c printk("syncreg=0x%x, ", nsp32_read1(base, SYNC_REG)); base 236 drivers/scsi/nsp32_debug.c printk("ackwidth=0x%x, ", nsp32_read1(base, ACK_WIDTH)); base 237 drivers/scsi/nsp32_debug.c printk("sgtpaddr=0x%lx, ", nsp32_read4(base, SGT_ADR)); base 238 drivers/scsi/nsp32_debug.c printk("scsioutlatch=0x%x, ", nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID)); base 239 drivers/scsi/nsp32_debug.c printk("msgout=0x%lx, ", nsp32_read4(base, SCSI_MSG_OUT)); base 240 drivers/scsi/nsp32_debug.c printk("miscrd=0x%x, ", nsp32_index_read2(base, MISC_WR)); base 241 drivers/scsi/nsp32_debug.c printk("seltimeout=0x%x, ", nsp32_read2(base, SEL_TIME_OUT)); base 242 drivers/scsi/nsp32_debug.c printk("sreqrate=0x%x, ", nsp32_read1(base, SREQ_SMPL_RATE)); base 243 drivers/scsi/nsp32_debug.c printk("transStatus=0x%x, ", nsp32_read2(base, TRANSFER_STATUS)); base 244 drivers/scsi/nsp32_debug.c printk("reselectid=0x%x, ", nsp32_read2(base, COMMAND_CONTROL)); base 245 drivers/scsi/nsp32_debug.c printk("arbit=0x%x, ", nsp32_read1(base, ARBIT_STATUS)); base 246 drivers/scsi/nsp32_debug.c printk("BmStart=0x%lx, ", nsp32_read4(base, BM_START_ADR)); base 247 drivers/scsi/nsp32_debug.c printk("BmCount=0x%lx, ", nsp32_read4(base, BM_CNT)); base 248 drivers/scsi/nsp32_debug.c printk("SackCnt=0x%lx, ", nsp32_read4(base, SACK_CNT)); base 249 drivers/scsi/nsp32_debug.c printk("SReqCnt=0x%lx, ", nsp32_read4(base, SREQ_CNT)); base 250 drivers/scsi/nsp32_debug.c printk("SavedSackCnt=0x%lx, ", nsp32_read4(base, SAVED_SACK_CNT)); base 251 drivers/scsi/nsp32_debug.c printk("ScsiBusControl=0x%x, ", nsp32_read1(base, SCSI_BUS_CONTROL)); base 252 drivers/scsi/nsp32_debug.c printk("FifoRestCnt=0x%x, ", nsp32_read2(base, FIFO_REST_CNT)); base 253 drivers/scsi/nsp32_debug.c printk("CdbIn=0x%x, ", nsp32_read1(base, SCSI_CSB_IN)); base 257 drivers/scsi/nsp32_debug.c printk("execph=0x%x, ", nsp32_read2(base, SCSI_EXECUTE_PHASE)); base 258 drivers/scsi/nsp32_debug.c printk("IrqStatus=0x%x, ", nsp32_read2(base, IRQ_STATUS)); base 12 drivers/scsi/nsp32_io.h static inline void nsp32_write1(unsigned int base, base 16 drivers/scsi/nsp32_io.h outb(val, (base + index)); base 19 drivers/scsi/nsp32_io.h static inline unsigned char nsp32_read1(unsigned int base, base 22 drivers/scsi/nsp32_io.h return inb(base + index); base 25 drivers/scsi/nsp32_io.h static inline void nsp32_write2(unsigned int base, base 29 drivers/scsi/nsp32_io.h outw(val, (base + index)); base 32 drivers/scsi/nsp32_io.h static inline unsigned short nsp32_read2(unsigned int base, base 35 drivers/scsi/nsp32_io.h return inw(base + index); base 38 drivers/scsi/nsp32_io.h static inline void nsp32_write4(unsigned int base, base 42 drivers/scsi/nsp32_io.h outl(val, (base + index)); base 45 drivers/scsi/nsp32_io.h static inline unsigned long nsp32_read4(unsigned int base, base 48 drivers/scsi/nsp32_io.h return inl(base + index); base 53 drivers/scsi/nsp32_io.h static inline void nsp32_mmio_write1(unsigned long base, base 59 drivers/scsi/nsp32_io.h ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index); base 64 drivers/scsi/nsp32_io.h static inline unsigned char nsp32_mmio_read1(unsigned long base, base 69 drivers/scsi/nsp32_io.h ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index); base 74 drivers/scsi/nsp32_io.h static inline void nsp32_mmio_write2(unsigned long base, base 80 drivers/scsi/nsp32_io.h ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index); base 85 drivers/scsi/nsp32_io.h static inline unsigned short nsp32_mmio_read2(unsigned long base, base 90 drivers/scsi/nsp32_io.h ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index); base 95 drivers/scsi/nsp32_io.h static inline void nsp32_mmio_write4(unsigned long base, base 101 drivers/scsi/nsp32_io.h ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index); base 106 drivers/scsi/nsp32_io.h static inline unsigned long nsp32_mmio_read4(unsigned long base, base 111 drivers/scsi/nsp32_io.h ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index); base 118 drivers/scsi/nsp32_io.h static inline unsigned char nsp32_index_read1(unsigned int base, base 121 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG); base 122 drivers/scsi/nsp32_io.h return inb(base + DATA_REG_LOW); base 125 drivers/scsi/nsp32_io.h static inline void nsp32_index_write1(unsigned int base, base 129 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG ); base 130 drivers/scsi/nsp32_io.h outb(val, base + DATA_REG_LOW); base 133 drivers/scsi/nsp32_io.h static inline unsigned short nsp32_index_read2(unsigned int base, base 136 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG); base 137 drivers/scsi/nsp32_io.h return inw(base + DATA_REG_LOW); base 140 drivers/scsi/nsp32_io.h static inline void nsp32_index_write2(unsigned int base, base 144 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG ); base 145 drivers/scsi/nsp32_io.h outw(val, base + DATA_REG_LOW); base 148 drivers/scsi/nsp32_io.h static inline unsigned long nsp32_index_read4(unsigned int base, base 153 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG); base 154 drivers/scsi/nsp32_io.h l = inw(base + DATA_REG_LOW); base 155 drivers/scsi/nsp32_io.h h = inw(base + DATA_REG_HI ); base 160 drivers/scsi/nsp32_io.h static inline void nsp32_index_write4(unsigned int base, base 169 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG ); base 170 drivers/scsi/nsp32_io.h outw(l, base + DATA_REG_LOW); base 171 drivers/scsi/nsp32_io.h outw(h, base + DATA_REG_HI ); base 176 drivers/scsi/nsp32_io.h static inline unsigned char nsp32_mmio_index_read1(unsigned long base, base 181 drivers/scsi/nsp32_io.h index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); base 182 drivers/scsi/nsp32_io.h data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); base 188 drivers/scsi/nsp32_io.h static inline void nsp32_mmio_index_write1(unsigned long base, base 194 drivers/scsi/nsp32_io.h index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); base 195 drivers/scsi/nsp32_io.h data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); base 201 drivers/scsi/nsp32_io.h static inline unsigned short nsp32_mmio_index_read2(unsigned long base, base 206 drivers/scsi/nsp32_io.h index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); base 207 drivers/scsi/nsp32_io.h data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); base 213 drivers/scsi/nsp32_io.h static inline void nsp32_mmio_index_write2(unsigned long base, base 219 drivers/scsi/nsp32_io.h index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG); base 220 drivers/scsi/nsp32_io.h data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW); base 228 drivers/scsi/nsp32_io.h static inline void nsp32_multi_read4(unsigned int base, base 233 drivers/scsi/nsp32_io.h insl(base + reg, buf, count); base 236 drivers/scsi/nsp32_io.h static inline void nsp32_fifo_read(unsigned int base, base 240 drivers/scsi/nsp32_io.h nsp32_multi_read4(base, FIFO_DATA_LOW, buf, count); base 243 drivers/scsi/nsp32_io.h static inline void nsp32_multi_write4(unsigned int base, base 248 drivers/scsi/nsp32_io.h outsl(base + reg, buf, count); base 251 drivers/scsi/nsp32_io.h static inline void nsp32_fifo_write(unsigned int base, base 255 drivers/scsi/nsp32_io.h nsp32_multi_write4(base, FIFO_DATA_LOW, buf, count); base 273 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = data->BaseAddress; base 286 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, TRANSFERMODE, transfer_mode_reg); base 308 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = data->BaseAddress; base 310 drivers/scsi/pcmcia/nsp_cs.c nsp_dbg(NSP_DEBUG_INIT, "in base=0x%x", base); base 320 drivers/scsi/pcmcia/nsp_cs.c nsp_write(base, IRQCONTROL, IRQCONTROL_ALLMASK); base 323 drivers/scsi/pcmcia/nsp_cs.c nsp_write(base, IFSELECT, IF_IFSEL); base 325 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIIRQMODE, 0); base 327 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, TRANSFERMODE, MODE_IO8); base 328 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, CLOCKDIV, data->ScsiClockDiv); base 330 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, PARITYCTRL, 0); base 331 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, POINTERCLR, POINTER_CLEAR | base 337 drivers/scsi/pcmcia/nsp_cs.c nsp_write(base, IFSELECT, IF_REGSEL); base 338 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, TERMPWRCTRL, 0); base 339 drivers/scsi/pcmcia/nsp_cs.c if ((nsp_index_read(base, OTHERCONTROL) & TPWR_SENSE) == 0) { base 341 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, TERMPWRCTRL, POWER_ON); base 344 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, TIMERCOUNT, 0); base 345 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, TIMERCOUNT, 0); /* requires 2 times!! */ base 347 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SYNCREG, 0); base 348 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, ACKWIDTH, 0); base 351 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIIRQMODE, SCSI_PHASE_CHANGE_EI | base 354 drivers/scsi/pcmcia/nsp_cs.c nsp_write(base, IRQCONTROL, IRQCONTROL_ALLCLEAR); base 367 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = SCpnt->device->host->io_port; base 375 drivers/scsi/pcmcia/nsp_cs.c phase = nsp_index_read(base, SCSIBUSMON); base 384 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SETARBIT, ARBIT_GO); base 389 drivers/scsi/pcmcia/nsp_cs.c arbit = nsp_index_read(base, ARBITSTATUS); base 397 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SETARBIT, ARBIT_FLAG_CLEAR); base 405 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIDATALATCH, BIT(host_id) | BIT(target)); base 406 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIBUSCTRL, SCSI_SEL | SCSI_BSY | SCSI_ATN); base 408 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIBUSCTRL, SCSI_SEL | SCSI_BSY | SCSI_DATAOUT_ENB | SCSI_ATN); base 409 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SETARBIT, ARBIT_FLAG_CLEAR); base 411 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIBUSCTRL, SCSI_SEL | SCSI_DATAOUT_ENB | SCSI_ATN); base 505 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = SCpnt->device->host->io_port; base 510 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, TIMERCOUNT, time); base 519 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = SCpnt->device->host->io_port; base 528 drivers/scsi/pcmcia/nsp_cs.c reg = nsp_index_read(base, SCSIBUSMON); base 548 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = SCpnt->device->host->io_port; base 556 drivers/scsi/pcmcia/nsp_cs.c phase = nsp_index_read(base, SCSIBUSMON); base 561 drivers/scsi/pcmcia/nsp_cs.c i_src = nsp_read(base, IRQSTATUS); base 581 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = SCpnt->device->host->io_port; base 599 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIBUSCTRL, AUTODIRECTION | ACKENB); base 605 drivers/scsi/pcmcia/nsp_cs.c buf[ptr] = nsp_index_read(base, SCSIDATAWITHACK); base 608 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIDATAWITHACK, buf[ptr]); base 653 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = SCpnt->device->host->io_port; base 662 drivers/scsi/pcmcia/nsp_cs.c id_reg = nsp_index_read(base, RESELECTID); base 680 drivers/scsi/pcmcia/nsp_cs.c bus_reg = nsp_index_read(base, SCSIBUSCTRL) & ~(SCSI_BSY | SCSI_ATN); base 681 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIBUSCTRL, bus_reg); base 682 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIBUSCTRL, bus_reg | AUTODIRECTION | ACKENB); base 692 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = SCpnt->device->host->io_port; base 696 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, POINTERCLR, POINTER_CLEAR | ACK_COUNTER); base 698 drivers/scsi/pcmcia/nsp_cs.c l = nsp_index_read(base, TRANSFERCOUNT); base 699 drivers/scsi/pcmcia/nsp_cs.c m = nsp_index_read(base, TRANSFERCOUNT); base 700 drivers/scsi/pcmcia/nsp_cs.c h = nsp_index_read(base, TRANSFERCOUNT); base 701 drivers/scsi/pcmcia/nsp_cs.c dummy = nsp_index_read(base, TRANSFERCOUNT); /* required this! */ base 719 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = SCpnt->device->host->io_port; base 720 drivers/scsi/pcmcia/nsp_cs.c unsigned long mmio_base = SCpnt->device->host->base; base 738 drivers/scsi/pcmcia/nsp_cs.c stat = nsp_index_read(base, SCSIBUSMON); base 754 drivers/scsi/pcmcia/nsp_cs.c fifo_stat = nsp_read(base, FIFOSTATUS); base 765 drivers/scsi/pcmcia/nsp_cs.c nsp_fifo32_read(base, SCpnt->SCp.ptr, res >> 2); base 768 drivers/scsi/pcmcia/nsp_cs.c nsp_fifo8_read (base, SCpnt->SCp.ptr, res ); base 818 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = SCpnt->device->host->io_port; base 819 drivers/scsi/pcmcia/nsp_cs.c unsigned long mmio_base = SCpnt->device->host->base; base 836 drivers/scsi/pcmcia/nsp_cs.c stat = nsp_index_read(base, SCSIBUSMON); base 864 drivers/scsi/pcmcia/nsp_cs.c nsp_fifo32_write(base, SCpnt->SCp.ptr, res >> 2); base 867 drivers/scsi/pcmcia/nsp_cs.c nsp_fifo8_write (base, SCpnt->SCp.ptr, res ); base 915 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = SCpnt->device->host->io_port; base 924 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SYNCREG, sync->SyncRegister); base 925 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, ACKWIDTH, sync->AckWidth); base 943 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, POINTERCLR, POINTER_CLEAR | base 957 drivers/scsi/pcmcia/nsp_cs.c unsigned int base; base 981 drivers/scsi/pcmcia/nsp_cs.c base = data->BaseAddress; base 987 drivers/scsi/pcmcia/nsp_cs.c nsp_write(base, IRQCONTROL, IRQCONTROL_IRQDISABLE); base 988 drivers/scsi/pcmcia/nsp_cs.c irq_status = nsp_read(base, IRQSTATUS); base 991 drivers/scsi/pcmcia/nsp_cs.c nsp_write(base, IRQCONTROL, 0); base 1000 drivers/scsi/pcmcia/nsp_cs.c phase = nsp_index_read(base, SCSIBUSMON); base 1002 drivers/scsi/pcmcia/nsp_cs.c irq_phase = nsp_index_read(base, IRQPHASESENCE); base 1015 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, TIMERCOUNT, 0); base 1016 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, TIMERCOUNT, 0); base 1023 drivers/scsi/pcmcia/nsp_cs.c nsp_write(base, IRQCONTROL, IRQCONTROL_TIMER_CLEAR); base 1027 drivers/scsi/pcmcia/nsp_cs.c nsp_write(base, IRQCONTROL, IRQCONTROL_TIMER_CLEAR | IRQCONTROL_FIFO_CLEAR); base 1064 drivers/scsi/pcmcia/nsp_cs.c nsp_write(base, IRQCONTROL, IRQCONTROL_RESELECT_CLEAR); base 1085 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIBUSCTRL, 0); base 1101 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIBUSCTRL, SCSI_ATN); base 1103 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIBUSCTRL, SCSI_ATN | AUTODIRECTION | ACKENB); base 1176 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, COMMANDCTRL, CLEAR_COMMAND_POINTER); base 1178 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, COMMANDDATA, tmpSC->cmnd[i]); base 1180 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, COMMANDCTRL, CLEAR_COMMAND_POINTER | AUTO_COMMAND_GO); base 1209 drivers/scsi/pcmcia/nsp_cs.c tmpSC->SCp.Status = nsp_index_read(base, SCSIDATAWITHACK); base 1339 drivers/scsi/pcmcia/nsp_cs.c host->base = data->MmioAddress; base 1347 drivers/scsi/pcmcia/nsp_cs.c host->base, base 1383 drivers/scsi/pcmcia/nsp_cs.c seq_printf(m, "MMIO(virtual address): 0x%lx-0x%lx\n", host->base, host->base + data->MmioLength - 1); base 1461 drivers/scsi/pcmcia/nsp_cs.c unsigned int base = data->BaseAddress; base 1464 drivers/scsi/pcmcia/nsp_cs.c nsp_write(base, IRQCONTROL, IRQCONTROL_ALLMASK); base 1466 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIBUSCTRL, SCSI_RST); base 1468 drivers/scsi/pcmcia/nsp_cs.c nsp_index_write(base, SCSIBUSCTRL, 0); base 1470 drivers/scsi/pcmcia/nsp_cs.c nsp_index_read(base, IRQPHASESENCE); /* dummy read */ base 1475 drivers/scsi/pcmcia/nsp_cs.c nsp_write(base, IRQCONTROL, IRQCONTROL_ALLCLEAR); base 15 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_write(unsigned int base, base 18 drivers/scsi/pcmcia/nsp_io.h static inline unsigned char nsp_read(unsigned int base, base 30 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_write(unsigned int base, base 34 drivers/scsi/pcmcia/nsp_io.h outb(val, (base + index)); base 37 drivers/scsi/pcmcia/nsp_io.h static inline unsigned char nsp_read(unsigned int base, base 40 drivers/scsi/pcmcia/nsp_io.h return inb(base + index); base 75 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_fifo8_read(unsigned int base, base 80 drivers/scsi/pcmcia/nsp_io.h nsp_multi_read_1(base, FIFODATA, buf, count); base 94 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_fifo16_read(unsigned int base, base 99 drivers/scsi/pcmcia/nsp_io.h nsp_multi_read_2(base, FIFODATA, buf, count); base 113 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_fifo32_read(unsigned int base, base 118 drivers/scsi/pcmcia/nsp_io.h nsp_multi_read_4(base, FIFODATA, buf, count); base 132 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_fifo8_write(unsigned int base, base 136 drivers/scsi/pcmcia/nsp_io.h nsp_multi_write_1(base, FIFODATA, buf, count); base 150 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_fifo16_write(unsigned int base, base 154 drivers/scsi/pcmcia/nsp_io.h nsp_multi_write_2(base, FIFODATA, buf, count); base 168 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_fifo32_write(unsigned int base, base 172 drivers/scsi/pcmcia/nsp_io.h nsp_multi_write_4(base, FIFODATA, buf, count); base 178 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_mmio_write(unsigned long base, base 182 drivers/scsi/pcmcia/nsp_io.h unsigned char *ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + index); base 187 drivers/scsi/pcmcia/nsp_io.h static inline unsigned char nsp_mmio_read(unsigned long base, base 190 drivers/scsi/pcmcia/nsp_io.h unsigned char *ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + index); base 197 drivers/scsi/pcmcia/nsp_io.h static inline unsigned char nsp_mmio_index_read(unsigned long base, base 200 drivers/scsi/pcmcia/nsp_io.h unsigned char *index_ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + INDEXREG); base 201 drivers/scsi/pcmcia/nsp_io.h unsigned char *data_ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + DATAREG); base 207 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_mmio_index_write(unsigned long base, base 211 drivers/scsi/pcmcia/nsp_io.h unsigned char *index_ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + INDEXREG); base 212 drivers/scsi/pcmcia/nsp_io.h unsigned char *data_ptr = (unsigned char *)(base + NSP_MMIO_OFFSET + DATAREG); base 219 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_mmio_multi_read_4(unsigned long base, base 224 drivers/scsi/pcmcia/nsp_io.h unsigned long *ptr = (unsigned long *)(base + Register); base 237 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_mmio_fifo32_read(unsigned int base, base 242 drivers/scsi/pcmcia/nsp_io.h nsp_mmio_multi_read_4(base, FIFODATA, buf, count); base 245 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_mmio_multi_write_4(unsigned long base, base 250 drivers/scsi/pcmcia/nsp_io.h unsigned long *ptr = (unsigned long *)(base + Register); base 263 drivers/scsi/pcmcia/nsp_io.h static inline void nsp_mmio_fifo32_write(unsigned int base, base 268 drivers/scsi/pcmcia/nsp_io.h nsp_mmio_multi_write_4(base, FIFODATA, buf, count); base 13 drivers/scsi/pcmcia/nsp_message.c unsigned int base = SCpnt->device->host->io_port; base 30 drivers/scsi/pcmcia/nsp_message.c data_reg = nsp_index_read(base, SCSIDATAIN); base 33 drivers/scsi/pcmcia/nsp_message.c control_reg = nsp_index_read(base, SCSIBUSCTRL); base 35 drivers/scsi/pcmcia/nsp_message.c nsp_index_write(base, SCSIBUSCTRL, control_reg); base 41 drivers/scsi/pcmcia/nsp_message.c control_reg = nsp_index_read(base, SCSIBUSCTRL); base 43 drivers/scsi/pcmcia/nsp_message.c nsp_index_write(base, SCSIBUSCTRL, control_reg); base 236 drivers/scsi/pcmcia/sym53c500_cs.c SYM53C500_pio_read(int fast_pio, int base, unsigned char *request, unsigned int reqlen) base 241 drivers/scsi/pcmcia/sym53c500_cs.c REG1(base); base 243 drivers/scsi/pcmcia/sym53c500_cs.c i = inb(base + PIO_STATUS); base 276 drivers/scsi/pcmcia/sym53c500_cs.c insl(base + PIO_FIFO, request, len >> 2); base 281 drivers/scsi/pcmcia/sym53c500_cs.c *request++ = inb(base + PIO_FIFO); base 291 drivers/scsi/pcmcia/sym53c500_cs.c SYM53C500_pio_write(int fast_pio, int base, unsigned char *request, unsigned int reqlen) base 296 drivers/scsi/pcmcia/sym53c500_cs.c REG1(base); base 298 drivers/scsi/pcmcia/sym53c500_cs.c i = inb(base + PIO_STATUS); base 327 drivers/scsi/pcmcia/sym53c500_cs.c outsl(base + PIO_FIFO, request, len >> 2); base 332 drivers/scsi/pcmcia/sym53c500_cs.c outb(*request++, base + PIO_FIFO); base 28 drivers/scsi/ppa.c static void ppa_reset_pulse(unsigned int base); base 32 drivers/scsi/ppa.c int base; /* Actual port address */ base 57 drivers/scsi/ppa.c dev->base = dev->dev->port->base; base 182 drivers/scsi/ppa.c unsigned short ppb = dev->base; base 240 drivers/scsi/ppa.c static int ppa_byte_out(unsigned short base, const char *buffer, int len) base 245 drivers/scsi/ppa.c w_dtr(base, *buffer++); base 246 drivers/scsi/ppa.c w_ctr(base, 0xe); base 247 drivers/scsi/ppa.c w_ctr(base, 0xc); base 252 drivers/scsi/ppa.c static int ppa_byte_in(unsigned short base, char *buffer, int len) base 257 drivers/scsi/ppa.c *buffer++ = r_dtr(base); base 258 drivers/scsi/ppa.c w_ctr(base, 0x27); base 259 drivers/scsi/ppa.c w_ctr(base, 0x25); base 264 drivers/scsi/ppa.c static int ppa_nibble_in(unsigned short base, char *buffer, int len) base 269 drivers/scsi/ppa.c w_ctr(base, 0x4); base 270 drivers/scsi/ppa.c h = r_str(base) & 0xf0; base 271 drivers/scsi/ppa.c w_ctr(base, 0x6); base 272 drivers/scsi/ppa.c *buffer++ = h | ((r_str(base) & 0xf0) >> 4); base 280 drivers/scsi/ppa.c unsigned short ppb = dev->base; base 325 drivers/scsi/ppa.c unsigned short ppb = dev->base; base 389 drivers/scsi/ppa.c unsigned short ppb = dev->base; base 408 drivers/scsi/ppa.c unsigned short ppb = dev->base; base 422 drivers/scsi/ppa.c unsigned short ppb = dev->base; base 466 drivers/scsi/ppa.c unsigned short ppb = dev->base; base 498 drivers/scsi/ppa.c w_ctr(dev->base, 0x0c); base 522 drivers/scsi/ppa.c unsigned short ppb = dev->base; base 673 drivers/scsi/ppa.c unsigned short ppb = dev->base; base 857 drivers/scsi/ppa.c static void ppa_reset_pulse(unsigned int base) base 859 drivers/scsi/ppa.c w_dtr(base, 0x40); base 860 drivers/scsi/ppa.c w_ctr(base, 0x8); base 862 drivers/scsi/ppa.c w_ctr(base, 0xc); base 874 drivers/scsi/ppa.c ppa_reset_pulse(dev->base); base 887 drivers/scsi/ppa.c int loop, old_mode, status, k, ppb = dev->base; base 1030 drivers/scsi/ppa.c dev->base = -1; base 1066 drivers/scsi/ppa.c ppb = dev->base = dev->dev->port->base; base 1106 drivers/scsi/ppa.c host->io_port = pb->base; base 4246 drivers/scsi/qla1280.c host->base = (unsigned long)ha->mmpbase; base 1097 drivers/scsi/qla4xxx/ql4_fw.h } base; base 186 drivers/scsi/qla4xxx/ql4_iocb.c cur_dsd->base.addrLow = cpu_to_le32(LSDW(sle_dma)); base 187 drivers/scsi/qla4xxx/ql4_iocb.c cur_dsd->base.addrHigh = cpu_to_le32(MSDW(sle_dma)); base 416 drivers/scsi/qla4xxx/ql4_iocb.c passthru_iocb->out_dsd.base.addrLow = base 418 drivers/scsi/qla4xxx/ql4_iocb.c passthru_iocb->out_dsd.base.addrHigh = base 425 drivers/scsi/qla4xxx/ql4_iocb.c passthru_iocb->in_dsd.base.addrLow = base 427 drivers/scsi/qla4xxx/ql4_iocb.c passthru_iocb->in_dsd.base.addrHigh = base 3246 drivers/scsi/sd.c const int base = 'z' - 'a' + 1; base 3254 drivers/scsi/sd.c unit = base; base 107 drivers/scsi/sgiwd93.c (struct hpc3_scsiregs *) cmd->device->host->base; base 148 drivers/scsi/sgiwd93.c hregs = (struct hpc3_scsiregs *) SCpnt->device->host->base; base 166 drivers/scsi/sgiwd93.c void sgiwd93_reset(unsigned long base) base 168 drivers/scsi/sgiwd93.c struct hpc3_scsiregs *hregs = (struct hpc3_scsiregs *) base; base 232 drivers/scsi/sgiwd93.c host->base = (unsigned long) hregs; base 108 drivers/scsi/sim710.c hostdata->base = ioport_map(base_addr, 64); base 121 drivers/scsi/sim710.c host->base = base_addr; base 153 drivers/scsi/sim710.c release_region(host->base, 64); base 58 drivers/scsi/sni_53c710.c unsigned long base; base 67 drivers/scsi/sni_53c710.c base = res->start; base 74 drivers/scsi/sni_53c710.c hostdata->base = ioremap_nocache(base, 0x100); base 86 drivers/scsi/sni_53c710.c host->base = base; base 101 drivers/scsi/sni_53c710.c iounmap(hostdata->base); base 115 drivers/scsi/sni_53c710.c iounmap(hostdata->base); base 262 drivers/scsi/stex.c u32 base[6]; base 497 drivers/scsi/stex.c memset(p->base, 0, sizeof(u32)*6); base 498 drivers/scsi/stex.c *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0); base 797 drivers/scsi/stex.c void __iomem *base = hba->mmio_base; base 807 drivers/scsi/stex.c hba->status_head = readl(base + OMR1); base 878 drivers/scsi/stex.c writel(hba->status_head, base + IMR1); base 879 drivers/scsi/stex.c readl(base + IMR1); /* flush */ base 885 drivers/scsi/stex.c void __iomem *base = hba->mmio_base; base 891 drivers/scsi/stex.c data = readl(base + ODBL); base 895 drivers/scsi/stex.c writel(data, base + ODBL); base 896 drivers/scsi/stex.c readl(base + ODBL); /* flush */ base 986 drivers/scsi/stex.c void __iomem *base = hba->mmio_base; base 993 drivers/scsi/stex.c data = readl(base + YI2H_INT); base 996 drivers/scsi/stex.c writel(data, base + YI2H_INT_C); base 1004 drivers/scsi/stex.c data = readl(base + PSCRATCH4); base 1008 drivers/scsi/stex.c writel(data, base + PSCRATCH1); base 1009 drivers/scsi/stex.c writel((1 << 22), base + YH2I_INT); base 1026 drivers/scsi/stex.c void __iomem *base = hba->mmio_base; base 1032 drivers/scsi/stex.c if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { base 1033 drivers/scsi/stex.c writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); base 1034 drivers/scsi/stex.c readl(base + IDBL); base 1036 drivers/scsi/stex.c while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { base 1050 drivers/scsi/stex.c data = readl(base + OMR1); base 1074 drivers/scsi/stex.c writel(status_phys, base + IMR0); base 1075 drivers/scsi/stex.c readl(base + IMR0); base 1076 drivers/scsi/stex.c writel((status_phys >> 16) >> 16, base + IMR1); base 1077 drivers/scsi/stex.c readl(base + IMR1); base 1079 drivers/scsi/stex.c writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */ base 1080 drivers/scsi/stex.c readl(base + OMR0); base 1081 drivers/scsi/stex.c writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); base 1082 drivers/scsi/stex.c readl(base + IDBL); /* flush */ base 1086 drivers/scsi/stex.c while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { base 1097 drivers/scsi/stex.c writel(0, base + IMR0); base 1098 drivers/scsi/stex.c readl(base + IMR0); base 1099 drivers/scsi/stex.c writel(0, base + OMR0); base 1100 drivers/scsi/stex.c readl(base + OMR0); base 1101 drivers/scsi/stex.c writel(0, base + IMR1); base 1102 drivers/scsi/stex.c readl(base + IMR1); base 1103 drivers/scsi/stex.c writel(0, base + OMR1); base 1104 drivers/scsi/stex.c readl(base + OMR1); /* flush */ base 1110 drivers/scsi/stex.c void __iomem *base = hba->mmio_base; base 1121 drivers/scsi/stex.c operationaldata = readl(base + YIOA_STATUS); base 1130 drivers/scsi/stex.c operationaldata = readl(base + YIOA_STATUS); base 1133 drivers/scsi/stex.c operationaldata = readl(base + PSCRATCH3); base 1142 drivers/scsi/stex.c operationaldata = readl(base + PSCRATCH3); base 1163 drivers/scsi/stex.c data = readl(base + YINT_EN); base 1165 drivers/scsi/stex.c writel(data, base + YINT_EN); base 1166 drivers/scsi/stex.c writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI); base 1167 drivers/scsi/stex.c readl(base + YH2I_REQ_HI); base 1168 drivers/scsi/stex.c writel(hba->dma_handle, base + YH2I_REQ); base 1169 drivers/scsi/stex.c readl(base + YH2I_REQ); /* flush */ base 1171 drivers/scsi/stex.c data = readl(base + YINT_EN); base 1174 drivers/scsi/stex.c writel(data, base + YINT_EN); base 1177 drivers/scsi/stex.c writel((1 << 6), base + YH2I_INT); base 1180 drivers/scsi/stex.c writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI); base 1181 drivers/scsi/stex.c writel(hba->dma_handle, base + YH2I_REQ); base 1199 drivers/scsi/stex.c mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS); base 1210 drivers/scsi/stex.c mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS); base 1251 drivers/scsi/stex.c void __iomem *base; base 1258 drivers/scsi/stex.c base = hba->mmio_base; base 1267 drivers/scsi/stex.c data = readl(base + YI2H_INT); base 1271 drivers/scsi/stex.c writel(data, base + YI2H_INT_C); base 1274 drivers/scsi/stex.c data = readl(base + PSCRATCH4); base 1278 drivers/scsi/stex.c writel(data, base + PSCRATCH1); base 1279 drivers/scsi/stex.c writel((1 << 22), base + YH2I_INT); base 1283 drivers/scsi/stex.c data = readl(base + ODBL); base 1287 drivers/scsi/stex.c writel(data, base + ODBL); base 1288 drivers/scsi/stex.c readl(base + ODBL); /* flush */ base 1348 drivers/scsi/stex.c void __iomem *base; base 1352 drivers/scsi/stex.c base = hba->mmio_base; base 1353 drivers/scsi/stex.c writel(MU_INBOUND_DOORBELL_RESET, base + IDBL); base 1354 drivers/scsi/stex.c readl(base + IDBL); /* flush */ base 589 drivers/scsi/sun3_scsi.c hostdata->base = mem->start; base 480 drivers/scsi/vmw_pvscsi.c dma_addr_t base; base 487 drivers/scsi/vmw_pvscsi.c base = adapter->reqRingPA; base 489 drivers/scsi/vmw_pvscsi.c cmd.reqRingPPNs[i] = base >> PAGE_SHIFT; base 490 drivers/scsi/vmw_pvscsi.c base += PAGE_SIZE; base 493 drivers/scsi/vmw_pvscsi.c base = adapter->cmpRingPA; base 495 drivers/scsi/vmw_pvscsi.c cmd.cmpRingPPNs[i] = base >> PAGE_SHIFT; base 496 drivers/scsi/vmw_pvscsi.c base += PAGE_SIZE; base 511 drivers/scsi/vmw_pvscsi.c base = adapter->msgRingPA; base 513 drivers/scsi/vmw_pvscsi.c cmd_msg.ringPPNs[i] = base >> PAGE_SHIFT; base 514 drivers/scsi/vmw_pvscsi.c base += PAGE_SIZE; base 1522 drivers/scsi/wd33c93.c sgiwd93_reset(instance->base); /* yeah, give it the hard one */ base 52 drivers/scsi/wd719x.c return ioread8(wd->base + reg); base 57 drivers/scsi/wd719x.c return ioread32(wd->base + reg); base 62 drivers/scsi/wd719x.c iowrite8(val, wd->base + reg); base 67 drivers/scsi/wd719x.c iowrite16(val, wd->base + reg); base 72 drivers/scsi/wd719x.c iowrite32(val, wd->base + reg); base 818 drivers/scsi/wd719x.c sh->base = pci_resource_start(wd->pdev, 0); base 863 drivers/scsi/wd719x.c card_types[wd->type], sh->base, sh->irq, sh->this_id); base 925 drivers/scsi/wd719x.c wd->base = pci_iomap(pdev, 0, 0); base 926 drivers/scsi/wd719x.c if (!wd->base) base 946 drivers/scsi/wd719x.c pci_iounmap(pdev, wd->base); base 965 drivers/scsi/wd719x.c pci_iounmap(pdev, wd->base); base 67 drivers/scsi/wd719x.h void __iomem *base; base 131 drivers/scsi/zalon.c device.slot.base = dev->hpa.start + GSC_SCSI_ZALON_OFFSET; base 106 drivers/scsi/zorro7xx.c hostdata->base = ioremap(ioaddr, zorro_resource_len(z)); base 108 drivers/scsi/zorro7xx.c hostdata->base = ZTWO_VADDR(ioaddr); base 128 drivers/scsi/zorro7xx.c host->base = ioaddr; base 146 drivers/scsi/zorro7xx.c iounmap(hostdata->base); base 785 drivers/scsi/zorro_esp.c host->base = ioaddr; base 933 drivers/scsi/zorro_esp.c if (host->base > 0xffffff) base 368 drivers/sh/clk/core.c if (!mapping->base && mapping->phys) { base 371 drivers/sh/clk/core.c mapping->base = ioremap_nocache(mapping->phys, mapping->len); base 372 drivers/sh/clk/core.c if (unlikely(!mapping->base)) base 374 drivers/sh/clk/core.c } else if (mapping->base) { base 383 drivers/sh/clk/core.c clk->mapped_reg = clk->mapping->base; base 394 drivers/sh/clk/core.c iounmap(mapping->base); base 414 drivers/sh/clk/cpg.c value = __raw_readl(clk->mapping->base); base 430 drivers/sh/clk/cpg.c __raw_writel(0, clk->mapping->base); base 437 drivers/sh/clk/cpg.c value = __raw_readl(clk->mapping->base) >> 16; base 441 drivers/sh/clk/cpg.c __raw_writel((value << 16) | 0x3, clk->mapping->base); base 452 drivers/sh/clk/cpg.c __raw_writel(0, clk->mapping->base); base 454 drivers/sh/clk/cpg.c __raw_writel(idx << 16, clk->mapping->base); base 53 drivers/sh/superhyway/superhyway.c int superhyway_add_device(unsigned long base, struct superhyway_device *sdev, base 66 drivers/sh/superhyway/superhyway.c superhyway_read_vcr(dev, base, &dev->vcr); base 76 drivers/sh/superhyway/superhyway.c dev->resource->start = base; base 94 drivers/slimbus/qcom-ctrl.c void *base; base 106 drivers/slimbus/qcom-ctrl.c void __iomem *base; base 125 drivers/slimbus/qcom-ctrl.c __iowrite32_copy(ctrl->base + tx_reg, buf, count); base 146 drivers/slimbus/qcom-ctrl.c return ctrl->rx.base + (idx * ctrl->rx.sl_sz); base 173 drivers/slimbus/qcom-ctrl.c ctrl->base + MGR_INT_CLR); base 176 drivers/slimbus/qcom-ctrl.c u32 mgr_stat = readl_relaxed(ctrl->base + MGR_STATUS); base 177 drivers/slimbus/qcom-ctrl.c u32 mgr_ie_stat = readl_relaxed(ctrl->base + MGR_IE_STAT); base 178 drivers/slimbus/qcom-ctrl.c u32 frm_stat = readl_relaxed(ctrl->base + FRM_STAT); base 179 drivers/slimbus/qcom-ctrl.c u32 frm_cfg = readl_relaxed(ctrl->base + FRM_CFG); base 180 drivers/slimbus/qcom-ctrl.c u32 frm_intr_stat = readl_relaxed(ctrl->base + FRM_INT_STAT); base 181 drivers/slimbus/qcom-ctrl.c u32 frm_ie_stat = readl_relaxed(ctrl->base + FRM_IE_STAT); base 182 drivers/slimbus/qcom-ctrl.c u32 intf_stat = readl_relaxed(ctrl->base + INTF_STAT); base 183 drivers/slimbus/qcom-ctrl.c u32 intf_intr_stat = readl_relaxed(ctrl->base + INTF_INT_STAT); base 184 drivers/slimbus/qcom-ctrl.c u32 intf_ie_stat = readl_relaxed(ctrl->base + INTF_IE_STAT); base 186 drivers/slimbus/qcom-ctrl.c writel_relaxed(MGR_INT_TX_NACKED_2, ctrl->base + MGR_INT_CLR); base 214 drivers/slimbus/qcom-ctrl.c pkt[0] = readl_relaxed(ctrl->base + MGR_RX_MSG); base 236 drivers/slimbus/qcom-ctrl.c __ioread32_copy(rx_buf + 1, ctrl->base + MGR_RX_MSG + 4, base 255 drivers/slimbus/qcom-ctrl.c writel(MGR_INT_RX_MSG_RCVD, ctrl->base + base 266 drivers/slimbus/qcom-ctrl.c u32 stat = readl_relaxed(ctrl->base + MGR_INT_STAT); base 286 drivers/slimbus/qcom-ctrl.c writel_relaxed(1, ctrl->base + FRM_WAKEUP); base 321 drivers/slimbus/qcom-ctrl.c return ctrl->tx.base + (idx * ctrl->tx.sl_sz); base 430 drivers/slimbus/qcom-ctrl.c memcpy(buf, ctrl->rx.base + (ctrl->rx.head * ctrl->rx.sl_sz), base 530 drivers/slimbus/qcom-ctrl.c ctrl->base = devm_ioremap_resource(ctrl->dev, slim_mem); base 531 drivers/slimbus/qcom-ctrl.c if (IS_ERR(ctrl->base)) base 532 drivers/slimbus/qcom-ctrl.c return PTR_ERR(ctrl->base); base 578 drivers/slimbus/qcom-ctrl.c ctrl->tx.base = devm_kcalloc(&pdev->dev, ctrl->tx.n, ctrl->tx.sl_sz, base 580 drivers/slimbus/qcom-ctrl.c if (!ctrl->tx.base) { base 585 drivers/slimbus/qcom-ctrl.c ctrl->rx.base = devm_kcalloc(&pdev->dev,ctrl->rx.n, ctrl->rx.sl_sz, base 587 drivers/slimbus/qcom-ctrl.c if (!ctrl->rx.base) { base 599 drivers/slimbus/qcom-ctrl.c ver = readl_relaxed(ctrl->base); base 603 drivers/slimbus/qcom-ctrl.c writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver)); base 605 drivers/slimbus/qcom-ctrl.c ctrl->base + CFG_PORT(COMP_TRUST_CFG, ver)); base 609 drivers/slimbus/qcom-ctrl.c MGR_INT_TX_MSG_SENT), ctrl->base + MGR_INT_EN); base 610 drivers/slimbus/qcom-ctrl.c writel(1, ctrl->base + MGR_CFG); base 614 drivers/slimbus/qcom-ctrl.c ctrl->base + FRM_CFG); base 615 drivers/slimbus/qcom-ctrl.c writel(MGR_CFG_ENABLE, ctrl->base + MGR_CFG); base 616 drivers/slimbus/qcom-ctrl.c writel(1, ctrl->base + INTF_CFG); base 617 drivers/slimbus/qcom-ctrl.c writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver)); base 136 drivers/slimbus/qcom-ngd-ctrl.c void *base; base 141 drivers/slimbus/qcom-ngd-ctrl.c void __iomem *base; base 151 drivers/slimbus/qcom-ngd-ctrl.c void __iomem *base; base 530 drivers/slimbus/qcom-ngd-ctrl.c desc->base = ctrl->tx_base + ctrl->tx_tail * SLIM_MSGQ_BUF_LEN; base 536 drivers/slimbus/qcom-ngd-ctrl.c return desc->base; base 569 drivers/slimbus/qcom-ngd-ctrl.c desc->base = ctrl->tx_base + offset; base 619 drivers/slimbus/qcom-ngd-ctrl.c qcom_slim_ngd_rx(ctrl, (u8 *)desc->base); base 645 drivers/slimbus/qcom-ngd-ctrl.c desc->base = ctrl->rx_base + i * SLIM_MSGQ_BUF_LEN; base 752 drivers/slimbus/qcom-ngd-ctrl.c void __iomem *base = ctrl->ngd->base; base 753 drivers/slimbus/qcom-ngd-ctrl.c u32 stat = readl(base + NGD_INT_STAT); base 761 drivers/slimbus/qcom-ngd-ctrl.c writel(stat, base + NGD_INT_CLR); base 1062 drivers/slimbus/qcom-ngd-ctrl.c u32 cfg = readl_relaxed(ctrl->ngd->base); base 1075 drivers/slimbus/qcom-ngd-ctrl.c writel_relaxed(cfg, ctrl->ngd->base); base 1101 drivers/slimbus/qcom-ngd-ctrl.c ctrl->ver = readl_relaxed(ctrl->base); base 1105 drivers/slimbus/qcom-ngd-ctrl.c laddr = readl_relaxed(ngd->base + NGD_STATUS); base 1118 drivers/slimbus/qcom-ngd-ctrl.c writel_relaxed(DEF_NGD_INT_MASK, ngd->base + NGD_INT_EN); base 1119 drivers/slimbus/qcom-ngd-ctrl.c rx_msgq = readl_relaxed(ngd->base + NGD_RX_MSGQ_CFG); base 1122 drivers/slimbus/qcom-ngd-ctrl.c ngd->base + NGD_RX_MSGQ_CFG); base 1360 drivers/slimbus/qcom-ngd-ctrl.c ngd->base = ctrl->base + ngd->id * data->offset + base 1420 drivers/slimbus/qcom-ngd-ctrl.c ctrl->base = devm_ioremap_resource(dev, res); base 1421 drivers/slimbus/qcom-ngd-ctrl.c if (IS_ERR(ctrl->base)) base 1422 drivers/slimbus/qcom-ngd-ctrl.c return PTR_ERR(ctrl->base); base 16 drivers/soc/actions/owl-sps-helper.c int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable) base 22 drivers/soc/actions/owl-sps-helper.c val = readl(base + OWL_SPS_PG_CTL); base 32 drivers/soc/actions/owl-sps-helper.c writel(val, base + OWL_SPS_PG_CTL); base 35 drivers/soc/actions/owl-sps-helper.c val = readl(base + OWL_SPS_PG_CTL); base 34 drivers/soc/actions/owl-sps.c void __iomem *base; base 54 drivers/soc/actions/owl-sps.c return owl_sps_set_pg(pd->sps->base, pwr_mask, ack_mask, enable); base 123 drivers/soc/actions/owl-sps.c sps->base = of_io_request_and_map(pdev->dev.of_node, 0, "owl-sps"); base 124 drivers/soc/actions/owl-sps.c if (IS_ERR(sps->base)) { base 126 drivers/soc/actions/owl-sps.c return PTR_ERR(sps->base); base 610 drivers/soc/amlogic/meson-clk-measure.c void __iomem *base; base 627 drivers/soc/amlogic/meson-clk-measure.c base = devm_ioremap_resource(&pdev->dev, res); base 628 drivers/soc/amlogic/meson-clk-measure.c if (IS_ERR(base)) { base 630 drivers/soc/amlogic/meson-clk-measure.c return PTR_ERR(base); base 633 drivers/soc/amlogic/meson-clk-measure.c priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 223 drivers/soc/amlogic/meson-ee-pwrc.c struct generic_pm_domain base; base 253 drivers/soc/amlogic/meson-ee-pwrc.c container_of(domain, struct meson_ee_pwrc_domain, base); base 289 drivers/soc/amlogic/meson-ee-pwrc.c container_of(domain, struct meson_ee_pwrc_domain, base); base 357 drivers/soc/amlogic/meson-ee-pwrc.c dom->base.name = dom->desc.name; base 358 drivers/soc/amlogic/meson-ee-pwrc.c dom->base.power_on = meson_ee_pwrc_on; base 359 drivers/soc/amlogic/meson-ee-pwrc.c dom->base.power_off = meson_ee_pwrc_off; base 377 drivers/soc/amlogic/meson-ee-pwrc.c ret = pm_genpd_init(&dom->base, &pm_domain_always_on_gov, base 382 drivers/soc/amlogic/meson-ee-pwrc.c ret = pm_genpd_init(&dom->base, NULL, base 449 drivers/soc/amlogic/meson-ee-pwrc.c pwrc->xlate.domains[i] = &dom->base; base 464 drivers/soc/amlogic/meson-ee-pwrc.c meson_ee_pwrc_off(&dom->base); base 132 drivers/soc/aspeed/aspeed-p2a-ctrl.c u64 base, end; base 135 drivers/soc/aspeed/aspeed-p2a-ctrl.c base = map->addr; base 144 drivers/soc/aspeed/aspeed-p2a-ctrl.c if (curr->max < base) base 109 drivers/soc/bcm/bcm2835-power.c #define PM_READ(reg) readl(power->base + (reg)) base 110 drivers/soc/bcm/bcm2835-power.c #define PM_WRITE(reg, val) writel(PM_PASSWORD | (val), power->base + (reg)) base 133 drivers/soc/bcm/bcm2835-power.c struct generic_pm_domain base; base 142 drivers/soc/bcm/bcm2835-power.c void __iomem *base; base 240 drivers/soc/bcm/bcm2835-power.c pd->base.name); base 255 drivers/soc/bcm/bcm2835-power.c pd->base.name); base 285 drivers/soc/bcm/bcm2835-power.c pd->base.name); base 300 drivers/soc/bcm/bcm2835-power.c pd->base.name); base 307 drivers/soc/bcm/bcm2835-power.c pd->base.name); base 313 drivers/soc/bcm/bcm2835-power.c pd->base.name); base 340 drivers/soc/bcm/bcm2835-power.c pd->base.name); base 346 drivers/soc/bcm/bcm2835-power.c pd->base.name); base 362 drivers/soc/bcm/bcm2835-power.c container_of(domain, struct bcm2835_power_domain, base); base 428 drivers/soc/bcm/bcm2835-power.c container_of(domain, struct bcm2835_power_domain, base); base 508 drivers/soc/bcm/bcm2835-power.c dom->base.name = name; base 509 drivers/soc/bcm/bcm2835-power.c dom->base.power_on = bcm2835_power_pd_power_on; base 510 drivers/soc/bcm/bcm2835-power.c dom->base.power_off = bcm2835_power_pd_power_off; base 516 drivers/soc/bcm/bcm2835-power.c pm_genpd_init(&dom->base, NULL, true); base 518 drivers/soc/bcm/bcm2835-power.c power->pd_xlate.domains[pd_xlate_index] = &dom->base; base 554 drivers/soc/bcm/bcm2835-power.c ret = bcm2835_power_pd_power_off(&pd->base); base 558 drivers/soc/bcm/bcm2835-power.c return bcm2835_power_pd_power_on(&pd->base); base 627 drivers/soc/bcm/bcm2835-power.c power->base = pm->base; base 652 drivers/soc/bcm/bcm2835-power.c pm_genpd_add_subdomain(&power->domains[domain_deps[i].parent].base, base 653 drivers/soc/bcm/bcm2835-power.c &power->domains[domain_deps[i].child].base); base 672 drivers/soc/bcm/bcm2835-power.c struct generic_pm_domain *dom = &power->domains[i].base; base 145 drivers/soc/bcm/brcmstb/pm/pm-arm.c void __iomem *base = ctrl.aon_ctrl_base; base 149 drivers/soc/bcm/brcmstb/pm/pm-arm.c writel_relaxed(0, base + AON_CTRL_PM_INITIATE); base 150 drivers/soc/bcm/brcmstb/pm/pm-arm.c (void)readl_relaxed(base + AON_CTRL_PM_INITIATE); base 153 drivers/soc/bcm/brcmstb/pm/pm-arm.c writel_relaxed((cmd << 1) | PM_INITIATE, base + AON_CTRL_PM_INITIATE); base 160 drivers/soc/bcm/brcmstb/pm/pm-arm.c (void)readl_relaxed(base + AON_CTRL_PM_INITIATE); base 166 drivers/soc/bcm/brcmstb/pm/pm-arm.c ret = readl_relaxed(base + AON_CTRL_PM_INITIATE); base 182 drivers/soc/bcm/brcmstb/pm/pm-arm.c void __iomem *base = ctrl.aon_ctrl_base; base 187 drivers/soc/bcm/brcmstb/pm/pm-arm.c tmp = readl_relaxed(base + AON_CTRL_HOST_MISC_CMDS); base 189 drivers/soc/bcm/brcmstb/pm/pm-arm.c writel_relaxed(tmp, base + AON_CTRL_HOST_MISC_CMDS); base 190 drivers/soc/bcm/brcmstb/pm/pm-arm.c (void)readl_relaxed(base + AON_CTRL_HOST_MISC_CMDS); base 312 drivers/soc/bcm/brcmstb/pm/pm-arm.c void __iomem *base = ctrl.aon_ctrl_base; base 318 drivers/soc/bcm/brcmstb/pm/pm-arm.c writel_relaxed(base_cmd, base + AON_CTRL_PM_CTRL); base 321 drivers/soc/bcm/brcmstb/pm/pm-arm.c (void)readl_relaxed(base + AON_CTRL_PM_CTRL); base 323 drivers/soc/bcm/brcmstb/pm/pm-arm.c writel_relaxed(base_cmd | PM_PWR_DOWN, base + AON_CTRL_PM_CTRL); base 324 drivers/soc/bcm/brcmstb/pm/pm-arm.c (void)readl_relaxed(base + AON_CTRL_PM_CTRL); base 683 drivers/soc/bcm/brcmstb/pm/pm-arm.c void __iomem *base; base 687 drivers/soc/bcm/brcmstb/pm/pm-arm.c base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL); base 688 drivers/soc/bcm/brcmstb/pm/pm-arm.c if (IS_ERR(base)) { base 690 drivers/soc/bcm/brcmstb/pm/pm-arm.c return PTR_ERR(base); base 692 drivers/soc/bcm/brcmstb/pm/pm-arm.c ctrl.aon_ctrl_base = base; base 695 drivers/soc/bcm/brcmstb/pm/pm-arm.c base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 1, NULL); base 696 drivers/soc/bcm/brcmstb/pm/pm-arm.c if (IS_ERR(base)) { base 701 drivers/soc/bcm/brcmstb/pm/pm-arm.c ctrl.aon_sram = base; base 707 drivers/soc/bcm/brcmstb/pm/pm-arm.c base = brcmstb_ioremap_match(ddr_phy_dt_ids, 0, base 709 drivers/soc/bcm/brcmstb/pm/pm-arm.c if (IS_ERR(base)) { base 711 drivers/soc/bcm/brcmstb/pm/pm-arm.c return PTR_ERR(base); base 716 drivers/soc/bcm/brcmstb/pm/pm-arm.c ctrl.memcs[0].ddr_phy_base = base; base 735 drivers/soc/bcm/brcmstb/pm/pm-arm.c base = of_io_request_and_map(dn, 0, dn->full_name); base 736 drivers/soc/bcm/brcmstb/pm/pm-arm.c if (IS_ERR(base)) { base 741 drivers/soc/bcm/brcmstb/pm/pm-arm.c return PTR_ERR(base); base 743 drivers/soc/bcm/brcmstb/pm/pm-arm.c ctrl.memcs[i].ddr_shimphy_base = base; base 750 drivers/soc/bcm/brcmstb/pm/pm-arm.c base = of_iomap(dn, 0); base 751 drivers/soc/bcm/brcmstb/pm/pm-arm.c if (!base) { base 758 drivers/soc/bcm/brcmstb/pm/pm-arm.c iounmap(base); base 768 drivers/soc/bcm/brcmstb/pm/pm-arm.c ctrl.memcs[i].ddr_ctrl = base; base 80 drivers/soc/bcm/brcmstb/pm/pm-mips.c #define AON_SAVE_SRAM(base, idx, val) \ base 81 drivers/soc/bcm/brcmstb/pm/pm-mips.c __raw_writel(val, base + (idx << 2)) base 134 drivers/soc/bcm/brcmstb/pm/pm-mips.c void __iomem *base = ctrl.aon_ctrl_base; base 138 drivers/soc/bcm/brcmstb/pm/pm-mips.c tmp = __raw_readl(base + AON_CTRL_HOST_MISC_CMDS); base 140 drivers/soc/bcm/brcmstb/pm/pm-mips.c __raw_writel(tmp, base + AON_CTRL_HOST_MISC_CMDS); base 141 drivers/soc/bcm/brcmstb/pm/pm-mips.c (void)__raw_readl(base + AON_CTRL_HOST_MISC_CMDS); base 143 drivers/soc/bcm/brcmstb/pm/pm-mips.c __raw_writel(0, base + AON_CTRL_PM_INITIATE); base 144 drivers/soc/bcm/brcmstb/pm/pm-mips.c (void)__raw_readl(base + AON_CTRL_PM_INITIATE); base 146 drivers/soc/bcm/brcmstb/pm/pm-mips.c base + AON_CTRL_PM_INITIATE); base 156 drivers/soc/bcm/brcmstb/pm/pm-mips.c void __iomem *base = ctrl.aon_ctrl_base; base 164 drivers/soc/bcm/brcmstb/pm/pm-mips.c __raw_writel(0x10, base + AON_CTRL_PM_CPU_WAIT_COUNT); base 165 drivers/soc/bcm/brcmstb/pm/pm-mips.c (void)__raw_readl(base + AON_CTRL_PM_CPU_WAIT_COUNT); base 168 drivers/soc/bcm/brcmstb/pm/pm-mips.c __raw_writel(PM_COLD_CONFIG, base + AON_CTRL_PM_CTRL); base 169 drivers/soc/bcm/brcmstb/pm/pm-mips.c (void)__raw_readl(base + AON_CTRL_PM_CTRL); base 171 drivers/soc/bcm/brcmstb/pm/pm-mips.c __raw_writel((PM_COLD_CONFIG | PM_PWR_DOWN), base + base 173 drivers/soc/bcm/brcmstb/pm/pm-mips.c (void)__raw_readl(base + AON_CTRL_PM_CTRL); base 383 drivers/soc/bcm/brcmstb/pm/pm-mips.c void __iomem *base; base 387 drivers/soc/bcm/brcmstb/pm/pm-mips.c base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL); base 388 drivers/soc/bcm/brcmstb/pm/pm-mips.c if (IS_ERR(base)) { base 392 drivers/soc/bcm/brcmstb/pm/pm-mips.c ctrl.aon_ctrl_base = base; base 395 drivers/soc/bcm/brcmstb/pm/pm-mips.c base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 1, NULL); base 396 drivers/soc/bcm/brcmstb/pm/pm-mips.c if (IS_ERR(base)) { base 400 drivers/soc/bcm/brcmstb/pm/pm-mips.c ctrl.aon_sram_base = base; base 410 drivers/soc/bcm/brcmstb/pm/pm-mips.c base = brcmstb_ioremap_node(dn, 0); base 411 drivers/soc/bcm/brcmstb/pm/pm-mips.c if (IS_ERR(base)) base 414 drivers/soc/bcm/brcmstb/pm/pm-mips.c ctrl.memcs[i].ddr_phy_base = base; base 419 drivers/soc/bcm/brcmstb/pm/pm-mips.c base = brcmstb_ioremap_match(arb_dt_ids, 0, NULL); base 420 drivers/soc/bcm/brcmstb/pm/pm-mips.c if (IS_ERR(base)) { base 424 drivers/soc/bcm/brcmstb/pm/pm-mips.c ctrl.memcs[0].arb_base = base; base 427 drivers/soc/bcm/brcmstb/pm/pm-mips.c base = brcmstb_ioremap_match(timers_ids, 0, NULL); base 428 drivers/soc/bcm/brcmstb/pm/pm-mips.c if (IS_ERR(base)) { base 432 drivers/soc/bcm/brcmstb/pm/pm-mips.c ctrl.timers_base = base; base 451 drivers/soc/bcm/brcmstb/pm/pm-mips.c return PTR_ERR(base); base 27 drivers/soc/bcm/raspberrypi-power.c struct generic_pm_domain base; base 67 drivers/soc/bcm/raspberrypi-power.c container_of(domain, struct rpi_power_domain, base); base 75 drivers/soc/bcm/raspberrypi-power.c container_of(domain, struct rpi_power_domain, base); base 87 drivers/soc/bcm/raspberrypi-power.c dom->base.name = name; base 88 drivers/soc/bcm/raspberrypi-power.c dom->base.power_on = rpi_domain_on; base 89 drivers/soc/bcm/raspberrypi-power.c dom->base.power_off = rpi_domain_off; base 99 drivers/soc/bcm/raspberrypi-power.c pm_genpd_init(&dom->base, NULL, true); base 101 drivers/soc/bcm/raspberrypi-power.c rpi_domains->xlate.domains[xlate_index] = &dom->base; base 125 drivers/soc/dove/pmu.c struct generic_pm_domain base; base 128 drivers/soc/dove/pmu.c #define to_pmu_domain(dom) container_of(dom, struct pmu_domain, base) base 216 drivers/soc/dove/pmu.c domain->base.power_off = pmu_domain_power_off; base 217 drivers/soc/dove/pmu.c domain->base.power_on = pmu_domain_power_on; base 219 drivers/soc/dove/pmu.c pm_genpd_init(&domain->base, NULL, !(val & domain->pwr_mask)); base 222 drivers/soc/dove/pmu.c of_genpd_add_provider_simple(np, &domain->base); base 231 drivers/soc/dove/pmu.c void __iomem *base = gc->reg_base; base 232 drivers/soc/dove/pmu.c u32 stat = readl_relaxed(base + PMC_IRQ_CAUSE) & gc->mask_cache; base 261 drivers/soc/dove/pmu.c done &= readl_relaxed(base + PMC_IRQ_CAUSE); base 262 drivers/soc/dove/pmu.c writel_relaxed(done, base + PMC_IRQ_CAUSE); base 334 drivers/soc/dove/pmu.c domain->base.name = domain_initdata->name; base 417 drivers/soc/dove/pmu.c domain->base.name = kasprintf(GFP_KERNEL, "%pOFn", np); base 418 drivers/soc/dove/pmu.c if (!domain->base.name) { base 149 drivers/soc/fsl/qbman/bman_ccsr.c fbpr_a = rmem->base; base 57 drivers/soc/fsl/qbman/dpaa_sys.c *addr = rmem->base; base 128 drivers/soc/fsl/qbman/qman.c #define qm_cl(base, idx) ((void *)base + ((idx) << 6)) base 474 drivers/soc/fsl/qbman/qman_ccsr.c fqd_a = rmem->base; base 484 drivers/soc/fsl/qbman/qman_ccsr.c pfdr_a = rmem->base; base 194 drivers/soc/fsl/qe/gpio.c err -= gc->base; base 405 drivers/soc/fsl/qe/qe.c static void qe_upload_microcode(const void *base, base 408 drivers/soc/fsl/qe/qe.c const __be32 *code = base + be32_to_cpu(ucode->code_offset); base 174 drivers/soc/fsl/qe/qe_ic.c static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg) base 176 drivers/soc/fsl/qe/qe_ic.c return in_be32(base + (reg >> 2)); base 179 drivers/soc/fsl/qe/qe_ic.c static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg, base 182 drivers/soc/fsl/qe/qe_ic.c out_be32(base + (reg >> 2), value); base 43 drivers/soc/imx/gpc.c struct generic_pm_domain base; base 56 drivers/soc/imx/gpc.c return container_of(genpd, struct imx_pm_domain, base); base 193 drivers/soc/imx/gpc.c if (domain->base.power_on) base 194 drivers/soc/imx/gpc.c domain->base.power_on(&domain->base); base 197 drivers/soc/imx/gpc.c pm_genpd_init(&domain->base, NULL, false); base 198 drivers/soc/imx/gpc.c ret = of_genpd_add_provider_simple(dev->of_node, &domain->base); base 208 drivers/soc/imx/gpc.c pm_genpd_remove(&domain->base); base 220 drivers/soc/imx/gpc.c pm_genpd_remove(&domain->base); base 254 drivers/soc/imx/gpc.c .base = { base 260 drivers/soc/imx/gpc.c .base = { base 271 drivers/soc/imx/gpc.c .base = { base 280 drivers/soc/imx/gpc.c .base = { base 351 drivers/soc/imx/gpc.c &imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base, base 352 drivers/soc/imx/gpc.c &imx_gpc_domains[GPC_PGC_DOMAIN_PU].base, base 380 drivers/soc/imx/gpc.c domain->base.power_on(&domain->base); base 385 drivers/soc/imx/gpc.c pm_genpd_init(&imx_gpc_domains[i].base, NULL, false); base 398 drivers/soc/imx/gpc.c pm_genpd_remove(&imx_gpc_domains[i].base); base 411 drivers/soc/imx/gpc.c void __iomem *base; base 421 drivers/soc/imx/gpc.c base = devm_platform_ioremap_resource(pdev, 0); base 422 drivers/soc/imx/gpc.c if (IS_ERR(base)) base 423 drivers/soc/imx/gpc.c return PTR_ERR(base); base 425 drivers/soc/imx/gpc.c regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, base 445 drivers/soc/imx/gpc.c imx_gpc_domains[GPC_PGC_DOMAIN_PU].base.flags |= base 450 drivers/soc/imx/gpc.c imx_gpc_domains[GPC_PGC_DOMAIN_DISPLAY].base.flags |= base 533 drivers/soc/imx/gpc.c ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base); base 538 drivers/soc/imx/gpc.c ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base); base 566 drivers/soc/imx/gpcv2.c void __iomem *base; base 575 drivers/soc/imx/gpcv2.c base = devm_platform_ioremap_resource(pdev, 0); base 576 drivers/soc/imx/gpcv2.c if (IS_ERR(base)) base 577 drivers/soc/imx/gpcv2.c return PTR_ERR(base); base 579 drivers/soc/imx/gpcv2.c regmap = devm_regmap_init_mmio(dev, base, ®map_config); base 974 drivers/soc/mediatek/mtk-pmic-wrap.c void __iomem *base; base 1002 drivers/soc/mediatek/mtk-pmic-wrap.c return readl(wrp->base + wrp->master->regs[reg]); base 1007 drivers/soc/mediatek/mtk-pmic-wrap.c writel(val, wrp->base + wrp->master->regs[reg]); base 1921 drivers/soc/mediatek/mtk-pmic-wrap.c wrp->base = devm_ioremap_resource(wrp->dev, res); base 1922 drivers/soc/mediatek/mtk-pmic-wrap.c if (IS_ERR(wrp->base)) base 1923 drivers/soc/mediatek/mtk-pmic-wrap.c return PTR_ERR(wrp->base); base 141 drivers/soc/mediatek/mtk-scpsys.c void __iomem *base; base 165 drivers/soc/mediatek/mtk-scpsys.c u32 status = readl(scp->base + scp->ctrl_reg.pwr_sta_offs) & base 167 drivers/soc/mediatek/mtk-scpsys.c u32 status2 = readl(scp->base + scp->ctrl_reg.pwr_sta2nd_offs) & base 187 drivers/soc/mediatek/mtk-scpsys.c void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs; base 277 drivers/soc/mediatek/mtk-scpsys.c void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs; base 367 drivers/soc/mediatek/mtk-scpsys.c scp->base = devm_ioremap_resource(&pdev->dev, res); base 368 drivers/soc/mediatek/mtk-scpsys.c if (IS_ERR(scp->base)) base 369 drivers/soc/mediatek/mtk-scpsys.c return ERR_CAST(scp->base); base 250 drivers/soc/qcom/cmd-db.c cmd_db_header = memremap(rmem->base, rmem->size, MEMREMAP_WB); base 316 drivers/soc/qcom/llcc-slice.c void __iomem *base; base 322 drivers/soc/qcom/llcc-slice.c base = devm_ioremap_resource(&pdev->dev, res); base 323 drivers/soc/qcom/llcc-slice.c if (IS_ERR(base)) base 324 drivers/soc/qcom/llcc-slice.c return ERR_CAST(base); base 327 drivers/soc/qcom/llcc-slice.c return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); base 91 drivers/soc/qcom/qcom-geni-se.c void __iomem *base; base 182 drivers/soc/qcom/qcom-geni-se.c return readl_relaxed(wrapper->base + QUP_HW_VER_REG); base 186 drivers/soc/qcom/qcom-geni-se.c static void geni_se_io_set_mode(void __iomem *base) base 190 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(base + SE_IRQ_EN); base 193 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, base + SE_IRQ_EN); base 195 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(base + SE_GENI_DMA_MODE_EN); base 197 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); base 199 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(0, base + SE_GSI_EVENT_EN); base 202 drivers/soc/qcom/qcom-geni-se.c static void geni_se_io_init(void __iomem *base) base 206 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(base + GENI_CGC_CTRL); base 208 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, base + GENI_CGC_CTRL); base 210 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(base + SE_DMA_GENERAL_CFG); base 213 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, base + SE_DMA_GENERAL_CFG); base 215 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL); base 216 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG); base 221 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(0, se->base + SE_GSI_EVENT_EN); base 222 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); base 223 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); base 224 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); base 225 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); base 226 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); base 243 drivers/soc/qcom/qcom-geni-se.c geni_se_io_init(se->base); base 244 drivers/soc/qcom/qcom-geni-se.c geni_se_io_set_mode(se->base); base 246 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); base 247 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); base 249 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); base 251 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); base 253 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); base 255 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); base 266 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); base 271 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); base 273 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); base 276 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); base 278 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); base 280 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); base 289 drivers/soc/qcom/qcom-geni-se.c val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); base 291 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); base 414 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); base 415 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); base 418 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); base 419 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); base 430 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); base 643 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); base 644 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); base 645 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); base 646 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); base 647 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(len, se->base + SE_DMA_TX_LEN); base 679 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); base 680 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); base 681 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); base 683 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(0, se->base + SE_DMA_RX_ATTR); base 684 drivers/soc/qcom/qcom-geni-se.c writel_relaxed(len, se->base + SE_DMA_RX_LEN); base 736 drivers/soc/qcom/qcom-geni-se.c wrapper->base = devm_ioremap_resource(dev, res); base 737 drivers/soc/qcom/qcom-geni-se.c if (IS_ERR(wrapper->base)) base 738 drivers/soc/qcom/qcom-geni-se.c return PTR_ERR(wrapper->base); base 131 drivers/soc/qcom/qcom_gsbi.c void __iomem *base; base 143 drivers/soc/qcom/qcom_gsbi.c base = devm_ioremap_resource(&pdev->dev, res); base 144 drivers/soc/qcom/qcom_gsbi.c if (IS_ERR(base)) base 145 drivers/soc/qcom/qcom_gsbi.c return PTR_ERR(base); base 190 drivers/soc/qcom/qcom_gsbi.c base + GSBI_CTRL_REG); base 27 drivers/soc/qcom/rmtfs_mem.c void *base; base 92 drivers/soc/qcom/rmtfs_mem.c if (copy_to_user(buf, rmtfs_mem->base + *f_pos, count)) base 111 drivers/soc/qcom/rmtfs_mem.c if (copy_from_user(rmtfs_mem->base + *f_pos, buf, count)) base 198 drivers/soc/qcom/rmtfs_mem.c rmtfs_mem->addr = rmem->base; base 207 drivers/soc/qcom/rmtfs_mem.c rmtfs_mem->base = devm_memremap(&rmtfs_mem->dev, rmtfs_mem->addr, base 209 drivers/soc/qcom/rmtfs_mem.c if (IS_ERR(rmtfs_mem->base)) { base 211 drivers/soc/qcom/rmtfs_mem.c ret = PTR_ERR(rmtfs_mem->base); base 536 drivers/soc/qcom/rpmh-rsc.c void __iomem *base; base 541 drivers/soc/qcom/rpmh-rsc.c base = devm_ioremap_resource(&pdev->dev, res); base 542 drivers/soc/qcom/rpmh-rsc.c if (IS_ERR(base)) base 543 drivers/soc/qcom/rpmh-rsc.c return PTR_ERR(base); base 548 drivers/soc/qcom/rpmh-rsc.c drv->tcs_base = base + offset; base 550 drivers/soc/qcom/rpmh-rsc.c config = readl_relaxed(base + DRV_PRNT_CHLD_CONFIG); base 16 drivers/soc/renesas/rcar-rst.c static int rcar_rst_enable_wdt_reset(void __iomem *base) base 18 drivers/soc/renesas/rcar-rst.c iowrite32(WDTRSTCR_RESET, base + WDTRSTCR); base 24 drivers/soc/renesas/rcar-rst.c int (*configure)(void *base); /* Platform specific configuration */ base 77 drivers/soc/renesas/rcar-rst.c void __iomem *base; base 84 drivers/soc/renesas/rcar-rst.c base = of_iomap(np, 0); base 85 drivers/soc/renesas/rcar-rst.c if (!base) { base 91 drivers/soc/renesas/rcar-rst.c rcar_rst_base = base; base 93 drivers/soc/renesas/rcar-rst.c saved_mode = ioread32(base + cfg->modemr); base 95 drivers/soc/renesas/rcar-rst.c error = cfg->configure(base); base 335 drivers/soc/renesas/rcar-sysc.c void __iomem *base; base 354 drivers/soc/renesas/rcar-sysc.c base = of_iomap(np, 0); base 355 drivers/soc/renesas/rcar-sysc.c if (!base) { base 361 drivers/soc/renesas/rcar-sysc.c rcar_sysc_base = base; base 38 drivers/soc/renesas/rmobile-sysc.c void __iomem *base; base 60 drivers/soc/renesas/rmobile-sysc.c if (__raw_readl(rmobile_pd->base + PSTR) & mask) { base 62 drivers/soc/renesas/rmobile-sysc.c __raw_writel(mask, rmobile_pd->base + SPDCR); base 65 drivers/soc/renesas/rmobile-sysc.c if (!(__raw_readl(rmobile_pd->base + SPDCR) & mask)) base 72 drivers/soc/renesas/rmobile-sysc.c __raw_readl(rmobile_pd->base + PSTR)); base 83 drivers/soc/renesas/rmobile-sysc.c if (__raw_readl(rmobile_pd->base + PSTR) & mask) base 86 drivers/soc/renesas/rmobile-sysc.c __raw_writel(mask, rmobile_pd->base + SWUCR); base 89 drivers/soc/renesas/rmobile-sysc.c if (!(__raw_readl(rmobile_pd->base + SWUCR) & mask)) base 101 drivers/soc/renesas/rmobile-sysc.c __raw_readl(rmobile_pd->base + PSTR)); base 280 drivers/soc/renesas/rmobile-sysc.c static int __init rmobile_add_pm_domains(void __iomem *base, base 301 drivers/soc/renesas/rmobile-sysc.c pd->base = base; base 309 drivers/soc/renesas/rmobile-sysc.c rmobile_add_pm_domains(base, np, &pd->genpd); base 318 drivers/soc/renesas/rmobile-sysc.c void __iomem *base; base 322 drivers/soc/renesas/rmobile-sysc.c base = of_iomap(np, 0); base 323 drivers/soc/renesas/rmobile-sysc.c if (!base) { base 340 drivers/soc/renesas/rmobile-sysc.c ret = rmobile_add_pm_domains(base, pmd, NULL); base 30 drivers/soc/samsung/pm_domains.c void __iomem *base; base 39 drivers/soc/samsung/pm_domains.c void __iomem *base; base 44 drivers/soc/samsung/pm_domains.c base = pd->base; base 47 drivers/soc/samsung/pm_domains.c writel_relaxed(pwr, base); base 52 drivers/soc/samsung/pm_domains.c while ((readl_relaxed(base + 0x4) & pd->local_pwr_cfg) != pwr) { base 128 drivers/soc/samsung/pm_domains.c pd->base = of_iomap(np, 0); base 129 drivers/soc/samsung/pm_domains.c if (!pd->base) { base 140 drivers/soc/samsung/pm_domains.c on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg; base 108 drivers/soc/sunxi/sunxi_sram.c static void __iomem *base; base 141 drivers/soc/sunxi/sunxi_sram.c val = readl(base + sram_data->reg); base 228 drivers/soc/sunxi/sunxi_sram.c if (IS_ERR(base)) base 229 drivers/soc/sunxi/sunxi_sram.c return PTR_ERR(base); base 231 drivers/soc/sunxi/sunxi_sram.c if (!base) base 252 drivers/soc/sunxi/sunxi_sram.c val = readl(base + sram_data->reg); base 255 drivers/soc/sunxi/sunxi_sram.c base + sram_data->reg); base 335 drivers/soc/sunxi/sunxi_sram.c base = devm_ioremap_resource(&pdev->dev, res); base 336 drivers/soc/sunxi/sunxi_sram.c if (IS_ERR(base)) base 337 drivers/soc/sunxi/sunxi_sram.c return PTR_ERR(base); base 347 drivers/soc/sunxi/sunxi_sram.c emac_clock = devm_regmap_init_mmio(&pdev->dev, base, base 143 drivers/soc/tegra/flowctrl.c void __iomem *base = tegra_flowctrl_base; base 151 drivers/soc/tegra/flowctrl.c iounmap(base); base 89 drivers/soc/tegra/fuse/fuse-tegra.c .base = NULL, base 120 drivers/soc/tegra/fuse/fuse-tegra.c void __iomem *base = fuse->base; base 127 drivers/soc/tegra/fuse/fuse-tegra.c fuse->base = devm_ioremap_resource(&pdev->dev, res); base 128 drivers/soc/tegra/fuse/fuse-tegra.c if (IS_ERR(fuse->base)) { base 129 drivers/soc/tegra/fuse/fuse-tegra.c err = PTR_ERR(fuse->base); base 130 drivers/soc/tegra/fuse/fuse-tegra.c fuse->base = base; base 140 drivers/soc/tegra/fuse/fuse-tegra.c fuse->base = base; base 150 drivers/soc/tegra/fuse/fuse-tegra.c fuse->base = base; base 160 drivers/soc/tegra/fuse/fuse-tegra.c iounmap(base); base 198 drivers/soc/tegra/fuse/fuse-tegra.c static void tegra_enable_fuse_clk(void __iomem *base) base 202 drivers/soc/tegra/fuse/fuse-tegra.c reg = readl_relaxed(base + 0x48); base 204 drivers/soc/tegra/fuse/fuse-tegra.c writel(reg, base + 0x48); base 210 drivers/soc/tegra/fuse/fuse-tegra.c reg = readl(base + 0x14); base 212 drivers/soc/tegra/fuse/fuse-tegra.c writel(reg, base + 0x14); base 316 drivers/soc/tegra/fuse/fuse-tegra.c void __iomem *base = of_iomap(np, 0); base 317 drivers/soc/tegra/fuse/fuse-tegra.c if (base) { base 318 drivers/soc/tegra/fuse/fuse-tegra.c tegra_enable_fuse_clk(base); base 319 drivers/soc/tegra/fuse/fuse-tegra.c iounmap(base); base 326 drivers/soc/tegra/fuse/fuse-tegra.c fuse->base = ioremap_nocache(regs.start, resource_size(®s)); base 327 drivers/soc/tegra/fuse/fuse-tegra.c if (!fuse->base) { base 31 drivers/soc/tegra/fuse/fuse-tegra20.c return readl_relaxed(fuse->base + FUSE_BEGIN + offset); base 42 drivers/soc/tegra/fuse/fuse-tegra30.c if (WARN_ON(!fuse->base)) base 45 drivers/soc/tegra/fuse/fuse-tegra30.c return readl_relaxed(fuse->base + FUSE_BEGIN + offset); base 59 drivers/soc/tegra/fuse/fuse-tegra30.c value = readl_relaxed(fuse->base + FUSE_BEGIN + offset); base 34 drivers/soc/tegra/fuse/fuse.h void __iomem *base; base 315 drivers/soc/tegra/pmc.c void __iomem *base; base 350 drivers/soc/tegra/pmc.c .base = NULL, base 379 drivers/soc/tegra/pmc.c return readl(pmc->base + offset); base 399 drivers/soc/tegra/pmc.c writel(value, pmc->base + offset); base 2050 drivers/soc/tegra/pmc.c void __iomem *base; base 2059 drivers/soc/tegra/pmc.c if (WARN_ON(!pmc->base || !pmc->soc)) base 2068 drivers/soc/tegra/pmc.c base = devm_ioremap_resource(&pdev->dev, res); base 2069 drivers/soc/tegra/pmc.c if (IS_ERR(base)) base 2070 drivers/soc/tegra/pmc.c return PTR_ERR(base); base 2078 drivers/soc/tegra/pmc.c pmc->wake = base; base 2087 drivers/soc/tegra/pmc.c pmc->aotag = base; base 2096 drivers/soc/tegra/pmc.c pmc->scratch = base; base 2145 drivers/soc/tegra/pmc.c iounmap(pmc->base); base 2146 drivers/soc/tegra/pmc.c pmc->base = base; base 2820 drivers/soc/tegra/pmc.c saved = readl(pmc->base + pmc->soc->regs->scratch0); base 2827 drivers/soc/tegra/pmc.c writel(value, pmc->base + pmc->soc->regs->scratch0); base 2828 drivers/soc/tegra/pmc.c value = readl(pmc->base + pmc->soc->regs->scratch0); base 2837 drivers/soc/tegra/pmc.c writel(saved, pmc->base + pmc->soc->regs->scratch0); base 2895 drivers/soc/tegra/pmc.c pmc->base = ioremap_nocache(regs.start, resource_size(®s)); base 2896 drivers/soc/tegra/pmc.c if (!pmc->base) { base 74 drivers/soc/ti/knav_qmss.h u32 base; base 1056 drivers/soc/ti/knav_qmss_queue.c writel_relaxed((u32)region->dma_start, ®s->base); base 161 drivers/soc/ux500/ux500-soc-id.c void __iomem *base; base 165 drivers/soc/ux500/ux500-soc-id.c base = of_iomap(backupram, 0); base 166 drivers/soc/ux500/ux500-soc-id.c if (!base) base 168 drivers/soc/ux500/ux500-soc-id.c uid = base + 0x1fc0; base 176 drivers/soc/ux500/ux500-soc-id.c iounmap(base); base 383 drivers/soundwire/cadence_master.c u32 base, i, data; base 392 drivers/soundwire/cadence_master.c base = CDNS_MCP_CMD_BASE; base 404 drivers/soundwire/cadence_master.c cdns_writel(cdns, base, data); base 405 drivers/soundwire/cadence_master.c base += CDNS_MCP_CMD_WORD_LEN; base 428 drivers/soundwire/cadence_master.c u32 data[2], base; base 447 drivers/soundwire/cadence_master.c base = CDNS_MCP_CMD_BASE; base 448 drivers/soundwire/cadence_master.c cdns_writel(cdns, base, data[0]); base 449 drivers/soundwire/cadence_master.c base += CDNS_MCP_CMD_WORD_LEN; base 450 drivers/soundwire/cadence_master.c cdns_writel(cdns, base, data[1]); base 116 drivers/soundwire/intel.c static inline int intel_readl(void __iomem *base, int offset) base 118 drivers/soundwire/intel.c return readl(base + offset); base 121 drivers/soundwire/intel.c static inline void intel_writel(void __iomem *base, int offset, int value) base 123 drivers/soundwire/intel.c writel(value, base + offset); base 126 drivers/soundwire/intel.c static inline u16 intel_readw(void __iomem *base, int offset) base 128 drivers/soundwire/intel.c return readw(base + offset); base 131 drivers/soundwire/intel.c static inline void intel_writew(void __iomem *base, int offset, u16 value) base 133 drivers/soundwire/intel.c writew(value, base + offset); base 136 drivers/soundwire/intel.c static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) base 141 drivers/soundwire/intel.c writel(value, base + offset); base 143 drivers/soundwire/intel.c reg_read = readl(base + offset); base 154 drivers/soundwire/intel.c static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) base 159 drivers/soundwire/intel.c writel(value, base + offset); base 161 drivers/soundwire/intel.c reg_read = readl(base + offset); base 44 drivers/spi/spi-altera.c void __iomem *base; base 67 drivers/spi/spi-altera.c writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); base 68 drivers/spi/spi-altera.c writel(0, hw->base + ALTERA_SPI_SLAVE_SEL); base 70 drivers/spi/spi-altera.c writel(BIT(spi->chip_select), hw->base + ALTERA_SPI_SLAVE_SEL); base 72 drivers/spi/spi-altera.c writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); base 92 drivers/spi/spi-altera.c writel(txd, hw->base + ALTERA_SPI_TXDATA); base 99 drivers/spi/spi-altera.c rxd = readl(hw->base + ALTERA_SPI_RXDATA); base 129 drivers/spi/spi-altera.c writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); base 137 drivers/spi/spi-altera.c while (!(readl(hw->base + ALTERA_SPI_STATUS) & base 161 drivers/spi/spi-altera.c writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); base 191 drivers/spi/spi-altera.c hw->base = devm_platform_ioremap_resource(pdev, 0); base 192 drivers/spi/spi-altera.c if (IS_ERR(hw->base)) { base 193 drivers/spi/spi-altera.c err = PTR_ERR(hw->base); base 198 drivers/spi/spi-altera.c writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); base 199 drivers/spi/spi-altera.c writel(0, hw->base + ALTERA_SPI_STATUS); /* clear status reg */ base 200 drivers/spi/spi-altera.c if (readl(hw->base + ALTERA_SPI_STATUS) & ALTERA_SPI_STATUS_RRDY_MSK) base 201 drivers/spi/spi-altera.c readl(hw->base + ALTERA_SPI_RXDATA); /* flush rxdata */ base 214 drivers/spi/spi-altera.c dev_info(&pdev->dev, "base %p, irq %d\n", hw->base, hw->irq); base 104 drivers/spi/spi-armada-3700.c void __iomem *base; base 119 drivers/spi/spi-armada-3700.c return readl(a3700_spi->base + offset); base 124 drivers/spi/spi-armada-3700.c writel(data, a3700_spi->base + offset); base 857 drivers/spi/spi-armada-3700.c spi->base = devm_platform_ioremap_resource(pdev, 0); base 858 drivers/spi/spi-armada-3700.c if (IS_ERR(spi->base)) { base 859 drivers/spi/spi-armada-3700.c ret = PTR_ERR(spi->base); base 44 drivers/spi/spi-ath79.c void __iomem *base; base 51 drivers/spi/spi-ath79.c return ioread32(sp->base + reg); base 56 drivers/spi/spi-ath79.c iowrite32(val, sp->base + reg); base 171 drivers/spi/spi-ath79.c sp->base = devm_platform_ioremap_resource(pdev, 0); base 172 drivers/spi/spi-ath79.c if (IS_ERR(sp->base)) { base 173 drivers/spi/spi-ath79.c ret = PTR_ERR(sp->base); base 87 drivers/spi/spi-axi-spi-engine.c void __iomem *base; base 289 drivers/spi/spi-axi-spi-engine.c void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO; base 293 drivers/spi/spi-axi-spi-engine.c n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM); base 309 drivers/spi/spi-axi-spi-engine.c void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO; base 313 drivers/spi/spi-axi-spi-engine.c n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM); base 331 drivers/spi/spi-axi-spi-engine.c void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO; base 335 drivers/spi/spi-axi-spi-engine.c n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL); base 358 drivers/spi/spi-axi-spi-engine.c pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING); base 362 drivers/spi/spi-axi-spi-engine.c spi_engine->base + SPI_ENGINE_REG_INT_PENDING); base 364 drivers/spi/spi-axi-spi-engine.c spi_engine->base + SPI_ENGINE_REG_SYNC_ID); base 401 drivers/spi/spi-axi-spi-engine.c spi_engine->base + SPI_ENGINE_REG_INT_ENABLE); base 451 drivers/spi/spi-axi-spi-engine.c spi_engine->base + SPI_ENGINE_REG_INT_ENABLE); base 482 drivers/spi/spi-axi-spi-engine.c spi_engine->base = devm_platform_ioremap_resource(pdev, 0); base 483 drivers/spi/spi-axi-spi-engine.c if (IS_ERR(spi_engine->base)) { base 484 drivers/spi/spi-axi-spi-engine.c ret = PTR_ERR(spi_engine->base); base 488 drivers/spi/spi-axi-spi-engine.c version = readl(spi_engine->base + SPI_ENGINE_REG_VERSION); base 518 drivers/spi/spi-axi-spi-engine.c writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET); base 519 drivers/spi/spi-axi-spi-engine.c writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING); base 520 drivers/spi/spi-axi-spi-engine.c writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE); base 563 drivers/spi/spi-axi-spi-engine.c writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING); base 564 drivers/spi/spi-axi-spi-engine.c writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE); base 565 drivers/spi/spi-axi-spi-engine.c writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET); base 197 drivers/spi/spi-bcm-qspi.c void __iomem *base[BASEMAX]; base 231 drivers/spi/spi-bcm-qspi.c return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset); base 238 drivers/spi/spi-bcm-qspi.c bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset); base 512 drivers/spi/spi-bcm-qspi.c if (qspi->base[CHIP_SELECT]) { base 1254 drivers/spi/spi-bcm-qspi.c qspi->base[MSPI] = devm_ioremap_resource(dev, res); base 1255 drivers/spi/spi-bcm-qspi.c if (IS_ERR(qspi->base[MSPI])) { base 1256 drivers/spi/spi-bcm-qspi.c ret = PTR_ERR(qspi->base[MSPI]); base 1265 drivers/spi/spi-bcm-qspi.c qspi->base[BSPI] = devm_ioremap_resource(dev, res); base 1266 drivers/spi/spi-bcm-qspi.c if (IS_ERR(qspi->base[BSPI])) { base 1267 drivers/spi/spi-bcm-qspi.c ret = PTR_ERR(qspi->base[BSPI]); base 1279 drivers/spi/spi-bcm-qspi.c qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res); base 1280 drivers/spi/spi-bcm-qspi.c if (IS_ERR(qspi->base[CHIP_SELECT])) { base 1281 drivers/spi/spi-bcm-qspi.c ret = PTR_ERR(qspi->base[CHIP_SELECT]); base 111 drivers/spi/spi-davinci.c void __iomem *base; base 234 drivers/spi/spi-davinci.c iowrite16(spidat1, dspi->base + SPIDAT1 + 2); base 376 drivers/spi/spi-davinci.c iowrite32(delay, dspi->base + SPIDELAY); base 379 drivers/spi/spi-davinci.c iowrite32(spifmt, dspi->base + SPIFMT0); base 427 drivers/spi/spi-davinci.c set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); base 431 drivers/spi/spi-davinci.c set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); base 434 drivers/spi/spi-davinci.c set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); base 436 drivers/spi/spi-davinci.c clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); base 516 drivers/spi/spi-davinci.c buf = ioread32(dspi->base + SPIBUF); base 523 drivers/spi/spi-davinci.c status = ioread32(dspi->base + SPIFLG); base 531 drivers/spi/spi-davinci.c spidat1 = ioread32(dspi->base + SPIDAT1); base 535 drivers/spi/spi-davinci.c iowrite32(spidat1, dspi->base + SPIDAT1); base 595 drivers/spi/spi-davinci.c spidat1 = ioread32(dspi->base + SPIDAT1); base 597 drivers/spi/spi-davinci.c clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); base 598 drivers/spi/spi-davinci.c set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); base 604 drivers/spi/spi-davinci.c set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); base 610 drivers/spi/spi-davinci.c iowrite32(spidat1, dspi->base + SPIDAT1); base 658 drivers/spi/spi-davinci.c iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); base 666 drivers/spi/spi-davinci.c set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); base 682 drivers/spi/spi-davinci.c clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); base 684 drivers/spi/spi-davinci.c clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); base 686 drivers/spi/spi-davinci.c clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); base 687 drivers/spi/spi-davinci.c set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); base 742 drivers/spi/spi-davinci.c clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); base 917 drivers/spi/spi-davinci.c dspi->base = devm_ioremap_resource(&pdev->dev, r); base 918 drivers/spi/spi-davinci.c if (IS_ERR(dspi->base)) { base 919 drivers/spi/spi-davinci.c ret = PTR_ERR(dspi->base); base 982 drivers/spi/spi-davinci.c iowrite32(0, dspi->base + SPIGCR0); base 984 drivers/spi/spi-davinci.c iowrite32(1, dspi->base + SPIGCR0); base 988 drivers/spi/spi-davinci.c iowrite32(spipc0, dspi->base + SPIPC0); base 991 drivers/spi/spi-davinci.c iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); base 993 drivers/spi/spi-davinci.c iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); base 995 drivers/spi/spi-davinci.c iowrite32(CS_DEFAULT, dspi->base + SPIDEF); base 998 drivers/spi/spi-davinci.c set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); base 999 drivers/spi/spi-davinci.c set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); base 1000 drivers/spi/spi-davinci.c set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); base 1006 drivers/spi/spi-davinci.c dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); base 76 drivers/spi/spi-efm32.c void __iomem *base; base 97 drivers/spi/spi-efm32.c writel_relaxed(value, ddata->base + offset); base 102 drivers/spi/spi-efm32.c return readl_relaxed(ddata->base + offset); base 396 drivers/spi/spi-efm32.c ddata->base = devm_ioremap_resource(&pdev->dev, res); base 397 drivers/spi/spi-efm32.c if (IS_ERR(ddata->base)) { base 398 drivers/spi/spi-efm32.c ret = PTR_ERR(ddata->base); base 1004 drivers/spi/spi-fsl-dspi.c void __iomem *base; base 1060 drivers/spi/spi-fsl-dspi.c base = devm_ioremap_resource(&pdev->dev, res); base 1061 drivers/spi/spi-fsl-dspi.c if (IS_ERR(base)) { base 1062 drivers/spi/spi-fsl-dspi.c ret = PTR_ERR(base); base 1070 drivers/spi/spi-fsl-dspi.c dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config); base 1080 drivers/spi/spi-fsl-dspi.c &pdev->dev, base + SPI_PUSHR, base 101 drivers/spi/spi-fsl-lpspi.c void __iomem *base; base 140 drivers/spi/spi-fsl-lpspi.c unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \ base 159 drivers/spi/spi-fsl-lpspi.c writel(val, fsl_lpspi->base + IMX7ULP_TDR); \ base 172 drivers/spi/spi-fsl-lpspi.c writel(enable, fsl_lpspi->base + IMX7ULP_IER); base 249 drivers/spi/spi-fsl-lpspi.c txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; base 260 drivers/spi/spi-fsl-lpspi.c temp = readl(fsl_lpspi->base + IMX7ULP_TCR); base 262 drivers/spi/spi-fsl-lpspi.c writel(temp, fsl_lpspi->base + IMX7ULP_TCR); base 272 drivers/spi/spi-fsl-lpspi.c while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY)) base 299 drivers/spi/spi-fsl-lpspi.c writel(temp, fsl_lpspi->base + IMX7ULP_TCR); base 314 drivers/spi/spi-fsl-lpspi.c writel(temp, fsl_lpspi->base + IMX7ULP_FCR); base 346 drivers/spi/spi-fsl-lpspi.c fsl_lpspi->base + IMX7ULP_CCR); base 420 drivers/spi/spi-fsl-lpspi.c writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1); base 422 drivers/spi/spi-fsl-lpspi.c temp = readl(fsl_lpspi->base + IMX7ULP_CR); base 424 drivers/spi/spi-fsl-lpspi.c writel(temp, fsl_lpspi->base + IMX7ULP_CR); base 429 drivers/spi/spi-fsl-lpspi.c writel(temp, fsl_lpspi->base + IMX7ULP_DER); base 527 drivers/spi/spi-fsl-lpspi.c writel(temp, fsl_lpspi->base + IMX7ULP_SR); base 531 drivers/spi/spi-fsl-lpspi.c writel(temp, fsl_lpspi->base + IMX7ULP_CR); base 762 drivers/spi/spi-fsl-lpspi.c temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER); base 764 drivers/spi/spi-fsl-lpspi.c temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR); base 774 drivers/spi/spi-fsl-lpspi.c readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) { base 775 drivers/spi/spi-fsl-lpspi.c writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); base 781 drivers/spi/spi-fsl-lpspi.c writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); base 907 drivers/spi/spi-fsl-lpspi.c fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res); base 908 drivers/spi/spi-fsl-lpspi.c if (IS_ERR(fsl_lpspi->base)) { base 909 drivers/spi/spi-fsl-lpspi.c ret = PTR_ERR(fsl_lpspi->base); base 950 drivers/spi/spi-fsl-lpspi.c temp = readl(fsl_lpspi->base + IMX7ULP_PARAM); base 407 drivers/spi/spi-fsl-qspi.c void __iomem *base = q->iobase; base 453 drivers/spi/spi-fsl-qspi.c qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i)); base 550 drivers/spi/spi-fsl-qspi.c void __iomem *base = q->iobase; base 557 drivers/spi/spi-fsl-qspi.c qspi_writel(q, val, base + QUADSPI_TBDR); base 563 drivers/spi/spi-fsl-qspi.c qspi_writel(q, val, base + QUADSPI_TBDR); base 568 drivers/spi/spi-fsl-qspi.c qspi_writel(q, 0, base + QUADSPI_TBDR); base 575 drivers/spi/spi-fsl-qspi.c void __iomem *base = q->iobase; base 581 drivers/spi/spi-fsl-qspi.c val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); base 587 drivers/spi/spi-fsl-qspi.c val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); base 595 drivers/spi/spi-fsl-qspi.c void __iomem *base = q->iobase; base 606 drivers/spi/spi-fsl-qspi.c base + QUADSPI_IPCR); base 618 drivers/spi/spi-fsl-qspi.c static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base, base 626 drivers/spi/spi-fsl-qspi.c return readl_poll_timeout(base, reg, !(reg & mask), delay_us, base 633 drivers/spi/spi-fsl-qspi.c void __iomem *base = q->iobase; base 640 drivers/spi/spi-fsl-qspi.c fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK | base 650 drivers/spi/spi-fsl-qspi.c base + QUADSPI_SFAR); base 652 drivers/spi/spi-fsl-qspi.c qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) | base 654 drivers/spi/spi-fsl-qspi.c base + QUADSPI_MCR); base 657 drivers/spi/spi-fsl-qspi.c base + QUADSPI_SPTRCLR); base 671 drivers/spi/spi-fsl-qspi.c QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT); base 706 drivers/spi/spi-fsl-qspi.c void __iomem *base = q->iobase; base 724 drivers/spi/spi-fsl-qspi.c base + QUADSPI_MCR); base 729 drivers/spi/spi-fsl-qspi.c base + QUADSPI_MCR); base 737 drivers/spi/spi-fsl-qspi.c qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) & base 739 drivers/spi/spi-fsl-qspi.c base + QUADSPI_FLSHCR); base 741 drivers/spi/spi-fsl-qspi.c reg = qspi_readl(q, base + QUADSPI_SMPR); base 745 drivers/spi/spi-fsl-qspi.c | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR); base 748 drivers/spi/spi-fsl-qspi.c qspi_writel(q, 0, base + QUADSPI_BUF0IND); base 749 drivers/spi/spi-fsl-qspi.c qspi_writel(q, 0, base + QUADSPI_BUF1IND); base 750 drivers/spi/spi-fsl-qspi.c qspi_writel(q, 0, base + QUADSPI_BUF2IND); base 754 drivers/spi/spi-fsl-qspi.c qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT); base 757 drivers/spi/spi-fsl-qspi.c base + QUADSPI_BUF3CR); base 770 drivers/spi/spi-fsl-qspi.c base + QUADSPI_SFA1AD); base 772 drivers/spi/spi-fsl-qspi.c base + QUADSPI_SFA2AD); base 774 drivers/spi/spi-fsl-qspi.c base + QUADSPI_SFB1AD); base 776 drivers/spi/spi-fsl-qspi.c base + QUADSPI_SFB2AD); base 782 drivers/spi/spi-fsl-qspi.c base + QUADSPI_MCR); base 133 drivers/spi/spi-geni-qcom.c writel(0, se->base + SE_GENI_TX_WATERMARK_REG); base 181 drivers/spi/spi-geni-qcom.c word_len = readl(se->base + SE_SPI_WORD_LEN); base 195 drivers/spi/spi-geni-qcom.c writel(word_len, se->base + SE_SPI_WORD_LEN); base 207 drivers/spi/spi-geni-qcom.c loopback_cfg = readl(se->base + SE_SPI_LOOPBACK); base 208 drivers/spi/spi-geni-qcom.c cpol = readl(se->base + SE_SPI_CPOL); base 209 drivers/spi/spi-geni-qcom.c cpha = readl(se->base + SE_SPI_CPHA); base 241 drivers/spi/spi-geni-qcom.c writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); base 242 drivers/spi/spi-geni-qcom.c writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); base 243 drivers/spi/spi-geni-qcom.c writel(cpha, se->base + SE_SPI_CPHA); base 244 drivers/spi/spi-geni-qcom.c writel(cpol, se->base + SE_SPI_CPOL); base 245 drivers/spi/spi-geni-qcom.c writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); base 246 drivers/spi/spi-geni-qcom.c writel(clk_sel, se->base + SE_GENI_CLK_SEL); base 247 drivers/spi/spi-geni-qcom.c writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); base 311 drivers/spi/spi-geni-qcom.c spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); base 338 drivers/spi/spi-geni-qcom.c writel(clk_sel, se->base + SE_GENI_CLK_SEL); base 339 drivers/spi/spi-geni-qcom.c writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); base 362 drivers/spi/spi-geni-qcom.c writel(len, se->base + SE_SPI_TX_TRANS_LEN); base 366 drivers/spi/spi-geni-qcom.c writel(len, se->base + SE_SPI_RX_TRANS_LEN); base 369 drivers/spi/spi-geni-qcom.c writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); base 379 drivers/spi/spi-geni-qcom.c writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); base 432 drivers/spi/spi-geni-qcom.c iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); base 436 drivers/spi/spi-geni-qcom.c writel(0, se->base + SE_GENI_TX_WATERMARK_REG); base 449 drivers/spi/spi-geni-qcom.c rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); base 468 drivers/spi/spi-geni-qcom.c ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); base 487 drivers/spi/spi-geni-qcom.c m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); base 513 drivers/spi/spi-geni-qcom.c writel(0, se->base + SE_GENI_TX_WATERMARK_REG); base 527 drivers/spi/spi-geni-qcom.c writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); base 537 drivers/spi/spi-geni-qcom.c void __iomem *base; base 544 drivers/spi/spi-geni-qcom.c base = devm_platform_ioremap_resource(pdev, 0); base 545 drivers/spi/spi-geni-qcom.c if (IS_ERR(base)) base 546 drivers/spi/spi-geni-qcom.c return PTR_ERR(base); base 565 drivers/spi/spi-geni-qcom.c mas->se.base = base; base 86 drivers/spi/spi-imx.c void __iomem *base; base 142 drivers/spi/spi-imx.c unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ base 164 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPITXDATA); \ base 284 drivers/spi/spi-imx.c unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); base 321 drivers/spi/spi-imx.c val = readl(spi_imx->base + MXC_CSPIRXDATA); base 353 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPITXDATA); base 381 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPITXDATA); base 386 drivers/spi/spi-imx.c u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); base 421 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPITXDATA); base 476 drivers/spi/spi-imx.c writel(val, spi_imx->base + MX51_ECSPI_INT); base 483 drivers/spi/spi-imx.c reg = readl(spi_imx->base + MX51_ECSPI_CTRL); base 485 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MX51_ECSPI_CTRL); base 492 drivers/spi/spi-imx.c ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); base 494 drivers/spi/spi-imx.c writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); base 503 drivers/spi/spi-imx.c u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); base 524 drivers/spi/spi-imx.c writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); base 526 drivers/spi/spi-imx.c testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); base 531 drivers/spi/spi-imx.c writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); base 561 drivers/spi/spi-imx.c writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); base 570 drivers/spi/spi-imx.c u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); base 591 drivers/spi/spi-imx.c writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); base 623 drivers/spi/spi-imx.c MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); base 628 drivers/spi/spi-imx.c return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; base 635 drivers/spi/spi-imx.c readl(spi_imx->base + MXC_CSPIRXDATA); base 678 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPIINT); base 685 drivers/spi/spi-imx.c reg = readl(spi_imx->base + MXC_CSPICTRL); base 687 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); base 728 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); base 730 drivers/spi/spi-imx.c reg = readl(spi_imx->base + MX31_CSPI_TESTREG); base 735 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MX31_CSPI_TESTREG); base 743 drivers/spi/spi-imx.c spi_imx->base + MX31_CSPI_DMAREG); base 751 drivers/spi/spi-imx.c return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; base 757 drivers/spi/spi-imx.c while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) base 758 drivers/spi/spi-imx.c readl(spi_imx->base + MXC_CSPIRXDATA); base 783 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPIINT); base 790 drivers/spi/spi-imx.c reg = readl(spi_imx->base + MXC_CSPICTRL); base 792 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); base 824 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); base 831 drivers/spi/spi-imx.c return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; base 836 drivers/spi/spi-imx.c writel(1, spi_imx->base + MXC_RESET); base 859 drivers/spi/spi-imx.c writel(val, spi_imx->base + MXC_CSPIINT); base 866 drivers/spi/spi-imx.c reg = readl(spi_imx->base + MXC_CSPICTRL); base 868 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); base 895 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); base 902 drivers/spi/spi-imx.c return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; base 907 drivers/spi/spi-imx.c writel(1, spi_imx->base + MXC_RESET); base 1069 drivers/spi/spi-imx.c ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); base 1072 drivers/spi/spi-imx.c writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); base 1504 drivers/spi/spi-imx.c readl(spi_imx->base + MXC_CSPIRXDATA); base 1670 drivers/spi/spi-imx.c spi_imx->base = devm_ioremap_resource(&pdev->dev, res); base 1671 drivers/spi/spi-imx.c if (IS_ERR(spi_imx->base)) { base 1672 drivers/spi/spi-imx.c ret = PTR_ERR(spi_imx->base); base 1789 drivers/spi/spi-imx.c writel(0, spi_imx->base + MXC_CSPICTRL); base 37 drivers/spi/spi-jcore.c void __iomem *base; base 59 drivers/spi/spi-jcore.c void __iomem *ctrl_reg = hw->base + CTRL_REG; base 101 drivers/spi/spi-jcore.c void __iomem *ctrl_reg = hw->base + CTRL_REG; base 102 drivers/spi/spi-jcore.c void __iomem *data_reg = hw->base + DATA_REG; base 173 drivers/spi/spi-jcore.c hw->base = devm_ioremap_nocache(&pdev->dev, res->start, base 175 drivers/spi/spi-jcore.c if (!hw->base) base 126 drivers/spi/spi-meson-spicc.c void __iomem *base; base 145 drivers/spi/spi-meson-spicc.c readl_relaxed(spicc->base + SPICC_STATREG)); base 151 drivers/spi/spi-meson-spicc.c readl_relaxed(spicc->base + SPICC_STATREG)); base 193 drivers/spi/spi-meson-spicc.c readl_relaxed(spicc->base + SPICC_RXDATA)); base 202 drivers/spi/spi-meson-spicc.c spicc->base + SPICC_TXDATA); base 233 drivers/spi/spi-meson-spicc.c spicc->base + SPICC_CONREG); base 242 drivers/spi/spi-meson-spicc.c u32 ctrl = readl_relaxed(spicc->base + SPICC_INTREG); base 243 drivers/spi/spi-meson-spicc.c u32 stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl; base 258 drivers/spi/spi-meson-spicc.c stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl; base 266 drivers/spi/spi-meson-spicc.c writel_relaxed(SPICC_TC, spicc->base + SPICC_STATREG); base 273 drivers/spi/spi-meson-spicc.c writel(0, spicc->base + SPICC_INTREG); base 289 drivers/spi/spi-meson-spicc.c spicc->base + SPICC_CONREG); base 296 drivers/spi/spi-meson-spicc.c writel(ctrl, spicc->base + SPICC_INTREG); base 341 drivers/spi/spi-meson-spicc.c conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG); base 353 drivers/spi/spi-meson-spicc.c writel_relaxed(conf, spicc->base + SPICC_CONREG); base 388 drivers/spi/spi-meson-spicc.c writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); base 391 drivers/spi/spi-meson-spicc.c writel_relaxed(irq, spicc->base + SPICC_INTREG); base 443 drivers/spi/spi-meson-spicc.c writel_relaxed(conf, spicc->base + SPICC_CONREG); base 446 drivers/spi/spi-meson-spicc.c writel_relaxed(0, spicc->base + SPICC_PERIODREG); base 448 drivers/spi/spi-meson-spicc.c writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG); base 458 drivers/spi/spi-meson-spicc.c writel(0, spicc->base + SPICC_INTREG); base 461 drivers/spi/spi-meson-spicc.c writel_bits_relaxed(SPICC_ENABLE, 0, spicc->base + SPICC_CONREG); base 519 drivers/spi/spi-meson-spicc.c spicc->base = devm_platform_ioremap_resource(pdev, 0); base 520 drivers/spi/spi-meson-spicc.c if (IS_ERR(spicc->base)) { base 522 drivers/spi/spi-meson-spicc.c ret = PTR_ERR(spicc->base); base 527 drivers/spi/spi-meson-spicc.c writel_relaxed(0, spicc->base + SPICC_INTREG); base 596 drivers/spi/spi-meson-spicc.c writel(0, spicc->base + SPICC_CONREG); base 289 drivers/spi/spi-meson-spifc.c void __iomem *base; base 302 drivers/spi/spi-meson-spifc.c base = devm_platform_ioremap_resource(pdev, 0); base 303 drivers/spi/spi-meson-spifc.c if (IS_ERR(base)) { base 304 drivers/spi/spi-meson-spifc.c ret = PTR_ERR(base); base 308 drivers/spi/spi-meson-spifc.c spifc->regmap = devm_regmap_init_mmio(spifc->dev, base, base 95 drivers/spi/spi-mt65xx.c void __iomem *base; base 183 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CMD_REG); base 185 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CMD_REG); base 187 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CMD_REG); base 189 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CMD_REG); base 204 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CMD_REG); base 252 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CMD_REG); base 257 drivers/spi/spi-mt65xx.c mdata->base + SPI_PAD_SEL_REG); base 267 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CMD_REG); base 270 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CMD_REG); base 273 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CMD_REG); base 299 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CFG2_REG); base 304 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CFG0_REG); base 311 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CFG0_REG); base 314 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CFG1_REG); base 317 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CFG1_REG); base 328 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CFG1_REG); base 332 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CFG1_REG); base 340 drivers/spi/spi-mt65xx.c cmd = readl(mdata->base + SPI_CMD_REG); base 345 drivers/spi/spi-mt65xx.c writel(cmd, mdata->base + SPI_CMD_REG); base 395 drivers/spi/spi-mt65xx.c mdata->base + SPI_TX_SRC_REG); base 399 drivers/spi/spi-mt65xx.c mdata->base + SPI_TX_SRC_REG_64); base 405 drivers/spi/spi-mt65xx.c mdata->base + SPI_RX_DST_REG); base 409 drivers/spi/spi-mt65xx.c mdata->base + SPI_RX_DST_REG_64); base 429 drivers/spi/spi-mt65xx.c iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); base 435 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_TX_DATA_REG); base 459 drivers/spi/spi-mt65xx.c cmd = readl(mdata->base + SPI_CMD_REG); base 464 drivers/spi/spi-mt65xx.c writel(cmd, mdata->base + SPI_CMD_REG); base 528 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_STATUS0_REG); base 537 drivers/spi/spi-mt65xx.c ioread32_rep(mdata->base + SPI_RX_DATA_REG, base 541 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_RX_DATA_REG); base 561 drivers/spi/spi-mt65xx.c iowrite32_rep(mdata->base + SPI_TX_DATA_REG, base 570 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_TX_DATA_REG); base 600 drivers/spi/spi-mt65xx.c cmd = readl(mdata->base + SPI_CMD_REG); base 603 drivers/spi/spi-mt65xx.c writel(cmd, mdata->base + SPI_CMD_REG); base 693 drivers/spi/spi-mt65xx.c mdata->base = devm_ioremap_resource(&pdev->dev, res); base 694 drivers/spi/spi-mt65xx.c if (IS_ERR(mdata->base)) { base 695 drivers/spi/spi-mt65xx.c ret = PTR_ERR(mdata->base); base 55 drivers/spi/spi-mt7621.c void __iomem *base; base 69 drivers/spi/spi-mt7621.c return ioread32(rs->base + reg); base 74 drivers/spi/spi-mt7621.c iowrite32(val, rs->base + reg); base 329 drivers/spi/spi-mt7621.c void __iomem *base; base 338 drivers/spi/spi-mt7621.c base = devm_platform_ioremap_resource(pdev, 0); base 339 drivers/spi/spi-mt7621.c if (IS_ERR(base)) base 340 drivers/spi/spi-mt7621.c return PTR_ERR(base); base 370 drivers/spi/spi-mt7621.c rs->base = base; base 91 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); base 97 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL1(ssp)); base 99 drivers/spi/spi-mxs.c writel(0x0, ssp->base + HW_SSP_CMD0); base 100 drivers/spi/spi-mxs.c writel(0x0, ssp->base + HW_SSP_CMD1); base 132 drivers/spi/spi-mxs.c reg = readl_relaxed(ssp->base + offset); base 159 drivers/spi/spi-mxs.c readl(ssp->base + HW_SSP_CTRL1(ssp)), base 160 drivers/spi/spi-mxs.c readl(ssp->base + HW_SSP_STATUS(ssp))); base 192 drivers/spi/spi-mxs.c ctrl0 = readl(ssp->base + HW_SSP_CTRL0); base 306 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); base 311 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); base 315 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); base 317 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); base 319 drivers/spi/spi-mxs.c writel(1, ssp->base + HW_SSP_XFER_SIZE); base 324 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); base 327 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); base 330 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); base 336 drivers/spi/spi-mxs.c writel(*buf, ssp->base + HW_SSP_DATA(ssp)); base 339 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); base 346 drivers/spi/spi-mxs.c *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff); base 372 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); base 374 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); base 399 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL1(ssp) + base 412 drivers/spi/spi-mxs.c ssp->base + HW_SSP_CTRL1(ssp) + base 428 drivers/spi/spi-mxs.c stmp_reset_block(ssp->base); base 536 drivers/spi/spi-mxs.c void __iomem *base; base 551 drivers/spi/spi-mxs.c base = devm_platform_ioremap_resource(pdev, 0); base 552 drivers/spi/spi-mxs.c if (IS_ERR(base)) base 553 drivers/spi/spi-mxs.c return PTR_ERR(base); base 583 drivers/spi/spi-mxs.c ssp->base = base; base 617 drivers/spi/spi-mxs.c ret = stmp_reset_block(ssp->base); base 27 drivers/spi/spi-npcm-pspi.c void __iomem *base; base 77 drivers/spi/spi-npcm-pspi.c val = ioread16(priv->base + NPCM_PSPI_CTL1); base 79 drivers/spi/spi-npcm-pspi.c iowrite16(val, priv->base + NPCM_PSPI_CTL1); base 86 drivers/spi/spi-npcm-pspi.c val = ioread16(priv->base + NPCM_PSPI_CTL1); base 88 drivers/spi/spi-npcm-pspi.c iowrite16(val, priv->base + NPCM_PSPI_CTL1); base 95 drivers/spi/spi-npcm-pspi.c val = ioread16(priv->base + NPCM_PSPI_CTL1); base 97 drivers/spi/spi-npcm-pspi.c iowrite16(val, priv->base + NPCM_PSPI_CTL1); base 104 drivers/spi/spi-npcm-pspi.c val = ioread16(priv->base + NPCM_PSPI_CTL1); base 106 drivers/spi/spi-npcm-pspi.c iowrite16(val, priv->base + NPCM_PSPI_CTL1); base 130 drivers/spi/spi-npcm-pspi.c regtemp = ioread16(priv->base + NPCM_PSPI_CTL1); base 132 drivers/spi/spi-npcm-pspi.c iowrite16(regtemp | mode_val, priv->base + NPCM_PSPI_CTL1); base 139 drivers/spi/spi-npcm-pspi.c regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base); base 150 drivers/spi/spi-npcm-pspi.c iowrite16(regtemp, NPCM_PSPI_CTL1 + priv->base); base 161 drivers/spi/spi-npcm-pspi.c regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base); base 163 drivers/spi/spi-npcm-pspi.c iowrite16(regtemp | (ckdiv << 9), NPCM_PSPI_CTL1 + priv->base); base 207 drivers/spi/spi-npcm-pspi.c iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base); base 210 drivers/spi/spi-npcm-pspi.c iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base); base 233 drivers/spi/spi-npcm-pspi.c val = ioread8(priv->base + NPCM_PSPI_DATA); base 236 drivers/spi/spi-npcm-pspi.c val = ioread16(priv->base + NPCM_PSPI_DATA); base 299 drivers/spi/spi-npcm-pspi.c stat = ioread8(priv->base + NPCM_PSPI_STAT); base 306 drivers/spi/spi-npcm-pspi.c val = ioread8(NPCM_PSPI_DATA + priv->base); base 334 drivers/spi/spi-npcm-pspi.c iowrite8(0x0, NPCM_PSPI_DATA + priv->base); base 370 drivers/spi/spi-npcm-pspi.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 371 drivers/spi/spi-npcm-pspi.c if (IS_ERR(priv->base)) { base 372 drivers/spi/spi-npcm-pspi.c ret = PTR_ERR(priv->base); base 446 drivers/spi/spi-nxp-fspi.c static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, base 456 drivers/spi/spi-nxp-fspi.c return readl_poll_timeout(base, reg, (reg & mask), base 459 drivers/spi/spi-nxp-fspi.c return readl_poll_timeout(base, reg, !(reg & mask), base 485 drivers/spi/spi-nxp-fspi.c void __iomem *base = f->iobase; base 533 drivers/spi/spi-nxp-fspi.c fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); base 655 drivers/spi/spi-nxp-fspi.c void __iomem *base = f->iobase; base 660 drivers/spi/spi-nxp-fspi.c fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR); base 674 drivers/spi/spi-nxp-fspi.c fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR); base 675 drivers/spi/spi-nxp-fspi.c fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4); base 676 drivers/spi/spi-nxp-fspi.c fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); base 690 drivers/spi/spi-nxp-fspi.c fspi_writel(f, data, base + FSPI_TFDR + j); base 692 drivers/spi/spi-nxp-fspi.c fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); base 699 drivers/spi/spi-nxp-fspi.c void __iomem *base = f->iobase; base 715 drivers/spi/spi-nxp-fspi.c *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR); base 716 drivers/spi/spi-nxp-fspi.c *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4); base 718 drivers/spi/spi-nxp-fspi.c fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); base 734 drivers/spi/spi-nxp-fspi.c tmp = fspi_readl(f, base + FSPI_RFDR + j); base 742 drivers/spi/spi-nxp-fspi.c fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR); base 744 drivers/spi/spi-nxp-fspi.c fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); base 749 drivers/spi/spi-nxp-fspi.c void __iomem *base = f->iobase; base 754 drivers/spi/spi-nxp-fspi.c reg = fspi_readl(f, base + FSPI_IPRXFCR); base 758 drivers/spi/spi-nxp-fspi.c fspi_writel(f, reg, base + FSPI_IPRXFCR); base 762 drivers/spi/spi-nxp-fspi.c fspi_writel(f, op->addr.val, base + FSPI_IPCR0); base 771 drivers/spi/spi-nxp-fspi.c base + FSPI_IPCR1); base 774 drivers/spi/spi-nxp-fspi.c fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD); base 844 drivers/spi/spi-nxp-fspi.c void __iomem *base = f->iobase; base 867 drivers/spi/spi-nxp-fspi.c fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); base 870 drivers/spi/spi-nxp-fspi.c fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); base 871 drivers/spi/spi-nxp-fspi.c fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); base 875 drivers/spi/spi-nxp-fspi.c base + FSPI_MCR0); base 883 drivers/spi/spi-nxp-fspi.c fspi_writel(f, reg, base + FSPI_MCR2); base 887 drivers/spi/spi-nxp-fspi.c fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i); base 894 drivers/spi/spi-nxp-fspi.c FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0); base 898 drivers/spi/spi-nxp-fspi.c base + FSPI_AHBCR); base 901 drivers/spi/spi-nxp-fspi.c fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); base 902 drivers/spi/spi-nxp-fspi.c fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); base 903 drivers/spi/spi-nxp-fspi.c fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); base 904 drivers/spi/spi-nxp-fspi.c fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); base 909 drivers/spi/spi-nxp-fspi.c fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN); base 42 drivers/spi/spi-oc-tiny.c void __iomem *base; base 89 drivers/spi/spi-oc-tiny.c writel(baud, hw->base + TINY_SPI_BAUD); base 90 drivers/spi/spi-oc-tiny.c writel(hw->mode, hw->base + TINY_SPI_CONTROL); base 108 drivers/spi/spi-oc-tiny.c while (!(readb(hw->base + TINY_SPI_STATUS) & base 115 drivers/spi/spi-oc-tiny.c while (!(readb(hw->base + TINY_SPI_STATUS) & base 138 drivers/spi/spi-oc-tiny.c hw->base + TINY_SPI_TXDATA); base 141 drivers/spi/spi-oc-tiny.c hw->base + TINY_SPI_TXDATA); base 143 drivers/spi/spi-oc-tiny.c writeb(TINY_SPI_STATUS_TXR, hw->base + TINY_SPI_STATUS); base 146 drivers/spi/spi-oc-tiny.c hw->base + TINY_SPI_TXDATA); base 148 drivers/spi/spi-oc-tiny.c writeb(TINY_SPI_STATUS_TXE, hw->base + TINY_SPI_STATUS); base 154 drivers/spi/spi-oc-tiny.c writeb(txp ? *txp++ : 0, hw->base + TINY_SPI_TXDATA); base 156 drivers/spi/spi-oc-tiny.c writeb(txp ? *txp++ : 0, hw->base + TINY_SPI_TXDATA); base 161 drivers/spi/spi-oc-tiny.c *rxp++ = readb(hw->base + TINY_SPI_TXDATA); base 165 drivers/spi/spi-oc-tiny.c *rxp++ = readb(hw->base + TINY_SPI_RXDATA); base 175 drivers/spi/spi-oc-tiny.c writeb(0, hw->base + TINY_SPI_STATUS); base 178 drivers/spi/spi-oc-tiny.c *hw->rxp++ = readb(hw->base + TINY_SPI_RXDATA); base 183 drivers/spi/spi-oc-tiny.c *hw->rxp++ = readb(hw->base + TINY_SPI_TXDATA); base 187 drivers/spi/spi-oc-tiny.c hw->base + TINY_SPI_TXDATA); base 190 drivers/spi/spi-oc-tiny.c hw->base + TINY_SPI_STATUS); base 193 drivers/spi/spi-oc-tiny.c hw->base + TINY_SPI_STATUS); base 266 drivers/spi/spi-oc-tiny.c hw->base = devm_platform_ioremap_resource(pdev, 0); base 267 drivers/spi/spi-oc-tiny.c if (IS_ERR(hw->base)) { base 268 drivers/spi/spi-oc-tiny.c err = PTR_ERR(hw->base); base 307 drivers/spi/spi-oc-tiny.c dev_info(&pdev->dev, "base %p, irq %d\n", hw->base, hw->irq); base 73 drivers/spi/spi-omap-100k.c void __iomem *base; base 77 drivers/spi/spi-omap-100k.c void __iomem *base; base 87 drivers/spi/spi-omap-100k.c val = readw(spi100k->base + SPI_SETUP1); base 89 drivers/spi/spi-omap-100k.c writew(val, spi100k->base + SPI_SETUP1); base 98 drivers/spi/spi-omap-100k.c val = readw(spi100k->base + SPI_SETUP1); base 100 drivers/spi/spi-omap-100k.c writew(val, spi100k->base + SPI_SETUP1); base 114 drivers/spi/spi-omap-100k.c writew(data , spi100k->base + SPI_TX_MSB); base 119 drivers/spi/spi-omap-100k.c spi100k->base + SPI_CTRL); base 122 drivers/spi/spi-omap-100k.c while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE) base 142 drivers/spi/spi-omap-100k.c spi100k->base + SPI_CTRL); base 144 drivers/spi/spi-omap-100k.c while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD) base 148 drivers/spi/spi-omap-100k.c dataL = readw(spi100k->base + SPI_RX_LSB); base 149 drivers/spi/spi-omap-100k.c dataH = readw(spi100k->base + SPI_RX_MSB); base 162 drivers/spi/spi-omap-100k.c SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1); base 167 drivers/spi/spi-omap-100k.c SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2); base 173 drivers/spi/spi-omap-100k.c writew(0x05fc, spi100k->base + SPI_CTRL); base 175 drivers/spi/spi-omap-100k.c writew(0x05fd, spi100k->base + SPI_CTRL); base 250 drivers/spi/spi-omap-100k.c writew(0x3e , spi100k->base + SPI_SETUP1); base 251 drivers/spi/spi-omap-100k.c writew(0x00 , spi100k->base + SPI_STATUS); base 252 drivers/spi/spi-omap-100k.c writew(0x3e , spi100k->base + SPI_CTRL); base 272 drivers/spi/spi-omap-100k.c cs->base = spi100k->base + spi->chip_select * 0x14; base 381 drivers/spi/spi-omap-100k.c spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev); base 124 drivers/spi/spi-omap2-mcspi.c void __iomem *base; base 136 drivers/spi/spi-omap2-mcspi.c void __iomem *base; base 150 drivers/spi/spi-omap2-mcspi.c writel_relaxed(val, mcspi->base + idx); base 157 drivers/spi/spi-omap2-mcspi.c return readl_relaxed(mcspi->base + idx); base 165 drivers/spi/spi-omap2-mcspi.c writel_relaxed(val, cs->base + idx); base 172 drivers/spi/spi-omap2-mcspi.c return readl_relaxed(cs->base + idx); base 441 drivers/spi/spi-omap2-mcspi.c void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; base 656 drivers/spi/spi-omap2-mcspi.c irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; base 668 drivers/spi/spi-omap2-mcspi.c chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; base 695 drivers/spi/spi-omap2-mcspi.c void __iomem *base = cs->base; base 709 drivers/spi/spi-omap2-mcspi.c tx_reg = base + OMAP2_MCSPI_TX0; base 710 drivers/spi/spi-omap2-mcspi.c rx_reg = base + OMAP2_MCSPI_RX0; base 711 drivers/spi/spi-omap2-mcspi.c chstat_reg = base + OMAP2_MCSPI_CHSTAT0; base 1048 drivers/spi/spi-omap2-mcspi.c cs->base = mcspi->base + spi->chip_select * 0x14; base 1216 drivers/spi/spi-omap2-mcspi.c writel_relaxed(0, cs->base base 1282 drivers/spi/spi-omap2-mcspi.c cs->base + OMAP2_MCSPI_CHCONF0); base 1283 drivers/spi/spi-omap2-mcspi.c readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); base 1357 drivers/spi/spi-omap2-mcspi.c cs->base + OMAP2_MCSPI_CHCONF0); base 1360 drivers/spi/spi-omap2-mcspi.c cs->base + OMAP2_MCSPI_CHCONF0); base 1363 drivers/spi/spi-omap2-mcspi.c cs->base + OMAP2_MCSPI_CHCONF0); base 1446 drivers/spi/spi-omap2-mcspi.c mcspi->base = devm_ioremap_resource(&pdev->dev, r); base 1447 drivers/spi/spi-omap2-mcspi.c if (IS_ERR(mcspi->base)) { base 1448 drivers/spi/spi-omap2-mcspi.c status = PTR_ERR(mcspi->base); base 1452 drivers/spi/spi-omap2-mcspi.c mcspi->base += regs_offset; base 97 drivers/spi/spi-orion.c void __iomem *base; base 108 drivers/spi/spi-orion.c return orion_spi->base + reg; base 680 drivers/spi/spi-orion.c spi->base = devm_ioremap_resource(&pdev->dev, r); base 681 drivers/spi/spi-orion.c if (IS_ERR(spi->base)) { base 682 drivers/spi/spi-orion.c status = PTR_ERR(spi->base); base 138 drivers/spi/spi-qcom-qspi.c void __iomem *base; base 169 drivers/spi/spi-qcom-qspi.c pio_xfer_cfg = readl(ctrl->base + PIO_XFER_CFG); base 179 drivers/spi/spi-qcom-qspi.c writel(pio_xfer_cfg, ctrl->base + PIO_XFER_CFG); base 186 drivers/spi/spi-qcom-qspi.c pio_xfer_ctrl = readl(ctrl->base + PIO_XFER_CTRL); base 189 drivers/spi/spi-qcom-qspi.c writel(pio_xfer_ctrl, ctrl->base + PIO_XFER_CTRL); base 199 drivers/spi/spi-qcom-qspi.c writel(QSPI_ALL_IRQS, ctrl->base + MSTR_INT_STATUS); base 206 drivers/spi/spi-qcom-qspi.c writel(ints, ctrl->base + MSTR_INT_EN); base 219 drivers/spi/spi-qcom-qspi.c writel(0, ctrl->base + MSTR_INT_EN); base 279 drivers/spi/spi-qcom-qspi.c mstr_cfg = readl(ctrl->base + MSTR_CONFIG); base 291 drivers/spi/spi-qcom-qspi.c writel(mstr_cfg, ctrl->base + MSTR_CONFIG); base 308 drivers/spi/spi-qcom-qspi.c rd_fifo_status = readl(ctrl->base + RD_FIFO_STATUS); base 324 drivers/spi/spi-qcom-qspi.c ioread32_rep(ctrl->base + RD_FIFO, word_buf, words_to_read); base 330 drivers/spi/spi-qcom-qspi.c rd_fifo = readl(ctrl->base + RD_FIFO); base 350 drivers/spi/spi-qcom-qspi.c wr_fifo_bytes = readl(ctrl->base + PIO_XFER_STATUS); base 361 drivers/spi/spi-qcom-qspi.c ctrl->base + PIO_DATAOUT_1B); base 376 drivers/spi/spi-qcom-qspi.c iowrite32_rep(ctrl->base + PIO_DATAOUT_4B, word_buf, wr_size); base 393 drivers/spi/spi-qcom-qspi.c int_status = readl(ctrl->base + MSTR_INT_STATUS); base 394 drivers/spi/spi-qcom-qspi.c writel(int_status, ctrl->base + MSTR_INT_STATUS); base 415 drivers/spi/spi-qcom-qspi.c writel(0, ctrl->base + MSTR_INT_EN); base 442 drivers/spi/spi-qcom-qspi.c ctrl->base = devm_platform_ioremap_resource(pdev, 0); base 443 drivers/spi/spi-qcom-qspi.c if (IS_ERR(ctrl->base)) { base 444 drivers/spi/spi-qcom-qspi.c ret = PTR_ERR(ctrl->base); base 126 drivers/spi/spi-qup.c void __iomem *base; base 158 drivers/spi/spi-qup.c u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); base 179 drivers/spi/spi-qup.c u32 opstate = readl_relaxed(controller->base + QUP_STATE); base 202 drivers/spi/spi-qup.c cur_state = readl_relaxed(controller->base + QUP_STATE); base 209 drivers/spi/spi-qup.c writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); base 210 drivers/spi/spi-qup.c writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); base 214 drivers/spi/spi-qup.c writel_relaxed(cur_state, controller->base + QUP_STATE); base 237 drivers/spi/spi-qup.c word = readl_relaxed(controller->base + QUP_INPUT_FIFO); base 274 drivers/spi/spi-qup.c controller->base + QUP_OPERATIONAL); base 310 drivers/spi/spi-qup.c *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); base 313 drivers/spi/spi-qup.c controller->base + QUP_OPERATIONAL); base 337 drivers/spi/spi-qup.c writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); base 360 drivers/spi/spi-qup.c controller->base + QUP_OPERATIONAL); base 599 drivers/spi/spi-qup.c qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); base 600 drivers/spi/spi-qup.c spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); base 601 drivers/spi/spi-qup.c opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); base 603 drivers/spi/spi-qup.c writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); base 604 drivers/spi/spi-qup.c writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); base 634 drivers/spi/spi-qup.c writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); base 717 drivers/spi/spi-qup.c controller->base + QUP_MX_READ_CNT); base 719 drivers/spi/spi-qup.c controller->base + QUP_MX_WRITE_CNT); base 721 drivers/spi/spi-qup.c writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); base 722 drivers/spi/spi-qup.c writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); base 726 drivers/spi/spi-qup.c controller->base + QUP_MX_INPUT_CNT); base 728 drivers/spi/spi-qup.c controller->base + QUP_MX_OUTPUT_CNT); base 730 drivers/spi/spi-qup.c writel_relaxed(0, controller->base + QUP_MX_READ_CNT); base 731 drivers/spi/spi-qup.c writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); base 736 drivers/spi/spi-qup.c input_cnt = controller->base + QUP_MX_INPUT_CNT; base 748 drivers/spi/spi-qup.c writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); base 754 drivers/spi/spi-qup.c controller->base + QUP_MX_INPUT_CNT); base 756 drivers/spi/spi-qup.c controller->base + QUP_MX_OUTPUT_CNT); base 758 drivers/spi/spi-qup.c writel_relaxed(0, controller->base + QUP_MX_READ_CNT); base 759 drivers/spi/spi-qup.c writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); base 767 drivers/spi/spi-qup.c iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); base 779 drivers/spi/spi-qup.c writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); base 781 drivers/spi/spi-qup.c control = readl_relaxed(controller->base + SPI_IO_CONTROL); base 788 drivers/spi/spi-qup.c writel_relaxed(control, controller->base + SPI_IO_CONTROL); base 790 drivers/spi/spi-qup.c config = readl_relaxed(controller->base + SPI_CONFIG); base 811 drivers/spi/spi-qup.c writel_relaxed(config, controller->base + SPI_CONFIG); base 813 drivers/spi/spi-qup.c config = readl_relaxed(controller->base + QUP_CONFIG); base 825 drivers/spi/spi-qup.c writel_relaxed(config, controller->base + QUP_CONFIG); base 839 drivers/spi/spi-qup.c writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); base 926 drivers/spi/spi-qup.c static int spi_qup_init_dma(struct spi_master *master, resource_size_t base) base 948 drivers/spi/spi-qup.c rx_conf->src_addr = base + QUP_INPUT_FIFO; base 953 drivers/spi/spi-qup.c tx_conf->dst_addr = base + QUP_OUTPUT_FIFO; base 984 drivers/spi/spi-qup.c spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); base 992 drivers/spi/spi-qup.c writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); base 1002 drivers/spi/spi-qup.c void __iomem *base; base 1008 drivers/spi/spi-qup.c base = devm_ioremap_resource(dev, res); base 1009 drivers/spi/spi-qup.c if (IS_ERR(base)) base 1010 drivers/spi/spi-qup.c return PTR_ERR(base); base 1076 drivers/spi/spi-qup.c controller->base = base; base 1095 drivers/spi/spi-qup.c iomode = readl_relaxed(base + QUP_IO_M_MODES); base 1119 drivers/spi/spi-qup.c writel_relaxed(1, base + QUP_SW_RESET); base 1127 drivers/spi/spi-qup.c writel_relaxed(0, base + QUP_OPERATIONAL); base 1128 drivers/spi/spi-qup.c writel_relaxed(0, base + QUP_IO_M_MODES); base 1131 drivers/spi/spi-qup.c writel_relaxed(0, base + QUP_OPERATIONAL_MASK); base 1134 drivers/spi/spi-qup.c base + SPI_ERROR_FLAGS_EN); base 1140 drivers/spi/spi-qup.c base + QUP_ERROR_FLAGS_EN); base 1142 drivers/spi/spi-qup.c writel_relaxed(0, base + SPI_CONFIG); base 1143 drivers/spi/spi-qup.c writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL); base 1180 drivers/spi/spi-qup.c config = readl(controller->base + QUP_CONFIG); base 1182 drivers/spi/spi-qup.c writel_relaxed(config, controller->base + QUP_CONFIG); base 1206 drivers/spi/spi-qup.c config = readl_relaxed(controller->base + QUP_CONFIG); base 1208 drivers/spi/spi-qup.c writel_relaxed(config, controller->base + QUP_CONFIG); base 21 drivers/spi/spi-rb4xx.c void __iomem *base; base 27 drivers/spi/spi-rb4xx.c return __raw_readl(rbspi->base + reg); base 32 drivers/spi/spi-rb4xx.c __raw_writel(value, rbspi->base + reg); base 172 drivers/spi/spi-rb4xx.c rbspi->base = spi_base; base 255 drivers/spi/spi-sirf.c void __iomem *base; base 306 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->usp_mode1) & base 307 drivers/spi/spi-sirf.c ~SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1); base 308 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->usp_mode1) | base 309 drivers/spi/spi-sirf.c SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1); base 317 drivers/spi/spi-sirf.c data = readl(sspi->base + sspi->regs->rxfifo_data); base 336 drivers/spi/spi-sirf.c writel(data, sspi->base + sspi->regs->txfifo_data); base 345 drivers/spi/spi-sirf.c data = readl(sspi->base + sspi->regs->rxfifo_data); base 365 drivers/spi/spi-sirf.c writel(data, sspi->base + sspi->regs->txfifo_data); base 374 drivers/spi/spi-sirf.c data = readl(sspi->base + sspi->regs->rxfifo_data); base 395 drivers/spi/spi-sirf.c writel(data, sspi->base + sspi->regs->txfifo_data); base 404 drivers/spi/spi-sirf.c spi_stat = readl(sspi->base + sspi->regs->int_st); base 408 drivers/spi/spi-sirf.c writel(0x0, sspi->base + sspi->regs->int_en); base 409 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->int_st), base 410 drivers/spi/spi-sirf.c sspi->base + sspi->regs->int_st); base 421 drivers/spi/spi-sirf.c writel(0x0, sspi->base + sspi->regs->int_en); base 424 drivers/spi/spi-sirf.c writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); base 427 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->int_st), base 428 drivers/spi/spi-sirf.c sspi->base + sspi->regs->int_st); base 433 drivers/spi/spi-sirf.c while (!(readl(sspi->base + sspi->regs->int_st) & base 440 drivers/spi/spi-sirf.c writel(0x0, sspi->base + sspi->regs->int_en); base 443 drivers/spi/spi-sirf.c writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); base 446 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->int_st), base 447 drivers/spi/spi-sirf.c sspi->base + sspi->regs->int_st); base 467 drivers/spi/spi-sirf.c writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); base 468 drivers/spi/spi-sirf.c writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); base 476 drivers/spi/spi-sirf.c writel(cmd, sspi->base + sspi->regs->spi_cmd); base 478 drivers/spi/spi-sirf.c sspi->base + sspi->regs->int_en); base 480 drivers/spi/spi-sirf.c sspi->base + sspi->regs->tx_rx_en); base 496 drivers/spi/spi-sirf.c writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); base 497 drivers/spi/spi-sirf.c writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); base 501 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rxfifo_op); base 503 drivers/spi/spi-sirf.c sspi->base + sspi->regs->txfifo_op); base 504 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->int_en); base 507 drivers/spi/spi-sirf.c writel(0x0, sspi->base + sspi->regs->rxfifo_op); base 508 drivers/spi/spi-sirf.c writel(0x0, sspi->base + sspi->regs->txfifo_op); base 509 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->int_en); base 512 drivers/spi/spi-sirf.c writel(0x0, sspi->base + sspi->regs->rxfifo_op); base 513 drivers/spi/spi-sirf.c writel(0x0, sspi->base + sspi->regs->txfifo_op); base 514 drivers/spi/spi-sirf.c writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); base 517 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->int_st), base 518 drivers/spi/spi-sirf.c sspi->base + sspi->regs->int_st); base 522 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->spi_ctrl) | base 525 drivers/spi/spi-sirf.c sspi->base + sspi->regs->spi_ctrl); base 527 drivers/spi/spi-sirf.c sspi->base + sspi->regs->tx_dma_io_len); base 529 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rx_dma_io_len); base 535 drivers/spi/spi-sirf.c sspi->base + sspi->regs->tx_dma_io_len); base 537 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rx_dma_io_len); base 542 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->spi_ctrl), base 543 drivers/spi/spi-sirf.c sspi->base + sspi->regs->spi_ctrl); base 544 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->tx_dma_io_len); base 545 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->rx_dma_io_len); base 570 drivers/spi/spi-sirf.c sspi->base + sspi->regs->tx_rx_en); base 574 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rxfifo_op); base 576 drivers/spi/spi-sirf.c sspi->base + sspi->regs->txfifo_op); base 592 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->tx_rx_en); base 598 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->rxfifo_op); base 599 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->txfifo_op); base 601 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->tx_rx_en); base 604 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->tx_rx_en); base 617 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rxfifo_op); base 619 drivers/spi/spi-sirf.c sspi->base + sspi->regs->txfifo_op); base 622 drivers/spi/spi-sirf.c writel(0x0, sspi->base + sspi->regs->rxfifo_op); base 623 drivers/spi/spi-sirf.c writel(0x0, sspi->base + sspi->regs->txfifo_op); base 624 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->int_en); base 625 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->int_st), base 626 drivers/spi/spi-sirf.c sspi->base + sspi->regs->int_st); base 629 drivers/spi/spi-sirf.c sspi->base + sspi->regs->tx_dma_io_len); base 632 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rx_dma_io_len); base 635 drivers/spi/spi-sirf.c writel(0x0, sspi->base + sspi->regs->rxfifo_op); base 636 drivers/spi/spi-sirf.c writel(0x0, sspi->base + sspi->regs->txfifo_op); base 637 drivers/spi/spi-sirf.c writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); base 638 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->int_st), base 639 drivers/spi/spi-sirf.c sspi->base + sspi->regs->int_st); base 642 drivers/spi/spi-sirf.c sspi->base + sspi->regs->tx_dma_io_len); base 645 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rx_dma_io_len); base 649 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rxfifo_op); base 651 drivers/spi/spi-sirf.c sspi->base + sspi->regs->txfifo_op); base 652 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->int_en); base 653 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->int_st), base 654 drivers/spi/spi-sirf.c sspi->base + sspi->regs->int_st); base 655 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->spi_ctrl) | base 658 drivers/spi/spi-sirf.c sspi->base + sspi->regs->spi_ctrl); base 661 drivers/spi/spi-sirf.c sspi->base + sspi->regs->tx_dma_io_len); base 663 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rx_dma_io_len); base 666 drivers/spi/spi-sirf.c while (!((readl(sspi->base + sspi->regs->txfifo_st) base 674 drivers/spi/spi-sirf.c sspi->base + sspi->regs->int_en); base 676 drivers/spi/spi-sirf.c sspi->base + sspi->regs->tx_rx_en); base 680 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rxfifo_op); base 682 drivers/spi/spi-sirf.c sspi->base + sspi->regs->txfifo_op); base 689 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->tx_rx_en); base 692 drivers/spi/spi-sirf.c while (!((readl(sspi->base + sspi->regs->rxfifo_st) base 698 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->tx_rx_en); base 699 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->rxfifo_op); base 700 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->txfifo_op); base 738 drivers/spi/spi-sirf.c regval = readl(sspi->base + sspi->regs->spi_ctrl); base 753 drivers/spi/spi-sirf.c writel(regval, sspi->base + sspi->regs->spi_ctrl); base 757 drivers/spi/spi-sirf.c regval = readl(sspi->base + base 774 drivers/spi/spi-sirf.c sspi->base + sspi->regs->usp_pin_io_data); base 797 drivers/spi/spi-sirf.c regval = readl(sspi->base + sspi->regs->spi_ctrl); base 798 drivers/spi/spi-sirf.c usp_mode1 = readl(sspi->base + sspi->regs->usp_mode1); base 840 drivers/spi/spi-sirf.c sspi->base + sspi->regs->txfifo_level_chk); base 847 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rxfifo_level_chk); base 855 drivers/spi/spi-sirf.c writel(regval, sspi->base + sspi->regs->spi_ctrl); base 862 drivers/spi/spi-sirf.c writel(usp_mode1, sspi->base + sspi->regs->usp_mode1); base 919 drivers/spi/spi-sirf.c writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl); base 920 drivers/spi/spi-sirf.c writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl); base 947 drivers/spi/spi-sirf.c sspi->base + sspi->regs->usp_tx_frame_ctrl); base 951 drivers/spi/spi-sirf.c sspi->base + sspi->regs->usp_rx_frame_ctrl); base 952 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->usp_mode2) | base 959 drivers/spi/spi-sirf.c sspi->base + sspi->regs->usp_mode2); base 962 drivers/spi/spi-sirf.c writel(regval, sspi->base + sspi->regs->spi_ctrl); base 968 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->spi_ctrl) | base 971 drivers/spi/spi-sirf.c sspi->base + sspi->regs->spi_ctrl); base 974 drivers/spi/spi-sirf.c writel(readl(sspi->base + sspi->regs->spi_ctrl) & base 976 drivers/spi/spi-sirf.c sspi->base + sspi->regs->spi_ctrl); base 981 drivers/spi/spi-sirf.c writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl); base 983 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rx_dma_io_ctrl); base 987 drivers/spi/spi-sirf.c sspi->base + sspi->regs->tx_dma_io_ctrl); base 989 drivers/spi/spi-sirf.c sspi->base + sspi->regs->rx_dma_io_ctrl); base 1099 drivers/spi/spi-sirf.c sspi->base = devm_platform_ioremap_resource(pdev, 0); base 1100 drivers/spi/spi-sirf.c if (IS_ERR(sspi->base)) { base 1101 drivers/spi/spi-sirf.c ret = PTR_ERR(sspi->base); base 1211 drivers/spi/spi-sirf.c writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); base 1212 drivers/spi/spi-sirf.c writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); base 1213 drivers/spi/spi-sirf.c writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); base 1214 drivers/spi/spi-sirf.c writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op); base 68 drivers/spi/spi-slave-mt27xx.c void __iomem *base; base 85 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); base 88 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); base 95 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_CFG_REG); base 98 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_CFG_REG); base 123 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_CFG_REG); base 140 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_CFG_REG); base 152 drivers/spi/spi-slave-mt27xx.c writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG); base 154 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_CFG_REG); base 159 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_CFG_REG); base 163 drivers/spi/spi-slave-mt27xx.c iowrite32_rep(mdata->base + SPIS_TX_DATA_REG, base 170 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_TX_DATA_REG); base 176 drivers/spi/spi-slave-mt27xx.c writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG); base 190 drivers/spi/spi-slave-mt27xx.c writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG); base 215 drivers/spi/spi-slave-mt27xx.c writel(xfer->tx_dma, mdata->base + SPIS_TX_SRC_REG); base 216 drivers/spi/spi-slave-mt27xx.c writel(xfer->rx_dma, mdata->base + SPIS_RX_DST_REG); base 218 drivers/spi/spi-slave-mt27xx.c writel(SPIS_DMA_ADDR_EN, mdata->base + SPIS_SOFT_RST_REG); base 221 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_CFG_REG); base 226 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_CFG_REG); base 231 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); base 233 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); base 239 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); base 260 drivers/spi/spi-slave-mt27xx.c writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG); base 288 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_IRQ_EN_REG); base 292 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_IRQ_MASK_REG); base 317 drivers/spi/spi-slave-mt27xx.c int_status = readl(mdata->base + SPIS_IRQ_ST_REG); base 318 drivers/spi/spi-slave-mt27xx.c writel(int_status, mdata->base + SPIS_IRQ_CLR_REG); base 326 drivers/spi/spi-slave-mt27xx.c writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG); base 344 drivers/spi/spi-slave-mt27xx.c ioread32_rep(mdata->base + SPIS_RX_DATA_REG, base 348 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_RX_DATA_REG); base 405 drivers/spi/spi-slave-mt27xx.c mdata->base = devm_ioremap_resource(&pdev->dev, res); base 406 drivers/spi/spi-slave-mt27xx.c if (IS_ERR(mdata->base)) { base 407 drivers/spi/spi-slave-mt27xx.c ret = PTR_ERR(mdata->base); base 112 drivers/spi/spi-sprd-adi.c void __iomem *base; base 143 drivers/spi/spi-sprd-adi.c sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS); base 160 drivers/spi/spi-sprd-adi.c return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL; base 184 drivers/spi/spi-sprd-adi.c writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD); base 193 drivers/spi/spi-sprd-adi.c val = readl_relaxed(sadi->base + REG_ADI_RD_DATA); base 413 drivers/spi/spi-sprd-adi.c writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL); base 414 drivers/spi/spi-sprd-adi.c writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH); base 417 drivers/spi/spi-sprd-adi.c tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0); base 419 drivers/spi/spi-sprd-adi.c writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0); base 438 drivers/spi/spi-sprd-adi.c writel_relaxed(chn_config, sadi->base + base 442 drivers/spi/spi-sprd-adi.c value = readl_relaxed(sadi->base + REG_ADI_CHN_EN); base 444 drivers/spi/spi-sprd-adi.c writel_relaxed(value, sadi->base + REG_ADI_CHN_EN); base 446 drivers/spi/spi-sprd-adi.c value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1); base 448 drivers/spi/spi-sprd-adi.c writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1); base 478 drivers/spi/spi-sprd-adi.c sadi->base = devm_ioremap_resource(&pdev->dev, res); base 479 drivers/spi/spi-sprd-adi.c if (IS_ERR(sadi->base)) { base 480 drivers/spi/spi-sprd-adi.c ret = PTR_ERR(sadi->base); base 484 drivers/spi/spi-sprd-adi.c sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET; base 152 drivers/spi/spi-sprd.c void __iomem *base; base 200 drivers/spi/spi-sprd.c ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val, base 207 drivers/spi/spi-sprd.c ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val, base 214 drivers/spi/spi-sprd.c writel_relaxed(SPRD_SPI_TX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR); base 225 drivers/spi/spi-sprd.c ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val, base 232 drivers/spi/spi-sprd.c writel_relaxed(SPRD_SPI_RX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR); base 239 drivers/spi/spi-sprd.c writel_relaxed(SPRD_SPI_SW_TX_REQ, ss->base + SPRD_SPI_CTL12); base 244 drivers/spi/spi-sprd.c writel_relaxed(SPRD_SPI_SW_RX_REQ, ss->base + SPRD_SPI_CTL12); base 249 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1); base 252 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL1); base 257 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL0); base 262 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL0); base 267 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL8); base 272 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL8); base 275 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL9); base 280 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL10); base 285 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL10); base 288 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL11); base 297 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL0); base 301 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL0); base 304 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL0); base 313 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL4); base 315 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL4); base 318 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL4); base 320 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL4); base 323 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL4); base 325 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL4); base 336 drivers/spi/spi-sprd.c writeb_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD); base 348 drivers/spi/spi-sprd.c writew_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD); base 360 drivers/spi/spi-sprd.c writel_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD); base 372 drivers/spi/spi-sprd.c rx_p[i] = readb_relaxed(ss->base + SPRD_SPI_TXD); base 384 drivers/spi/spi-sprd.c rx_p[i] = readw_relaxed(ss->base + SPRD_SPI_TXD); base 396 drivers/spi/spi-sprd.c rx_p[i] = readl_relaxed(ss->base + SPRD_SPI_TXD); base 463 drivers/spi/spi-sprd.c ss->base + SPRD_SPI_INT_CLR); base 465 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_INT_EN); base 468 drivers/spi/spi-sprd.c ss->base + SPRD_SPI_INT_EN); base 473 drivers/spi/spi-sprd.c writel_relaxed(0, ss->base + SPRD_SPI_INT_EN); base 478 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL2); base 485 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL2); base 669 drivers/spi/spi-sprd.c writel_relaxed(clk_div, ss->base + SPRD_SPI_CLKD); base 677 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL0); base 682 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL0); base 693 drivers/spi/spi-sprd.c writel_relaxed(interval, ss->base + SPRD_SPI_CTL5); base 696 drivers/spi/spi-sprd.c writel_relaxed(1, ss->base + SPRD_SPI_FIFO_RST); base 697 drivers/spi/spi-sprd.c writel_relaxed(0, ss->base + SPRD_SPI_FIFO_RST); base 700 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL7); base 713 drivers/spi/spi-sprd.c writel_relaxed(val, ss->base + SPRD_SPI_CTL7); base 766 drivers/spi/spi-sprd.c val = readl_relaxed(ss->base + SPRD_SPI_CTL1); base 773 drivers/spi/spi-sprd.c writel_relaxed(val | mode, ss->base + SPRD_SPI_CTL1); base 816 drivers/spi/spi-sprd.c u32 val = readl_relaxed(ss->base + SPRD_SPI_INT_MASK_STS); base 819 drivers/spi/spi-sprd.c writel_relaxed(SPRD_SPI_TX_END_CLR, ss->base + SPRD_SPI_INT_CLR); base 827 drivers/spi/spi-sprd.c writel_relaxed(SPRD_SPI_RX_END_CLR, ss->base + SPRD_SPI_INT_CLR); base 931 drivers/spi/spi-sprd.c ss->base = devm_ioremap_resource(&pdev->dev, res); base 932 drivers/spi/spi-sprd.c if (IS_ERR(ss->base)) { base 933 drivers/spi/spi-sprd.c ret = PTR_ERR(ss->base); base 56 drivers/spi/spi-st-ssc4.c void __iomem *base; base 89 drivers/spi/spi-st-ssc4.c writel_relaxed(word, spi_st->base + SSC_TBUF); base 105 drivers/spi/spi-st-ssc4.c word = readl_relaxed(spi_st->base + SSC_RBUF); base 146 drivers/spi/spi-st-ssc4.c ctl = readl_relaxed(spi_st->base + SSC_CTL); base 147 drivers/spi/spi-st-ssc4.c writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL); base 149 drivers/spi/spi-st-ssc4.c readl_relaxed(spi_st->base + SSC_RBUF); base 160 drivers/spi/spi-st-ssc4.c writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN); base 167 drivers/spi/spi-st-ssc4.c writel_relaxed(ctl, spi_st->base + SSC_CTL); base 224 drivers/spi/spi-st-ssc4.c writel_relaxed(sscbrg, spi_st->base + SSC_BRG); base 231 drivers/spi/spi-st-ssc4.c var = readl_relaxed(spi_st->base + SSC_CTL); base 260 drivers/spi/spi-st-ssc4.c writel_relaxed(var, spi_st->base + SSC_CTL); base 263 drivers/spi/spi-st-ssc4.c readl_relaxed(spi_st->base + SSC_RBUF); base 285 drivers/spi/spi-st-ssc4.c writel_relaxed(0x0, spi_st->base + SSC_IEN); base 290 drivers/spi/spi-st-ssc4.c readl(spi_st->base + SSC_IEN); base 333 drivers/spi/spi-st-ssc4.c spi_st->base = devm_platform_ioremap_resource(pdev, 0); base 334 drivers/spi/spi-st-ssc4.c if (IS_ERR(spi_st->base)) { base 335 drivers/spi/spi-st-ssc4.c ret = PTR_ERR(spi_st->base); base 340 drivers/spi/spi-st-ssc4.c writel_relaxed(0x0, spi_st->base + SSC_I2C); base 341 drivers/spi/spi-st-ssc4.c var = readw_relaxed(spi_st->base + SSC_CTL); base 343 drivers/spi/spi-st-ssc4.c writel_relaxed(var, spi_st->base + SSC_CTL); base 346 drivers/spi/spi-st-ssc4.c var = readl_relaxed(spi_st->base + SSC_CTL); base 348 drivers/spi/spi-st-ssc4.c writel_relaxed(var, spi_st->base + SSC_CTL); base 351 drivers/spi/spi-st-ssc4.c var = readl_relaxed(spi_st->base + SSC_CTL); base 353 drivers/spi/spi-st-ssc4.c writel_relaxed(var, spi_st->base + SSC_CTL); base 411 drivers/spi/spi-st-ssc4.c writel_relaxed(0, spi_st->base + SSC_IEN); base 294 drivers/spi/spi-stm32.c void __iomem *base; base 356 drivers/spi/spi-stm32.c writel_relaxed(readl_relaxed(spi->base + offset) | bits, base 357 drivers/spi/spi-stm32.c spi->base + offset); base 363 drivers/spi/spi-stm32.c writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, base 364 drivers/spi/spi-stm32.c spi->base + offset); base 380 drivers/spi/spi-stm32.c while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) base 381 drivers/spi/spi-stm32.c writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); base 419 drivers/spi/spi-stm32.c cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); base 504 drivers/spi/spi-stm32.c if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & base 511 drivers/spi/spi-stm32.c writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); base 516 drivers/spi/spi-stm32.c writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); base 534 drivers/spi/spi-stm32.c (readl_relaxed(spi->base + STM32H7_SPI_SR) & base 541 drivers/spi/spi-stm32.c writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); base 546 drivers/spi/spi-stm32.c writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); base 551 drivers/spi/spi-stm32.c writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); base 568 drivers/spi/spi-stm32.c if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & base 575 drivers/spi/spi-stm32.c *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); base 580 drivers/spi/spi-stm32.c *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); base 597 drivers/spi/spi-stm32.c u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); base 610 drivers/spi/spi-stm32.c *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); base 616 drivers/spi/spi-stm32.c *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); base 621 drivers/spi/spi-stm32.c *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); base 625 drivers/spi/spi-stm32.c sr = readl_relaxed(spi->base + STM32H7_SPI_SR); base 659 drivers/spi/spi-stm32.c if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & base 671 drivers/spi/spi-stm32.c if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, base 688 drivers/spi/spi-stm32.c readl_relaxed(spi->base + STM32F4_SPI_DR); base 689 drivers/spi/spi-stm32.c readl_relaxed(spi->base + STM32F4_SPI_SR); base 715 drivers/spi/spi-stm32.c cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); base 723 drivers/spi/spi-stm32.c if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR, base 728 drivers/spi/spi-stm32.c spi->base + STM32H7_SPI_CR1); base 730 drivers/spi/spi-stm32.c spi->base + STM32H7_SPI_SR, base 752 drivers/spi/spi-stm32.c writel_relaxed(0, spi->base + STM32H7_SPI_IER); base 753 drivers/spi/spi-stm32.c writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); base 797 drivers/spi/spi-stm32.c sr = readl_relaxed(spi->base + STM32F4_SPI_SR); base 827 drivers/spi/spi-stm32.c readl_relaxed(spi->base + STM32F4_SPI_DR); base 828 drivers/spi/spi-stm32.c readl_relaxed(spi->base + STM32F4_SPI_SR); base 900 drivers/spi/spi-stm32.c sr = readl_relaxed(spi->base + STM32H7_SPI_SR); base 901 drivers/spi/spi-stm32.c ier = readl_relaxed(spi->base + STM32H7_SPI_IER); base 964 drivers/spi/spi-stm32.c writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR); base 1042 drivers/spi/spi-stm32.c (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & base 1044 drivers/spi/spi-stm32.c spi->base + spi->cfg->regs->cpol.reg); base 1093 drivers/spi/spi-stm32.c sr = readl_relaxed(spi->base + STM32H7_SPI_SR); base 1224 drivers/spi/spi-stm32.c writel_relaxed(ier, spi->base + STM32H7_SPI_IER); base 1406 drivers/spi/spi-stm32.c (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & base 1408 drivers/spi/spi-stm32.c spi->base + STM32H7_SPI_CFG1); base 1424 drivers/spi/spi-stm32.c writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & base 1426 drivers/spi/spi-stm32.c spi->base + spi->cfg->regs->br.reg); base 1511 drivers/spi/spi-stm32.c (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & base 1513 drivers/spi/spi-stm32.c spi->base + STM32H7_SPI_CFG2); base 1541 drivers/spi/spi-stm32.c writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & base 1543 drivers/spi/spi-stm32.c spi->base + STM32H7_SPI_CFG2); base 1559 drivers/spi/spi-stm32.c writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) & base 1561 drivers/spi/spi-stm32.c spi->base + STM32H7_SPI_CR2); base 1832 drivers/spi/spi-stm32.c spi->base = devm_ioremap_resource(&pdev->dev, res); base 1833 drivers/spi/spi-stm32.c if (IS_ERR(spi->base)) { base 1834 drivers/spi/spi-stm32.c ret = PTR_ERR(spi->base); base 173 drivers/spi/spi-tegra114.c void __iomem *base; base 230 drivers/spi/spi-tegra114.c return readl(tspi->base + reg); base 236 drivers/spi/spi-tegra114.c writel(val, tspi->base + reg); base 240 drivers/spi/spi-tegra114.c readl(tspi->base + SPI_COMMAND1); base 1346 drivers/spi/spi-tegra114.c tspi->base = devm_ioremap_resource(&pdev->dev, r); base 1347 drivers/spi/spi-tegra114.c if (IS_ERR(tspi->base)) { base 1348 drivers/spi/spi-tegra114.c ret = PTR_ERR(tspi->base); base 110 drivers/spi/spi-tegra20-sflash.c void __iomem *base; base 142 drivers/spi/spi-tegra20-sflash.c return readl(tsd->base + reg); base 148 drivers/spi/spi-tegra20-sflash.c writel(val, tsd->base + reg); base 453 drivers/spi/spi-tegra20-sflash.c tsd->base = devm_platform_ioremap_resource(pdev, 0); base 454 drivers/spi/spi-tegra20-sflash.c if (IS_ERR(tsd->base)) { base 455 drivers/spi/spi-tegra20-sflash.c ret = PTR_ERR(tsd->base); base 159 drivers/spi/spi-tegra20-slink.c void __iomem *base; base 213 drivers/spi/spi-tegra20-slink.c return readl(tspi->base + reg); base 219 drivers/spi/spi-tegra20-slink.c writel(val, tspi->base + reg); base 223 drivers/spi/spi-tegra20-slink.c readl(tspi->base + SLINK_MAS_DATA); base 1055 drivers/spi/spi-tegra20-slink.c tspi->base = devm_ioremap_resource(&pdev->dev, r); base 1056 drivers/spi/spi-tegra20-slink.c if (IS_ERR(tspi->base)) { base 1057 drivers/spi/spi-tegra20-slink.c ret = PTR_ERR(tspi->base); base 45 drivers/spi/spi-ti-qspi.c void __iomem *base; base 133 drivers/spi/spi-ti-qspi.c return readl(qspi->base + reg); base 139 drivers/spi/spi-ti-qspi.c writel(val, qspi->base + reg); base 270 drivers/spi/spi-ti-qspi.c writel(data, qspi->base + base 273 drivers/spi/spi-ti-qspi.c writel(data, qspi->base + base 276 drivers/spi/spi-ti-qspi.c writel(data, qspi->base + base 279 drivers/spi/spi-ti-qspi.c writel(data, qspi->base + base 284 drivers/spi/spi-ti-qspi.c writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); base 293 drivers/spi/spi-ti-qspi.c writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); base 298 drivers/spi/spi-ti-qspi.c writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); base 348 drivers/spi/spi-ti-qspi.c *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG); base 351 drivers/spi/spi-ti-qspi.c *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); base 354 drivers/spi/spi-ti-qspi.c *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); base 729 drivers/spi/spi-ti-qspi.c qspi->base = devm_ioremap_resource(&pdev->dev, r); base 730 drivers/spi/spi-ti-qspi.c if (IS_ERR(qspi->base)) { base 731 drivers/spi/spi-ti-qspi.c ret = PTR_ERR(qspi->base); base 25 drivers/spi/spi-uniphier.c void __iomem *base; base 101 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_IE); base 103 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_IE); base 111 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_IE); base 113 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_IE); base 159 drivers/spi/spi-uniphier.c writel(val1, priv->base + SSI_CKS); base 160 drivers/spi/spi-uniphier.c writel(val2, priv->base + SSI_FPS); base 165 drivers/spi/spi-uniphier.c writel(val1, priv->base + SSI_TXWDS); base 166 drivers/spi/spi-uniphier.c writel(val1, priv->base + SSI_RXWDS); base 174 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_TXWDS); base 178 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_TXWDS); base 180 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_RXWDS); base 183 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_RXWDS); base 199 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_CKS); base 202 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_CKS); base 236 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_FC); base 263 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_TXDR); base 274 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_RXDR); base 298 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_FC); base 302 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_FC); base 327 drivers/spi/spi-uniphier.c val = readl(priv->base + SSI_FPS); base 334 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_FPS); base 375 drivers/spi/spi-uniphier.c while (!(readl(priv->base + SSI_SR) & SSI_SR_RNE) base 421 drivers/spi/spi-uniphier.c writel(SSI_CTL_EN, priv->base + SSI_CTL); base 430 drivers/spi/spi-uniphier.c writel(0, priv->base + SSI_CTL); base 440 drivers/spi/spi-uniphier.c stat = readl(priv->base + SSI_IS); base 442 drivers/spi/spi-uniphier.c writel(val, priv->base + SSI_IC); base 452 drivers/spi/spi-uniphier.c while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) && base 456 drivers/spi/spi-uniphier.c if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) || base 494 drivers/spi/spi-uniphier.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 495 drivers/spi/spi-uniphier.c if (IS_ERR(priv->base)) { base 496 drivers/spi/spi-uniphier.c ret = PTR_ERR(priv->base); base 92 drivers/spi/spi-xlp.c void __iomem *base; /* spi registers base address */ base 108 drivers/spi/spi-xlp.c return readl(priv->base + regoff + cs * SPI_CS_OFFSET); base 114 drivers/spi/spi-xlp.c writel(val, priv->base + regoff + cs * SPI_CS_OFFSET); base 120 drivers/spi/spi-xlp.c writel(val, priv->base + regoff); base 380 drivers/spi/spi-xlp.c xspi->base = devm_platform_ioremap_resource(pdev, 0); base 381 drivers/spi/spi-xlp.c if (IS_ERR(xspi->base)) base 382 drivers/spi/spi-xlp.c return PTR_ERR(xspi->base); base 243 drivers/spmi/spmi-pmic-arb.c void __iomem *base, u8 sid, u16 addr, base 260 drivers/spmi/spmi-pmic-arb.c status = readl_relaxed(base + offset); base 174 drivers/ssb/driver_gige.c u32 base, tmslow, tmshigh; base 198 drivers/ssb/driver_gige.c base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1)); base 199 drivers/ssb/driver_gige.c gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base); base 203 drivers/ssb/driver_gige.c dev->mem_resource.start = base; base 204 drivers/ssb/driver_gige.c dev->mem_resource.end = base + 0x10000 - 1; base 236 drivers/ssb/driver_gpio.c chip->base = 0; base 238 drivers/ssb/driver_gpio.c chip->base = -1; base 429 drivers/ssb/driver_gpio.c chip->base = 0; base 431 drivers/ssb/driver_gpio.c chip->base = -1; base 1234 drivers/ssb/main.c u32 base = 0; base 1238 drivers/ssb/main.c base = (adm & SSB_ADM_BASE0); base 1242 drivers/ssb/main.c base = (adm & SSB_ADM_BASE1); base 1246 drivers/ssb/main.c base = (adm & SSB_ADM_BASE2); base 1252 drivers/ssb/main.c return base; base 60 drivers/staging/board/board.c unsigned int base) base 70 drivers/staging/board/board.c irqc_base = base; base 28 drivers/staging/board/board.h int board_staging_gic_setup_xlate(const char *gic_match, unsigned int base); base 55 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c void __iomem *base; base 147 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c clk_wzrd->base = devm_ioremap_resource(&pdev->dev, mem); base 148 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c if (IS_ERR(clk_wzrd->base)) base 149 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c return PTR_ERR(clk_wzrd->base); base 187 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & base 189 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg |= readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2)) & base 195 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & base 214 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & base 243 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2) + i * 12); base 1009 drivers/staging/comedi/comedi.h #define _TERM_N(base, n, x) ((base) + ((x) & ((n) - 1))) base 465 drivers/staging/comedi/drivers/addi_apci_3xxx.c unsigned int base; base 477 drivers/staging/comedi/drivers/addi_apci_3xxx.c base = 1; base 480 drivers/staging/comedi/drivers/addi_apci_3xxx.c base = 1000; base 483 drivers/staging/comedi/drivers/addi_apci_3xxx.c base = 1000000; base 490 drivers/staging/comedi/drivers/addi_apci_3xxx.c timer = DIV_ROUND_CLOSEST(*ns, base); base 493 drivers/staging/comedi/drivers/addi_apci_3xxx.c timer = *ns / base; base 496 drivers/staging/comedi/drivers/addi_apci_3xxx.c timer = DIV_ROUND_UP(*ns, base); base 368 drivers/staging/comedi/drivers/dt282x.c unsigned int prescale, base, divider; base 373 drivers/staging/comedi/drivers/dt282x.c base = DT2821_OSC_BASE * DT2821_PRESCALE(prescale); base 377 drivers/staging/comedi/drivers/dt282x.c divider = DIV_ROUND_CLOSEST(*ns, base); base 380 drivers/staging/comedi/drivers/dt282x.c divider = (*ns) / base; base 383 drivers/staging/comedi/drivers/dt282x.c divider = DIV_ROUND_UP(*ns, base); base 392 drivers/staging/comedi/drivers/dt282x.c base = DT2821_OSC_BASE * DT2821_PRESCALE(prescale); base 394 drivers/staging/comedi/drivers/dt282x.c *ns = divider * base; base 345 drivers/staging/comedi/drivers/dt3000.c unsigned int divider, base, prescale; base 351 drivers/staging/comedi/drivers/dt3000.c base = timer_base * (prescale + 1); base 355 drivers/staging/comedi/drivers/dt3000.c divider = DIV_ROUND_CLOSEST(*nanosec, base); base 358 drivers/staging/comedi/drivers/dt3000.c divider = (*nanosec) / base; base 361 drivers/staging/comedi/drivers/dt3000.c divider = DIV_ROUND_UP(*nanosec, base); base 365 drivers/staging/comedi/drivers/dt3000.c *nanosec = divider * base; base 371 drivers/staging/comedi/drivers/dt3000.c base = timer_base * (prescale + 1); base 373 drivers/staging/comedi/drivers/dt3000.c *nanosec = divider * base; base 133 drivers/staging/comedi/drivers/ni_mio_cs.c int base, ret; base 138 drivers/staging/comedi/drivers/ni_mio_cs.c for (base = 0x000; base < 0x400; base += 0x20) { base 139 drivers/staging/comedi/drivers/ni_mio_cs.c p_dev->resource[0]->start = base; base 507 drivers/staging/comedi/drivers/ni_pcidio.c int divider, base; base 509 drivers/staging/comedi/drivers/ni_pcidio.c base = TIMER_BASE; base 514 drivers/staging/comedi/drivers/ni_pcidio.c divider = DIV_ROUND_CLOSEST(*nanosec, base); base 517 drivers/staging/comedi/drivers/ni_pcidio.c divider = (*nanosec) / base; base 520 drivers/staging/comedi/drivers/ni_pcidio.c divider = DIV_ROUND_UP(*nanosec, base); base 524 drivers/staging/comedi/drivers/ni_pcidio.c *nanosec = base * divider; base 375 drivers/staging/comedi/drivers/rtd520.c unsigned int flags, int base) base 382 drivers/staging/comedi/drivers/rtd520.c divider = DIV_ROUND_CLOSEST(*nanosec, base); base 385 drivers/staging/comedi/drivers/rtd520.c divider = (*nanosec) / base; base 388 drivers/staging/comedi/drivers/rtd520.c divider = DIV_ROUND_UP(*nanosec, base); base 399 drivers/staging/comedi/drivers/rtd520.c *nanosec = base * divider; base 1629 drivers/staging/comedi/drivers/s626.c int divider, base; base 1631 drivers/staging/comedi/drivers/s626.c base = 500; /* 2MHz internal clock */ base 1636 drivers/staging/comedi/drivers/s626.c divider = DIV_ROUND_CLOSEST(*nanosec, base); base 1639 drivers/staging/comedi/drivers/s626.c divider = (*nanosec) / base; base 1642 drivers/staging/comedi/drivers/s626.c divider = DIV_ROUND_UP(*nanosec, base); base 1646 drivers/staging/comedi/drivers/s626.c *nanosec = base * divider; base 5 drivers/staging/fbtft/fbtft-sysfs.c static int get_next_ulong(char **str_p, unsigned long *val, char *sep, int base) base 17 drivers/staging/fbtft/fbtft-sysfs.c return kstrtoul(p_val, base, val); base 131 drivers/staging/fieldbus/anybuss/arcx-anybus.c void __iomem *base; base 135 drivers/staging/fieldbus/anybuss/arcx-anybus.c base = devm_ioremap_resource(dev, res); base 136 drivers/staging/fieldbus/anybuss/arcx-anybus.c if (IS_ERR(base)) base 137 drivers/staging/fieldbus/anybuss/arcx-anybus.c return ERR_CAST(base); base 138 drivers/staging/fieldbus/anybuss/arcx-anybus.c return devm_regmap_init_mmio(dev, base, &arcx_regmap_cfg); base 77 drivers/staging/fsl-dpaa2/ethsw/ethsw-ethtool.c link_ksettings->base.autoneg = AUTONEG_ENABLE; base 79 drivers/staging/fsl-dpaa2/ethsw/ethsw-ethtool.c link_ksettings->base.duplex = DUPLEX_FULL; base 80 drivers/staging/fsl-dpaa2/ethsw/ethsw-ethtool.c link_ksettings->base.speed = state.rate; base 108 drivers/staging/fsl-dpaa2/ethsw/ethsw-ethtool.c cfg.rate = link_ksettings->base.speed; base 109 drivers/staging/fsl-dpaa2/ethsw/ethsw-ethtool.c if (link_ksettings->base.autoneg == AUTONEG_ENABLE) base 113 drivers/staging/fsl-dpaa2/ethsw/ethsw-ethtool.c if (link_ksettings->base.duplex == DUPLEX_HALF) base 335 drivers/staging/gasket/gasket_core.c ulong base, bytes; base 350 drivers/staging/gasket/gasket_core.c base = pci_resource_start(dev->pci_dev, bar_num); base 351 drivers/staging/gasket/gasket_core.c if (!base) { base 358 drivers/staging/gasket/gasket_core.c release_mem_region(base, bytes); base 502 drivers/staging/gasket/gasket_core.c (ulong)bar_desc->base); base 724 drivers/staging/gasket/gasket_core.c if ((address >= coh_buff_desc.base) && base 725 drivers/staging/gasket/gasket_core.c (address < coh_buff_desc.base + coh_buff_desc.size)) { base 744 drivers/staging/gasket/gasket_core.c if (phys_addr >= bar_desc.base && base 745 drivers/staging/gasket/gasket_core.c phys_addr < (bar_desc.base + bar_desc.size)) { base 855 drivers/staging/gasket/gasket_core.c raw_offset - driver_desc->bar_descriptions[bar_index].base; base 197 drivers/staging/gasket/gasket_core.h u64 base; base 220 drivers/staging/gasket/gasket_core.h u64 base; base 1288 drivers/staging/gasket/gasket_page_table.c *dma_address = driver_desc->coherent_buffer_description.base; base 1324 drivers/staging/gasket/gasket_page_table.c if (driver_desc->coherent_buffer_description.base != dma_address) base 563 drivers/staging/greybus/gpio.c gpio->base = -1; /* Allocate base dynamically */ base 284 drivers/staging/greybus/pwm.c pwm->base = -1; /* Allocate base dynamically */ base 219 drivers/staging/isdn/avm/avmcard.h static inline unsigned char b1outp(unsigned int base, base 223 drivers/staging/isdn/avm/avmcard.h outb(value, base + offset); base 224 drivers/staging/isdn/avm/avmcard.h return inb(base + B1_ANALYSE); base 228 drivers/staging/isdn/avm/avmcard.h static inline int b1_rx_full(unsigned int base) base 230 drivers/staging/isdn/avm/avmcard.h return inb(base + B1_INSTAT) & 0x1; base 233 drivers/staging/isdn/avm/avmcard.h static inline unsigned char b1_get_byte(unsigned int base) base 236 drivers/staging/isdn/avm/avmcard.h while (!b1_rx_full(base) && time_before(jiffies, stop)); base 237 drivers/staging/isdn/avm/avmcard.h if (b1_rx_full(base)) base 238 drivers/staging/isdn/avm/avmcard.h return inb(base + B1_READ); base 239 drivers/staging/isdn/avm/avmcard.h printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base); base 243 drivers/staging/isdn/avm/avmcard.h static inline unsigned int b1_get_word(unsigned int base) base 246 drivers/staging/isdn/avm/avmcard.h val |= b1_get_byte(base); base 247 drivers/staging/isdn/avm/avmcard.h val |= (b1_get_byte(base) << 8); base 248 drivers/staging/isdn/avm/avmcard.h val |= (b1_get_byte(base) << 16); base 249 drivers/staging/isdn/avm/avmcard.h val |= (b1_get_byte(base) << 24); base 253 drivers/staging/isdn/avm/avmcard.h static inline int b1_tx_empty(unsigned int base) base 255 drivers/staging/isdn/avm/avmcard.h return inb(base + B1_OUTSTAT) & 0x1; base 258 drivers/staging/isdn/avm/avmcard.h static inline void b1_put_byte(unsigned int base, unsigned char val) base 260 drivers/staging/isdn/avm/avmcard.h while (!b1_tx_empty(base)); base 261 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_WRITE, val); base 264 drivers/staging/isdn/avm/avmcard.h static inline int b1_save_put_byte(unsigned int base, unsigned char val) base 267 drivers/staging/isdn/avm/avmcard.h while (!b1_tx_empty(base) && time_before(jiffies, stop)); base 268 drivers/staging/isdn/avm/avmcard.h if (!b1_tx_empty(base)) return -1; base 269 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_WRITE, val); base 273 drivers/staging/isdn/avm/avmcard.h static inline void b1_put_word(unsigned int base, unsigned int val) base 275 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, val & 0xff); base 276 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, (val >> 8) & 0xff); base 277 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, (val >> 16) & 0xff); base 278 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, (val >> 24) & 0xff); base 281 drivers/staging/isdn/avm/avmcard.h static inline unsigned int b1_get_slice(unsigned int base, base 286 drivers/staging/isdn/avm/avmcard.h len = i = b1_get_word(base); base 287 drivers/staging/isdn/avm/avmcard.h while (i-- > 0) *dp++ = b1_get_byte(base); base 291 drivers/staging/isdn/avm/avmcard.h static inline void b1_put_slice(unsigned int base, base 295 drivers/staging/isdn/avm/avmcard.h b1_put_word(base, i); base 297 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, *dp++); base 300 drivers/staging/isdn/avm/avmcard.h static void b1_wr_reg(unsigned int base, base 304 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, WRITE_REGISTER); base 305 drivers/staging/isdn/avm/avmcard.h b1_put_word(base, reg); base 306 drivers/staging/isdn/avm/avmcard.h b1_put_word(base, value); base 309 drivers/staging/isdn/avm/avmcard.h static inline unsigned int b1_rd_reg(unsigned int base, base 312 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, READ_REGISTER); base 313 drivers/staging/isdn/avm/avmcard.h b1_put_word(base, reg); base 314 drivers/staging/isdn/avm/avmcard.h return b1_get_word(base); base 318 drivers/staging/isdn/avm/avmcard.h static inline void b1_reset(unsigned int base) base 320 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_RESET, 0); base 323 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_RESET, 1); base 326 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_RESET, 0); base 330 drivers/staging/isdn/avm/avmcard.h static inline unsigned char b1_disable_irq(unsigned int base) base 332 drivers/staging/isdn/avm/avmcard.h return b1outp(base, B1_INSTAT, 0x00); base 337 drivers/staging/isdn/avm/avmcard.h static inline void b1_set_test_bit(unsigned int base, base 341 drivers/staging/isdn/avm/avmcard.h b1_wr_reg(base, B1_STAT0(cardtype), onoff ? 0x21 : 0x20); base 344 drivers/staging/isdn/avm/avmcard.h static inline int b1_get_test_bit(unsigned int base, base 347 drivers/staging/isdn/avm/avmcard.h return (b1_rd_reg(base, B1_STAT0(cardtype)) & 0x01) != 0; base 386 drivers/staging/isdn/avm/avmcard.h static inline void t1outp(unsigned int base, base 390 drivers/staging/isdn/avm/avmcard.h outb(value, base + offset); base 393 drivers/staging/isdn/avm/avmcard.h static inline unsigned char t1inp(unsigned int base, base 396 drivers/staging/isdn/avm/avmcard.h return inb(base + offset); base 399 drivers/staging/isdn/avm/avmcard.h static inline int t1_isfastlink(unsigned int base) base 401 drivers/staging/isdn/avm/avmcard.h return (inb(base + T1_IDENT) & ~0x82) == 1; base 404 drivers/staging/isdn/avm/avmcard.h static inline unsigned char t1_fifostatus(unsigned int base) base 406 drivers/staging/isdn/avm/avmcard.h return inb(base + T1_FIFOSTAT); base 409 drivers/staging/isdn/avm/avmcard.h static inline unsigned int t1_get_slice(unsigned int base, base 417 drivers/staging/isdn/avm/avmcard.h len = i = b1_get_word(base); base 418 drivers/staging/isdn/avm/avmcard.h if (t1_isfastlink(base)) { base 421 drivers/staging/isdn/avm/avmcard.h status = t1_fifostatus(base) & (T1F_IREADY | T1F_IHALF); base 426 drivers/staging/isdn/avm/avmcard.h insb(base + B1_READ, dp, FIFO_INPBSIZE); base 434 drivers/staging/isdn/avm/avmcard.h insb(base + B1_READ, dp, i); base 442 drivers/staging/isdn/avm/avmcard.h *dp++ = b1_get_byte(base); base 453 drivers/staging/isdn/avm/avmcard.h base, len, wcnt, bcnt); base 457 drivers/staging/isdn/avm/avmcard.h *dp++ = b1_get_byte(base); base 462 drivers/staging/isdn/avm/avmcard.h static inline void t1_put_slice(unsigned int base, base 466 drivers/staging/isdn/avm/avmcard.h b1_put_word(base, i); base 467 drivers/staging/isdn/avm/avmcard.h if (t1_isfastlink(base)) { base 470 drivers/staging/isdn/avm/avmcard.h status = t1_fifostatus(base) & (T1F_OREADY | T1F_OHALF); base 474 drivers/staging/isdn/avm/avmcard.h outsb(base + B1_WRITE, dp, FIFO_OUTBSIZE); base 479 drivers/staging/isdn/avm/avmcard.h outsb(base + B1_WRITE, dp, i); base 484 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, *dp++); base 491 drivers/staging/isdn/avm/avmcard.h b1_put_byte(base, *dp++); base 495 drivers/staging/isdn/avm/avmcard.h static inline void t1_disable_irq(unsigned int base) base 497 drivers/staging/isdn/avm/avmcard.h t1outp(base, T1_IRQMASTER, 0x00); base 500 drivers/staging/isdn/avm/avmcard.h static inline void t1_reset(unsigned int base) base 503 drivers/staging/isdn/avm/avmcard.h b1_reset(base); base 505 drivers/staging/isdn/avm/avmcard.h t1outp(base, B1_INSTAT, 0x00); base 506 drivers/staging/isdn/avm/avmcard.h t1outp(base, B1_OUTSTAT, 0x00); base 507 drivers/staging/isdn/avm/avmcard.h t1outp(base, T1_IRQMASTER, 0x00); base 509 drivers/staging/isdn/avm/avmcard.h t1outp(base, T1_RESETBOARD, 0xf); base 512 drivers/staging/isdn/avm/avmcard.h static inline void b1_setinterrupt(unsigned int base, unsigned irq, base 517 drivers/staging/isdn/avm/avmcard.h t1outp(base, B1_INSTAT, 0x00); base 518 drivers/staging/isdn/avm/avmcard.h t1outp(base, B1_INSTAT, 0x02); base 519 drivers/staging/isdn/avm/avmcard.h t1outp(base, T1_IRQMASTER, 0x08); base 522 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_INSTAT, 0x00); base 523 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_RESET, b1_irq_table[irq]); base 524 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_INSTAT, 0x02); base 530 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_INSTAT, 0x00); base 531 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_RESET, 0xf0); base 532 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_INSTAT, 0x02); base 536 drivers/staging/isdn/avm/avmcard.h b1outp(base, B1_RESET, 0xf0); base 544 drivers/staging/isdn/avm/avmcard.h int b1_detect(unsigned int base, enum avmcardtype cardtype); base 102 drivers/staging/isdn/avm/b1.c int b1_detect(unsigned int base, enum avmcardtype cardtype) base 109 drivers/staging/isdn/avm/b1.c if ((inb(base + B1_INSTAT) & 0xfc) base 110 drivers/staging/isdn/avm/b1.c || (inb(base + B1_OUTSTAT) & 0xfc)) base 115 drivers/staging/isdn/avm/b1.c b1outp(base, B1_INSTAT, 0x2); /* enable irq */ base 117 drivers/staging/isdn/avm/b1.c if ((inb(base + B1_INSTAT) & 0xfe) != 0x2 base 123 drivers/staging/isdn/avm/b1.c b1outp(base, B1_INSTAT, 0x0); /* disable irq */ base 124 drivers/staging/isdn/avm/b1.c b1outp(base, B1_OUTSTAT, 0x0); base 125 drivers/staging/isdn/avm/b1.c if ((inb(base + B1_INSTAT) & 0xfe) base 126 drivers/staging/isdn/avm/b1.c || (inb(base + B1_OUTSTAT) & 0xfe)) base 130 drivers/staging/isdn/avm/b1.c b1_set_test_bit(base, cardtype, onoff); base 131 drivers/staging/isdn/avm/b1.c if (b1_get_test_bit(base, cardtype) != onoff) base 139 drivers/staging/isdn/avm/b1.c if ((b1_rd_reg(base, B1_STAT1(cardtype)) & 0x0f) != 0x01) base 157 drivers/staging/isdn/avm/b1.c unsigned int base = card->port; base 169 drivers/staging/isdn/avm/b1.c if (b1_save_put_byte(base, buf[i]) < 0) { base 185 drivers/staging/isdn/avm/b1.c if (b1_save_put_byte(base, buf[i]) < 0) { base 198 drivers/staging/isdn/avm/b1.c unsigned int base = card->port; base 204 drivers/staging/isdn/avm/b1.c b1_put_byte(base, SEND_CONFIG); base 205 drivers/staging/isdn/avm/b1.c b1_put_word(base, 1); base 206 drivers/staging/isdn/avm/b1.c b1_put_byte(base, SEND_CONFIG); base 207 drivers/staging/isdn/avm/b1.c b1_put_word(base, left); base 217 drivers/staging/isdn/avm/b1.c b1_put_byte(base, SEND_CONFIG); base 219 drivers/staging/isdn/avm/b1.c b1_put_byte(base, buf[i++]); base 233 drivers/staging/isdn/avm/b1.c b1_put_byte(base, SEND_CONFIG); base 236 drivers/staging/isdn/avm/b1.c b1_put_byte(base, buf[i++]); base 238 drivers/staging/isdn/avm/b1.c b1_put_byte(base, 0); base 247 drivers/staging/isdn/avm/b1.c unsigned int base = card->port; base 253 drivers/staging/isdn/avm/b1.c if (b1_tx_empty(base)) base 256 drivers/staging/isdn/avm/b1.c if (!b1_tx_empty(base)) { base 261 drivers/staging/isdn/avm/b1.c b1_put_byte(base, SEND_POLL); base 263 drivers/staging/isdn/avm/b1.c if (b1_rx_full(base)) { base 264 drivers/staging/isdn/avm/b1.c if ((ans = b1_get_byte(base)) == RECEIVE_POLL) { base 654 drivers/staging/isdn/avm/b1dma.c unsigned int base = card->port; base 657 drivers/staging/isdn/avm/b1dma.c if (b1_tx_empty(base)) base 660 drivers/staging/isdn/avm/b1dma.c if (!b1_tx_empty(base)) { base 665 drivers/staging/isdn/avm/b1dma.c b1_put_byte(base, SEND_POLLACK); base 667 drivers/staging/isdn/avm/b1dma.c if (b1_rx_full(base)) { base 668 drivers/staging/isdn/avm/b1dma.c if ((ans = b1_get_byte(base)) == RECEIVE_POLLDWORD) { base 62 drivers/staging/isdn/avm/t1isa.c static int t1_detectandinit(unsigned int base, unsigned irq, int cardnr) base 87 drivers/staging/isdn/avm/t1isa.c t1outp(base, T1_RESETBOARD, 0xf); base 89 drivers/staging/isdn/avm/t1isa.c dummy = t1inp(base, T1_FASTLINK + T1_OUTSTAT); /* first read */ base 92 drivers/staging/isdn/avm/t1isa.c dummy = (base >> 4) & 0xff; base 93 drivers/staging/isdn/avm/t1isa.c for (i = 1; i <= 0xf; i++) t1outp(base, i, dummy); base 94 drivers/staging/isdn/avm/t1isa.c t1outp(base, HEMA_PAL_ID & 0xf, dummy); base 95 drivers/staging/isdn/avm/t1isa.c t1outp(base, HEMA_PAL_ID >> 4, cregs[0]); base 96 drivers/staging/isdn/avm/t1isa.c for (i = 1; i < 7; i++) t1outp(base, 0, cregs[i]); base 97 drivers/staging/isdn/avm/t1isa.c t1outp(base, ((base >> 4)) & 0x3, cregs[7]); base 101 drivers/staging/isdn/avm/t1isa.c t1outp(base, T1_FASTLINK + T1_RESETLINK, 0); base 102 drivers/staging/isdn/avm/t1isa.c t1outp(base, T1_SLOWLINK + T1_RESETLINK, 0); base 104 drivers/staging/isdn/avm/t1isa.c t1outp(base, T1_FASTLINK + T1_RESETLINK, 1); base 105 drivers/staging/isdn/avm/t1isa.c t1outp(base, T1_SLOWLINK + T1_RESETLINK, 1); base 107 drivers/staging/isdn/avm/t1isa.c t1outp(base, T1_FASTLINK + T1_RESETLINK, 0); base 108 drivers/staging/isdn/avm/t1isa.c t1outp(base, T1_SLOWLINK + T1_RESETLINK, 0); base 110 drivers/staging/isdn/avm/t1isa.c t1outp(base, T1_FASTLINK + T1_ANALYSE, 0); base 112 drivers/staging/isdn/avm/t1isa.c t1outp(base, T1_SLOWLINK + T1_ANALYSE, 0); base 114 drivers/staging/isdn/avm/t1isa.c if (t1inp(base, T1_FASTLINK + T1_OUTSTAT) != 0x1) /* tx empty */ base 116 drivers/staging/isdn/avm/t1isa.c if (t1inp(base, T1_FASTLINK + T1_INSTAT) != 0x0) /* rx empty */ base 118 drivers/staging/isdn/avm/t1isa.c if (t1inp(base, T1_FASTLINK + T1_IRQENABLE) != 0x0) base 120 drivers/staging/isdn/avm/t1isa.c if ((t1inp(base, T1_FASTLINK + T1_FIFOSTAT) & 0xf0) != 0x70) base 122 drivers/staging/isdn/avm/t1isa.c if ((t1inp(base, T1_FASTLINK + T1_IRQMASTER) & 0x0e) != 0) base 124 drivers/staging/isdn/avm/t1isa.c if ((t1inp(base, T1_FASTLINK + T1_IDENT) & 0x7d) != 1) base 126 drivers/staging/isdn/avm/t1isa.c if (t1inp(base, T1_SLOWLINK + T1_OUTSTAT) != 0x1) /* tx empty */ base 128 drivers/staging/isdn/avm/t1isa.c if ((t1inp(base, T1_SLOWLINK + T1_IRQMASTER) & 0x0e) != 0) base 130 drivers/staging/isdn/avm/t1isa.c if ((t1inp(base, T1_SLOWLINK + T1_IDENT) & 0x7d) != 0) base 106 drivers/staging/kpc2000/kpc2000_spi.c u64 __iomem *base; base 111 drivers/staging/kpc2000/kpc2000_spi.c void __iomem *base; base 164 drivers/staging/kpc2000/kpc2000_spi.c u64 __iomem *addr = cs->base; base 178 drivers/staging/kpc2000/kpc2000_spi.c u64 __iomem *addr = cs->base; base 273 drivers/staging/kpc2000/kpc2000_spi.c cs->base = kpspi->base; base 469 drivers/staging/kpc2000/kpc2000_spi.c kpspi->base = devm_ioremap_nocache(&pldev->dev, r->start, base 757 drivers/staging/media/allegro-dvt/allegro-core.c unsigned int base, size_t size) base 762 drivers/staging/media/allegro-dvt/allegro-core.c mbox->head = base; base 763 drivers/staging/media/allegro-dvt/allegro-core.c mbox->tail = base + 0x4; base 764 drivers/staging/media/allegro-dvt/allegro-core.c mbox->data = base + 0x8; base 284 drivers/staging/media/hantro/hantro.h u32 base; base 373 drivers/staging/media/hantro/hantro.h v = vdpu_read(vpu, reg->base); base 376 drivers/staging/media/hantro/hantro.h vdpu_write_relaxed(vpu, v, reg->base); base 274 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.base = G1_REG_DEC_CTRL2; base 280 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.base = G1_REG_DEC_CTRL6; base 301 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.base = G1_REG_DEC_CTRL6; base 338 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.base = G1_REG_BD_REF_PIC(3); base 199 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_VP8_CTRL0, base 205 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_VP8_DATA_VAL, base 211 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_VP8_DATA_VAL, base 217 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_STREAM_LEN, base 223 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_VP8_PIC_MB_SIZE, base 229 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_VP8_PIC_MB_SIZE, base 235 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_VP8_PIC_MB_SIZE, base 241 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_VP8_PIC_MB_SIZE, base 247 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_VP8_CTRL0, base 253 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_VP8_CTRL0, base 259 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_DEC_CTRL0, base 265 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_DEC_CTRL0, base 271 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .base = VDPU_REG_EN_FLAGS, base 439 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c if (vp8_dec_pred_bc_tap[i][j].base != 0) base 42 drivers/staging/media/imx/imx6-mipi-csi2.c void __iomem *base; base 124 drivers/staging/media/imx/imx6-mipi-csi2.c writel(0x1, csi2->base + CSI2_PHY_SHUTDOWNZ); base 125 drivers/staging/media/imx/imx6-mipi-csi2.c writel(0x1, csi2->base + CSI2_DPHY_RSTZ); base 126 drivers/staging/media/imx/imx6-mipi-csi2.c writel(0x1, csi2->base + CSI2_RESETN); base 128 drivers/staging/media/imx/imx6-mipi-csi2.c writel(0x0, csi2->base + CSI2_PHY_SHUTDOWNZ); base 129 drivers/staging/media/imx/imx6-mipi-csi2.c writel(0x0, csi2->base + CSI2_DPHY_RSTZ); base 130 drivers/staging/media/imx/imx6-mipi-csi2.c writel(0x0, csi2->base + CSI2_RESETN); base 138 drivers/staging/media/imx/imx6-mipi-csi2.c writel(lanes - 1, csi2->base + CSI2_N_LANES); base 145 drivers/staging/media/imx/imx6-mipi-csi2.c writel(PHY_TESTCLR, csi2->base + CSI2_PHY_TST_CTRL0); base 146 drivers/staging/media/imx/imx6-mipi-csi2.c writel(0x0, csi2->base + CSI2_PHY_TST_CTRL1); base 147 drivers/staging/media/imx/imx6-mipi-csi2.c writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0); base 150 drivers/staging/media/imx/imx6-mipi-csi2.c writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0); base 153 drivers/staging/media/imx/imx6-mipi-csi2.c writel(PHY_TESTEN | test_code, csi2->base + CSI2_PHY_TST_CTRL1); base 154 drivers/staging/media/imx/imx6-mipi-csi2.c writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0); base 157 drivers/staging/media/imx/imx6-mipi-csi2.c writel(test_data, csi2->base + CSI2_PHY_TST_CTRL1); base 158 drivers/staging/media/imx/imx6-mipi-csi2.c writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0); base 161 drivers/staging/media/imx/imx6-mipi-csi2.c writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0); base 227 drivers/staging/media/imx/imx6-mipi-csi2.c ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg, base 235 drivers/staging/media/imx/imx6-mipi-csi2.c ret = readl_poll_timeout(csi2->base + CSI2_ERR1, reg, base 254 drivers/staging/media/imx/imx6-mipi-csi2.c ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg, base 268 drivers/staging/media/imx/imx6-mipi-csi2.c ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg, base 293 drivers/staging/media/imx/imx6-mipi-csi2.c writel(reg, csi2->base + CSI2IPU_GASKET); base 622 drivers/staging/media/imx/imx6-mipi-csi2.c csi2->base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE); base 623 drivers/staging/media/imx/imx6-mipi-csi2.c if (!csi2->base) base 203 drivers/staging/media/ipu3/ipu3-css.c static int imgu_hw_wait(void __iomem *base, int reg, u32 mask, u32 cmp) base 207 drivers/staging/media/ipu3/ipu3-css.c return readl_poll_timeout(base + reg, val, (val & mask) == cmp, base 213 drivers/staging/media/ipu3/ipu3-css.c int imgu_css_set_powerup(struct device *dev, void __iomem *base) base 220 drivers/staging/media/ipu3/ipu3-css.c readl(base + IMGU_REG_GP_BUSY); base 221 drivers/staging/media/ipu3/ipu3-css.c writel(0, base + IMGU_REG_GP_BUSY); base 224 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(base, IMGU_REG_STATE, IMGU_STATE_IDLE_STS, base 231 drivers/staging/media/ipu3/ipu3-css.c writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_FORCE_RESET, base 232 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_PM_CTRL); base 238 drivers/staging/media/ipu3/ipu3-css.c pm_ctrl = readl(base + IMGU_REG_PM_CTRL); base 239 drivers/staging/media/ipu3/ipu3-css.c state = readl(base + IMGU_REG_STATE); base 247 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_PM_CTRL); base 248 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(base, IMGU_REG_PM_CTRL, base 255 drivers/staging/media/ipu3/ipu3-css.c writel(IMGU_PM_CTRL_RACE_TO_HALT, base + IMGU_REG_PM_CTRL); base 259 drivers/staging/media/ipu3/ipu3-css.c writel(readl(base + IMGU_REG_GP_BUSY) | 1, base + IMGU_REG_GP_BUSY); base 262 drivers/staging/media/ipu3/ipu3-css.c pm_ctrl = readl(base + IMGU_REG_PM_CTRL); base 264 drivers/staging/media/ipu3/ipu3-css.c writel(val, base + IMGU_REG_PM_CTRL); base 265 drivers/staging/media/ipu3/ipu3-css.c writel(0, base + IMGU_REG_GP_BUSY); base 266 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(base, IMGU_REG_STATE, base 272 drivers/staging/media/ipu3/ipu3-css.c writel(val, base + IMGU_REG_SYSTEM_REQ); base 273 drivers/staging/media/ipu3/ipu3-css.c writel(1, base + IMGU_REG_GP_BUSY); base 274 drivers/staging/media/ipu3/ipu3-css.c writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_FORCE_HALT, base 275 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_PM_CTRL); base 276 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(base, IMGU_REG_STATE, IMGU_STATE_HALT_STS, base 282 drivers/staging/media/ipu3/ipu3-css.c writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_START, base 283 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_PM_CTRL); base 284 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(base, IMGU_REG_PM_CTRL, IMGU_PM_CTRL_START, 0)) { base 288 drivers/staging/media/ipu3/ipu3-css.c writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_FORCE_UNHALT, base 289 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_PM_CTRL); base 291 drivers/staging/media/ipu3/ipu3-css.c val = readl(base + IMGU_REG_PM_CTRL); /* get pm_ctrl */ base 294 drivers/staging/media/ipu3/ipu3-css.c writel(val, base + IMGU_REG_PM_CTRL); base 299 drivers/staging/media/ipu3/ipu3-css.c imgu_css_set_powerdown(dev, base); base 303 drivers/staging/media/ipu3/ipu3-css.c void imgu_css_set_powerdown(struct device *dev, void __iomem *base) base 307 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(base, IMGU_REG_CIO_GATE_BURST_STATE, base 312 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(base, IMGU_REG_STATE, IMGU_STATE_IDLE_STS, base 317 drivers/staging/media/ipu3/ipu3-css.c writel(1, base + IMGU_REG_GP_HALT); base 318 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(base, IMGU_REG_STATE, IMGU_STATE_HALT_STS, base 323 drivers/staging/media/ipu3/ipu3-css.c writel(0, base + IMGU_REG_GP_BUSY); base 328 drivers/staging/media/ipu3/ipu3-css.c void __iomem *const base = css->base; base 337 drivers/staging/media/ipu3/ipu3-css.c val = readl(base + IMGU_REG_SP_CTRL(0)) | IMGU_CTRL_IRQ_READY; base 338 drivers/staging/media/ipu3/ipu3-css.c writel(val, base + IMGU_REG_SP_CTRL(0)); base 339 drivers/staging/media/ipu3/ipu3-css.c writel(val | IMGU_CTRL_IRQ_CLEAR, base + IMGU_REG_SP_CTRL(0)); base 342 drivers/staging/media/ipu3/ipu3-css.c writel(IMGU_REG_INT_CSS_IRQ, base + IMGU_REG_INT_ENABLE); base 344 drivers/staging/media/ipu3/ipu3-css.c writel(IMGU_REG_INT_CSS_IRQ, base + IMGU_REG_INT_STATUS); base 347 drivers/staging/media/ipu3/ipu3-css.c writel(~0, base + IMGU_REG_IRQCTRL_EDGE_NOT_PULSE(IMGU_IRQCTRL_MAIN)); base 348 drivers/staging/media/ipu3/ipu3-css.c writel(0, base + IMGU_REG_IRQCTRL_MASK(IMGU_IRQCTRL_MAIN)); base 350 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_IRQCTRL_EDGE(IMGU_IRQCTRL_MAIN)); base 352 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_IRQCTRL_ENABLE(IMGU_IRQCTRL_MAIN)); base 354 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_IRQCTRL_CLEAR(IMGU_IRQCTRL_MAIN)); base 356 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_IRQCTRL_MASK(IMGU_IRQCTRL_MAIN)); base 358 drivers/staging/media/ipu3/ipu3-css.c readl(base + IMGU_REG_IRQCTRL_ENABLE(IMGU_IRQCTRL_MAIN)); base 362 drivers/staging/media/ipu3/ipu3-css.c writel(~0, base + IMGU_REG_IRQCTRL_EDGE_NOT_PULSE(i)); base 363 drivers/staging/media/ipu3/ipu3-css.c writel(0, base + IMGU_REG_IRQCTRL_MASK(i)); base 364 drivers/staging/media/ipu3/ipu3-css.c writel(IMGU_IRQCTRL_IRQ_MASK, base + IMGU_REG_IRQCTRL_EDGE(i)); base 366 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_IRQCTRL_ENABLE(i)); base 367 drivers/staging/media/ipu3/ipu3-css.c writel(IMGU_IRQCTRL_IRQ_MASK, base + IMGU_REG_IRQCTRL_CLEAR(i)); base 368 drivers/staging/media/ipu3/ipu3-css.c writel(IMGU_IRQCTRL_IRQ_MASK, base + IMGU_REG_IRQCTRL_MASK(i)); base 370 drivers/staging/media/ipu3/ipu3-css.c readl(base + IMGU_REG_IRQCTRL_ENABLE(i)); base 426 drivers/staging/media/ipu3/ipu3-css.c void __iomem *const base = css->base; base 435 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_SP_ICACHE_ADDR(bi->type)); base 436 drivers/staging/media/ipu3/ipu3-css.c writel(readl(base + IMGU_REG_SP_CTRL(bi->type)) | base 438 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_SP_CTRL(bi->type)); base 440 drivers/staging/media/ipu3/ipu3-css.c writel(css->binary[css->fw_bl].daddr, base + IMGU_REG_ISP_ICACHE_ADDR); base 441 drivers/staging/media/ipu3/ipu3-css.c writel(readl(base + IMGU_REG_ISP_CTRL) | IMGU_CTRL_ICACHE_INV, base 442 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_ISP_CTRL); base 446 drivers/staging/media/ipu3/ipu3-css.c if (!(readl(base + IMGU_REG_SP_CTRL(0)) & IMGU_CTRL_IDLE)) { base 450 drivers/staging/media/ipu3/ipu3-css.c if (!(readl(base + IMGU_REG_ISP_CTRL) & IMGU_CTRL_IDLE)) { base 456 drivers/staging/media/ipu3/ipu3-css.c val = readl(base + stream_monitors[i].reg); base 473 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_GDC_LUT_BASE + i * 8); base 475 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_GDC_LUT_BASE + i * 8 + 4); base 484 drivers/staging/media/ipu3/ipu3-css.c void __iomem *const base = css->base; base 496 drivers/staging/media/ipu3/ipu3-css.c writes(&dmem_cfg, sizeof(dmem_cfg), base + base 499 drivers/staging/media/ipu3/ipu3-css.c writel(bi->info.sp.sp_entry, base + IMGU_REG_SP_START_ADDR(sp)); base 501 drivers/staging/media/ipu3/ipu3-css.c writel(readl(base + IMGU_REG_SP_CTRL(sp)) base 502 drivers/staging/media/ipu3/ipu3-css.c | IMGU_CTRL_START | IMGU_CTRL_RUN, base + IMGU_REG_SP_CTRL(sp)); base 504 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(css->base, IMGU_REG_SP_DMEM_BASE(sp) base 529 drivers/staging/media/ipu3/ipu3-css.c void __iomem *const base = css->base; base 533 drivers/staging/media/ipu3/ipu3-css.c writel(IMGU_TLB_INVALIDATE, base + IMGU_REG_TLB_INVALIDATE); base 538 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_ISP_DMEM_BASE + bl->info.bl.sw_state); base 540 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_ISP_DMEM_BASE + bl->info.bl.num_dma_cmds); base 555 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_ISP_DMEM_BASE + i * sizeof(dma_cmd) + base 559 drivers/staging/media/ipu3/ipu3-css.c writel(bl->info.bl.bl_entry, base + IMGU_REG_ISP_START_ADDR); base 561 drivers/staging/media/ipu3/ipu3-css.c writel(readl(base + IMGU_REG_ISP_CTRL) base 562 drivers/staging/media/ipu3/ipu3-css.c | IMGU_CTRL_START | IMGU_CTRL_RUN, base + IMGU_REG_ISP_CTRL); base 563 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(css->base, IMGU_REG_ISP_DMEM_BASE base 578 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_SP_DMEM_BASE(0) + bi->info.sp.per_frame_data); base 581 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_SP_DMEM_BASE(0) + bi->info.sp.sw_state); base 582 drivers/staging/media/ipu3/ipu3-css.c writel(1, base + IMGU_REG_SP_DMEM_BASE(0) + bi->info.sp.invalidate_tlb); base 587 drivers/staging/media/ipu3/ipu3-css.c writel(0, base + IMGU_REG_SP_DMEM_BASE(0) + bi->info.sp.isp_started); base 588 drivers/staging/media/ipu3/ipu3-css.c writel(0, base + IMGU_REG_SP_DMEM_BASE(0) + base 590 drivers/staging/media/ipu3/ipu3-css.c writel(0, base + IMGU_REG_SP_DMEM_BASE(0) + bi->info.sp.sleep_mode); base 591 drivers/staging/media/ipu3/ipu3-css.c writel(0, base + IMGU_REG_SP_DMEM_BASE(0) + bi->info.sp.invalidate_tlb); base 592 drivers/staging/media/ipu3/ipu3-css.c writel(IMGU_ABI_SP_COMM_COMMAND_READY, base + IMGU_REG_SP_DMEM_BASE(0) base 598 drivers/staging/media/ipu3/ipu3-css.c writel(event_mask, base + IMGU_REG_SP_DMEM_BASE(0) base 601 drivers/staging/media/ipu3/ipu3-css.c writel(1, base + IMGU_REG_SP_DMEM_BASE(0) + base 609 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_SP_DMEM_BASE(1) + bi->info.sp.sw_state); base 614 drivers/staging/media/ipu3/ipu3-css.c writel(IMGU_ABI_SP_COMM_COMMAND_READY, base + IMGU_REG_SP_DMEM_BASE(1) base 622 drivers/staging/media/ipu3/ipu3-css.c void __iomem *const base = css->base; base 627 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_SP_DMEM_BASE(0) + base 629 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(css->base, IMGU_REG_SP_CTRL(0), base 632 drivers/staging/media/ipu3/ipu3-css.c if (readl(base + IMGU_REG_SP_DMEM_BASE(0) + bi->info.sp.sw_state) != base 635 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(css->base, IMGU_REG_ISP_CTRL, base 642 drivers/staging/media/ipu3/ipu3-css.c void __iomem *const base = css->base; base 647 drivers/staging/media/ipu3/ipu3-css.c readl(base + IMGU_REG_GP_BUSY); base 648 drivers/staging/media/ipu3/ipu3-css.c writel(0, base + IMGU_REG_GP_BUSY); base 651 drivers/staging/media/ipu3/ipu3-css.c if (imgu_hw_wait(css->base, IMGU_REG_STATE, IMGU_STATE_IDLE_STS, base 656 drivers/staging/media/ipu3/ipu3-css.c writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_FORCE_RESET, base 657 drivers/staging/media/ipu3/ipu3-css.c base + IMGU_REG_PM_CTRL); base 1105 drivers/staging/media/ipu3/ipu3-css.c void __iomem *const base = css->base; base 1107 drivers/staging/media/ipu3/ipu3-css.c struct imgu_abi_queues __iomem *q = base + IMGU_REG_SP_DMEM_BASE(sp) + base 1119 drivers/staging/media/ipu3/ipu3-css.c void __iomem *const base = css->base; base 1121 drivers/staging/media/ipu3/ipu3-css.c struct imgu_abi_queues __iomem *q = base + IMGU_REG_SP_DMEM_BASE(sp) + base 1157 drivers/staging/media/ipu3/ipu3-css.c void __iomem *const base = css->base; base 1159 drivers/staging/media/ipu3/ipu3-css.c struct imgu_abi_queues __iomem *q = base + IMGU_REG_SP_DMEM_BASE(sp) + base 1548 drivers/staging/media/ipu3/ipu3-css.c void __iomem *base, int length) base 1555 drivers/staging/media/ipu3/ipu3-css.c css->base = base; base 2357 drivers/staging/media/ipu3/ipu3-css.c void __iomem *const base = css->base; base 2361 drivers/staging/media/ipu3/ipu3-css.c u32 imgu_status = readl(base + IMGU_REG_INT_STATUS); base 2363 drivers/staging/media/ipu3/ipu3-css.c writel(imgu_status, base + IMGU_REG_INT_STATUS); base 2365 drivers/staging/media/ipu3/ipu3-css.c irq_status[i] = readl(base + IMGU_REG_IRQCTRL_STATUS(i)); base 2370 drivers/staging/media/ipu3/ipu3-css.c u32 cnt = readl(base + IMGU_REG_SP_DMEM_BASE(0) + base 2372 drivers/staging/media/ipu3/ipu3-css.c u32 val = readl(base + IMGU_REG_SP_DMEM_BASE(0) + base 2382 drivers/staging/media/ipu3/ipu3-css.c writel(irq_status[i], base + IMGU_REG_IRQCTRL_CLEAR(i)); base 2384 drivers/staging/media/ipu3/ipu3-css.c readl(base + IMGU_REG_IRQCTRL_ENABLE(i)); base 152 drivers/staging/media/ipu3/ipu3-css.h void __iomem *base; base 169 drivers/staging/media/ipu3/ipu3-css.h void __iomem *base, int length); base 190 drivers/staging/media/ipu3/ipu3-css.h int imgu_css_set_powerup(struct device *dev, void __iomem *base); base 191 drivers/staging/media/ipu3/ipu3-css.h void imgu_css_set_powerdown(struct device *dev, void __iomem *base); base 50 drivers/staging/media/ipu3/ipu3-mmu.c void __iomem *base; base 80 drivers/staging/media/ipu3/ipu3-mmu.c writel(TLB_INVALIDATE, mmu->base + REG_TLB_INVALIDATE); base 106 drivers/staging/media/ipu3/ipu3-mmu.c writel(halt, mmu->base + REG_GP_HALT); base 107 drivers/staging/media/ipu3/ipu3-mmu.c ret = readl_poll_timeout(mmu->base + REG_GP_HALTED, base 425 drivers/staging/media/ipu3/ipu3-mmu.c struct imgu_mmu_info *imgu_mmu_init(struct device *parent, void __iomem *base) base 435 drivers/staging/media/ipu3/ipu3-mmu.c mmu->base = base; base 475 drivers/staging/media/ipu3/ipu3-mmu.c writel(pteval, mmu->base + REG_L1_PHYS); base 531 drivers/staging/media/ipu3/ipu3-mmu.c writel(pteval, mmu->base + REG_L1_PHYS); base 25 drivers/staging/media/ipu3/ipu3-mmu.h struct imgu_mmu_info *imgu_mmu_init(struct device *parent, void __iomem *base); base 349 drivers/staging/media/ipu3/ipu3.c r = imgu_css_set_powerup(&imgu->pci_dev->dev, imgu->base); base 360 drivers/staging/media/ipu3/ipu3.c imgu_css_set_powerdown(&imgu->pci_dev->dev, imgu->base); base 649 drivers/staging/media/ipu3/ipu3.c imgu->base = iomap[IMGU_PCI_BAR]; base 669 drivers/staging/media/ipu3/ipu3.c r = imgu_css_set_powerup(&pci_dev->dev, imgu->base); base 676 drivers/staging/media/ipu3/ipu3.c imgu->mmu = imgu_mmu_init(&pci_dev->dev, imgu->base); base 691 drivers/staging/media/ipu3/ipu3.c r = imgu_css_init(&pci_dev->dev, &imgu->css, imgu->base, phys_len); base 727 drivers/staging/media/ipu3/ipu3.c imgu_css_set_powerdown(&pci_dev->dev, imgu->base); base 743 drivers/staging/media/ipu3/ipu3.c imgu_css_set_powerdown(&pci_dev->dev, imgu->base); base 124 drivers/staging/media/ipu3/ipu3.h void __iomem *base; base 145 drivers/staging/media/sunxi/cedrus/cedrus.h void __iomem *base; base 161 drivers/staging/media/sunxi/cedrus/cedrus.h writel(val, dev->base + reg); base 166 drivers/staging/media/sunxi/cedrus/cedrus.h return readl(dev->base + reg); base 229 drivers/staging/media/sunxi/cedrus/cedrus_hw.c dev->base = devm_ioremap_resource(dev->dev, res); base 230 drivers/staging/media/sunxi/cedrus/cedrus_hw.c if (IS_ERR(dev->base)) { base 233 drivers/staging/media/sunxi/cedrus/cedrus_hw.c ret = PTR_ERR(dev->base); base 14 drivers/staging/media/tegra-vde/trace.h TP_PROTO(struct tegra_vde *vde, void __iomem *base, base 16 drivers/staging/media/tegra-vde/trace.h TP_ARGS(vde, base, offset, value), base 18 drivers/staging/media/tegra-vde/trace.h __string(hw_name, tegra_vde_reg_base_name(vde, base)) base 23 drivers/staging/media/tegra-vde/trace.h __assign_str(hw_name, tegra_vde_reg_base_name(vde, base)); base 32 drivers/staging/media/tegra-vde/trace.h TP_PROTO(struct tegra_vde *vde, void __iomem *base, base 34 drivers/staging/media/tegra-vde/trace.h TP_ARGS(vde, base, offset, value)); base 36 drivers/staging/media/tegra-vde/trace.h TP_PROTO(struct tegra_vde *vde, void __iomem *base, base 38 drivers/staging/media/tegra-vde/trace.h TP_ARGS(vde, base, offset, value)); base 54 drivers/staging/media/tegra-vde/vde.c u32 value, void __iomem *base, u32 offset) base 56 drivers/staging/media/tegra-vde/vde.c trace_vde_writel(vde, base, offset, value); base 58 drivers/staging/media/tegra-vde/vde.c writel_relaxed(value, base + offset); base 62 drivers/staging/media/tegra-vde/vde.c void __iomem *base, u32 offset) base 64 drivers/staging/media/tegra-vde/vde.c u32 value = readl_relaxed(base + offset); base 66 drivers/staging/media/tegra-vde/vde.c trace_vde_readl(vde, base, offset, value); base 72 drivers/staging/media/tegra-vde/vde.c u32 mask, void __iomem *base, u32 offset) base 74 drivers/staging/media/tegra-vde/vde.c u32 value = tegra_vde_readl(vde, base, offset); base 76 drivers/staging/media/tegra-vde/vde.c tegra_vde_writel(vde, value | mask, base, offset); base 75 drivers/staging/media/tegra-vde/vde.h tegra_vde_reg_base_name(struct tegra_vde *vde, void __iomem *base) base 77 drivers/staging/media/tegra-vde/vde.h if (vde->sxe == base) base 80 drivers/staging/media/tegra-vde/vde.h if (vde->bsev == base) base 83 drivers/staging/media/tegra-vde/vde.h if (vde->mbe == base) base 86 drivers/staging/media/tegra-vde/vde.h if (vde->ppe == base) base 89 drivers/staging/media/tegra-vde/vde.h if (vde->mce == base) base 92 drivers/staging/media/tegra-vde/vde.h if (vde->tfe == base) base 95 drivers/staging/media/tegra-vde/vde.h if (vde->ppb == base) base 98 drivers/staging/media/tegra-vde/vde.h if (vde->vdma == base) base 101 drivers/staging/media/tegra-vde/vde.h if (vde->frameid == base) base 158 drivers/staging/mt7621-dma/mtk-hsdma.c void __iomem *base; base 185 drivers/staging/mt7621-dma/mtk-hsdma.c return readl(hsdma->base + reg); base 191 drivers/staging/mt7621-dma/mtk-hsdma.c writel(val, hsdma->base + reg); base 656 drivers/staging/mt7621-dma/mtk-hsdma.c void __iomem *base; base 671 drivers/staging/mt7621-dma/mtk-hsdma.c base = devm_ioremap_resource(&pdev->dev, res); base 672 drivers/staging/mt7621-dma/mtk-hsdma.c if (IS_ERR(base)) base 673 drivers/staging/mt7621-dma/mtk-hsdma.c return PTR_ERR(base); base 674 drivers/staging/mt7621-dma/mtk-hsdma.c hsdma->base = base + HSDMA_BASE_OFFSET; base 108 drivers/staging/mt7621-pci/pci-mt7621.c void __iomem *base; base 132 drivers/staging/mt7621-pci/pci-mt7621.c void __iomem *base; base 149 drivers/staging/mt7621-pci/pci-mt7621.c return readl(pcie->base + reg); base 154 drivers/staging/mt7621-pci/pci-mt7621.c writel(val, pcie->base + reg); base 159 drivers/staging/mt7621-pci/pci-mt7621.c return readl(port->base + reg); base 165 drivers/staging/mt7621-pci/pci-mt7621.c writel(val, port->base + reg); base 182 drivers/staging/mt7621-pci/pci-mt7621.c writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR); base 184 drivers/staging/mt7621-pci/pci-mt7621.c return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); base 346 drivers/staging/mt7621-pci/pci-mt7621.c port->base = devm_ioremap_resource(dev, ®s); base 347 drivers/staging/mt7621-pci/pci-mt7621.c if (IS_ERR(port->base)) base 348 drivers/staging/mt7621-pci/pci-mt7621.c return PTR_ERR(port->base); base 390 drivers/staging/mt7621-pci/pci-mt7621.c pcie->base = devm_ioremap_resource(dev, ®s); base 391 drivers/staging/mt7621-pci/pci-mt7621.c if (IS_ERR(pcie->base)) base 392 drivers/staging/mt7621-pci/pci-mt7621.c return PTR_ERR(pcie->base); base 372 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c range->base = __be32_to_cpu(*gpiobase); base 373 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c range->pin_base = range->base; base 35 drivers/staging/netlogic/xlr_net.c static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val) base 37 drivers/staging/netlogic/xlr_net.c __raw_writel(val, base + reg); base 40 drivers/staging/netlogic/xlr_net.c static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg) base 42 drivers/staging/netlogic/xlr_net.c return __raw_readl(base + reg); base 382 drivers/staging/netlogic/xlr_net.c u32 *base; base 386 drivers/staging/netlogic/xlr_net.c base = priv->base_addr; base 396 drivers/staging/netlogic/xlr_net.c xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff); base 397 drivers/staging/netlogic/xlr_net.c xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07); base 398 drivers/staging/netlogic/xlr_net.c xlr_nae_wreg(base, reg_size, spill_size); base 585 drivers/staging/nvec/nvec.c status = readl(nvec->base + I2C_SL_STATUS); base 599 drivers/staging/nvec/nvec.c received = readl(nvec->base + I2C_SL_RCVD); base 601 drivers/staging/nvec/nvec.c writel(0, nvec->base + I2C_SL_RCVD); base 693 drivers/staging/nvec/nvec.c writel(to_send, nvec->base + I2C_SL_RCVD); base 733 drivers/staging/nvec/nvec.c writel(val, nvec->base + I2C_CNFG); base 737 drivers/staging/nvec/nvec.c writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG); base 738 drivers/staging/nvec/nvec.c writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT); base 740 drivers/staging/nvec/nvec.c writel(nvec->i2c_addr >> 1, nvec->base + I2C_SL_ADDR1); base 741 drivers/staging/nvec/nvec.c writel(0, nvec->base + I2C_SL_ADDR2); base 750 drivers/staging/nvec/nvec.c writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG); base 770 drivers/staging/nvec/nvec.c void __iomem *base; base 792 drivers/staging/nvec/nvec.c base = devm_platform_ioremap_resource(pdev, 0); base 793 drivers/staging/nvec/nvec.c if (IS_ERR(base)) base 794 drivers/staging/nvec/nvec.c return PTR_ERR(base); base 812 drivers/staging/nvec/nvec.c nvec->base = base; base 138 drivers/staging/nvec/nvec.h void __iomem *base; base 392 drivers/staging/qlge/qlge_ethtool.c ecmd->base.port = PORT_TP; base 393 drivers/staging/qlge/qlge_ethtool.c ecmd->base.autoneg = AUTONEG_ENABLE; base 397 drivers/staging/qlge/qlge_ethtool.c ecmd->base.port = PORT_FIBRE; base 400 drivers/staging/qlge/qlge_ethtool.c ecmd->base.speed = SPEED_10000; base 401 drivers/staging/qlge/qlge_ethtool.c ecmd->base.duplex = DUPLEX_FULL; base 123 drivers/staging/ralink-gdma/ralink-gdma.c void __iomem *base; base 158 drivers/staging/ralink-gdma/ralink-gdma.c return readl(dma_dev->base + reg); base 164 drivers/staging/ralink-gdma/ralink-gdma.c writel(val, dma_dev->base + reg); base 802 drivers/staging/ralink-gdma/ralink-gdma.c void __iomem *base; base 822 drivers/staging/ralink-gdma/ralink-gdma.c base = devm_ioremap_resource(&pdev->dev, res); base 823 drivers/staging/ralink-gdma/ralink-gdma.c if (IS_ERR(base)) base 824 drivers/staging/ralink-gdma/ralink-gdma.c return PTR_ERR(base); base 825 drivers/staging/ralink-gdma/ralink-gdma.c dma_dev->base = base; base 199 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c u8 path, base; base 204 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_1TX, MGN_11M); base 205 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, CCK, RF_1TX, base); base 208 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_1TX, MGN_54M); base 209 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, OFDM, RF_1TX, base); base 212 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_1TX, MGN_MCS7); base 213 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base); base 216 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_2TX, MGN_MCS15); base 217 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base); base 220 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_3TX, MGN_MCS23); base 221 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, HT_MCS16_MCS23, RF_3TX, base); base 224 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_1TX, MGN_VHT1SS_MCS7); base 225 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base); base 228 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_2TX, MGN_VHT2SS_MCS7); base 229 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base); base 232 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_3TX, MGN_VHT3SS_MCS7); base 233 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, VHT_3SSMCS0_3SSMCS9, RF_3TX, base); base 236 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_1TX, MGN_54M); base 237 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, OFDM, RF_1TX, base); base 240 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_1TX, MGN_MCS7); base 241 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base); base 244 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_2TX, MGN_MCS15); base 245 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base); base 248 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_3TX, MGN_MCS23); base 249 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, HT_MCS16_MCS23, RF_3TX, base); base 252 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_1TX, MGN_VHT1SS_MCS7); base 253 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base); base 256 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_2TX, MGN_VHT2SS_MCS7); base 257 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base); base 260 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_3TX, MGN_VHT2SS_MCS7); base 261 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, VHT_3SSMCS0_3SSMCS9, RF_3TX, base); base 819 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c u8 base = 0, i = 0, value = 0, band = 0, path = 0, txNum = 0; base 854 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_11M); base 857 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c PHY_SetTxPowerByRate(padapter, band, path, txNum, cckRates[i], value - base); base 861 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_54M); base 864 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c PHY_SetTxPowerByRate(padapter, band, path, txNum, ofdmRates[i], value - base); base 868 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_MCS7); base 871 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c PHY_SetTxPowerByRate(padapter, band, path, txNum, mcs0_7Rates[i], value - base); base 875 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_MCS15); base 878 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c PHY_SetTxPowerByRate(padapter, band, path, txNum, mcs8_15Rates[i], value - base); base 882 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_MCS23); base 885 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c PHY_SetTxPowerByRate(padapter, band, path, txNum, mcs16_23Rates[i], value - base); base 889 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_VHT1SS_MCS7); base 892 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c PHY_SetTxPowerByRate(padapter, band, path, txNum, vht1ssRates[i], value - base); base 896 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_VHT2SS_MCS7); base 899 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c PHY_SetTxPowerByRate(padapter, band, path, txNum, vht2ssRates[i], value - base); base 903 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_VHT3SS_MCS7); base 906 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c PHY_SetTxPowerByRate(padapter, band, path, txNum, vht3ssRates[i], value - base); base 97 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h u8 base:4; base 108 drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h #define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base base 165 drivers/staging/sm750fb/sm750.c unsigned int base, pitch, Bpp, rop; base 178 drivers/staging/sm750fb/sm750.c base = par->crtc.oScreen; base 195 drivers/staging/sm750fb/sm750.c base, pitch, Bpp, base 207 drivers/staging/sm750fb/sm750.c unsigned int base, pitch, Bpp; base 216 drivers/staging/sm750fb/sm750.c base = par->crtc.oScreen; base 229 drivers/staging/sm750fb/sm750.c base, pitch, region->sx, region->sy, base 230 drivers/staging/sm750fb/sm750.c base, pitch, Bpp, region->dx, region->dy, base 239 drivers/staging/sm750fb/sm750.c unsigned int base, pitch, Bpp; base 250 drivers/staging/sm750fb/sm750.c base = par->crtc.oScreen; base 279 drivers/staging/sm750fb/sm750.c base, pitch, Bpp, base 1064 drivers/staging/sm750fb/sm750.c ap->ranges[0].base = pci_resource_start(pdev, 0); base 89 drivers/staging/sm750fb/sm750_accel.c u32 base, u32 pitch, u32 Bpp, base 104 drivers/staging/sm750fb/sm750_accel.c write_dpr(accel, DE_WINDOW_DESTINATION_BASE, base); /* dpr40 */ base 193 drivers/staging/sm750fb/sm750_accel.h u32 base, u32 pitch, u32 Bpp, base 605 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c user_service = (struct user_service *)service->base.userdata; base 964 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c user_service = service->base.userdata; base 1005 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c service->base.fourcc), base 1190 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c user_service = service->base.userdata; base 1304 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c user_service = (struct user_service *)service->base.userdata; base 1431 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c (struct user_service *)service->base.userdata; base 1985 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c struct user_service *user_service = service->base.userdata; base 1997 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c struct user_service *user_service = service->base.userdata; base 2034 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c service->base.userdata; base 2135 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c if (service && (service->base.callback == service_callback)) { base 2146 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c if (service && (service->base.callback == service_callback)) { base 2177 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c (struct user_service *)service->base.userdata; base 2183 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c if ((service->base.callback == service_callback) && base 2707 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), base 2835 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), base 3051 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c service_data[found].fourcc = service_ptr->base.fourcc; base 3113 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), base 292 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c service->userdata_term(service->base.userdata); base 315 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c return service ? service->base.userdata : NULL; base 323 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c return service ? service->base.fourcc : 0; base 366 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c status = service->base.callback(reason, header, service->handle, base 998 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c ? service->base.fourcc base 1101 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c ? service->base.fourcc base 1365 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), base 1600 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c ? service->base.fourcc base 1665 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), base 2003 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c ? service->base.fourcc base 2298 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c service->base.fourcc = params->fourcc; base 2299 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c service->base.callback = params->callback; base 2300 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c service->base.userdata = params->userdata; base 2361 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c (srv->base.callback != base 2419 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c service->base.fourcc, base 3427 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c int fourcc = service->base.fourcc; base 252 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h struct vchiq_service_base base; base 138 drivers/staging/wusbcore/host/whci/asl.c le_writeq(qset->qset_dma | QH_LINK_NTDS(8), whc->base + WUSBASYNCLISTADDR); base 141 drivers/staging/wusbcore/host/whci/asl.c whci_wait_for(&whc->umc->dev, whc->base + WUSBSTS, base 149 drivers/staging/wusbcore/host/whci/asl.c whci_wait_for(&whc->umc->dev, whc->base + WUSBSTS, base 173 drivers/staging/wusbcore/host/whci/asl.c (le_readl(whc->base + WUSBCMD) & WUSBCMD_ASYNC_UPDATED) == 0, base 48 drivers/staging/wusbcore/host/whci/hcd.c whc->base + WUSBINTR); base 85 drivers/staging/wusbcore/host/whci/hcd.c le_writel(0, whc->base + WUSBINTR); base 87 drivers/staging/wusbcore/host/whci/hcd.c whci_wait_for(&whc->umc->dev, whc->base + WUSBSTS, base 22 drivers/staging/wusbcore/host/whci/hw.c cmd = le_readl(whc->base + WUSBCMD); base 24 drivers/staging/wusbcore/host/whci/hw.c le_writel(cmd, whc->base + WUSBCMD); base 48 drivers/staging/wusbcore/host/whci/hw.c (le_readl(whc->base + WUSBGENCMDSTS) & WUSBGENCMDSTS_ACTIVE) == 0, base 52 drivers/staging/wusbcore/host/whci/hw.c le_readl(whc->base + WUSBGENCMDSTS), base 53 drivers/staging/wusbcore/host/whci/hw.c le_readl(whc->base + WUSBGENCMDPARAMS)); base 67 drivers/staging/wusbcore/host/whci/hw.c le_writel(params, whc->base + WUSBGENCMDPARAMS); base 68 drivers/staging/wusbcore/host/whci/hw.c le_writeq(dma_addr, whc->base + WUSBGENADDR); base 71 drivers/staging/wusbcore/host/whci/hw.c whc->base + WUSBGENCMDSTS); base 21 drivers/staging/wusbcore/host/whci/init.c le_writel(WUSBCMD_WHCRESET, whc->base + WUSBCMD); base 22 drivers/staging/wusbcore/host/whci/init.c whci_wait_for(&whc->umc->dev, whc->base + WUSBCMD, WUSBCMD_WHCRESET, 0, base 34 drivers/staging/wusbcore/host/whci/init.c le_writeq(whc->di_buf_dma, whc->base + WUSBDEVICEINFOADDR); base 43 drivers/staging/wusbcore/host/whci/init.c le_writeq(whc->dn_buf_dma, whc->base + WUSBDNTSBUFADDR); base 82 drivers/staging/wusbcore/host/whci/init.c whc->base = ioremap(start, len); base 83 drivers/staging/wusbcore/host/whci/init.c if (!whc->base) { base 92 drivers/staging/wusbcore/host/whci/init.c whcsparams = le_readl(whc->base + WHCSPARAMS); base 170 drivers/staging/wusbcore/host/whci/init.c if (whc->base) base 171 drivers/staging/wusbcore/host/whci/init.c iounmap(whc->base); base 26 drivers/staging/wusbcore/host/whci/int.c sts = le_readl(whc->base + WUSBSTS); base 29 drivers/staging/wusbcore/host/whci/int.c le_writel(sts & WUSBSTS_INT_MASK, whc->base + WUSBSTS); base 147 drivers/staging/wusbcore/host/whci/pzl.c le_writeq(whc->pz_list_dma, whc->base + WUSBPERIODICLISTBASE); base 150 drivers/staging/wusbcore/host/whci/pzl.c whci_wait_for(&whc->umc->dev, whc->base + WUSBSTS, base 162 drivers/staging/wusbcore/host/whci/pzl.c whci_wait_for(&whc->umc->dev, whc->base + WUSBSTS, base 186 drivers/staging/wusbcore/host/whci/pzl.c (le_readl(whc->base + WUSBCMD) & WUSBCMD_PERIODIC_UPDATED) == 0, base 388 drivers/staging/wusbcore/host/whci/pzl.c le_writeq(whc->pz_list_dma, whc->base + WUSBPERIODICLISTBASE); base 26 drivers/staging/wusbcore/host/whci/whcd.h void __iomem *base; base 19 drivers/staging/wusbcore/host/whci/wusb.c le_writel(bit, whc->base + WUSBDIBUPDATED + offset); base 22 drivers/staging/wusbcore/host/whci/wusb.c whc->base + WUSBDIBUPDATED + offset, bit, 0, base 51 drivers/staging/wusbcore/host/whci/wusb.c now_time = le_readl(whc->base + WUSBTIME) & WUSBTIME_CHANNEL_TIME_MASK; base 125 drivers/staging/wusbcore/host/whci/wusb.c le_writel(dntsctrl, whc->base + WUSBDNTSCTRL); base 143 drivers/staging/wusbcore/host/whci/wusb.c le_writel(tkid, whc->base + WUSBTKID); base 145 drivers/staging/wusbcore/host/whci/wusb.c le_writel(seckey[i], whc->base + WUSBSECKEY + 4*i); base 146 drivers/staging/wusbcore/host/whci/wusb.c le_writel(setkeycmd, whc->base + WUSBSETSECKEYCMD); base 148 drivers/staging/wusbcore/host/whci/wusb.c ret = whci_wait_for(&whc->umc->dev, whc->base + WUSBSETSECKEYCMD, base 712 drivers/thermal/armada_thermal.c void __iomem *base; base 716 drivers/thermal/armada_thermal.c base = devm_ioremap_resource(&pdev->dev, res); base 717 drivers/thermal/armada_thermal.c if (IS_ERR(base)) base 718 drivers/thermal/armada_thermal.c return PTR_ERR(base); base 727 drivers/thermal/armada_thermal.c if (((unsigned long)base & ~PAGE_MASK) < data->syscon_status_off) base 729 drivers/thermal/armada_thermal.c base -= data->syscon_status_off; base 731 drivers/thermal/armada_thermal.c priv->syscon = devm_regmap_init_mmio(&pdev->dev, base, base 133 drivers/thermal/broadcom/bcm2835_thermal.c regset->base = data->regs; base 74 drivers/thermal/qcom/qcom-spmi-temp-alarm.c unsigned int base; base 90 drivers/thermal/qcom/qcom-spmi-temp-alarm.c ret = regmap_read(chip->map, chip->base + addr, &val); base 100 drivers/thermal/qcom/qcom-spmi-temp-alarm.c return regmap_write(chip->map, chip->base + addr, data); base 389 drivers/thermal/qcom/qcom-spmi-temp-alarm.c chip->base = res; base 81 drivers/thermal/rcar_gen3_thermal.c void __iomem *base; base 99 drivers/thermal/rcar_gen3_thermal.c return ioread32(tsc->base + reg); base 105 drivers/thermal/rcar_gen3_thermal.c iowrite32(data, tsc->base + reg); base 419 drivers/thermal/rcar_gen3_thermal.c tsc->base = devm_ioremap_resource(dev, res); base 420 drivers/thermal/rcar_gen3_thermal.c if (IS_ERR(tsc->base)) { base 421 drivers/thermal/rcar_gen3_thermal.c ret = PTR_ERR(tsc->base); base 43 drivers/thermal/rcar_thermal.c void __iomem *base; base 90 drivers/thermal/rcar_thermal.c void __iomem *base; base 107 drivers/thermal/rcar_thermal.c #define rcar_has_irq_support(priv) ((priv)->common->base) base 147 drivers/thermal/rcar_thermal.c return ioread32(common->base + reg); base 155 drivers/thermal/rcar_thermal.c iowrite32(data, common->base + reg); base 165 drivers/thermal/rcar_thermal.c val = ioread32(common->base + reg); base 168 drivers/thermal/rcar_thermal.c iowrite32(val, common->base + reg); base 174 drivers/thermal/rcar_thermal.c return ioread32(priv->base + reg); base 181 drivers/thermal/rcar_thermal.c iowrite32(data, priv->base + reg); base 190 drivers/thermal/rcar_thermal.c val = ioread32(priv->base + reg); base 193 drivers/thermal/rcar_thermal.c iowrite32(val, priv->base + reg); base 520 drivers/thermal/rcar_thermal.c if (!common->base) { base 528 drivers/thermal/rcar_thermal.c common->base = devm_ioremap_resource(dev, res); base 529 drivers/thermal/rcar_thermal.c if (IS_ERR(common->base)) base 530 drivers/thermal/rcar_thermal.c return PTR_ERR(common->base); base 558 drivers/thermal/rcar_thermal.c priv->base = devm_ioremap_resource(dev, res); base 559 drivers/thermal/rcar_thermal.c if (IS_ERR(priv->base)) { base 560 drivers/thermal/rcar_thermal.c ret = PTR_ERR(priv->base); base 611 drivers/thermal/rcar_thermal.c if (common->base && enr_bits) base 175 drivers/thermal/samsung/exynos_tmu.c void __iomem *base; base 292 drivers/thermal/samsung/exynos_tmu.c status = readb(data->base + EXYNOS_TMU_REG_STATUS); base 370 drivers/thermal/samsung/exynos_tmu.c writeb(th_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); base 374 drivers/thermal/samsung/exynos_tmu.c writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip * 4); base 387 drivers/thermal/samsung/exynos_tmu.c sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); base 395 drivers/thermal/samsung/exynos_tmu.c th = readl(data->base + EXYNOS_THD_TEMP_RISE); base 398 drivers/thermal/samsung/exynos_tmu.c writel(th, data->base + EXYNOS_THD_TEMP_RISE); base 401 drivers/thermal/samsung/exynos_tmu.c con = readl(data->base + EXYNOS_TMU_REG_CONTROL); base 403 drivers/thermal/samsung/exynos_tmu.c writel(con, data->base + EXYNOS_TMU_REG_CONTROL); base 412 drivers/thermal/samsung/exynos_tmu.c th = readl(data->base + EXYNOS_THD_TEMP_FALL); base 416 drivers/thermal/samsung/exynos_tmu.c writel(th, data->base + EXYNOS_THD_TEMP_FALL); base 428 drivers/thermal/samsung/exynos_tmu.c ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); base 430 drivers/thermal/samsung/exynos_tmu.c writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); base 432 drivers/thermal/samsung/exynos_tmu.c ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); base 434 drivers/thermal/samsung/exynos_tmu.c writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); base 441 drivers/thermal/samsung/exynos_tmu.c trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); base 460 drivers/thermal/samsung/exynos_tmu.c th = readl(data->base + reg_off); base 463 drivers/thermal/samsung/exynos_tmu.c writel(th, data->base + reg_off); base 480 drivers/thermal/samsung/exynos_tmu.c th = readl(data->base + reg_off); base 483 drivers/thermal/samsung/exynos_tmu.c writel(th, data->base + reg_off); base 492 drivers/thermal/samsung/exynos_tmu.c trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); base 501 drivers/thermal/samsung/exynos_tmu.c writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO); base 528 drivers/thermal/samsung/exynos_tmu.c th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); base 531 drivers/thermal/samsung/exynos_tmu.c writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); base 543 drivers/thermal/samsung/exynos_tmu.c th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); base 546 drivers/thermal/samsung/exynos_tmu.c writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); base 554 drivers/thermal/samsung/exynos_tmu.c trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); base 564 drivers/thermal/samsung/exynos_tmu.c con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); base 584 drivers/thermal/samsung/exynos_tmu.c writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); base 585 drivers/thermal/samsung/exynos_tmu.c writel(con, data->base + EXYNOS_TMU_REG_CONTROL); base 594 drivers/thermal/samsung/exynos_tmu.c con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); base 614 drivers/thermal/samsung/exynos_tmu.c writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN); base 615 drivers/thermal/samsung/exynos_tmu.c writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN); base 616 drivers/thermal/samsung/exynos_tmu.c writel(con, data->base + EXYNOS_TMU_REG_CONTROL); base 625 drivers/thermal/samsung/exynos_tmu.c con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); base 646 drivers/thermal/samsung/exynos_tmu.c writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); base 647 drivers/thermal/samsung/exynos_tmu.c writel(con, data->base + EXYNOS_TMU_REG_CONTROL); base 723 drivers/thermal/samsung/exynos_tmu.c val = readl(data->base + emul_con); base 725 drivers/thermal/samsung/exynos_tmu.c writel(val, data->base + emul_con); base 756 drivers/thermal/samsung/exynos_tmu.c int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); base 764 drivers/thermal/samsung/exynos_tmu.c return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); base 769 drivers/thermal/samsung/exynos_tmu.c return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & base 810 drivers/thermal/samsung/exynos_tmu.c val_irq = readl(data->base + tmu_intstat); base 819 drivers/thermal/samsung/exynos_tmu.c writel(val_irq, data->base + tmu_intclear); base 888 drivers/thermal/samsung/exynos_tmu.c data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); base 889 drivers/thermal/samsung/exynos_tmu.c if (!data->base) { base 102 drivers/thermal/st/stm_thermal.c void __iomem *base; base 122 drivers/thermal/st/stm_thermal.c value = readl_relaxed(sensor->base + DTS_SR_OFFSET); base 125 drivers/thermal/st/stm_thermal.c writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_CIFR_OFFSET); base 128 drivers/thermal/st/stm_thermal.c writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_CIFR_OFFSET); base 141 drivers/thermal/st/stm_thermal.c value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET); base 143 drivers/thermal/st/stm_thermal.c writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET); base 150 drivers/thermal/st/stm_thermal.c ret = readl_poll_timeout(sensor->base + DTS_SR_OFFSET, base 157 drivers/thermal/st/stm_thermal.c value = readl_relaxed(sensor->base + base 160 drivers/thermal/st/stm_thermal.c writel_relaxed(value, sensor->base + base 171 drivers/thermal/st/stm_thermal.c value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET); base 173 drivers/thermal/st/stm_thermal.c writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET); base 179 drivers/thermal/st/stm_thermal.c value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET); base 181 drivers/thermal/st/stm_thermal.c writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET); base 184 drivers/thermal/st/stm_thermal.c return readl_poll_timeout(sensor->base + DTS_SR_OFFSET, value, base 206 drivers/thermal/st/stm_thermal.c value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET); base 227 drivers/thermal/st/stm_thermal.c writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET); base 236 drivers/thermal/st/stm_thermal.c sensor->t0 = readl_relaxed(sensor->base + DTS_T0VALR1_OFFSET) & base 244 drivers/thermal/st/stm_thermal.c sensor->fmt0 = ADJUST * (readl_relaxed(sensor->base + base 248 drivers/thermal/st/stm_thermal.c sensor->ramp_coeff = readl_relaxed(sensor->base + DTS_RAMPVALR_OFFSET) & base 269 drivers/thermal/st/stm_thermal.c sampling_time = (readl_relaxed(sensor->base + DTS_CFGR1_OFFSET) & base 296 drivers/thermal/st/stm_thermal.c value = readl_relaxed(sensor->base + DTS_ITR1_OFFSET); base 319 drivers/thermal/st/stm_thermal.c writel_relaxed(value, sensor->base + DTS_ITR1_OFFSET); base 330 drivers/thermal/st/stm_thermal.c value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET); base 332 drivers/thermal/st/stm_thermal.c sensor->base + DTS_ITENR_OFFSET); base 350 drivers/thermal/st/stm_thermal.c writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_CIFR_OFFSET); base 353 drivers/thermal/st/stm_thermal.c value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET); base 359 drivers/thermal/st/stm_thermal.c writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_CIFR_OFFSET); base 366 drivers/thermal/st/stm_thermal.c writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET); base 415 drivers/thermal/st/stm_thermal.c ret = readl_poll_timeout(sensor->base + DTS_DR_OFFSET, freqM, base 426 drivers/thermal/st/stm_thermal.c sampling_time = (readl_relaxed(sensor->base + DTS_CFGR1_OFFSET) & base 616 drivers/thermal/st/stm_thermal.c void __iomem *base; base 634 drivers/thermal/st/stm_thermal.c base = devm_ioremap_resource(&pdev->dev, res); base 635 drivers/thermal/st/stm_thermal.c if (IS_ERR(base)) base 636 drivers/thermal/st/stm_thermal.c return PTR_ERR(base); base 639 drivers/thermal/st/stm_thermal.c sensor->base = base; base 29 drivers/thermal/tango_thermal.c void __iomem *base; base 33 drivers/thermal/tango_thermal.c static bool temp_above_thresh(void __iomem *base, int thresh_idx) base 35 drivers/thermal/tango_thermal.c writel(CMD_READ | thresh_idx << 8, base + TEMPSI_CMD); base 37 drivers/thermal/tango_thermal.c writel(CMD_READ | thresh_idx << 8, base + TEMPSI_CMD); base 39 drivers/thermal/tango_thermal.c return readl(base + TEMPSI_RES); base 47 drivers/thermal/tango_thermal.c if (temp_above_thresh(priv->base, idx)) { base 49 drivers/thermal/tango_thermal.c while (idx < IDX_MAX && temp_above_thresh(priv->base, ++idx)) base 54 drivers/thermal/tango_thermal.c while (idx > IDX_MIN && !temp_above_thresh(priv->base, --idx)) base 70 drivers/thermal/tango_thermal.c writel(0, priv->base + TEMPSI_CFG); base 71 drivers/thermal/tango_thermal.c writel(CMD_ON, priv->base + TEMPSI_CMD); base 85 drivers/thermal/tango_thermal.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 86 drivers/thermal/tango_thermal.c if (IS_ERR(priv->base)) base 87 drivers/thermal/tango_thermal.c return PTR_ERR(priv->base); base 388 drivers/thermal/tegra/soctherm.c void __iomem *base = tegra->regs + sensor->base; base 392 drivers/thermal/tegra/soctherm.c writel(val, base + SENSOR_CONFIG0); base 398 drivers/thermal/tegra/soctherm.c writel(val, base + SENSOR_CONFIG1); base 400 drivers/thermal/tegra/soctherm.c writel(tegra->calib[i], base + SENSOR_CONFIG2); base 1299 drivers/thermal/tegra/soctherm.c r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1); base 1317 drivers/thermal/tegra/soctherm.c r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1); base 1323 drivers/thermal/tegra/soctherm.c r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0); base 1329 drivers/thermal/tegra/soctherm.c r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0); base 1341 drivers/thermal/tegra/soctherm.c r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2); base 94 drivers/thermal/tegra/soctherm.h const u32 base; base 130 drivers/thermal/tegra/tegra124-soctherm.c .base = 0xc0, base 138 drivers/thermal/tegra/tegra124-soctherm.c .base = 0xe0, base 146 drivers/thermal/tegra/tegra124-soctherm.c .base = 0x100, base 154 drivers/thermal/tegra/tegra124-soctherm.c .base = 0x120, base 162 drivers/thermal/tegra/tegra124-soctherm.c .base = 0x140, base 170 drivers/thermal/tegra/tegra124-soctherm.c .base = 0x160, base 178 drivers/thermal/tegra/tegra124-soctherm.c .base = 0x180, base 186 drivers/thermal/tegra/tegra124-soctherm.c .base = 0x1a0, base 130 drivers/thermal/tegra/tegra132-soctherm.c .base = 0xc0, base 138 drivers/thermal/tegra/tegra132-soctherm.c .base = 0xe0, base 146 drivers/thermal/tegra/tegra132-soctherm.c .base = 0x100, base 154 drivers/thermal/tegra/tegra132-soctherm.c .base = 0x120, base 162 drivers/thermal/tegra/tegra132-soctherm.c .base = 0x140, base 170 drivers/thermal/tegra/tegra132-soctherm.c .base = 0x160, base 178 drivers/thermal/tegra/tegra132-soctherm.c .base = 0x180, base 186 drivers/thermal/tegra/tegra132-soctherm.c .base = 0x1a0, base 131 drivers/thermal/tegra/tegra210-soctherm.c .base = 0xc0, base 139 drivers/thermal/tegra/tegra210-soctherm.c .base = 0xe0, base 147 drivers/thermal/tegra/tegra210-soctherm.c .base = 0x100, base 155 drivers/thermal/tegra/tegra210-soctherm.c .base = 0x120, base 163 drivers/thermal/tegra/tegra210-soctherm.c .base = 0x140, base 171 drivers/thermal/tegra/tegra210-soctherm.c .base = 0x160, base 179 drivers/thermal/tegra/tegra210-soctherm.c .base = 0x180, base 187 drivers/thermal/tegra/tegra210-soctherm.c .base = 0x1a0, base 46 drivers/thermal/ti-soc-thermal/ti-bandgap.c return readl(bgp->base + reg); base 59 drivers/thermal/ti-soc-thermal/ti-bandgap.c writel(val, bgp->base + reg); base 855 drivers/thermal/ti-soc-thermal/ti-bandgap.c bgp->base = chunk; base 195 drivers/thermal/ti-soc-thermal/ti-bandgap.h void __iomem *base; base 57 drivers/thunderbolt/dma_port.c u32 base; base 222 drivers/thunderbolt/dma_port.c dma->base = DMA_PORT_CAP; base 250 drivers/thunderbolt/dma_port.c dma->base + MAIL_IN, 1, 50); base 286 drivers/thunderbolt/dma_port.c dma->base + MAIL_IN, 1, DMA_PORT_TIMEOUT); base 295 drivers/thunderbolt/dma_port.c dma->base + MAIL_OUT, 1, DMA_PORT_TIMEOUT); base 323 drivers/thunderbolt/dma_port.c dma->base + MAIL_DATA, dwords, DMA_PORT_TIMEOUT); base 337 drivers/thunderbolt/dma_port.c dma->base + MAIL_DATA, dwords, DMA_PORT_TIMEOUT); base 488 drivers/thunderbolt/dma_port.c dma->base + MAIL_OUT, 1, DMA_PORT_TIMEOUT); base 3398 drivers/tty/cyclades.c const char *name, const u32 mailbox, void __iomem *base, base 3465 drivers/tty/cyclades.c if (base != NULL) base 3466 drivers/tty/cyclades.c memcpy_toio(base + b->ram_offset, base 39 drivers/tty/goldfish.c void __iomem *base; base 59 drivers/tty/goldfish.c void __iomem *base = qtty->base; base 62 drivers/tty/goldfish.c gf_write_ptr((void *)address, base + GOLDFISH_TTY_REG_DATA_PTR, base 63 drivers/tty/goldfish.c base + GOLDFISH_TTY_REG_DATA_PTR_HIGH); base 64 drivers/tty/goldfish.c writel(count, base + GOLDFISH_TTY_REG_DATA_LEN); base 68 drivers/tty/goldfish.c base + GOLDFISH_TTY_REG_CMD); base 71 drivers/tty/goldfish.c base + GOLDFISH_TTY_REG_CMD); base 140 drivers/tty/goldfish.c void __iomem *base = qtty->base; base 145 drivers/tty/goldfish.c count = readl(base + GOLDFISH_TTY_REG_BYTES_READY); base 162 drivers/tty/goldfish.c writel(GOLDFISH_TTY_CMD_INT_ENABLE, qtty->base + GOLDFISH_TTY_REG_CMD); base 170 drivers/tty/goldfish.c writel(GOLDFISH_TTY_CMD_INT_DISABLE, qtty->base + GOLDFISH_TTY_REG_CMD); base 204 drivers/tty/goldfish.c void __iomem *base = qtty->base; base 205 drivers/tty/goldfish.c return readl(base + GOLDFISH_TTY_REG_BYTES_READY); base 225 drivers/tty/goldfish.c if (!goldfish_ttys[co->index].base) base 300 drivers/tty/goldfish.c void __iomem *base; base 310 drivers/tty/goldfish.c base = ioremap(r->start, 0x1000); base 311 drivers/tty/goldfish.c if (!base) { base 349 drivers/tty/goldfish.c qtty->base = base; base 360 drivers/tty/goldfish.c qtty->version = readl(base + GOLDFISH_TTY_REG_VERSION); base 379 drivers/tty/goldfish.c writel(GOLDFISH_TTY_CMD_INT_DISABLE, base + GOLDFISH_TTY_REG_CMD); base 416 drivers/tty/goldfish.c iounmap(base); base 428 drivers/tty/goldfish.c iounmap(qtty->base); base 429 drivers/tty/goldfish.c qtty->base = NULL; base 137 drivers/tty/isicom.c #define InterruptTheCard(base) outw(0, (base) + 0xc) base 138 drivers/tty/isicom.c #define ClearInterrupt(base) inw((base) + 0x0a) base 185 drivers/tty/isicom.c unsigned long base; base 219 drivers/tty/isicom.c static int WaitTillCardIsFree(unsigned long base) base 223 drivers/tty/isicom.c while (!(inw(base + 0xe) & 0x1) && count++ < 100) base 226 drivers/tty/isicom.c return !(inw(base + 0xe) & 0x1); base 231 drivers/tty/isicom.c unsigned long base = card->base; base 237 drivers/tty/isicom.c if (inw(base + 0xe) & 0x1) base 244 drivers/tty/isicom.c pr_warn("Failed to lock Card (0x%lx)\n", card->base); base 262 drivers/tty/isicom.c unsigned long base = card->base; base 265 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 268 drivers/tty/isicom.c outw(0x8000 | (channel << card->shift_count) | 0x02, base); base 269 drivers/tty/isicom.c outw(0x0504, base); base 270 drivers/tty/isicom.c InterruptTheCard(base); base 278 drivers/tty/isicom.c unsigned long base = card->base; base 281 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 284 drivers/tty/isicom.c outw(0x8000 | (channel << card->shift_count) | 0x02, base); base 285 drivers/tty/isicom.c outw(0x0404, base); base 286 drivers/tty/isicom.c InterruptTheCard(base); base 294 drivers/tty/isicom.c unsigned long base = card->base; base 297 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 300 drivers/tty/isicom.c outw(0x8000 | (channel << card->shift_count) | 0x02, base); base 301 drivers/tty/isicom.c outw(0x0a04, base); base 302 drivers/tty/isicom.c InterruptTheCard(base); base 310 drivers/tty/isicom.c unsigned long base = card->base; base 313 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 316 drivers/tty/isicom.c outw(0x8000 | (channel << card->shift_count) | 0x02, base); base 317 drivers/tty/isicom.c outw(0x0804, base); base 318 drivers/tty/isicom.c InterruptTheCard(base); base 328 drivers/tty/isicom.c unsigned long base = card->base; base 335 drivers/tty/isicom.c outw(0x8000 | (channel << card->shift_count) | 0x02, base); base 336 drivers/tty/isicom.c outw(0x0f04, base); base 337 drivers/tty/isicom.c InterruptTheCard(base); base 340 drivers/tty/isicom.c outw(0x8000 | (channel << card->shift_count) | 0x02, base); base 341 drivers/tty/isicom.c outw(0x0C04, base); base 342 drivers/tty/isicom.c InterruptTheCard(base); base 352 drivers/tty/isicom.c unsigned long base = card->base; base 355 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 358 drivers/tty/isicom.c outw(0x8000 | (channel << card->shift_count) | 0x02, base); base 359 drivers/tty/isicom.c outw(0x0c04, base); base 360 drivers/tty/isicom.c InterruptTheCard(base); base 395 drivers/tty/isicom.c unsigned long flags, base; base 416 drivers/tty/isicom.c base = isi_card[card].base; base 420 drivers/tty/isicom.c if (inw(base + 0xe) & 0x1) base 441 drivers/tty/isicom.c if (!(inw(base + 0x02) & (1 << port->channel))) base 447 drivers/tty/isicom.c base); base 463 drivers/tty/isicom.c outw(wrd, base); base 465 drivers/tty/isicom.c outw(wrd, base); base 472 drivers/tty/isicom.c outsw(base, port->port.xmit_buf+port->xmit_tail, word_count); base 487 drivers/tty/isicom.c InterruptTheCard(base); base 512 drivers/tty/isicom.c unsigned long base; base 520 drivers/tty/isicom.c base = card->base; base 523 drivers/tty/isicom.c if (!(inw(base + 0x0e) & 0x02)) base 532 drivers/tty/isicom.c outw(0x8000, base+0x04); base 533 drivers/tty/isicom.c ClearInterrupt(base); base 535 drivers/tty/isicom.c inw(base); /* get the dummy word out */ base 536 drivers/tty/isicom.c header = inw(base); base 542 drivers/tty/isicom.c __func__, base, channel + 1); base 543 drivers/tty/isicom.c outw(0x0000, base+0x04); /* enable interrupts */ base 549 drivers/tty/isicom.c outw(0x0000, base+0x04); /* enable interrupts */ base 557 drivers/tty/isicom.c inw(base); base 561 drivers/tty/isicom.c inw(base); base 562 drivers/tty/isicom.c outw(0x0000, base+0x04); /* enable interrupts */ base 568 drivers/tty/isicom.c header = inw(base); base 649 drivers/tty/isicom.c insw(base, rp, word_count); base 652 drivers/tty/isicom.c tty_insert_flip_char(&port->port, inw(base) & 0xff, base 658 drivers/tty/isicom.c __func__, base, channel + 1); base 661 drivers/tty/isicom.c inw(base); base 667 drivers/tty/isicom.c outw(0x0000, base+0x04); /* enable interrupts */ base 679 drivers/tty/isicom.c unsigned long base = card->base; base 723 drivers/tty/isicom.c if (WaitTillCardIsFree(base) == 0) { base 724 drivers/tty/isicom.c outw(0x8000 | (channel << shift_count) | 0x03, base); base 725 drivers/tty/isicom.c outw(linuxb_to_isib[baud] << 8 | 0x03, base); base 749 drivers/tty/isicom.c outw(channel_setup, base); base 750 drivers/tty/isicom.c InterruptTheCard(base); base 764 drivers/tty/isicom.c if (WaitTillCardIsFree(base) == 0) { base 765 drivers/tty/isicom.c outw(0x8000 | (channel << shift_count) | 0x04, base); base 766 drivers/tty/isicom.c outw(flow_ctrl << 8 | 0x05, base); base 767 drivers/tty/isicom.c outw((STOP_CHAR(tty)) << 8 | (START_CHAR(tty)), base); base 768 drivers/tty/isicom.c InterruptTheCard(base); base 774 drivers/tty/isicom.c outw(card->port_status, base + 0x02); base 812 drivers/tty/isicom.c if (WaitTillCardIsFree(card->base) == 0) { base 814 drivers/tty/isicom.c card->base); base 815 drivers/tty/isicom.c outw(((ISICOM_KILLTX | ISICOM_KILLRX) << 8) | 0x06, card->base); base 816 drivers/tty/isicom.c InterruptTheCard(card->base); base 877 drivers/tty/isicom.c __func__, card->base, card->count); base 911 drivers/tty/isicom.c outw(card->port_status, card->base + 0x02); base 1034 drivers/tty/isicom.c unsigned long base = card->base; base 1042 drivers/tty/isicom.c outw(0x8000 | ((port->channel) << (card->shift_count)) | 0x3, base); base 1043 drivers/tty/isicom.c outw((length & 0xff) << 8 | 0x00, base); base 1044 drivers/tty/isicom.c outw((length & 0xff00u), base); base 1045 drivers/tty/isicom.c InterruptTheCard(base); base 1142 drivers/tty/isicom.c ss->port = port->card->base; base 1187 drivers/tty/isicom.c outw(card->port_status, card->base + 0x02); base 1201 drivers/tty/isicom.c outw(card->port_status, card->base + 0x02); base 1277 drivers/tty/isicom.c unsigned long base = board->base; base 1282 drivers/tty/isicom.c base); base 1284 drivers/tty/isicom.c inw(base + 0x8); base 1288 drivers/tty/isicom.c outw(0, base + 0x8); /* Reset */ base 1292 drivers/tty/isicom.c sig = inw(base + 0x4) & 0xff; base 1297 drivers/tty/isicom.c "bad I/O Port Address 0x%lx).\n", card + 1, base); base 1305 drivers/tty/isicom.c portcount = inw(base + 0x2); base 1306 drivers/tty/isicom.c if (!(inw(base + 0xe) & 0x1) || (portcount != 0 && portcount != 4 && base 1339 drivers/tty/isicom.c unsigned long base = board->base; base 1383 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 1386 drivers/tty/isicom.c outw(0xf0, base); /* start upload sequence */ base 1387 drivers/tty/isicom.c outw(0x00, base); base 1388 drivers/tty/isicom.c outw(frame->addr, base); /* lsb of address */ base 1391 drivers/tty/isicom.c outw(word_count, base); base 1392 drivers/tty/isicom.c InterruptTheCard(base); base 1396 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 1399 drivers/tty/isicom.c status = inw(base + 0x4); base 1408 drivers/tty/isicom.c outsw(base, frame->data, word_count); base 1410 drivers/tty/isicom.c InterruptTheCard(base); base 1414 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 1417 drivers/tty/isicom.c status = inw(base + 0x4); base 1431 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 1434 drivers/tty/isicom.c outw(0xf1, base); /* start download sequence */ base 1435 drivers/tty/isicom.c outw(0x00, base); base 1436 drivers/tty/isicom.c outw(frame->addr, base); /* lsb of address */ base 1439 drivers/tty/isicom.c outw(word_count + 1, base); base 1440 drivers/tty/isicom.c InterruptTheCard(base); base 1444 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 1447 drivers/tty/isicom.c status = inw(base + 0x4); base 1463 drivers/tty/isicom.c inw(base); base 1464 drivers/tty/isicom.c insw(base, data, word_count); base 1465 drivers/tty/isicom.c InterruptTheCard(base); base 1478 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 1481 drivers/tty/isicom.c status = inw(base + 0x4); base 1490 drivers/tty/isicom.c if (WaitTillCardIsFree(base)) base 1493 drivers/tty/isicom.c outw(0xf2, base); base 1494 drivers/tty/isicom.c outw(0x800, base); base 1495 drivers/tty/isicom.c outw(0x0, base); base 1496 drivers/tty/isicom.c outw(0x0, base); base 1497 drivers/tty/isicom.c InterruptTheCard(base); base 1498 drivers/tty/isicom.c outw(0x0, base + 0x4); /* for ISI4608 cards */ base 1534 drivers/tty/isicom.c if (isi_card[index].base == 0) { base 1545 drivers/tty/isicom.c board->base = pci_resource_start(pdev, 3); base 1554 drivers/tty/isicom.c "will be disabled.\n", board->base, board->base + 15, base 1593 drivers/tty/isicom.c board->base = 0; base 1613 drivers/tty/isicom.c board->base = 0; base 1634 drivers/tty/isicom.c isi_card[idx].base = 0; base 2364 drivers/tty/n_gsm.c unsigned int base; base 2375 drivers/tty/n_gsm.c base = mux_num_to_base(gsm); /* Base for this MUX */ base 2377 drivers/tty/n_gsm.c tty_register_device(gsm_tty_driver, base + i, NULL); base 2393 drivers/tty/n_gsm.c unsigned int base = mux_num_to_base(gsm); /* Base for this MUX */ base 2398 drivers/tty/n_gsm.c tty_unregister_device(gsm_tty_driver, base + i); base 2616 drivers/tty/n_gsm.c unsigned int base; base 2629 drivers/tty/n_gsm.c base = mux_num_to_base(gsm); base 2630 drivers/tty/n_gsm.c return put_user(base + 1, (__u32 __user *)arg); base 208 drivers/tty/serial/8250/8250_hp300.c unsigned long base; base 249 drivers/tty/serial/8250/8250_hp300.c base = (FRODO_BASE + FRODO_APCI_OFFSET(i)); base 258 drivers/tty/serial/8250/8250_hp300.c uart.port.mapbase = base; base 259 drivers/tty/serial/8250/8250_hp300.c uart.port.membase = (char *)(base + DIO_VIRADDRBASE); base 1135 drivers/tty/serial/8250/8250_pci.c unsigned long base = port->port.iobase; base 1138 drivers/tty/serial/8250/8250_pci.c LCR = inb(base + UART_LCR); base 1139 drivers/tty/serial/8250/8250_pci.c outb(0xBF, base + UART_LCR); base 1140 drivers/tty/serial/8250/8250_pci.c val = inb(base + UART_SCR); base 1141 drivers/tty/serial/8250/8250_pci.c outb(LCR, base + UART_LCR); base 1147 drivers/tty/serial/8250/8250_pci.c unsigned long base = port->port.iobase; base 1150 drivers/tty/serial/8250/8250_pci.c LCR = inb(base + UART_LCR); base 1151 drivers/tty/serial/8250/8250_pci.c outb(0xBF, base + UART_LCR); base 1152 drivers/tty/serial/8250/8250_pci.c inb(base + UART_SCR); base 1153 drivers/tty/serial/8250/8250_pci.c outb(qopr, base + UART_SCR); base 1154 drivers/tty/serial/8250/8250_pci.c outb(LCR, base + UART_LCR); base 1159 drivers/tty/serial/8250/8250_pci.c unsigned long base = port->port.iobase; base 1162 drivers/tty/serial/8250/8250_pci.c LCR = inb(base + UART_LCR); base 1163 drivers/tty/serial/8250/8250_pci.c outb(0xBF, base + UART_LCR); base 1164 drivers/tty/serial/8250/8250_pci.c val = inb(base + UART_SCR); base 1165 drivers/tty/serial/8250/8250_pci.c outb(val | 0x10, base + UART_SCR); base 1166 drivers/tty/serial/8250/8250_pci.c qmcr = inb(base + UART_MCR); base 1167 drivers/tty/serial/8250/8250_pci.c outb(val, base + UART_SCR); base 1168 drivers/tty/serial/8250/8250_pci.c outb(LCR, base + UART_LCR); base 1175 drivers/tty/serial/8250/8250_pci.c unsigned long base = port->port.iobase; base 1178 drivers/tty/serial/8250/8250_pci.c LCR = inb(base + UART_LCR); base 1179 drivers/tty/serial/8250/8250_pci.c outb(0xBF, base + UART_LCR); base 1180 drivers/tty/serial/8250/8250_pci.c val = inb(base + UART_SCR); base 1181 drivers/tty/serial/8250/8250_pci.c outb(val | 0x10, base + UART_SCR); base 1182 drivers/tty/serial/8250/8250_pci.c outb(qmcr, base + UART_MCR); base 1183 drivers/tty/serial/8250/8250_pci.c outb(val, base + UART_SCR); base 1184 drivers/tty/serial/8250/8250_pci.c outb(LCR, base + UART_LCR); base 1189 drivers/tty/serial/8250/8250_pci.c unsigned long base = port->port.iobase; base 1192 drivers/tty/serial/8250/8250_pci.c LCR = inb(base + UART_LCR); base 1193 drivers/tty/serial/8250/8250_pci.c outb(0xBF, base + UART_LCR); base 1194 drivers/tty/serial/8250/8250_pci.c val = inb(base + UART_SCR); base 1198 drivers/tty/serial/8250/8250_pci.c outb(LCR, base + UART_LCR); base 1293 drivers/tty/serial/8250/8250_pci.c unsigned long base = pci_resource_start(dev, 0); base 1294 drivers/tty/serial/8250/8250_pci.c if (base) { base 1297 drivers/tty/serial/8250/8250_pci.c outl(inl(base + 0x38) | 0x00002000, base + 0x38); base 1298 drivers/tty/serial/8250/8250_pci.c tmp = inl(base + 0x3c); base 1299 drivers/tty/serial/8250/8250_pci.c outl(tmp | 0x01000000, base + 0x3c); base 1300 drivers/tty/serial/8250/8250_pci.c outl(tmp &= ~0x01000000, base + 0x3c); base 402 drivers/tty/serial/8250/8250_pnp.c static const resource_size_t base[] = {0x2f8, 0x3f8, 0x2e8, 0x3e8}; base 405 drivers/tty/serial/8250/8250_pnp.c for (i = 0; i < ARRAY_SIZE(base); i++) { base 406 drivers/tty/serial/8250/8250_pnp.c if (pnp_possible_config(dev, IORESOURCE_IO, base[i], 8)) base 421 drivers/tty/serial/8250/serial_cs.c static const unsigned int base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 }; base 432 drivers/tty/serial/8250/serial_cs.c p_dev->resource[0]->start = base[j]; base 433 drivers/tty/serial/8250/serial_cs.c p_dev->io_lines = base[j] ? 16 : 3; base 701 drivers/tty/serial/amba-pl010.c void __iomem *base; base 716 drivers/tty/serial/amba-pl010.c base = devm_ioremap(&dev->dev, dev->res.start, base 718 drivers/tty/serial/amba-pl010.c if (!base) base 727 drivers/tty/serial/amba-pl010.c uap->port.membase = base; base 2573 drivers/tty/serial/amba-pl011.c void __iomem *base; base 2575 drivers/tty/serial/amba-pl011.c base = devm_ioremap_resource(dev, mmiobase); base 2576 drivers/tty/serial/amba-pl011.c if (IS_ERR(base)) base 2577 drivers/tty/serial/amba-pl011.c return PTR_ERR(base); base 2584 drivers/tty/serial/amba-pl011.c uap->port.membase = base; base 765 drivers/tty/serial/dz.c unsigned long base; base 773 drivers/tty/serial/dz.c base = dec_kn_slot_base + KN01_DZ11; base 775 drivers/tty/serial/dz.c base = dec_kn_slot_base + KN02_DZ11; base 789 drivers/tty/serial/dz.c uport->mapbase = base; base 41 drivers/tty/serial/earlycon.c void __iomem *base; base 44 drivers/tty/serial/earlycon.c base = (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE); base 45 drivers/tty/serial/earlycon.c base += paddr & ~PAGE_MASK; base 47 drivers/tty/serial/earlycon.c base = ioremap(paddr, size); base 49 drivers/tty/serial/earlycon.c if (!base) base 52 drivers/tty/serial/earlycon.c return base; base 2222 drivers/tty/serial/imx.c void __iomem *base; base 2245 drivers/tty/serial/imx.c base = devm_ioremap_resource(&pdev->dev, res); base 2246 drivers/tty/serial/imx.c if (IS_ERR(base)) base 2247 drivers/tty/serial/imx.c return PTR_ERR(base); base 2255 drivers/tty/serial/imx.c sport->port.membase = base; base 979 drivers/tty/serial/ip22zilog.c unsigned long base; base 986 drivers/tty/serial/ip22zilog.c base = (unsigned long) &sgioc->uart; base 989 drivers/tty/serial/ip22zilog.c request_mem_region(base, 8, "IP22-Zilog"); base 991 drivers/tty/serial/ip22zilog.c return (struct zilog_layout *) base; base 1391 drivers/tty/serial/max310x.c s->gpio.base = -1; base 293 drivers/tty/serial/msm_serial.c static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base) base 313 drivers/tty/serial/msm_serial.c conf.dst_addr = base + UARTDM_TF; base 336 drivers/tty/serial/msm_serial.c static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base) base 360 drivers/tty/serial/msm_serial.c conf.src_addr = base + UARTDM_RF; base 1647 drivers/tty/serial/omap-serial.c void __iomem *base; base 1671 drivers/tty/serial/omap-serial.c base = devm_ioremap_resource(&pdev->dev, mem); base 1672 drivers/tty/serial/omap-serial.c if (IS_ERR(base)) base 1673 drivers/tty/serial/omap-serial.c return PTR_ERR(base); base 1714 drivers/tty/serial/omap-serial.c up->port.membase = base; base 206 drivers/tty/serial/qcom_geni_serial.c port->se.base = uport->membase; base 1126 drivers/tty/serial/qcom_geni_serial.c se.base = uport->membase; base 184 drivers/tty/serial/rp2.c void __iomem *base; base 237 drivers/tty/serial/rp2.c u32 tmp = readl(up->base + reg); base 240 drivers/tty/serial/rp2.c writel(tmp, up->base + reg); base 281 drivers/tty/serial/rp2.c tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT); base 292 drivers/tty/serial/rp2.c status = readl(up->base + RP2_CHAN_STAT); base 344 drivers/tty/serial/rp2.c writew(baud_div - 1, up->base + RP2_BAUD); base 401 drivers/tty/serial/rp2.c u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT); base 405 drivers/tty/serial/rp2.c u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ; base 434 drivers/tty/serial/rp2.c u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT); base 444 drivers/tty/serial/rp2.c writeb(up->port.x_char, up->base + RP2_DATA_BYTE); base 453 drivers/tty/serial/rp2.c writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE); base 472 drivers/tty/serial/rp2.c status = readl(up->base + RP2_CHAN_STAT); base 473 drivers/tty/serial/rp2.c writel(status, up->base + RP2_CHAN_STAT); base 487 drivers/tty/serial/rp2.c void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id); base 489 drivers/tty/serial/rp2.c unsigned long status = readl(base + RP2_CH_IRQ_STAT) & base 490 drivers/tty/serial/rp2.c ~readl(base + RP2_CH_IRQ_MASK); base 515 drivers/tty/serial/rp2.c readl(up->base + RP2_UART_CTL); base 600 drivers/tty/serial/rp2.c void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id); base 603 drivers/tty/serial/rp2.c writew(1, base + RP2_GLOBAL_CMD); base 604 drivers/tty/serial/rp2.c readw(base + RP2_GLOBAL_CMD); base 606 drivers/tty/serial/rp2.c writel(0, base + RP2_CLK_PRESCALER); base 609 drivers/tty/serial/rp2.c clk_cfg = readw(base + RP2_ASIC_CFG); base 611 drivers/tty/serial/rp2.c writew(clk_cfg, base + RP2_ASIC_CFG); base 614 drivers/tty/serial/rp2.c writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK); base 615 drivers/tty/serial/rp2.c writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ); base 634 drivers/tty/serial/rp2.c writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL); base 635 drivers/tty/serial/rp2.c readl(up->base + RP2_UART_CTL); base 638 drivers/tty/serial/rp2.c writel(0, up->base + RP2_TXRX_CTL); base 639 drivers/tty/serial/rp2.c writel(0, up->base + RP2_UART_CTL); base 640 drivers/tty/serial/rp2.c readl(up->base + RP2_UART_CTL); base 687 drivers/tty/serial/rp2.c rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING; base 702 drivers/tty/serial/rp2.c p->membase = rp->base; base 707 drivers/tty/serial/rp2.c rp->base += RP2_ASIC_SPACING; base 1243 drivers/tty/serial/sc16is7xx.c s->gpio.base = -1; base 896 drivers/tty/serial/sifive.c void __iomem *base; base 904 drivers/tty/serial/sifive.c base = devm_ioremap_resource(&pdev->dev, mem); base 905 drivers/tty/serial/sifive.c if (IS_ERR(base)) { base 907 drivers/tty/serial/sifive.c return PTR_ERR(base); base 941 drivers/tty/serial/sifive.c ssp->port.membase = base; base 619 drivers/tty/serial/uartlite.c static int ulite_assign(struct device *dev, int id, u32 base, int irq, base 636 drivers/tty/serial/uartlite.c if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) { base 649 drivers/tty/serial/uartlite.c port->mapbase = base; base 323 drivers/tty/tty_io.c dev_t base = MKDEV(p->major, p->minor_start); base 324 drivers/tty/tty_io.c if (device < base || device >= base + p->num) base 326 drivers/tty/tty_io.c *index = device - base; base 423 drivers/tty/vt/keyboard.c if (accent_table[i].diacr == d && accent_table[i].base == ch) base 875 drivers/tty/vt/keyboard.c unsigned int base; base 882 drivers/tty/vt/keyboard.c base = 10; base 886 drivers/tty/vt/keyboard.c base = 16; base 894 drivers/tty/vt/keyboard.c npadch_value = npadch_value * base + value; base 1677 drivers/tty/vt/keyboard.c dia[i].base = conv_uni_to_8bit( base 1678 drivers/tty/vt/keyboard.c accent_table[i].base); base 1748 drivers/tty/vt/keyboard.c accent_table[i].base = base 1749 drivers/tty/vt/keyboard.c conv_8bit_to_uni(dia[i].base); base 4720 drivers/tty/vt/vt.c unsigned int rolled_over, void *base, unsigned int size) base 4722 drivers/tty/vt/vt.c unsigned long ubase = (unsigned long)base; base 4723 drivers/tty/vt/vt.c ptrdiff_t scr_end = (void *)c->vc_scr_end - base; base 4724 drivers/tty/vt/vt.c ptrdiff_t vorigin = (void *)c->vc_visible_origin - base; base 4725 drivers/tty/vt/vt.c ptrdiff_t origin = (void *)c->vc_origin - base; base 81 drivers/uio/uio_pruss.c void __iomem *base = gdev->prussio_vaddr + gdev->pintc_base; base 82 drivers/uio/uio_pruss.c void __iomem *intren_reg = base + PINTC_HIER; base 83 drivers/uio/uio_pruss.c void __iomem *intrdis_reg = base + PINTC_HIDISR; base 84 drivers/uio/uio_pruss.c void __iomem *intrstat_reg = base + PINTC_HIPIR + (intr_bit << 2); base 134 drivers/usb/c67x00/c67x00-drv.c c67x00->hpi.base = ioremap(res->start, resource_size(res)); base 135 drivers/usb/c67x00/c67x00-drv.c if (!c67x00->hpi.base) { base 171 drivers/usb/c67x00/c67x00-drv.c iounmap(c67x00->hpi.base); base 195 drivers/usb/c67x00/c67x00-drv.c iounmap(c67x00->hpi.base); base 73 drivers/usb/c67x00/c67x00-ll-hpi.c return __raw_readw(dev->hpi.base + reg * dev->hpi.regstep); base 79 drivers/usb/c67x00/c67x00-ll-hpi.c __raw_writew(value, dev->hpi.base + reg * dev->hpi.regstep); base 220 drivers/usb/c67x00/c67x00.h void __iomem *base; base 45 drivers/usb/chipidea/ci_hdrc_msm.c void __iomem *base; base 52 drivers/usb/chipidea/ci_hdrc_msm.c void __iomem *addr = ci_msm->base; base 91 drivers/usb/chipidea/ci_hdrc_msm.c u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL); base 93 drivers/usb/chipidea/ci_hdrc_msm.c writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL); base 164 drivers/usb/chipidea/ci_hdrc_msm.c val = readl_relaxed(ci->base + HS_PHY_SEC_CTRL); base 166 drivers/usb/chipidea/ci_hdrc_msm.c writel_relaxed(val, ci->base + HS_PHY_SEC_CTRL); base 211 drivers/usb/chipidea/ci_hdrc_msm.c ci->base = devm_platform_ioremap_resource(pdev, 1); base 212 drivers/usb/chipidea/ci_hdrc_msm.c if (IS_ERR(ci->base)) base 213 drivers/usb/chipidea/ci_hdrc_msm.c return PTR_ERR(ci->base); base 236 drivers/usb/chipidea/core.c static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) base 241 drivers/usb/chipidea/core.c ci->hw_bank.abs = base; base 981 drivers/usb/chipidea/core.c void __iomem *base; base 991 drivers/usb/chipidea/core.c base = devm_ioremap_resource(dev, res); base 992 drivers/usb/chipidea/core.c if (IS_ERR(base)) base 993 drivers/usb/chipidea/core.c return PTR_ERR(base); base 1008 drivers/usb/chipidea/core.c ret = hw_device_init(ci, base); base 117 drivers/usb/chipidea/usbmisc_imx.c void __iomem *base; base 136 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base); base 148 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base); base 151 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base); base 164 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base); base 187 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX25_USB_PHY_CTRL_OFFSET; base 224 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base) | val; base 226 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base) & ~val; base 227 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base); base 244 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET); base 247 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET); base 254 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET; base 261 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET; base 269 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_CTRL_1_OFFSET; base 276 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_UH2_CTRL_OFFSET; base 282 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + base 291 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_UH2_CTRL_OFFSET; base 299 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_CTRL_1_OFFSET; base 306 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_UH3_CTRL_OFFSET; base 313 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + base 321 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_UH3_CTRL_OFFSET; base 347 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + data->index * 4); base 355 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base + data->index * 4); base 372 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base + data->index * 4); base 390 drivers/usb/chipidea/usbmisc_imx.c writel(reg, usbmisc->base + data->index * 4); base 393 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base + data->index * 4); base 395 drivers/usb/chipidea/usbmisc_imx.c usbmisc->base + data->index * 4); base 399 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base + data->index * 4); base 401 drivers/usb/chipidea/usbmisc_imx.c usbmisc->base + data->index * 4); base 402 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET base 405 drivers/usb/chipidea/usbmisc_imx.c writel(reg, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET base 451 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + offset); base 454 drivers/usb/chipidea/usbmisc_imx.c usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + offset); base 475 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + offset); base 482 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + offset); base 499 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX6_USB_OTG1_PHY_CTRL + data->index * 4; base 508 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + data->index * 4); base 510 drivers/usb/chipidea/usbmisc_imx.c usbmisc->base + data->index * 4); base 516 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET); base 518 drivers/usb/chipidea/usbmisc_imx.c writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET); base 537 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base); base 538 drivers/usb/chipidea/usbmisc_imx.c writel(reg | VF610_OVER_CUR_DIS, usbmisc->base); base 554 drivers/usb/chipidea/usbmisc_imx.c val = readl(usbmisc->base); base 556 drivers/usb/chipidea/usbmisc_imx.c writel(val | wakeup_setting, usbmisc->base); base 560 drivers/usb/chipidea/usbmisc_imx.c writel(val & ~wakeup_setting, usbmisc->base); base 577 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base); base 595 drivers/usb/chipidea/usbmisc_imx.c writel(reg, usbmisc->base); base 597 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base + MX7D_USBNC_USB_CTRL2); base 600 drivers/usb/chipidea/usbmisc_imx.c usbmisc->base + MX7D_USBNC_USB_CTRL2); base 789 drivers/usb/chipidea/usbmisc_imx.c data->base = devm_platform_ioremap_resource(pdev, 0); base 790 drivers/usb/chipidea/usbmisc_imx.c if (IS_ERR(data->base)) base 791 drivers/usb/chipidea/usbmisc_imx.c return PTR_ERR(data->base); base 1122 drivers/usb/class/cdc-acm.c acm->read_buffers[i].base, acm->read_buffers[i].dma); base 1392 drivers/usb/class/cdc-acm.c rb->base = usb_alloc_coherent(acm->dev, readsize, GFP_KERNEL, base 1394 drivers/usb/class/cdc-acm.c if (!rb->base) base 1406 drivers/usb/class/cdc-acm.c usb_fill_int_urb(urb, acm->dev, acm->in, rb->base, base 1411 drivers/usb/class/cdc-acm.c usb_fill_bulk_urb(urb, acm->dev, acm->in, rb->base, base 77 drivers/usb/class/cdc-acm.h unsigned char *base; base 792 drivers/usb/dwc2/debugfs.c hsotg->regset->base = hsotg->regs; base 917 drivers/usb/dwc3/debugfs.c dwc->regset->base = dwc->regs - DWC3_GLOBALS_REGS_START; base 39 drivers/usb/dwc3/dwc3-keystone.c static inline u32 kdwc3_readl(void __iomem *base, u32 offset) base 41 drivers/usb/dwc3/dwc3-keystone.c return readl(base + offset); base 44 drivers/usb/dwc3/dwc3-keystone.c static inline void kdwc3_writel(void __iomem *base, u32 offset, u32 value) base 46 drivers/usb/dwc3/dwc3-keystone.c writel(value, base + offset); base 388 drivers/usb/dwc3/dwc3-meson-g12a.c void __iomem *base; base 396 drivers/usb/dwc3/dwc3-meson-g12a.c base = devm_platform_ioremap_resource(pdev, 0); base 397 drivers/usb/dwc3/dwc3-meson-g12a.c if (IS_ERR(base)) base 398 drivers/usb/dwc3/dwc3-meson-g12a.c return PTR_ERR(base); base 400 drivers/usb/dwc3/dwc3-meson-g12a.c priv->regmap = devm_regmap_init_mmio(dev, base, base 118 drivers/usb/dwc3/dwc3-omap.c void __iomem *base; base 141 drivers/usb/dwc3/dwc3-omap.c static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) base 143 drivers/usb/dwc3/dwc3-omap.c return readl(base + offset); base 146 drivers/usb/dwc3/dwc3-omap.c static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) base 148 drivers/usb/dwc3/dwc3-omap.c writel(value, base + offset); base 153 drivers/usb/dwc3/dwc3-omap.c return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL + base 159 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL + base 166 drivers/usb/dwc3/dwc3-omap.c return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 - base 172 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - base 179 drivers/usb/dwc3/dwc3-omap.c return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC + base 185 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + base 192 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + base 199 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - base 205 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + base 211 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - base 462 drivers/usb/dwc3/dwc3-omap.c void __iomem *base; base 479 drivers/usb/dwc3/dwc3-omap.c base = devm_platform_ioremap_resource(pdev, 0); base 480 drivers/usb/dwc3/dwc3-omap.c if (IS_ERR(base)) base 481 drivers/usb/dwc3/dwc3-omap.c return PTR_ERR(base); base 493 drivers/usb/dwc3/dwc3-omap.c omap->base = base; base 507 drivers/usb/dwc3/dwc3-omap.c reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); base 81 drivers/usb/dwc3/dwc3-qcom.c static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) base 85 drivers/usb/dwc3/dwc3-qcom.c reg = readl(base + offset); base 87 drivers/usb/dwc3/dwc3-qcom.c writel(reg, base + offset); base 90 drivers/usb/dwc3/dwc3-qcom.c readl(base + offset); base 93 drivers/usb/dwc3/dwc3-qcom.c static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val) base 97 drivers/usb/dwc3/dwc3-qcom.c reg = readl(base + offset); base 99 drivers/usb/dwc3/dwc3-qcom.c writel(reg, base + offset); base 102 drivers/usb/dwc3/dwc3-qcom.c readl(base + offset); base 98 drivers/usb/dwc3/dwc3-st.c static inline u32 st_dwc3_readl(void __iomem *base, u32 offset) base 100 drivers/usb/dwc3/dwc3-st.c return readl_relaxed(base + offset); base 103 drivers/usb/dwc3/dwc3-st.c static inline void st_dwc3_writel(void __iomem *base, u32 offset, u32 value) base 105 drivers/usb/dwc3/dwc3-st.c writel_relaxed(value, base + offset); base 19 drivers/usb/dwc3/io.h static inline u32 dwc3_readl(void __iomem *base, u32 offset) base 28 drivers/usb/dwc3/io.h value = readl(base + offset - DWC3_GLOBALS_REGS_START); base 35 drivers/usb/dwc3/io.h trace_dwc3_readl(base - DWC3_GLOBALS_REGS_START, offset, value); base 40 drivers/usb/dwc3/io.h static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) base 47 drivers/usb/dwc3/io.h writel(value, base + offset - DWC3_GLOBALS_REGS_START); base 54 drivers/usb/dwc3/io.h trace_dwc3_writel(base - DWC3_GLOBALS_REGS_START, offset, value); base 23 drivers/usb/dwc3/trace.h TP_PROTO(void *base, u32 offset, u32 value), base 24 drivers/usb/dwc3/trace.h TP_ARGS(base, offset, value), base 26 drivers/usb/dwc3/trace.h __field(void *, base) base 31 drivers/usb/dwc3/trace.h __entry->base = base; base 35 drivers/usb/dwc3/trace.h TP_printk("addr %p value %08x", __entry->base + __entry->offset, base 40 drivers/usb/dwc3/trace.h TP_PROTO(void __iomem *base, u32 offset, u32 value), base 41 drivers/usb/dwc3/trace.h TP_ARGS(base, offset, value) base 45 drivers/usb/dwc3/trace.h TP_PROTO(void __iomem *base, u32 offset, u32 value), base 46 drivers/usb/dwc3/trace.h TP_ARGS(base, offset, value) base 41 drivers/usb/early/xhci-dbc.c void __iomem *base; base 88 drivers/usb/early/xhci-dbc.c base = early_ioremap(val64, sz64); base 90 drivers/usb/early/xhci-dbc.c return base; base 957 drivers/usb/early/xhci-dbc.c void __iomem *base; base 974 drivers/usb/early/xhci-dbc.c base = ioremap_nocache(xdbc.xhci_start, xdbc.xhci_length); base 975 drivers/usb/early/xhci-dbc.c if (!base) { base 983 drivers/usb/early/xhci-dbc.c xdbc.xhci_base = base; base 458 drivers/usb/gadget/udc/bdc/bdc.h static inline u32 bdc_readl(void __iomem *base, u32 offset) base 460 drivers/usb/gadget/udc/bdc/bdc.h return readl(base + offset); base 463 drivers/usb/gadget/udc/bdc/bdc.h static inline void bdc_writel(void __iomem *base, u32 offset, u32 value) base 465 drivers/usb/gadget/udc/bdc/bdc.h writel(value, base + offset); base 1744 drivers/usb/gadget/udc/goku_udc.c void __iomem *base = NULL; base 1785 drivers/usb/gadget/udc/goku_udc.c base = ioremap_nocache(resource, len); base 1786 drivers/usb/gadget/udc/goku_udc.c if (base == NULL) { base 1791 drivers/usb/gadget/udc/goku_udc.c dev->regs = (struct goku_udc_regs __iomem *) base; base 1796 drivers/usb/gadget/udc/goku_udc.c INFO(dev, "irq %d, pci mem %p\n", pdev->irq, base); base 2593 drivers/usb/gadget/udc/net2272.c resource_size_t base, len; base 2618 drivers/usb/gadget/udc/net2272.c base = iomem->start; base 2623 drivers/usb/gadget/udc/net2272.c if (!request_mem_region(base, len, driver_name)) { base 2628 drivers/usb/gadget/udc/net2272.c dev->base_addr = ioremap_nocache(base, len); base 2648 drivers/usb/gadget/udc/net2272.c release_mem_region(base, len); base 3617 drivers/usb/gadget/udc/net2280.c void __iomem *base = NULL; base 3662 drivers/usb/gadget/udc/net2280.c base = ioremap_nocache(resource, len); base 3663 drivers/usb/gadget/udc/net2280.c if (base == NULL) { base 3668 drivers/usb/gadget/udc/net2280.c dev->regs = (struct net2280_regs __iomem *) base; base 3669 drivers/usb/gadget/udc/net2280.c dev->usb = (struct net2280_usb_regs __iomem *) (base + 0x0080); base 3670 drivers/usb/gadget/udc/net2280.c dev->pci = (struct net2280_pci_regs __iomem *) (base + 0x0100); base 3671 drivers/usb/gadget/udc/net2280.c dev->dma = (struct net2280_dma_regs __iomem *) (base + 0x0180); base 3672 drivers/usb/gadget/udc/net2280.c dev->dep = (struct net2280_dep_regs __iomem *) (base + 0x0200); base 3673 drivers/usb/gadget/udc/net2280.c dev->epregs = (struct net2280_ep_regs __iomem *) (base + 0x0300); base 3679 drivers/usb/gadget/udc/net2280.c (base + 0x00b4); base 3681 drivers/usb/gadget/udc/net2280.c (base + 0x0700); base 3683 drivers/usb/gadget/udc/net2280.c (base + 0x0800); base 3771 drivers/usb/gadget/udc/net2280.c pdev->irq, base, dev->chiprev); base 74 drivers/usb/gadget/udc/s3c2410_udc.c static inline void udc_writeb(void __iomem *base, u32 value, u32 reg) base 76 drivers/usb/gadget/udc/s3c2410_udc.c writeb(value, base + reg); base 175 drivers/usb/gadget/udc/s3c2410_udc.c static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base) base 177 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG); base 178 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY, base 182 drivers/usb/gadget/udc/s3c2410_udc.c static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base) base 184 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG); base 185 drivers/usb/gadget/udc/s3c2410_udc.c writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG); base 188 drivers/usb/gadget/udc/s3c2410_udc.c static inline void s3c2410_udc_clear_ep0_se(void __iomem *base) base 190 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG); base 191 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG); base 194 drivers/usb/gadget/udc/s3c2410_udc.c static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base) base 196 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG); base 197 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG); base 200 drivers/usb/gadget/udc/s3c2410_udc.c static inline void s3c2410_udc_set_ep0_de(void __iomem *base) base 202 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG); base 203 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG); base 212 drivers/usb/gadget/udc/s3c2410_udc.c static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base) base 214 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG); base 216 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY base 221 drivers/usb/gadget/udc/s3c2410_udc.c static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base) base 223 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG); base 224 drivers/usb/gadget/udc/s3c2410_udc.c udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY base 26 drivers/usb/host/ehci-exynos.c #define EHCI_INSNREG00(base) (base + 0x90) base 32 drivers/usb/host/ehci-mv.c void __iomem *base; base 137 drivers/usb/host/ehci-mv.c ehci_mv->base = devm_ioremap_resource(&pdev->dev, r); base 138 drivers/usb/host/ehci-mv.c if (IS_ERR(ehci_mv->base)) { base 139 drivers/usb/host/ehci-mv.c retval = PTR_ERR(ehci_mv->base); base 150 drivers/usb/host/ehci-mv.c (void __iomem *) ((unsigned long) ehci_mv->base + U2x_CAPREGS_OFFSET); base 60 drivers/usb/host/ehci-omap.c static inline void ehci_write(void __iomem *base, u32 reg, u32 val) base 62 drivers/usb/host/ehci-omap.c __raw_writel(val, base + reg); base 65 drivers/usb/host/ehci-omap.c static inline u32 ehci_read(void __iomem *base, u32 reg) base 67 drivers/usb/host/ehci-omap.c return __raw_readl(base + reg); base 159 drivers/usb/host/ehci-orion.c wrl(USB_WINDOW_BASE(i), cs->base); base 41 drivers/usb/host/ehci-pmcmsp.c u8 *base; base 48 drivers/usb/host/ehci-pmcmsp.c base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; base 53 drivers/usb/host/ehci-pmcmsp.c val = ehci_readl(ehci, (u32 *)base); base 55 drivers/usb/host/ehci-pmcmsp.c (u32 *)base); base 1486 drivers/usb/host/ehci-sched.c u32 now, base, next, start, period, span, now2; base 1577 drivers/usb/host/ehci-sched.c base = ehci->last_iso_frame << 3; base 1578 drivers/usb/host/ehci-sched.c next = (next - base) & (mod - 1); base 1579 drivers/usb/host/ehci-sched.c start = (stream->next_uframe - base) & (mod - 1); base 1590 drivers/usb/host/ehci-sched.c now2 = (now - base) & (mod - 1); base 1595 drivers/usb/host/ehci-sched.c urb, stream->next_uframe, base, period, mod); base 1624 drivers/usb/host/ehci-sched.c urb, start + base, span - period, now2 + base, base 1625 drivers/usb/host/ehci-sched.c base); base 1656 drivers/usb/host/ehci-sched.c start += base; base 72 drivers/usb/host/fhci-tds.c static struct usb_td __iomem *next_bd(struct usb_td __iomem *base, base 77 drivers/usb/host/fhci-tds.c return base; base 121 drivers/usb/host/ohci-tmio.c unsigned long base = hcd->rsrc_start; base 124 drivers/usb/host/ohci-tmio.c tmio_iowrite16(base, tmio->ccr + CCR_BASE); base 125 drivers/usb/host/ohci-tmio.c tmio_iowrite16(base >> 16, tmio->ccr + CCR_BASE + 2); base 679 drivers/usb/host/oxu210hp-hcd.c static inline u32 oxu_readl(void *base, u32 reg) base 681 drivers/usb/host/oxu210hp-hcd.c return readl(base + reg); base 684 drivers/usb/host/oxu210hp-hcd.c static inline void oxu_writel(void *base, u32 reg, u32 val) base 686 drivers/usb/host/oxu210hp-hcd.c writel(val, base + reg); base 4066 drivers/usb/host/oxu210hp-hcd.c static void oxu_configuration(struct platform_device *pdev, void *base) base 4073 drivers/usb/host/oxu210hp-hcd.c oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D); base 4074 drivers/usb/host/oxu210hp-hcd.c oxu_writel(base, OXU_SOFTRESET, OXU_SRESET); base 4075 drivers/usb/host/oxu210hp-hcd.c oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D); base 4077 drivers/usb/host/oxu210hp-hcd.c tmp = oxu_readl(base, OXU_PIOBURSTREADCTRL); base 4078 drivers/usb/host/oxu210hp-hcd.c oxu_writel(base, OXU_PIOBURSTREADCTRL, tmp | 0x0040); base 4080 drivers/usb/host/oxu210hp-hcd.c oxu_writel(base, OXU_ASO, OXU_SPHPOEN | OXU_OVRCCURPUPDEN | base 4083 drivers/usb/host/oxu210hp-hcd.c tmp = oxu_readl(base, OXU_CLKCTRL_SET); base 4084 drivers/usb/host/oxu210hp-hcd.c oxu_writel(base, OXU_CLKCTRL_SET, tmp | OXU_SYSCLKEN | OXU_USBOTGCLKEN); base 4087 drivers/usb/host/oxu210hp-hcd.c oxu_writel(base, OXU_CHIPIRQEN_CLR, 0xff); base 4090 drivers/usb/host/oxu210hp-hcd.c oxu_writel(base, OXU_CHIPIRQSTATUS, 0xff); base 4093 drivers/usb/host/oxu210hp-hcd.c oxu_writel(base, OXU_CHIPIRQEN_SET, OXU_USBSPHLPWUI | OXU_USBOTGLPWUI); base 4096 drivers/usb/host/oxu210hp-hcd.c static int oxu_verify_id(struct platform_device *pdev, void *base) base 4107 drivers/usb/host/oxu210hp-hcd.c id = oxu_readl(base, OXU_DEVICEID); base 4124 drivers/usb/host/oxu210hp-hcd.c void *base, int irq, int otg) base 4133 drivers/usb/host/oxu210hp-hcd.c oxu_writel(base + (otg ? OXU_OTG_CORE_OFFSET : OXU_SPH_CORE_OFFSET), base 4144 drivers/usb/host/oxu210hp-hcd.c hcd->regs = base; base 4161 drivers/usb/host/oxu210hp-hcd.c void *base, int irq) base 4168 drivers/usb/host/oxu210hp-hcd.c oxu_configuration(pdev, base); base 4170 drivers/usb/host/oxu210hp-hcd.c ret = oxu_verify_id(pdev, base); base 4177 drivers/usb/host/oxu210hp-hcd.c hcd = oxu_create(pdev, memstart, memlen, base, irq, 1); base 4186 drivers/usb/host/oxu210hp-hcd.c hcd = oxu_create(pdev, memstart, memlen, base, irq, 0); base 4194 drivers/usb/host/oxu210hp-hcd.c oxu_writel(base, OXU_CHIPIRQEN_SET, base 4195 drivers/usb/host/oxu210hp-hcd.c oxu_readl(base, OXU_CHIPIRQEN_SET) | 3); base 4210 drivers/usb/host/oxu210hp-hcd.c void *base; base 4231 drivers/usb/host/oxu210hp-hcd.c base = devm_ioremap_resource(&pdev->dev, res); base 4232 drivers/usb/host/oxu210hp-hcd.c if (IS_ERR(base)) { base 4233 drivers/usb/host/oxu210hp-hcd.c ret = PTR_ERR(base); base 4256 drivers/usb/host/oxu210hp-hcd.c ret = oxu_init(pdev, memstart, memlen, base, irq); base 637 drivers/usb/host/pci-quirks.c void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) base 649 drivers/usb/host/pci-quirks.c outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); base 652 drivers/usb/host/pci-quirks.c if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) base 658 drivers/usb/host/pci-quirks.c outw(0, base + UHCI_USBINTR); base 659 drivers/usb/host/pci-quirks.c outw(0, base + UHCI_USBCMD); base 669 drivers/usb/host/pci-quirks.c int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) base 691 drivers/usb/host/pci-quirks.c cmd = inw(base + UHCI_USBCMD); base 699 drivers/usb/host/pci-quirks.c intr = inw(base + UHCI_USBINTR); base 709 drivers/usb/host/pci-quirks.c uhci_reset_hc(pdev, base); base 725 drivers/usb/host/pci-quirks.c unsigned long base = 0; base 733 drivers/usb/host/pci-quirks.c base = pci_resource_start(pdev, i); base 737 drivers/usb/host/pci-quirks.c if (base) base 738 drivers/usb/host/pci-quirks.c uhci_check_and_reset_hc(pdev, base); base 748 drivers/usb/host/pci-quirks.c void __iomem *base; base 757 drivers/usb/host/pci-quirks.c base = pci_ioremap_bar(pdev, 0); base 758 drivers/usb/host/pci-quirks.c if (base == NULL) base 768 drivers/usb/host/pci-quirks.c control = readl(base + OHCI_CONTROL); base 778 drivers/usb/host/pci-quirks.c writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); base 779 drivers/usb/host/pci-quirks.c writel(OHCI_OCR, base + OHCI_CMDSTATUS); base 781 drivers/usb/host/pci-quirks.c readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { base 788 drivers/usb/host/pci-quirks.c readl(base + OHCI_CONTROL)); base 793 drivers/usb/host/pci-quirks.c writel((u32) ~0, base + OHCI_INTRDISABLE); base 796 drivers/usb/host/pci-quirks.c writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); base 797 drivers/usb/host/pci-quirks.c readl(base + OHCI_CONTROL); base 801 drivers/usb/host/pci-quirks.c fminterval = readl(base + OHCI_FMINTERVAL); base 803 drivers/usb/host/pci-quirks.c writel(OHCI_HCR, base + OHCI_CMDSTATUS); base 807 drivers/usb/host/pci-quirks.c if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0) base 813 drivers/usb/host/pci-quirks.c writel(fminterval, base + OHCI_FMINTERVAL); base 816 drivers/usb/host/pci-quirks.c iounmap(base); base 928 drivers/usb/host/pci-quirks.c void __iomem *base, *op_reg_base; base 936 drivers/usb/host/pci-quirks.c base = pci_ioremap_bar(pdev, 0); base 937 drivers/usb/host/pci-quirks.c if (base == NULL) base 940 drivers/usb/host/pci-quirks.c cap_length = readb(base); base 941 drivers/usb/host/pci-quirks.c op_reg_base = base + cap_length; base 947 drivers/usb/host/pci-quirks.c hcc_params = readl(base + EHCI_HCC_PARAMS); base 991 drivers/usb/host/pci-quirks.c iounmap(base); base 1143 drivers/usb/host/pci-quirks.c void __iomem *base; base 1153 drivers/usb/host/pci-quirks.c base = ioremap_nocache(pci_resource_start(pdev, 0), len); base 1154 drivers/usb/host/pci-quirks.c if (base == NULL) base 1161 drivers/usb/host/pci-quirks.c ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY); base 1171 drivers/usb/host/pci-quirks.c val = readl(base + ext_cap_offset); base 1178 drivers/usb/host/pci-quirks.c writel(val, base + ext_cap_offset); base 1183 drivers/usb/host/pci-quirks.c writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset); base 1186 drivers/usb/host/pci-quirks.c timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED, base 1194 drivers/usb/host/pci-quirks.c writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset); base 1198 drivers/usb/host/pci-quirks.c val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); base 1204 drivers/usb/host/pci-quirks.c writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); base 1210 drivers/usb/host/pci-quirks.c op_reg_base = base + XHCI_HC_LENGTH(readl(base)); base 1241 drivers/usb/host/pci-quirks.c iounmap(base); base 6 drivers/usb/host/pci-quirks.h void uhci_reset_hc(struct pci_dev *pdev, unsigned long base); base 7 drivers/usb/host/pci-quirks.h int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base); base 18 drivers/usb/host/sl811.h #define SL811_EP_A(base) ((base) + 0) base 19 drivers/usb/host/sl811.h #define SL811_EP_B(base) ((base) + 8) base 836 drivers/usb/host/xhci-dbgcap.c void __iomem *base; base 839 drivers/usb/host/xhci-dbgcap.c base = &xhci->cap_regs->hc_capbase; base 840 drivers/usb/host/xhci-dbgcap.c dbc_cap_offs = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_DEBUG); base 848 drivers/usb/host/xhci-dbgcap.c dbc->regs = base + dbc_cap_offs; base 113 drivers/usb/host/xhci-debugfs.c static void xhci_debugfs_regset(struct xhci_hcd *xhci, u32 base, base 134 drivers/usb/host/xhci-debugfs.c regset->base = hcd->regs + base; base 146 drivers/usb/host/xhci-debugfs.c void __iomem *base = &xhci->cap_regs->hc_capbase; base 148 drivers/usb/host/xhci-debugfs.c offset = xhci_find_next_ext_cap(base, 0, cap_id); base 151 drivers/usb/host/xhci-debugfs.c psic = XHCI_EXT_PORT_PSIC(readl(base + offset + 8)); base 158 drivers/usb/host/xhci-debugfs.c offset = xhci_find_next_ext_cap(base, offset, cap_id); base 85 drivers/usb/host/xhci-ext-caps.c void __iomem *base = &xhci->cap_regs->hc_capbase; base 89 drivers/usb/host/xhci-ext-caps.c offset = xhci_find_next_ext_cap(base, 0, 0); base 92 drivers/usb/host/xhci-ext-caps.c val = readl(base + offset); base 104 drivers/usb/host/xhci-ext-caps.c offset = xhci_find_next_ext_cap(base, offset, 0); base 97 drivers/usb/host/xhci-ext-caps.h static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id) base 105 drivers/usb/host/xhci-ext-caps.h val = readl(base + XHCI_HCC_PARAMS_OFFSET); base 113 drivers/usb/host/xhci-ext-caps.h val = readl(base + offset); base 2269 drivers/usb/host/xhci-mem.c void __iomem *base; base 2301 drivers/usb/host/xhci-mem.c base = &xhci->cap_regs->hc_capbase; base 2303 drivers/usb/host/xhci-mem.c cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL); base 2313 drivers/usb/host/xhci-mem.c offset = xhci_find_next_ext_cap(base, offset, base 2330 drivers/usb/host/xhci-mem.c xhci_add_in_port(xhci, num_ports, base + offset, cap_count); base 2334 drivers/usb/host/xhci-mem.c offset = xhci_find_next_ext_cap(base, offset, base 344 drivers/usb/host/xhci-mtk-sch.c u32 base = offset + i * sch_ep->esit; base 347 drivers/usb/host/xhci-mtk-sch.c bw = sch_bw->bus_bw[base + j] + base 360 drivers/usb/host/xhci-mtk-sch.c u32 base; base 366 drivers/usb/host/xhci-mtk-sch.c base = sch_ep->offset + i * sch_ep->esit; base 369 drivers/usb/host/xhci-mtk-sch.c sch_bw->bus_bw[base + j] += base 372 drivers/usb/host/xhci-mtk-sch.c sch_bw->bus_bw[base + j] -= base 455 drivers/usb/host/xhci-mtk-sch.c u32 base, num_esit; base 460 drivers/usb/host/xhci-mtk-sch.c base = sch_ep->offset + i * sch_ep->esit; base 462 drivers/usb/host/xhci-mtk-sch.c set_bit(base + j, tt->split_bit_map); base 22 drivers/usb/host/xhci-mvebu.c static void xhci_mvebu_mbus_config(void __iomem *base, base 29 drivers/usb/host/xhci-mvebu.c writel(0, base + USB3_WIN_CTRL(win)); base 30 drivers/usb/host/xhci-mvebu.c writel(0, base + USB3_WIN_BASE(win)); base 39 drivers/usb/host/xhci-mvebu.c base + USB3_WIN_CTRL(win)); base 41 drivers/usb/host/xhci-mvebu.c writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(win)); base 50 drivers/usb/host/xhci-mvebu.c void __iomem *base; base 61 drivers/usb/host/xhci-mvebu.c base = ioremap(res->start, resource_size(res)); base 62 drivers/usb/host/xhci-mvebu.c if (!base) base 66 drivers/usb/host/xhci-mvebu.c xhci_mvebu_mbus_config(base, dram); base 72 drivers/usb/host/xhci-mvebu.c iounmap(base); base 55 drivers/usb/isp1760/isp1760-core.h static inline u32 isp1760_read32(void __iomem *base, u32 reg) base 57 drivers/usb/isp1760/isp1760-core.h return readl(base + reg); base 60 drivers/usb/isp1760/isp1760-core.h static inline void isp1760_write32(void __iomem *base, u32 reg, u32 val) base 62 drivers/usb/isp1760/isp1760-core.h writel(val, base + reg); base 163 drivers/usb/isp1760/isp1760-hcd.c static u32 reg_read32(void __iomem *base, u32 reg) base 165 drivers/usb/isp1760/isp1760-hcd.c return isp1760_read32(base, reg); base 168 drivers/usb/isp1760/isp1760-hcd.c static void reg_write32(void __iomem *base, u32 reg, u32 val) base 170 drivers/usb/isp1760/isp1760-hcd.c isp1760_write32(base, reg, val); base 280 drivers/usb/isp1760/isp1760-hcd.c static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot, base 283 drivers/usb/isp1760/isp1760-hcd.c reg_write32(base, HC_MEMORY_REG, base 286 drivers/usb/isp1760/isp1760-hcd.c bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0), base 290 drivers/usb/isp1760/isp1760-hcd.c static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, base 293 drivers/usb/isp1760/isp1760-hcd.c mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), base 298 drivers/usb/isp1760/isp1760-hcd.c mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, base 510 drivers/usb/isp1760/isp1760-hcd.c static u32 base_to_chip(u32 base) base 512 drivers/usb/isp1760/isp1760-hcd.c return ((base - 0x400) >> 3); base 137 drivers/usb/mtu3/mtu3.h u32 base; base 396 drivers/usb/mtu3/mtu3.h static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data) base 398 drivers/usb/mtu3/mtu3.h writel(data, base + offset); base 401 drivers/usb/mtu3/mtu3.h static inline u32 mtu3_readl(void __iomem *base, u32 offset) base 403 drivers/usb/mtu3/mtu3.h return readl(base + offset); base 406 drivers/usb/mtu3/mtu3.h static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits) base 408 drivers/usb/mtu3/mtu3.h void __iomem *addr = base + offset; base 414 drivers/usb/mtu3/mtu3.h static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits) base 416 drivers/usb/mtu3/mtu3.h void __iomem *addr = base + offset; base 43 drivers/usb/mtu3/mtu3_core.c mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit; base 58 drivers/usb/mtu3/mtu3_core.c if (unlikely(addr < fifo->base || bits > fifo->limit)) base 61 drivers/usb/mtu3/mtu3_core.c start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT; base 447 drivers/usb/mtu3/mtu3_core.c tx_fifo->base = 0; base 453 drivers/usb/mtu3/mtu3_core.c rx_fifo->base = 0; base 460 drivers/usb/mtu3/mtu3_core.c tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE; base 465 drivers/usb/mtu3/mtu3_core.c rx_fifo->base = base 466 drivers/usb/mtu3/mtu3_core.c tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT; base 473 drivers/usb/mtu3/mtu3_core.c __func__, tx_fifo->base, tx_fifo->limit, base 474 drivers/usb/mtu3/mtu3_core.c rx_fifo->base, rx_fifo->limit); base 123 drivers/usb/mtu3/mtu3_debugfs.c static void mtu3_debugfs_regset(struct mtu3 *mtu, void __iomem *base, base 138 drivers/usb/mtu3/mtu3_debugfs.c regset->base = base; base 354 drivers/usb/musb/cppi_dma.c void __iomem *base = c->controller->mregs; base 357 drivers/usb/musb/cppi_dma.c musb_ep_select(base, c->index + 1); base 384 drivers/usb/musb/cppi_dma.c void __iomem *base = c->controller->mregs; base 387 drivers/usb/musb/cppi_dma.c musb_ep_select(base, c->index + 1); base 454 drivers/usb/musb/da8xx.c da8xx_dma_controller_create(struct musb *musb, void __iomem *base) base 458 drivers/usb/musb/da8xx.c controller = cppi41_dma_controller_create(musb, base); base 397 drivers/usb/musb/musb_core.c (*musb_dma_controller_create)(struct musb *musb, void __iomem *base); base 2446 drivers/usb/musb/musb_core.c void __iomem *base; base 2452 drivers/usb/musb/musb_core.c base = devm_ioremap_resource(dev, iomem); base 2453 drivers/usb/musb/musb_core.c if (IS_ERR(base)) base 2454 drivers/usb/musb/musb_core.c return PTR_ERR(base); base 2456 drivers/usb/musb/musb_core.c return musb_init_controller(dev, irq, base); base 171 drivers/usb/musb/musb_core.h (*dma_init) (struct musb *musb, void __iomem *base); base 750 drivers/usb/musb/musb_cppi41.c cppi41_dma_controller_create(struct musb *musb, void __iomem *base) base 192 drivers/usb/musb/musb_dma.h musbhs_dma_controller_create(struct musb *musb, void __iomem *base); base 196 drivers/usb/musb/musb_dma.h tusb_dma_controller_create(struct musb *musb, void __iomem *base); base 200 drivers/usb/musb/musb_dma.h cppi_dma_controller_create(struct musb *musb, void __iomem *base); base 204 drivers/usb/musb/musb_dma.h cppi41_dma_controller_create(struct musb *musb, void __iomem *base); base 208 drivers/usb/musb/musb_dma.h ux500_dma_controller_create(struct musb *musb, void __iomem *base); base 419 drivers/usb/musb/musb_dsps.c glue->regset.base = musb->ctrl_base; base 654 drivers/usb/musb/musb_dsps.c dsps_dma_controller_create(struct musb *musb, void __iomem *base) base 660 drivers/usb/musb/musb_dsps.c controller = cppi41_dma_controller_create(musb, base); base 998 drivers/usb/musb/musb_gadget_ep0.c void __iomem *base, *regs; base 1008 drivers/usb/musb/musb_gadget_ep0.c base = musb->mregs; base 1019 drivers/usb/musb/musb_gadget_ep0.c musb_ep_select(base, 0); base 73 drivers/usb/musb/musbhsdma.c void __iomem *base; base 155 drivers/usb/musb/musbhsdma.c void __iomem *mbase = controller->base; base 228 drivers/usb/musb/musbhsdma.c void __iomem *mbase = musb_channel->controller->base; base 278 drivers/usb/musb/musbhsdma.c void __iomem *mbase = controller->base; base 402 drivers/usb/musb/musbhsdma.c void __iomem *base) base 420 drivers/usb/musb/musbhsdma.c controller->base = base; base 315 drivers/usb/musb/sunxi.c sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base) base 583 drivers/usb/musb/tusb6010_omap.c tusb_dma_controller_create(struct musb *musb, void __iomem *base) base 358 drivers/usb/musb/ux500_dma.c ux500_dma_controller_create(struct musb *musb, void __iomem *base) base 33 drivers/usb/phy/phy-keystone.c static inline u32 keystone_usbphy_readl(void __iomem *base, u32 offset) base 35 drivers/usb/phy/phy-keystone.c return readl(base + offset); base 38 drivers/usb/phy/phy-keystone.c static inline void keystone_usbphy_writel(void __iomem *base, base 41 drivers/usb/phy/phy-keystone.c writel(value, base + offset); base 235 drivers/usb/phy/phy-mxs-usb.c void __iomem *base = mxs_phy->phy.io_priv; base 240 drivers/usb/phy/phy-mxs-usb.c phytx = readl(base + HW_USBPHY_TX); base 243 drivers/usb/phy/phy-mxs-usb.c writel(phytx, base + HW_USBPHY_TX); base 247 drivers/usb/phy/phy-mxs-usb.c static int mxs_phy_pll_enable(void __iomem *base, bool enable) base 254 drivers/usb/phy/phy-mxs-usb.c writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_SET); base 255 drivers/usb/phy/phy-mxs-usb.c writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_CLR); base 256 drivers/usb/phy/phy-mxs-usb.c writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_SET); base 257 drivers/usb/phy/phy-mxs-usb.c ret = readl_poll_timeout(base + HW_USBPHY_PLL_SIC, base 263 drivers/usb/phy/phy-mxs-usb.c writel(BM_USBPHY_PLL_EN_USB_CLKS, base + base 266 drivers/usb/phy/phy-mxs-usb.c writel(BM_USBPHY_PLL_EN_USB_CLKS, base + base 268 drivers/usb/phy/phy-mxs-usb.c writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_CLR); base 269 drivers/usb/phy/phy-mxs-usb.c writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_SET); base 270 drivers/usb/phy/phy-mxs-usb.c writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_CLR); base 279 drivers/usb/phy/phy-mxs-usb.c void __iomem *base = mxs_phy->phy.io_priv; base 282 drivers/usb/phy/phy-mxs-usb.c ret = mxs_phy_pll_enable(base, true); base 287 drivers/usb/phy/phy-mxs-usb.c ret = stmp_reset_block(base + HW_USBPHY_CTRL); base 292 drivers/usb/phy/phy-mxs-usb.c writel(0, base + HW_USBPHY_PWD); base 306 drivers/usb/phy/phy-mxs-usb.c base + HW_USBPHY_CTRL_SET); base 309 drivers/usb/phy/phy-mxs-usb.c writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET); base 330 drivers/usb/phy/phy-mxs-usb.c mxs_phy_pll_enable(base, false); base 359 drivers/usb/phy/phy-mxs-usb.c void __iomem *base = mxs_phy->phy.io_priv; base 364 drivers/usb/phy/phy-mxs-usb.c base + HW_USBPHY_DEBUG_CLR); base 382 drivers/usb/phy/phy-mxs-usb.c base + HW_USBPHY_DEBUG_SET); base 391 drivers/usb/phy/phy-mxs-usb.c void __iomem *base = mxs_phy->phy.io_priv; base 392 drivers/usb/phy/phy-mxs-usb.c u32 phyctrl = readl(base + HW_USBPHY_CTRL); base 681 drivers/usb/phy/phy-mxs-usb.c void __iomem *base = phy->io_priv; base 695 drivers/usb/phy/phy-mxs-usb.c base + HW_USBPHY_DEBUG_CLR); base 705 drivers/usb/phy/phy-mxs-usb.c base + HW_USBPHY_DEBUG_SET); base 714 drivers/usb/phy/phy-mxs-usb.c void __iomem *base; base 727 drivers/usb/phy/phy-mxs-usb.c base = devm_ioremap_resource(&pdev->dev, res); base 728 drivers/usb/phy/phy-mxs-usb.c if (IS_ERR(base)) base 729 drivers/usb/phy/phy-mxs-usb.c return PTR_ERR(base); base 789 drivers/usb/phy/phy-mxs-usb.c mxs_phy->phy.io_priv = base; base 22 drivers/usb/phy/phy-omap-otg.c void __iomem *base; base 44 drivers/usb/phy/phy-omap-otg.c l = readl(otg_dev->base + OMAP_OTG_CTRL); base 47 drivers/usb/phy/phy-omap-otg.c writel(l, otg_dev->base + OMAP_OTG_CTRL); base 105 drivers/usb/phy/phy-omap-otg.c otg_dev->base = devm_ioremap_resource(&pdev->dev, &pdev->resource[0]); base 106 drivers/usb/phy/phy-omap-otg.c if (IS_ERR(otg_dev->base)) base 107 drivers/usb/phy/phy-omap-otg.c return PTR_ERR(otg_dev->base); base 128 drivers/usb/phy/phy-omap-otg.c rev = readl(otg_dev->base); base 199 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->regs; base 203 drivers/usb/phy/phy-tegra-usb.c val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); base 206 drivers/usb/phy/phy-tegra-usb.c writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); base 208 drivers/usb/phy/phy-tegra-usb.c val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; base 211 drivers/usb/phy/phy-tegra-usb.c writel(val, base + TEGRA_USB_PORTSC1); base 217 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->regs; base 221 drivers/usb/phy/phy-tegra-usb.c val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); base 226 drivers/usb/phy/phy-tegra-usb.c writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); base 228 drivers/usb/phy/phy-tegra-usb.c val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; base 233 drivers/usb/phy/phy-tegra-usb.c writel(val, base + TEGRA_USB_PORTSC1); base 321 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->pad_regs; base 329 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BIAS_CFG0); base 341 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BIAS_CFG0); base 352 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->pad_regs; base 364 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BIAS_CFG0); base 366 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BIAS_CFG0); base 387 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->regs; base 394 drivers/usb/phy/phy-tegra-usb.c if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0) base 398 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 400 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 404 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 406 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 410 drivers/usb/phy/phy-tegra-usb.c if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) base 418 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->regs; base 425 drivers/usb/phy/phy-tegra-usb.c if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, base 430 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 432 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 436 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 438 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 442 drivers/usb/phy/phy-tegra-usb.c if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, base 451 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->regs; base 454 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 456 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 459 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB1_LEGACY_CTRL); base 461 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB1_LEGACY_CTRL); base 464 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_TX_CFG0); base 466 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_TX_CFG0); base 468 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_HSRX_CFG0); base 472 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_HSRX_CFG0); base 474 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_HSRX_CFG1); base 477 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_HSRX_CFG1); base 479 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_DEBOUNCE_CFG0); base 482 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_DEBOUNCE_CFG0); base 484 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_MISC_CFG0); base 486 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_MISC_CFG0); base 489 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_MISC_CFG1); base 494 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_MISC_CFG1); base 496 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_PLL_CFG1); base 501 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_PLL_CFG1); base 505 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 507 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 509 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BAT_CHRG_CFG0); base 511 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BAT_CHRG_CFG0); base 513 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BAT_CHRG_CFG0); base 515 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BAT_CHRG_CFG0); base 520 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_XCVR_CFG0); base 538 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_XCVR_CFG0); base 540 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_XCVR_CFG1); base 544 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_XCVR_CFG1); base 546 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BIAS_CFG1); base 549 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BIAS_CFG1); base 551 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_SPARE_CFG0); base 556 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_SPARE_CFG0); base 559 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 561 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 564 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 566 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 569 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB1_LEGACY_CTRL); base 572 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB1_LEGACY_CTRL); base 574 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 576 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 582 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_USBMODE); base 588 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_USBMODE); base 600 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->regs; base 605 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 608 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 611 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 613 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 615 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_BAT_CHRG_CFG0); base 617 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_BAT_CHRG_CFG0); base 619 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_XCVR_CFG0); base 622 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_XCVR_CFG0); base 624 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_XCVR_CFG1); base 627 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_XCVR_CFG1); base 635 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->regs; base 637 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_TX_CFG0); base 639 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_TX_CFG0); base 645 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->regs; base 647 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_TX_CFG0); base 649 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_TX_CFG0); base 656 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->regs; base 658 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_MISC_CFG0); base 664 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_MISC_CFG0); base 667 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_MISC_CFG0); base 669 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_MISC_CFG0); base 676 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->regs; base 678 drivers/usb/phy/phy-tegra-usb.c val = readl(base + UTMIP_MISC_CFG0); base 680 drivers/usb/phy/phy-tegra-usb.c writel(val, base + UTMIP_MISC_CFG0); base 688 drivers/usb/phy/phy-tegra-usb.c void __iomem *base = phy->regs; base 707 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 709 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 711 drivers/usb/phy/phy-tegra-usb.c val = readl(base + ULPI_TIMING_CTRL_0); base 713 drivers/usb/phy/phy-tegra-usb.c writel(val, base + ULPI_TIMING_CTRL_0); base 715 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 717 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 720 drivers/usb/phy/phy-tegra-usb.c writel(val, base + ULPI_TIMING_CTRL_1); base 725 drivers/usb/phy/phy-tegra-usb.c writel(val, base + ULPI_TIMING_CTRL_1); base 731 drivers/usb/phy/phy-tegra-usb.c writel(val, base + ULPI_TIMING_CTRL_1); base 746 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 748 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 751 drivers/usb/phy/phy-tegra-usb.c val = readl(base + USB_SUSP_CTRL); base 753 drivers/usb/phy/phy-tegra-usb.c writel(val, base + USB_SUSP_CTRL); base 64 drivers/usb/renesas_usbhs/common.c return ioread16(priv->base + reg); base 69 drivers/usb/renesas_usbhs/common.c iowrite16(data, priv->base + reg); base 418 drivers/usb/renesas_usbhs/common.c usbhs_platform_call(priv, power_ctrl, pdev, priv->base, enable); base 427 drivers/usb/renesas_usbhs/common.c usbhs_platform_call(priv, power_ctrl, pdev, priv->base, enable); base 623 drivers/usb/renesas_usbhs/common.c priv->base = devm_ioremap_resource(&pdev->dev, res); base 624 drivers/usb/renesas_usbhs/common.c if (IS_ERR(priv->base)) base 625 drivers/usb/renesas_usbhs/common.c return PTR_ERR(priv->base); base 253 drivers/usb/renesas_usbhs/common.h void __iomem *base; base 314 drivers/usb/renesas_usbhs/fifo.c u16 base = usbhs_pipe_number(pipe); /* CURPIPE */ base 321 drivers/usb/renesas_usbhs/fifo.c base |= (1 == write) << 5; /* ISEL */ base 328 drivers/usb/renesas_usbhs/fifo.c usbhs_write(priv, fifo->sel, base | MBW_32); base 332 drivers/usb/renesas_usbhs/fifo.c if (base == (mask & usbhs_read(priv, fifo->sel))) { base 498 drivers/usb/renesas_usbhs/fifo.c void __iomem *addr = priv->base + fifo->port; base 645 drivers/usb/renesas_usbhs/fifo.c void __iomem *addr = priv->base + fifo->port; base 45 drivers/usb/renesas_usbhs/rcar2.c void __iomem *base, int enable) base 39 drivers/usb/renesas_usbhs/rcar3.c iowrite32(data, priv->base + reg); base 44 drivers/usb/renesas_usbhs/rcar3.c return ioread32(priv->base + reg); base 53 drivers/usb/renesas_usbhs/rcar3.c void __iomem *base, int enable) base 72 drivers/usb/renesas_usbhs/rcar3.c void __iomem *base, int enable) base 39 drivers/usb/renesas_usbhs/rza2.c void __iomem *base, int enable) base 46 drivers/usb/roles/intel-xhci-usb-role-switch.c void __iomem *base; base 81 drivers/usb/roles/intel-xhci-usb-role-switch.c val = readl(data->base + DUAL_ROLE_CFG0); base 104 drivers/usb/roles/intel-xhci-usb-role-switch.c writel(val, data->base + DUAL_ROLE_CFG0); base 113 drivers/usb/roles/intel-xhci-usb-role-switch.c val = readl(data->base + DUAL_ROLE_CFG1); base 136 drivers/usb/roles/intel-xhci-usb-role-switch.c val = readl(data->base + DUAL_ROLE_CFG0); base 164 drivers/usb/roles/intel-xhci-usb-role-switch.c data->base = devm_ioremap_nocache(dev, res->start, resource_size(res)); base 165 drivers/usb/roles/intel-xhci-usb-role-switch.c if (!data->base) base 1739 drivers/usb/serial/cp210x.c priv->gc.base = -1; base 1088 drivers/usb/serial/ftdi_sio.c static unsigned short int ftdi_232am_baud_base_to_divisor(int baud, int base); base 1090 drivers/usb/serial/ftdi_sio.c static u32 ftdi_232bm_baud_base_to_divisor(int baud, int base); base 1092 drivers/usb/serial/ftdi_sio.c static u32 ftdi_2232h_baud_base_to_divisor(int baud, int base); base 1140 drivers/usb/serial/ftdi_sio.c static unsigned short int ftdi_232am_baud_base_to_divisor(int baud, int base) base 1144 drivers/usb/serial/ftdi_sio.c int divisor3 = DIV_ROUND_CLOSEST(base, 2 * baud); base 1165 drivers/usb/serial/ftdi_sio.c static u32 ftdi_232bm_baud_base_to_divisor(int baud, int base) base 1170 drivers/usb/serial/ftdi_sio.c int divisor3 = DIV_ROUND_CLOSEST(base, 2 * baud); base 1186 drivers/usb/serial/ftdi_sio.c static u32 ftdi_2232h_baud_base_to_divisor(int baud, int base) base 1193 drivers/usb/serial/ftdi_sio.c divisor3 = DIV_ROUND_CLOSEST(8 * base, 10 * baud); base 2176 drivers/usb/serial/ftdi_sio.c priv->gc.base = -1; base 496 drivers/usb/storage/freecom.c int from, base; base 522 drivers/usb/storage/freecom.c base = ((length - 1) / 16) * 16; base 531 drivers/usb/storage/freecom.c if (buffer[base+i] >= 32 && buffer[base+i] <= 126) base 532 drivers/usb/storage/freecom.c line[offset++] = buffer[base+i]; base 128 drivers/usb/typec/ucsi/ucsi_ccg.c struct version_format base; base 138 drivers/usb/typec/ucsi/ucsi_ccg.c struct version_format base; base 807 drivers/usb/typec/ucsi/ucsi_ccg.c } else if (le16_to_cpu(version[FW1].base.build) < base 231 drivers/usb/usbip/stub_rx.c priv->seqnum = pdu->base.seqnum; base 270 drivers/usb/usbip/stub_rx.c stub_enqueue_ret_unlink(sdev, pdu->base.seqnum, 0); base 282 drivers/usb/usbip/stub_rx.c if (pdu->base.devid == sdev->devid) { base 311 drivers/usb/usbip/stub_rx.c priv->seqnum = pdu->base.seqnum; base 330 drivers/usb/usbip/stub_rx.c int epnum = pdu->base.ep; base 331 drivers/usb/usbip/stub_rx.c int dir = pdu->base.direction; base 599 drivers/usb/usbip/stub_rx.c pdu->base.seqnum); base 657 drivers/usb/usbip/stub_rx.c switch (pdu.base.command) { base 107 drivers/usb/usbip/stub_tx.c static inline void setup_base_pdu(struct usbip_header_basic *base, base 110 drivers/usb/usbip/stub_tx.c base->command = command; base 111 drivers/usb/usbip/stub_tx.c base->seqnum = seqnum; base 112 drivers/usb/usbip/stub_tx.c base->devid = 0; base 113 drivers/usb/usbip/stub_tx.c base->ep = 0; base 114 drivers/usb/usbip/stub_tx.c base->direction = 0; base 121 drivers/usb/usbip/stub_tx.c setup_base_pdu(&rpdu->base, USBIP_RET_SUBMIT, priv->seqnum); base 128 drivers/usb/usbip/stub_tx.c setup_base_pdu(&rpdu->base, USBIP_RET_UNLINK, unlink->seqnum); base 205 drivers/usb/usbip/stub_tx.c pdu_header.base.seqnum); base 262 drivers/usb/usbip/usbip_common.c pdu->base.command, base 263 drivers/usb/usbip/usbip_common.c pdu->base.seqnum, base 264 drivers/usb/usbip/usbip_common.c pdu->base.devid, base 265 drivers/usb/usbip/usbip_common.c pdu->base.direction, base 266 drivers/usb/usbip/usbip_common.c pdu->base.ep); base 268 drivers/usb/usbip/usbip_common.c switch (pdu->base.command) { base 415 drivers/usb/usbip/usbip_common.c static void correct_endian_basic(struct usbip_header_basic *base, int send) base 418 drivers/usb/usbip/usbip_common.c base->command = cpu_to_be32(base->command); base 419 drivers/usb/usbip/usbip_common.c base->seqnum = cpu_to_be32(base->seqnum); base 420 drivers/usb/usbip/usbip_common.c base->devid = cpu_to_be32(base->devid); base 421 drivers/usb/usbip/usbip_common.c base->direction = cpu_to_be32(base->direction); base 422 drivers/usb/usbip/usbip_common.c base->ep = cpu_to_be32(base->ep); base 424 drivers/usb/usbip/usbip_common.c base->command = be32_to_cpu(base->command); base 425 drivers/usb/usbip/usbip_common.c base->seqnum = be32_to_cpu(base->seqnum); base 426 drivers/usb/usbip/usbip_common.c base->devid = be32_to_cpu(base->devid); base 427 drivers/usb/usbip/usbip_common.c base->direction = be32_to_cpu(base->direction); base 428 drivers/usb/usbip/usbip_common.c base->ep = be32_to_cpu(base->ep); base 493 drivers/usb/usbip/usbip_common.c cmd = pdu->base.command; base 495 drivers/usb/usbip/usbip_common.c correct_endian_basic(&pdu->base, send); base 498 drivers/usb/usbip/usbip_common.c cmd = pdu->base.command; base 208 drivers/usb/usbip/usbip_common.h struct usbip_header_basic base; base 65 drivers/usb/usbip/vhci_rx.c urb = pickup_urb_and_free_priv(vdev, pdu->base.seqnum); base 70 drivers/usb/usbip/vhci_rx.c pdu->base.seqnum, base 101 drivers/usb/usbip/vhci_rx.c usbip_dbg_vhci_rx("now giveback urb %u\n", pdu->base.seqnum); base 122 drivers/usb/usbip/vhci_rx.c if (unlink->seqnum == pdu->base.seqnum) { base 151 drivers/usb/usbip/vhci_rx.c pdu->base.seqnum); base 166 drivers/usb/usbip/vhci_rx.c pdu->base.seqnum); base 168 drivers/usb/usbip/vhci_rx.c usbip_dbg_vhci_rx("now giveback urb %d\n", pdu->base.seqnum); base 240 drivers/usb/usbip/vhci_rx.c switch (pdu.base.command) { base 249 drivers/usb/usbip/vhci_rx.c pr_err("unknown pdu %u\n", pdu.base.command); base 21 drivers/usb/usbip/vhci_tx.c pdup->base.command = USBIP_CMD_SUBMIT; base 22 drivers/usb/usbip/vhci_tx.c pdup->base.seqnum = priv->seqnum; base 23 drivers/usb/usbip/vhci_tx.c pdup->base.devid = vdev->devid; base 24 drivers/usb/usbip/vhci_tx.c pdup->base.direction = usb_pipein(urb->pipe) ? base 26 drivers/usb/usbip/vhci_tx.c pdup->base.ep = usb_pipeendpoint(urb->pipe); base 207 drivers/usb/usbip/vhci_tx.c pdu_header.base.command = USBIP_CMD_UNLINK; base 208 drivers/usb/usbip/vhci_tx.c pdu_header.base.seqnum = unlink->seqnum; base 209 drivers/usb/usbip/vhci_tx.c pdu_header.base.devid = vdev->devid; base 210 drivers/usb/usbip/vhci_tx.c pdu_header.base.ep = 0; base 47 drivers/usb/usbip/vudc_rx.c urb->pipe |= pdu->base.direction == USBIP_DIR_IN ? base 73 drivers/usb/usbip/vudc_rx.c urb_p->seqnum = pdu->base.seqnum; base 80 drivers/usb/usbip/vudc_rx.c v_enqueue_ret_unlink(udc, pdu->base.seqnum, 0); base 103 drivers/usb/usbip/vudc_rx.c address = pdu->base.ep; base 104 drivers/usb/usbip/vudc_rx.c if (pdu->base.direction == USBIP_DIR_IN) base 121 drivers/usb/usbip/vudc_rx.c urb_p->seqnum = pdu->base.seqnum; base 211 drivers/usb/usbip/vudc_rx.c switch (pdu.base.command) { base 15 drivers/usb/usbip/vudc_tx.c static inline void setup_base_pdu(struct usbip_header_basic *base, base 18 drivers/usb/usbip/vudc_tx.c base->command = command; base 19 drivers/usb/usbip/vudc_tx.c base->seqnum = seqnum; base 20 drivers/usb/usbip/vudc_tx.c base->devid = 0; base 21 drivers/usb/usbip/vudc_tx.c base->ep = 0; base 22 drivers/usb/usbip/vudc_tx.c base->direction = 0; base 27 drivers/usb/usbip/vudc_tx.c setup_base_pdu(&rpdu->base, USBIP_RET_SUBMIT, urb_p->seqnum); base 34 drivers/usb/usbip/vudc_tx.c setup_base_pdu(&rpdu->base, USBIP_RET_UNLINK, unlink->seqnum); base 111 drivers/usb/usbip/vudc_tx.c pdu_header.base.seqnum); base 1041 drivers/vfio/pci/vfio_pci_config.c int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE : base 1049 drivers/vfio/pci/vfio_pci_config.c while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap) base 28 drivers/vfio/pci/vfio_pci_igd.c void *base = vdev->region[i].data; base 36 drivers/vfio/pci/vfio_pci_igd.c if (copy_to_user(buf, base + pos, count)) base 59 drivers/vfio/pci/vfio_pci_igd.c void *base; base 69 drivers/vfio/pci/vfio_pci_igd.c base = memremap(addr, OPREGION_SIZE, MEMREMAP_WB); base 70 drivers/vfio/pci/vfio_pci_igd.c if (!base) base 73 drivers/vfio/pci/vfio_pci_igd.c if (memcmp(base, OPREGION_SIGNATURE, 16)) { base 74 drivers/vfio/pci/vfio_pci_igd.c memunmap(base); base 78 drivers/vfio/pci/vfio_pci_igd.c size = le32_to_cpu(*(__le32 *)(base + 16)); base 80 drivers/vfio/pci/vfio_pci_igd.c memunmap(base); base 87 drivers/vfio/pci/vfio_pci_igd.c memunmap(base); base 88 drivers/vfio/pci/vfio_pci_igd.c base = memremap(addr, size, MEMREMAP_WB); base 89 drivers/vfio/pci/vfio_pci_igd.c if (!base) base 96 drivers/vfio/pci/vfio_pci_igd.c &vfio_pci_igd_regops, size, VFIO_REGION_INFO_FLAG_READ, base); base 98 drivers/vfio/pci/vfio_pci_igd.c memunmap(base); base 301 drivers/vfio/pci/vfio_pci_nvlink2.c void *base; /* ATSD register virtual address, for emulated access */ base 320 drivers/vfio/pci/vfio_pci_nvlink2.c if (copy_from_user(data->base + pos, buf, count)) base 323 drivers/vfio/pci/vfio_pci_nvlink2.c if (copy_to_user(buf, data->base + pos, count)) base 357 drivers/vfio/pci/vfio_pci_nvlink2.c memunmap(data->base); base 447 drivers/vfio/pci/vfio_pci_nvlink2.c data->base = memremap(data->mmio_atsd, SZ_64K, MEMREMAP_WT); base 448 drivers/vfio/pci/vfio_pci_nvlink2.c if (!data->base) { base 476 drivers/vfio/pci/vfio_pci_nvlink2.c if (data->base) base 477 drivers/vfio/pci/vfio_pci_nvlink2.c memunmap(data->base); base 1309 drivers/vfio/vfio_iommu_type1.c phys_addr_t *base) base 1326 drivers/vfio/vfio_iommu_type1.c *base = region->start; base 1782 drivers/vhost/vhost.c void __user *base = (void __user *)(unsigned long)p; base 1786 drivers/vhost/vhost.c if (vq->private_data && !vq_log_access_ok(vq, base)) base 1789 drivers/vhost/vhost.c vq->log_base = base; base 1828 drivers/vhost/vhost.c void *base; base 1836 drivers/vhost/vhost.c base = kmap_atomic(page); base 1837 drivers/vhost/vhost.c set_bit(bit, base); base 1838 drivers/vhost/vhost.c kunmap_atomic(base); base 1854 drivers/vhost/vhost.c u64 base = (u64)(unsigned long)log_base; base 1855 drivers/vhost/vhost.c u64 log = base + write_page / 8; base 124 drivers/video/backlight/corgi_lcd.c static void lcdtg_i2c_send_start(struct corgi_lcd *lcd, uint8_t base) base 126 drivers/video/backlight/corgi_lcd.c lcdtg_ssp_i2c_send(lcd, base | POWER0_COM_DCLK | POWER0_COM_DOUT); base 127 drivers/video/backlight/corgi_lcd.c lcdtg_ssp_i2c_send(lcd, base | POWER0_COM_DCLK); base 128 drivers/video/backlight/corgi_lcd.c lcdtg_ssp_i2c_send(lcd, base); base 131 drivers/video/backlight/corgi_lcd.c static void lcdtg_i2c_send_stop(struct corgi_lcd *lcd, uint8_t base) base 133 drivers/video/backlight/corgi_lcd.c lcdtg_ssp_i2c_send(lcd, base); base 134 drivers/video/backlight/corgi_lcd.c lcdtg_ssp_i2c_send(lcd, base | POWER0_COM_DCLK); base 135 drivers/video/backlight/corgi_lcd.c lcdtg_ssp_i2c_send(lcd, base | POWER0_COM_DCLK | POWER0_COM_DOUT); base 139 drivers/video/backlight/corgi_lcd.c uint8_t base, uint8_t data) base 145 drivers/video/backlight/corgi_lcd.c lcdtg_i2c_send_bit(lcd, base | POWER0_COM_DOUT); base 147 drivers/video/backlight/corgi_lcd.c lcdtg_i2c_send_bit(lcd, base); base 152 drivers/video/backlight/corgi_lcd.c static void lcdtg_i2c_wait_ack(struct corgi_lcd *lcd, uint8_t base) base 154 drivers/video/backlight/corgi_lcd.c lcdtg_i2c_send_bit(lcd, base); base 258 drivers/video/console/sticore.c static void sti_rom_copy(unsigned long base, unsigned long count, void *dest) base 265 drivers/video/console/sticore.c *(u32 *)dest = gsc_readl(base); base 266 drivers/video/console/sticore.c base += 4; base 271 drivers/video/console/sticore.c *(u8 *)dest = gsc_readb(base); base 272 drivers/video/console/sticore.c base++; base 665 drivers/video/console/sticore.c static void sti_bmode_rom_copy(unsigned long base, unsigned long count, base 672 drivers/video/console/sticore.c *(u8 *)dest = gsc_readl(base); base 673 drivers/video/console/sticore.c base += 4; base 1034 drivers/video/fbdev/acornfb.c void *base; base 1041 drivers/video/fbdev/acornfb.c base = dma_alloc_wc(current_par.dev, size, &handle, base 1043 drivers/video/fbdev/acornfb.c if (base == NULL) { base 1048 drivers/video/fbdev/acornfb.c fb_info.screen_base = base; base 1459 drivers/video/fbdev/aty/atyfb_base.c int i; u32 base; base 1462 drivers/video/fbdev/aty/atyfb_base.c base = 0x2000; base 1467 drivers/video/fbdev/aty/atyfb_base.c printk("debug atyfb: 0x%04X: ", base + i); base 1475 drivers/video/fbdev/aty/atyfb_base.c base = 0x00; base 1480 drivers/video/fbdev/aty/atyfb_base.c printk("debug atyfb: 0x%02X: ", base + i); base 1492 drivers/video/fbdev/aty/atyfb_base.c base = 0x00; base 1506 drivers/video/fbdev/aty/atyfb_base.c base + i); base 2946 drivers/video/fbdev/aty/atyfb_base.c unsigned long base; base 2949 drivers/video/fbdev/aty/atyfb_base.c base = rp->start; base 2953 drivers/video/fbdev/aty/atyfb_base.c size = rp->end - base + 1; base 2966 drivers/video/fbdev/aty/atyfb_base.c if (base == addr) { base 2968 drivers/video/fbdev/aty/atyfb_base.c par->mmap_map[j].poff = base & PAGE_MASK; base 2979 drivers/video/fbdev/aty/atyfb_base.c if (base == addr) { base 2981 drivers/video/fbdev/aty/atyfb_base.c par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK; base 2990 drivers/video/fbdev/aty/atyfb_base.c par->mmap_map[j].poff = base & PAGE_MASK; base 2264 drivers/video/fbdev/aty/radeon_base.c ap->ranges[0].base = pci_resource_start(pdev, 0); base 1317 drivers/video/fbdev/cirrusfb.c unsigned long base; base 1328 drivers/video/fbdev/cirrusfb.c base = var->yoffset * info->fix.line_length + xoffset; base 1334 drivers/video/fbdev/cirrusfb.c base /= 4; base 1342 drivers/video/fbdev/cirrusfb.c vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff); base 1343 drivers/video/fbdev/cirrusfb.c vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff); base 1348 drivers/video/fbdev/cirrusfb.c if (base & 0x10000) base 1350 drivers/video/fbdev/cirrusfb.c if (base & 0x20000) base 1352 drivers/video/fbdev/cirrusfb.c if (base & 0x40000) base 1361 drivers/video/fbdev/cirrusfb.c tmp = (tmp & ~0x18) | ((base >> 16) & 0x18); base 1363 drivers/video/fbdev/cirrusfb.c tmp = (tmp & ~0x80) | ((base >> 12) & 0x80); base 35 drivers/video/fbdev/clps711x-fb.c void __iomem *base; base 62 drivers/video/fbdev/clps711x-fb.c writel((readl(cfb->base + regno) & ~mask) | level, cfb->base + regno); base 143 drivers/video/fbdev/clps711x-fb.c writel(lcdcon, cfb->base + CLPS711X_LCDCON); base 232 drivers/video/fbdev/clps711x-fb.c cfb->base = devm_ioremap(dev, res->start, resource_size(res)); base 233 drivers/video/fbdev/clps711x-fb.c if (!cfb->base) { base 262 drivers/video/fbdev/clps711x-fb.c info->apertures->ranges[0].base = info->fix.smem_start; base 301 drivers/video/fbdev/clps711x-fb.c if (info->fix.smem_start != (readb(cfb->base + CLPS711X_FBADDR) << 28)) base 311 drivers/video/fbdev/clps711x-fb.c writeb(info->fix.smem_start >> 28, cfb->base + CLPS711X_FBADDR); base 386 drivers/video/fbdev/core/cfbcopyarea.c unsigned long __iomem *base = NULL; base 404 drivers/video/fbdev/core/cfbcopyarea.c base = (unsigned long __iomem *)((unsigned long)p->screen_base & ~(bytes-1)); base 417 drivers/video/fbdev/core/cfbcopyarea.c bitcpy_rev(p, base + (dst_idx / bits), dst_idx % bits, base 418 drivers/video/fbdev/core/cfbcopyarea.c base + (src_idx / bits), src_idx % bits, bits, base 423 drivers/video/fbdev/core/cfbcopyarea.c bitcpy(p, base + (dst_idx / bits), dst_idx % bits, base 424 drivers/video/fbdev/core/cfbcopyarea.c base + (src_idx / bits), src_idx % bits, bits, base 1512 drivers/video/fbdev/core/fbmem.c if (gen->base == hw->base) base 1515 drivers/video/fbdev/core/fbmem.c if (gen->base > hw->base && gen->base < hw->base + hw->size) base 1532 drivers/video/fbdev/core/fbmem.c (unsigned long long)g->base, base 1534 drivers/video/fbdev/core/fbmem.c (unsigned long long)h->base, base 1562 drivers/video/fbdev/core/fbmem.c gen_aper->ranges[0].base == VGA_FB_PHYS)) { base 1742 drivers/video/fbdev/core/fbmem.c a->ranges[0].base = 0; base 1790 drivers/video/fbdev/core/fbmem.c ap->ranges[idx].base = pci_resource_start(pdev, bar); base 320 drivers/video/fbdev/core/syscopyarea.c unsigned long *base = NULL; base 337 drivers/video/fbdev/core/syscopyarea.c base = (unsigned long *)((unsigned long)p->screen_base & ~(bytes-1)); base 350 drivers/video/fbdev/core/syscopyarea.c bitcpy_rev(p, base + (dst_idx / bits), dst_idx % bits, base 351 drivers/video/fbdev/core/syscopyarea.c base + (src_idx / bits), src_idx % bits, bits, base 356 drivers/video/fbdev/core/syscopyarea.c bitcpy(p, base + (dst_idx / bits), dst_idx % bits, base 357 drivers/video/fbdev/core/syscopyarea.c base + (src_idx / bits), src_idx % bits, bits, base 539 drivers/video/fbdev/cyber2000fb.c u_int base = var->yoffset * var->xres_virtual + var->xoffset; base 541 drivers/video/fbdev/cyber2000fb.c base *= var->bits_per_pixel; base 547 drivers/video/fbdev/cyber2000fb.c base >>= 5; base 549 drivers/video/fbdev/cyber2000fb.c if (base >= 1 << 20) base 552 drivers/video/fbdev/cyber2000fb.c cyber2000_grphw(0x10, base >> 16 | 0x10, cfb); base 553 drivers/video/fbdev/cyber2000fb.c cyber2000_crtcw(0x0c, base >> 8, cfb); base 554 drivers/video/fbdev/cyber2000fb.c cyber2000_crtcw(0x0d, base, cfb); base 253 drivers/video/fbdev/efifb.c release_mem_region(info->apertures->ranges[0].base, base 318 drivers/video/fbdev/efifb.c efifb_attr_decl(base, "0x%x"); base 453 drivers/video/fbdev/efifb.c info->apertures->ranges[0].base = efifb_fix.smem_start; base 643 drivers/video/fbdev/efifb.c u64 base = screen_info.lfb_base; base 651 drivers/video/fbdev/efifb.c base |= (u64)screen_info.ext_lfb_base << 32; base 653 drivers/video/fbdev/efifb.c if (!base) base 662 drivers/video/fbdev/efifb.c if (res->start <= base && res->end >= base + size - 1) { base 663 drivers/video/fbdev/efifb.c record_efifb_bar_resource(dev, i, base - res->start); base 256 drivers/video/fbdev/hgafb.c unsigned int base; base 259 drivers/video/fbdev/hgafb.c base = (yoffset / 8) * 90 + xoffset; base 261 drivers/video/fbdev/hgafb.c write_hga_w(base, 0x0c); /* start address */ base 263 drivers/video/fbdev/hgafb.c DPRINTK("hga_pan: base:%d\n", base); base 715 drivers/video/fbdev/hyperv_fb.c info->apertures->ranges[0].base = screen_info.lfb_base; base 720 drivers/video/fbdev/hyperv_fb.c info->apertures->ranges[0].base = pci_resource_start(pdev, 0); base 403 drivers/video/fbdev/i740fb.c u32 bpp, base, dacspeed24, mem; base 582 drivers/video/fbdev/i740fb.c base = (yoffset * vxres + (xoffset & ~7)) >> 2; base 597 drivers/video/fbdev/i740fb.c base *= 2; base 604 drivers/video/fbdev/i740fb.c base &= 0xFFFFFFFE; /* ...ignore the last bit. */ base 605 drivers/video/fbdev/i740fb.c base *= 3; base 612 drivers/video/fbdev/i740fb.c base *= 4; base 616 drivers/video/fbdev/i740fb.c par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF; base 617 drivers/video/fbdev/i740fb.c par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8; base 619 drivers/video/fbdev/i740fb.c ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE; base 620 drivers/video/fbdev/i740fb.c par->ext_start_addr_hi = (base & 0x3FC00000) >> 22; base 900 drivers/video/fbdev/i740fb.c u32 base = (var->yoffset * info->var.xres_virtual base 904 drivers/video/fbdev/i740fb.c var->xoffset, var->yoffset, base); base 911 drivers/video/fbdev/i740fb.c base *= 2; base 918 drivers/video/fbdev/i740fb.c base &= 0xFFFFFFFE; /* ...ignore the last bit. */ base 919 drivers/video/fbdev/i740fb.c base *= 3; base 922 drivers/video/fbdev/i740fb.c base *= 4; base 926 drivers/video/fbdev/i740fb.c par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF; base 927 drivers/video/fbdev/i740fb.c par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8; base 928 drivers/video/fbdev/i740fb.c par->ext_start_addr_hi = (base & 0x3FC00000) >> 22; base 930 drivers/video/fbdev/i740fb.c ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE; base 932 drivers/video/fbdev/i740fb.c i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO, base & 0x000000FF); base 934 drivers/video/fbdev/i740fb.c (base & 0x0000FF00) >> 8); base 936 drivers/video/fbdev/i740fb.c (base & 0x3FC00000) >> 22); base 938 drivers/video/fbdev/i740fb.c ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE); base 404 drivers/video/fbdev/imsttfb.c static inline u32 read_reg_le32(volatile u32 __iomem *base, int regindex) base 407 drivers/video/fbdev/imsttfb.c return in_le32(base + regindex); base 409 drivers/video/fbdev/imsttfb.c return readl(base + regindex); base 413 drivers/video/fbdev/imsttfb.c static inline void write_reg_le32(volatile u32 __iomem *base, int regindex, u32 val) base 416 drivers/video/fbdev/imsttfb.c out_le32(base + regindex, val); base 418 drivers/video/fbdev/imsttfb.c writel(val, base + regindex); base 658 drivers/video/fbdev/macfb.c unsigned long base = ndev->board->slot_addr; base 660 drivers/video/fbdev/macfb.c if (mac_bi_data.videoaddr < base || base 661 drivers/video/fbdev/macfb.c mac_bi_data.videoaddr - base > 0xFFFFFF) base 669 drivers/video/fbdev/macfb.c slot_addr = (unsigned char *)base; base 377 drivers/video/fbdev/matrox/matroxfb_base.c release_mem_region(minfo->video.base, minfo->video.len_maximum); base 378 drivers/video/fbdev/matrox/matroxfb_base.c release_mem_region(minfo->mmio.base, 16384); base 715 drivers/video/fbdev/matrox/matroxfb_base.c fix->mmio_start = minfo->mmio.base; base 726 drivers/video/fbdev/matrox/matroxfb_base.c fix->smem_start = minfo->video.base + minfo->curr.ydstorg.bytes; base 1419 drivers/video/fbdev/matrox/matroxfb_base.c struct video_board* base; base 1637 drivers/video/fbdev/matrox/matroxfb_base.c minfo->hw_switch = b->base->lowlevel; base 1638 drivers/video/fbdev/matrox/matroxfb_base.c minfo->devflags.accelerator = b->base->accelID; base 1697 drivers/video/fbdev/matrox/matroxfb_base.c memsize = b->base->maxvram; base 1718 drivers/video/fbdev/matrox/matroxfb_base.c minfo->mmio.base = ctrlptr_phys; base 1720 drivers/video/fbdev/matrox/matroxfb_base.c minfo->video.base = video_base_phys; base 1766 drivers/video/fbdev/matrox/matroxfb_base.c minfo->video.base = video_base_phys; base 1768 drivers/video/fbdev/matrox/matroxfb_base.c if (minfo->video.len_usable > b->base->maxdisplayable) base 1769 drivers/video/fbdev/matrox/matroxfb_base.c minfo->video.len_usable = b->base->maxdisplayable; base 1916 drivers/video/fbdev/matrox/matroxfb_base.c minfo->video.base, vaddr_va(minfo->video.vbase), minfo->video.len); base 392 drivers/video/fbdev/matrox/matroxfb_base.h unsigned long base; /* physical */ base 400 drivers/video/fbdev/matrox/matroxfb_base.h unsigned long base; /* physical */ base 304 drivers/video/fbdev/matrox/matroxfb_crtc2.c fix->smem_start = m2info->video.base; base 309 drivers/video/fbdev/matrox/matroxfb_crtc2.c fix->mmio_start = m2info->mmio.base; base 626 drivers/video/fbdev/matrox/matroxfb_crtc2.c m2info->video.base = minfo->video.base + m2info->video.offbase; base 629 drivers/video/fbdev/matrox/matroxfb_crtc2.c m2info->mmio.base = minfo->mmio.base; base 16 drivers/video/fbdev/matrox/matroxfb_crtc2.h unsigned long base; /* physical */ base 25 drivers/video/fbdev/matrox/matroxfb_crtc2.h unsigned long base; base 1138 drivers/video/fbdev/mx3fb.c unsigned long base; base 1170 drivers/video/fbdev/mx3fb.c base = fbi->fix.smem_start + offset; base 1173 drivers/video/fbdev/mx3fb.c mx3_fbi->cur_ipu_buf, base); base 1194 drivers/video/fbdev/mx3fb.c sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base; base 1223 drivers/video/fbdev/mx3fb.c mx3_fbi->cur_ipu_buf, base); base 284 drivers/video/fbdev/offb.c release_mem_region(info->apertures->ranges[0].base, info->apertures->ranges[0].size); base 345 drivers/video/fbdev/offb.c unsigned long base = address & 0xff000000UL; base 347 drivers/video/fbdev/offb.c ioremap(base + 0x7ff000, 0x1000) + 0xcc0; base 511 drivers/video/fbdev/offb.c info->apertures->ranges[0].base = address; base 46 drivers/video/fbdev/omap/sossi.c void __iomem *base; base 72 drivers/video/fbdev/omap/sossi.c return readl(sossi.base + reg); base 77 drivers/video/fbdev/omap/sossi.c return readw(sossi.base + reg); base 82 drivers/video/fbdev/omap/sossi.c return readb(sossi.base + reg); base 87 drivers/video/fbdev/omap/sossi.c writel(value, sossi.base + reg); base 92 drivers/video/fbdev/omap/sossi.c writew(value, sossi.base + reg); base 97 drivers/video/fbdev/omap/sossi.c writeb(value, sossi.base + reg); base 565 drivers/video/fbdev/omap/sossi.c sossi.base = ioremap(OMAP_SOSSI_BASE, SZ_1K); base 566 drivers/video/fbdev/omap/sossi.c if (!sossi.base) { base 661 drivers/video/fbdev/omap/sossi.c iounmap(sossi.base); base 102 drivers/video/fbdev/omap2/omapfb/dss/dispc.c void __iomem *base; base 253 drivers/video/fbdev/omap2/omapfb/dss/dispc.c __raw_writel(val, dispc.base + idx); base 258 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return __raw_readl(dispc.base + idx); base 4063 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, base 4065 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (!dispc.base) { base 435 drivers/video/fbdev/omap2/omapfb/dss/dsi.c void __iomem *base; base 438 drivers/video/fbdev/omap2/omapfb/dss/dsi.c case DSI_PROTO: base = dsi->proto_base; break; base 439 drivers/video/fbdev/omap2/omapfb/dss/dsi.c case DSI_PHY: base = dsi->phy_base; break; base 440 drivers/video/fbdev/omap2/omapfb/dss/dsi.c case DSI_PLL: base = dsi->pll_base; break; base 444 drivers/video/fbdev/omap2/omapfb/dss/dsi.c __raw_writel(val, base + idx.idx); base 451 drivers/video/fbdev/omap2/omapfb/dss/dsi.c void __iomem *base; base 454 drivers/video/fbdev/omap2/omapfb/dss/dsi.c case DSI_PROTO: base = dsi->proto_base; break; base 455 drivers/video/fbdev/omap2/omapfb/dss/dsi.c case DSI_PHY: base = dsi->phy_base; break; base 456 drivers/video/fbdev/omap2/omapfb/dss/dsi.c case DSI_PLL: base = dsi->pll_base; break; base 460 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return __raw_readl(base + idx.idx); base 5223 drivers/video/fbdev/omap2/omapfb/dss/dsi.c pll->base = dsi->pll_base; base 72 drivers/video/fbdev/omap2/omapfb/dss/dss.c void __iomem *base; base 115 drivers/video/fbdev/omap2/omapfb/dss/dss.c __raw_writel(val, dss.base + idx.idx); base 120 drivers/video/fbdev/omap2/omapfb/dss/dss.c return __raw_readl(dss.base + idx.idx); base 1086 drivers/video/fbdev/omap2/omapfb/dss/dss.c dss.base = devm_ioremap(&pdev->dev, dss_mem->start, base 1088 drivers/video/fbdev/omap2/omapfb/dss/dss.c if (!dss.base) { base 166 drivers/video/fbdev/omap2/omapfb/dss/dss.h void __iomem *base; base 224 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void __iomem *base; base 231 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void __iomem *base; base 237 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void __iomem *base; base 244 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void __iomem *base; base 258 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h #define REG_FLD_MOD(base, idx, val, start, end) \ base 259 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ base 261 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h #define REG_GET(base, idx, start, end) \ base 262 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h FLD_GET(hdmi_read_reg(base, idx), start, end) base 33 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c return core->base + HDMI_CORE_AV; base 38 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c void __iomem *base = core->base; base 41 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); base 44 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { base 46 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); base 48 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, base 56 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); base 59 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, base 66 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); base 69 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, base 81 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c void __iomem *base = core->base; base 87 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, base 97 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); base 100 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); base 103 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); base 106 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); base 107 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); base 111 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); base 113 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); base 116 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { base 121 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { base 130 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { base 137 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { base 145 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); base 203 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0); base 209 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); base 215 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); base 223 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c void __iomem *core_sys_base = core->base; base 358 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c hdmi_read_reg(core->base, r)) base 886 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c core->base = devm_ioremap_resource(&pdev->dev, res); base 887 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (IS_ERR(core->base)) { base 889 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c return PTR_ERR(core->base); base 88 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL); base 91 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); base 98 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); base 317 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); base 319 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); base 323 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); base 333 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); base 342 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); base 701 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); base 41 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 56 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); base 57 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, base 62 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); base 66 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, base 68 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, base 73 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, base 75 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, base 80 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, base 82 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, base 87 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, base 89 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, base 94 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0); base 96 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0); base 97 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0); base 100 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7); base 103 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6); base 106 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3); base 109 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2); base 112 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3); base 115 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2); base 120 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 123 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); base 124 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); base 125 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); base 130 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 137 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0); base 147 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); base 149 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS, base 153 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1); base 155 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0); base 160 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0); base 180 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0); base 223 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_read_reg(core->base, r)) base 309 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 319 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); base 325 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r); base 328 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, base 330 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, base 334 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, base 336 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, base 340 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0); base 341 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0); base 344 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0); base 347 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, base 349 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, base 353 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, base 357 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, base 359 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, base 363 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, base 367 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, base 373 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 377 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4); base 379 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6); base 381 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5); base 383 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3); base 385 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1); base 387 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2); base 389 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0); base 397 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4); base 405 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0); base 411 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 447 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0, base 450 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1, base 453 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2, base 456 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic); base 458 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3, base 461 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0); base 467 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 469 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0); base 470 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0); base 471 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0); base 472 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0); base 473 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0); base 474 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0); base 475 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0); base 476 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0); base 477 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0); base 478 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0); base 479 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0); base 480 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0); base 481 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0); base 482 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0); base 483 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0); base 484 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0); base 485 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0); base 486 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0); base 487 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0); base 488 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0); base 489 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0); base 490 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0); base 491 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0); base 492 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0); base 494 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0); base 509 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 513 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0); base 514 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0); base 515 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0); base 516 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0); base 517 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0); base 518 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0); base 519 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0); base 520 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1); base 525 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 528 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0); base 532 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0); base 533 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0); base 534 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0); base 535 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0); base 537 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2); base 538 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0); base 540 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0); base 542 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); base 543 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); base 544 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); base 546 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0); base 548 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); base 552 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); base 553 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0); base 554 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0); base 555 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0); base 557 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0); base 559 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0); base 561 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); base 563 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); base 569 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0); base 574 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 576 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0); base 577 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0); base 578 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0); base 579 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0); base 580 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); base 581 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0); base 582 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0); base 583 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); base 584 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0); base 637 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 641 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4); base 644 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0); base 645 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0); base 646 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0); base 652 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4); base 653 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0); base 654 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0); base 655 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0); base 659 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0); base 661 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0); base 665 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0); base 666 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4); base 674 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1); base 675 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5); base 676 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2); base 677 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6); base 681 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3); base 682 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7); base 686 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0); base 691 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4); base 696 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0); base 699 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1), base 704 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4); base 708 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0); base 711 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0); base 713 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4); base 715 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0); base 717 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4); base 719 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0); base 721 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4); base 723 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0); base 725 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4); base 728 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7), base 732 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8), base 736 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2); base 742 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); base 744 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0); base 747 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); base 749 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0); base 752 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); base 754 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0); base 758 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0); base 760 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1); base 762 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0); base 764 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0); base 767 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4); base 773 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c void __iomem *base = core->base; base 776 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0, base 780 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss); base 781 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca); base 782 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, base 898 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c core->base = devm_ioremap_resource(&pdev->dev, res); base 899 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c if (IS_ERR(core->base)) { base 901 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c return PTR_ERR(core->base); base 31 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c hdmi_read_reg(phy->base, r)) base 128 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); base 129 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); base 141 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL); base 148 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); base 165 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); base 168 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); base 172 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); base 222 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c phy->base = devm_ioremap_resource(&pdev->dev, res); base 223 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c if (IS_ERR(phy->base)) { base 225 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c return PTR_ERR(phy->base); base 26 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c hdmi_read_reg(pll->base, r)) base 191 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->base = hpll->base; base 233 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->base = devm_ioremap_resource(&pdev->dev, res); base 234 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c if (IS_ERR(pll->base)) { base 236 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c return PTR_ERR(pll->base); base 23 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) base 47 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); base 52 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); base 54 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); base 59 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); base 64 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); base 71 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) base 75 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); base 78 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) base 91 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); base 94 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) base 105 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); base 114 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE); base 116 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); base 123 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW); base 136 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, base 141 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l); base 154 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); base 159 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r); base 173 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); base 178 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v); base 210 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG); base 223 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r); base 233 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2); base 236 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r); base 238 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL); base 241 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r); base 246 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); base 253 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); base 269 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c wp->base = devm_ioremap_resource(&pdev->dev, res); base 270 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (IS_ERR(wp->base)) { base 272 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c return PTR_ERR(wp->base); base 216 drivers/video/fbdev/omap2/omapfb/dss/pll.c void __iomem *base = pll->base; base 218 drivers/video/fbdev/omap2/omapfb/dss/pll.c if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1) base 229 drivers/video/fbdev/omap2/omapfb/dss/pll.c u32 v = readl_relaxed(pll->base + PLL_STATUS); base 242 drivers/video/fbdev/omap2/omapfb/dss/pll.c void __iomem *base = pll->base; base 257 drivers/video/fbdev/omap2/omapfb/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION1); base 266 drivers/video/fbdev/omap2/omapfb/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION3); base 268 drivers/video/fbdev/omap2/omapfb/dss/pll.c l = readl_relaxed(base + PLL_CONFIGURATION2); base 291 drivers/video/fbdev/omap2/omapfb/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION2); base 293 drivers/video/fbdev/omap2/omapfb/dss/pll.c writel_relaxed(1, base + PLL_GO); /* PLL_GO */ base 295 drivers/video/fbdev/omap2/omapfb/dss/pll.c if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) { base 301 drivers/video/fbdev/omap2/omapfb/dss/pll.c if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { base 307 drivers/video/fbdev/omap2/omapfb/dss/pll.c l = readl_relaxed(base + PLL_CONFIGURATION2); base 314 drivers/video/fbdev/omap2/omapfb/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION2); base 334 drivers/video/fbdev/omap2/omapfb/dss/pll.c void __iomem *base = pll->base; base 340 drivers/video/fbdev/omap2/omapfb/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION1); base 342 drivers/video/fbdev/omap2/omapfb/dss/pll.c l = readl_relaxed(base + PLL_CONFIGURATION2); base 354 drivers/video/fbdev/omap2/omapfb/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION2); base 356 drivers/video/fbdev/omap2/omapfb/dss/pll.c l = readl_relaxed(base + PLL_CONFIGURATION3); base 358 drivers/video/fbdev/omap2/omapfb/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION3); base 360 drivers/video/fbdev/omap2/omapfb/dss/pll.c l = readl_relaxed(base + PLL_CONFIGURATION4); base 363 drivers/video/fbdev/omap2/omapfb/dss/pll.c writel_relaxed(l, base + PLL_CONFIGURATION4); base 365 drivers/video/fbdev/omap2/omapfb/dss/pll.c writel_relaxed(1, base + PLL_GO); /* PLL_GO */ base 367 drivers/video/fbdev/omap2/omapfb/dss/pll.c if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) { base 372 drivers/video/fbdev/omap2/omapfb/dss/pll.c if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) { base 287 drivers/video/fbdev/omap2/omapfb/dss/venc.c void __iomem *base; base 303 drivers/video/fbdev/omap2/omapfb/dss/venc.c __raw_writel(val, venc.base + idx); base 308 drivers/video/fbdev/omap2/omapfb/dss/venc.c u32 l = __raw_readl(venc.base + idx); base 864 drivers/video/fbdev/omap2/omapfb/dss/venc.c venc.base = devm_ioremap(&pdev->dev, venc_mem->start, base 866 drivers/video/fbdev/omap2/omapfb/dss/venc.c if (!venc.base) { base 191 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c pll->base = pll_base; base 49 drivers/video/fbdev/omap2/omapfb/vrfb.c u32 base; base 308 drivers/video/fbdev/omap2/omapfb/vrfb.c paddr = ctxs[ctx].base + SMS_ROT_VIRT_BASE(rot); base 365 drivers/video/fbdev/omap2/omapfb/vrfb.c ctxs[i].base = mem->start; base 692 drivers/video/fbdev/pm2fb.c u32 base; base 729 drivers/video/fbdev/pm2fb.c base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1); base 827 drivers/video/fbdev/pm2fb.c pm2_WR(par, PM2R_SCREEN_BASE, base); base 970 drivers/video/fbdev/pm2fb.c u32 base; base 975 drivers/video/fbdev/pm2fb.c base = to3264(var->yoffset * xres + var->xoffset, depth, 1); base 977 drivers/video/fbdev/pm2fb.c pm2_WR(p, PM2R_SCREEN_BASE, base); base 70 drivers/video/fbdev/pm3fb.c u32 base; /* screen base in 128 bits unit */ base 818 drivers/video/fbdev/pm3fb.c PM3_WRITE_REG(par, PM3ScreenBase, par->base); base 1019 drivers/video/fbdev/pm3fb.c par->base = pm3fb_shift_bpp(bpp, (info->var.yoffset * xres) base 1145 drivers/video/fbdev/pm3fb.c par->base = pm3fb_shift_bpp(info->var.bits_per_pixel, base 1149 drivers/video/fbdev/pm3fb.c PM3_WRITE_REG(par, PM3ScreenBase, par->base); base 120 drivers/video/fbdev/pxa3xx-gcu.c u32 base = gc_readl(priv, REG_GCRBBR); \ base 137 drivers/video/fbdev/pxa3xx-gcu.c (gc_readl(priv, REG_GCRBEXHR) - base) / 4, \ base 138 drivers/video/fbdev/pxa3xx-gcu.c (gc_readl(priv, REG_GCRBHR) - base) / 4, \ base 139 drivers/video/fbdev/pxa3xx-gcu.c (gc_readl(priv, REG_GCRBTR) - base) / 4); \ base 173 drivers/video/fbdev/pxa3xx-gcu.c u32 base = gc_readl(priv, REG_GCRBBR); base 183 drivers/video/fbdev/pxa3xx-gcu.c (gc_readl(priv, REG_GCRBEXHR) - base) / 4, base 184 drivers/video/fbdev/pxa3xx-gcu.c (gc_readl(priv, REG_GCRBHR) - base) / 4, base 185 drivers/video/fbdev/pxa3xx-gcu.c (gc_readl(priv, REG_GCRBTR) - base) / 4); base 1235 drivers/video/fbdev/riva/fbdev.c unsigned int base; base 1238 drivers/video/fbdev/riva/fbdev.c base = var->yoffset * info->fix.line_length + var->xoffset; base 1239 drivers/video/fbdev/riva/fbdev.c par->riva.SetStartAddress(&par->riva, base); base 704 drivers/video/fbdev/sa1100fb.c if (readl_relaxed(fbi->base + LCCR0) != fbi->reg_lccr0 || base 705 drivers/video/fbdev/sa1100fb.c readl_relaxed(fbi->base + LCCR1) != fbi->reg_lccr1 || base 706 drivers/video/fbdev/sa1100fb.c readl_relaxed(fbi->base + LCCR2) != fbi->reg_lccr2 || base 707 drivers/video/fbdev/sa1100fb.c readl_relaxed(fbi->base + LCCR3) != fbi->reg_lccr3 || base 708 drivers/video/fbdev/sa1100fb.c readl_relaxed(fbi->base + DBAR1) != fbi->dbar1 || base 709 drivers/video/fbdev/sa1100fb.c readl_relaxed(fbi->base + DBAR2) != fbi->dbar2) base 794 drivers/video/fbdev/sa1100fb.c writel_relaxed(fbi->reg_lccr3, fbi->base + LCCR3); base 795 drivers/video/fbdev/sa1100fb.c writel_relaxed(fbi->reg_lccr2, fbi->base + LCCR2); base 796 drivers/video/fbdev/sa1100fb.c writel_relaxed(fbi->reg_lccr1, fbi->base + LCCR1); base 797 drivers/video/fbdev/sa1100fb.c writel_relaxed(fbi->reg_lccr0 & ~LCCR0_LEN, fbi->base + LCCR0); base 798 drivers/video/fbdev/sa1100fb.c writel_relaxed(fbi->dbar1, fbi->base + DBAR1); base 799 drivers/video/fbdev/sa1100fb.c writel_relaxed(fbi->dbar2, fbi->base + DBAR2); base 800 drivers/video/fbdev/sa1100fb.c writel_relaxed(fbi->reg_lccr0 | LCCR0_LEN, fbi->base + LCCR0); base 805 drivers/video/fbdev/sa1100fb.c dev_dbg(fbi->dev, "DBAR1: 0x%08x\n", readl_relaxed(fbi->base + DBAR1)); base 806 drivers/video/fbdev/sa1100fb.c dev_dbg(fbi->dev, "DBAR2: 0x%08x\n", readl_relaxed(fbi->base + DBAR2)); base 807 drivers/video/fbdev/sa1100fb.c dev_dbg(fbi->dev, "LCCR0: 0x%08x\n", readl_relaxed(fbi->base + LCCR0)); base 808 drivers/video/fbdev/sa1100fb.c dev_dbg(fbi->dev, "LCCR1: 0x%08x\n", readl_relaxed(fbi->base + LCCR1)); base 809 drivers/video/fbdev/sa1100fb.c dev_dbg(fbi->dev, "LCCR2: 0x%08x\n", readl_relaxed(fbi->base + LCCR2)); base 810 drivers/video/fbdev/sa1100fb.c dev_dbg(fbi->dev, "LCCR3: 0x%08x\n", readl_relaxed(fbi->base + LCCR3)); base 827 drivers/video/fbdev/sa1100fb.c writel_relaxed(~0, fbi->base + LCSR); base 829 drivers/video/fbdev/sa1100fb.c lccr0 = readl_relaxed(fbi->base + LCCR0); base 831 drivers/video/fbdev/sa1100fb.c writel_relaxed(lccr0, fbi->base + LCCR0); base 833 drivers/video/fbdev/sa1100fb.c writel_relaxed(lccr0, fbi->base + LCCR0); base 848 drivers/video/fbdev/sa1100fb.c unsigned int lcsr = readl_relaxed(fbi->base + LCSR); base 851 drivers/video/fbdev/sa1100fb.c u32 lccr0 = readl_relaxed(fbi->base + LCCR0) | LCCR0_LDM; base 852 drivers/video/fbdev/sa1100fb.c writel_relaxed(lccr0, fbi->base + LCCR0); base 856 drivers/video/fbdev/sa1100fb.c writel_relaxed(lcsr, fbi->base + LCSR); base 1176 drivers/video/fbdev/sa1100fb.c fbi->base = devm_ioremap_resource(&pdev->dev, res); base 1177 drivers/video/fbdev/sa1100fb.c if (IS_ERR(fbi->base)) base 1178 drivers/video/fbdev/sa1100fb.c return PTR_ERR(fbi->base); base 35 drivers/video/fbdev/sa1100fb.h void __iomem *base; base 1475 drivers/video/fbdev/savage/savagefb_driver.c static void savagefb_update_start(struct savagefb_par *par, int base) base 1478 drivers/video/fbdev/savage/savagefb_driver.c vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par); base 1479 drivers/video/fbdev/savage/savagefb_driver.c vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par); base 1481 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, (base & 0x7f0000) >> 16, par); base 1542 drivers/video/fbdev/savage/savagefb_driver.c int base; base 1544 drivers/video/fbdev/savage/savagefb_driver.c base = (var->yoffset * info->fix.line_length base 1547 drivers/video/fbdev/savage/savagefb_driver.c savagefb_update_start(par, base); base 31 drivers/video/fbdev/sh7760fb.c void __iomem *base; base 60 drivers/video/fbdev/sh7760fb.c while (--i && ((ioread16(par->base + LDPMMR) & 3) != val)) base 74 drivers/video/fbdev/sh7760fb.c unsigned short cntr = ioread16(par->base + LDCNTR); base 75 drivers/video/fbdev/sh7760fb.c unsigned short intr = ioread16(par->base + LDINTR); base 91 drivers/video/fbdev/sh7760fb.c iowrite16(intr, par->base + LDINTR); base 92 drivers/video/fbdev/sh7760fb.c iowrite16(cntr, par->base + LDCNTR); base 249 drivers/video/fbdev/sh7760fb.c iowrite16(par->pd->ldickr, par->base + LDICKR); /* pixclock */ base 250 drivers/video/fbdev/sh7760fb.c iowrite16(ldmtr, par->base + LDMTR); /* polarities */ base 251 drivers/video/fbdev/sh7760fb.c iowrite16(lddfr, par->base + LDDFR); /* color/depth */ base 252 drivers/video/fbdev/sh7760fb.c iowrite16((par->rot ? 1 << 13 : 0), par->base + LDSMR); /* rotate */ base 253 drivers/video/fbdev/sh7760fb.c iowrite16(par->pd->ldpmmr, par->base + LDPMMR); /* Power Management */ base 254 drivers/video/fbdev/sh7760fb.c iowrite16(par->pd->ldpspr, par->base + LDPSPR); /* Power Supply Ctrl */ base 258 drivers/video/fbdev/sh7760fb.c par->base + LDHCNR); base 259 drivers/video/fbdev/sh7760fb.c iowrite16(vdln - 1, par->base + LDVDLNR); base 260 drivers/video/fbdev/sh7760fb.c iowrite16(vtln - 1, par->base + LDVTLNR); base 262 drivers/video/fbdev/sh7760fb.c iowrite16((vsynp - 1) | ((vsynw - 1) << 12), par->base + LDVSYNR); base 264 drivers/video/fbdev/sh7760fb.c par->base + LDHSYNR); base 266 drivers/video/fbdev/sh7760fb.c iowrite16(par->pd->ldaclnr, par->base + LDACLNR); base 292 drivers/video/fbdev/sh7760fb.c iowrite16(stride, par->base + LDLAOR); base 299 drivers/video/fbdev/sh7760fb.c iowrite32(sbase, par->base + LDSARU); base 321 drivers/video/fbdev/sh7760fb.c iowrite32(ldsarl, par->base + LDSARL); /* mem for lower half of DSTN */ base 466 drivers/video/fbdev/sh7760fb.c par->base = ioremap_nocache(res->start, resource_size(res)); base 467 drivers/video/fbdev/sh7760fb.c if (!par->base) { base 473 drivers/video/fbdev/sh7760fb.c iowrite16(0, par->base + LDINTR); /* disable vsync irq */ base 517 drivers/video/fbdev/sh7760fb.c iowrite16(LDCNTR_DON2, par->base + LDCNTR); base 549 drivers/video/fbdev/sh7760fb.c iounmap(par->base); base 568 drivers/video/fbdev/sh7760fb.c iounmap(par->base); base 181 drivers/video/fbdev/sh_mobile_lcdcfb.c unsigned long base; base 207 drivers/video/fbdev/sh_mobile_lcdcfb.c void __iomem *base; base 291 drivers/video/fbdev/sh_mobile_lcdcfb.c iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]); base 293 drivers/video/fbdev/sh_mobile_lcdcfb.c iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + base 300 drivers/video/fbdev/sh_mobile_lcdcfb.c iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + base 307 drivers/video/fbdev/sh_mobile_lcdcfb.c return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]); base 313 drivers/video/fbdev/sh_mobile_lcdcfb.c iowrite32(data, ovl->channel->lcdc->base + reg); base 314 drivers/video/fbdev/sh_mobile_lcdcfb.c iowrite32(data, ovl->channel->lcdc->base + reg + SIDE_B_OFFSET); base 320 drivers/video/fbdev/sh_mobile_lcdcfb.c iowrite32(data, priv->base + reg_offs); base 326 drivers/video/fbdev/sh_mobile_lcdcfb.c return ioread32(priv->base + reg_offs); base 2303 drivers/video/fbdev/sh_mobile_lcdcfb.c if (priv->base) base 2304 drivers/video/fbdev/sh_mobile_lcdcfb.c iounmap(priv->base); base 2591 drivers/video/fbdev/sh_mobile_lcdcfb.c priv->base = ioremap_nocache(res->start, resource_size(res)); base 2592 drivers/video/fbdev/sh_mobile_lcdcfb.c if (!priv->base) { base 456 drivers/video/fbdev/simplefb.c info->apertures->ranges[0].base = info->fix.smem_start; base 392 drivers/video/fbdev/sis/sis.h #define MMIO_IN8(base, offset) readb((base+offset)) base 393 drivers/video/fbdev/sis/sis.h #define MMIO_IN16(base, offset) readw((base+offset)) base 394 drivers/video/fbdev/sis/sis.h #define MMIO_IN32(base, offset) readl((base+offset)) base 396 drivers/video/fbdev/sis/sis.h #define MMIO_OUT8(base, offset, val) writeb(((u8)(val)), (base+offset)) base 397 drivers/video/fbdev/sis/sis.h #define MMIO_OUT16(base, offset, val) writew(((u16)(val)), (base+offset)) base 398 drivers/video/fbdev/sis/sis.h #define MMIO_OUT32(base, offset, val) writel(((u32)(val)), (base+offset)) base 678 drivers/video/fbdev/sis/sis.h void sis_free(u32 base); base 679 drivers/video/fbdev/sis/sis.h void sis_free_new(struct pci_dev *pdev, u32 base); base 150 drivers/video/fbdev/sis/sis_accel.h #define SiS300SetupSRCBase(base) \ base 152 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(0), base);\ base 165 drivers/video/fbdev/sis/sis_accel.h #define SiS300SetupDSTBase(base) \ base 167 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(4), base);\ base 280 drivers/video/fbdev/sis/sis_accel.h #define SiS310SetupSRCBase(base) \ base 282 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, SRC_ADDR, base);\ base 295 drivers/video/fbdev/sis/sis_accel.h #define SiS310SetupDSTBase(base) \ base 297 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, DST_ADDR, base);\ base 101 drivers/video/fbdev/sis/sis_main.c static struct SIS_OH * sisfb_poh_free(struct SIS_HEAP *memheap, u32 base); base 1338 drivers/video/fbdev/sis/sis_main.c sisfb_set_base_CRT1(struct sis_video_info *ivideo, unsigned int base) base 1342 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISCR, 0x0D, base & 0xFF); base 1343 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISCR, 0x0C, (base >> 8) & 0xFF); base 1344 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x0D, (base >> 16) & 0xFF); base 1346 drivers/video/fbdev/sis/sis_main.c SiS_SetRegANDOR(SISSR, 0x37, 0xFE, (base >> 24) & 0x01); base 1351 drivers/video/fbdev/sis/sis_main.c sisfb_set_base_CRT2(struct sis_video_info *ivideo, unsigned int base) base 1355 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISPART1, 0x06, (base & 0xFF)); base 1356 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISPART1, 0x05, ((base >> 8) & 0xFF)); base 1357 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISPART1, 0x04, ((base >> 16) & 0xFF)); base 1359 drivers/video/fbdev/sis/sis_main.c SiS_SetRegANDOR(SISPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7); base 3332 drivers/video/fbdev/sis/sis_main.c sisfb_poh_free(struct SIS_HEAP *memheap, u32 base) base 3345 drivers/video/fbdev/sis/sis_main.c if(poh_freed->offset == base) { base 3452 drivers/video/fbdev/sis/sis_main.c sis_int_free(struct sis_video_info *ivideo, u32 base) base 3459 drivers/video/fbdev/sis/sis_main.c poh = sisfb_poh_free(&ivideo->sisfb_heap, base); base 3463 drivers/video/fbdev/sis/sis_main.c (unsigned int) base); base 3468 drivers/video/fbdev/sis/sis_main.c sis_free(u32 base) base 3472 drivers/video/fbdev/sis/sis_main.c sis_int_free(ivideo, base); base 3476 drivers/video/fbdev/sis/sis_main.c sis_free_new(struct pci_dev *pdev, u32 base) base 3480 drivers/video/fbdev/sis/sis_main.c sis_int_free(ivideo, base); base 528 drivers/video/fbdev/sm501fb.c void __iomem *base = fbi->regs; base 532 drivers/video/fbdev/sm501fb.c base += SM501_DC_CRT_H_TOT; base 534 drivers/video/fbdev/sm501fb.c base += SM501_DC_PANEL_H_TOT; base 549 drivers/video/fbdev/sm501fb.c smc501_writel(reg, base + SM501_OFF_DC_H_TOT); base 556 drivers/video/fbdev/sm501fb.c smc501_writel(reg, base + SM501_OFF_DC_H_SYNC); base 563 drivers/video/fbdev/sm501fb.c smc501_writel(reg, base + SM501_OFF_DC_V_TOT); base 569 drivers/video/fbdev/sm501fb.c smc501_writel(reg, base + SM501_OFF_DC_V_SYNC); base 917 drivers/video/fbdev/sm501fb.c void __iomem *base = fbi->regs; base 921 drivers/video/fbdev/sm501fb.c base += SM501_DC_CRT_PALETTE; base 923 drivers/video/fbdev/sm501fb.c base += SM501_DC_PANEL_PALETTE; base 946 drivers/video/fbdev/sm501fb.c smc501_writel(val, base + (regno * 4)); base 1042 drivers/video/fbdev/sm501fb.c void __iomem *base = fbi->regs; base 1049 drivers/video/fbdev/sm501fb.c base += SM501_DC_CRT_HWC_BASE; base 1051 drivers/video/fbdev/sm501fb.c base += SM501_DC_PANEL_HWC_BASE; base 1064 drivers/video/fbdev/sm501fb.c hwc_addr = smc501_readl(base + SM501_OFF_HWC_ADDR); base 1068 drivers/video/fbdev/sm501fb.c base + SM501_OFF_HWC_ADDR); base 1071 drivers/video/fbdev/sm501fb.c base + SM501_OFF_HWC_ADDR); base 1085 drivers/video/fbdev/sm501fb.c smc501_writel(x | (y << 16), base + SM501_OFF_HWC_LOC); base 1105 drivers/video/fbdev/sm501fb.c smc501_writel(bg, base + SM501_OFF_HWC_COLOR_1_2); base 1106 drivers/video/fbdev/sm501fb.c smc501_writel(fg, base + SM501_OFF_HWC_COLOR_3); base 384 drivers/video/fbdev/stifb.c #define BAIndexBase(base) (base) base 429 drivers/video/fbdev/tgafb.c int n, shift, base, min_diff, target; base 477 drivers/video/fbdev/tgafb.c base = target * r; base 478 drivers/video/fbdev/tgafb.c while (base < 449) { base 479 drivers/video/fbdev/tgafb.c for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) { base 490 drivers/video/fbdev/tgafb.c base += target; base 267 drivers/video/fbdev/tmiofb.c unsigned long base; base 272 drivers/video/fbdev/tmiofb.c base = nlcr->start; base 281 drivers/video/fbdev/tmiofb.c tmio_iowrite16(base >> 16, par->ccr + CCR_BASEH); base 282 drivers/video/fbdev/tmiofb.c tmio_iowrite16(base, par->ccr + CCR_BASEL); base 290 drivers/video/fbdev/tmiofb.c base = vram->start + info->screen_size; base 291 drivers/video/fbdev/tmiofb.c tmio_iowrite16(base >> 16, par->lcr + LCR_CFSAH); base 292 drivers/video/fbdev/tmiofb.c tmio_iowrite16(base, par->lcr + LCR_CFSAL); base 824 drivers/video/fbdev/tridentfb.c static void set_screen_start(struct tridentfb_par *par, int base) base 827 drivers/video/fbdev/tridentfb.c write3X4(par, VGA_CRTC_START_LO, base & 0xFF); base 828 drivers/video/fbdev/tridentfb.c write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8); base 830 drivers/video/fbdev/tridentfb.c write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11)); base 832 drivers/video/fbdev/tridentfb.c write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17)); base 150 drivers/video/fbdev/udlfb.c static char *dlfb_set_base16bpp(char *wrptr, u32 base) base 153 drivers/video/fbdev/udlfb.c wrptr = dlfb_set_register(wrptr, 0x20, base >> 16); base 154 drivers/video/fbdev/udlfb.c wrptr = dlfb_set_register(wrptr, 0x21, base >> 8); base 155 drivers/video/fbdev/udlfb.c return dlfb_set_register(wrptr, 0x22, base); base 162 drivers/video/fbdev/udlfb.c static char *dlfb_set_base8bpp(char *wrptr, u32 base) base 164 drivers/video/fbdev/udlfb.c wrptr = dlfb_set_register(wrptr, 0x26, base >> 16); base 165 drivers/video/fbdev/udlfb.c wrptr = dlfb_set_register(wrptr, 0x27, base >> 8); base 166 drivers/video/fbdev/udlfb.c return dlfb_set_register(wrptr, 0x28, base); base 189 drivers/video/fbdev/vesafb.c release_mem_region(info->apertures->ranges[0].base, info->apertures->ranges[0].size); base 318 drivers/video/fbdev/vesafb.c info->apertures->ranges[0].base = screen_info.lfb_base; base 1370 drivers/video/fbdev/vga16fb.c info->apertures->ranges[0].base = VGA_FB_PHYS; base 151 drivers/video/fbdev/via/via-gpio.c .base = -1, base 201 drivers/video/fbdev/via/via-gpio.c return viafb_gpio_config.gpio_chip.base + i; base 251 drivers/video/fbdev/via/via-gpio.c viafb_gpio_config.gpio_chip.base = -1; /* Dynamic */ base 87 drivers/virtio/virtio_mmio.c void __iomem *base; base 112 drivers/virtio/virtio_mmio.c writel(1, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); base 113 drivers/virtio/virtio_mmio.c features = readl(vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES); base 116 drivers/virtio/virtio_mmio.c writel(0, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); base 117 drivers/virtio/virtio_mmio.c features |= readl(vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES); base 136 drivers/virtio/virtio_mmio.c writel(1, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); base 138 drivers/virtio/virtio_mmio.c vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES); base 140 drivers/virtio/virtio_mmio.c writel(0, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); base 142 drivers/virtio/virtio_mmio.c vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES); base 151 drivers/virtio/virtio_mmio.c void __iomem *base = vm_dev->base + VIRTIO_MMIO_CONFIG; base 161 drivers/virtio/virtio_mmio.c ptr[i] = readb(base + offset + i); base 167 drivers/virtio/virtio_mmio.c b = readb(base + offset); base 171 drivers/virtio/virtio_mmio.c w = cpu_to_le16(readw(base + offset)); base 175 drivers/virtio/virtio_mmio.c l = cpu_to_le32(readl(base + offset)); base 179 drivers/virtio/virtio_mmio.c l = cpu_to_le32(readl(base + offset)); base 181 drivers/virtio/virtio_mmio.c l = cpu_to_le32(ioread32(base + offset + sizeof l)); base 193 drivers/virtio/virtio_mmio.c void __iomem *base = vm_dev->base + VIRTIO_MMIO_CONFIG; base 203 drivers/virtio/virtio_mmio.c writeb(ptr[i], base + offset + i); base 211 drivers/virtio/virtio_mmio.c writeb(b, base + offset); base 215 drivers/virtio/virtio_mmio.c writew(le16_to_cpu(w), base + offset); base 219 drivers/virtio/virtio_mmio.c writel(le32_to_cpu(l), base + offset); base 223 drivers/virtio/virtio_mmio.c writel(le32_to_cpu(l), base + offset); base 225 drivers/virtio/virtio_mmio.c writel(le32_to_cpu(l), base + offset + sizeof l); base 239 drivers/virtio/virtio_mmio.c return readl(vm_dev->base + VIRTIO_MMIO_CONFIG_GENERATION); base 246 drivers/virtio/virtio_mmio.c return readl(vm_dev->base + VIRTIO_MMIO_STATUS) & 0xff; base 256 drivers/virtio/virtio_mmio.c writel(status, vm_dev->base + VIRTIO_MMIO_STATUS); base 264 drivers/virtio/virtio_mmio.c writel(0, vm_dev->base + VIRTIO_MMIO_STATUS); base 278 drivers/virtio/virtio_mmio.c writel(vq->index, vm_dev->base + VIRTIO_MMIO_QUEUE_NOTIFY); base 292 drivers/virtio/virtio_mmio.c status = readl(vm_dev->base + VIRTIO_MMIO_INTERRUPT_STATUS); base 293 drivers/virtio/virtio_mmio.c writel(status, vm_dev->base + VIRTIO_MMIO_INTERRUPT_ACK); base 324 drivers/virtio/virtio_mmio.c writel(index, vm_dev->base + VIRTIO_MMIO_QUEUE_SEL); base 326 drivers/virtio/virtio_mmio.c writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN); base 328 drivers/virtio/virtio_mmio.c writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_READY); base 329 drivers/virtio/virtio_mmio.c WARN_ON(readl(vm_dev->base + VIRTIO_MMIO_QUEUE_READY)); base 363 drivers/virtio/virtio_mmio.c writel(index, vm_dev->base + VIRTIO_MMIO_QUEUE_SEL); base 366 drivers/virtio/virtio_mmio.c if (readl(vm_dev->base + (vm_dev->version == 1 ? base 379 drivers/virtio/virtio_mmio.c num = readl(vm_dev->base + VIRTIO_MMIO_QUEUE_NUM_MAX); base 394 drivers/virtio/virtio_mmio.c writel(virtqueue_get_vring_size(vq), vm_dev->base + VIRTIO_MMIO_QUEUE_NUM); base 411 drivers/virtio/virtio_mmio.c writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_QUEUE_ALIGN); base 412 drivers/virtio/virtio_mmio.c writel(q_pfn, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN); base 417 drivers/virtio/virtio_mmio.c writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_DESC_LOW); base 419 drivers/virtio/virtio_mmio.c vm_dev->base + VIRTIO_MMIO_QUEUE_DESC_HIGH); base 422 drivers/virtio/virtio_mmio.c writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_AVAIL_LOW); base 424 drivers/virtio/virtio_mmio.c vm_dev->base + VIRTIO_MMIO_QUEUE_AVAIL_HIGH); base 427 drivers/virtio/virtio_mmio.c writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_USED_LOW); base 429 drivers/virtio/virtio_mmio.c vm_dev->base + VIRTIO_MMIO_QUEUE_USED_HIGH); base 431 drivers/virtio/virtio_mmio.c writel(1, vm_dev->base + VIRTIO_MMIO_QUEUE_READY); base 447 drivers/virtio/virtio_mmio.c writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN); base 449 drivers/virtio/virtio_mmio.c writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_READY); base 450 drivers/virtio/virtio_mmio.c WARN_ON(readl(vm_dev->base + VIRTIO_MMIO_QUEUE_READY)); base 557 drivers/virtio/virtio_mmio.c vm_dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); base 558 drivers/virtio/virtio_mmio.c if (vm_dev->base == NULL) base 562 drivers/virtio/virtio_mmio.c magic = readl(vm_dev->base + VIRTIO_MMIO_MAGIC_VALUE); base 569 drivers/virtio/virtio_mmio.c vm_dev->version = readl(vm_dev->base + VIRTIO_MMIO_VERSION); base 576 drivers/virtio/virtio_mmio.c vm_dev->vdev.id.device = readl(vm_dev->base + VIRTIO_MMIO_DEVICE_ID); base 584 drivers/virtio/virtio_mmio.c vm_dev->vdev.id.vendor = readl(vm_dev->base + VIRTIO_MMIO_VENDOR_ID); base 587 drivers/virtio/virtio_mmio.c writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_GUEST_PAGE_SIZE); base 641 drivers/virtio/virtio_mmio.c long long int base, size; base 651 drivers/virtio/virtio_mmio.c &base, &irq, &consumed, base 663 drivers/virtio/virtio_mmio.c resources[0].start = base; base 664 drivers/virtio/virtio_mmio.c resources[0].end = base + size - 1; base 82 drivers/vlynq/vlynq.c static void vlynq_dump_mem(u32 *base, int count) base 89 drivers/vlynq/vlynq.c printk(KERN_DEBUG " 0x%08x", *(base + i)); base 100 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DGCS); base 117 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DGCS); base 138 drivers/vme/bridges/vme_ca91cx42.c vec = ioread32(bridge->base + base 160 drivers/vme/bridges/vme_ca91cx42.c enable = ioread32(bridge->base + LINT_EN); base 161 drivers/vme/bridges/vme_ca91cx42.c stat = ioread32(bridge->base + LINT_STAT); base 189 drivers/vme/bridges/vme_ca91cx42.c iowrite32(serviced, bridge->base + LINT_STAT); base 206 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + VINT_EN); base 209 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + LINT_EN); base 211 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); base 222 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + LINT_MAP0); base 223 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + LINT_MAP1); base 224 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + LINT_MAP2); base 231 drivers/vme/bridges/vme_ca91cx42.c iowrite32(tmp, bridge->base + LINT_EN); base 242 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + VINT_EN); base 245 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + LINT_EN); base 247 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); base 258 drivers/vme/bridges/vme_ca91cx42.c tmp = ioread32(bridge->base + LINT_STAT); base 280 drivers/vme/bridges/vme_ca91cx42.c tmp = ioread32(bridge->base + LINT_EN); base 287 drivers/vme/bridges/vme_ca91cx42.c iowrite32(tmp, bridge->base + LINT_EN); base 310 drivers/vme/bridges/vme_ca91cx42.c tmp = ioread32(bridge->base + VINT_EN); base 313 drivers/vme/bridges/vme_ca91cx42.c iowrite32(statid << 24, bridge->base + STATID); base 317 drivers/vme/bridges/vme_ca91cx42.c iowrite32(tmp, bridge->base + VINT_EN); base 324 drivers/vme/bridges/vme_ca91cx42.c tmp = ioread32(bridge->base + VINT_EN); base 326 drivers/vme/bridges/vme_ca91cx42.c iowrite32(tmp, bridge->base + VINT_EN); base 404 drivers/vme/bridges/vme_ca91cx42.c temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); base 406 drivers/vme/bridges/vme_ca91cx42.c iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); base 409 drivers/vme/bridges/vme_ca91cx42.c iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); base 410 drivers/vme/bridges/vme_ca91cx42.c iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); base 411 drivers/vme/bridges/vme_ca91cx42.c iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); base 429 drivers/vme/bridges/vme_ca91cx42.c iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); base 434 drivers/vme/bridges/vme_ca91cx42.c iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); base 457 drivers/vme/bridges/vme_ca91cx42.c ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); base 459 drivers/vme/bridges/vme_ca91cx42.c *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]); base 460 drivers/vme/bridges/vme_ca91cx42.c vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]); base 461 drivers/vme/bridges/vme_ca91cx42.c pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]); base 650 drivers/vme/bridges/vme_ca91cx42.c temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); base 652 drivers/vme/bridges/vme_ca91cx42.c iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); base 723 drivers/vme/bridges/vme_ca91cx42.c iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]); base 724 drivers/vme/bridges/vme_ca91cx42.c iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]); base 725 drivers/vme/bridges/vme_ca91cx42.c iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]); base 728 drivers/vme/bridges/vme_ca91cx42.c iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); base 733 drivers/vme/bridges/vme_ca91cx42.c iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); base 758 drivers/vme/bridges/vme_ca91cx42.c ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); base 760 drivers/vme/bridges/vme_ca91cx42.c pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]); base 761 drivers/vme/bridges/vme_ca91cx42.c vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]); base 762 drivers/vme/bridges/vme_ca91cx42.c pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]); base 993 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + SCYC_CTL); base 996 drivers/vme/bridges/vme_ca91cx42.c iowrite32(mask, bridge->base + SCYC_EN); base 997 drivers/vme/bridges/vme_ca91cx42.c iowrite32(compare, bridge->base + SCYC_CMP); base 998 drivers/vme/bridges/vme_ca91cx42.c iowrite32(swap, bridge->base + SCYC_SWP); base 999 drivers/vme/bridges/vme_ca91cx42.c iowrite32(pci_addr, bridge->base + SCYC_ADDR); base 1002 drivers/vme/bridges/vme_ca91cx42.c iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL); base 1008 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + SCYC_CTL); base 1169 drivers/vme/bridges/vme_ca91cx42.c tmp = ioread32(bridge->base + DGCS); base 1215 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + DTBC); base 1216 drivers/vme/bridges/vme_ca91cx42.c iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); base 1219 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DGCS); base 1228 drivers/vme/bridges/vme_ca91cx42.c iowrite32(val, bridge->base + DGCS); base 1232 drivers/vme/bridges/vme_ca91cx42.c iowrite32(val, bridge->base + DGCS); base 1238 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DGCS); base 1239 drivers/vme/bridges/vme_ca91cx42.c iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS); base 1251 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DGCS); base 1257 drivers/vme/bridges/vme_ca91cx42.c val = ioread32(bridge->base + DCTL); base 1350 drivers/vme/bridges/vme_ca91cx42.c iowrite32(lm_base, bridge->base + LM_BS); base 1351 drivers/vme/bridges/vme_ca91cx42.c iowrite32(lm_ctl, bridge->base + LM_CTL); base 1371 drivers/vme/bridges/vme_ca91cx42.c *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); base 1372 drivers/vme/bridges/vme_ca91cx42.c lm_ctl = ioread32(bridge->base + LM_CTL); base 1417 drivers/vme/bridges/vme_ca91cx42.c lm_ctl = ioread32(bridge->base + LM_CTL); base 1436 drivers/vme/bridges/vme_ca91cx42.c tmp = ioread32(bridge->base + LINT_EN); base 1438 drivers/vme/bridges/vme_ca91cx42.c iowrite32(tmp, bridge->base + LINT_EN); base 1443 drivers/vme/bridges/vme_ca91cx42.c iowrite32(lm_ctl, bridge->base + LM_CTL); base 1464 drivers/vme/bridges/vme_ca91cx42.c tmp = ioread32(bridge->base + LINT_EN); base 1466 drivers/vme/bridges/vme_ca91cx42.c iowrite32(tmp, bridge->base + LINT_EN); base 1469 drivers/vme/bridges/vme_ca91cx42.c bridge->base + LINT_STAT); base 1478 drivers/vme/bridges/vme_ca91cx42.c tmp = ioread32(bridge->base + LM_CTL); base 1480 drivers/vme/bridges/vme_ca91cx42.c iowrite32(tmp, bridge->base + LM_CTL); base 1496 drivers/vme/bridges/vme_ca91cx42.c slot = ioread32(bridge->base + VCSR_BS); base 1548 drivers/vme/bridges/vme_ca91cx42.c iowrite32(geoid << 27, bridge->base + VCSR_BS); base 1567 drivers/vme/bridges/vme_ca91cx42.c iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO); base 1569 drivers/vme/bridges/vme_ca91cx42.c tmp = ioread32(bridge->base + VCSR_CTL); base 1571 drivers/vme/bridges/vme_ca91cx42.c iowrite32(tmp, bridge->base + VCSR_CTL); base 1585 drivers/vme/bridges/vme_ca91cx42.c tmp = ioread32(bridge->base + VCSR_CTL); base 1587 drivers/vme/bridges/vme_ca91cx42.c iowrite32(tmp, bridge->base + VCSR_CTL); base 1590 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + VCSR_TO); base 1641 drivers/vme/bridges/vme_ca91cx42.c ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0), base 1643 drivers/vme/bridges/vme_ca91cx42.c if (!ca91cx42_device->base) { base 1650 drivers/vme/bridges/vme_ca91cx42.c data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF; base 1772 drivers/vme/bridges/vme_ca91cx42.c data = ioread32(ca91cx42_device->base + MISC_CTL); base 1829 drivers/vme/bridges/vme_ca91cx42.c iounmap(ca91cx42_device->base); base 1857 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0, bridge->base + LINT_EN); base 1860 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00800000, bridge->base + LSI0_CTL); base 1861 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00800000, bridge->base + LSI1_CTL); base 1862 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00800000, bridge->base + LSI2_CTL); base 1863 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00800000, bridge->base + LSI3_CTL); base 1864 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00800000, bridge->base + LSI4_CTL); base 1865 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00800000, bridge->base + LSI5_CTL); base 1866 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00800000, bridge->base + LSI6_CTL); base 1867 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00800000, bridge->base + LSI7_CTL); base 1868 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00F00000, bridge->base + VSI0_CTL); base 1869 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00F00000, bridge->base + VSI1_CTL); base 1870 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00F00000, bridge->base + VSI2_CTL); base 1871 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00F00000, bridge->base + VSI3_CTL); base 1872 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00F00000, bridge->base + VSI4_CTL); base 1873 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00F00000, bridge->base + VSI5_CTL); base 1874 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00F00000, bridge->base + VSI6_CTL); base 1875 drivers/vme/bridges/vme_ca91cx42.c iowrite32(0x00F00000, bridge->base + VSI7_CTL); base 1912 drivers/vme/bridges/vme_ca91cx42.c iounmap(bridge->base); base 38 drivers/vme/bridges/vme_ca91cx42.h void __iomem *base; /* Base Address of device registers */ base 814 drivers/vme/bridges/vme_fake.c u32 tmp, base; base 824 drivers/vme/bridges/vme_fake.c base = bridge->masters[i].vme_base; base 832 drivers/vme/bridges/vme_fake.c tmp = fake_vmeread32(bridge, base + offset, aspace, cycle); base 840 drivers/vme/bridges/vme_fake.c fake_vmewrite32(bridge, &tmp, base + offset, aspace, cycle); base 127 drivers/vme/bridges/vme_tsi148.c val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); base 148 drivers/vme/bridges/vme_tsi148.c ioread32be(bridge->base + TSI148_LCSR_EDPAU), base 149 drivers/vme/bridges/vme_tsi148.c ioread32be(bridge->base + TSI148_LCSR_EDPAL), base 150 drivers/vme/bridges/vme_tsi148.c ioread32be(bridge->base + TSI148_LCSR_EDPAT)); base 154 drivers/vme/bridges/vme_tsi148.c ioread32be(bridge->base + TSI148_LCSR_EDPXA), base 155 drivers/vme/bridges/vme_tsi148.c ioread32be(bridge->base + TSI148_LCSR_EDPXS)); base 157 drivers/vme/bridges/vme_tsi148.c iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); base 175 drivers/vme/bridges/vme_tsi148.c error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); base 176 drivers/vme/bridges/vme_tsi148.c error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); base 177 drivers/vme/bridges/vme_tsi148.c error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT); base 196 drivers/vme/bridges/vme_tsi148.c iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT); base 229 drivers/vme/bridges/vme_tsi148.c vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3); base 255 drivers/vme/bridges/vme_tsi148.c enable = ioread32be(bridge->base + TSI148_LCSR_INTEO); base 256 drivers/vme/bridges/vme_tsi148.c stat = ioread32be(bridge->base + TSI148_LCSR_INTS); base 299 drivers/vme/bridges/vme_tsi148.c iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC); base 359 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); base 360 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); base 371 drivers/vme/bridges/vme_tsi148.c iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO); base 372 drivers/vme/bridges/vme_tsi148.c iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN); base 375 drivers/vme/bridges/vme_tsi148.c iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC); base 388 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); base 410 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); base 412 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); base 414 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); base 416 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); base 423 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); base 425 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); base 427 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); base 429 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); base 448 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); base 453 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); base 457 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); base 539 drivers/vme/bridges/vme_tsi148.c temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + base 542 drivers/vme/bridges/vme_tsi148.c iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + base 546 drivers/vme/bridges/vme_tsi148.c iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] + base 548 drivers/vme/bridges/vme_tsi148.c iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] + base 550 drivers/vme/bridges/vme_tsi148.c iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] + base 552 drivers/vme/bridges/vme_tsi148.c iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] + base 554 drivers/vme/bridges/vme_tsi148.c iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] + base 556 drivers/vme/bridges/vme_tsi148.c iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] + base 601 drivers/vme/bridges/vme_tsi148.c iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + base 607 drivers/vme/bridges/vme_tsi148.c iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + base 632 drivers/vme/bridges/vme_tsi148.c ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + base 635 drivers/vme/bridges/vme_tsi148.c vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + base 637 drivers/vme/bridges/vme_tsi148.c vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + base 639 drivers/vme/bridges/vme_tsi148.c vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + base 641 drivers/vme/bridges/vme_tsi148.c vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + base 643 drivers/vme/bridges/vme_tsi148.c pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + base 645 drivers/vme/bridges/vme_tsi148.c pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + base 903 drivers/vme/bridges/vme_tsi148.c temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + base 906 drivers/vme/bridges/vme_tsi148.c iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + base 1008 drivers/vme/bridges/vme_tsi148.c iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] + base 1010 drivers/vme/bridges/vme_tsi148.c iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] + base 1012 drivers/vme/bridges/vme_tsi148.c iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] + base 1014 drivers/vme/bridges/vme_tsi148.c iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] + base 1016 drivers/vme/bridges/vme_tsi148.c iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] + base 1018 drivers/vme/bridges/vme_tsi148.c iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] + base 1022 drivers/vme/bridges/vme_tsi148.c iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + base 1028 drivers/vme/bridges/vme_tsi148.c iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + base 1065 drivers/vme/bridges/vme_tsi148.c ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + base 1068 drivers/vme/bridges/vme_tsi148.c pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + base 1070 drivers/vme/bridges/vme_tsi148.c pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + base 1072 drivers/vme/bridges/vme_tsi148.c pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + base 1074 drivers/vme/bridges/vme_tsi148.c pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + base 1076 drivers/vme/bridges/vme_tsi148.c vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + base 1078 drivers/vme/bridges/vme_tsi148.c vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + base 1384 drivers/vme/bridges/vme_tsi148.c pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + base 1386 drivers/vme/bridges/vme_tsi148.c pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + base 1393 drivers/vme/bridges/vme_tsi148.c iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN); base 1394 drivers/vme/bridges/vme_tsi148.c iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC); base 1395 drivers/vme/bridges/vme_tsi148.c iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS); base 1396 drivers/vme/bridges/vme_tsi148.c iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU); base 1397 drivers/vme/bridges/vme_tsi148.c iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL); base 1400 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); base 1402 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); base 1408 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); base 1410 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); base 1792 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + base 1848 drivers/vme/bridges/vme_tsi148.c iowrite32be(bus_addr_high, bridge->base + base 1850 drivers/vme/bridges/vme_tsi148.c iowrite32be(bus_addr_low, bridge->base + base 1853 drivers/vme/bridges/vme_tsi148.c dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + base 1857 drivers/vme/bridges/vme_tsi148.c iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base + base 1864 drivers/vme/bridges/vme_tsi148.c iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base + base 1877 drivers/vme/bridges/vme_tsi148.c val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + base 1981 drivers/vme/bridges/vme_tsi148.c iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU); base 1982 drivers/vme/bridges/vme_tsi148.c iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL); base 1983 drivers/vme/bridges/vme_tsi148.c iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); base 2003 drivers/vme/bridges/vme_tsi148.c lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU); base 2004 drivers/vme/bridges/vme_tsi148.c lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL); base 2005 drivers/vme/bridges/vme_tsi148.c lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); base 2058 drivers/vme/bridges/vme_tsi148.c lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); base 2078 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); base 2080 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); base 2082 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); base 2084 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); base 2089 drivers/vme/bridges/vme_tsi148.c iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); base 2110 drivers/vme/bridges/vme_tsi148.c lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN); base 2112 drivers/vme/bridges/vme_tsi148.c iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN); base 2114 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); base 2116 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); base 2119 drivers/vme/bridges/vme_tsi148.c bridge->base + TSI148_LCSR_INTC); base 2128 drivers/vme/bridges/vme_tsi148.c tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT); base 2130 drivers/vme/bridges/vme_tsi148.c iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT); base 2149 drivers/vme/bridges/vme_tsi148.c slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT); base 2212 drivers/vme/bridges/vme_tsi148.c iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU); base 2213 drivers/vme/bridges/vme_tsi148.c iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL); base 2216 drivers/vme/bridges/vme_tsi148.c cbar = ioread32be(bridge->base + TSI148_CBAR); base 2224 drivers/vme/bridges/vme_tsi148.c iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); base 2228 drivers/vme/bridges/vme_tsi148.c crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); base 2234 drivers/vme/bridges/vme_tsi148.c bridge->base + TSI148_LCSR_CRAT); base 2263 drivers/vme/bridges/vme_tsi148.c crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); base 2265 drivers/vme/bridges/vme_tsi148.c bridge->base + TSI148_LCSR_CRAT); base 2268 drivers/vme/bridges/vme_tsi148.c iowrite32be(0, bridge->base + TSI148_LCSR_CROU); base 2269 drivers/vme/bridges/vme_tsi148.c iowrite32be(0, bridge->base + TSI148_LCSR_CROL); base 2320 drivers/vme/bridges/vme_tsi148.c tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0), base 2322 drivers/vme/bridges/vme_tsi148.c if (!tsi148_device->base) { base 2329 drivers/vme/bridges/vme_tsi148.c data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF; base 2479 drivers/vme/bridges/vme_tsi148.c data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); base 2507 drivers/vme/bridges/vme_tsi148.c data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); base 2510 drivers/vme/bridges/vme_tsi148.c iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT); base 2550 drivers/vme/bridges/vme_tsi148.c iounmap(tsi148_device->base); base 2584 drivers/vme/bridges/vme_tsi148.c iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] + base 2586 drivers/vme/bridges/vme_tsi148.c iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] + base 2593 drivers/vme/bridges/vme_tsi148.c iowrite32be(0, bridge->base + TSI148_LCSR_LMAT); base 2598 drivers/vme/bridges/vme_tsi148.c iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT); base 2603 drivers/vme/bridges/vme_tsi148.c iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT); base 2604 drivers/vme/bridges/vme_tsi148.c iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT); base 2605 drivers/vme/bridges/vme_tsi148.c iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT); base 2610 drivers/vme/bridges/vme_tsi148.c if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800) base 2611 drivers/vme/bridges/vme_tsi148.c iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR); base 2616 drivers/vme/bridges/vme_tsi148.c iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1); base 2617 drivers/vme/bridges/vme_tsi148.c iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2); base 2647 drivers/vme/bridges/vme_tsi148.c iounmap(bridge->base); base 34 drivers/vme/bridges/vme_tsi148.h void __iomem *base; /* Base Address of device registers */ base 170 drivers/vme/vme.c unsigned long long base, size; base 176 drivers/vme/vme.c retval = vme_master_get(resource, &enabled, &base, &size, base 184 drivers/vme/vme.c retval = vme_slave_get(resource, &enabled, &base, &size, base 18 drivers/watchdog/aspeed_wdt.c void __iomem *base; base 108 drivers/watchdog/aspeed_wdt.c writel(0, wdt->base + WDT_CTRL); base 109 drivers/watchdog/aspeed_wdt.c writel(count, wdt->base + WDT_RELOAD_VALUE); base 110 drivers/watchdog/aspeed_wdt.c writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); base 111 drivers/watchdog/aspeed_wdt.c writel(wdt->ctrl, wdt->base + WDT_CTRL); base 128 drivers/watchdog/aspeed_wdt.c writel(wdt->ctrl, wdt->base + WDT_CTRL); base 137 drivers/watchdog/aspeed_wdt.c writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); base 152 drivers/watchdog/aspeed_wdt.c writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE); base 153 drivers/watchdog/aspeed_wdt.c writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); base 176 drivers/watchdog/aspeed_wdt.c u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS); base 194 drivers/watchdog/aspeed_wdt.c wdt->base + WDT_CLEAR_TIMEOUT_STATUS); base 257 drivers/watchdog/aspeed_wdt.c wdt->base = devm_platform_ioremap_resource(pdev, 0); base 258 drivers/watchdog/aspeed_wdt.c if (IS_ERR(wdt->base)) base 259 drivers/watchdog/aspeed_wdt.c return PTR_ERR(wdt->base); base 312 drivers/watchdog/aspeed_wdt.c if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) { base 325 drivers/watchdog/aspeed_wdt.c u32 reg = readl(wdt->base + WDT_RESET_WIDTH); base 333 drivers/watchdog/aspeed_wdt.c writel(reg, wdt->base + WDT_RESET_WIDTH); base 341 drivers/watchdog/aspeed_wdt.c writel(reg, wdt->base + WDT_RESET_WIDTH); base 367 drivers/watchdog/aspeed_wdt.c writel(duration - 1, wdt->base + WDT_RESET_WIDTH); base 370 drivers/watchdog/aspeed_wdt.c status = readl(wdt->base + WDT_TIMEOUT_STATUS); base 41 drivers/watchdog/at91sam9_wdt.c readl_relaxed((wdt)->base + (field)) base 43 drivers/watchdog/at91sam9_wdt.c writel_relaxed((val), (wdt)->base + (field)) base 83 drivers/watchdog/at91sam9_wdt.c void __iomem *base; base 348 drivers/watchdog/at91sam9_wdt.c wdt->base = devm_platform_ioremap_resource(pdev, 0); base 349 drivers/watchdog/at91sam9_wdt.c if (IS_ERR(wdt->base)) base 350 drivers/watchdog/at91sam9_wdt.c return PTR_ERR(wdt->base); base 37 drivers/watchdog/atlas7_wdt.c void __iomem *base; base 47 drivers/watchdog/atlas7_wdt.c counter = readl(wdt->base + ATLAS7_WDT_CNT); base 48 drivers/watchdog/atlas7_wdt.c match = readl(wdt->base + ATLAS7_WDT_CNT_MATCH); base 59 drivers/watchdog/atlas7_wdt.c counter = readl(wdt->base + ATLAS7_WDT_CNT); base 63 drivers/watchdog/atlas7_wdt.c writel(match, wdt->base + ATLAS7_WDT_CNT_MATCH); base 74 drivers/watchdog/atlas7_wdt.c writel(readl(wdt->base + ATLAS7_WDT_CNT_CTRL) | ATLAS7_WDT_CNT_EN, base 75 drivers/watchdog/atlas7_wdt.c wdt->base + ATLAS7_WDT_CNT_CTRL); base 76 drivers/watchdog/atlas7_wdt.c writel(1, wdt->base + ATLAS7_WDT_EN); base 85 drivers/watchdog/atlas7_wdt.c writel(0, wdt->base + ATLAS7_WDT_EN); base 86 drivers/watchdog/atlas7_wdt.c writel(readl(wdt->base + ATLAS7_WDT_CNT_CTRL) & ~ATLAS7_WDT_CNT_EN, base 87 drivers/watchdog/atlas7_wdt.c wdt->base + ATLAS7_WDT_CNT_CTRL); base 142 drivers/watchdog/atlas7_wdt.c wdt->base = devm_platform_ioremap_resource(pdev, 0); base 143 drivers/watchdog/atlas7_wdt.c if (IS_ERR(wdt->base)) base 144 drivers/watchdog/atlas7_wdt.c return PTR_ERR(wdt->base); base 159 drivers/watchdog/atlas7_wdt.c writel(0, wdt->base + ATLAS7_WDT_CNT_CTRL); base 47 drivers/watchdog/bcm2835_wdt.c void __iomem *base; base 60 drivers/watchdog/bcm2835_wdt.c cur = readl(wdt->base + PM_RSTC); base 74 drivers/watchdog/bcm2835_wdt.c PM_WDOG_TIME_SET), wdt->base + PM_WDOG); base 75 drivers/watchdog/bcm2835_wdt.c cur = readl_relaxed(wdt->base + PM_RSTC); base 77 drivers/watchdog/bcm2835_wdt.c PM_RSTC_WRCFG_FULL_RESET, wdt->base + PM_RSTC); base 88 drivers/watchdog/bcm2835_wdt.c writel_relaxed(PM_PASSWORD | PM_RSTC_RESET, wdt->base + PM_RSTC); base 96 drivers/watchdog/bcm2835_wdt.c uint32_t ret = readl_relaxed(wdt->base + PM_WDOG); base 105 drivers/watchdog/bcm2835_wdt.c writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG); base 106 drivers/watchdog/bcm2835_wdt.c val = readl_relaxed(wdt->base + PM_RSTC); base 109 drivers/watchdog/bcm2835_wdt.c writel_relaxed(val, wdt->base + PM_RSTC); base 162 drivers/watchdog/bcm2835_wdt.c val = readl_relaxed(wdt->base + PM_RSTS); base 164 drivers/watchdog/bcm2835_wdt.c writel_relaxed(val, wdt->base + PM_RSTS); base 183 drivers/watchdog/bcm2835_wdt.c wdt->base = pm->base; base 29 drivers/watchdog/bcm7038_wdt.c void __iomem *base; base 44 drivers/watchdog/bcm7038_wdt.c writel(timeout, wdt->base + WDT_TIMEOUT_REG); base 51 drivers/watchdog/bcm7038_wdt.c writel(WDT_START_1, wdt->base + WDT_CMD_REG); base 52 drivers/watchdog/bcm7038_wdt.c writel(WDT_START_2, wdt->base + WDT_CMD_REG); base 69 drivers/watchdog/bcm7038_wdt.c writel(WDT_STOP_1, wdt->base + WDT_CMD_REG); base 70 drivers/watchdog/bcm7038_wdt.c writel(WDT_STOP_2, wdt->base + WDT_CMD_REG); base 91 drivers/watchdog/bcm7038_wdt.c time_left = readl(wdt->base + WDT_CMD_REG); base 127 drivers/watchdog/bcm7038_wdt.c wdt->base = devm_platform_ioremap_resource(pdev, 0); base 128 drivers/watchdog/bcm7038_wdt.c if (IS_ERR(wdt->base)) base 129 drivers/watchdog/bcm7038_wdt.c return PTR_ERR(wdt->base); base 38 drivers/watchdog/bcm_kona_wdt.c void __iomem *base; base 71 drivers/watchdog/bcm_kona_wdt.c val = readl_relaxed(wdt->base + offset); base 182 drivers/watchdog/bcm_kona_wdt.c writel_relaxed(val, wdt->base + SECWDOG_CTRL_REG); base 280 drivers/watchdog/bcm_kona_wdt.c wdt->base = devm_platform_ioremap_resource(pdev, 0); base 281 drivers/watchdog/bcm_kona_wdt.c if (IS_ERR(wdt->base)) base 65 drivers/watchdog/davinci_wdt.c void __iomem *base; base 80 drivers/watchdog/davinci_wdt.c iowrite32(0, davinci_wdt->base + TCR); base 82 drivers/watchdog/davinci_wdt.c iowrite32(0, davinci_wdt->base + TGCR); base 84 drivers/watchdog/davinci_wdt.c iowrite32(tgcr, davinci_wdt->base + TGCR); base 86 drivers/watchdog/davinci_wdt.c iowrite32(0, davinci_wdt->base + TIM12); base 87 drivers/watchdog/davinci_wdt.c iowrite32(0, davinci_wdt->base + TIM34); base 90 drivers/watchdog/davinci_wdt.c iowrite32(timer_margin, davinci_wdt->base + PRD12); base 92 drivers/watchdog/davinci_wdt.c iowrite32(timer_margin, davinci_wdt->base + PRD34); base 94 drivers/watchdog/davinci_wdt.c iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR); base 100 drivers/watchdog/davinci_wdt.c iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR); base 102 drivers/watchdog/davinci_wdt.c iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR); base 111 drivers/watchdog/davinci_wdt.c iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR); base 113 drivers/watchdog/davinci_wdt.c iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR); base 125 drivers/watchdog/davinci_wdt.c val = ioread32(davinci_wdt->base + WDTCR); base 134 drivers/watchdog/davinci_wdt.c timer_counter = ioread32(davinci_wdt->base + TIM12); base 135 drivers/watchdog/davinci_wdt.c timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32); base 149 drivers/watchdog/davinci_wdt.c iowrite32(0, davinci_wdt->base + TCR); base 153 drivers/watchdog/davinci_wdt.c iowrite32(tgcr, davinci_wdt->base + TGCR); base 155 drivers/watchdog/davinci_wdt.c iowrite32(tgcr, davinci_wdt->base + TGCR); base 158 drivers/watchdog/davinci_wdt.c iowrite32(0, davinci_wdt->base + TIM12); base 159 drivers/watchdog/davinci_wdt.c iowrite32(0, davinci_wdt->base + TIM34); base 160 drivers/watchdog/davinci_wdt.c iowrite32(0, davinci_wdt->base + PRD12); base 161 drivers/watchdog/davinci_wdt.c iowrite32(0, davinci_wdt->base + PRD34); base 165 drivers/watchdog/davinci_wdt.c iowrite32(wdtcr, davinci_wdt->base + WDTCR); base 169 drivers/watchdog/davinci_wdt.c iowrite32(wdtcr, davinci_wdt->base + WDTCR); base 173 drivers/watchdog/davinci_wdt.c iowrite32(wdtcr, davinci_wdt->base + WDTCR); base 244 drivers/watchdog/davinci_wdt.c davinci_wdt->base = devm_platform_ioremap_resource(pdev, 0); base 245 drivers/watchdog/davinci_wdt.c if (IS_ERR(davinci_wdt->base)) base 246 drivers/watchdog/davinci_wdt.c return PTR_ERR(davinci_wdt->base); base 25 drivers/watchdog/digicolor_wdt.c void __iomem *base; base 40 drivers/watchdog/digicolor_wdt.c writel_relaxed(0, wdt->base + TIMER_A_CONTROL); base 41 drivers/watchdog/digicolor_wdt.c writel_relaxed(ticks, wdt->base + TIMER_A_COUNT); base 43 drivers/watchdog/digicolor_wdt.c wdt->base + TIMER_A_CONTROL); base 73 drivers/watchdog/digicolor_wdt.c writel_relaxed(0, wdt->base + TIMER_A_CONTROL); base 91 drivers/watchdog/digicolor_wdt.c uint32_t count = readl_relaxed(wdt->base + TIMER_A_COUNT); base 126 drivers/watchdog/digicolor_wdt.c wdt->base = devm_platform_ioremap_resource(pdev, 0); base 127 drivers/watchdog/digicolor_wdt.c if (IS_ERR(wdt->base)) base 128 drivers/watchdog/digicolor_wdt.c return PTR_ERR(wdt->base); base 130 drivers/watchdog/f71808e_wdt.c static inline int superio_inb(int base, int reg); base 131 drivers/watchdog/f71808e_wdt.c static inline int superio_inw(int base, int reg); base 132 drivers/watchdog/f71808e_wdt.c static inline void superio_outb(int base, int reg, u8 val); base 133 drivers/watchdog/f71808e_wdt.c static inline void superio_set_bit(int base, int reg, int bit); base 134 drivers/watchdog/f71808e_wdt.c static inline void superio_clear_bit(int base, int reg, int bit); base 135 drivers/watchdog/f71808e_wdt.c static inline int superio_enter(int base); base 136 drivers/watchdog/f71808e_wdt.c static inline void superio_select(int base, int ld); base 137 drivers/watchdog/f71808e_wdt.c static inline void superio_exit(int base); base 160 drivers/watchdog/f71808e_wdt.c static inline int superio_inb(int base, int reg) base 162 drivers/watchdog/f71808e_wdt.c outb(reg, base); base 163 drivers/watchdog/f71808e_wdt.c return inb(base + 1); base 166 drivers/watchdog/f71808e_wdt.c static int superio_inw(int base, int reg) base 169 drivers/watchdog/f71808e_wdt.c val = superio_inb(base, reg) << 8; base 170 drivers/watchdog/f71808e_wdt.c val |= superio_inb(base, reg + 1); base 174 drivers/watchdog/f71808e_wdt.c static inline void superio_outb(int base, int reg, u8 val) base 176 drivers/watchdog/f71808e_wdt.c outb(reg, base); base 177 drivers/watchdog/f71808e_wdt.c outb(val, base + 1); base 180 drivers/watchdog/f71808e_wdt.c static inline void superio_set_bit(int base, int reg, int bit) base 182 drivers/watchdog/f71808e_wdt.c unsigned long val = superio_inb(base, reg); base 184 drivers/watchdog/f71808e_wdt.c superio_outb(base, reg, val); base 187 drivers/watchdog/f71808e_wdt.c static inline void superio_clear_bit(int base, int reg, int bit) base 189 drivers/watchdog/f71808e_wdt.c unsigned long val = superio_inb(base, reg); base 191 drivers/watchdog/f71808e_wdt.c superio_outb(base, reg, val); base 194 drivers/watchdog/f71808e_wdt.c static inline int superio_enter(int base) base 197 drivers/watchdog/f71808e_wdt.c if (!request_muxed_region(base, 2, DRVNAME)) { base 198 drivers/watchdog/f71808e_wdt.c pr_err("I/O address 0x%04x already in use\n", (int)base); base 203 drivers/watchdog/f71808e_wdt.c outb(SIO_UNLOCK_KEY, base); base 204 drivers/watchdog/f71808e_wdt.c outb(SIO_UNLOCK_KEY, base); base 209 drivers/watchdog/f71808e_wdt.c static inline void superio_select(int base, int ld) base 211 drivers/watchdog/f71808e_wdt.c outb(SIO_REG_LDSEL, base); base 212 drivers/watchdog/f71808e_wdt.c outb(ld, base + 1); base 215 drivers/watchdog/f71808e_wdt.c static inline void superio_exit(int base) base 217 drivers/watchdog/f71808e_wdt.c outb(SIO_LOCK_KEY, base); base 218 drivers/watchdog/f71808e_wdt.c release_region(base, 2); base 40 drivers/watchdog/ftwdt010_wdt.c void __iomem *base; base 55 drivers/watchdog/ftwdt010_wdt.c writel(wdd->timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD); base 56 drivers/watchdog/ftwdt010_wdt.c writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART); base 59 drivers/watchdog/ftwdt010_wdt.c writel(enable, gwdt->base + FTWDT010_WDCR); base 63 drivers/watchdog/ftwdt010_wdt.c writel(enable, gwdt->base + FTWDT010_WDCR); base 72 drivers/watchdog/ftwdt010_wdt.c writel(0, gwdt->base + FTWDT010_WDCR); base 81 drivers/watchdog/ftwdt010_wdt.c writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART); base 133 drivers/watchdog/ftwdt010_wdt.c gwdt->base = devm_platform_ioremap_resource(pdev, 0); base 134 drivers/watchdog/ftwdt010_wdt.c if (IS_ERR(gwdt->base)) base 135 drivers/watchdog/ftwdt010_wdt.c return PTR_ERR(gwdt->base); base 151 drivers/watchdog/ftwdt010_wdt.c reg = readw(gwdt->base + FTWDT010_WDCR); base 155 drivers/watchdog/ftwdt010_wdt.c writel(reg, gwdt->base + FTWDT010_WDCR); base 183 drivers/watchdog/ftwdt010_wdt.c reg = readw(gwdt->base + FTWDT010_WDCR); base 185 drivers/watchdog/ftwdt010_wdt.c writel(reg, gwdt->base + FTWDT010_WDCR); base 196 drivers/watchdog/ftwdt010_wdt.c reg = readw(gwdt->base + FTWDT010_WDCR); base 198 drivers/watchdog/ftwdt010_wdt.c writel(reg, gwdt->base + FTWDT010_WDCR); base 49 drivers/watchdog/i6300esb.c #define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */ base 50 drivers/watchdog/i6300esb.c #define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */ base 51 drivers/watchdog/i6300esb.c #define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */ base 52 drivers/watchdog/i6300esb.c #define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */ base 94 drivers/watchdog/i6300esb.c void __iomem *base; base 229 drivers/watchdog/i6300esb.c edev->base = pci_ioremap_bar(edev->pdev, 0); base 230 drivers/watchdog/i6300esb.c if (edev->base == NULL) { base 326 drivers/watchdog/i6300esb.c iounmap(edev->base); base 337 drivers/watchdog/i6300esb.c iounmap(edev->base); base 86 drivers/watchdog/imgpdc_wdt.c void __iomem *base; base 93 drivers/watchdog/imgpdc_wdt.c writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1); base 94 drivers/watchdog/imgpdc_wdt.c writel(PDC_WDT_TICKLE2_MAGIC, wdt->base + PDC_WDT_TICKLE2); base 104 drivers/watchdog/imgpdc_wdt.c val = readl(wdt->base + PDC_WDT_CONFIG); base 106 drivers/watchdog/imgpdc_wdt.c writel(val, wdt->base + PDC_WDT_CONFIG); base 119 drivers/watchdog/imgpdc_wdt.c val = readl(wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK; base 121 drivers/watchdog/imgpdc_wdt.c writel(val, wdt->base + PDC_WDT_CONFIG); base 144 drivers/watchdog/imgpdc_wdt.c val = readl(wdt->base + PDC_WDT_CONFIG); base 146 drivers/watchdog/imgpdc_wdt.c writel(val, wdt->base + PDC_WDT_CONFIG); base 157 drivers/watchdog/imgpdc_wdt.c writel(0x1, wdt->base + PDC_WDT_SOFT_RESET); base 195 drivers/watchdog/imgpdc_wdt.c pdc_wdt->base = devm_platform_ioremap_resource(pdev, 0); base 196 drivers/watchdog/imgpdc_wdt.c if (IS_ERR(pdc_wdt->base)) base 197 drivers/watchdog/imgpdc_wdt.c return PTR_ERR(pdc_wdt->base); base 263 drivers/watchdog/imgpdc_wdt.c val = readl(pdc_wdt->base + PDC_WDT_TICKLE1); base 252 drivers/watchdog/imx2_wdt.c void __iomem *base; base 260 drivers/watchdog/imx2_wdt.c base = devm_platform_ioremap_resource(pdev, 0); base 261 drivers/watchdog/imx2_wdt.c if (IS_ERR(base)) base 262 drivers/watchdog/imx2_wdt.c return PTR_ERR(base); base 264 drivers/watchdog/imx2_wdt.c wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, base 46 drivers/watchdog/imx7ulp_wdt.c void __iomem *base; base 50 drivers/watchdog/imx7ulp_wdt.c static inline void imx7ulp_wdt_enable(void __iomem *base, bool enable) base 52 drivers/watchdog/imx7ulp_wdt.c u32 val = readl(base + WDOG_CS); base 54 drivers/watchdog/imx7ulp_wdt.c writel(UNLOCK, base + WDOG_CNT); base 56 drivers/watchdog/imx7ulp_wdt.c writel(val | WDOG_CS_EN, base + WDOG_CS); base 58 drivers/watchdog/imx7ulp_wdt.c writel(val & ~WDOG_CS_EN, base + WDOG_CS); base 61 drivers/watchdog/imx7ulp_wdt.c static inline bool imx7ulp_wdt_is_enabled(void __iomem *base) base 63 drivers/watchdog/imx7ulp_wdt.c u32 val = readl(base + WDOG_CS); base 72 drivers/watchdog/imx7ulp_wdt.c writel(REFRESH, wdt->base + WDOG_CNT); base 81 drivers/watchdog/imx7ulp_wdt.c imx7ulp_wdt_enable(wdt->base, true); base 90 drivers/watchdog/imx7ulp_wdt.c imx7ulp_wdt_enable(wdt->base, false); base 101 drivers/watchdog/imx7ulp_wdt.c writel(UNLOCK, wdt->base + WDOG_CNT); base 102 drivers/watchdog/imx7ulp_wdt.c writel(val, wdt->base + WDOG_TOVAL); base 114 drivers/watchdog/imx7ulp_wdt.c imx7ulp_wdt_enable(wdt->base, true); base 139 drivers/watchdog/imx7ulp_wdt.c static inline void imx7ulp_wdt_init(void __iomem *base, unsigned int timeout) base 144 drivers/watchdog/imx7ulp_wdt.c writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT); base 145 drivers/watchdog/imx7ulp_wdt.c writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT); base 148 drivers/watchdog/imx7ulp_wdt.c writel(timeout, base + WDOG_TOVAL); base 151 drivers/watchdog/imx7ulp_wdt.c writel(val, base + WDOG_CS); base 172 drivers/watchdog/imx7ulp_wdt.c imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0); base 173 drivers/watchdog/imx7ulp_wdt.c if (IS_ERR(imx7ulp_wdt->base)) base 174 drivers/watchdog/imx7ulp_wdt.c return PTR_ERR(imx7ulp_wdt->base); base 202 drivers/watchdog/imx7ulp_wdt.c imx7ulp_wdt_init(imx7ulp_wdt->base, wdog->timeout * WDOG_CLOCK_RATE); base 229 drivers/watchdog/imx7ulp_wdt.c if (imx7ulp_wdt_is_enabled(imx7ulp_wdt->base)) base 230 drivers/watchdog/imx7ulp_wdt.c imx7ulp_wdt_init(imx7ulp_wdt->base, timeout); base 52 drivers/watchdog/jz4740_wdt.c void __iomem *base; base 60 drivers/watchdog/jz4740_wdt.c writew(0x0, drvdata->base + TCU_REG_WDT_TCNT); base 87 drivers/watchdog/jz4740_wdt.c tcer = readb(drvdata->base + TCU_REG_WDT_TCER); base 88 drivers/watchdog/jz4740_wdt.c writeb(0x0, drvdata->base + TCU_REG_WDT_TCER); base 89 drivers/watchdog/jz4740_wdt.c writew(clock_div, drvdata->base + TCU_REG_WDT_TCSR); base 91 drivers/watchdog/jz4740_wdt.c writew((u16)timeout_value, drvdata->base + TCU_REG_WDT_TDR); base 92 drivers/watchdog/jz4740_wdt.c writew(0x0, drvdata->base + TCU_REG_WDT_TCNT); base 93 drivers/watchdog/jz4740_wdt.c writew(clock_div | JZ_WDT_CLOCK_RTC, drvdata->base + TCU_REG_WDT_TCSR); base 96 drivers/watchdog/jz4740_wdt.c writeb(TCU_WDT_TCER_TCEN, drvdata->base + TCU_REG_WDT_TCER); base 107 drivers/watchdog/jz4740_wdt.c tcer = readb(drvdata->base + TCU_REG_WDT_TCER); base 114 drivers/watchdog/jz4740_wdt.c writeb(TCU_WDT_TCER_TCEN, drvdata->base + TCU_REG_WDT_TCER); base 123 drivers/watchdog/jz4740_wdt.c writeb(0x0, drvdata->base + TCU_REG_WDT_TCER); base 184 drivers/watchdog/jz4740_wdt.c drvdata->base = devm_platform_ioremap_resource(pdev, 0); base 185 drivers/watchdog/jz4740_wdt.c if (IS_ERR(drvdata->base)) base 186 drivers/watchdog/jz4740_wdt.c return PTR_ERR(drvdata->base); base 21 drivers/watchdog/loongson1_wdt.c void __iomem *base; base 31 drivers/watchdog/loongson1_wdt.c writel(0x1, drvdata->base + WDT_SET); base 46 drivers/watchdog/loongson1_wdt.c writel(counts, drvdata->base + WDT_TIMER); base 55 drivers/watchdog/loongson1_wdt.c writel(0x1, drvdata->base + WDT_EN); base 64 drivers/watchdog/loongson1_wdt.c writel(0x0, drvdata->base + WDT_EN); base 99 drivers/watchdog/loongson1_wdt.c drvdata->base = devm_platform_ioremap_resource(pdev, 0); base 100 drivers/watchdog/loongson1_wdt.c if (IS_ERR(drvdata->base)) base 101 drivers/watchdog/loongson1_wdt.c return PTR_ERR(drvdata->base); base 56 drivers/watchdog/lpc18xx_wdt.c void __iomem *base; base 71 drivers/watchdog/lpc18xx_wdt.c writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED); base 72 drivers/watchdog/lpc18xx_wdt.c writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED); base 109 drivers/watchdog/lpc18xx_wdt.c writel(val, lpc18xx_wdt->base + LPC18XX_WDT_TC); base 128 drivers/watchdog/lpc18xx_wdt.c val = readl(lpc18xx_wdt->base + LPC18XX_WDT_TV); base 140 drivers/watchdog/lpc18xx_wdt.c val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD); base 143 drivers/watchdog/lpc18xx_wdt.c writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD); base 167 drivers/watchdog/lpc18xx_wdt.c val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD); base 170 drivers/watchdog/lpc18xx_wdt.c writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD); base 172 drivers/watchdog/lpc18xx_wdt.c writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED); base 173 drivers/watchdog/lpc18xx_wdt.c writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED); base 175 drivers/watchdog/lpc18xx_wdt.c writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED); base 176 drivers/watchdog/lpc18xx_wdt.c writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED); base 215 drivers/watchdog/lpc18xx_wdt.c lpc18xx_wdt->base = devm_platform_ioremap_resource(pdev, 0); base 216 drivers/watchdog/lpc18xx_wdt.c if (IS_ERR(lpc18xx_wdt->base)) base 217 drivers/watchdog/lpc18xx_wdt.c return PTR_ERR(lpc18xx_wdt->base); base 52 drivers/watchdog/max63xx_wdt.c void __iomem *base; base 166 drivers/watchdog/max63xx_wdt.c val = __raw_readb(wdt->base); base 168 drivers/watchdog/max63xx_wdt.c __raw_writeb(val | MAX6369_WDI, wdt->base); base 169 drivers/watchdog/max63xx_wdt.c __raw_writeb(val & ~MAX6369_WDI, wdt->base); base 180 drivers/watchdog/max63xx_wdt.c val = __raw_readb(wdt->base); base 183 drivers/watchdog/max63xx_wdt.c __raw_writeb(val, wdt->base); base 190 drivers/watchdog/max63xx_wdt.c wdt->base = devm_platform_ioremap_resource(p, 0); base 191 drivers/watchdog/max63xx_wdt.c if (IS_ERR(wdt->base)) base 192 drivers/watchdog/max63xx_wdt.c return PTR_ERR(wdt->base); base 15 drivers/watchdog/menz69_wdt.c void __iomem *base; base 39 drivers/watchdog/menz69_wdt.c val = readw(drv->base + MEN_Z069_WTR); base 41 drivers/watchdog/menz69_wdt.c writew(val, drv->base + MEN_Z069_WTR); base 51 drivers/watchdog/menz69_wdt.c val = readw(drv->base + MEN_Z069_WTR); base 53 drivers/watchdog/menz69_wdt.c writew(val, drv->base + MEN_Z069_WTR); base 64 drivers/watchdog/menz69_wdt.c val = readw(drv->base + MEN_Z069_WVR); base 66 drivers/watchdog/menz69_wdt.c writew(val, drv->base + MEN_Z069_WVR); base 80 drivers/watchdog/menz69_wdt.c reg = readw(drv->base + MEN_Z069_WVR); base 83 drivers/watchdog/menz69_wdt.c writew(reg, drv->base + MEN_Z069_WTR); base 123 drivers/watchdog/menz69_wdt.c drv->base = devm_ioremap(&dev->dev, mem->start, resource_size(mem)); base 124 drivers/watchdog/menz69_wdt.c if (drv->base == NULL) base 29 drivers/watchdog/moxart_wdt.c void __iomem *base; base 40 drivers/watchdog/moxart_wdt.c writel(1, moxart_wdt->base + REG_COUNT); base 41 drivers/watchdog/moxart_wdt.c writel(0x5ab9, moxart_wdt->base + REG_MODE); base 42 drivers/watchdog/moxart_wdt.c writel(0x03, moxart_wdt->base + REG_ENABLE); base 51 drivers/watchdog/moxart_wdt.c writel(0, moxart_wdt->base + REG_ENABLE); base 61 drivers/watchdog/moxart_wdt.c moxart_wdt->base + REG_COUNT); base 62 drivers/watchdog/moxart_wdt.c writel(0x5ab9, moxart_wdt->base + REG_MODE); base 63 drivers/watchdog/moxart_wdt.c writel(0x03, moxart_wdt->base + REG_ENABLE); base 105 drivers/watchdog/moxart_wdt.c moxart_wdt->base = devm_platform_ioremap_resource(pdev, 0); base 106 drivers/watchdog/moxart_wdt.c if (IS_ERR(moxart_wdt->base)) base 107 drivers/watchdog/moxart_wdt.c return PTR_ERR(moxart_wdt->base); base 50 drivers/watchdog/mpc8xxx_wdt.c struct mpc8xxx_wdt __iomem *base; base 76 drivers/watchdog/mpc8xxx_wdt.c out_be16(&ddata->base->swsrr, 0x556c); base 77 drivers/watchdog/mpc8xxx_wdt.c out_be16(&ddata->base->swsrr, 0xaa39); base 85 drivers/watchdog/mpc8xxx_wdt.c u32 tmp = in_be32(&ddata->base->swcrr); base 94 drivers/watchdog/mpc8xxx_wdt.c out_be32(&ddata->base->swcrr, tmp); base 96 drivers/watchdog/mpc8xxx_wdt.c tmp = in_be32(&ddata->base->swcrr); base 148 drivers/watchdog/mpc8xxx_wdt.c ddata->base = devm_platform_ioremap_resource(ofdev, 0); base 149 drivers/watchdog/mpc8xxx_wdt.c if (IS_ERR(ddata->base)) base 150 drivers/watchdog/mpc8xxx_wdt.c return PTR_ERR(ddata->base); base 152 drivers/watchdog/mpc8xxx_wdt.c enabled = in_be32(&ddata->base->swcrr) & SWCRR_SWEN; base 30 drivers/watchdog/nv_tco.h #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */ base 31 drivers/watchdog/nv_tco.h #define TCO_TMR(base) ((base) + 0x01) /* TCO Timer Initial Value */ base 33 drivers/watchdog/nv_tco.h #define TCO_STS(base) ((base) + 0x04) /* TCO Status Register */ base 49 drivers/watchdog/nv_tco.h #define TCO_CNT(base) ((base) + 0x08) /* TCO Control Register */ base 59 drivers/watchdog/nv_tco.h #define MCP51_SMI_EN(base) ((base) - 0x40 + 0x04) base 41 drivers/watchdog/of_xilinx_wdt.c void __iomem *base; base 63 drivers/watchdog/of_xilinx_wdt.c control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); base 67 drivers/watchdog/of_xilinx_wdt.c xdev->base + XWT_TWCSR0_OFFSET); base 69 drivers/watchdog/of_xilinx_wdt.c iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET); base 83 drivers/watchdog/of_xilinx_wdt.c control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); base 86 drivers/watchdog/of_xilinx_wdt.c xdev->base + XWT_TWCSR0_OFFSET); base 88 drivers/watchdog/of_xilinx_wdt.c iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET); base 106 drivers/watchdog/of_xilinx_wdt.c control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); base 108 drivers/watchdog/of_xilinx_wdt.c iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET); base 137 drivers/watchdog/of_xilinx_wdt.c timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET); base 138 drivers/watchdog/of_xilinx_wdt.c timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); base 143 drivers/watchdog/of_xilinx_wdt.c timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); base 176 drivers/watchdog/of_xilinx_wdt.c xdev->base = devm_platform_ioremap_resource(pdev, 0); base 177 drivers/watchdog/of_xilinx_wdt.c if (IS_ERR(xdev->base)) base 178 drivers/watchdog/of_xilinx_wdt.c return PTR_ERR(xdev->base); base 247 drivers/watchdog/of_xilinx_wdt.c xdev->base, xilinx_wdt_wdd->timeout); base 64 drivers/watchdog/omap_wdt.c void __iomem *base; /* physical */ base 73 drivers/watchdog/omap_wdt.c void __iomem *base = wdev->base; base 76 drivers/watchdog/omap_wdt.c while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) base 80 drivers/watchdog/omap_wdt.c writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); base 83 drivers/watchdog/omap_wdt.c while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) base 90 drivers/watchdog/omap_wdt.c void __iomem *base = wdev->base; base 93 drivers/watchdog/omap_wdt.c writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR); base 94 drivers/watchdog/omap_wdt.c while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) base 97 drivers/watchdog/omap_wdt.c writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR); base 98 drivers/watchdog/omap_wdt.c while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) base 104 drivers/watchdog/omap_wdt.c void __iomem *base = wdev->base; base 107 drivers/watchdog/omap_wdt.c writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ base 108 drivers/watchdog/omap_wdt.c while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) base 111 drivers/watchdog/omap_wdt.c writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ base 112 drivers/watchdog/omap_wdt.c while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) base 120 drivers/watchdog/omap_wdt.c void __iomem *base = wdev->base; base 123 drivers/watchdog/omap_wdt.c while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) base 126 drivers/watchdog/omap_wdt.c writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR); base 127 drivers/watchdog/omap_wdt.c while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) base 134 drivers/watchdog/omap_wdt.c void __iomem *base = wdev->base; base 150 drivers/watchdog/omap_wdt.c while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) base 153 drivers/watchdog/omap_wdt.c writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); base 154 drivers/watchdog/omap_wdt.c while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) base 208 drivers/watchdog/omap_wdt.c void __iomem *base = wdev->base; base 211 drivers/watchdog/omap_wdt.c value = readl_relaxed(base + OMAP_WATCHDOG_CRR); base 245 drivers/watchdog/omap_wdt.c wdev->base = devm_platform_ioremap_resource(pdev, 0); base 246 drivers/watchdog/omap_wdt.c if (IS_ERR(wdev->base)) base 247 drivers/watchdog/omap_wdt.c return PTR_ERR(wdev->base); base 281 drivers/watchdog/omap_wdt.c readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, base 46 drivers/watchdog/qcom-wdt.c void __iomem *base; base 52 drivers/watchdog/qcom-wdt.c return wdt->base + wdt->layout[reg]; base 214 drivers/watchdog/qcom-wdt.c wdt->base = devm_ioremap_resource(dev, res); base 215 drivers/watchdog/qcom-wdt.c if (IS_ERR(wdt->base)) base 216 drivers/watchdog/qcom-wdt.c return PTR_ERR(wdt->base); base 49 drivers/watchdog/renesas_wdt.c void __iomem *base; base 62 drivers/watchdog/renesas_wdt.c writel_relaxed(val, priv->base + reg); base 91 drivers/watchdog/renesas_wdt.c val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME; base 100 drivers/watchdog/renesas_wdt.c while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG) base 123 drivers/watchdog/renesas_wdt.c u16 val = readw_relaxed(priv->base + RWTCNT); base 205 drivers/watchdog/renesas_wdt.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 206 drivers/watchdog/renesas_wdt.c if (IS_ERR(priv->base)) base 207 drivers/watchdog/renesas_wdt.c return PTR_ERR(priv->base); base 216 drivers/watchdog/renesas_wdt.c priv->wdev.bootstatus = (readb_relaxed(priv->base + RWTCSRA) & base 29 drivers/watchdog/rtd119x_wdt.c void __iomem *base; base 38 drivers/watchdog/rtd119x_wdt.c val = readl_relaxed(data->base + RTD119X_TCWCR); base 41 drivers/watchdog/rtd119x_wdt.c writel(val, data->base + RTD119X_TCWCR); base 51 drivers/watchdog/rtd119x_wdt.c val = readl_relaxed(data->base + RTD119X_TCWCR); base 54 drivers/watchdog/rtd119x_wdt.c writel(val, data->base + RTD119X_TCWCR); base 63 drivers/watchdog/rtd119x_wdt.c writel_relaxed(RTD119X_TCWTR_WDCLR, data->base + RTD119X_TCWTR); base 72 drivers/watchdog/rtd119x_wdt.c writel(val * clk_get_rate(data->clk), data->base + RTD119X_TCWOV); base 112 drivers/watchdog/rtd119x_wdt.c data->base = devm_platform_ioremap_resource(pdev, 0); base 113 drivers/watchdog/rtd119x_wdt.c if (IS_ERR(data->base)) base 114 drivers/watchdog/rtd119x_wdt.c return PTR_ERR(data->base); base 139 drivers/watchdog/rtd119x_wdt.c writel_relaxed(RTD119X_TCWTR_WDCLR, data->base + RTD119X_TCWTR); base 44 drivers/watchdog/rza_wdt.c void __iomem *base; base 79 drivers/watchdog/rza_wdt.c writew(WTCSR_MAGIC | 0, priv->base + WTCSR); base 82 drivers/watchdog/rza_wdt.c readb(priv->base + WRCSR); base 83 drivers/watchdog/rza_wdt.c writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR); base 87 drivers/watchdog/rza_wdt.c writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR); base 88 drivers/watchdog/rza_wdt.c writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT); base 90 drivers/watchdog/rza_wdt.c WTSCR_CKS(priv->cks), priv->base + WTCSR); base 99 drivers/watchdog/rza_wdt.c writew(WTCSR_MAGIC | 0, priv->base + WTCSR); base 108 drivers/watchdog/rza_wdt.c writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT); base 128 drivers/watchdog/rza_wdt.c writew(WTCSR_MAGIC | 0, priv->base + WTCSR); base 131 drivers/watchdog/rza_wdt.c readb(priv->base + WRCSR); base 132 drivers/watchdog/rza_wdt.c writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR); base 138 drivers/watchdog/rza_wdt.c writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR); base 139 drivers/watchdog/rza_wdt.c writew(WTCNT_MAGIC | 255, priv->base + WTCNT); base 140 drivers/watchdog/rza_wdt.c writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME, priv->base + WTCSR); base 178 drivers/watchdog/rza_wdt.c priv->base = devm_platform_ioremap_resource(pdev, 0); base 179 drivers/watchdog/rza_wdt.c if (IS_ERR(priv->base)) base 180 drivers/watchdog/rza_wdt.c return PTR_ERR(priv->base); base 73 drivers/watchdog/shwdt.c void __iomem *base; base 243 drivers/watchdog/shwdt.c wdt->base = devm_platform_ioremap_resource(pdev, 0); base 244 drivers/watchdog/shwdt.c if (IS_ERR(wdt->base)) base 245 drivers/watchdog/shwdt.c return PTR_ERR(wdt->base); base 150 drivers/watchdog/sirfsoc_wdt.c void __iomem *base; base 152 drivers/watchdog/sirfsoc_wdt.c base = devm_platform_ioremap_resource(pdev, 0); base 153 drivers/watchdog/sirfsoc_wdt.c if (IS_ERR(base)) base 154 drivers/watchdog/sirfsoc_wdt.c return PTR_ERR(base); base 156 drivers/watchdog/sirfsoc_wdt.c watchdog_set_drvdata(&sirfsoc_wdd, (__force void *)base); base 16 drivers/watchdog/sp5100_tco.h #define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */ base 17 drivers/watchdog/sp5100_tco.h #define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */ base 69 drivers/watchdog/sp805_wdt.c void __iomem *base; base 85 drivers/watchdog/sp805_wdt.c u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL); base 125 drivers/watchdog/sp805_wdt.c load = readl_relaxed(wdt->base + WDTVALUE); base 128 drivers/watchdog/sp805_wdt.c if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK)) base 140 drivers/watchdog/sp805_wdt.c writel_relaxed(UNLOCK, wdt->base + WDTLOCK); base 141 drivers/watchdog/sp805_wdt.c writel_relaxed(0, wdt->base + WDTCONTROL); base 142 drivers/watchdog/sp805_wdt.c writel_relaxed(0, wdt->base + WDTLOAD); base 143 drivers/watchdog/sp805_wdt.c writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL); base 146 drivers/watchdog/sp805_wdt.c readl_relaxed(wdt->base + WDTLOCK); base 167 drivers/watchdog/sp805_wdt.c writel_relaxed(UNLOCK, wdt->base + WDTLOCK); base 168 drivers/watchdog/sp805_wdt.c writel_relaxed(wdt->load_val, wdt->base + WDTLOAD); base 169 drivers/watchdog/sp805_wdt.c writel_relaxed(INT_MASK, wdt->base + WDTINTCLR); base 172 drivers/watchdog/sp805_wdt.c writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + base 175 drivers/watchdog/sp805_wdt.c writel_relaxed(LOCK, wdt->base + WDTLOCK); base 178 drivers/watchdog/sp805_wdt.c readl_relaxed(wdt->base + WDTLOCK); base 202 drivers/watchdog/sp805_wdt.c writel_relaxed(UNLOCK, wdt->base + WDTLOCK); base 203 drivers/watchdog/sp805_wdt.c writel_relaxed(0, wdt->base + WDTCONTROL); base 204 drivers/watchdog/sp805_wdt.c writel_relaxed(LOCK, wdt->base + WDTLOCK); base 207 drivers/watchdog/sp805_wdt.c readl_relaxed(wdt->base + WDTLOCK); base 242 drivers/watchdog/sp805_wdt.c wdt->base = devm_ioremap_resource(&adev->dev, &adev->res); base 243 drivers/watchdog/sp805_wdt.c if (IS_ERR(wdt->base)) base 244 drivers/watchdog/sp805_wdt.c return PTR_ERR(wdt->base); base 59 drivers/watchdog/sprd_wdt.c void __iomem *base; base 85 drivers/watchdog/sprd_wdt.c sprd_wdt_unlock(wdt->base); base 86 drivers/watchdog/sprd_wdt.c writel_relaxed(SPRD_WDT_INT_CLEAR_BIT, wdt->base + SPRD_WDT_INT_CLR); base 87 drivers/watchdog/sprd_wdt.c sprd_wdt_lock(wdt->base); base 96 drivers/watchdog/sprd_wdt.c val = readl_relaxed(wdt->base + SPRD_WDT_CNT_HIGH) << base 98 drivers/watchdog/sprd_wdt.c val |= readl_relaxed(wdt->base + SPRD_WDT_CNT_LOW) & base 111 drivers/watchdog/sprd_wdt.c sprd_wdt_unlock(wdt->base); base 113 drivers/watchdog/sprd_wdt.c SPRD_WDT_LOW_VALUE_MASK, wdt->base + SPRD_WDT_LOAD_HIGH); base 115 drivers/watchdog/sprd_wdt.c wdt->base + SPRD_WDT_LOAD_LOW); base 118 drivers/watchdog/sprd_wdt.c wdt->base + SPRD_WDT_IRQ_LOAD_HIGH); base 120 drivers/watchdog/sprd_wdt.c wdt->base + SPRD_WDT_IRQ_LOAD_LOW); base 121 drivers/watchdog/sprd_wdt.c sprd_wdt_lock(wdt->base); base 128 drivers/watchdog/sprd_wdt.c val = readl_relaxed(wdt->base + SPRD_WDT_INT_RAW); base 154 drivers/watchdog/sprd_wdt.c sprd_wdt_unlock(wdt->base); base 155 drivers/watchdog/sprd_wdt.c val = readl_relaxed(wdt->base + SPRD_WDT_CTRL); base 157 drivers/watchdog/sprd_wdt.c writel_relaxed(val, wdt->base + SPRD_WDT_CTRL); base 158 drivers/watchdog/sprd_wdt.c sprd_wdt_lock(wdt->base); base 166 drivers/watchdog/sprd_wdt.c sprd_wdt_unlock(wdt->base); base 167 drivers/watchdog/sprd_wdt.c writel_relaxed(0x0, wdt->base + SPRD_WDT_CTRL); base 168 drivers/watchdog/sprd_wdt.c sprd_wdt_lock(wdt->base); base 184 drivers/watchdog/sprd_wdt.c sprd_wdt_unlock(wdt->base); base 185 drivers/watchdog/sprd_wdt.c val = readl_relaxed(wdt->base + SPRD_WDT_CTRL); base 187 drivers/watchdog/sprd_wdt.c writel_relaxed(val, wdt->base + SPRD_WDT_CTRL); base 188 drivers/watchdog/sprd_wdt.c sprd_wdt_lock(wdt->base); base 199 drivers/watchdog/sprd_wdt.c sprd_wdt_unlock(wdt->base); base 200 drivers/watchdog/sprd_wdt.c val = readl_relaxed(wdt->base + SPRD_WDT_CTRL); base 203 drivers/watchdog/sprd_wdt.c writel_relaxed(val, wdt->base + SPRD_WDT_CTRL); base 204 drivers/watchdog/sprd_wdt.c sprd_wdt_lock(wdt->base); base 270 drivers/watchdog/sprd_wdt.c wdt->base = devm_platform_ioremap_resource(pdev, 0); base 271 drivers/watchdog/sprd_wdt.c if (IS_ERR(wdt->base)) base 272 drivers/watchdog/sprd_wdt.c return PTR_ERR(wdt->base); base 42 drivers/watchdog/st_lpc_wdt.c void __iomem *base; base 85 drivers/watchdog/st_lpc_wdt.c writel_relaxed(timeout * clkrate, st_wdog->base + LPC_LPA_LSB_OFF); base 86 drivers/watchdog/st_lpc_wdt.c writel_relaxed(1, st_wdog->base + LPC_LPA_START_OFF); base 93 drivers/watchdog/st_lpc_wdt.c writel_relaxed(1, st_wdog->base + LPC_WDT_OFF); base 102 drivers/watchdog/st_lpc_wdt.c writel_relaxed(0, st_wdog->base + LPC_WDT_OFF); base 158 drivers/watchdog/st_lpc_wdt.c void __iomem *base; base 183 drivers/watchdog/st_lpc_wdt.c base = devm_platform_ioremap_resource(pdev, 0); base 184 drivers/watchdog/st_lpc_wdt.c if (IS_ERR(base)) base 185 drivers/watchdog/st_lpc_wdt.c return PTR_ERR(base); base 200 drivers/watchdog/st_lpc_wdt.c st_wdog->base = base; base 77 drivers/watchdog/stm32_iwdg.c static inline u32 reg_read(void __iomem *base, u32 reg) base 79 drivers/watchdog/stm32_iwdg.c return readl_relaxed(base + reg); base 82 drivers/watchdog/stm32_iwdg.c static inline void reg_write(void __iomem *base, u32 reg, u32 val) base 84 drivers/watchdog/stm32_iwdg.c writel_relaxed(val, base + reg); base 42 drivers/watchdog/tangox_wdt.c void __iomem *base; base 61 drivers/watchdog/tangox_wdt.c writel(ticks, dev->base + WD_COUNTER); base 70 drivers/watchdog/tangox_wdt.c writel(0, dev->base + WD_COUNTER); base 80 drivers/watchdog/tangox_wdt.c count = readl(dev->base + WD_COUNTER); base 98 drivers/watchdog/tangox_wdt.c writel(1, dev->base + WD_COUNTER); base 126 drivers/watchdog/tangox_wdt.c dev->base = devm_platform_ioremap_resource(pdev, 0); base 127 drivers/watchdog/tangox_wdt.c if (IS_ERR(dev->base)) base 128 drivers/watchdog/tangox_wdt.c return PTR_ERR(dev->base); base 161 drivers/watchdog/tangox_wdt.c config = readl(dev->base + WD_CONFIG); base 163 drivers/watchdog/tangox_wdt.c writel(0, dev->base + WD_COUNTER); base 165 drivers/watchdog/tangox_wdt.c writel(WD_CONFIG_XTAL_IN, dev->base + WD_CONFIG); base 171 drivers/watchdog/tangox_wdt.c if (readl(dev->base + WD_COUNTER)) { base 1318 drivers/xen/grant-table.c uint32_t base, width; base 1321 drivers/xen/grant-table.c base = xen_cpuid_base(); base 1322 drivers/xen/grant-table.c if (cpuid_eax(base) < 5) base 1324 drivers/xen/grant-table.c width = cpuid_ebx(base + 5) & base 345 drivers/xen/xenbus/xenbus_comms.c void *base; base 366 drivers/xen/xenbus/xenbus_comms.c base = &state.req->msg; base 369 drivers/xen/xenbus/xenbus_comms.c base = state.req->vec[state.idx].iov_base; base 372 drivers/xen/xenbus/xenbus_comms.c err = xb_write(base + state.written, len - state.written); base 729 drivers/xen/xenbus/xenbus_xs.c uint32_t eax, ebx, ecx, edx, base; base 731 drivers/xen/xenbus/xenbus_xs.c base = xen_cpuid_base(); base 732 drivers/xen/xenbus/xenbus_xs.c cpuid(base + 1, &eax, &ebx, &ecx, &edx); base 922 fs/binfmt_elf_fdpic.c unsigned long load_addr, base = ULONG_MAX, top = 0, maddr = 0, mflags; base 935 fs/binfmt_elf_fdpic.c if (base > phdr->p_vaddr) base 936 fs/binfmt_elf_fdpic.c base = phdr->p_vaddr; base 946 fs/binfmt_elf_fdpic.c maddr = vm_mmap(NULL, load_addr, top - base, base 952 fs/binfmt_elf_fdpic.c load_addr += PAGE_ALIGN(top - base); base 960 fs/binfmt_elf_fdpic.c seg->addr = maddr + (phdr->p_vaddr - base); base 3046 fs/btrfs/scrub.c int num, u64 base, u64 length) base 3132 fs/btrfs/scrub.c logical = base + offset; base 3137 fs/btrfs/scrub.c logic_end += base; base 3207 fs/btrfs/scrub.c logical += base; base 3210 fs/btrfs/scrub.c stripe_logical += base; base 3358 fs/btrfs/scrub.c logical += base; base 3361 fs/btrfs/scrub.c stripe_logical += base; base 1092 fs/btrfs/tree-log.c unsigned long base; base 1098 fs/btrfs/tree-log.c base = btrfs_item_ptr_offset(leaf, path->slots[0]); base 1101 fs/btrfs/tree-log.c extref = (struct btrfs_inode_extref *)(base + cur_offset); base 2136 fs/ceph/mds_client.c u64 base; base 2185 fs/ceph/mds_client.c base = ceph_ino(d_inode(temp)); base 2197 fs/ceph/mds_client.c *pbase = base; base 2200 fs/ceph/mds_client.c dentry, d_count(dentry), base, *plen, path + pos); base 505 fs/ceph/mds_client.h extern char *ceph_mdsc_build_path(struct dentry *dentry, int *plen, u64 *base, base 132 fs/compat_ioctl.c u32 base, len; base 134 fs/compat_ioctl.c if (get_user(base, &iov32[i].iov_base) || base 136 fs/compat_ioctl.c put_user(compat_ptr(base), &iov[i].iov_base) || base 100 fs/crypto/keysetup.c crypto_skcipher_alg(tfm)->base.cra_driver_name); base 1083 fs/debugfs/file.c int nregs, void __iomem *base, char *prefix) base 1091 fs/debugfs/file.c readl(base + regs->offset)); base 1102 fs/debugfs/file.c debugfs_print_regs32(s, regset->regs, regset->nregs, regset->base, ""); base 68 fs/dlm/lowcomms.c unsigned int base; base 80 fs/dlm/lowcomms.c return ((cb->base + cb->len) & cb->mask); base 85 fs/dlm/lowcomms.c cb->base = cb->len = 0; base 92 fs/dlm/lowcomms.c cb->base += n; base 93 fs/dlm/lowcomms.c cb->base &= cb->mask; base 659 fs/dlm/lowcomms.c iov[0].iov_len = con->cb.base - cbuf_data(&con->cb); base 668 fs/dlm/lowcomms.c if (cbuf_data(&con->cb) >= con->cb.base) { base 670 fs/dlm/lowcomms.c iov[1].iov_len = con->cb.base; base 686 fs/dlm/lowcomms.c con->cb.base, con->cb.len, base 690 fs/dlm/lowcomms.c page_address(con->rx_page), con->cb.base, base 32 fs/dlm/midcomms.c static void copy_from_cb(void *dst, const void *base, unsigned offset, base 39 fs/dlm/midcomms.c memcpy(dst, base + offset, copy); base 42 fs/dlm/midcomms.c memcpy(dst + copy, base, len); base 56 fs/dlm/midcomms.c int dlm_process_incoming_buffer(int nodeid, const void *base, base 76 fs/dlm/midcomms.c copy_from_cb(p, base, offset, sizeof(struct dlm_header), base 118 fs/dlm/midcomms.c copy_from_cb(p, base, offset, msglen, limit); base 15 fs/dlm/midcomms.h int dlm_process_incoming_buffer(int nodeid, const void *base, unsigned offset, base 357 fs/ecryptfs/crypto.c struct extent_crypt_result *ecr = req->base.data; base 202 fs/erofs/zmap.c unsigned int vcnt, base, lo, encodebits, nblk; base 214 fs/erofs/zmap.c base = round_down(eofs, vcnt << amortizedshift); base 215 fs/erofs/zmap.c in = m->kaddr + base; base 217 fs/erofs/zmap.c i = (eofs - base) >> amortizedshift; base 236 fs/eventpoll.c struct epitem *base; base 348 fs/eventpoll.c return container_of(p, struct eppoll_entry, wait)->base; base 1325 fs/eventpoll.c pwq->base = epi; base 243 fs/ext2/dir.c ext2_validate_entry(char *base, unsigned offset, unsigned mask) base 245 fs/ext2/dir.c ext2_dirent *de = (ext2_dirent*)(base + offset); base 246 fs/ext2/dir.c ext2_dirent *p = (ext2_dirent*)(base + (offset&mask)); base 252 fs/ext2/dir.c return (char *)p - base; base 282 fs/ext4/namei.c static struct ext4_dir_entry_2* dx_pack_dirents(char *base, unsigned blocksize); base 620 fs/ext4/namei.c char *base = (char *) de; base 624 fs/ext4/namei.c while ((char *) de < base + size) base 652 fs/ext4/namei.c - base)); base 684 fs/ext4/namei.c - base)); base 693 fs/ext4/namei.c (unsigned) ((char *) de - base)); base 1213 fs/ext4/namei.c char *base = (char *) de; base 1216 fs/ext4/namei.c while ((char *) de < base + blocksize) { base 1221 fs/ext4/namei.c map_tail->offs = ((char *) de - base)>>2; base 1785 fs/ext4/namei.c static struct ext4_dir_entry_2* dx_pack_dirents(char *base, unsigned blocksize) base 1787 fs/ext4/namei.c struct ext4_dir_entry_2 *next, *to, *prev, *de = (struct ext4_dir_entry_2 *) base; base 1791 fs/ext4/namei.c while ((char*)de < base + blocksize) { base 1325 fs/ext4/xattr.c size_t *min_offs, void *base, int *total) base 1336 fs/ext4/xattr.c return (*min_offs - ((void *)last - base) - sizeof(__u32)); base 1567 fs/ext4/xattr.c size_t min_offs = s->end - s->base, name_len = strlen(i->name); base 1585 fs/ext4/xattr.c void *val = s->base + offs; base 1618 fs/ext4/xattr.c free = min_offs - ((void *)last - s->base) - sizeof(__u32); base 1701 fs/ext4/xattr.c void *first_val = s->base + min_offs; base 1703 fs/ext4/xattr.c void *val = s->base + offs; base 1751 fs/ext4/xattr.c void *val = s->base + min_offs - new_size; base 1785 fs/ext4/xattr.c __le32 *value = s->base + le16_to_cpu( base 1796 fs/ext4/xattr.c ext4_xattr_rehash((struct ext4_xattr_header *)s->base); base 1832 fs/ext4/xattr.c bs->s.base = BHDR(bs->bh); base 1864 fs/ext4/xattr.c if (s->base) { base 1871 fs/ext4/xattr.c if (header(s->base)->h_refcount == cpu_to_le32(1)) { base 1901 fs/ext4/xattr.c s->base = kmalloc(bs->bh->b_size, GFP_NOFS); base 1903 fs/ext4/xattr.c if (s->base == NULL) base 1905 fs/ext4/xattr.c memcpy(s->base, BHDR(bs->bh), bs->bh->b_size); base 1906 fs/ext4/xattr.c s->first = ENTRY(header(s->base)+1); base 1907 fs/ext4/xattr.c header(s->base)->h_refcount = cpu_to_le32(1); base 1908 fs/ext4/xattr.c s->here = ENTRY(s->base + offset); base 1909 fs/ext4/xattr.c s->end = s->base + bs->bh->b_size; base 1943 fs/ext4/xattr.c s->base = kzalloc(sb->s_blocksize, GFP_NOFS); base 1946 fs/ext4/xattr.c if (s->base == NULL) base 1948 fs/ext4/xattr.c header(s->base)->h_magic = cpu_to_le32(EXT4_XATTR_MAGIC); base 1949 fs/ext4/xattr.c header(s->base)->h_blocks = cpu_to_le32(1); base 1950 fs/ext4/xattr.c header(s->base)->h_refcount = cpu_to_le32(1); base 1951 fs/ext4/xattr.c s->first = ENTRY(header(s->base)+1); base 1952 fs/ext4/xattr.c s->here = ENTRY(header(s->base)+1); base 1953 fs/ext4/xattr.c s->end = s->base + sb->s_blocksize; base 1981 fs/ext4/xattr.c new_bh = ext4_xattr_block_cache_find(inode, header(s->base), base 2049 fs/ext4/xattr.c } else if (bs->bh && s->base == bs->bh->b_data) { base 2088 fs/ext4/xattr.c ENTRY(header(s->base)+1)); base 2110 fs/ext4/xattr.c memcpy(new_bh->b_data, s->base, new_bh->b_size); base 2157 fs/ext4/xattr.c if (!(bs->bh && s->base == bs->bh->b_data)) base 2158 fs/ext4/xattr.c kfree(s->base); base 2185 fs/ext4/xattr.c is->s.base = is->s.first = IFIRST(header); base 2260 fs/ext4/xattr.c value = ((void *)s->base) + le16_to_cpu(s->here->e_value_offs); base 2397 fs/ext4/xattr.c if (EXT4_I(inode)->i_file_acl && !bs.s.base) { base 2706 fs/ext4/xattr.c void *base, *end; base 2723 fs/ext4/xattr.c base = IFIRST(header); base 2725 fs/ext4/xattr.c min_offs = end - base; base 2732 fs/ext4/xattr.c ifree = ext4_xattr_free_space(base, &min_offs, base, &total_ino); base 2753 fs/ext4/xattr.c base = BHDR(bh); base 2755 fs/ext4/xattr.c min_offs = end - base; base 2756 fs/ext4/xattr.c bfree = ext4_xattr_free_space(BFIRST(bh), &min_offs, base, base 108 fs/ext4/xattr.h void *base; base 740 fs/f2fs/data.c int base = 0; base 743 fs/f2fs/data.c base = get_extra_isize(dn->inode); base 747 fs/f2fs/data.c addr_array[base + dn->ofs_in_node] = cpu_to_le32(dn->data_blkaddr); base 2291 fs/f2fs/f2fs.h int base = 0; base 2299 fs/f2fs/f2fs.h base = offset_in_addr(&raw_node->i); base 2301 fs/f2fs/f2fs.h base = get_extra_isize(inode); base 2305 fs/f2fs/f2fs.h return le32_to_cpu(addr_array[base + offset]); base 521 fs/f2fs/file.c int base = 0; base 524 fs/f2fs/file.c base = get_extra_isize(dn->inode); base 527 fs/f2fs/file.c addr = blkaddr_in_node(raw_node) + base + ofs; base 613 fs/f2fs/node.c pgoff_t base = 0; base 623 fs/f2fs/node.c base += 2 * indirect_blks; base 626 fs/f2fs/node.c base += 2 * direct_blks; base 629 fs/f2fs/node.c base += direct_index; base 635 fs/f2fs/node.c return ((pgofs - base) / skipped_unit + 1) * skipped_unit + base; base 795 fs/f2fs/segment.h static inline block_t sum_blk_addr(struct f2fs_sb_info *sbi, int base, int type) base 799 fs/f2fs/segment.h - (base + 1) + type; base 333 fs/fat/namei_vfat.c unsigned char base[9], ext[4], buf[5], *p; base 382 fs/fat/namei_vfat.c for (baselen = i = 0, p = base, ip = uname; i < sz; i++, ip++) { base 432 fs/fat/namei_vfat.c base[baselen] = '\0'; base 435 fs/fat/namei_vfat.c if (base[0] == DELETED_FLAG) base 436 fs/fat/namei_vfat.c base[0] = 0x05; base 444 fs/fat/namei_vfat.c memcpy(name_res, base, baselen); base 241 fs/file_table.c struct file *alloc_file_clone(struct file *base, int flags, base 244 fs/file_table.c struct file *f = alloc_file(&base->f_path, flags, fops); base 247 fs/file_table.c f->f_mapping = base->f_mapping; base 2645 fs/fuse/file.c if (fiov[i].base != (unsigned long) fiov[i].base || base 2649 fs/fuse/file.c dst[i].iov_base = (void __user *) (unsigned long) fiov[i].base; base 2654 fs/fuse/file.c (ptr_to_compat(dst[i].iov_base) != fiov[i].base || base 406 fs/hostfs/hostfs_kern.c loff_t base = page_offset(page); base 416 fs/hostfs/hostfs_kern.c err = write_file(HOSTFS_I(inode)->fd, &base, buffer, count); base 422 fs/hostfs/hostfs_kern.c if (base > inode->i_size) base 423 fs/hostfs/hostfs_kern.c inode->i_size = base; base 122 fs/jffs2/nodelist.c static void jffs2_fragtree_insert(struct jffs2_node_frag *newfrag, struct jffs2_node_frag *base) base 124 fs/jffs2/nodelist.c struct rb_node *parent = &base->rb; base 131 fs/jffs2/nodelist.c base = rb_entry(parent, struct jffs2_node_frag, rb); base 133 fs/jffs2/nodelist.c if (newfrag->ofs > base->ofs) base 134 fs/jffs2/nodelist.c link = &base->rb.rb_right; base 135 fs/jffs2/nodelist.c else if (newfrag->ofs < base->ofs) base 136 fs/jffs2/nodelist.c link = &base->rb.rb_left; base 138 fs/jffs2/nodelist.c JFFS2_ERROR("duplicate frag at %08x (%p,%p)\n", newfrag->ofs, newfrag, base); base 143 fs/jffs2/nodelist.c rb_link_node(&newfrag->rb, &base->rb, link); base 57 fs/jfs/jfs_debug.c struct proc_dir_entry *base; base 59 fs/jfs/jfs_debug.c base = proc_mkdir("fs/jfs", NULL); base 60 fs/jfs/jfs_debug.c if (!base) base 64 fs/jfs/jfs_debug.c proc_create_single("lmstats", 0, base, jfs_lmstats_proc_show); base 65 fs/jfs/jfs_debug.c proc_create_single("txstats", 0, base, jfs_txstats_proc_show); base 66 fs/jfs/jfs_debug.c proc_create_single("xtstat", 0, base, jfs_xtstat_proc_show); base 67 fs/jfs/jfs_debug.c proc_create_single("mpstat", 0, base, jfs_mpstat_proc_show); base 70 fs/jfs/jfs_debug.c proc_create_single("TxAnchor", 0, base, jfs_txanchor_proc_show); base 71 fs/jfs/jfs_debug.c proc_create("loglevel", 0, base, &jfs_loglevel_proc_fops); base 576 fs/jfs/jfs_dtree.c int base, index, lim; base 633 fs/jfs/jfs_dtree.c for (base = 0, lim = p->header.nextindex; lim; lim >>= 1) { base 634 fs/jfs/jfs_dtree.c index = base + (lim >> 1); base 708 fs/jfs/jfs_dtree.c base = index + 1; base 743 fs/jfs/jfs_dtree.c btsp->index = base; base 756 fs/jfs/jfs_dtree.c index = base ? base - 1 : base; base 1174 fs/jfs/jfs_logmgr.c log->base = addressPXD(&JFS_SBI(sb)->logpxd); base 1210 fs/jfs/jfs_logmgr.c dummy_log->base = 0; base 1323 fs/jfs/jfs_logmgr.c log, (unsigned long long)log->base, log->size); base 1332 fs/jfs/jfs_logmgr.c log, (unsigned long long)log->base, log->size); base 1902 fs/jfs/jfs_logmgr.c bp->l_blkno = log->base + (pn << (L2LOGPSIZE - log->l2bsize)); base 2032 fs/jfs/jfs_logmgr.c log->base + (bp->l_pn << (L2LOGPSIZE - log->l2bsize)); base 2102 fs/jfs/jfs_logmgr.c log->base + (bp->l_pn << (L2LOGPSIZE - log->l2bsize)); base 362 fs/jfs/jfs_logmgr.h s64 base; /* @8: log extent address (inline log ) */ base 236 fs/jfs/jfs_xtree.c int base, index, lim, btindex; base 368 fs/jfs/jfs_xtree.c for (base = XTENTRYSTART; lim; lim >>= 1) { base 369 fs/jfs/jfs_xtree.c index = base + (lim >> 1); base 418 fs/jfs/jfs_xtree.c base = index + 1; base 429 fs/jfs/jfs_xtree.c if (base < le16_to_cpu(p->header.nextindex)) base 430 fs/jfs/jfs_xtree.c next = offsetXAD(&p->xad[base]); base 453 fs/jfs/jfs_xtree.c btsp->index = base; base 458 fs/jfs/jfs_xtree.c if (base == btindex || base == btindex + 1) base 462 fs/jfs/jfs_xtree.c jfs_ip->btindex = base; base 476 fs/jfs/jfs_xtree.c index = base ? base - 1 : base; base 2888 fs/jfs/jfs_xtree.c int base, index, lim; base 2929 fs/jfs/jfs_xtree.c for (base = XTENTRYSTART; lim; lim >>= 1) { base 2930 fs/jfs/jfs_xtree.c index = base + (lim >> 1); base 2957 fs/jfs/jfs_xtree.c base = index + 1; base 2970 fs/jfs/jfs_xtree.c index = base ? base - 1 : base; base 254 fs/jfs/resize.c log->base = newLogAddress; base 60 fs/kernfs/symlink.c struct kernfs_node *base, *kn; base 65 fs/kernfs/symlink.c base = parent; base 66 fs/kernfs/symlink.c while (base->parent) { base 68 fs/kernfs/symlink.c while (kn->parent && base != kn) base 71 fs/kernfs/symlink.c if (base == kn) base 79 fs/kernfs/symlink.c base = base->parent; base 84 fs/kernfs/symlink.c while (kn->parent && kn != base) { base 98 fs/kernfs/symlink.c while (kn->parent && kn != base) { base 1522 fs/namei.c struct dentry *base, unsigned int flags) base 1524 fs/namei.c struct dentry *dentry = lookup_dcache(name, base, flags); base 1526 fs/namei.c struct inode *dir = base->d_inode; base 1535 fs/namei.c dentry = d_alloc(base, name); base 2449 fs/namei.c static int lookup_one_len_common(const char *name, struct dentry *base, base 2454 fs/namei.c this->hash = full_name_hash(base, name, len); base 2472 fs/namei.c if (base->d_flags & DCACHE_OP_HASH) { base 2473 fs/namei.c int err = base->d_op->d_hash(base, this); base 2478 fs/namei.c return inode_permission(base->d_inode, MAY_EXEC); base 2495 fs/namei.c struct dentry *try_lookup_one_len(const char *name, struct dentry *base, int len) base 2500 fs/namei.c WARN_ON_ONCE(!inode_is_locked(base->d_inode)); base 2502 fs/namei.c err = lookup_one_len_common(name, base, len, &this); base 2506 fs/namei.c return lookup_dcache(&this, base, 0); base 2521 fs/namei.c struct dentry *lookup_one_len(const char *name, struct dentry *base, int len) base 2527 fs/namei.c WARN_ON_ONCE(!inode_is_locked(base->d_inode)); base 2529 fs/namei.c err = lookup_one_len_common(name, base, len, &this); base 2533 fs/namei.c dentry = lookup_dcache(&this, base, 0); base 2534 fs/namei.c return dentry ? dentry : __lookup_slow(&this, base, 0); base 2551 fs/namei.c struct dentry *base, int len) base 2557 fs/namei.c err = lookup_one_len_common(name, base, len, &this); base 2561 fs/namei.c ret = lookup_dcache(&this, base, 0); base 2563 fs/namei.c ret = lookup_slow(&this, base, 0); base 702 fs/nfs/internal.h unsigned int nfs_page_array_len(unsigned int base, size_t len) base 704 fs/nfs/internal.h return ((unsigned long)len + (unsigned long)base + base 57 fs/nfs/namespace.c const char *base; base 94 fs/nfs/namespace.c base = dentry->d_fsdata; base 95 fs/nfs/namespace.c if (!base) { base 101 fs/nfs/namespace.c namelen = strlen(base); base 104 fs/nfs/namespace.c while (namelen > 0 && base[namelen - 1] == '/') base 114 fs/nfs/namespace.c memcpy(end, base, namelen); base 1345 fs/nfs/nfs3xdr.c unsigned int base; base 1351 fs/nfs/nfs3xdr.c base = req->rq_slen; base 1357 fs/nfs/nfs3xdr.c error = nfsacl_encode(xdr->buf, base, args->inode, base 1362 fs/nfs/nfs3xdr.c error = nfsacl_encode(xdr->buf, base + error, args->inode, base 92 fs/nfs_common/nfsacl.c int nfsacl_encode(struct xdr_buf *buf, unsigned int base, struct inode *inode, base 111 fs/nfs_common/nfsacl.c xdr_encode_word(buf, base, entries)) base 131 fs/nfs_common/nfsacl.c err = xdr_encode_array2(buf, base + 4, &nfsacl_desc.desc); base 265 fs/nfs_common/nfsacl.c int nfsacl_decode(struct xdr_buf *buf, unsigned int base, unsigned int *aclcnt, base 277 fs/nfs_common/nfsacl.c if (xdr_decode_word(buf, base, &entries) || base 281 fs/nfs_common/nfsacl.c err = xdr_decode_array2(buf, base + 4, &nfsacl_desc.desc); base 203 fs/nfsd/nfs2acl.c unsigned int base; base 214 fs/nfsd/nfs2acl.c base = (char *)p - (char *)head->iov_base; base 215 fs/nfsd/nfs2acl.c n = nfsacl_decode(&rqstp->rq_arg, base, NULL, base 219 fs/nfsd/nfs2acl.c n = nfsacl_decode(&rqstp->rq_arg, base + n, NULL, base 267 fs/nfsd/nfs2acl.c unsigned int base; base 284 fs/nfsd/nfs2acl.c base = (char *)p - (char *)head->iov_base; base 295 fs/nfsd/nfs2acl.c n = nfsacl_encode(&rqstp->rq_res, base, inode, base 299 fs/nfsd/nfs2acl.c n = nfsacl_encode(&rqstp->rq_res, base + n, inode, base 145 fs/nfsd/nfs3acl.c unsigned int base; base 156 fs/nfsd/nfs3acl.c base = (char *)p - (char *)head->iov_base; base 157 fs/nfsd/nfs3acl.c n = nfsacl_decode(&rqstp->rq_arg, base, NULL, base 161 fs/nfsd/nfs3acl.c n = nfsacl_decode(&rqstp->rq_arg, base + n, NULL, base 181 fs/nfsd/nfs3acl.c unsigned int base; base 188 fs/nfsd/nfs3acl.c base = (char *)p - (char *)head->iov_base; base 199 fs/nfsd/nfs3acl.c n = nfsacl_encode(&rqstp->rq_res, base, inode, base 203 fs/nfsd/nfs3acl.c n = nfsacl_encode(&rqstp->rq_res, base + n, inode, base 490 fs/nfsd/nfs3xdr.c char *base = (char *)p; base 502 fs/nfsd/nfs3xdr.c args->first.iov_len -= (char *)p - base; base 2809 fs/nfsd/nfs4state.c unsigned int base; base 2825 fs/nfsd/nfs4state.c base = resp->cstate.data_offset; base 2826 fs/nfsd/nfs4state.c slot->sl_datalen = buf->len - base; base 2827 fs/nfsd/nfs4state.c if (read_bytes_from_xdr_buf(buf, base, slot->sl_data, slot->sl_datalen)) base 295 fs/nfsd/nfscache.c unsigned int base; base 309 fs/nfsd/nfscache.c base = buf->page_base & ~PAGE_MASK; base 311 fs/nfsd/nfscache.c p = page_address(buf->pages[idx]) + base; base 312 fs/nfsd/nfscache.c len = min_t(size_t, PAGE_SIZE - base, csum_len); base 315 fs/nfsd/nfscache.c base = 0; base 372 fs/nfsd/nfsxdr.c char *base = (char *)p; base 385 fs/nfsd/nfsxdr.c args->first.iov_len -= (char *)p - base; base 53 fs/nilfs2/ioctl.c void __user *base = (void __user *)(unsigned long)argv->v_base; base 85 fs/nilfs2/ioctl.c copy_from_user(buf, base + argv->v_size * i, base 98 fs/nilfs2/ioctl.c copy_to_user(base + argv->v_size * i, buf, base 870 fs/nilfs2/ioctl.c void __user *base; base 919 fs/nilfs2/ioctl.c base = (void __user *)(unsigned long)argv[n].v_base; base 930 fs/nilfs2/ioctl.c if (copy_from_user(kbufs[n], base, len)) { base 1222 fs/nilfs2/ioctl.c void __user *base; base 1253 fs/nilfs2/ioctl.c base = (void __user *)(unsigned long)argv.v_base; base 1260 fs/nilfs2/ioctl.c if (copy_from_user(kbuf, base, len)) { base 20 fs/ntfs/runlist.c static inline void ntfs_rl_mm(runlist_element *base, int dst, int src, base 24 fs/ntfs/runlist.c memmove(base + dst, base + src, size * sizeof(*base)); base 128 fs/ocfs2/xattr.c void *base; base 1089 fs/ocfs2/xattr.c cmp = memcmp(name, (xs->base + base 1172 fs/ocfs2/xattr.c xs->base = (void *)xs->header; base 1183 fs/ocfs2/xattr.c memcpy(buffer, (void *)xs->base + base 1188 fs/ocfs2/xattr.c (xs->base + le16_to_cpu( base 1255 fs/ocfs2/xattr.c xs->base = bucket_block(xs->bucket, block_off); base 1258 fs/ocfs2/xattr.c memcpy(buffer, (void *)xs->base + base 1262 fs/ocfs2/xattr.c (xs->base + name_offset + name_len); base 2702 fs/ocfs2/xattr.c xs->base = (void *)xs->header; base 2838 fs/ocfs2/xattr.c xs->base = (void *)xs->header; base 2973 fs/ocfs2/xattr.c xs->base = (void *)xs->header; base 3009 fs/ocfs2/xattr.c size_t min_offs = xs->end - xs->base; base 3023 fs/ocfs2/xattr.c free = min_offs - ((void *)last - xs->base) - OCFS2_XATTR_HEADER_GAP; base 3050 fs/ocfs2/xattr.c char *base = NULL; base 3081 fs/ocfs2/xattr.c base = xis->base; base 3097 fs/ocfs2/xattr.c base = bucket_block(xbs->bucket, block_off); base 3100 fs/ocfs2/xattr.c base = xbs->base; base 3149 fs/ocfs2/xattr.c (base + name_offset + name_len); base 3906 fs/ocfs2/xattr.c xs->base = bucket_block(xs->bucket, 0); base 3907 fs/ocfs2/xattr.c xs->end = xs->base + inode->i_sb->s_blocksize; base 4262 fs/ocfs2/xattr.c xs->base = bucket_block(xs->bucket, 0); base 4263 fs/ocfs2/xattr.c xs->end = xs->base + inode->i_sb->s_blocksize; base 5771 fs/ocfs2/xattr.c char *base; base 5786 fs/ocfs2/xattr.c base = xis->base; base 5806 fs/ocfs2/xattr.c base = bucket_block(xbs->bucket, block_off); base 5820 fs/ocfs2/xattr.c base = xbs->base; base 5830 fs/ocfs2/xattr.c (base + name_offset + name_len); base 6009 fs/ocfs2/xattr.c void *base; base 6021 fs/ocfs2/xattr.c base = bucket_block(bucket, block_off); base 6023 fs/ocfs2/xattr.c *xv = (struct ocfs2_xattr_value_root *)(base + name_offset + base 194 fs/overlayfs/namei.c static int ovl_lookup_single(struct dentry *base, struct ovl_lookup_data *d, base 203 fs/overlayfs/namei.c this = lookup_one_len_unlocked(name, base, namelen); base 280 fs/overlayfs/namei.c static int ovl_lookup_layer(struct dentry *base, struct ovl_lookup_data *d, base 289 fs/overlayfs/namei.c return ovl_lookup_single(base, d, d->name.name, d->name.len, base 292 fs/overlayfs/namei.c while (!IS_ERR_OR_NULL(base) && d_can_lookup(base)) { base 302 fs/overlayfs/namei.c err = ovl_lookup_single(base, d, s, thislen, base 303 fs/overlayfs/namei.c d->name.len - rem, next, &base); base 307 fs/overlayfs/namei.c dentry = base; base 155 fs/reiserfs/stree.c const void *base, /* First item in the array. */ base 174 fs/reiserfs/stree.c ((struct reiserfs_key *)((char *)base + j * width), base 373 fs/splice.c size_t offset, base, copied = 0; base 388 fs/splice.c res = iov_iter_get_pages_alloc(&to, &pages, len + offset, &base); base 392 fs/splice.c nr_pages = DIV_ROUND_UP(res + base, PAGE_SIZE); base 107 fs/squashfs/inode.c struct squashfs_base_inode *sqshb_ino = &squashfs_ino.base; base 396 fs/squashfs/squashfs_fs.h struct squashfs_base_inode base; base 252 fs/sysv/dir.c char *base; base 264 fs/sysv/dir.c base = (char*)page_address(page); base 265 fs/sysv/dir.c memset(base, 0, PAGE_SIZE); base 267 fs/sysv/dir.c de = (struct sysv_dir_entry *) base; base 408 fs/ufs/dir.c ufs_validate_entry(struct super_block *sb, char *base, base 411 fs/ufs/dir.c struct ufs_dir_entry *de = (struct ufs_dir_entry*)(base + offset); base 412 fs/ufs/dir.c struct ufs_dir_entry *p = (struct ufs_dir_entry*)(base + (offset&mask)); base 415 fs/ufs/dir.c return (char *)p - base; base 550 fs/ufs/dir.c char *base; base 563 fs/ufs/dir.c base = (char*)page_address(page); base 564 fs/ufs/dir.c memset(base, 0, PAGE_SIZE); base 566 fs/ufs/dir.c de = (struct ufs_dir_entry *) base; base 509 fs/ufs/super.c unsigned char * base, * space; base 520 fs/ufs/super.c base = space = kmalloc(size, GFP_NOFS); base 521 fs/ufs/super.c if (!base) base 574 fs/ufs/super.c kfree (base); base 649 fs/ufs/super.c unsigned char * base, * space; base 658 fs/ufs/super.c base = space = (char*) sbi->s_csp; base 681 fs/ufs/super.c kfree (base); base 397 fs/ufs/util.h unsigned base, count, pos; base 402 fs/ufs/util.h base = offset >> uspi->s_bpfshift; base 407 fs/ufs/util.h pos = find_next_zero_bit_le(ubh->bh[base]->b_data, count, offset); base 410 fs/ufs/util.h base++; base 413 fs/ufs/util.h return (base << uspi->s_bpfshift) + pos - begin; base 444 fs/ufs/util.h unsigned base, count, pos, size; base 449 fs/ufs/util.h base = start >> uspi->s_bpfshift; base 456 fs/ufs/util.h pos = find_last_zero_bit (ubh->bh[base]->b_data, base 460 fs/ufs/util.h base--; base 463 fs/ufs/util.h return (base << uspi->s_bpfshift) + pos - begin; base 172 fs/xfs/libxfs/xfs_attr_leaf.c to->freemap[i].base = be16_to_cpu(hdr3->freemap[i].base); base 186 fs/xfs/libxfs/xfs_attr_leaf.c to->freemap[i].base = be16_to_cpu(from->hdr.freemap[i].base); base 215 fs/xfs/libxfs/xfs_attr_leaf.c hdr3->freemap[i].base = cpu_to_be16(from->freemap[i].base); base 230 fs/xfs/libxfs/xfs_attr_leaf.c to->hdr.freemap[i].base = cpu_to_be16(from->freemap[i].base); base 289 fs/xfs/libxfs/xfs_attr_leaf.c if (ichdr.freemap[i].base > mp->m_attr_geo->blksize) base 291 fs/xfs/libxfs/xfs_attr_leaf.c if (ichdr.freemap[i].base & 0x3) base 299 fs/xfs/libxfs/xfs_attr_leaf.c end = (uint32_t)ichdr.freemap[i].base + ichdr.freemap[i].size; base 300 fs/xfs/libxfs/xfs_attr_leaf.c if (end < ichdr.freemap[i].base) base 673 fs/xfs/libxfs/xfs_attr_leaf.c int base, size=0, end, totsize, i; base 681 fs/xfs/libxfs/xfs_attr_leaf.c base = sizeof(xfs_attr_sf_hdr_t); base 686 fs/xfs/libxfs/xfs_attr_leaf.c base += size, i++) { base 702 fs/xfs/libxfs/xfs_attr_leaf.c end = base + size; base 705 fs/xfs/libxfs/xfs_attr_leaf.c memmove(&((char *)sf)[base], &((char *)sf)[end], totsize - end); base 1185 fs/xfs/libxfs/xfs_attr_leaf.c ichdr.freemap[0].base = sizeof(struct xfs_attr3_leaf_hdr); base 1188 fs/xfs/libxfs/xfs_attr_leaf.c ichdr.freemap[0].base = sizeof(struct xfs_attr_leaf_hdr); base 1190 fs/xfs/libxfs/xfs_attr_leaf.c ichdr.freemap[0].size = ichdr.firstused - ichdr.freemap[0].base; base 1295 fs/xfs/libxfs/xfs_attr_leaf.c if (ichdr.freemap[i].base < ichdr.firstused) base 1378 fs/xfs/libxfs/xfs_attr_leaf.c ASSERT(ichdr->freemap[mapindex].base < args->geo->blksize); base 1379 fs/xfs/libxfs/xfs_attr_leaf.c ASSERT((ichdr->freemap[mapindex].base & 0x3) == 0); base 1387 fs/xfs/libxfs/xfs_attr_leaf.c entry->nameidx = cpu_to_be16(ichdr->freemap[mapindex].base + base 1448 fs/xfs/libxfs/xfs_attr_leaf.c if (ichdr->freemap[i].base == tmp) { base 1449 fs/xfs/libxfs/xfs_attr_leaf.c ichdr->freemap[i].base += sizeof(xfs_attr_leaf_entry_t); base 1493 fs/xfs/libxfs/xfs_attr_leaf.c ichdr_dst->freemap[0].base = xfs_attr3_leaf_hdr_size(leaf_src); base 1495 fs/xfs/libxfs/xfs_attr_leaf.c ichdr_dst->freemap[0].base; base 2028 fs/xfs/libxfs/xfs_attr_leaf.c ASSERT(ichdr.freemap[i].base < args->geo->blksize); base 2030 fs/xfs/libxfs/xfs_attr_leaf.c if (ichdr.freemap[i].base == tablesize) { base 2031 fs/xfs/libxfs/xfs_attr_leaf.c ichdr.freemap[i].base -= sizeof(xfs_attr_leaf_entry_t); base 2035 fs/xfs/libxfs/xfs_attr_leaf.c if (ichdr.freemap[i].base + ichdr.freemap[i].size == base 2038 fs/xfs/libxfs/xfs_attr_leaf.c } else if (ichdr.freemap[i].base == base 2055 fs/xfs/libxfs/xfs_attr_leaf.c ichdr.freemap[after].base = 0; base 2060 fs/xfs/libxfs/xfs_attr_leaf.c ichdr.freemap[after].base = be16_to_cpu(entry->nameidx); base 2068 fs/xfs/libxfs/xfs_attr_leaf.c ichdr.freemap[smallest].base = be16_to_cpu(entry->nameidx); base 2557 fs/xfs/libxfs/xfs_attr_leaf.c ichdr_d->freemap[0].base = xfs_attr3_leaf_hdr_size(leaf_d); base 2558 fs/xfs/libxfs/xfs_attr_leaf.c ichdr_d->freemap[0].base += ichdr_d->count * sizeof(xfs_attr_leaf_entry_t); base 2559 fs/xfs/libxfs/xfs_attr_leaf.c ichdr_d->freemap[0].size = ichdr_d->firstused - ichdr_d->freemap[0].base; base 2560 fs/xfs/libxfs/xfs_attr_leaf.c ichdr_d->freemap[1].base = 0; base 2561 fs/xfs/libxfs/xfs_attr_leaf.c ichdr_d->freemap[2].base = 0; base 631 fs/xfs/libxfs/xfs_da_format.h __be16 base; /* base of free region */ base 730 fs/xfs/libxfs/xfs_da_format.h uint16_t base; base 228 fs/xfs/scrub/attr.c leafhdr->freemap[i].base, base 114 fs/xfs/xfs_super.c suffix_kstrtoint(const substring_t *s, unsigned int base, int *res) base 138 fs/xfs/xfs_super.c if (kstrtoint(value, base, &_res)) base 43 include/asm-generic/div64.h # define do_div(n,base) ({ \ base 44 include/asm-generic/div64.h uint32_t __base = (base); \ base 223 include/asm-generic/div64.h # define do_div(n,base) ({ \ base 224 include/asm-generic/div64.h uint32_t __base = (base); \ base 8 include/asm-generic/dma-contiguous.h dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) { } base 11 include/clocksource/pxa.h extern void pxa_timer_nodt_init(int irq, void __iomem *base); base 29 include/clocksource/samsung_pwm.h void samsung_pwm_clocksource_init(void __iomem *base, base 13 include/clocksource/timer-sp804.h static inline void sp804_clocksource_init(void __iomem *base, const char *name) base 15 include/clocksource/timer-sp804.h __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0); base 18 include/clocksource/timer-sp804.h static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base, base 21 include/clocksource/timer-sp804.h __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1); base 24 include/clocksource/timer-sp804.h static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name) base 26 include/clocksource/timer-sp804.h __sp804_clockevents_init(base, irq, NULL, name); base 27 include/crypto/acompress.h struct crypto_async_request base; base 52 include/crypto/acompress.h struct crypto_tfm base; base 83 include/crypto/acompress.h struct crypto_alg base; base 112 include/crypto/acompress.h return &tfm->base; base 117 include/crypto/acompress.h return container_of(alg, struct acomp_alg, base); base 122 include/crypto/acompress.h return container_of(tfm, struct crypto_acomp, base); base 138 include/crypto/acompress.h req->base.tfm = crypto_acomp_tfm(tfm); base 143 include/crypto/acompress.h return __crypto_acomp_tfm(req->base.tfm); base 199 include/crypto/acompress.h req->base.complete = cmpl; base 200 include/crypto/acompress.h req->base.data = data; base 201 include/crypto/acompress.h req->base.flags = flgs; base 244 include/crypto/acompress.h struct crypto_alg *alg = tfm->base.__crt_alg; base 266 include/crypto/acompress.h struct crypto_alg *alg = tfm->base.__crt_alg; base 82 include/crypto/aead.h struct crypto_async_request base; base 143 include/crypto/aead.h struct crypto_alg base; base 150 include/crypto/aead.h struct crypto_tfm base; base 155 include/crypto/aead.h return container_of(tfm, struct crypto_aead, base); base 176 include/crypto/aead.h return &tfm->base; base 191 include/crypto/aead.h struct aead_alg, base); base 298 include/crypto/aead.h return __crypto_aead_cast(req->base.tfm); base 379 include/crypto/aead.h req->base.tfm = crypto_aead_tfm(tfm); base 445 include/crypto/aead.h req->base.complete = compl; base 446 include/crypto/aead.h req->base.data = data; base 447 include/crypto/aead.h req->base.flags = flags; base 34 include/crypto/akcipher.h struct crypto_async_request base; base 49 include/crypto/akcipher.h struct crypto_tfm base; base 106 include/crypto/akcipher.h struct crypto_alg base; base 136 include/crypto/akcipher.h return &tfm->base; base 141 include/crypto/akcipher.h return container_of(alg, struct akcipher_alg, base); base 147 include/crypto/akcipher.h return container_of(tfm, struct crypto_akcipher, base); base 164 include/crypto/akcipher.h req->base.tfm = crypto_akcipher_tfm(tfm); base 170 include/crypto/akcipher.h return __crypto_akcipher_tfm(req->base.tfm); base 229 include/crypto/akcipher.h req->base.complete = cmpl; base 230 include/crypto/akcipher.h req->base.data = data; base 231 include/crypto/akcipher.h req->base.flags = flgs; base 289 include/crypto/akcipher.h struct crypto_alg *calg = tfm->base.__crt_alg; base 313 include/crypto/akcipher.h struct crypto_alg *calg = tfm->base.__crt_alg; base 337 include/crypto/akcipher.h struct crypto_alg *calg = tfm->base.__crt_alg; base 364 include/crypto/akcipher.h struct crypto_alg *calg = tfm->base.__crt_alg; base 281 include/crypto/algapi.h return crypto_tfm_ctx(&tfm->base); base 286 include/crypto/algapi.h return crypto_tfm_ctx_aligned(&tfm->base); base 300 include/crypto/algapi.h return crypto_tfm_ctx(&tfm->base); base 305 include/crypto/algapi.h return crypto_tfm_ctx_aligned(&tfm->base); base 359 include/crypto/algapi.h return crypto_enqueue_request(queue, &request->base); base 22 include/crypto/cryptd.h struct crypto_skcipher base; base 34 include/crypto/cryptd.h struct crypto_ahash base; base 53 include/crypto/cryptd.h struct crypto_aead base; base 46 include/crypto/hash.h struct crypto_alg base; base 50 include/crypto/hash.h struct crypto_async_request base; base 200 include/crypto/hash.h struct crypto_alg base; base 215 include/crypto/hash.h struct crypto_tfm base; base 220 include/crypto/hash.h struct crypto_tfm base; base 235 include/crypto/hash.h return container_of(tfm, struct crypto_ahash, base); base 257 include/crypto/hash.h return &tfm->base; base 314 include/crypto/hash.h return container_of(alg, struct hash_alg_common, base); base 381 include/crypto/hash.h return __crypto_ahash_cast(req->base.tfm); base 529 include/crypto/hash.h struct crypto_alg *alg = tfm->base.__crt_alg; base 561 include/crypto/hash.h req->base.tfm = crypto_ahash_tfm(tfm); base 608 include/crypto/hash.h return container_of(req, struct ahash_request, base); base 641 include/crypto/hash.h req->base.complete = compl; base 642 include/crypto/hash.h req->base.data = data; base 643 include/crypto/hash.h req->base.flags = flags; base 700 include/crypto/hash.h return &tfm->base; base 744 include/crypto/hash.h return container_of(alg, struct shash_alg, base); base 23 include/crypto/internal/acompress.h return tfm->base.__crt_ctx; base 29 include/crypto/internal/acompress.h req->base.complete(&req->base, err); base 22 include/crypto/internal/aead.h char head[offsetof(struct aead_alg, base)]; base 23 include/crypto/internal/aead.h struct crypto_instance base; base 30 include/crypto/internal/aead.h struct crypto_spawn base; base 34 include/crypto/internal/aead.h struct crypto_queue base; base 39 include/crypto/internal/aead.h return crypto_tfm_ctx(&tfm->base); base 45 include/crypto/internal/aead.h return container_of(&inst->alg.base, struct crypto_instance, alg); base 50 include/crypto/internal/aead.h return container_of(&inst->alg, struct aead_instance, alg.base); base 55 include/crypto/internal/aead.h return aead_instance(crypto_tfm_alg_instance(&aead->base)); base 70 include/crypto/internal/aead.h req->base.complete(&req->base, err); base 75 include/crypto/internal/aead.h return req->base.flags; base 81 include/crypto/internal/aead.h return container_of(req, struct aead_request, base); base 87 include/crypto/internal/aead.h crypto_set_spawn(&spawn->base, inst); base 95 include/crypto/internal/aead.h crypto_drop_spawn(&spawn->base); base 101 include/crypto/internal/aead.h return container_of(spawn->base.alg, struct aead_alg, base); base 107 include/crypto/internal/aead.h return crypto_spawn_tfm2(&spawn->base); base 129 include/crypto/internal/aead.h crypto_init_queue(&queue->base, max_qlen); base 135 include/crypto/internal/aead.h return crypto_enqueue_request(&queue->base, &request->base); base 143 include/crypto/internal/aead.h req = crypto_dequeue_request(&queue->base); base 145 include/crypto/internal/aead.h return req ? container_of(req, struct aead_request, base) : NULL; base 152 include/crypto/internal/aead.h req = crypto_get_backlog(&queue->base); base 154 include/crypto/internal/aead.h return req ? container_of(req, struct aead_request, base) : NULL; base 17 include/crypto/internal/akcipher.h char head[offsetof(struct akcipher_alg, base)]; base 18 include/crypto/internal/akcipher.h struct crypto_instance base; base 25 include/crypto/internal/akcipher.h struct crypto_spawn base; base 44 include/crypto/internal/akcipher.h return tfm->base.__crt_ctx; base 50 include/crypto/internal/akcipher.h req->base.complete(&req->base, err); base 61 include/crypto/internal/akcipher.h return container_of(&inst->alg.base, struct crypto_instance, alg); base 67 include/crypto/internal/akcipher.h return container_of(&inst->alg, struct akcipher_instance, alg.base); base 73 include/crypto/internal/akcipher.h return akcipher_instance(crypto_tfm_alg_instance(&akcipher->base)); base 85 include/crypto/internal/akcipher.h crypto_set_spawn(&spawn->base, inst); base 94 include/crypto/internal/akcipher.h return crypto_spawn_tfm2(&spawn->base); base 99 include/crypto/internal/akcipher.h crypto_drop_spawn(&spawn->base); base 105 include/crypto/internal/akcipher.h return container_of(spawn->base.alg, struct akcipher_alg, base); base 41 include/crypto/internal/hash.h struct crypto_spawn base; base 45 include/crypto/internal/hash.h struct crypto_spawn base; base 96 include/crypto/internal/hash.h crypto_drop_spawn(&spawn->base); base 115 include/crypto/internal/hash.h crypto_drop_spawn(&spawn->base); base 146 include/crypto/internal/hash.h return container_of(&inst->alg.halg.base, struct crypto_instance, alg); base 152 include/crypto/internal/hash.h return container_of(&inst->alg, struct ahash_instance, alg.halg.base); base 173 include/crypto/internal/hash.h req->base.complete(&req->base, err); base 178 include/crypto/internal/hash.h return req->base.flags; base 184 include/crypto/internal/hash.h return crypto_spawn_tfm2(&spawn->base); base 190 include/crypto/internal/hash.h return crypto_enqueue_request(queue, &request->base); base 201 include/crypto/internal/hash.h return crypto_tfm_ctx(&tfm->base); base 207 include/crypto/internal/hash.h return container_of(&inst->alg.base, struct crypto_instance, alg); base 232 include/crypto/internal/hash.h return crypto_spawn_tfm2(&spawn->base); base 237 include/crypto/internal/hash.h return crypto_tfm_ctx_aligned(&tfm->base); base 242 include/crypto/internal/hash.h return container_of(tfm, struct crypto_shash, base); base 23 include/crypto/internal/kpp.h return tfm->base.__crt_ctx; base 28 include/crypto/internal/kpp.h req->base.complete(&req->base, err); base 31 include/crypto/internal/rng.h return crypto_tfm_ctx(&tfm->base); base 16 include/crypto/internal/scompress.h struct crypto_tfm base; base 37 include/crypto/internal/scompress.h struct crypto_alg base; base 42 include/crypto/internal/scompress.h return container_of(alg, struct scomp_alg, base); base 47 include/crypto/internal/scompress.h return container_of(tfm, struct crypto_scomp, base); base 52 include/crypto/internal/scompress.h return &tfm->base; base 23 include/crypto/internal/skcipher.h char head[offsetof(struct skcipher_alg, base)]; base 24 include/crypto/internal/skcipher.h struct crypto_instance base; base 31 include/crypto/internal/skcipher.h struct crypto_spawn base; base 71 include/crypto/internal/skcipher.h return &inst->s.base; base 88 include/crypto/internal/skcipher.h req->base.complete(&req->base, err); base 94 include/crypto/internal/skcipher.h crypto_set_spawn(&spawn->base, inst); base 102 include/crypto/internal/skcipher.h crypto_drop_spawn(&spawn->base); base 108 include/crypto/internal/skcipher.h return container_of(spawn->base.alg, struct skcipher_alg, base); base 120 include/crypto/internal/skcipher.h return crypto_spawn_tfm2(&spawn->base); base 159 include/crypto/internal/skcipher.h req->base.complete(&req->base, err); base 164 include/crypto/internal/skcipher.h return req->base.flags; base 169 include/crypto/internal/skcipher.h return crypto_tfm_ctx(&tfm->base); base 179 include/crypto/internal/skcipher.h return req->base.flags; base 185 include/crypto/internal/skcipher.h if ((alg->base.cra_flags & CRYPTO_ALG_TYPE_MASK) == base 187 include/crypto/internal/skcipher.h return alg->base.cra_blkcipher.min_keysize; base 189 include/crypto/internal/skcipher.h if (alg->base.cra_ablkcipher.encrypt) base 190 include/crypto/internal/skcipher.h return alg->base.cra_ablkcipher.min_keysize; base 198 include/crypto/internal/skcipher.h if ((alg->base.cra_flags & CRYPTO_ALG_TYPE_MASK) == base 200 include/crypto/internal/skcipher.h return alg->base.cra_blkcipher.max_keysize; base 202 include/crypto/internal/skcipher.h if (alg->base.cra_ablkcipher.encrypt) base 203 include/crypto/internal/skcipher.h return alg->base.cra_ablkcipher.max_keysize; base 211 include/crypto/internal/skcipher.h if ((alg->base.cra_flags & CRYPTO_ALG_TYPE_MASK) == base 213 include/crypto/internal/skcipher.h return alg->base.cra_blocksize; base 215 include/crypto/internal/skcipher.h if (alg->base.cra_ablkcipher.encrypt) base 216 include/crypto/internal/skcipher.h return alg->base.cra_blocksize; base 28 include/crypto/kpp.h struct crypto_async_request base; base 43 include/crypto/kpp.h struct crypto_tfm base; base 83 include/crypto/kpp.h struct crypto_alg base; base 109 include/crypto/kpp.h return &tfm->base; base 114 include/crypto/kpp.h return container_of(alg, struct kpp_alg, base); base 119 include/crypto/kpp.h return container_of(tfm, struct crypto_kpp, base); base 135 include/crypto/kpp.h req->base.tfm = crypto_kpp_tfm(tfm); base 140 include/crypto/kpp.h return __crypto_kpp_tfm(req->base.tfm); base 209 include/crypto/kpp.h req->base.complete = cmpl; base 210 include/crypto/kpp.h req->base.data = data; base 211 include/crypto/kpp.h req->base.flags = flgs; base 285 include/crypto/kpp.h struct crypto_alg *calg = tfm->base.__crt_alg; base 311 include/crypto/kpp.h struct crypto_alg *calg = tfm->base.__crt_alg; base 334 include/crypto/kpp.h struct crypto_alg *calg = tfm->base.__crt_alg; base 51 include/crypto/rng.h struct crypto_alg base; base 55 include/crypto/rng.h struct crypto_tfm base; base 94 include/crypto/rng.h return &tfm->base; base 108 include/crypto/rng.h struct rng_alg, base); base 138 include/crypto/rng.h struct crypto_alg *alg = tfm->base.__crt_alg; base 32 include/crypto/skcipher.h struct crypto_async_request base; base 47 include/crypto/skcipher.h struct crypto_tfm base; base 51 include/crypto/skcipher.h struct crypto_skcipher base; base 125 include/crypto/skcipher.h struct crypto_alg base; base 174 include/crypto/skcipher.h return container_of(tfm, struct crypto_skcipher, base); base 200 include/crypto/skcipher.h return &tfm->base; base 214 include/crypto/skcipher.h crypto_free_skcipher(&tfm->base); base 256 include/crypto/skcipher.h struct skcipher_alg, base); base 261 include/crypto/skcipher.h if ((alg->base.cra_flags & CRYPTO_ALG_TYPE_MASK) == base 263 include/crypto/skcipher.h return alg->base.cra_blkcipher.ivsize; base 265 include/crypto/skcipher.h if (alg->base.cra_ablkcipher.encrypt) base 266 include/crypto/skcipher.h return alg->base.cra_ablkcipher.ivsize; base 288 include/crypto/skcipher.h return crypto_skcipher_ivsize(&tfm->base); base 310 include/crypto/skcipher.h if ((alg->base.cra_flags & CRYPTO_ALG_TYPE_MASK) == base 312 include/crypto/skcipher.h return alg->base.cra_blocksize; base 314 include/crypto/skcipher.h if (alg->base.cra_ablkcipher.encrypt) base 315 include/crypto/skcipher.h return alg->base.cra_blocksize; base 340 include/crypto/skcipher.h return crypto_skcipher_blocksize(&tfm->base); base 369 include/crypto/skcipher.h return crypto_skcipher_get_flags(&tfm->base); base 375 include/crypto/skcipher.h crypto_skcipher_set_flags(&tfm->base, flags); base 381 include/crypto/skcipher.h crypto_skcipher_clear_flags(&tfm->base, flags); base 409 include/crypto/skcipher.h return crypto_skcipher_setkey(&tfm->base, key, keylen); base 430 include/crypto/skcipher.h return __crypto_skcipher_cast(req->base.tfm); base 438 include/crypto/skcipher.h return container_of(tfm, struct crypto_sync_skcipher, base); base 500 include/crypto/skcipher.h req->base.tfm = crypto_skcipher_tfm(tfm); base 506 include/crypto/skcipher.h skcipher_request_set_tfm(req, &tfm->base); base 512 include/crypto/skcipher.h return container_of(req, struct skcipher_request, base); base 586 include/crypto/skcipher.h req->base.complete = compl; base 587 include/crypto/skcipher.h req->base.data = data; base 588 include/crypto/skcipher.h req->base.flags = flags; base 40 include/drm/bridge/dw_mipi_dsi.h void __iomem *base; base 23 include/drm/drm_agpsupport.h unsigned long base; base 1101 include/drm/drm_connector.h struct drm_mode_object base; base 1415 include/drm/drm_connector.h #define obj_to_connector(x) container_of(x, struct drm_connector, base) base 1470 include/drm/drm_connector.h drm_mode_object_get(&connector->base); base 1482 include/drm/drm_connector.h drm_mode_object_put(&connector->base); base 909 include/drm/drm_crtc.h struct drm_mode_object base; base 1141 include/drm/drm_crtc.h #define obj_to_crtc(x) container_of(x, struct drm_crtc, base) base 69 include/drm/drm_displayid.h struct displayid_block base; base 91 include/drm/drm_displayid.h struct displayid_block base; base 426 include/drm/drm_dp_mst_helper.h #define to_dp_mst_topology_state(x) container_of(x, struct drm_dp_mst_topology_state, base) base 435 include/drm/drm_dp_mst_helper.h struct drm_private_state base; base 440 include/drm/drm_dp_mst_helper.h #define to_dp_mst_topology_mgr(x) container_of(x, struct drm_dp_mst_topology_mgr, base) base 453 include/drm/drm_dp_mst_helper.h struct drm_private_obj base; base 103 include/drm/drm_encoder.h struct drm_mode_object base; base 180 include/drm/drm_encoder.h #define obj_to_encoder(x) container_of(x, struct drm_encoder, base) base 96 include/drm/drm_encoder_slave.h struct drm_encoder base; base 102 include/drm/drm_encoder_slave.h #define to_encoder_slave(x) container_of((x), struct drm_encoder_slave, base) base 131 include/drm/drm_framebuffer.h struct drm_mode_object base; base 216 include/drm/drm_framebuffer.h #define obj_to_fb(x) container_of(x, struct drm_framebuffer, base) base 236 include/drm/drm_framebuffer.h drm_mode_object_get(&fb->base); base 248 include/drm/drm_framebuffer.h drm_mode_object_put(&fb->base); base 259 include/drm/drm_framebuffer.h return kref_read(&fb->base.refcount); base 21 include/drm/drm_gem_cma_helper.h struct drm_gem_object base; base 30 include/drm/drm_gem_cma_helper.h container_of(gem_obj, struct drm_gem_cma_object, base) base 27 include/drm/drm_gem_shmem_helper.h struct drm_gem_object base; base 102 include/drm/drm_gem_shmem_helper.h container_of(obj, struct drm_gem_shmem_object, base) base 146 include/drm/drm_gem_shmem_helper.h !shmem->base.dma_buf && !shmem->base.import_attach; base 70 include/drm/drm_gem_vram_helper.h return container_of(gem, struct drm_gem_vram_object, bo.base); base 446 include/drm/drm_modes.h #define obj_to_mode(x) container_of(x, struct drm_display_mode, base) base 584 include/drm/drm_plane.h struct drm_mode_object base; base 710 include/drm/drm_plane.h #define obj_to_plane(x) container_of(x, struct drm_plane, base) base 82 include/drm/drm_property.h struct drm_mode_object base; base 210 include/drm/drm_property.h struct drm_mode_object base; base 223 include/drm/drm_property.h #define obj_to_property(x) container_of(x, struct drm_property, base) base 224 include/drm/drm_property.h #define obj_to_blob(x) container_of(x, struct drm_property_blob, base) base 44 include/drm/drm_vblank.h struct drm_pending_event base; base 60 include/drm/drm_vblank.h struct drm_event base; base 19 include/drm/drm_writeback.h struct drm_connector base; base 137 include/drm/drm_writeback.h return container_of(connector, struct drm_writeback_connector, base); base 46 include/drm/i915_component.h struct drm_audio_component base; base 72 include/drm/ttm/ttm_bo_api.h phys_addr_t base; base 173 include/drm/ttm/ttm_bo_api.h struct drm_gem_object base; base 786 include/drm/ttm/ttm_bo_api.h return bo->base.dev != NULL; base 667 include/drm/ttm/ttm_bo_driver.h success = dma_resv_trylock(bo->base.resv); base 672 include/drm/ttm/ttm_bo_driver.h ret = dma_resv_lock_interruptible(bo->base.resv, ticket); base 674 include/drm/ttm/ttm_bo_driver.h ret = dma_resv_lock(bo->base.resv, ticket); base 758 include/drm/ttm/ttm_bo_driver.h ret = dma_resv_lock_slow_interruptible(bo->base.resv, base 761 include/drm/ttm/ttm_bo_driver.h dma_resv_lock_slow(bo->base.resv, ticket); base 786 include/drm/ttm/ttm_bo_driver.h dma_resv_unlock(bo->base.resv); base 196 include/kvm/arm_vgic.h gpa_t base; base 25 include/linux/acpi_iort.h int iort_register_domain_token(int trans_id, phys_addr_t base, base 114 include/linux/amba/bus.h resource_size_t base, size_t size, base 118 include/linux/amba/bus.h resource_size_t base, size_t size, base 123 include/linux/amba/bus.h resource_size_t base, size_t size, int irq1, base 128 include/linux/amba/bus.h resource_size_t base, size_t size, int irq1, base 180 include/linux/amba/bus.h #define AMBA_APB_DEVICE(name, busid, id, base, irqs, data) \ base 183 include/linux/amba/bus.h .res = DEFINE_RES_MEM(base, SZ_4K), \ base 191 include/linux/amba/bus.h #define AMBA_AHB_DEVICE(name, busid, id, base, irqs, data) \ base 194 include/linux/amba/bus.h .res = DEFINE_RES_MEM(base, SZ_4K), \ base 212 include/linux/amba/serial.h void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl); base 53 include/linux/amba/sp810.h static inline void sysctl_soft_reset(void __iomem *base) base 56 include/linux/amba/sp810.h writel(0x2, base + SCCTRL); base 59 include/linux/amba/sp810.h writel(0, base + SCSYSSTAT); base 21 include/linux/amd-iommu.h u64 base; base 332 include/linux/atmel-ssc.h #define ssc_readl(base, reg) __raw_readl(base + SSC_##reg) base 333 include/linux/atmel-ssc.h #define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg) base 14 include/linux/bcm47xx_nvram.h int bcm47xx_nvram_init_from_mem(u32 base, u32 lim); base 23 include/linux/bcm47xx_nvram.h static inline int bcm47xx_nvram_init_from_mem(u32 base, u32 lim) base 113 include/linux/bitfield.h #define ____MAKE_OP(type,base,to,from) \ base 114 include/linux/bitfield.h static __always_inline __##type type##_encode_bits(base v, base field) \ base 121 include/linux/bitfield.h base val, base field) \ base 126 include/linux/bitfield.h base val, base field) \ base 130 include/linux/bitfield.h static __always_inline base type##_get_bits(__##type v, base field) \ base 664 include/linux/bpf.h void bpf_map_area_free(void *base); base 7 include/linux/bsearch.h void *bsearch(const void *key, const void *base, size_t num, size_t size, base 17 include/linux/clk/davinci.h int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 20 include/linux/clk/davinci.h int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 23 include/linux/clk/davinci.h int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 24 include/linux/clk/davinci.h int dm355_psc_init(struct device *dev, void __iomem *base); base 27 include/linux/clk/davinci.h int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 28 include/linux/clk/davinci.h int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 29 include/linux/clk/davinci.h int dm365_psc_init(struct device *dev, void __iomem *base); base 32 include/linux/clk/davinci.h int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 33 include/linux/clk/davinci.h int dm644x_psc_init(struct device *dev, void __iomem *base); base 36 include/linux/clk/davinci.h int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); base 37 include/linux/clk/davinci.h int dm646x_psc_init(struct device *dev, void __iomem *base); base 27 include/linux/cma.h extern int __init cma_declare_contiguous(phys_addr_t base, base 31 include/linux/cma.h extern int cma_init_reserved_mem(phys_addr_t base, phys_addr_t size, base 281 include/linux/coresight.h extern int coresight_claim_device(void __iomem *base); base 282 include/linux/coresight.h extern int coresight_claim_device_unlocked(void __iomem *base); base 284 include/linux/coresight.h extern void coresight_disclaim_device(void __iomem *base); base 285 include/linux/coresight.h extern void coresight_disclaim_device_unlocked(void __iomem *base); base 297 include/linux/coresight.h static inline int coresight_claim_device_unlocked(void __iomem *base) base 302 include/linux/coresight.h static inline int coresight_claim_device(void __iomem *base) base 307 include/linux/coresight.h static inline void coresight_disclaim_device(void __iomem *base) {} base 308 include/linux/coresight.h static inline void coresight_disclaim_device_unlocked(void __iomem *base) {} base 167 include/linux/crypto.h struct crypto_async_request base; base 724 include/linux/crypto.h struct crypto_ablkcipher *base; base 780 include/linux/crypto.h struct crypto_tfm base; base 784 include/linux/crypto.h struct crypto_tfm base; base 788 include/linux/crypto.h struct crypto_tfm base; base 792 include/linux/crypto.h struct crypto_tfm base; base 950 include/linux/crypto.h return &tfm->base; base 1060 include/linux/crypto.h return crt->setkey(crt->base, key, keylen); base 1075 include/linux/crypto.h return __crypto_ablkcipher_cast(req->base.tfm); base 1093 include/linux/crypto.h struct crypto_alg *alg = crt->base->base.__crt_alg; base 1118 include/linux/crypto.h struct crypto_alg *alg = crt->base->base.__crt_alg; base 1162 include/linux/crypto.h req->base.tfm = crypto_ablkcipher_tfm(crypto_ablkcipher_crt(tfm)->base); base 1168 include/linux/crypto.h return container_of(req, struct ablkcipher_request, base); base 1234 include/linux/crypto.h req->base.complete = compl; base 1235 include/linux/crypto.h req->base.data = data; base 1236 include/linux/crypto.h req->base.flags = flags; base 1336 include/linux/crypto.h return &tfm->base; base 1655 include/linux/crypto.h return &tfm->base; base 1807 include/linux/crypto.h return &tfm->base; base 37 include/linux/debugfs.h void __iomem *base; base 134 include/linux/debugfs.h int nregs, void __iomem *base, char *prefix); base 346 include/linux/debugfs.h int nregs, void __iomem *base, char *prefix) base 136 include/linux/dio.h #define DIO_SIZE(scode, base) (DIO_ISDIOII((scode)) ? DIOII_SIZE((base)) : DIO_DEVSIZE) base 82 include/linux/dma-contiguous.h int __init dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base, base 100 include/linux/dma-contiguous.h phys_addr_t base, phys_addr_t limit) base 104 include/linux/dma-contiguous.h ret = dma_contiguous_reserve_area(size, base, limit, &cma, true); base 131 include/linux/dma-contiguous.h static inline int dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base, base 140 include/linux/dma-contiguous.h phys_addr_t base, phys_addr_t limit) base 38 include/linux/dma-fence-array.h struct dma_fence base; base 74 include/linux/dma-fence-array.h return container_of(fence, struct dma_fence_array, base); base 27 include/linux/dma-fence-chain.h struct dma_fence base; base 51 include/linux/dma-fence-chain.h return container_of(fence, struct dma_fence_chain, base); base 18 include/linux/dma-iommu.h int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base); base 57 include/linux/dma-iommu.h static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) base 80 include/linux/dma-resv.h #define dma_resv_held(obj) lockdep_is_held(&(obj)->lock.base) base 81 include/linux/dma-resv.h #define dma_resv_assert_held(obj) lockdep_assert_held(&(obj)->lock.base) base 20 include/linux/dw_apb_timer.h void __iomem *base; base 44 include/linux/dw_apb_timer.h void __iomem *base, int irq, unsigned long freq); base 46 include/linux/dw_apb_timer.h dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base, base 1785 include/linux/efi.h phys_addr_t base; base 109 include/linux/ethtool.h struct ethtool_link_settings base; base 12 include/linux/extable.h search_extable(const struct exception_table_entry *base, base 500 include/linux/fb.h resource_size_t base; base 141 include/linux/fsl/ptp_qoriq.h void __iomem *base; base 185 include/linux/fsl/ptp_qoriq.h int ptp_qoriq_init(struct ptp_qoriq *ptp_qoriq, void __iomem *base, base 379 include/linux/gpio/driver.h int base; base 526 include/linux/gpio/driver.h int base; base 9 include/linux/gpio/gpio-reg.h int base, int num, const char *label, u32 direction, u32 def_out, base 152 include/linux/host1x.h u32 host1x_syncpt_base_id(struct host1x_syncpt_base *base); base 121 include/linux/hrtimer.h struct hrtimer_clock_base *base; base 301 include/linux/hrtimer.h return ktime_sub(timer->node.expires, timer->base->get_time()); base 306 include/linux/hrtimer.h return timer->base->get_time(); base 312 include/linux/hrtimer.h timer->base->cpu_base->hres_active : 0; base 350 include/linux/hrtimer.h timer->base->get_time()); base 479 include/linux/hrtimer.h return timer->base->running == timer; base 505 include/linux/hrtimer.h return hrtimer_forward(timer, timer->base->get_time(), interval); base 65 include/linux/i3c/master.h struct i2c_board_info base; base 35 include/linux/idr.h #define IDR_INIT_BASE(name, base) { \ base 37 include/linux/idr.h .idr_base = (base), \ base 135 include/linux/idr.h static inline void idr_init_base(struct idr *idr, int base) base 138 include/linux/idr.h idr->idr_base = base; base 418 include/linux/intel-iommu.h struct irte *base; base 23 include/linux/io-mapping.h resource_size_t base; base 41 include/linux/io-mapping.h resource_size_t base, base 46 include/linux/io-mapping.h if (iomap_create_wc(base, size, &prot)) base 49 include/linux/io-mapping.h iomap->base = base; base 58 include/linux/io-mapping.h iomap_free(mapping->base, mapping->size); base 70 include/linux/io-mapping.h phys_addr = mapping->base + offset; base 89 include/linux/io-mapping.h phys_addr = mapping->base + offset; base 108 include/linux/io-mapping.h resource_size_t base, base 111 include/linux/io-mapping.h iomap->base = base; base 113 include/linux/io-mapping.h iomap->iomem = ioremap_wc(base, size); base 166 include/linux/io-mapping.h io_mapping_create_wc(resource_size_t base, base 175 include/linux/io-mapping.h if (!io_mapping_init_wc(iomap, base, size)) { base 126 include/linux/io.h static inline int __must_check arch_phys_wc_add(unsigned long base, base 168 include/linux/io.h static inline int arch_io_reserve_memtype_wc(resource_size_t base, base 174 include/linux/io.h static inline void arch_io_free_memtype_wc(resource_size_t base, base 299 include/linux/ioport.h struct resource *base, unsigned long size); base 300 include/linux/ioport.h struct resource *request_free_mem_region(struct resource *base, base 19 include/linux/irqchip/arm-vic.h void __vic_init(void __iomem *base, int parent_irq, int irq_start, base 21 include/linux/irqchip/arm-vic.h void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources); base 22 include/linux/irqchip/arm-vic.h int vic_init_cascaded(void __iomem *base, unsigned int parent_irq, base 339 include/linux/kernel.h int __must_check _kstrtoul(const char *s, unsigned int base, unsigned long *res); base 340 include/linux/kernel.h int __must_check _kstrtol(const char *s, unsigned int base, long *res); base 342 include/linux/kernel.h int __must_check kstrtoull(const char *s, unsigned int base, unsigned long long *res); base 343 include/linux/kernel.h int __must_check kstrtoll(const char *s, unsigned int base, long long *res); base 361 include/linux/kernel.h static inline int __must_check kstrtoul(const char *s, unsigned int base, unsigned long *res) base 369 include/linux/kernel.h return kstrtoull(s, base, (unsigned long long *)res); base 371 include/linux/kernel.h return _kstrtoul(s, base, res); base 390 include/linux/kernel.h static inline int __must_check kstrtol(const char *s, unsigned int base, long *res) base 398 include/linux/kernel.h return kstrtoll(s, base, (long long *)res); base 400 include/linux/kernel.h return _kstrtol(s, base, res); base 403 include/linux/kernel.h int __must_check kstrtouint(const char *s, unsigned int base, unsigned int *res); base 404 include/linux/kernel.h int __must_check kstrtoint(const char *s, unsigned int base, int *res); base 406 include/linux/kernel.h static inline int __must_check kstrtou64(const char *s, unsigned int base, u64 *res) base 408 include/linux/kernel.h return kstrtoull(s, base, res); base 411 include/linux/kernel.h static inline int __must_check kstrtos64(const char *s, unsigned int base, s64 *res) base 413 include/linux/kernel.h return kstrtoll(s, base, res); base 416 include/linux/kernel.h static inline int __must_check kstrtou32(const char *s, unsigned int base, u32 *res) base 418 include/linux/kernel.h return kstrtouint(s, base, res); base 421 include/linux/kernel.h static inline int __must_check kstrtos32(const char *s, unsigned int base, s32 *res) base 423 include/linux/kernel.h return kstrtoint(s, base, res); base 426 include/linux/kernel.h int __must_check kstrtou16(const char *s, unsigned int base, u16 *res); base 427 include/linux/kernel.h int __must_check kstrtos16(const char *s, unsigned int base, s16 *res); base 428 include/linux/kernel.h int __must_check kstrtou8(const char *s, unsigned int base, u8 *res); base 429 include/linux/kernel.h int __must_check kstrtos8(const char *s, unsigned int base, s8 *res); base 432 include/linux/kernel.h int __must_check kstrtoull_from_user(const char __user *s, size_t count, unsigned int base, unsigned long long *res); base 433 include/linux/kernel.h int __must_check kstrtoll_from_user(const char __user *s, size_t count, unsigned int base, long long *res); base 434 include/linux/kernel.h int __must_check kstrtoul_from_user(const char __user *s, size_t count, unsigned int base, unsigned long *res); base 435 include/linux/kernel.h int __must_check kstrtol_from_user(const char __user *s, size_t count, unsigned int base, long *res); base 436 include/linux/kernel.h int __must_check kstrtouint_from_user(const char __user *s, size_t count, unsigned int base, unsigned int *res); base 437 include/linux/kernel.h int __must_check kstrtoint_from_user(const char __user *s, size_t count, unsigned int base, int *res); base 438 include/linux/kernel.h int __must_check kstrtou16_from_user(const char __user *s, size_t count, unsigned int base, u16 *res); base 439 include/linux/kernel.h int __must_check kstrtos16_from_user(const char __user *s, size_t count, unsigned int base, s16 *res); base 440 include/linux/kernel.h int __must_check kstrtou8_from_user(const char __user *s, size_t count, unsigned int base, u8 *res); base 441 include/linux/kernel.h int __must_check kstrtos8_from_user(const char __user *s, size_t count, unsigned int base, s8 *res); base 444 include/linux/kernel.h static inline int __must_check kstrtou64_from_user(const char __user *s, size_t count, unsigned int base, u64 *res) base 446 include/linux/kernel.h return kstrtoull_from_user(s, count, base, res); base 449 include/linux/kernel.h static inline int __must_check kstrtos64_from_user(const char __user *s, size_t count, unsigned int base, s64 *res) base 451 include/linux/kernel.h return kstrtoll_from_user(s, count, base, res); base 454 include/linux/kernel.h static inline int __must_check kstrtou32_from_user(const char __user *s, size_t count, unsigned int base, u32 *res) base 456 include/linux/kernel.h return kstrtouint_from_user(s, count, base, res); base 459 include/linux/kernel.h static inline int __must_check kstrtos32_from_user(const char __user *s, size_t count, unsigned int base, s32 *res) base 461 include/linux/kernel.h return kstrtoint_from_user(s, count, base, res); base 511 include/linux/kernel.h u64 int_pow(u64 base, unsigned int exp); base 216 include/linux/lockdep.h base : 24; base 33 include/linux/lp.h #define LP_BASE(x) lp_table[(x)].dev->port->base base 120 include/linux/lz4.h const unsigned char *base; base 34 include/linux/mbus.h u64 base; base 92 include/linux/mbus.h phys_addr_t base, size_t size, base 95 include/linux/mbus.h phys_addr_t base, size_t size); base 96 include/linux/mbus.h int mvebu_mbus_del_window(phys_addr_t base, size_t size); base 50 include/linux/memblock.h phys_addr_t base; base 111 include/linux/memblock.h int memblock_add_node(phys_addr_t base, phys_addr_t size, int nid); base 112 include/linux/memblock.h int memblock_add(phys_addr_t base, phys_addr_t size); base 113 include/linux/memblock.h int memblock_remove(phys_addr_t base, phys_addr_t size); base 114 include/linux/memblock.h int memblock_free(phys_addr_t base, phys_addr_t size); base 115 include/linux/memblock.h int memblock_reserve(phys_addr_t base, phys_addr_t size); base 118 include/linux/memblock.h phys_addr_t base, phys_addr_t size); base 119 include/linux/memblock.h int memblock_mark_hotplug(phys_addr_t base, phys_addr_t size); base 120 include/linux/memblock.h int memblock_clear_hotplug(phys_addr_t base, phys_addr_t size); base 121 include/linux/memblock.h int memblock_mark_mirror(phys_addr_t base, phys_addr_t size); base 122 include/linux/memblock.h int memblock_mark_nomap(phys_addr_t base, phys_addr_t size); base 123 include/linux/memblock.h int memblock_clear_nomap(phys_addr_t base, phys_addr_t size); base 131 include/linux/memblock.h phys_addr_t base, phys_addr_t size, base 147 include/linux/memblock.h void __memblock_free_late(phys_addr_t base, phys_addr_t size); base 315 include/linux/memblock.h int memblock_set_node(phys_addr_t base, phys_addr_t size, base 404 include/linux/memblock.h static inline void __init memblock_free_early(phys_addr_t base, base 407 include/linux/memblock.h memblock_free(base, size); base 410 include/linux/memblock.h static inline void __init memblock_free_early_nid(phys_addr_t base, base 413 include/linux/memblock.h memblock_free(base, size); base 416 include/linux/memblock.h static inline void __init memblock_free_late(phys_addr_t base, phys_addr_t size) base 418 include/linux/memblock.h __memblock_free_late(base, size); base 445 include/linux/memblock.h void memblock_cap_memory_range(phys_addr_t base, phys_addr_t size); base 449 include/linux/memblock.h bool memblock_is_region_memory(phys_addr_t base, phys_addr_t size); base 451 include/linux/memblock.h bool memblock_is_region_reserved(phys_addr_t base, phys_addr_t size); base 488 include/linux/memblock.h return PFN_UP(reg->base); base 499 include/linux/memblock.h return PFN_DOWN(reg->base + reg->size); base 510 include/linux/memblock.h return PFN_DOWN(reg->base); base 521 include/linux/memblock.h return PFN_UP(reg->base + reg->size); base 61 include/linux/mfd/asic3.h #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg) base 62 include/linux/mfd/asic3.h #define ASIC3_GPIO_OFFSET(base, reg) \ base 63 include/linux/mfd/asic3.h (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg) base 10 include/linux/mfd/bcm2835-pm.h void __iomem *base; base 94 include/linux/mfd/davinci_voicecodec.h void __iomem *base; base 111 include/linux/mfd/ipaq-micro.h void __iomem *base; base 3751 include/linux/mfd/palmas.h static inline int palmas_read(struct palmas *palmas, unsigned int base, base 3754 include/linux/mfd/palmas.h unsigned int addr = PALMAS_BASE_TO_REG(base, reg); base 3755 include/linux/mfd/palmas.h int slave_id = PALMAS_BASE_TO_SLAVE(base); base 3760 include/linux/mfd/palmas.h static inline int palmas_write(struct palmas *palmas, unsigned int base, base 3763 include/linux/mfd/palmas.h unsigned int addr = PALMAS_BASE_TO_REG(base, reg); base 3764 include/linux/mfd/palmas.h int slave_id = PALMAS_BASE_TO_SLAVE(base); base 3769 include/linux/mfd/palmas.h static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base, base 3772 include/linux/mfd/palmas.h unsigned int addr = PALMAS_BASE_TO_REG(base, reg); base 3773 include/linux/mfd/palmas.h int slave_id = PALMAS_BASE_TO_SLAVE(base); base 3779 include/linux/mfd/palmas.h static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base, base 3782 include/linux/mfd/palmas.h unsigned int addr = PALMAS_BASE_TO_REG(base, reg); base 3783 include/linux/mfd/palmas.h int slave_id = PALMAS_BASE_TO_SLAVE(base); base 3789 include/linux/mfd/palmas.h static inline int palmas_update_bits(struct palmas *palmas, unsigned int base, base 3792 include/linux/mfd/palmas.h unsigned int addr = PALMAS_BASE_TO_REG(base, reg); base 3793 include/linux/mfd/palmas.h int slave_id = PALMAS_BASE_TO_SLAVE(base); base 94 include/linux/mfd/sun4i-gpadc.h void __iomem *base; base 28 include/linux/mfd/tmio.h #define sd_config_write8(base, shift, reg, val) \ base 29 include/linux/mfd/tmio.h tmio_iowrite8((val), (base) + ((reg) << (shift))) base 30 include/linux/mfd/tmio.h #define sd_config_write16(base, shift, reg, val) \ base 31 include/linux/mfd/tmio.h tmio_iowrite16((val), (base) + ((reg) << (shift))) base 32 include/linux/mfd/tmio.h #define sd_config_write32(base, shift, reg, val) \ base 34 include/linux/mfd/tmio.h tmio_iowrite16((val), (base) + ((reg) << (shift))); \ base 35 include/linux/mfd/tmio.h tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \ base 85 include/linux/mfd/tmio.h int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); base 86 include/linux/mfd/tmio.h int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); base 196 include/linux/mfd/tps65010.h int base; base 1144 include/linux/mlx4/device.h int *base, u8 flags, u8 usage); base 93 include/linux/mmc/sh_mmcif.h static inline void sh_mmcif_boot_cmd_send(void __iomem *base, base 96 include/linux/mmc/sh_mmcif.h sh_mmcif_writel(base, MMCIF_CE_INT, 0); base 97 include/linux/mmc/sh_mmcif.h sh_mmcif_writel(base, MMCIF_CE_ARG, arg); base 98 include/linux/mmc/sh_mmcif.h sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd); base 101 include/linux/mmc/sh_mmcif.h static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask) base 107 include/linux/mmc/sh_mmcif.h tmp = sh_mmcif_readl(base, MMCIF_CE_INT); base 109 include/linux/mmc/sh_mmcif.h sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask); base 117 include/linux/mmc/sh_mmcif.h static inline int sh_mmcif_boot_cmd(void __iomem *base, base 120 include/linux/mmc/sh_mmcif.h sh_mmcif_boot_cmd_send(base, cmd, arg); base 121 include/linux/mmc/sh_mmcif.h return sh_mmcif_boot_cmd_poll(base, 0x00010000); base 124 include/linux/mmc/sh_mmcif.h static inline int sh_mmcif_boot_do_read_single(void __iomem *base, base 131 include/linux/mmc/sh_mmcif.h sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000); base 133 include/linux/mmc/sh_mmcif.h if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900) base 137 include/linux/mmc/sh_mmcif.h sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS); base 138 include/linux/mmc/sh_mmcif.h if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0) base 142 include/linux/mmc/sh_mmcif.h buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA); base 147 include/linux/mmc/sh_mmcif.h static inline int sh_mmcif_boot_do_read(void __iomem *base, base 156 include/linux/mmc/sh_mmcif.h sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, base 161 include/linux/mmc/sh_mmcif.h sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000); base 164 include/linux/mmc/sh_mmcif.h sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000); base 167 include/linux/mmc/sh_mmcif.h sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS); base 170 include/linux/mmc/sh_mmcif.h ret = sh_mmcif_boot_do_read_single(base, first_block + k, base 176 include/linux/mmc/sh_mmcif.h static inline void sh_mmcif_boot_init(void __iomem *base) base 179 include/linux/mmc/sh_mmcif.h sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON); base 180 include/linux/mmc/sh_mmcif.h sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF); base 183 include/linux/mmc/sh_mmcif.h sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); base 186 include/linux/mmc/sh_mmcif.h sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS); base 189 include/linux/mmc/sh_mmcif.h sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, base 194 include/linux/mmc/sh_mmcif.h sh_mmcif_boot_cmd(base, 0x00000040, 0); base 198 include/linux/mmc/sh_mmcif.h sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */ base 199 include/linux/mmc/sh_mmcif.h } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000) base 203 include/linux/mmc/sh_mmcif.h sh_mmcif_boot_cmd(base, 0x02806040, 0); base 206 include/linux/mmc/sh_mmcif.h sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000); base 309 include/linux/module.h void *base; base 542 include/linux/module.h return (unsigned long)mod->core_layout.base <= addr && base 543 include/linux/module.h addr < (unsigned long)mod->core_layout.base + mod->core_layout.size; base 549 include/linux/module.h return (unsigned long)mod->init_layout.base <= addr && base 550 include/linux/module.h addr < (unsigned long)mod->init_layout.base + mod->init_layout.size; base 60 include/linux/mpi.h int mpi_powm(MPI res, MPI base, MPI exp, MPI mod); base 302 include/linux/mtd/cfi.h uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base, base 340 include/linux/mtd/cfi.h int __xipram cfi_qry_present(struct map_info *map, __u32 base, base 342 include/linux/mtd/cfi.h int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map, base 344 include/linux/mtd/cfi.h void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map, base 17 include/linux/mtd/gen_probe.h int (*probe_chip)(struct map_info *map, __u32 base, base 532 include/linux/mtd/mtd.h static inline loff_t mtd_wunit_to_offset(struct mtd_info *mtd, loff_t base, base 535 include/linux/mtd/mtd.h return base + (wunit * mtd->writesize); base 84 include/linux/mtd/onenand.h void __iomem *base; base 163 include/linux/mtd/onenand.h (this->read_word(this->base + ONENAND_REG_SYS_CFG1)) base 165 include/linux/mtd/onenand.h (this->write_word(v, this->base + ONENAND_REG_SYS_CFG1)) base 1083 include/linux/mtd/rawnand.h struct nand_device base; base 1146 include/linux/mtd/rawnand.h return container_of(mtd, struct nand_chip, base.mtd); base 1151 include/linux/mtd/rawnand.h return &chip->base.mtd; base 1274 include/linux/mtd/rawnand.h WARN(nanddev_bits_per_cell(&chip->base) == 0, base 1276 include/linux/mtd/rawnand.h return nanddev_bits_per_cell(&chip->base) == 1; base 368 include/linux/mtd/spinand.h struct nand_device base; base 404 include/linux/mtd/spinand.h return container_of(mtd_to_nanddev(mtd), struct spinand_device, base); base 415 include/linux/mtd/spinand.h return nanddev_to_mtd(&spinand->base); base 426 include/linux/mtd/spinand.h return container_of(nand, struct spinand_device, base); base 438 include/linux/mtd/spinand.h return &spinand->base; base 451 include/linux/mtd/spinand.h nanddev_set_of_node(&spinand->base, np); base 919 include/linux/mv643xx.h extern void mv64340_irq_init(unsigned int base); base 280 include/linux/netfilter/x_tables.h int xt_check_entry_offsets(const void *base, const char *elems, base 528 include/linux/netfilter/x_tables.h int xt_compat_check_entry_offsets(const void *base, const char *elems, base 36 include/linux/nfsacl.h nfsacl_encode(struct xdr_buf *buf, unsigned int base, struct inode *inode, base 39 include/linux/nfsacl.h nfsacl_decode(struct xdr_buf *buf, unsigned int base, unsigned int *aclcnt, base 282 include/linux/ntb.h phys_addr_t *base, resource_size_t *size); base 913 include/linux/ntb.h phys_addr_t *base, resource_size_t *size) base 915 include/linux/ntb.h return ntb->ops->peer_mw_get_addr(ntb, widx, base, size); base 21 include/linux/nubus.h unsigned char *base; base 29 include/linux/nubus.h unsigned char *base; base 69 include/linux/of_fdt.h extern void early_init_dt_add_memory_arch(u64 base, u64 size); base 70 include/linux/of_fdt.h extern int early_init_dt_mark_hotplug_memory_arch(u64 base, u64 size); base 71 include/linux/of_fdt.h extern int early_init_dt_reserve_memory_arch(phys_addr_t base, phys_addr_t size, base 15 include/linux/of_reserved_mem.h phys_addr_t base; base 40 include/linux/of_reserved_mem.h phys_addr_t base, phys_addr_t size); base 52 include/linux/of_reserved_mem.h const char *uname, phys_addr_t base, phys_addr_t size) { } base 78 include/linux/omap-gpmc.h extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); base 190 include/linux/parport.h unsigned long base; /* base address */ base 278 include/linux/parport.h struct parport *parport_register_port(unsigned long base, int irq, int dma, base 13 include/linux/parport_pc.h #define EPPDATA(p) ((p)->base + 0x4) base 14 include/linux/parport_pc.h #define EPPADDR(p) ((p)->base + 0x3) base 15 include/linux/parport_pc.h #define CONTROL(p) ((p)->base + 0x2) base 16 include/linux/parport_pc.h #define STATUS(p) ((p)->base + 0x1) base 17 include/linux/parport_pc.h #define DATA(p) ((p)->base + 0x0) base 232 include/linux/parport_pc.h extern struct parport *parport_pc_probe_port(unsigned long base, base 62 include/linux/pinctrl/pinctrl.h unsigned int base; base 1 include/linux/platform_data/clk-integrator.h void integrator_impd1_clk_init(void __iomem *base, unsigned int id); base 14 include/linux/platform_data/clk-st.h void __iomem *base; base 1 include/linux/platform_data/clk-u300.h void __init u300_clk_init(void __iomem *base); base 53 include/linux/platform_data/dma-ep93xx.h void __iomem *base; base 21 include/linux/platform_data/gpio-davinci.h u32 base; base 20 include/linux/platform_data/usb-musb-ux500.h void ux500_add_usb(struct device *parent, resource_size_t base, base 34 include/linux/platform_data/x86/clk-pmc-atom.h void __iomem *base; base 178 include/linux/pm_domain.h struct pm_domain_data base; base 189 include/linux/pm_domain.h return container_of(pdd, struct generic_pm_domain_data, base); base 457 include/linux/pnp.h int pnp_possible_config(struct pnp_dev *dev, int type, resource_size_t base, base 488 include/linux/pnp.h resource_size_t base, base 171 include/linux/power/smartreflex.h void __iomem *base; base 293 include/linux/pwm.h int base; base 38 include/linux/qcom-geni-se.h void __iomem *base; base 246 include/linux/qcom-geni-se.h val = readl_relaxed(se->base + GENI_FW_REVISION_RO); base 265 include/linux/qcom-geni-se.h writel_relaxed(m_cmd, se->base + SE_GENI_M_CMD0); base 281 include/linux/qcom-geni-se.h s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); base 285 include/linux/qcom-geni-se.h writel_relaxed(s_cmd, se->base + SE_GENI_S_CMD0); base 298 include/linux/qcom-geni-se.h writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG); base 311 include/linux/qcom-geni-se.h writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG); base 323 include/linux/qcom-geni-se.h writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG); base 336 include/linux/qcom-geni-se.h writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG); base 352 include/linux/qcom-geni-se.h val = readl_relaxed(se->base + SE_HW_PARAM_0); base 370 include/linux/qcom-geni-se.h val = readl_relaxed(se->base + SE_HW_PARAM_0); base 388 include/linux/qcom-geni-se.h val = readl_relaxed(se->base + SE_HW_PARAM_1); base 370 include/linux/scatterlist.h struct sg_page_iter base; base 395 include/linux/scatterlist.h return sg_dma_address(dma_iter->base.sg) + base 396 include/linux/scatterlist.h (dma_iter->base.sg_pgoffset << PAGE_SHIFT); base 423 include/linux/scatterlist.h for (__sg_page_iter_start(&(dma_iter)->base, sglist, dma_nents, \ base 24 include/linux/seqno-fence.h struct dma_fence base; base 46 include/linux/seqno-fence.h return container_of(fence, struct seqno_fence, base); base 102 include/linux/seqno-fence.h dma_fence_init(&fence->base, &seqno_fence_ops, lock, context, seqno); base 230 include/linux/sfp.h struct sfp_eeprom_base base; base 17 include/linux/sh_clk.h void __iomem *base; base 9 include/linux/soc/actions/owl-sps.h int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable); base 7 include/linux/sort.h void sort_r(void *base, size_t num, size_t size, base 12 include/linux/sort.h void sort(void *base, size_t num, size_t size, base 24 include/linux/spi/max7301.h unsigned base; base 7 include/linux/spi/mc33880.h unsigned base; base 17 include/linux/spi/mcp23s08.h unsigned base; base 122 include/linux/spi/mxs-spi.h void __iomem *base; base 180 include/linux/sunrpc/clnt.h unsigned int base, unsigned int len, base 290 include/linux/sunrpc/gss_krb5.h xdr_extend_head(struct xdr_buf *buf, unsigned int base, unsigned int shiftlen); base 220 include/linux/sunrpc/xdr.h extern int xdr_decode_array2(struct xdr_buf *buf, unsigned int base, base 222 include/linux/sunrpc/xdr.h extern int xdr_encode_array2(struct xdr_buf *buf, unsigned int base, base 258 include/linux/sunrpc/xdr.h unsigned int base, unsigned int len); base 32 include/linux/superhyway.h int (*read_vcr)(unsigned long base, struct superhyway_vcr_info *vcr); base 33 include/linux/superhyway.h int (*write_vcr)(unsigned long base, struct superhyway_vcr_info vcr); base 82 include/linux/superhyway.h superhyway_read_vcr(struct superhyway_device *dev, unsigned long base, base 85 include/linux/superhyway.h return dev->bus->ops->read_vcr(base, vcr); base 89 include/linux/superhyway.h superhyway_write_vcr(struct superhyway_device *dev, unsigned long base, base 92 include/linux/superhyway.h return dev->bus->ops->write_vcr(base, vcr); base 100 include/linux/superhyway.h int superhyway_add_device(unsigned long base, struct superhyway_device *, struct superhyway_bus *); base 41 include/linux/timekeeper_internal.h ktime_t base; base 65 include/linux/usb/renesas_usbhs.h void __iomem *base, int enable); base 52 include/linux/ww_mutex.h struct mutex base; base 73 include/linux/ww_mutex.h { .base = __MUTEX_INITIALIZER(lockname.base) \ base 98 include/linux/ww_mutex.h __mutex_init(&lock->base, ww_class->mutex_name, &ww_class->mutex_key); base 345 include/linux/ww_mutex.h return mutex_trylock(&lock->base); base 358 include/linux/ww_mutex.h mutex_destroy(&lock->base); base 369 include/linux/ww_mutex.h return mutex_is_locked(&lock->base); base 597 include/media/demux.h u64 *stc, unsigned int *base); base 97 include/media/v4l2-fwnode.h struct fwnode_endpoint base; base 378 include/misc/ocxl.h u16 *base, u16 *enabled, u16 *supported); base 167 include/net/inet_sock.h struct inet_cork base; base 98 include/net/inetpeer.h struct inet_peer *inet_getpeer(struct inet_peer_base *base, base 102 include/net/inetpeer.h static inline struct inet_peer *inet_getpeer_v4(struct inet_peer_base *base, base 111 include/net/inetpeer.h return inet_getpeer(base, &daddr, create); base 114 include/net/inetpeer.h static inline struct inet_peer *inet_getpeer_v6(struct inet_peer_base *base, base 122 include/net/inetpeer.h return inet_getpeer(base, &daddr, create); base 242 include/net/ip.h return __ip_make_skb(sk, fl4, &sk->sk_write_queue, &inet_sk(sk)->cork.base); base 57 include/net/ip6_checksum.h __wsum base) base 59 include/net/ip6_checksum.h return csum_ipv6_magic(saddr, daddr, len, IPPROTO_TCP, base); base 91 include/net/ip6_checksum.h __wsum base) base 93 include/net/ip6_checksum.h return csum_ipv6_magic(saddr, daddr, len, IPPROTO_UDP, base); base 351 include/net/neighbour.h unsigned long neigh_rand_reach_time(unsigned long base); base 51 include/net/netfilter/nf_tables_core.h enum nft_payload_bases base:8; base 58 include/net/netfilter/nf_tables_core.h enum nft_payload_bases base:8; base 145 include/net/pkt_cls.h __tcf_bind_filter(struct Qdisc *q, struct tcf_result *r, unsigned long base) base 149 include/net/pkt_cls.h cl = q->ops->cl_ops->bind_tcf(q, base, r->classid); base 156 include/net/pkt_cls.h tcf_bind_filter(struct tcf_proto *tp, struct tcf_result *r, unsigned long base) base 166 include/net/pkt_cls.h __tcf_bind_filter(q, r, base); base 1278 include/net/sctp/structs.h struct sctp_ep_common base; base 1349 include/net/sctp/structs.h static inline struct sctp_endpoint *sctp_ep(struct sctp_ep_common *base) base 1353 include/net/sctp/structs.h ep = container_of(base, struct sctp_endpoint, base); base 1560 include/net/sctp/structs.h struct sctp_ep_common base; base 2091 include/net/sctp/structs.h static inline struct sctp_association *sctp_assoc(struct sctp_ep_common *base) base 2095 include/net/sctp/structs.h asoc = container_of(base, struct sctp_association, base); base 1336 include/net/tcp.h __be32 daddr, __wsum base) base 1338 include/net/tcp.h return csum_tcpudp_magic(saddr, daddr, len, IPPROTO_TCP, base); base 149 include/net/udp.h __be32 daddr, __wsum base) base 151 include/net/udp.h return csum_tcpudp_magic(saddr, daddr, len, IPPROTO_UDP, base); base 384 include/pcmcia/cistpl.h u_int base; base 424 include/pcmcia/cistpl.h u_int base; base 234 include/rdma/ib_addr.h if (cmd.base.speed >= 40000) base 236 include/rdma/ib_addr.h else if (cmd.base.speed >= 30000) base 238 include/rdma/ib_addr.h else if (cmd.base.speed >= 20000) base 240 include/rdma/ib_addr.h else if (cmd.base.speed >= 10000) base 670 include/scsi/scsi_host.h unsigned long base; base 124 include/soc/nps/common.h u32 base:8, cl_x:4, cl_y:4, base 134 include/soc/nps/common.h u32 base:7, blkid:11, reg:12, __reserved:2; base 344 include/soc/tegra/bpmp-abi.h uint32_t base; base 372 include/soc/tegra/bpmp-abi.h uint32_t base; base 507 include/soc/tegra/bpmp-abi.h uint32_t base; base 44 include/sound/aess.h static inline void aess_enable_autogating(void __iomem *base) base 50 include/sound/aess.h writel(v, base + AESS_AUTO_GATING_ENABLE_OFFSET); base 23 include/sound/snd_wavefront.h unsigned long base; /* I/O port address */ base 52 include/sound/snd_wavefront.h unsigned long base; /* low i/o port address */ base 55 include/sound/snd_wavefront.h #define mpu_data_port base base 56 include/sound/snd_wavefront.h #define mpu_command_port base + 1 /* write semantics */ base 57 include/sound/snd_wavefront.h #define mpu_status_port base + 1 /* read semantics */ base 58 include/sound/snd_wavefront.h #define data_port base + 2 base 59 include/sound/snd_wavefront.h #define status_port base + 3 /* read semantics */ base 60 include/sound/snd_wavefront.h #define control_port base + 3 /* write semantics */ base 61 include/sound/snd_wavefront.h #define block_port base + 4 /* 16 bit, writeonly */ base 62 include/sound/snd_wavefront.h #define last_block_port base + 6 /* 16 bit, writeonly */ base 70 include/sound/snd_wavefront.h #define fx_status base + 8 base 71 include/sound/snd_wavefront.h #define fx_op base + 8 base 72 include/sound/snd_wavefront.h #define fx_lcr base + 9 base 73 include/sound/snd_wavefront.h #define fx_dsp_addr base + 0xa base 74 include/sound/snd_wavefront.h #define fx_dsp_page base + 0xb base 75 include/sound/snd_wavefront.h #define fx_dsp_lsb base + 0xc base 76 include/sound/snd_wavefront.h #define fx_dsp_msb base + 0xd base 77 include/sound/snd_wavefront.h #define fx_mod_addr base + 0xe base 78 include/sound/snd_wavefront.h #define fx_mod_data base + 0xf base 283 include/sound/soc-dai.h unsigned int base; base 301 include/sound/soc.h {.base = xbase, .num_regs = xregs }) } base 308 include/sound/soc.h {.base = xbase, .num_regs = xregs, \ base 1176 include/sound/soc.h int base; base 1058 include/trace/events/rpcrdma.h __field(const void *, base) base 1066 include/trace/events/rpcrdma.h __entry->base = rqst->rq_rcv_buf.head[0].iov_base; base 1073 include/trace/events/rpcrdma.h __entry->base, __entry->len, __entry->hdrlen base 73 include/trace/events/sctp.h __entry->bind_port = ep->base.bind_addr.port; base 983 include/uapi/drm/drm.h struct drm_event base; base 995 include/uapi/drm/drm.h struct drm_event base; base 402 include/uapi/drm/exynos_drm.h struct drm_event base; base 411 include/uapi/drm/exynos_drm.h struct drm_event base; base 1649 include/uapi/drm/i915_drm.h struct i915_user_extension base; base 1661 include/uapi/drm/i915_drm.h struct i915_user_extension base; \ base 1685 include/uapi/drm/i915_drm.h struct i915_user_extension base; base 1699 include/uapi/drm/i915_drm.h struct i915_user_extension base; \ base 1722 include/uapi/drm/i915_drm.h struct i915_user_extension base; base 1728 include/uapi/drm/i915_drm.h struct i915_user_extension base; base 704 include/uapi/drm/vmwgfx_drm.h struct drm_event base; base 1150 include/uapi/drm/vmwgfx_drm.h struct drm_vmw_gb_surface_create_req base; base 210 include/uapi/linux/dvb/dmx.h unsigned int base; base 751 include/uapi/linux/fuse.h uint64_t base; base 121 include/uapi/linux/kd.h unsigned char diacr, base, result; base 131 include/uapi/linux/kd.h unsigned int diacr, base, result; base 82 include/uapi/linux/keyctl.h __s32 base; base 76 include/uapi/linux/phonet.h } base; base 87 include/uapi/linux/phonet.h #define pn_submsg_id pn_msg_u.base.pn_submsg_id base 90 include/uapi/linux/phonet.h #define pn_data pn_msg_u.base.pn_data base 1098 include/uapi/linux/videodev2.h void *base; base 260 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_query_device_resp base; base 436 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_create_cq_resp base; base 647 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_create_qp_resp base; base 743 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_modify_qp base; base 247 include/uapi/sound/asequencer.h unsigned int base; base 440 include/uapi/sound/asoc.h __le32 base; base 22 include/video/sisfb.h extern void sis_free(u32 base); base 23 include/video/sisfb.h extern void sis_free_new(struct pci_dev *pdev, u32 base); base 1424 ipc/shm.c struct file *file, *base; base 1513 ipc/shm.c base = get_file(shp->shm_file); base 1515 ipc/shm.c size = i_size_read(file_inode(base)); base 1522 ipc/shm.c fput(base); base 1526 ipc/shm.c file = alloc_file_clone(base, f_flags, base 1527 ipc/shm.c is_file_hugepages(base) ? base 1533 ipc/shm.c fput(base); base 1539 ipc/shm.c sfd->file = base; base 172 kernel/bpf/arraymap.c u64 base = (unsigned long)array->value; base 177 kernel/bpf/arraymap.c if (imm < base || imm >= base + range) base 180 kernel/bpf/arraymap.c *off = imm - base; base 367 kernel/bpf/helpers.c unsigned int base = flags & BPF_STRTOX_BASE_MASK; base 377 kernel/bpf/helpers.c if (base != 0 && base != 8 && base != 10 && base != 16) base 400 kernel/bpf/helpers.c cur_buf = _parse_integer_fixup_radix(cur_buf, &base); base 401 kernel/bpf/helpers.c val_len = _parse_integer(cur_buf, base, res); base 2047 kernel/debug/kdb/kdb_main.c kdb_printf(" 0x%px", mod->core_layout.base); base 309 kernel/dma/coherent.c ret = dma_init_coherent_memory(rmem->base, rmem->base, base 313 kernel/dma/coherent.c &rmem->base, (unsigned long)rmem->size / SZ_1M); base 357 kernel/dma/coherent.c &rmem->base, (unsigned long)rmem->size / SZ_1M); base 162 kernel/dma/contiguous.c int __init dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base, base 168 kernel/dma/contiguous.c ret = cma_declare_contiguous(base, size, limit, 0, 0, fixed, base 311 kernel/dma/contiguous.c if ((rmem->base & mask) || (rmem->size & mask)) { base 316 kernel/dma/contiguous.c err = cma_init_reserved_mem(rmem->base, rmem->size, 0, rmem->name, &cma); base 322 kernel/dma/contiguous.c dma_contiguous_early_fixup(rmem->base, rmem->size); base 331 kernel/dma/contiguous.c &rmem->base, (unsigned long)rmem->size / SZ_1M); base 846 kernel/events/ring_buffer.c void *base; base 852 kernel/events/ring_buffer.c base = rb->user_page; base 855 kernel/events/ring_buffer.c perf_mmap_unmark_page(base + (i * PAGE_SIZE)); base 857 kernel/events/ring_buffer.c vfree(base); base 3982 kernel/futex.c compat_uptr_t base = ptr_to_compat(entry); base 3983 kernel/futex.c void __user *uaddr = compat_ptr(base + futex_offset); base 183 kernel/irq/devres.c int base; base 189 kernel/irq/devres.c base = __irq_alloc_descs(irq, from, cnt, node, owner, affinity); base 190 kernel/irq/devres.c if (base < 0) { base 192 kernel/irq/devres.c return base; base 195 kernel/irq/devres.c dr->from = base; base 199 kernel/irq/devres.c return base; base 284 kernel/irq/ipi.c unsigned int base = data->irq; base 287 kernel/irq/ipi.c unsigned irq = base + cpu - data->common->ipi_offset; base 949 kernel/locking/lockdep.c for (i = chain->base; i < chain->base + chain->depth; i++) base 2634 kernel/locking/lockdep.c return lock_classes + chain_hlocks[chain->base + i]; base 2699 kernel/locking/lockdep.c class_id = chain_hlocks[chain->base + i]; base 2753 kernel/locking/lockdep.c if (DEBUG_LOCKS_WARN_ON(chain_hlocks[chain->base + j] != id)) { base 2832 kernel/locking/lockdep.c chain->base = nr_chain_hlocks; base 2835 kernel/locking/lockdep.c chain_hlocks[chain->base + j] = lock_id; base 2837 kernel/locking/lockdep.c chain_hlocks[chain->base + j] = class - lock_classes; base 4782 kernel/locking/lockdep.c for (i = chain->base; i < chain->base + chain->depth; i++) { base 4788 kernel/locking/lockdep.c (chain->base + chain->depth - i) * base 4802 kernel/locking/lockdep.c for (i = chain->base; i < chain->base + chain->depth; i++) base 487 kernel/locking/mutex.c if (likely(!(atomic_long_read(&lock->base.owner) & MUTEX_FLAG_WAITERS))) base 494 kernel/locking/mutex.c spin_lock(&lock->base.wait_lock); base 495 kernel/locking/mutex.c __ww_mutex_check_waiters(&lock->base, ctx); base 496 kernel/locking/mutex.c spin_unlock(&lock->base.wait_lock); base 507 kernel/locking/mutex.c ww = container_of(lock, struct ww_mutex, base); base 770 kernel/locking/mutex.c mutex_unlock(&lock->base); base 782 kernel/locking/mutex.c ww = container_of(lock, struct ww_mutex, base); base 808 kernel/locking/mutex.c struct ww_mutex *ww = container_of(lock, struct ww_mutex, base); base 908 kernel/locking/mutex.c struct ww_mutex *ww = container_of(lock, struct ww_mutex, base); base 941 kernel/locking/mutex.c ww = container_of(lock, struct ww_mutex, base); base 1190 kernel/locking/mutex.c ret = __ww_mutex_lock(&lock->base, TASK_UNINTERRUPTIBLE, base 1206 kernel/locking/mutex.c ret = __ww_mutex_lock(&lock->base, TASK_INTERRUPTIBLE, base 1382 kernel/locking/mutex.c return __ww_mutex_lock(&lock->base, TASK_UNINTERRUPTIBLE, 0, NULL, base 1390 kernel/locking/mutex.c return __ww_mutex_lock(&lock->base, TASK_INTERRUPTIBLE, 0, NULL, base 1432 kernel/locking/mutex.c if (__mutex_trylock_fast(&lock->base)) { base 1447 kernel/locking/mutex.c if (__mutex_trylock_fast(&lock->base)) { base 133 kernel/locking/qspinlock.c struct mcs_spinlock *grab_mcs_node(struct mcs_spinlock *base, int idx) base 135 kernel/locking/qspinlock.c return &((struct qnode *)base + idx)->mcs; base 109 kernel/module.c return (unsigned long)layout->base; base 232 kernel/module.c static void __mod_update_bounds(void *base, unsigned int size) base 234 kernel/module.c unsigned long min = (unsigned long)base; base 245 kernel/module.c __mod_update_bounds(mod->core_layout.base, mod->core_layout.size); base 247 kernel/module.c __mod_update_bounds(mod->init_layout.base, mod->init_layout.size); base 398 kernel/module.c #define symversion(base, idx) NULL base 400 kernel/module.c #define symversion(base, idx) ((base != NULL) ? ((base) + (idx)) : NULL) base 1963 kernel/module.c BUG_ON((unsigned long)layout->base & (PAGE_SIZE-1)); base 1965 kernel/module.c set_memory((unsigned long)layout->base, base 1973 kernel/module.c BUG_ON((unsigned long)layout->base & (PAGE_SIZE-1)); base 1976 kernel/module.c set_memory((unsigned long)layout->base + layout->text_size, base 1983 kernel/module.c BUG_ON((unsigned long)layout->base & (PAGE_SIZE-1)); base 1986 kernel/module.c set_memory((unsigned long)layout->base + layout->ro_size, base 1993 kernel/module.c BUG_ON((unsigned long)layout->base & (PAGE_SIZE-1)); base 1996 kernel/module.c set_memory((unsigned long)layout->base + layout->ro_after_init_size, base 2018 kernel/module.c set_vm_flush_reset_perms(mod->core_layout.base); base 2019 kernel/module.c set_vm_flush_reset_perms(mod->init_layout.base); base 2230 kernel/module.c module_memfree(mod->init_layout.base); base 2235 kernel/module.c lockdep_free_key_range(mod->core_layout.base, mod->core_layout.size); base 2238 kernel/module.c module_memfree(mod->core_layout.base); base 2755 kernel/module.c mod->kallsyms = mod->init_layout.base + info->mod_kallsyms_init_off; base 2761 kernel/module.c mod->kallsyms->typetab = mod->init_layout.base + info->init_typeoffs; base 2767 kernel/module.c mod->core_kallsyms.symtab = dst = mod->core_layout.base + info->symoffs; base 2768 kernel/module.c mod->core_kallsyms.strtab = s = mod->core_layout.base + info->stroffs; base 2769 kernel/module.c mod->core_kallsyms.typetab = mod->core_layout.base + info->core_typeoffs; base 3269 kernel/module.c mod->core_layout.base = ptr; base 3281 kernel/module.c module_memfree(mod->core_layout.base); base 3285 kernel/module.c mod->init_layout.base = ptr; base 3287 kernel/module.c mod->init_layout.base = NULL; base 3299 kernel/module.c dest = mod->init_layout.base base 3302 kernel/module.c dest = mod->core_layout.base + shdr->sh_entsize; base 3369 kernel/module.c if (mod->init_layout.base) base 3370 kernel/module.c flush_icache_range((unsigned long)mod->init_layout.base, base 3371 kernel/module.c (unsigned long)mod->init_layout.base base 3373 kernel/module.c flush_icache_range((unsigned long)mod->core_layout.base, base 3374 kernel/module.c (unsigned long)mod->core_layout.base + mod->core_layout.size); base 3467 kernel/module.c module_memfree(mod->init_layout.base); base 3468 kernel/module.c module_memfree(mod->core_layout.base); base 3571 kernel/module.c freeinit->module_init = mod->init_layout.base; base 3619 kernel/module.c ftrace_free_mem(mod, mod->init_layout.base, mod->init_layout.base + base 3632 kernel/module.c mod->init_layout.base = NULL; base 3971 kernel/module.c lockdep_free_key_range(mod->core_layout.base, mod->core_layout.size); base 4064 kernel/module.c nextval = (unsigned long)mod->init_layout.base+mod->init_layout.text_size; base 4066 kernel/module.c nextval = (unsigned long)mod->core_layout.base+mod->core_layout.text_size; base 4358 kernel/module.c value = m->private ? NULL : mod->core_layout.base; base 4517 kernel/module.c if (!within(addr, mod->init_layout.base, mod->init_layout.text_size) base 4518 kernel/module.c && !within(addr, mod->core_layout.base, mod->core_layout.text_size)) base 1567 kernel/power/snapshot.c static unsigned long __fraction(u64 x, u64 multiplier, u64 base) base 1570 kernel/power/snapshot.c do_div(x, base); base 1648 kernel/resource.c struct resource *base, unsigned long size, const char *name) base 1654 kernel/resource.c end = min_t(unsigned long, base->end, (1UL << MAX_PHYSMEM_BITS) - 1); base 1657 kernel/resource.c for (; addr > size && addr >= base->start; addr -= size) { base 1687 kernel/resource.c struct resource *base, unsigned long size) base 1689 kernel/resource.c return __request_free_mem_region(dev, base, size, dev_name(dev)); base 1693 kernel/resource.c struct resource *request_free_mem_region(struct resource *base, base 1696 kernel/resource.c return __request_free_mem_region(NULL, base, size, name); base 291 kernel/sched/core.c time = ktime_add_ns(timer->base->get_time(), delta); base 659 kernel/signal.c hrtimer_forward(tmr, tmr->base->get_time(), base 2162 kernel/sysctl.c static int strtoul_lenient(const char *cp, char **endp, unsigned int base, base 2168 kernel/sysctl.c cp = _parse_integer_fixup_radix(cp, &base); base 2169 kernel/sysctl.c rv = _parse_integer(cp, base, &result); base 169 kernel/time/alarmtimer.c static void alarmtimer_enqueue(struct alarm_base *base, struct alarm *alarm) base 172 kernel/time/alarmtimer.c timerqueue_del(&base->timerqueue, &alarm->node); base 174 kernel/time/alarmtimer.c timerqueue_add(&base->timerqueue, &alarm->node); base 187 kernel/time/alarmtimer.c static void alarmtimer_dequeue(struct alarm_base *base, struct alarm *alarm) base 192 kernel/time/alarmtimer.c timerqueue_del(&base->timerqueue, &alarm->node); base 209 kernel/time/alarmtimer.c struct alarm_base *base = &alarm_bases[alarm->type]; base 214 kernel/time/alarmtimer.c spin_lock_irqsave(&base->lock, flags); base 215 kernel/time/alarmtimer.c alarmtimer_dequeue(base, alarm); base 216 kernel/time/alarmtimer.c spin_unlock_irqrestore(&base->lock, flags); base 219 kernel/time/alarmtimer.c restart = alarm->function(alarm, base->gettime()); base 221 kernel/time/alarmtimer.c spin_lock_irqsave(&base->lock, flags); base 224 kernel/time/alarmtimer.c alarmtimer_enqueue(base, alarm); base 227 kernel/time/alarmtimer.c spin_unlock_irqrestore(&base->lock, flags); base 229 kernel/time/alarmtimer.c trace_alarmtimer_fired(alarm, base->gettime()); base 236 kernel/time/alarmtimer.c struct alarm_base *base = &alarm_bases[alarm->type]; base 237 kernel/time/alarmtimer.c return ktime_sub(alarm->node.expires, base->gettime()); base 273 kernel/time/alarmtimer.c struct alarm_base *base = &alarm_bases[i]; base 277 kernel/time/alarmtimer.c spin_lock_irqsave(&base->lock, flags); base 278 kernel/time/alarmtimer.c next = timerqueue_getnext(&base->timerqueue); base 279 kernel/time/alarmtimer.c spin_unlock_irqrestore(&base->lock, flags); base 282 kernel/time/alarmtimer.c delta = ktime_sub(next->expires, base->gettime()); base 367 kernel/time/alarmtimer.c struct alarm_base *base = &alarm_bases[alarm->type]; base 370 kernel/time/alarmtimer.c spin_lock_irqsave(&base->lock, flags); base 372 kernel/time/alarmtimer.c alarmtimer_enqueue(base, alarm); base 374 kernel/time/alarmtimer.c spin_unlock_irqrestore(&base->lock, flags); base 376 kernel/time/alarmtimer.c trace_alarmtimer_start(alarm, base->gettime()); base 387 kernel/time/alarmtimer.c struct alarm_base *base = &alarm_bases[alarm->type]; base 389 kernel/time/alarmtimer.c start = ktime_add_safe(start, base->gettime()); base 396 kernel/time/alarmtimer.c struct alarm_base *base = &alarm_bases[alarm->type]; base 399 kernel/time/alarmtimer.c spin_lock_irqsave(&base->lock, flags); base 402 kernel/time/alarmtimer.c alarmtimer_enqueue(base, alarm); base 403 kernel/time/alarmtimer.c spin_unlock_irqrestore(&base->lock, flags); base 416 kernel/time/alarmtimer.c struct alarm_base *base = &alarm_bases[alarm->type]; base 420 kernel/time/alarmtimer.c spin_lock_irqsave(&base->lock, flags); base 423 kernel/time/alarmtimer.c alarmtimer_dequeue(base, alarm); base 424 kernel/time/alarmtimer.c spin_unlock_irqrestore(&base->lock, flags); base 426 kernel/time/alarmtimer.c trace_alarmtimer_cancel(alarm, base->gettime()); base 484 kernel/time/alarmtimer.c struct alarm_base *base = &alarm_bases[alarm->type]; base 486 kernel/time/alarmtimer.c return alarm_forward(alarm, base->gettime(), interval); base 494 kernel/time/alarmtimer.c struct alarm_base *base; base 500 kernel/time/alarmtimer.c base = &alarm_bases[ALARM_REALTIME]; base 504 kernel/time/alarmtimer.c base = &alarm_bases[ALARM_BOOTTIME]; base 512 kernel/time/alarmtimer.c delta = ktime_sub(absexp, base->gettime()); base 641 kernel/time/alarmtimer.c struct alarm_base *base = &alarm_bases[alarm->type]; base 644 kernel/time/alarmtimer.c expires = ktime_add_safe(expires, base->gettime()); base 677 kernel/time/alarmtimer.c struct alarm_base *base = &alarm_bases[clock2alarm(which_clock)]; base 682 kernel/time/alarmtimer.c *tp = ktime_to_timespec64(base->gettime()); base 143 kernel/time/hrtimer.c static inline bool is_migration_base(struct hrtimer_clock_base *base) base 145 kernel/time/hrtimer.c return base == &migration_base; base 164 kernel/time/hrtimer.c struct hrtimer_clock_base *base; base 167 kernel/time/hrtimer.c base = READ_ONCE(timer->base); base 168 kernel/time/hrtimer.c if (likely(base != &migration_base)) { base 169 kernel/time/hrtimer.c raw_spin_lock_irqsave(&base->cpu_base->lock, *flags); base 170 kernel/time/hrtimer.c if (likely(base == timer->base)) base 171 kernel/time/hrtimer.c return base; base 173 kernel/time/hrtimer.c raw_spin_unlock_irqrestore(&base->cpu_base->lock, *flags); base 198 kernel/time/hrtimer.c struct hrtimer_cpu_base *get_target_base(struct hrtimer_cpu_base *base, base 205 kernel/time/hrtimer.c return base; base 221 kernel/time/hrtimer.c switch_hrtimer_base(struct hrtimer *timer, struct hrtimer_clock_base *base, base 226 kernel/time/hrtimer.c int basenum = base->index; base 233 kernel/time/hrtimer.c if (base != new_base) { base 244 kernel/time/hrtimer.c return base; base 247 kernel/time/hrtimer.c WRITE_ONCE(timer->base, &migration_base); base 248 kernel/time/hrtimer.c raw_spin_unlock(&base->cpu_base->lock); base 254 kernel/time/hrtimer.c raw_spin_lock(&base->cpu_base->lock); base 256 kernel/time/hrtimer.c WRITE_ONCE(timer->base, base); base 259 kernel/time/hrtimer.c WRITE_ONCE(timer->base, new_base); base 272 kernel/time/hrtimer.c static inline bool is_migration_base(struct hrtimer_clock_base *base) base 280 kernel/time/hrtimer.c struct hrtimer_clock_base *base = timer->base; base 282 kernel/time/hrtimer.c raw_spin_lock_irqsave(&base->cpu_base->lock, *flags); base 284 kernel/time/hrtimer.c return base; base 500 kernel/time/hrtimer.c #define for_each_active_base(base, cpu_base, active) \ base 501 kernel/time/hrtimer.c while ((base = __next_base((cpu_base), &(active)))) base 508 kernel/time/hrtimer.c struct hrtimer_clock_base *base; base 511 kernel/time/hrtimer.c for_each_active_base(base, cpu_base, active) { base 515 kernel/time/hrtimer.c next = timerqueue_getnext(&base->active); base 525 kernel/time/hrtimer.c expires = ktime_sub(hrtimer_get_expires(timer), base->offset); base 592 kernel/time/hrtimer.c static inline ktime_t hrtimer_update_base(struct hrtimer_cpu_base *base) base 594 kernel/time/hrtimer.c ktime_t *offs_real = &base->clock_base[HRTIMER_BASE_REALTIME].offset; base 595 kernel/time/hrtimer.c ktime_t *offs_boot = &base->clock_base[HRTIMER_BASE_BOOTTIME].offset; base 596 kernel/time/hrtimer.c ktime_t *offs_tai = &base->clock_base[HRTIMER_BASE_TAI].offset; base 598 kernel/time/hrtimer.c ktime_t now = ktime_get_update_offsets_now(&base->clock_was_set_seq, base 601 kernel/time/hrtimer.c base->clock_base[HRTIMER_BASE_REALTIME_SOFT].offset = *offs_real; base 602 kernel/time/hrtimer.c base->clock_base[HRTIMER_BASE_BOOTTIME_SOFT].offset = *offs_boot; base 603 kernel/time/hrtimer.c base->clock_base[HRTIMER_BASE_TAI_SOFT].offset = *offs_tai; base 713 kernel/time/hrtimer.c struct hrtimer_cpu_base *base = this_cpu_ptr(&hrtimer_bases); base 715 kernel/time/hrtimer.c if (!__hrtimer_hres_active(base)) base 718 kernel/time/hrtimer.c raw_spin_lock(&base->lock); base 719 kernel/time/hrtimer.c hrtimer_update_base(base); base 720 kernel/time/hrtimer.c hrtimer_force_reprogram(base, 0); base 721 kernel/time/hrtimer.c raw_spin_unlock(&base->lock); base 729 kernel/time/hrtimer.c struct hrtimer_cpu_base *base = this_cpu_ptr(&hrtimer_bases); base 733 kernel/time/hrtimer.c base->cpu); base 736 kernel/time/hrtimer.c base->hres_active = 1; base 778 kernel/time/hrtimer.c struct hrtimer_clock_base *base = timer->base; base 779 kernel/time/hrtimer.c ktime_t expires = ktime_sub(hrtimer_get_expires(timer), base->offset); base 798 kernel/time/hrtimer.c struct hrtimer_cpu_base *timer_cpu_base = base->cpu_base; base 818 kernel/time/hrtimer.c if (base->cpu_base != cpu_base) base 898 kernel/time/hrtimer.c raw_spin_unlock_irqrestore(&timer->base->cpu_base->lock, *flags); base 962 kernel/time/hrtimer.c struct hrtimer_clock_base *base, base 967 kernel/time/hrtimer.c base->cpu_base->active_bases |= 1 << base->index; base 972 kernel/time/hrtimer.c return timerqueue_add(&base->active, &timer->node); base 986 kernel/time/hrtimer.c struct hrtimer_clock_base *base, base 989 kernel/time/hrtimer.c struct hrtimer_cpu_base *cpu_base = base->cpu_base; base 997 kernel/time/hrtimer.c if (!timerqueue_del(&base->active, &timer->node)) base 998 kernel/time/hrtimer.c cpu_base->active_bases &= ~(1 << base->index); base 1016 kernel/time/hrtimer.c remove_hrtimer(struct hrtimer *timer, struct hrtimer_clock_base *base, bool restart) base 1032 kernel/time/hrtimer.c reprogram = base->cpu_base == this_cpu_ptr(&hrtimer_bases); base 1037 kernel/time/hrtimer.c __remove_hrtimer(timer, base, state, reprogram); base 1086 kernel/time/hrtimer.c struct hrtimer_clock_base *base) base 1091 kernel/time/hrtimer.c remove_hrtimer(timer, base, true); base 1094 kernel/time/hrtimer.c tim = ktime_add_safe(tim, base->get_time()); base 1101 kernel/time/hrtimer.c new_base = switch_hrtimer_base(timer, base, mode & HRTIMER_MODE_PINNED); base 1118 kernel/time/hrtimer.c struct hrtimer_clock_base *base; base 1131 kernel/time/hrtimer.c base = lock_hrtimer_base(timer, &flags); base 1133 kernel/time/hrtimer.c if (__hrtimer_start_range_ns(timer, tim, delta_ns, mode, base)) base 1153 kernel/time/hrtimer.c struct hrtimer_clock_base *base; base 1166 kernel/time/hrtimer.c base = lock_hrtimer_base(timer, &flags); base 1169 kernel/time/hrtimer.c ret = remove_hrtimer(timer, base, false); base 1179 kernel/time/hrtimer.c static void hrtimer_cpu_base_init_expiry_lock(struct hrtimer_cpu_base *base) base 1181 kernel/time/hrtimer.c spin_lock_init(&base->softirq_expiry_lock); base 1184 kernel/time/hrtimer.c static void hrtimer_cpu_base_lock_expiry(struct hrtimer_cpu_base *base) base 1186 kernel/time/hrtimer.c spin_lock(&base->softirq_expiry_lock); base 1189 kernel/time/hrtimer.c static void hrtimer_cpu_base_unlock_expiry(struct hrtimer_cpu_base *base) base 1191 kernel/time/hrtimer.c spin_unlock(&base->softirq_expiry_lock); base 1231 kernel/time/hrtimer.c struct hrtimer_clock_base *base = READ_ONCE(timer->base); base 1237 kernel/time/hrtimer.c if (!timer->is_soft || is_migration_base(base)) { base 1249 kernel/time/hrtimer.c atomic_inc(&base->cpu_base->timer_waiters); base 1250 kernel/time/hrtimer.c spin_lock_bh(&base->cpu_base->softirq_expiry_lock); base 1251 kernel/time/hrtimer.c atomic_dec(&base->cpu_base->timer_waiters); base 1252 kernel/time/hrtimer.c spin_unlock_bh(&base->cpu_base->softirq_expiry_lock); base 1256 kernel/time/hrtimer.c hrtimer_cpu_base_init_expiry_lock(struct hrtimer_cpu_base *base) { } base 1258 kernel/time/hrtimer.c hrtimer_cpu_base_lock_expiry(struct hrtimer_cpu_base *base) { } base 1260 kernel/time/hrtimer.c hrtimer_cpu_base_unlock_expiry(struct hrtimer_cpu_base *base) { } base 1261 kernel/time/hrtimer.c static inline void hrtimer_sync_wait_running(struct hrtimer_cpu_base *base, base 1367 kernel/time/hrtimer.c int base = hrtimer_clock_to_base_table[clock_id]; base 1369 kernel/time/hrtimer.c if (likely(base != HRTIMER_MAX_CLOCK_BASES)) base 1370 kernel/time/hrtimer.c return base; base 1381 kernel/time/hrtimer.c int base; base 1404 kernel/time/hrtimer.c base = softtimer ? HRTIMER_MAX_CLOCK_BASES / 2 : 0; base 1405 kernel/time/hrtimer.c base += hrtimer_clockid_to_base(clock_id); base 1408 kernel/time/hrtimer.c timer->base = &cpu_base->clock_base[base]; base 1441 kernel/time/hrtimer.c struct hrtimer_clock_base *base; base 1445 kernel/time/hrtimer.c base = READ_ONCE(timer->base); base 1446 kernel/time/hrtimer.c seq = raw_read_seqcount_begin(&base->seq); base 1449 kernel/time/hrtimer.c base->running == timer) base 1452 kernel/time/hrtimer.c } while (read_seqcount_retry(&base->seq, seq) || base 1453 kernel/time/hrtimer.c base != READ_ONCE(timer->base)); base 1478 kernel/time/hrtimer.c struct hrtimer_clock_base *base, base 1488 kernel/time/hrtimer.c base->running = timer; base 1497 kernel/time/hrtimer.c raw_write_seqcount_barrier(&base->seq); base 1499 kernel/time/hrtimer.c __remove_hrtimer(timer, base, HRTIMER_STATE_INACTIVE, 0); base 1532 kernel/time/hrtimer.c enqueue_hrtimer(timer, base, HRTIMER_MODE_ABS); base 1541 kernel/time/hrtimer.c raw_write_seqcount_barrier(&base->seq); base 1543 kernel/time/hrtimer.c WARN_ON_ONCE(base->running != timer); base 1544 kernel/time/hrtimer.c base->running = NULL; base 1550 kernel/time/hrtimer.c struct hrtimer_clock_base *base; base 1553 kernel/time/hrtimer.c for_each_active_base(base, cpu_base, active) { base 1557 kernel/time/hrtimer.c basenow = ktime_add(now, base->offset); base 1559 kernel/time/hrtimer.c while ((node = timerqueue_getnext(&base->active))) { base 1579 kernel/time/hrtimer.c __run_hrtimer(cpu_base, base, timer, &basenow, flags); base 1939 kernel/time/hrtimer.c restart->nanosleep.clockid = t.timer.base->clockid; base 2029 kernel/time/hrtimer.c timer->base = new_base; base 493 kernel/time/posix-cpu-timers.c struct posix_cputimer_base *base; base 496 kernel/time/posix-cpu-timers.c base = p->posix_cputimers.bases + clkidx; base 498 kernel/time/posix-cpu-timers.c base = p->signal->posix_cputimers.bases + clkidx; base 500 kernel/time/posix-cpu-timers.c if (!cpu_timer_enqueue(&base->tqhead, ctmr)) base 509 kernel/time/posix-cpu-timers.c if (newexp < base->nextevt) base 510 kernel/time/posix-cpu-timers.c base->nextevt = newexp; base 790 kernel/time/posix-cpu-timers.c struct posix_cputimer_base *base = pct->bases; base 793 kernel/time/posix-cpu-timers.c for (i = 0; i < CPUCLOCK_MAX; i++, base++) { base 794 kernel/time/posix-cpu-timers.c base->nextevt = collect_timerqueue(&base->tqhead, firing, base 271 kernel/time/posix-timers.c timr->it_overrun += hrtimer_forward(timer, timer->base->get_time(), base 796 kernel/time/posix-timers.c expires = ktime_add_safe(expires, timer->base->get_time()); base 76 kernel/time/tick-broadcast-hrtimer.c bc->bound_on = bctimer.base->cpu_base->cpu; base 1363 kernel/time/tick-sched.c if (ts->sched_timer.base) base 67 kernel/time/timekeeping.c struct tk_read_base base[2]; base 83 kernel/time/timekeeping.c .base[0] = { .clock = &dummy_clock, }, base 84 kernel/time/timekeeping.c .base[1] = { .clock = &dummy_clock, }, base 88 kernel/time/timekeeping.c .base[0] = { .clock = &dummy_clock, }, base 89 kernel/time/timekeeping.c .base[1] = { .clock = &dummy_clock, }, base 404 kernel/time/timekeeping.c struct tk_read_base *base = tkf->base; base 410 kernel/time/timekeeping.c memcpy(base, tkr, sizeof(*base)); base 416 kernel/time/timekeeping.c memcpy(base + 1, base, sizeof(*base)); base 459 kernel/time/timekeeping.c tkr = tkf->base + (seq & 0x01); base 460 kernel/time/timekeeping.c now = ktime_to_ns(tkr->base); base 525 kernel/time/timekeeping.c tkr = tkf->base + (seq & 0x01); base 565 kernel/time/timekeeping.c tkr_dummy.base_real = tkr->base + tk->offs_real; base 644 kernel/time/timekeeping.c tk->tkr_mono.base = ns_to_ktime(seconds * NSEC_PER_SEC + nsec); base 657 kernel/time/timekeeping.c tk->tkr_raw.base = ns_to_ktime(tk->raw_sec * NSEC_PER_SEC); base 674 kernel/time/timekeeping.c tk->tkr_mono.base_real = tk->tkr_mono.base + tk->offs_real; base 751 kernel/time/timekeeping.c ktime_t base; base 758 kernel/time/timekeeping.c base = tk->tkr_mono.base; base 763 kernel/time/timekeeping.c return ktime_add_ns(base, nsecs); base 794 kernel/time/timekeeping.c ktime_t base, *offset = offsets[offs]; base 801 kernel/time/timekeeping.c base = ktime_add(tk->tkr_mono.base, *offset); base 806 kernel/time/timekeeping.c return ktime_add_ns(base, nsecs); base 815 kernel/time/timekeeping.c ktime_t base, *offset = offsets[offs]; base 822 kernel/time/timekeeping.c base = ktime_add(tk->tkr_mono.base, *offset); base 827 kernel/time/timekeeping.c return ktime_add_ns(base, nsecs); base 858 kernel/time/timekeeping.c ktime_t base; base 863 kernel/time/timekeeping.c base = tk->tkr_raw.base; base 868 kernel/time/timekeeping.c return ktime_add_ns(base, nsecs); base 984 kernel/time/timekeeping.c base_real = ktime_add(tk->tkr_mono.base, base 986 kernel/time/timekeeping.c base_raw = tk->tkr_raw.base; base 998 kernel/time/timekeeping.c static int scale64_check_overflow(u64 mult, u64 div, u64 *base) base 1002 kernel/time/timekeeping.c tmp = div64_u64_rem(*base, div, &rem); base 1011 kernel/time/timekeeping.c *base = tmp + rem; base 1170 kernel/time/timekeeping.c base_real = ktime_add(tk->tkr_mono.base, base 1172 kernel/time/timekeeping.c base_raw = tk->tkr_raw.base; base 2218 kernel/time/timekeeping.c ktime_t base; base 2224 kernel/time/timekeeping.c base = tk->tkr_mono.base; base 2226 kernel/time/timekeeping.c base = ktime_add_ns(base, nsecs); base 2236 kernel/time/timekeeping.c if (unlikely(base >= tk->next_leap_ktime)) base 2241 kernel/time/timekeeping.c return base; base 537 kernel/time/timer.c static void enqueue_timer(struct timer_base *base, struct timer_list *timer, base 540 kernel/time/timer.c hlist_add_head(&timer->entry, base->vectors + idx); base 541 kernel/time/timer.c __set_bit(idx, base->pending_map); base 548 kernel/time/timer.c __internal_add_timer(struct timer_base *base, struct timer_list *timer) base 552 kernel/time/timer.c idx = calc_wheel_index(timer->expires, base->clk); base 553 kernel/time/timer.c enqueue_timer(base, timer, idx); base 557 kernel/time/timer.c trigger_dyntick_cpu(struct timer_base *base, struct timer_list *timer) base 567 kernel/time/timer.c if (tick_nohz_full_cpu(base->cpu)) base 568 kernel/time/timer.c wake_up_nohz_cpu(base->cpu); base 577 kernel/time/timer.c if (!base->is_idle) base 581 kernel/time/timer.c if (time_after_eq(timer->expires, base->next_expiry)) base 588 kernel/time/timer.c base->next_expiry = timer->expires; base 589 kernel/time/timer.c wake_up_nohz_cpu(base->cpu); base 593 kernel/time/timer.c internal_add_timer(struct timer_base *base, struct timer_list *timer) base 595 kernel/time/timer.c __internal_add_timer(base, timer); base 596 kernel/time/timer.c trigger_dyntick_cpu(base, timer); base 821 kernel/time/timer.c static int detach_if_pending(struct timer_list *timer, struct timer_base *base, base 829 kernel/time/timer.c if (hlist_is_singular_node(&timer->entry, base->vectors + idx)) base 830 kernel/time/timer.c __clear_bit(idx, base->pending_map); base 838 kernel/time/timer.c struct timer_base *base = per_cpu_ptr(&timer_bases[BASE_STD], cpu); base 845 kernel/time/timer.c base = per_cpu_ptr(&timer_bases[BASE_DEF], cpu); base 846 kernel/time/timer.c return base; base 851 kernel/time/timer.c struct timer_base *base = this_cpu_ptr(&timer_bases[BASE_STD]); base 858 kernel/time/timer.c base = this_cpu_ptr(&timer_bases[BASE_DEF]); base 859 kernel/time/timer.c return base; base 868 kernel/time/timer.c get_target_base(struct timer_base *base, unsigned tflags) base 878 kernel/time/timer.c static inline void forward_timer_base(struct timer_base *base) base 888 kernel/time/timer.c if (likely(!base->must_forward_clk)) base 892 kernel/time/timer.c base->must_forward_clk = base->is_idle; base 893 kernel/time/timer.c if ((long)(jnow - base->clk) < 2) base 900 kernel/time/timer.c if (time_after(base->next_expiry, jnow)) base 901 kernel/time/timer.c base->clk = jnow; base 903 kernel/time/timer.c base->clk = base->next_expiry; base 921 kernel/time/timer.c __acquires(timer->base->lock) base 924 kernel/time/timer.c struct timer_base *base; base 935 kernel/time/timer.c base = get_timer_base(tf); base 936 kernel/time/timer.c raw_spin_lock_irqsave(&base->lock, *flags); base 938 kernel/time/timer.c return base; base 939 kernel/time/timer.c raw_spin_unlock_irqrestore(&base->lock, *flags); base 951 kernel/time/timer.c struct timer_base *base, *new_base; base 982 kernel/time/timer.c base = lock_timer_base(timer, &flags); base 983 kernel/time/timer.c forward_timer_base(base); base 991 kernel/time/timer.c clk = base->clk; base 1008 kernel/time/timer.c base = lock_timer_base(timer, &flags); base 1009 kernel/time/timer.c forward_timer_base(base); base 1012 kernel/time/timer.c ret = detach_if_pending(timer, base, false); base 1016 kernel/time/timer.c new_base = get_target_base(base, timer->flags); base 1018 kernel/time/timer.c if (base != new_base) { base 1026 kernel/time/timer.c if (likely(base->running_timer != timer)) { base 1030 kernel/time/timer.c raw_spin_unlock(&base->lock); base 1031 kernel/time/timer.c base = new_base; base 1032 kernel/time/timer.c raw_spin_lock(&base->lock); base 1034 kernel/time/timer.c (timer->flags & ~TIMER_BASEMASK) | base->cpu); base 1035 kernel/time/timer.c forward_timer_base(base); base 1049 kernel/time/timer.c if (idx != UINT_MAX && clk == base->clk) { base 1050 kernel/time/timer.c enqueue_timer(base, timer, idx); base 1051 kernel/time/timer.c trigger_dyntick_cpu(base, timer); base 1053 kernel/time/timer.c internal_add_timer(base, timer); base 1057 kernel/time/timer.c raw_spin_unlock_irqrestore(&base->lock, flags); base 1149 kernel/time/timer.c struct timer_base *new_base, *base; base 1161 kernel/time/timer.c base = lock_timer_base(timer, &flags); base 1162 kernel/time/timer.c if (base != new_base) { base 1165 kernel/time/timer.c raw_spin_unlock(&base->lock); base 1166 kernel/time/timer.c base = new_base; base 1167 kernel/time/timer.c raw_spin_lock(&base->lock); base 1171 kernel/time/timer.c forward_timer_base(base); base 1174 kernel/time/timer.c internal_add_timer(base, timer); base 1175 kernel/time/timer.c raw_spin_unlock_irqrestore(&base->lock, flags); base 1192 kernel/time/timer.c struct timer_base *base; base 1199 kernel/time/timer.c base = lock_timer_base(timer, &flags); base 1200 kernel/time/timer.c ret = detach_if_pending(timer, base, true); base 1201 kernel/time/timer.c raw_spin_unlock_irqrestore(&base->lock, flags); base 1217 kernel/time/timer.c struct timer_base *base; base 1223 kernel/time/timer.c base = lock_timer_base(timer, &flags); base 1225 kernel/time/timer.c if (base->running_timer != timer) base 1226 kernel/time/timer.c ret = detach_if_pending(timer, base, true); base 1228 kernel/time/timer.c raw_spin_unlock_irqrestore(&base->lock, flags); base 1235 kernel/time/timer.c static __init void timer_base_init_expiry_lock(struct timer_base *base) base 1237 kernel/time/timer.c spin_lock_init(&base->expiry_lock); base 1240 kernel/time/timer.c static inline void timer_base_lock_expiry(struct timer_base *base) base 1242 kernel/time/timer.c spin_lock(&base->expiry_lock); base 1245 kernel/time/timer.c static inline void timer_base_unlock_expiry(struct timer_base *base) base 1247 kernel/time/timer.c spin_unlock(&base->expiry_lock); base 1257 kernel/time/timer.c static void timer_sync_wait_running(struct timer_base *base) base 1259 kernel/time/timer.c if (atomic_read(&base->timer_waiters)) { base 1260 kernel/time/timer.c spin_unlock(&base->expiry_lock); base 1261 kernel/time/timer.c spin_lock(&base->expiry_lock); base 1281 kernel/time/timer.c struct timer_base *base = get_timer_base(tf); base 1291 kernel/time/timer.c atomic_inc(&base->timer_waiters); base 1292 kernel/time/timer.c spin_lock_bh(&base->expiry_lock); base 1293 kernel/time/timer.c atomic_dec(&base->timer_waiters); base 1294 kernel/time/timer.c spin_unlock_bh(&base->expiry_lock); base 1298 kernel/time/timer.c static inline void timer_base_init_expiry_lock(struct timer_base *base) { } base 1299 kernel/time/timer.c static inline void timer_base_lock_expiry(struct timer_base *base) { } base 1300 kernel/time/timer.c static inline void timer_base_unlock_expiry(struct timer_base *base) { } base 1301 kernel/time/timer.c static inline void timer_sync_wait_running(struct timer_base *base) { } base 1422 kernel/time/timer.c static void expire_timers(struct timer_base *base, struct hlist_head *head) base 1429 kernel/time/timer.c unsigned long baseclk = base->clk - 1; base 1437 kernel/time/timer.c base->running_timer = timer; base 1443 kernel/time/timer.c raw_spin_unlock(&base->lock); base 1445 kernel/time/timer.c base->running_timer = NULL; base 1446 kernel/time/timer.c raw_spin_lock(&base->lock); base 1448 kernel/time/timer.c raw_spin_unlock_irq(&base->lock); base 1450 kernel/time/timer.c base->running_timer = NULL; base 1451 kernel/time/timer.c timer_sync_wait_running(base); base 1452 kernel/time/timer.c raw_spin_lock_irq(&base->lock); base 1457 kernel/time/timer.c static int __collect_expired_timers(struct timer_base *base, base 1460 kernel/time/timer.c unsigned long clk = base->clk; base 1468 kernel/time/timer.c if (__test_and_clear_bit(idx, base->pending_map)) { base 1469 kernel/time/timer.c vec = base->vectors + idx; base 1488 kernel/time/timer.c static int next_pending_bucket(struct timer_base *base, unsigned offset, base 1494 kernel/time/timer.c pos = find_next_bit(base->pending_map, end, start); base 1498 kernel/time/timer.c pos = find_next_bit(base->pending_map, start, offset); base 1506 kernel/time/timer.c static unsigned long __next_timer_interrupt(struct timer_base *base) base 1511 kernel/time/timer.c next = base->clk + NEXT_TIMER_MAX_DELTA; base 1512 kernel/time/timer.c clk = base->clk; base 1514 kernel/time/timer.c int pos = next_pending_bucket(base, offset, clk & LVL_MASK); base 1609 kernel/time/timer.c struct timer_base *base = this_cpu_ptr(&timer_bases[BASE_STD]); base 1621 kernel/time/timer.c raw_spin_lock(&base->lock); base 1622 kernel/time/timer.c nextevt = __next_timer_interrupt(base); base 1623 kernel/time/timer.c is_max_delta = (nextevt == base->clk + NEXT_TIMER_MAX_DELTA); base 1624 kernel/time/timer.c base->next_expiry = nextevt; base 1630 kernel/time/timer.c if (time_after(basej, base->clk)) { base 1632 kernel/time/timer.c base->clk = basej; base 1633 kernel/time/timer.c else if (time_after(nextevt, base->clk)) base 1634 kernel/time/timer.c base->clk = nextevt; base 1639 kernel/time/timer.c base->is_idle = false; base 1651 kernel/time/timer.c base->must_forward_clk = true; base 1652 kernel/time/timer.c base->is_idle = true; base 1655 kernel/time/timer.c raw_spin_unlock(&base->lock); base 1667 kernel/time/timer.c struct timer_base *base = this_cpu_ptr(&timer_bases[BASE_STD]); base 1675 kernel/time/timer.c base->is_idle = false; base 1678 kernel/time/timer.c static int collect_expired_timers(struct timer_base *base, base 1688 kernel/time/timer.c if ((long)(now - base->clk) > 2) { base 1689 kernel/time/timer.c unsigned long next = __next_timer_interrupt(base); base 1700 kernel/time/timer.c base->clk = now; base 1703 kernel/time/timer.c base->clk = next; base 1705 kernel/time/timer.c return __collect_expired_timers(base, heads); base 1708 kernel/time/timer.c static inline int collect_expired_timers(struct timer_base *base, base 1711 kernel/time/timer.c return __collect_expired_timers(base, heads); base 1740 kernel/time/timer.c static inline void __run_timers(struct timer_base *base) base 1745 kernel/time/timer.c if (!time_after_eq(jiffies, base->clk)) base 1748 kernel/time/timer.c timer_base_lock_expiry(base); base 1749 kernel/time/timer.c raw_spin_lock_irq(&base->lock); base 1765 kernel/time/timer.c base->must_forward_clk = false; base 1767 kernel/time/timer.c while (time_after_eq(jiffies, base->clk)) { base 1769 kernel/time/timer.c levels = collect_expired_timers(base, heads); base 1770 kernel/time/timer.c base->clk++; base 1773 kernel/time/timer.c expire_timers(base, heads + levels); base 1775 kernel/time/timer.c raw_spin_unlock_irq(&base->lock); base 1776 kernel/time/timer.c timer_base_unlock_expiry(base); base 1784 kernel/time/timer.c struct timer_base *base = this_cpu_ptr(&timer_bases[BASE_STD]); base 1786 kernel/time/timer.c __run_timers(base); base 1796 kernel/time/timer.c struct timer_base *base = this_cpu_ptr(&timer_bases[BASE_STD]); base 1800 kernel/time/timer.c if (time_before(jiffies, base->clk)) { base 1804 kernel/time/timer.c base++; base 1805 kernel/time/timer.c if (time_before(jiffies, base->clk)) base 1960 kernel/time/timer.c struct timer_base *base; base 1964 kernel/time/timer.c base = per_cpu_ptr(&timer_bases[b], cpu); base 1965 kernel/time/timer.c base->clk = jiffies; base 1966 kernel/time/timer.c base->next_expiry = base->clk + NEXT_TIMER_MAX_DELTA; base 1967 kernel/time/timer.c base->is_idle = false; base 1968 kernel/time/timer.c base->must_forward_clk = true; base 2013 kernel/time/timer.c struct timer_base *base; base 2017 kernel/time/timer.c base = per_cpu_ptr(&timer_bases[i], cpu); base 2018 kernel/time/timer.c base->cpu = cpu; base 2019 kernel/time/timer.c raw_spin_lock_init(&base->lock); base 2020 kernel/time/timer.c base->clk = jiffies; base 2021 kernel/time/timer.c timer_base_init_expiry_lock(base); base 73 kernel/time/timer_list.c print_active_timers(struct seq_file *m, struct hrtimer_clock_base *base, base 86 kernel/time/timer_list.c raw_spin_lock_irqsave(&base->cpu_base->lock, flags); base 88 kernel/time/timer_list.c curr = timerqueue_getnext(&base->active); base 102 kernel/time/timer_list.c raw_spin_unlock_irqrestore(&base->cpu_base->lock, flags); base 108 kernel/time/timer_list.c raw_spin_unlock_irqrestore(&base->cpu_base->lock, flags); base 112 kernel/time/timer_list.c print_base(struct seq_file *m, struct hrtimer_clock_base *base, u64 now) base 114 kernel/time/timer_list.c SEQ_printf(m, " .base: %pK\n", base); base 115 kernel/time/timer_list.c SEQ_printf(m, " .index: %d\n", base->index); base 120 kernel/time/timer_list.c print_name_offset(m, base->get_time); base 124 kernel/time/timer_list.c (unsigned long long) ktime_to_ns(base->offset)); base 127 kernel/time/timer_list.c print_active_timers(m, base, now + ktime_to_ns(base->offset)); base 1066 kernel/trace/trace_kprobe.c fetch_store_string(unsigned long addr, void *dest, void *base) base 1075 kernel/trace/trace_kprobe.c __dest = get_loc_data(dest, base); base 1083 kernel/trace/trace_kprobe.c *(u32 *)dest = make_data_loc(ret, __dest - base); base 1093 kernel/trace/trace_kprobe.c fetch_store_string_user(unsigned long addr, void *dest, void *base) base 1103 kernel/trace/trace_kprobe.c __dest = get_loc_data(dest, base); base 1107 kernel/trace/trace_kprobe.c *(u32 *)dest = make_data_loc(ret, __dest - base); base 1129 kernel/trace/trace_kprobe.c void *base) base 1170 kernel/trace/trace_kprobe.c return process_fetch_insn_bottom(code, val, dest, base); base 58 kernel/trace/trace_probe_tmpl.h void *dest, void *base); base 61 kernel/trace/trace_probe_tmpl.h fetch_store_string(unsigned long addr, void *dest, void *base); base 64 kernel/trace/trace_probe_tmpl.h fetch_store_string_user(unsigned long addr, void *dest, void *base); base 73 kernel/trace/trace_probe_tmpl.h void *dest, void *base) base 126 kernel/trace/trace_probe_tmpl.h ret = fetch_store_string(val + code->offset, dest, base); base 130 kernel/trace/trace_probe_tmpl.h ret = fetch_store_string_user(val + code->offset, dest, base); base 195 kernel/trace/trace_probe_tmpl.h void *base = data - header_size; base 205 kernel/trace/trace_probe_tmpl.h *dl = make_data_loc(maxlen, dyndata - base); base 206 kernel/trace/trace_probe_tmpl.h ret = process_fetch_insn(arg->code, regs, dl, base); base 208 kernel/trace/trace_probe_tmpl.h *dl = make_data_loc(0, dyndata - base); base 149 kernel/trace/trace_uprobe.c fetch_store_string(unsigned long addr, void *dest, void *base) base 154 kernel/trace/trace_uprobe.c u8 *dst = get_loc_data(dest, base); base 174 kernel/trace/trace_uprobe.c *(u32 *)dest = make_data_loc(ret, (void *)dst - base); base 181 kernel/trace/trace_uprobe.c fetch_store_string_user(unsigned long addr, void *dest, void *base) base 183 kernel/trace/trace_uprobe.c return fetch_store_string(addr, dest, base); base 221 kernel/trace/trace_uprobe.c void *base) base 256 kernel/trace/trace_uprobe.c return process_fetch_insn_bottom(code, val, dest, base); base 31 lib/bsearch.c void *bsearch(const void *key, const void *base, size_t num, size_t size, base 38 lib/bsearch.c pivot = base + (num >> 1) * size; base 45 lib/bsearch.c base = pivot + size; base 85 lib/decompress_bunzip2.c int base[MAX_HUFCODE_BITS]; base 159 lib/decompress_bunzip2.c int *base = NULL; base 303 lib/decompress_bunzip2.c base = hufGroup->base-1; base 338 lib/decompress_bunzip2.c base[i+1] = pp-(t += temp[i]); base 343 lib/decompress_bunzip2.c base[minLen] = 0; base 365 lib/decompress_bunzip2.c base = hufGroup->base-1; base 401 lib/decompress_bunzip2.c || (((unsigned)(j = (j>>(hufGroup->maxLen-i))-base[i])) base 116 lib/extable.c search_extable(const struct exception_table_entry *base, base 120 lib/extable.c return bsearch(&value, base, num, base 38 lib/idr.c unsigned int base = idr->idr_base; base 44 lib/idr.c id = (id < base) ? 0 : id - base; base 46 lib/idr.c slot = idr_get_free(&idr->idr_rt, &iter, gfp, max - base); base 50 lib/idr.c *nextid = iter.index + base; base 200 lib/idr.c int base = idr->idr_base; base 204 lib/idr.c unsigned long id = iter.index + base; base 232 lib/idr.c unsigned long base = idr->idr_base; base 235 lib/idr.c id = (id < base) ? 0 : id - base; base 249 lib/idr.c *nextid = iter.index + base; base 24 lib/kstrtox.c const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) base 26 lib/kstrtox.c if (*base == 0) { base 29 lib/kstrtox.c *base = 16; base 31 lib/kstrtox.c *base = 8; base 33 lib/kstrtox.c *base = 10; base 35 lib/kstrtox.c if (*base == 16 && s[0] == '0' && _tolower(s[1]) == 'x') base 48 lib/kstrtox.c unsigned int _parse_integer(const char *s, unsigned int base, unsigned long long *p) base 67 lib/kstrtox.c if (val >= base) base 74 lib/kstrtox.c if (res > div_u64(ULLONG_MAX - val, base)) base 77 lib/kstrtox.c res = res * base + val; base 85 lib/kstrtox.c static int _kstrtoull(const char *s, unsigned int base, unsigned long long *res) base 90 lib/kstrtox.c s = _parse_integer_fixup_radix(s, &base); base 91 lib/kstrtox.c rv = _parse_integer(s, base, &_res); base 121 lib/kstrtox.c int kstrtoull(const char *s, unsigned int base, unsigned long long *res) base 125 lib/kstrtox.c return _kstrtoull(s, base, res); base 145 lib/kstrtox.c int kstrtoll(const char *s, unsigned int base, long long *res) base 151 lib/kstrtox.c rv = _kstrtoull(s + 1, base, &tmp); base 158 lib/kstrtox.c rv = kstrtoull(s, base, &tmp); base 170 lib/kstrtox.c int _kstrtoul(const char *s, unsigned int base, unsigned long *res) base 175 lib/kstrtox.c rv = kstrtoull(s, base, &tmp); base 186 lib/kstrtox.c int _kstrtol(const char *s, unsigned int base, long *res) base 191 lib/kstrtox.c rv = kstrtoll(s, base, &tmp); base 217 lib/kstrtox.c int kstrtouint(const char *s, unsigned int base, unsigned int *res) base 222 lib/kstrtox.c rv = kstrtoull(s, base, &tmp); base 248 lib/kstrtox.c int kstrtoint(const char *s, unsigned int base, int *res) base 253 lib/kstrtox.c rv = kstrtoll(s, base, &tmp); base 263 lib/kstrtox.c int kstrtou16(const char *s, unsigned int base, u16 *res) base 268 lib/kstrtox.c rv = kstrtoull(s, base, &tmp); base 278 lib/kstrtox.c int kstrtos16(const char *s, unsigned int base, s16 *res) base 283 lib/kstrtox.c rv = kstrtoll(s, base, &tmp); base 293 lib/kstrtox.c int kstrtou8(const char *s, unsigned int base, u8 *res) base 298 lib/kstrtox.c rv = kstrtoull(s, base, &tmp); base 308 lib/kstrtox.c int kstrtos8(const char *s, unsigned int base, s8 *res) base 313 lib/kstrtox.c rv = kstrtoll(s, base, &tmp); base 388 lib/kstrtox.c int f(const char __user *s, size_t count, unsigned int base, type *res) \ base 397 lib/kstrtox.c return g(buf, base, res); \ base 6 lib/kstrtox.h const char *_parse_integer_fixup_radix(const char *s, unsigned int *base); base 7 lib/kstrtox.h unsigned int _parse_integer(const char *s, unsigned int base, unsigned long long *res); base 1118 lib/locking-selftest.c I_WW(t); I_WW(t2); I_WW(o.base); I_WW(o2.base); I_WW(o3.base); base 1356 lib/locking-selftest.c mutex_lock(&o.base); base 1357 lib/locking-selftest.c mutex_unlock(&o.base); base 1362 lib/locking-selftest.c ret = mutex_lock_interruptible(&o.base); base 1364 lib/locking-selftest.c mutex_unlock(&o.base); base 1371 lib/locking-selftest.c ret = mutex_lock_killable(&o.base); base 1373 lib/locking-selftest.c mutex_unlock(&o.base); base 1380 lib/locking-selftest.c ret = mutex_trylock(&o.base); base 1383 lib/locking-selftest.c mutex_unlock(&o.base); base 1390 lib/locking-selftest.c mutex_lock(&o.base); base 1391 lib/locking-selftest.c ret = mutex_trylock(&o.base); base 1393 lib/locking-selftest.c mutex_unlock(&o.base); base 1398 lib/locking-selftest.c mutex_lock_nest_lock(&o.base, &t); base 1399 lib/locking-selftest.c mutex_unlock(&o.base); base 1476 lib/locking-selftest.c mutex_lock(&o2.base); base 1478 lib/locking-selftest.c mutex_release(&o2.base.dep_map, 1, _THIS_IP_); base 1491 lib/locking-selftest.c mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_); base 1492 lib/locking-selftest.c mutex_unlock(&o2.base); base 1502 lib/locking-selftest.c mutex_lock(&o2.base); base 1503 lib/locking-selftest.c mutex_release(&o2.base.dep_map, 1, _THIS_IP_); base 1517 lib/locking-selftest.c mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_); base 1518 lib/locking-selftest.c mutex_unlock(&o2.base); base 1528 lib/locking-selftest.c mutex_lock(&o2.base); base 1530 lib/locking-selftest.c mutex_release(&o2.base.dep_map, 1, _THIS_IP_); base 1543 lib/locking-selftest.c mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_); base 1544 lib/locking-selftest.c mutex_unlock(&o2.base); base 1553 lib/locking-selftest.c mutex_lock(&o2.base); base 1554 lib/locking-selftest.c mutex_release(&o2.base.dep_map, 1, _THIS_IP_); base 1568 lib/locking-selftest.c mutex_acquire(&o2.base.dep_map, 0, 1, _THIS_IP_); base 1569 lib/locking-selftest.c mutex_unlock(&o2.base); base 1578 lib/locking-selftest.c mutex_lock(&o2.base); base 1579 lib/locking-selftest.c mutex_release(&o2.base.dep_map, 1, _THIS_IP_); base 1599 lib/locking-selftest.c mutex_lock(&o2.base); base 1600 lib/locking-selftest.c mutex_release(&o2.base.dep_map, 1, _THIS_IP_); base 1620 lib/locking-selftest.c mutex_lock(&o2.base); base 1621 lib/locking-selftest.c mutex_release(&o2.base.dep_map, 1, _THIS_IP_); base 1624 lib/locking-selftest.c mutex_lock(&o3.base); base 1625 lib/locking-selftest.c mutex_release(&o3.base.dep_map, 1, _THIS_IP_); base 1646 lib/locking-selftest.c mutex_lock(&o2.base); base 1647 lib/locking-selftest.c mutex_release(&o2.base.dep_map, 1, _THIS_IP_); base 1650 lib/locking-selftest.c mutex_lock(&o3.base); base 1651 lib/locking-selftest.c mutex_release(&o3.base.dep_map, 1, _THIS_IP_); base 1671 lib/locking-selftest.c mutex_lock(&o2.base); base 1672 lib/locking-selftest.c mutex_release(&o2.base.dep_map, 1, _THIS_IP_); base 1696 lib/locking-selftest.c mutex_lock(&o2.base); base 1697 lib/locking-selftest.c mutex_release(&o2.base.dep_map, 1, _THIS_IP_); base 1719 lib/locking-selftest.c raw_spin_lock_nest_lock(&lock_A, &o.base); base 189 lib/lz4/lz4_compress.c const BYTE *base; base 215 lib/lz4/lz4_compress.c base = (const BYTE *)source; base 219 lib/lz4/lz4_compress.c base = (const BYTE *)source - dictPtr->currentOffset; base 223 lib/lz4/lz4_compress.c base = (const BYTE *)source - dictPtr->currentOffset; base 240 lib/lz4/lz4_compress.c LZ4_putPosition(ip, dictPtr->hashTable, tableType, base); base 267 lib/lz4/lz4_compress.c tableType, base); base 282 lib/lz4/lz4_compress.c tableType, base); base 398 lib/lz4/lz4_compress.c LZ4_putPosition(ip - 2, dictPtr->hashTable, tableType, base); base 402 lib/lz4/lz4_compress.c tableType, base); base 414 lib/lz4/lz4_compress.c LZ4_putPosition(ip, dictPtr->hashTable, tableType, base); base 531 lib/lz4/lz4_compress.c const BYTE *base = (const BYTE *) src; base 564 lib/lz4/lz4_compress.c LZ4_putPosition(ip, ctx->hashTable, tableType, base); base 589 lib/lz4/lz4_compress.c tableType, base); base 594 lib/lz4/lz4_compress.c base); base 671 lib/lz4/lz4_compress.c LZ4_putPosition(ip - 2, ctx->hashTable, tableType, base); base 674 lib/lz4/lz4_compress.c match = LZ4_getPosition(ip, ctx->hashTable, tableType, base); base 675 lib/lz4/lz4_compress.c LZ4_putPosition(ip, ctx->hashTable, tableType, base); base 781 lib/lz4/lz4_compress.c const BYTE *base; base 798 lib/lz4/lz4_compress.c base = p - dict->currentOffset; base 804 lib/lz4/lz4_compress.c LZ4_putPosition(p, dict->hashTable, byU32, base); base 66 lib/lz4/lz4hc_compress.c hc4->base = start - 64 * KB; base 79 lib/lz4/lz4hc_compress.c const BYTE * const base = hc4->base; base 80 lib/lz4/lz4hc_compress.c U32 const target = (U32)(ip - base); base 84 lib/lz4/lz4hc_compress.c U32 const h = LZ4HC_hashPtr(base + idx); base 108 lib/lz4/lz4hc_compress.c const BYTE * const base = hc4->base; base 111 lib/lz4/lz4hc_compress.c const U32 lowLimit = (hc4->lowLimit + 64 * KB > (U32)(ip - base)) base 113 lib/lz4/lz4hc_compress.c : (U32)(ip - base) - (64 * KB - 1); base 126 lib/lz4/lz4hc_compress.c const BYTE * const match = base + matchIndex; base 153 lib/lz4/lz4hc_compress.c base + dictLimit, base 158 lib/lz4/lz4hc_compress.c *matchpos = base + matchIndex; base 180 lib/lz4/lz4hc_compress.c const BYTE * const base = hc4->base; base 182 lib/lz4/lz4hc_compress.c const BYTE * const lowPrefixPtr = base + dictLimit; base 183 lib/lz4/lz4hc_compress.c const U32 lowLimit = (hc4->lowLimit + 64 * KB > (U32)(ip - base)) base 185 lib/lz4/lz4hc_compress.c : (U32)(ip - base) - (64 * KB - 1); base 199 lib/lz4/lz4hc_compress.c const BYTE *matchPtr = base + matchIndex; base 239 lib/lz4/lz4hc_compress.c mlt += LZ4_count(ip + mlt, base + dictLimit, base 250 lib/lz4/lz4hc_compress.c *matchpos = base + matchIndex + back; base 621 lib/lz4/lz4hc_compress.c LZ4_streamHCPtr->internal_donotuse.base = NULL; base 649 lib/lz4/lz4hc_compress.c if (ctxPtr->end >= ctxPtr->base + 4) { base 659 lib/lz4/lz4hc_compress.c ctxPtr->dictLimit = (U32)(ctxPtr->end - ctxPtr->base); base 660 lib/lz4/lz4hc_compress.c ctxPtr->dictBase = ctxPtr->base; base 661 lib/lz4/lz4hc_compress.c ctxPtr->base = newBlock - ctxPtr->dictLimit; base 678 lib/lz4/lz4hc_compress.c if (ctxPtr->base == NULL) base 682 lib/lz4/lz4hc_compress.c if ((size_t)(ctxPtr->end - ctxPtr->base) > 2 * GB) { base 683 lib/lz4/lz4hc_compress.c size_t dictSize = (size_t)(ctxPtr->end - ctxPtr->base) base 741 lib/lz4/lz4hc_compress.c - (streamPtr->base + streamPtr->dictLimit)); base 753 lib/lz4/lz4hc_compress.c U32 const endIndex = (U32)(streamPtr->end - streamPtr->base); base 756 lib/lz4/lz4hc_compress.c streamPtr->base = streamPtr->end - endIndex; base 29 lib/math/div64.c uint32_t __attribute__((weak)) __div64_32(uint64_t *n, uint32_t base) base 32 lib/math/div64.c uint64_t b = base; base 38 lib/math/div64.c if (high >= base) { base 39 lib/math/div64.c high /= base; base 41 lib/math/div64.c rem -= (uint64_t) (high*base) << 32; base 19 lib/math/int_pow.c u64 int_pow(u64 base, unsigned int exp) base 25 lib/math/int_pow.c result *= base; base 27 lib/math/int_pow.c base *= base; base 24 lib/mpi/mpi-pow.c int mpi_powm(MPI res, MPI base, MPI exp, MPI mod) base 79 lib/mpi/mpi-pow.c bsize = base->nlimbs; base 80 lib/mpi/mpi-pow.c bsign = base->sign; base 87 lib/mpi/mpi-pow.c MPN_COPY(bp, base->d, bsize); base 96 lib/mpi/mpi-pow.c bp = base->d; base 159 lib/mpi/mpi-pow.c negative_result = (ep[0] & 1) && base->sign; base 126 lib/parser.c static int match_number(substring_t *s, int *result, int base) base 138 lib/parser.c val = simple_strtol(buf, &endp, base); base 159 lib/parser.c static int match_u64int(substring_t *s, u64 *result, int base) base 169 lib/parser.c ret = kstrtoull(buf, base, &val); base 643 lib/scatterlist.c struct sg_page_iter *piter = &dma_iter->base; base 33 lib/sort.c static bool is_aligned(const void *base, size_t size, unsigned char align) base 37 lib/sort.c (void)base; base 39 lib/sort.c lsbits |= (unsigned char)(uintptr_t)base; base 204 lib/sort.c void sort_r(void *base, size_t num, size_t size, base 217 lib/sort.c if (is_aligned(base, size, 8)) base 219 lib/sort.c else if (is_aligned(base, size, 4)) base 238 lib/sort.c do_swap(base, base + n, size, swap_func); base 255 lib/sort.c b = do_cmp(base + c, base + d, cmp_func, priv) >= 0 ? c : d; base 260 lib/sort.c while (b != a && do_cmp(base + a, base + b, cmp_func, priv) >= 0) base 265 lib/sort.c do_swap(base + b, base + c, size, swap_func); base 271 lib/sort.c void sort(void *base, size_t num, size_t size, base 275 lib/sort.c return sort_r(base, num, size, _CMP_WRAPPER, swap_func, cmp_func); base 10 lib/test-kstrtox.c unsigned int base; base 19 lib/test-kstrtox.c unsigned int base; \ base 36 lib/test-kstrtox.c rv = fn(t->str, t->base, &tmp); \ base 39 lib/test-kstrtox.c t->str, t->base, rv, tmp); \ base 54 lib/test-kstrtox.c rv = fn(t->str, t->base, &res); \ base 57 lib/test-kstrtox.c t->str, t->base, t->expected_res, rv); \ base 62 lib/test-kstrtox.c t->str, t->base, t->expected_res, res); \ base 57 lib/test_ida.c static void ida_check_destroy_1(struct ida *ida, unsigned int base) base 59 lib/test_ida.c IDA_BUG_ON(ida, ida_alloc_min(ida, base, GFP_KERNEL) != base); base 84 lib/test_ida.c static void ida_check_leaf(struct ida *ida, unsigned int base) base 89 lib/test_ida.c IDA_BUG_ON(ida, ida_alloc_min(ida, base, GFP_KERNEL) != base 90 lib/test_ida.c base + i); base 112 lib/test_ida.c unsigned long base = (1UL << 31) - j; base 114 lib/test_ida.c IDA_BUG_ON(ida, ida_alloc_min(ida, base, GFP_KERNEL) != base 115 lib/test_ida.c base + i); base 117 lib/test_ida.c IDA_BUG_ON(ida, ida_alloc_min(ida, base, GFP_KERNEL) != base 208 lib/test_xarray.c unsigned long base = round_down(index, 1UL << order); base 209 lib/test_xarray.c unsigned long next = base + (1UL << order); base 219 lib/test_xarray.c for (i = base; i < next; i++) { base 652 lib/test_xarray.c static noinline void check_xa_alloc_1(struct xarray *xa, unsigned int base) base 659 lib/test_xarray.c xa_alloc_index(xa, base, GFP_KERNEL); base 662 lib/test_xarray.c xa_erase_index(xa, base); base 666 lib/test_xarray.c xa_alloc_index(xa, base, GFP_KERNEL); base 669 lib/test_xarray.c for (i = base + 1; i < 2 * XA_CHUNK_SIZE; i++) base 671 lib/test_xarray.c for (i = base; i < 2 * XA_CHUNK_SIZE; i++) base 673 lib/test_xarray.c xa_alloc_index(xa, base, GFP_KERNEL); base 679 lib/test_xarray.c xa_alloc_index(xa, base, GFP_KERNEL); base 682 lib/test_xarray.c xa_alloc_index(xa, base + 1, GFP_KERNEL); base 683 lib/test_xarray.c xa_erase_index(xa, base + 1); base 686 lib/test_xarray.c xa_store_index(xa, base + 1, GFP_KERNEL); base 687 lib/test_xarray.c xa_alloc_index(xa, base + 2, GFP_KERNEL); base 690 lib/test_xarray.c xa_erase_index(xa, base); base 691 lib/test_xarray.c xa_alloc_index(xa, base, GFP_KERNEL); base 693 lib/test_xarray.c xa_erase_index(xa, base + 1); base 694 lib/test_xarray.c xa_erase_index(xa, base + 2); base 697 lib/test_xarray.c xa_alloc_index(xa, base + i, GFP_KERNEL); base 727 lib/test_xarray.c static noinline void check_xa_alloc_2(struct xarray *xa, unsigned int base) base 736 lib/test_xarray.c XA_BUG_ON(xa, id != base); base 744 lib/test_xarray.c XA_BUG_ON(xa, id != base); base 749 lib/test_xarray.c for (i = base; i < base + 10; i++) { base 766 lib/test_xarray.c for (i = base; i < base + 9; i++) { base 772 lib/test_xarray.c XA_BUG_ON(xa, xa_erase(xa, base + 9) != NULL); base 778 lib/test_xarray.c static noinline void check_xa_alloc_3(struct xarray *xa, unsigned int base) base 809 lib/test_xarray.c if (base != 0) base 810 lib/test_xarray.c xa_erase_index(xa, base); base 811 lib/test_xarray.c xa_erase_index(xa, base + 1); base 816 lib/test_xarray.c XA_BUG_ON(xa, xa_alloc_cyclic(xa, &id, xa_mk_index(base), base 818 lib/test_xarray.c XA_BUG_ON(xa, id != base); base 819 lib/test_xarray.c XA_BUG_ON(xa, xa_alloc_cyclic(xa, &id, xa_mk_index(base + 1), base 821 lib/test_xarray.c XA_BUG_ON(xa, id != base + 1); base 1413 lib/test_xarray.c unsigned long base = xas.xa_index; base 1423 lib/test_xarray.c void *old = xas_store(&xas, xa_mk_index(base + i)); base 1425 lib/test_xarray.c XA_BUG_ON(xa, old != xa_mk_index(base + i)); base 1436 lib/test_xarray.c for (i = base; i < base + (1UL << order); i++) base 61 lib/vsprintf.c unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base) base 66 lib/vsprintf.c cp = _parse_integer_fixup_radix(cp, &base); base 67 lib/vsprintf.c rv = _parse_integer(cp, base, &result); base 86 lib/vsprintf.c unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base) base 88 lib/vsprintf.c return simple_strtoull(cp, endp, base); base 100 lib/vsprintf.c long simple_strtol(const char *cp, char **endp, unsigned int base) base 103 lib/vsprintf.c return -simple_strtoul(cp + 1, endp, base); base 105 lib/vsprintf.c return simple_strtoul(cp, endp, base); base 117 lib/vsprintf.c long long simple_strtoll(const char *cp, char **endp, unsigned int base) base 120 lib/vsprintf.c return -simple_strtoull(cp + 1, endp, base); base 122 lib/vsprintf.c return simple_strtoull(cp, endp, base); base 407 lib/vsprintf.c unsigned int base:8; /* number base, 8, 10 or 16 only */ base 423 lib/vsprintf.c int need_pfx = ((spec.flags & SPECIAL) && spec.base != 10); base 449 lib/vsprintf.c if (spec.base == 16) base 457 lib/vsprintf.c if (num < spec.base) base 459 lib/vsprintf.c else if (spec.base != 10) { /* 8 or 16 */ base 460 lib/vsprintf.c int mask = spec.base - 1; base 463 lib/vsprintf.c if (spec.base == 16) base 493 lib/vsprintf.c if (spec.base == 16 || !is_zero) { base 498 lib/vsprintf.c if (spec.base == 16) { base 544 lib/vsprintf.c spec.base = 16; base 675 lib/vsprintf.c spec.base = 16; base 945 lib/vsprintf.c .base = 16, base 951 lib/vsprintf.c .base = 10, base 956 lib/vsprintf.c .base = 10, base 963 lib/vsprintf.c .base = 10, base 981 lib/vsprintf.c .base = 16, base 987 lib/vsprintf.c .base = 16, base 993 lib/vsprintf.c .base = 16, base 1134 lib/vsprintf.c spec = (struct printf_spec){ .flags = SMALL | ZEROPAD, .base = 16 }; base 1925 lib/vsprintf.c .base = 10, base 2327 lib/vsprintf.c spec->base = 10; base 2347 lib/vsprintf.c spec->base = 8; base 2355 lib/vsprintf.c spec->base = 16; base 3138 lib/vsprintf.c unsigned int base; base 3221 lib/vsprintf.c base = 10; base 3305 lib/vsprintf.c base = 8; base 3309 lib/vsprintf.c base = 16; base 3312 lib/vsprintf.c base = 0; base 3339 lib/vsprintf.c || (base == 16 && !isxdigit(digit)) base 3340 lib/vsprintf.c || (base == 10 && !isdigit(digit)) base 3341 lib/vsprintf.c || (base == 8 && (!isdigit(digit) || digit > '7')) base 3342 lib/vsprintf.c || (base == 0 && !isdigit(digit))) base 3347 lib/vsprintf.c simple_strtol(str, &next, base) : base 3348 lib/vsprintf.c simple_strtoll(str, &next, base); base 3351 lib/vsprintf.c simple_strtoul(str, &next, base) : base 3352 lib/vsprintf.c simple_strtoull(str, &next, base); base 3355 lib/vsprintf.c if (base == 0) base 3356 lib/vsprintf.c _parse_integer_fixup_radix(str, &base); base 3359 lib/vsprintf.c val.s = div_s64(val.s, base); base 3361 lib/vsprintf.c val.u = div_u64(val.u, base); base 416 lib/zlib_deflate/deftree.c int base = desc->stat_desc->extra_base; base 443 lib/zlib_deflate/deftree.c if (n >= base) xbits = extra[n-base]; base 41 lib/zlib_inflate/inftrees.c const unsigned short *base; /* base value table to use */ base 170 lib/zlib_inflate/inftrees.c base = extra = work; /* dummy value--not used */ base 174 lib/zlib_inflate/inftrees.c base = lbase; base 175 lib/zlib_inflate/inftrees.c base -= 257; base 181 lib/zlib_inflate/inftrees.c base = dbase; base 211 lib/zlib_inflate/inftrees.c this.val = base[work[sym]]; base 55 lib/zstd/compress.c const BYTE *base; /* All regular indexes relative to this position */ base 219 lib/zstd/compress.c U32 const end = (U32)(cctx->nextSrc - cctx->base); base 293 lib/zstd/compress.c zc->base = NULL; base 373 lib/zstd/compress.c dstCCtx->base = srcCCtx->base; base 996 lib/zstd/compress.c const BYTE *const base = zc->base; base 997 lib/zstd/compress.c const BYTE *ip = base + zc->nextToUpdate; base 1002 lib/zstd/compress.c hashTable[ZSTD_hashPtr(ip, hBits, mls)] = (U32)(ip - base); base 1013 lib/zstd/compress.c const BYTE *const base = cctx->base; base 1018 lib/zstd/compress.c const BYTE *const lowest = base + lowestIndex; base 1038 lib/zstd/compress.c U32 const curr = (U32)(ip - base); base 1040 lib/zstd/compress.c const BYTE *match = base + matchIndex; base 1072 lib/zstd/compress.c hashTable[ZSTD_hashPtr(base + curr + 2, hBits, mls)] = curr + 2; /* here because curr+2 could be > iend-8 */ base 1073 lib/zstd/compress.c hashTable[ZSTD_hashPtr(ip - 2, hBits, mls)] = (U32)(ip - 2 - base); base 1083 lib/zstd/compress.c hashTable[ZSTD_hashPtr(ip, hBits, mls)] = (U32)(ip - base); base 1121 lib/zstd/compress.c const BYTE *const base = ctx->base; base 1129 lib/zstd/compress.c const BYTE *const lowPrefixPtr = base + dictLimit; base 1139 lib/zstd/compress.c const BYTE *matchBase = matchIndex < dictLimit ? dictBase : base; base 1141 lib/zstd/compress.c const U32 curr = (U32)(ip - base); base 1143 lib/zstd/compress.c const BYTE *repBase = repIndex < dictLimit ? dictBase : base; base 1182 lib/zstd/compress.c hashTable[ZSTD_hashPtr(base + curr + 2, hBits, mls)] = curr + 2; base 1183 lib/zstd/compress.c hashTable[ZSTD_hashPtr(ip - 2, hBits, mls)] = (U32)(ip - 2 - base); base 1186 lib/zstd/compress.c U32 const curr2 = (U32)(ip - base); base 1188 lib/zstd/compress.c const BYTE *repMatch2 = repIndex2 < dictLimit ? dictBase + repIndex2 : base + repIndex2; base 1241 lib/zstd/compress.c const BYTE *const base = cctx->base; base 1242 lib/zstd/compress.c const BYTE *ip = base + cctx->nextToUpdate; base 1247 lib/zstd/compress.c hashSmall[ZSTD_hashPtr(ip, hBitsS, mls)] = (U32)(ip - base); base 1248 lib/zstd/compress.c hashLarge[ZSTD_hashPtr(ip, hBitsL, 8)] = (U32)(ip - base); base 1261 lib/zstd/compress.c const BYTE *const base = cctx->base; base 1266 lib/zstd/compress.c const BYTE *const lowest = base + lowestIndex; base 1287 lib/zstd/compress.c U32 const curr = (U32)(ip - base); base 1290 lib/zstd/compress.c const BYTE *matchLong = base + matchIndexL; base 1291 lib/zstd/compress.c const BYTE *match = base + matchIndexS; base 1311 lib/zstd/compress.c const BYTE *match3 = base + matchIndex3; base 1348 lib/zstd/compress.c hashLong[ZSTD_hashPtr(base + curr + 2, hBitsL, 8)] = hashSmall[ZSTD_hashPtr(base + curr + 2, hBitsS, mls)] = base 1350 lib/zstd/compress.c hashLong[ZSTD_hashPtr(ip - 2, hBitsL, 8)] = hashSmall[ZSTD_hashPtr(ip - 2, hBitsS, mls)] = (U32)(ip - 2 - base); base 1361 lib/zstd/compress.c hashSmall[ZSTD_hashPtr(ip, hBitsS, mls)] = (U32)(ip - base); base 1362 lib/zstd/compress.c hashLong[ZSTD_hashPtr(ip, hBitsL, 8)] = (U32)(ip - base); base 1402 lib/zstd/compress.c const BYTE *const base = ctx->base; base 1410 lib/zstd/compress.c const BYTE *const lowPrefixPtr = base + dictLimit; base 1420 lib/zstd/compress.c const BYTE *matchBase = matchIndex < dictLimit ? dictBase : base; base 1425 lib/zstd/compress.c const BYTE *matchLongBase = matchLongIndex < dictLimit ? dictBase : base; base 1428 lib/zstd/compress.c const U32 curr = (U32)(ip - base); base 1430 lib/zstd/compress.c const BYTE *repBase = repIndex < dictLimit ? dictBase : base; base 1460 lib/zstd/compress.c const BYTE *const match3Base = matchIndex3 < dictLimit ? dictBase : base; base 1502 lib/zstd/compress.c hashSmall[ZSTD_hashPtr(base + curr + 2, hBitsS, mls)] = curr + 2; base 1503 lib/zstd/compress.c hashLong[ZSTD_hashPtr(base + curr + 2, hBitsL, 8)] = curr + 2; base 1504 lib/zstd/compress.c hashSmall[ZSTD_hashPtr(ip - 2, hBitsS, mls)] = (U32)(ip - 2 - base); base 1505 lib/zstd/compress.c hashLong[ZSTD_hashPtr(ip - 2, hBitsL, 8)] = (U32)(ip - 2 - base); base 1508 lib/zstd/compress.c U32 const curr2 = (U32)(ip - base); base 1510 lib/zstd/compress.c const BYTE *repMatch2 = repIndex2 < dictLimit ? dictBase + repIndex2 : base + repIndex2; base 1571 lib/zstd/compress.c const BYTE *const base = zc->base; base 1575 lib/zstd/compress.c const BYTE *const prefixStart = base + dictLimit; base 1577 lib/zstd/compress.c const U32 curr = (U32)(ip - base); base 1593 lib/zstd/compress.c match = base + matchIndex; base 1600 lib/zstd/compress.c match = base + matchIndex; /* to prepare for next usage of match[matchLength] */ base 1654 lib/zstd/compress.c const BYTE *const base = zc->base; base 1658 lib/zstd/compress.c const BYTE *const prefixStart = base + dictLimit; base 1659 lib/zstd/compress.c const U32 curr = (U32)(ip - base); base 1676 lib/zstd/compress.c match = base + matchIndex; base 1683 lib/zstd/compress.c match = base + matchIndex; /* to prepare for next usage of match[matchLength] */ base 1726 lib/zstd/compress.c const BYTE *const base = zc->base; base 1727 lib/zstd/compress.c const U32 target = (U32)(ip - base); base 1731 lib/zstd/compress.c idx += ZSTD_insertBt1(zc, base + idx, mls, iend, nbCompares, 0); base 1737 lib/zstd/compress.c if (ip < zc->base + zc->nextToUpdate) base 1757 lib/zstd/compress.c const BYTE *const base = zc->base; base 1758 lib/zstd/compress.c const U32 target = (U32)(ip - base); base 1762 lib/zstd/compress.c idx += ZSTD_insertBt1(zc, base + idx, mls, iend, nbCompares, 1); base 1769 lib/zstd/compress.c if (ip < zc->base + zc->nextToUpdate) base 1802 lib/zstd/compress.c const BYTE *const base = zc->base; base 1803 lib/zstd/compress.c const U32 target = (U32)(ip - base); base 1807 lib/zstd/compress.c size_t const h = ZSTD_hashPtr(base + idx, hashLog, mls); base 1826 lib/zstd/compress.c const BYTE *const base = zc->base; base 1829 lib/zstd/compress.c const BYTE *const prefixStart = base + dictLimit; base 1832 lib/zstd/compress.c const U32 curr = (U32)(ip - base); base 1844 lib/zstd/compress.c match = base + matchIndex; base 1905 lib/zstd/compress.c const BYTE *const base = ctx->base + ctx->dictLimit; base 1915 lib/zstd/compress.c ip += (ip == base); base 1918 lib/zstd/compress.c U32 const maxRep = (U32)(ip - base); base 2005 lib/zstd/compress.c while ((start > anchor) && (start > base + offset - ZSTD_REP_MOVE) && base 2066 lib/zstd/compress.c const BYTE *const base = ctx->base; base 2069 lib/zstd/compress.c const BYTE *const prefixStart = base + dictLimit; base 2091 lib/zstd/compress.c U32 curr = (U32)(ip - base); base 2096 lib/zstd/compress.c const BYTE *const repBase = repIndex < dictLimit ? dictBase : base; base 2130 lib/zstd/compress.c const BYTE *const repBase = repIndex < dictLimit ? dictBase : base; base 2165 lib/zstd/compress.c const BYTE *const repBase = repIndex < dictLimit ? dictBase : base; base 2198 lib/zstd/compress.c U32 const matchIndex = (U32)((start - base) - (offset - ZSTD_REP_MOVE)); base 2199 lib/zstd/compress.c const BYTE *match = (matchIndex < dictLimit) ? dictBase + matchIndex : base + matchIndex; base 2219 lib/zstd/compress.c const U32 repIndex = (U32)((ip - base) - offset_2); base 2220 lib/zstd/compress.c const BYTE *const repBase = repIndex < dictLimit ? dictBase : base; base 2336 lib/zstd/compress.c const BYTE *const base = zc->base; base 2338 lib/zstd/compress.c const U32 curr = (U32)(istart - base); base 2379 lib/zstd/compress.c U32 const curr = (U32)(ip - cctx->base); base 2384 lib/zstd/compress.c cctx->base += correction; base 2394 lib/zstd/compress.c if ((U32)(ip + blockSize - cctx->base) > cctx->loadedDictEnd + maxDist) { base 2396 lib/zstd/compress.c U32 const newLowLimit = (U32)(ip + blockSize - cctx->base) - maxDist; base 2512 lib/zstd/compress.c cctx->dictLimit = (U32)(cctx->nextSrc - cctx->base); base 2513 lib/zstd/compress.c cctx->dictBase = cctx->base; base 2514 lib/zstd/compress.c cctx->base -= delta; base 2564 lib/zstd/compress.c zc->dictLimit = (U32)(zc->nextSrc - zc->base); base 2565 lib/zstd/compress.c zc->dictBase = zc->base; base 2566 lib/zstd/compress.c zc->base += ip - zc->nextSrc; base 2568 lib/zstd/compress.c zc->loadedDictEnd = zc->forceWindow ? 0 : (U32)(iend - zc->base); base 2597 lib/zstd/compress.c zc->nextToUpdate = (U32)(iend - zc->base); base 84 lib/zstd/decompress.c const void *base; /* start of curr segment */ base 111 lib/zstd/decompress.c dctx->base = NULL; base 874 lib/zstd/decompress.c const BYTE *base; base 880 lib/zstd/decompress.c size_t ZSTD_execSequenceLast7(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base, base 908 lib/zstd/decompress.c if (sequence.offset > (size_t)(oLitEnd - base)) { base 912 lib/zstd/decompress.c match = dictEnd - (base - match); base 923 lib/zstd/decompress.c match = base; base 1007 lib/zstd/decompress.c size_t ZSTD_execSequence(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base, base 1023 lib/zstd/decompress.c return ZSTD_execSequenceLast7(op, oend, sequence, litPtr, litLimit, base, vBase, dictEnd); base 1034 lib/zstd/decompress.c if (sequence.offset > (size_t)(oLitEnd - base)) { base 1038 lib/zstd/decompress.c match = dictEnd + (match - base); base 1049 lib/zstd/decompress.c match = base; base 1102 lib/zstd/decompress.c const BYTE *const base = (const BYTE *)(dctx->base); base 1133 lib/zstd/decompress.c size_t const oneSeqSize = ZSTD_execSequence(op, oend, sequence, &litPtr, litEnd, base, vBase, dictEnd); base 1237 lib/zstd/decompress.c seq.match = seqState->base + pos - seq.offset; /* single memory segment */ base 1263 lib/zstd/decompress.c size_t ZSTD_execSequenceLong(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base, base 1279 lib/zstd/decompress.c return ZSTD_execSequenceLast7(op, oend, sequence, litPtr, litLimit, base, vBase, dictEnd); base 1290 lib/zstd/decompress.c if (sequence.offset > (size_t)(oLitEnd - base)) { base 1304 lib/zstd/decompress.c match = base; base 1357 lib/zstd/decompress.c const BYTE *const base = (const BYTE *)(dctx->base); base 1387 lib/zstd/decompress.c seqState.base = base; base 1388 lib/zstd/decompress.c seqState.pos = (size_t)(op - base); base 1389 lib/zstd/decompress.c seqState.gotoDict = (uPtrDiff)dictEnd - (uPtrDiff)base; /* cast to avoid undefined behaviour */ base 1406 lib/zstd/decompress.c ZSTD_execSequenceLong(op, oend, sequences[(seqNb - ADVANCED_SEQS) & STOSEQ_MASK], &litPtr, litEnd, base, vBase, dictEnd); base 1419 lib/zstd/decompress.c size_t const oneSeqSize = ZSTD_execSequenceLong(op, oend, sequences[seqNb & STOSEQ_MASK], &litPtr, litEnd, base, vBase, dictEnd); base 1473 lib/zstd/decompress.c dctx->vBase = (const char *)dst - ((const char *)(dctx->previousDstEnd) - (const char *)(dctx->base)); base 1474 lib/zstd/decompress.c dctx->base = dst; base 1865 lib/zstd/decompress.c dctx->vBase = (const char *)dict - ((const char *)(dctx->previousDstEnd) - (const char *)(dctx->base)); base 1866 lib/zstd/decompress.c dctx->base = dict; base 2000 lib/zstd/decompress.c dstDCtx->base = ddict->dictContent; base 385 lib/zstd/huf_compress.c U32 base; base 397 lib/zstd/huf_compress.c rank[r].base++; base 400 lib/zstd/huf_compress.c rank[n - 1].base += rank[n].base; base 402 lib/zstd/huf_compress.c rank[n].curr = rank[n].base; base 407 lib/zstd/huf_compress.c while ((pos > rank[r].base) && (c > huffNode[pos - 1].count)) base 219 lib/zstd/zstd_opt.h const BYTE *const base = zc->base; base 221 lib/zstd/zstd_opt.h const U32 target = zc->nextToUpdate3 = (U32)(ip - base); base 225 lib/zstd/zstd_opt.h hashTable3[ZSTD_hash3Ptr(base + idx, hashLog3)] = idx; base 238 lib/zstd/zstd_opt.h const BYTE *const base = zc->base; base 239 lib/zstd/zstd_opt.h const U32 curr = (U32)(ip - base); base 251 lib/zstd/zstd_opt.h const BYTE *const prefixStart = base + dictLimit; base 269 lib/zstd/zstd_opt.h match = base + matchIndex3; base 301 lib/zstd/zstd_opt.h match = base + matchIndex; base 309 lib/zstd/zstd_opt.h match = base + matchIndex; /* to prepare for next usage of match[matchLength] */ base 359 lib/zstd/zstd_opt.h if (ip < zc->base + zc->nextToUpdate) base 383 lib/zstd/zstd_opt.h if (ip < zc->base + zc->nextToUpdate) base 415 lib/zstd/zstd_opt.h const BYTE *const base = ctx->base; base 416 lib/zstd/zstd_opt.h const BYTE *const prefixStart = base + ctx->dictLimit; base 708 lib/zstd/zstd_opt.h const BYTE *const base = ctx->base; base 711 lib/zstd/zstd_opt.h const BYTE *const prefixStart = base + dictLimit; base 740 lib/zstd/zstd_opt.h U32 curr = (U32)(ip - base); base 751 lib/zstd/zstd_opt.h const BYTE *const repBase = repIndex < dictLimit ? dictBase : base; base 864 lib/zstd/zstd_opt.h const BYTE *const repBase = repIndex < dictLimit ? dictBase : base; base 174 mm/cma.c int __init cma_init_reserved_mem(phys_addr_t base, phys_addr_t size, base 188 mm/cma.c if (!size || !memblock_is_region_reserved(base, size)) base 199 mm/cma.c if (ALIGN(base, alignment) != base || ALIGN(size, alignment) != size) base 214 mm/cma.c cma->base_pfn = PFN_DOWN(base); base 243 mm/cma.c int __init cma_declare_contiguous(phys_addr_t base, base 260 mm/cma.c __func__, &size, &base, &limit, &alignment); base 281 mm/cma.c if (fixed && base & (alignment - 1)) { base 284 mm/cma.c &base, &alignment); base 287 mm/cma.c base = ALIGN(base, alignment); base 291 mm/cma.c if (!base) base 302 mm/cma.c if (fixed && base < highmem_start && base + size > highmem_start) { base 305 mm/cma.c &base, &highmem_start); base 317 mm/cma.c if (base + size > limit) { base 320 mm/cma.c &size, &base, &limit); base 326 mm/cma.c if (memblock_is_region_reserved(base, size) || base 327 mm/cma.c memblock_reserve(base, size) < 0) { base 340 mm/cma.c if (base < highmem_start && limit > highmem_start) { base 347 mm/cma.c addr = memblock_phys_alloc_range(size, alignment, base, base 360 mm/cma.c base = addr; base 363 mm/cma.c ret = cma_init_reserved_mem(base, size, order_per_bit, name, res_cma); base 368 mm/cma.c &base); base 372 mm/cma.c memblock_free(base, size); base 4830 mm/hugetlb.c unsigned long base = addr & PUD_MASK; base 4831 mm/hugetlb.c unsigned long end = base + PUD_SIZE; base 4836 mm/hugetlb.c if (vma->vm_flags & VM_MAYSHARE && range_in_vma(vma, base, end)) base 398 mm/internal.h static inline struct page *mem_map_offset(struct page *base, int offset) base 401 mm/internal.h return nth_page(base, offset); base 402 mm/internal.h return base + offset; base 410 mm/internal.h struct page *base, int offset) base 413 mm/internal.h unsigned long pfn = page_to_pfn(base) + offset; base 174 mm/kasan/common.c void *base = task_stack_page(task); base 175 mm/kasan/common.c size_t size = sp - base; base 177 mm/kasan/common.c kasan_unpoison_shadow(base, size); base 194 mm/kasan/common.c void *base = (void *)((unsigned long)watermark & ~(THREAD_SIZE - 1)); base 196 mm/kasan/common.c kasan_unpoison_shadow(base, watermark - base); base 148 mm/memblock.c static inline phys_addr_t memblock_cap_size(phys_addr_t base, phys_addr_t *size) base 150 mm/memblock.c return *size = min(*size, PHYS_ADDR_MAX - base); base 163 mm/memblock.c phys_addr_t base, phys_addr_t size) base 168 mm/memblock.c if (memblock_addrs_overlap(base, size, type->regions[i].base, base 367 mm/memblock.c type->regions[0].base = 0; base 520 mm/memblock.c if (this->base + this->size != next->base || base 524 mm/memblock.c BUG_ON(this->base + this->size > next->base); base 549 mm/memblock.c int idx, phys_addr_t base, base 558 mm/memblock.c rgn->base = base; base 583 mm/memblock.c phys_addr_t base, phys_addr_t size, base 587 mm/memblock.c phys_addr_t obase = base; base 588 mm/memblock.c phys_addr_t end = base + memblock_cap_size(base, &size); base 598 mm/memblock.c type->regions[0].base = base; base 611 mm/memblock.c base = obase; base 615 mm/memblock.c phys_addr_t rbase = rgn->base; base 620 mm/memblock.c if (rend <= base) base 626 mm/memblock.c if (rbase > base) { base 633 mm/memblock.c memblock_insert_region(type, idx++, base, base 634 mm/memblock.c rbase - base, nid, base 638 mm/memblock.c base = min(rend, end); base 642 mm/memblock.c if (base < end) { base 645 mm/memblock.c memblock_insert_region(type, idx, base, end - base, base 680 mm/memblock.c int __init_memblock memblock_add_node(phys_addr_t base, phys_addr_t size, base 683 mm/memblock.c return memblock_add_range(&memblock.memory, base, size, nid, 0); base 697 mm/memblock.c int __init_memblock memblock_add(phys_addr_t base, phys_addr_t size) base 699 mm/memblock.c phys_addr_t end = base + size - 1; base 702 mm/memblock.c &base, &end, (void *)_RET_IP_); base 704 mm/memblock.c return memblock_add_range(&memblock.memory, base, size, MAX_NUMNODES, 0); base 724 mm/memblock.c phys_addr_t base, phys_addr_t size, base 727 mm/memblock.c phys_addr_t end = base + memblock_cap_size(base, &size); base 738 mm/memblock.c if (memblock_double_array(type, base, size) < 0) base 742 mm/memblock.c phys_addr_t rbase = rgn->base; base 747 mm/memblock.c if (rend <= base) base 750 mm/memblock.c if (rbase < base) { base 755 mm/memblock.c rgn->base = base; base 756 mm/memblock.c rgn->size -= base - rbase; base 757 mm/memblock.c type->total_size -= base - rbase; base 758 mm/memblock.c memblock_insert_region(type, idx, rbase, base - rbase, base 766 mm/memblock.c rgn->base = end; base 784 mm/memblock.c phys_addr_t base, phys_addr_t size) base 789 mm/memblock.c ret = memblock_isolate_range(type, base, size, &start_rgn, &end_rgn); base 798 mm/memblock.c int __init_memblock memblock_remove(phys_addr_t base, phys_addr_t size) base 800 mm/memblock.c phys_addr_t end = base + size - 1; base 803 mm/memblock.c &base, &end, (void *)_RET_IP_); base 805 mm/memblock.c return memblock_remove_range(&memblock.memory, base, size); base 816 mm/memblock.c int __init_memblock memblock_free(phys_addr_t base, phys_addr_t size) base 818 mm/memblock.c phys_addr_t end = base + size - 1; base 821 mm/memblock.c &base, &end, (void *)_RET_IP_); base 823 mm/memblock.c kmemleak_free_part_phys(base, size); base 824 mm/memblock.c return memblock_remove_range(&memblock.reserved, base, size); base 827 mm/memblock.c int __init_memblock memblock_reserve(phys_addr_t base, phys_addr_t size) base 829 mm/memblock.c phys_addr_t end = base + size - 1; base 832 mm/memblock.c &base, &end, (void *)_RET_IP_); base 834 mm/memblock.c return memblock_add_range(&memblock.reserved, base, size, MAX_NUMNODES, 0); base 848 mm/memblock.c static int __init_memblock memblock_setclr_flag(phys_addr_t base, base 854 mm/memblock.c ret = memblock_isolate_range(type, base, size, &start_rgn, &end_rgn); base 878 mm/memblock.c int __init_memblock memblock_mark_hotplug(phys_addr_t base, phys_addr_t size) base 880 mm/memblock.c return memblock_setclr_flag(base, size, 1, MEMBLOCK_HOTPLUG); base 890 mm/memblock.c int __init_memblock memblock_clear_hotplug(phys_addr_t base, phys_addr_t size) base 892 mm/memblock.c return memblock_setclr_flag(base, size, 0, MEMBLOCK_HOTPLUG); base 902 mm/memblock.c int __init_memblock memblock_mark_mirror(phys_addr_t base, phys_addr_t size) base 906 mm/memblock.c return memblock_setclr_flag(base, size, 1, MEMBLOCK_MIRROR); base 916 mm/memblock.c int __init_memblock memblock_mark_nomap(phys_addr_t base, phys_addr_t size) base 918 mm/memblock.c return memblock_setclr_flag(base, size, 1, MEMBLOCK_NOMAP); base 928 mm/memblock.c int __init_memblock memblock_clear_nomap(phys_addr_t base, phys_addr_t size) base 930 mm/memblock.c return memblock_setclr_flag(base, size, 0, MEMBLOCK_NOMAP); base 949 mm/memblock.c phys_addr_t base = r->base; base 953 mm/memblock.c *out_start = base; base 955 mm/memblock.c *out_end = base + size - 1; base 1031 mm/memblock.c phys_addr_t m_start = m->base; base 1032 mm/memblock.c phys_addr_t m_end = m->base + m->size; base 1057 mm/memblock.c r_start = idx_b ? r[-1].base + r[-1].size : 0; base 1059 mm/memblock.c r->base : PHYS_ADDR_MAX; base 1135 mm/memblock.c phys_addr_t m_start = m->base; base 1136 mm/memblock.c phys_addr_t m_end = m->base + m->size; base 1161 mm/memblock.c r_start = idx_b ? r[-1].base + r[-1].size : 0; base 1163 mm/memblock.c r->base : PHYS_ADDR_MAX; base 1206 mm/memblock.c if (PFN_UP(r->base) >= PFN_DOWN(r->base + r->size)) base 1217 mm/memblock.c *out_start_pfn = PFN_UP(r->base); base 1219 mm/memblock.c *out_end_pfn = PFN_DOWN(r->base + r->size); base 1237 mm/memblock.c int __init_memblock memblock_set_node(phys_addr_t base, phys_addr_t size, base 1243 mm/memblock.c ret = memblock_isolate_range(type, base, size, &start_rgn, &end_rgn); base 1566 mm/memblock.c void __init __memblock_free_late(phys_addr_t base, phys_addr_t size) base 1570 mm/memblock.c end = base + size - 1; base 1572 mm/memblock.c __func__, &base, &end, (void *)_RET_IP_); base 1573 mm/memblock.c kmemleak_free_part_phys(base, size); base 1574 mm/memblock.c cursor = PFN_UP(base); base 1575 mm/memblock.c end = PFN_DOWN(base + size); base 1617 mm/memblock.c return memblock.memory.regions[0].base; base 1624 mm/memblock.c return (memblock.memory.regions[idx].base + memblock.memory.regions[idx].size); base 1639 mm/memblock.c max_addr = r->base + limit; base 1668 mm/memblock.c void __init memblock_cap_memory_range(phys_addr_t base, phys_addr_t size) base 1676 mm/memblock.c ret = memblock_isolate_range(&memblock.memory, base, size, base 1691 mm/memblock.c memblock_remove_range(&memblock.reserved, 0, base); base 1693 mm/memblock.c base + size, PHYS_ADDR_MAX); base 1719 mm/memblock.c if (addr < type->regions[mid].base) base 1721 mm/memblock.c else if (addr >= (type->regions[mid].base + base 1759 mm/memblock.c *start_pfn = PFN_DOWN(type->regions[mid].base); base 1760 mm/memblock.c *end_pfn = PFN_DOWN(type->regions[mid].base + type->regions[mid].size); base 1776 mm/memblock.c bool __init_memblock memblock_is_region_memory(phys_addr_t base, phys_addr_t size) base 1778 mm/memblock.c int idx = memblock_search(&memblock.memory, base); base 1779 mm/memblock.c phys_addr_t end = base + memblock_cap_size(base, &size); base 1783 mm/memblock.c return (memblock.memory.regions[idx].base + base 1798 mm/memblock.c bool __init_memblock memblock_is_region_reserved(phys_addr_t base, phys_addr_t size) base 1800 mm/memblock.c memblock_cap_size(base, &size); base 1801 mm/memblock.c return memblock_overlaps_region(&memblock.reserved, base, size); base 1810 mm/memblock.c orig_start = r->base; base 1811 mm/memblock.c orig_end = r->base + r->size; base 1819 mm/memblock.c r->base = start; base 1841 mm/memblock.c phys_addr_t base, end, size; base 1851 mm/memblock.c base = rgn->base; base 1853 mm/memblock.c end = base + size - 1; base 1861 mm/memblock.c type->name, idx, &base, &end, &size, nid_buf, flags); base 1997 mm/memblock.c end = reg->base + reg->size - 1; base 2000 mm/memblock.c seq_printf(m, "%pa..%pa\n", ®->base, &end); base 4483 mm/memory.c int i, n, base, l; base 4492 mm/memory.c base = 0; base 4501 mm/memory.c base = pages_per_huge_page - 2 * (pages_per_huge_page - n); base 4504 mm/memory.c for (i = 0; i < base; i++) { base 4514 mm/memory.c int left_idx = base + i; base 4515 mm/memory.c int right_idx = base + 2 * l - 1 - i; base 2085 mm/mmap.c #define arch_get_mmap_base(addr, base) (base) base 1010 mm/nommu.c void *base; base 1046 mm/nommu.c base = alloc_pages_exact(total << PAGE_SHIFT, GFP_KERNEL); base 1047 mm/nommu.c if (!base) base 1053 mm/nommu.c region->vm_start = (unsigned long) base; base 1067 mm/nommu.c ret = kernel_read(vma->vm_file, base, len, &fpos); base 1073 mm/nommu.c memset(base + ret, 0, len - ret); base 7130 mm/page_alloc.c usable_startpfn = PFN_DOWN(r->base); base 102 mm/page_ext.c static inline struct page_ext *get_entry(void *base, unsigned long index) base 104 mm/page_ext.c return base + page_ext_size * index; base 119 mm/page_ext.c struct page_ext *base; base 121 mm/page_ext.c base = NODE_DATA(page_to_nid(page))->node_page_ext; base 128 mm/page_ext.c if (unlikely(!base)) base 132 mm/page_ext.c return get_entry(base, index); base 137 mm/page_ext.c struct page_ext *base; base 156 mm/page_ext.c base = memblock_alloc_try_nid( base 159 mm/page_ext.c if (!base) base 161 mm/page_ext.c NODE_DATA(nid)->node_page_ext = base; base 224 mm/page_ext.c struct page_ext *base; base 233 mm/page_ext.c base = alloc_page_ext(table_size, nid); base 240 mm/page_ext.c kmemleak_not_leak(base); base 242 mm/page_ext.c if (!base) { base 252 mm/page_ext.c section->page_ext = (void *)base - page_ext_size * pfn; base 276 mm/page_ext.c struct page_ext *base; base 281 mm/page_ext.c base = get_entry(ms->page_ext, pfn); base 282 mm/page_ext.c free_page_ext(base); base 2001 mm/percpu.c void __percpu *base = __addr_to_pcpu_ptr(pcpu_base_addr); base 2005 mm/percpu.c void *start = per_cpu_ptr(base, cpu); base 2012 mm/percpu.c per_cpu_ptr(base, get_boot_cpu_id()); base 2063 mm/percpu.c void __percpu *base = __addr_to_pcpu_ptr(pcpu_base_addr); base 2085 mm/percpu.c void *start = per_cpu_ptr(base, cpu); base 2704 mm/percpu.c void *base = (void *)ULONG_MAX; base 2746 mm/percpu.c base = min(ptr, base); base 2750 mm/percpu.c max_distance = areas[highest_group] - base; base 2787 mm/percpu.c ai->groups[group].base_offset = areas[group] - base; base 2794 mm/percpu.c pcpu_setup_first_chunk(ai, base); base 148 mm/slob.c slob_t *base = (slob_t *)((unsigned long)s & PAGE_MASK); base 149 mm/slob.c slobidx_t offset = next - base; base 173 mm/slob.c slob_t *base = (slob_t *)((unsigned long)s & PAGE_MASK); base 180 mm/slob.c return base+next; base 511 mm/slub.c void *base; base 516 mm/slub.c base = page_address(page); base 519 mm/slub.c if (object < base || object >= base + page->objects * s->size || base 520 mm/slub.c (object - base) % s->size) { base 3234 mm/vmalloc.c unsigned long base, start, size, end, last_end; base 3286 mm/vmalloc.c base = pvm_determine_end_from_reverse(&va, align) - end; base 3293 mm/vmalloc.c if (base + last_end < vmalloc_start + last_end) base 3306 mm/vmalloc.c if (base + end > va->va_end) { base 3307 mm/vmalloc.c base = pvm_determine_end_from_reverse(&va, align) - end; base 3315 mm/vmalloc.c if (base + start < va->va_start) { base 3317 mm/vmalloc.c base = pvm_determine_end_from_reverse(&va, align) - end; base 3332 mm/vmalloc.c va = pvm_find_va_enclose_addr(base + end); base 3339 mm/vmalloc.c start = base + offsets[area]; base 136 net/batman-adv/bat_v_elp.c if (ret == 0 && link_settings.base.autoneg == AUTONEG_ENABLE) { base 138 net/batman-adv/bat_v_elp.c if (link_settings.base.duplex == DUPLEX_FULL) base 143 net/batman-adv/bat_v_elp.c throughput = link_settings.base.speed; base 119 net/batman-adv/tp_meter.c static u32 batadv_tp_cwnd(u32 base, u32 increment, u32 min) base 121 net/batman-adv/tp_meter.c u32 new_size = base + increment; base 124 net/batman-adv/tp_meter.c if (new_size < base) base 40 net/bridge/br_if.c switch (ecmd.base.speed) { base 191 net/bridge/netfilter/ebtables.c const char *base; base 211 net/bridge/netfilter/ebtables.c base = private->entries; base 278 net/bridge/netfilter/ebtables.c chaininfo = (struct ebt_entries *) (base + verdict); base 762 net/bridge/netfilter/ebtables.c unsigned int udc_cnt, unsigned int hooknr, char *base) base 795 net/bridge/netfilter/ebtables.c (struct ebt_entries *)(base + verdict); base 1330 net/bridge/netfilter/ebtables.c const char *base, char __user *ubase) base 1332 net/bridge/netfilter/ebtables.c return ebt_obj_to_user(ubase + ((char *)m - base), base 1339 net/bridge/netfilter/ebtables.c const char *base, char __user *ubase) base 1341 net/bridge/netfilter/ebtables.c return ebt_obj_to_user(ubase + ((char *)w - base), base 1347 net/bridge/netfilter/ebtables.c static inline int ebt_entry_to_user(struct ebt_entry *e, const char *base, base 1356 net/bridge/netfilter/ebtables.c if (copy_to_user(ubase + ((char *)e - base), e, base 1362 net/bridge/netfilter/ebtables.c if (copy_to_user(ubase + ((char *)e - base), e, sizeof(*e))) base 1365 net/bridge/netfilter/ebtables.c hlp = ubase + (((char *)e + e->target_offset) - base); base 1368 net/bridge/netfilter/ebtables.c ret = EBT_MATCH_ITERATE(e, ebt_match_to_user, base, ubase); base 1371 net/bridge/netfilter/ebtables.c ret = EBT_WATCHER_ITERATE(e, ebt_watcher_to_user, base, ubase); base 1732 net/bridge/netfilter/ebtables.c const void *base, base 1743 net/bridge/netfilter/ebtables.c entry_offset = (void *)e - base; base 1762 net/bridge/netfilter/ebtables.c (e < (struct ebt_entry *)(base - hookptr))) { base 1907 net/bridge/netfilter/ebtables.c const unsigned char *base) base 1984 net/bridge/netfilter/ebtables.c struct ebt_entries_buf_state *state, const void *base) base 2020 net/bridge/netfilter/ebtables.c ret = compat_mtw_from_user(match32, type, state, base); base 2042 net/bridge/netfilter/ebtables.c static int size_entry_mwt(const struct ebt_entry *entry, const unsigned char *base, base 2113 net/bridge/netfilter/ebtables.c ret = ebt_size_mwt(match32, size, i, state, base); base 2125 net/bridge/netfilter/ebtables.c unsigned int offset = buf_start - (char *) base; base 101 net/ceph/auth_none.c au->base.destroy = ceph_auth_none_destroy_authorizer; base 16 net/ceph/auth_none.h struct ceph_authorizer base; base 642 net/ceph/auth_x.c au->base.destroy = ceph_x_destroy_authorizer; base 31 net/ceph/auth_x.h struct ceph_authorizer base; base 5351 net/core/dev.c unsigned int i, base = ~0U; base 5355 net/core/dev.c base += i; base 5356 net/core/dev.c __napi_gro_flush_chain(napi, base, flush_old); base 464 net/core/ethtool.c link_ksettings->base.speed base 466 net/core/ethtool.c link_ksettings->base.duplex base 468 net/core/ethtool.c link_ksettings->base.port base 470 net/core/ethtool.c link_ksettings->base.phy_address base 472 net/core/ethtool.c link_ksettings->base.autoneg base 474 net/core/ethtool.c link_ksettings->base.mdio_support base 476 net/core/ethtool.c link_ksettings->base.eth_tp_mdix base 478 net/core/ethtool.c link_ksettings->base.eth_tp_mdix_ctrl base 509 net/core/ethtool.c ethtool_cmd_speed_set(legacy_settings, link_ksettings->base.speed); base 511 net/core/ethtool.c = link_ksettings->base.duplex; base 513 net/core/ethtool.c = link_ksettings->base.port; base 515 net/core/ethtool.c = link_ksettings->base.phy_address; base 517 net/core/ethtool.c = link_ksettings->base.autoneg; base 519 net/core/ethtool.c = link_ksettings->base.mdio_support; base 521 net/core/ethtool.c = link_ksettings->base.eth_tp_mdix; base 523 net/core/ethtool.c = link_ksettings->base.eth_tp_mdix_ctrl; base 525 net/core/ethtool.c = link_ksettings->base.transceiver; base 535 net/core/ethtool.c struct ethtool_link_settings base; base 568 net/core/ethtool.c memcpy(&to->base, &link_usettings.base, sizeof(to->base)); base 592 net/core/ethtool.c memcpy(&link_usettings.base, &from->base, sizeof(link_usettings)); base 621 net/core/ethtool.c if (copy_from_user(&link_ksettings.base, useraddr, base 622 net/core/ethtool.c sizeof(link_ksettings.base))) base 626 net/core/ethtool.c != link_ksettings.base.link_mode_masks_nwords) { base 629 net/core/ethtool.c link_ksettings.base.cmd = ETHTOOL_GLINKSETTINGS; base 633 net/core/ethtool.c link_ksettings.base.link_mode_masks_nwords base 639 net/core/ethtool.c if (copy_to_user(useraddr, &link_ksettings.base, base 640 net/core/ethtool.c sizeof(link_ksettings.base))) base 656 net/core/ethtool.c link_ksettings.base.cmd = ETHTOOL_GLINKSETTINGS; base 657 net/core/ethtool.c link_ksettings.base.link_mode_masks_nwords base 676 net/core/ethtool.c if (copy_from_user(&link_ksettings.base, useraddr, base 677 net/core/ethtool.c sizeof(link_ksettings.base))) base 681 net/core/ethtool.c != link_ksettings.base.link_mode_masks_nwords) base 693 net/core/ethtool.c != link_ksettings.base.link_mode_masks_nwords) base 755 net/core/ethtool.c link_ksettings.base.link_mode_masks_nwords = base 113 net/core/neighbour.c unsigned long neigh_rand_reach_time(unsigned long base) base 115 net/core/neighbour.c return base ? (prandom_u32() % base) + (base >> 1) : 0; base 205 net/core/net-sysfs.c ret = sprintf(buf, fmt_dec, cmd.base.speed); base 227 net/core/net-sysfs.c switch (cmd.base.duplex) { base 480 net/decnet/dn_neigh.c static char *dn_find_slot(char *base, int max, int priority) base 485 net/decnet/dn_neigh.c base += 6; /* skip first id */ base 488 net/decnet/dn_neigh.c if (!min || (*base < *min)) base 489 net/decnet/dn_neigh.c min = base; base 490 net/decnet/dn_neigh.c base += 7; /* find next priority */ base 120 net/ipv4/ah4.c static void ah_output_done(struct crypto_async_request *base, int err) base 124 net/ipv4/ah4.c struct sk_buff *skb = base->data; base 265 net/ipv4/ah4.c static void ah_input_done(struct crypto_async_request *base, int err) base 270 net/ipv4/ah4.c struct sk_buff *skb = base->data; base 120 net/ipv4/esp4.c static void esp_output_done(struct crypto_async_request *base, int err) base 122 net/ipv4/esp4.c struct sk_buff *skb = base->data; base 204 net/ipv4/esp4.c static void esp_output_done_esn(struct crypto_async_request *base, int err) base 206 net/ipv4/esp4.c struct sk_buff *skb = base->data; base 209 net/ipv4/esp4.c esp_output_done(base, err); base 653 net/ipv4/esp4.c static void esp_input_done(struct crypto_async_request *base, int err) base 655 net/ipv4/esp4.c struct sk_buff *skb = base->data; base 683 net/ipv4/esp4.c static void esp_input_done_esn(struct crypto_async_request *base, int err) base 685 net/ipv4/esp4.c struct sk_buff *skb = base->data; base 688 net/ipv4/esp4.c esp_input_done(base, err); base 99 net/ipv4/inetpeer.c struct inet_peer_base *base, base 109 net/ipv4/inetpeer.c pp = &base->rb_root.rb_node; base 128 net/ipv4/inetpeer.c } else if (unlikely(read_seqretry(&base->lock, seq))) { base 147 net/ipv4/inetpeer.c static void inet_peer_gc(struct inet_peer_base *base, base 155 net/ipv4/inetpeer.c if (base->total >= inet_peer_threshold) base 160 net/ipv4/inetpeer.c base->total / inet_peer_threshold * HZ; base 175 net/ipv4/inetpeer.c rb_erase(&p->rb_node, &base->rb_root); base 176 net/ipv4/inetpeer.c base->total--; base 182 net/ipv4/inetpeer.c struct inet_peer *inet_getpeer(struct inet_peer_base *base, base 195 net/ipv4/inetpeer.c seq = read_seqbegin(&base->lock); base 196 net/ipv4/inetpeer.c p = lookup(daddr, base, seq, NULL, &gc_cnt, &parent, &pp); base 197 net/ipv4/inetpeer.c invalidated = read_seqretry(&base->lock, seq); base 211 net/ipv4/inetpeer.c write_seqlock_bh(&base->lock); base 214 net/ipv4/inetpeer.c p = lookup(daddr, base, seq, gc_stack, &gc_cnt, &parent, &pp); base 231 net/ipv4/inetpeer.c rb_insert_color(&p->rb_node, &base->rb_root); base 232 net/ipv4/inetpeer.c base->total++; base 236 net/ipv4/inetpeer.c inet_peer_gc(base, gc_stack, gc_cnt); base 237 net/ipv4/inetpeer.c write_sequnlock_bh(&base->lock); base 296 net/ipv4/inetpeer.c void inetpeer_invalidate_tree(struct inet_peer_base *base) base 298 net/ipv4/inetpeer.c struct rb_node *p = rb_first(&base->rb_root); base 304 net/ipv4/inetpeer.c rb_erase(&peer->rb_node, &base->rb_root); base 309 net/ipv4/inetpeer.c base->total = 0; base 1310 net/ipv4/ip_output.c err = ip_setup_cork(sk, &inet->cork.base, ipc, rtp); base 1317 net/ipv4/ip_output.c return __ip_append_data(sk, fl4, &sk->sk_write_queue, &inet->cork.base, base 1345 net/ipv4/ip_output.c cork = &inet->cork.base; base 1602 net/ipv4/ip_output.c __ip_flush_pending_frames(sk, &sk->sk_write_queue, &inet_sk(sk)->cork.base); base 171 net/ipv4/netfilter/arp_tables.c get_entry(const void *base, unsigned int offset) base 173 net/ipv4/netfilter/arp_tables.c return (struct arpt_entry *)(base + offset); base 453 net/ipv4/netfilter/arp_tables.c const unsigned char *base, base 483 net/ipv4/netfilter/arp_tables.c if ((unsigned char *)e - base == hook_entries[h]) base 485 net/ipv4/netfilter/arp_tables.c if ((unsigned char *)e - base == underflows[h]) { base 737 net/ipv4/netfilter/arp_tables.c const void *base, struct xt_table_info *newinfo) base 744 net/ipv4/netfilter/arp_tables.c entry_offset = (void *)e - base; base 755 net/ipv4/netfilter/arp_tables.c (e < (struct arpt_entry *)(base + info->hook_entry[i]))) base 758 net/ipv4/netfilter/arp_tables.c (e < (struct arpt_entry *)(base + info->underflow[i]))) base 1075 net/ipv4/netfilter/arp_tables.c const unsigned char *base, base 1101 net/ipv4/netfilter/arp_tables.c entry_offset = (void *)e - (void *)base; base 1129 net/ipv4/netfilter/arp_tables.c struct xt_table_info *newinfo, unsigned char *base) base 1150 net/ipv4/netfilter/arp_tables.c if ((unsigned char *)de - base < newinfo->hook_entry[h]) base 1152 net/ipv4/netfilter/arp_tables.c if ((unsigned char *)de - base < newinfo->underflow[h]) base 103 net/ipv4/netfilter/ip_tables.c get_entry(const void *base, unsigned int offset) base 105 net/ipv4/netfilter/ip_tables.c return (struct ipt_entry *)(base + offset); base 590 net/ipv4/netfilter/ip_tables.c const unsigned char *base, base 620 net/ipv4/netfilter/ip_tables.c if ((unsigned char *)e - base == hook_entries[h]) base 622 net/ipv4/netfilter/ip_tables.c if ((unsigned char *)e - base == underflows[h]) { base 892 net/ipv4/netfilter/ip_tables.c const void *base, struct xt_table_info *newinfo) base 900 net/ipv4/netfilter/ip_tables.c entry_offset = (void *)e - base; base 912 net/ipv4/netfilter/ip_tables.c (e < (struct ipt_entry *)(base + info->hook_entry[i]))) base 915 net/ipv4/netfilter/ip_tables.c (e < (struct ipt_entry *)(base + info->underflow[i]))) base 1289 net/ipv4/netfilter/ip_tables.c const unsigned char *base, base 1317 net/ipv4/netfilter/ip_tables.c entry_offset = (void *)e - (void *)base; base 1357 net/ipv4/netfilter/ip_tables.c struct xt_table_info *newinfo, unsigned char *base) base 1383 net/ipv4/netfilter/ip_tables.c if ((unsigned char *)de - base < newinfo->hook_entry[h]) base 1385 net/ipv4/netfilter/ip_tables.c if ((unsigned char *)de - base < newinfo->underflow[h]) base 601 net/ipv4/tcp_bpf.c struct proto *base) base 603 net/ipv4/tcp_bpf.c prot[TCP_BPF_BASE] = *base; base 919 net/ipv4/udp.c err = udp_send_skb(skb, fl4, &inet->cork.base); base 68 net/ipv6/ah6.c static inline struct tmp_ext *ah_tmp_ext(void *base) base 70 net/ipv6/ah6.c return base + IPV6HDR_BASELEN; base 287 net/ipv6/ah6.c static void ah6_output_done(struct crypto_async_request *base, int err) base 292 net/ipv6/ah6.c struct sk_buff *skb = base->data; base 457 net/ipv6/ah6.c static void ah6_input_done(struct crypto_async_request *base, int err) base 462 net/ipv6/ah6.c struct sk_buff *skb = base->data; base 127 net/ipv6/esp6.c static void esp_output_done(struct crypto_async_request *base, int err) base 129 net/ipv6/esp6.c struct sk_buff *skb = base->data; base 202 net/ipv6/esp6.c static void esp_output_done_esn(struct crypto_async_request *base, int err) base 204 net/ipv6/esp6.c struct sk_buff *skb = base->data; base 207 net/ipv6/esp6.c esp_output_done(base, err); base 553 net/ipv6/esp6.c static void esp_input_done(struct crypto_async_request *base, int err) base 555 net/ipv6/esp6.c struct sk_buff *skb = base->data; base 583 net/ipv6/esp6.c static void esp_input_done_esn(struct crypto_async_request *base, int err) base 585 net/ipv6/esp6.c struct sk_buff *skb = base->data; base 588 net/ipv6/esp6.c esp_input_done(base, err); base 1281 net/ipv6/ip6_output.c cork->base.dst = &rt->dst; base 1297 net/ipv6/ip6_output.c cork->base.fragsize = mtu; base 1298 net/ipv6/ip6_output.c cork->base.gso_size = ipc6->gso_size; base 1299 net/ipv6/ip6_output.c cork->base.tx_flags = 0; base 1300 net/ipv6/ip6_output.c cork->base.mark = ipc6->sockc.mark; base 1301 net/ipv6/ip6_output.c sock_tx_timestamp(sk, ipc6->sockc.tsflags, &cork->base.tx_flags); base 1304 net/ipv6/ip6_output.c cork->base.flags |= IPCORK_ALLFRAG; base 1305 net/ipv6/ip6_output.c cork->base.length = 0; base 1307 net/ipv6/ip6_output.c cork->base.transmit_time = ipc6->sockc.transmit_time; base 1687 net/ipv6/ip6_output.c return __ip6_append_data(sk, fl6, &sk->sk_write_queue, &inet->cork.base, base 1705 net/ipv6/ip6_output.c if (cork->base.dst) { base 1706 net/ipv6/ip6_output.c dst_release(cork->base.dst); base 1707 net/ipv6/ip6_output.c cork->base.dst = NULL; base 1708 net/ipv6/ip6_output.c cork->base.flags &= ~IPCORK_ALLFRAG; base 1725 net/ipv6/ip6_output.c struct rt6_info *rt = (struct rt6_info *)cork->base.dst; base 1771 net/ipv6/ip6_output.c skb->mark = cork->base.mark; base 1773 net/ipv6/ip6_output.c skb->tstamp = cork->base.transmit_time; base 1861 net/ipv6/ip6_output.c cork->base.flags = 0; base 1862 net/ipv6/ip6_output.c cork->base.addr = 0; base 1863 net/ipv6/ip6_output.c cork->base.opt = NULL; base 1864 net/ipv6/ip6_output.c cork->base.dst = NULL; base 1874 net/ipv6/ip6_output.c err = __ip6_append_data(sk, fl6, &queue, &cork->base, &v6_cork, base 128 net/ipv6/netfilter/ip6_tables.c get_entry(const void *base, unsigned int offset) base 130 net/ipv6/netfilter/ip6_tables.c return (struct ip6t_entry *)(base + offset); base 608 net/ipv6/netfilter/ip6_tables.c const unsigned char *base, base 638 net/ipv6/netfilter/ip6_tables.c if ((unsigned char *)e - base == hook_entries[h]) base 640 net/ipv6/netfilter/ip6_tables.c if ((unsigned char *)e - base == underflows[h]) { base 908 net/ipv6/netfilter/ip6_tables.c const void *base, struct xt_table_info *newinfo) base 916 net/ipv6/netfilter/ip6_tables.c entry_offset = (void *)e - base; base 928 net/ipv6/netfilter/ip6_tables.c (e < (struct ip6t_entry *)(base + info->hook_entry[i]))) base 931 net/ipv6/netfilter/ip6_tables.c (e < (struct ip6t_entry *)(base + info->underflow[i]))) base 1305 net/ipv6/netfilter/ip6_tables.c const unsigned char *base, base 1333 net/ipv6/netfilter/ip6_tables.c entry_offset = (void *)e - (void *)base; base 1373 net/ipv6/netfilter/ip6_tables.c struct xt_table_info *newinfo, unsigned char *base) base 1398 net/ipv6/netfilter/ip6_tables.c if ((unsigned char *)de - base < newinfo->hook_entry[h]) base 1400 net/ipv6/netfilter/ip6_tables.c if ((unsigned char *)de - base < newinfo->underflow[h]) base 558 net/ipv6/raw.c total_len = inet_sk(sk)->cork.base.length; base 1206 net/ipv6/udp.c err = udp_v6_send_skb(skb, &fl6, &inet_sk(sk)->cork.base); base 1471 net/ipv6/udp.c err = udp_v6_send_skb(skb, &fl6, &cork.base); base 110 net/netfilter/nf_conntrack_h323_asn1.c static int decode_nul(struct bitstr *bs, const struct field_t *f, char *base, int level); base 111 net/netfilter/nf_conntrack_h323_asn1.c static int decode_bool(struct bitstr *bs, const struct field_t *f, char *base, int level); base 112 net/netfilter/nf_conntrack_h323_asn1.c static int decode_oid(struct bitstr *bs, const struct field_t *f, char *base, int level); base 113 net/netfilter/nf_conntrack_h323_asn1.c static int decode_int(struct bitstr *bs, const struct field_t *f, char *base, int level); base 114 net/netfilter/nf_conntrack_h323_asn1.c static int decode_enum(struct bitstr *bs, const struct field_t *f, char *base, int level); base 115 net/netfilter/nf_conntrack_h323_asn1.c static int decode_bitstr(struct bitstr *bs, const struct field_t *f, char *base, int level); base 116 net/netfilter/nf_conntrack_h323_asn1.c static int decode_numstr(struct bitstr *bs, const struct field_t *f, char *base, int level); base 117 net/netfilter/nf_conntrack_h323_asn1.c static int decode_octstr(struct bitstr *bs, const struct field_t *f, char *base, int level); base 118 net/netfilter/nf_conntrack_h323_asn1.c static int decode_bmpstr(struct bitstr *bs, const struct field_t *f, char *base, int level); base 119 net/netfilter/nf_conntrack_h323_asn1.c static int decode_seq(struct bitstr *bs, const struct field_t *f, char *base, int level); base 120 net/netfilter/nf_conntrack_h323_asn1.c static int decode_seqof(struct bitstr *bs, const struct field_t *f, char *base, int level); base 121 net/netfilter/nf_conntrack_h323_asn1.c static int decode_choice(struct bitstr *bs, const struct field_t *f, char *base, int level); base 277 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 285 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 296 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 315 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 335 net/netfilter/nf_conntrack_h323_asn1.c if (base && (f->attr & DECODE)) { /* timeToLive */ base 338 net/netfilter/nf_conntrack_h323_asn1.c *((unsigned int *)(base + f->offset)) = v; base 362 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 378 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 414 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 434 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 444 net/netfilter/nf_conntrack_h323_asn1.c if (base && (f->attr & DECODE)) { base 451 net/netfilter/nf_conntrack_h323_asn1.c *((unsigned int *)(base + f->offset)) = base 487 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 516 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 526 net/netfilter/nf_conntrack_h323_asn1.c base = (base && (f->attr & DECODE)) ? base + f->offset : NULL; base 537 net/netfilter/nf_conntrack_h323_asn1.c if (base) base 538 net/netfilter/nf_conntrack_h323_asn1.c *(unsigned int *)base = bmp; base 560 net/netfilter/nf_conntrack_h323_asn1.c if (!base || !(son->attr & DECODE)) { base 569 net/netfilter/nf_conntrack_h323_asn1.c if ((err = (Decoders[son->type]) (bs, son, base, base 576 net/netfilter/nf_conntrack_h323_asn1.c } else if ((err = (Decoders[son->type]) (bs, son, base, base 594 net/netfilter/nf_conntrack_h323_asn1.c if (base) base 595 net/netfilter/nf_conntrack_h323_asn1.c *(unsigned int *)base = bmp; base 625 net/netfilter/nf_conntrack_h323_asn1.c if (!base || !(son->attr & DECODE)) { base 633 net/netfilter/nf_conntrack_h323_asn1.c if ((err = (Decoders[son->type]) (bs, son, base, base 645 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 655 net/netfilter/nf_conntrack_h323_asn1.c base = (base && (f->attr & DECODE)) ? base + f->offset : NULL; base 688 net/netfilter/nf_conntrack_h323_asn1.c if (base) { base 690 net/netfilter/nf_conntrack_h323_asn1.c *(unsigned int *)base = effective_count; base 691 net/netfilter/nf_conntrack_h323_asn1.c base += sizeof(unsigned int); base 696 net/netfilter/nf_conntrack_h323_asn1.c if (base) base 697 net/netfilter/nf_conntrack_h323_asn1.c base -= son->offset; base 706 net/netfilter/nf_conntrack_h323_asn1.c if (!base || !(son->attr & DECODE)) { base 717 net/netfilter/nf_conntrack_h323_asn1.c base : NULL, base 728 net/netfilter/nf_conntrack_h323_asn1.c base : NULL, base 733 net/netfilter/nf_conntrack_h323_asn1.c if (base) base 734 net/netfilter/nf_conntrack_h323_asn1.c base += son->offset; base 741 net/netfilter/nf_conntrack_h323_asn1.c char *base, int level) base 751 net/netfilter/nf_conntrack_h323_asn1.c base = (base && (f->attr & DECODE)) ? base + f->offset : NULL; base 771 net/netfilter/nf_conntrack_h323_asn1.c if (base) base 772 net/netfilter/nf_conntrack_h323_asn1.c *(unsigned int *)base = type; base 800 net/netfilter/nf_conntrack_h323_asn1.c if (!base || !(son->attr & DECODE)) { base 808 net/netfilter/nf_conntrack_h323_asn1.c if ((err = (Decoders[son->type]) (bs, son, base, level + 1)) < base 814 net/netfilter/nf_conntrack_h323_asn1.c } else if ((err = (Decoders[son->type]) (bs, son, base, level + 1)) < base 70 net/netfilter/nf_tables_core.c if (priv->base == NFT_PAYLOAD_NETWORK_HEADER) base 83 net/netfilter/nft_payload.c switch (priv->base) { base 133 net/netfilter/nft_payload.c priv->base = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_BASE])); base 147 net/netfilter/nft_payload.c nla_put_be32(skb, NFTA_PAYLOAD_BASE, htonl(priv->base)) || base 360 net/netfilter/nft_payload.c switch (priv->base) { base 502 net/netfilter/nft_payload.c switch (priv->base) { base 524 net/netfilter/nft_payload.c (priv->base != NFT_PAYLOAD_TRANSPORT_HEADER || base 553 net/netfilter/nft_payload.c priv->base = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_BASE])); base 590 net/netfilter/nft_payload.c nla_put_be32(skb, NFTA_PAYLOAD_BASE, htonl(priv->base)) || base 616 net/netfilter/nft_payload.c enum nft_payload_bases base; base 624 net/netfilter/nft_payload.c base = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_BASE])); base 625 net/netfilter/nft_payload.c switch (base) { base 647 net/netfilter/nft_payload.c base != NFT_PAYLOAD_LL_HEADER) base 801 net/netfilter/x_tables.c int xt_compat_check_entry_offsets(const void *base, const char *elems, base 805 net/netfilter/x_tables.c long size_of_base_struct = elems - (const char *)base; base 807 net/netfilter/x_tables.c const char *e = base; base 844 net/netfilter/x_tables.c return xt_check_entry_match(elems, base + target_offset, base 893 net/netfilter/x_tables.c int xt_check_entry_offsets(const void *base, base 898 net/netfilter/x_tables.c long size_of_base_struct = elems - (const char *)base; base 900 net/netfilter/x_tables.c const char *e = base; base 932 net/netfilter/x_tables.c return xt_check_entry_match(elems, base + target_offset, base 600 net/openvswitch/actions.c flags = OVS_MASKED(flags, key.base.flags, mask.base.flags); base 601 net/openvswitch/actions.c flow_key->nsh.base.flags = flags; base 603 net/openvswitch/actions.c ttl = OVS_MASKED(ttl, key.base.ttl, mask.base.ttl); base 604 net/openvswitch/actions.c flow_key->nsh.base.ttl = ttl; base 606 net/openvswitch/actions.c nh->path_hdr = OVS_MASKED(nh->path_hdr, key.base.path_hdr, base 607 net/openvswitch/actions.c mask.base.path_hdr); base 608 net/openvswitch/actions.c flow_key->nsh.base.path_hdr = nh->path_hdr; base 502 net/openvswitch/flow.c key->nsh.base.flags = nsh_get_flags(nh); base 503 net/openvswitch/flow.c key->nsh.base.ttl = nsh_get_ttl(nh); base 504 net/openvswitch/flow.c key->nsh.base.mdtype = nh->mdtype; base 505 net/openvswitch/flow.c key->nsh.base.np = nh->np; base 506 net/openvswitch/flow.c key->nsh.base.path_hdr = nh->path_hdr; base 507 net/openvswitch/flow.c switch (key->nsh.base.mdtype) { base 57 net/openvswitch/flow.h struct ovs_nsh_key_base base; base 1299 net/openvswitch/flow_netlink.c const struct ovs_nsh_key_base *base = nla_data(a); base 1301 net/openvswitch/flow_netlink.c flags = base->flags; base 1302 net/openvswitch/flow_netlink.c ttl = base->ttl; base 1303 net/openvswitch/flow_netlink.c nh->np = base->np; base 1304 net/openvswitch/flow_netlink.c nh->mdtype = base->mdtype; base 1305 net/openvswitch/flow_netlink.c nh->path_hdr = base->path_hdr; base 1347 net/openvswitch/flow_netlink.c const struct ovs_nsh_key_base *base = nla_data(a); base 1348 net/openvswitch/flow_netlink.c const struct ovs_nsh_key_base *base_mask = base + 1; base 1350 net/openvswitch/flow_netlink.c nsh->base = *base; base 1351 net/openvswitch/flow_netlink.c nsh_mask->base = *base_mask; base 1413 net/openvswitch/flow_netlink.c const struct ovs_nsh_key_base *base = nla_data(a); base 1416 net/openvswitch/flow_netlink.c mdtype = base->mdtype; base 1417 net/openvswitch/flow_netlink.c SW_FLOW_KEY_PUT(match, nsh.base.flags, base 1418 net/openvswitch/flow_netlink.c base->flags, is_mask); base 1419 net/openvswitch/flow_netlink.c SW_FLOW_KEY_PUT(match, nsh.base.ttl, base 1420 net/openvswitch/flow_netlink.c base->ttl, is_mask); base 1421 net/openvswitch/flow_netlink.c SW_FLOW_KEY_PUT(match, nsh.base.mdtype, base 1422 net/openvswitch/flow_netlink.c base->mdtype, is_mask); base 1423 net/openvswitch/flow_netlink.c SW_FLOW_KEY_PUT(match, nsh.base.np, base 1424 net/openvswitch/flow_netlink.c base->np, is_mask); base 1425 net/openvswitch/flow_netlink.c SW_FLOW_KEY_PUT(match, nsh.base.path_hdr, base 1426 net/openvswitch/flow_netlink.c base->path_hdr, is_mask); base 1951 net/openvswitch/flow_netlink.c if (nla_put(skb, OVS_NSH_KEY_ATTR_BASE, sizeof(nsh->base), &nsh->base)) base 1954 net/openvswitch/flow_netlink.c if (is_mask || nsh->base.mdtype == NSH_M_TYPE1) { base 3160 net/openvswitch/flow_netlink.c inner_proto = tun_p_to_eth_p(key->nsh.base.np); base 3163 net/openvswitch/flow_netlink.c if (key->nsh.base.np == TUN_P_ETHERNET) base 540 net/packet/af_packet.c if (ecmd.base.speed < SPEED_1000 || base 541 net/packet/af_packet.c ecmd.base.speed == SPEED_UNKNOWN) { base 545 net/packet/af_packet.c div = ecmd.base.speed / 1000; base 812 net/rxrpc/input.c rxrpc_seq_t base = READ_ONCE(call->ackr_first_seq); base 814 net/rxrpc/input.c if (after(first_pkt, base)) base 817 net/rxrpc/input.c if (before(first_pkt, base)) base 824 net/rxrpc/input.c if (after_eq(prev_pkt, base + call->tx_winsize)) base 303 net/rxrpc/peer_event.c time64_t base, base 325 net/rxrpc/peer_event.c slot = keepalive_at - base; base 329 net/rxrpc/peer_event.c if (keepalive_at <= base || base 330 net/rxrpc/peer_event.c keepalive_at > base + RXRPC_KEEPALIVE_TIME) { base 360 net/rxrpc/peer_event.c time64_t base, now, delay; base 365 net/rxrpc/peer_event.c base = rxnet->peer_keepalive_base; base 367 net/rxrpc/peer_event.c _enter("%lld,%u", base - now, cursor); base 383 net/rxrpc/peer_event.c while (base <= now && (s8)(cursor - stop) < 0) { base 386 net/rxrpc/peer_event.c base++; base 390 net/rxrpc/peer_event.c base = now; base 393 net/rxrpc/peer_event.c rxnet->peer_keepalive_base = base; base 395 net/rxrpc/peer_event.c rxrpc_peer_keepalive_dispatch(rxnet, &collector, base, cursor); base 404 net/rxrpc/peer_event.c base++; base 408 net/rxrpc/peer_event.c delay = base - now; base 119 net/rxrpc/rxkad.c req = skcipher_request_alloc(&conn->cipher->base, GFP_NOFS); base 152 net/rxrpc/rxkad.c struct crypto_skcipher *tfm = &call->conn->cipher->base; base 788 net/rxrpc/rxkad.c req = skcipher_request_alloc(&conn->cipher->base, GFP_NOFS); base 1267 net/rxrpc/rxkad.c req = skcipher_request_alloc(&tfm->base, GFP_KERNEL); base 146 net/sched/cls_basic.c struct basic_filter *f, unsigned long base, base 163 net/sched/cls_basic.c tcf_bind_filter(tp, &f->res, base); base 171 net/sched/cls_basic.c struct tcf_proto *tp, unsigned long base, u32 handle, base 219 net/sched/cls_basic.c err = basic_set_parms(net, tp, fnew, base, tb, tca[TCA_RATE], ovr, base 267 net/sched/cls_basic.c unsigned long base) base 273 net/sched/cls_basic.c __tcf_bind_filter(q, &f->res, base); base 409 net/sched/cls_bpf.c struct cls_bpf_prog *prog, unsigned long base, base 452 net/sched/cls_bpf.c tcf_bind_filter(tp, &prog->res, base); base 459 net/sched/cls_bpf.c struct tcf_proto *tp, unsigned long base, base 506 net/sched/cls_bpf.c ret = cls_bpf_set_parms(net, tp, prog, base, tb, tca[TCA_RATE], ovr, base 635 net/sched/cls_bpf.c void *q, unsigned long base) base 641 net/sched/cls_bpf.c __tcf_bind_filter(q, &prog->res, base); base 77 net/sched/cls_cgroup.c struct tcf_proto *tp, unsigned long base, base 388 net/sched/cls_flow.c struct tcf_proto *tp, unsigned long base, base 1470 net/sched/cls_flower.c unsigned long base, struct nlattr **tb, base 1486 net/sched/cls_flower.c tcf_bind_filter(tp, &f->res, base); base 1529 net/sched/cls_flower.c struct tcf_proto *tp, unsigned long base, base 1590 net/sched/cls_flower.c err = fl_set_parms(net, tp, fnew, mask, base, tb, tca[TCA_RATE], ovr, base 2517 net/sched/cls_flower.c unsigned long base) base 2523 net/sched/cls_flower.c __tcf_bind_filter(q, &f->res, base); base 201 net/sched/cls_fw.c struct nlattr **tca, unsigned long base, bool ovr, base 215 net/sched/cls_fw.c tcf_bind_filter(tp, &f->res, base); base 238 net/sched/cls_fw.c struct tcf_proto *tp, unsigned long base, base 280 net/sched/cls_fw.c err = fw_set_parms(net, tp, fnew, tb, tca, base, ovr, extack); base 329 net/sched/cls_fw.c err = fw_set_parms(net, tp, f, tb, tca, base, ovr, extack); base 423 net/sched/cls_fw.c unsigned long base) base 429 net/sched/cls_fw.c __tcf_bind_filter(q, &f->res, base); base 165 net/sched/cls_matchall.c unsigned long base, struct nlattr **tb, base 178 net/sched/cls_matchall.c tcf_bind_filter(tp, &head->res, base); base 184 net/sched/cls_matchall.c struct tcf_proto *tp, unsigned long base, base 230 net/sched/cls_matchall.c err = mall_set_parms(net, tp, new, base, tb, tca[TCA_RATE], ovr, base 398 net/sched/cls_matchall.c unsigned long base) base 404 net/sched/cls_matchall.c __tcf_bind_filter(q, &head->res, base); base 382 net/sched/cls_route.c unsigned long base, struct route4_filter *f, base 459 net/sched/cls_route.c tcf_bind_filter(tp, &f->res, base); base 466 net/sched/cls_route.c struct tcf_proto *tp, unsigned long base, u32 handle, base 512 net/sched/cls_route.c err = route4_set_parms(net, tp, base, f, handle, head, tb, base 645 net/sched/cls_route.c unsigned long base) base 651 net/sched/cls_route.c __tcf_bind_filter(q, &f->res, base); base 472 net/sched/cls_rsvp.h struct tcf_proto *tp, unsigned long base, base 530 net/sched/cls_rsvp.h tcf_bind_filter(tp, &n->res, base); base 604 net/sched/cls_rsvp.h tcf_bind_filter(tp, &f->res, base); base 740 net/sched/cls_rsvp.h unsigned long base) base 746 net/sched/cls_rsvp.h __tcf_bind_filter(q, &f->res, base); base 327 net/sched/cls_tcindex.c tcindex_set_parms(struct net *net, struct tcf_proto *tp, unsigned long base, base 471 net/sched/cls_tcindex.c tcf_bind_filter(tp, &cr, base); base 524 net/sched/cls_tcindex.c struct tcf_proto *tp, unsigned long base, u32 handle, base 546 net/sched/cls_tcindex.c return tcindex_set_parms(net, tp, base, handle, p, r, tb, base 693 net/sched/cls_tcindex.c void *q, unsigned long base) base 699 net/sched/cls_tcindex.c __tcf_bind_filter(q, &r->res, base); base 710 net/sched/cls_u32.c unsigned long base, base 752 net/sched/cls_u32.c tcf_bind_filter(tp, &n->res, base); base 844 net/sched/cls_u32.c struct tcf_proto *tp, unsigned long base, u32 handle, base 902 net/sched/cls_u32.c err = u32_set_parms(net, tp, base, new, tb, base 1068 net/sched/cls_u32.c err = u32_set_parms(net, tp, base, n, tb, tca[TCA_RATE], ovr, base 1259 net/sched/cls_u32.c unsigned long base) base 1265 net/sched/cls_u32.c __tcf_bind_filter(q, &n->res, base); base 1894 net/sched/sch_api.c unsigned long base; base 1907 net/sched/sch_api.c tp->ops->bind_class(n, a->classid, a->cl, q, a->base); base 1942 net/sched/sch_api.c arg.base = cl; base 319 net/sched/sch_cbs.c if (ecmd.base.speed && ecmd.base.speed != SPEED_UNKNOWN) base 320 net/sched/sch_cbs.c speed = ecmd.base.speed; base 328 net/sched/sch_cbs.c ecmd.base.speed); base 974 net/sched/sch_taprio.c ktime_t now, base, cycle; base 977 net/sched/sch_taprio.c base = sched_base_time(sched); base 980 net/sched/sch_taprio.c if (ktime_after(base, now)) { base 981 net/sched/sch_taprio.c *start = base; base 998 net/sched/sch_taprio.c n = div64_s64(ktime_sub_ns(now, base), cycle); base 999 net/sched/sch_taprio.c *start = ktime_add_ns(base, (n + 1) * cycle); base 1004 net/sched/sch_taprio.c struct sched_gate_list *sched, ktime_t base) base 1015 net/sched/sch_taprio.c sched->cycle_close_time = ktime_add_ns(base, cycle); base 1017 net/sched/sch_taprio.c first->close_time = ktime_add_ns(base, first->interval); base 1056 net/sched/sch_taprio.c if (ecmd.base.speed && ecmd.base.speed != SPEED_UNKNOWN) base 1057 net/sched/sch_taprio.c speed = ecmd.base.speed; base 1065 net/sched/sch_taprio.c ecmd.base.speed); base 1098 net/sched/sch_taprio.c struct sched_gate_list *sched, ktime_t base) base 1104 net/sched/sch_taprio.c entry->next_txtime = ktime_add_ns(base, interval); base 66 net/sctp/associola.c asoc->base.sk = (struct sock *)sk; base 67 net/sctp/associola.c asoc->base.net = sock_net(sk); base 70 net/sctp/associola.c sock_hold(asoc->base.sk); base 73 net/sctp/associola.c asoc->base.type = SCTP_EP_TYPE_ASSOCIATION; base 76 net/sctp/associola.c refcount_set(&asoc->base.refcnt, 1); base 79 net/sctp/associola.c sctp_bind_addr_init(&asoc->base.bind_addr, ep->base.bind_addr.port); base 173 net/sctp/associola.c asoc->c.my_port = ep->base.bind_addr.port; base 218 net/sctp/associola.c sctp_inq_init(&asoc->base.inqueue); base 219 net/sctp/associola.c sctp_inq_set_th_handler(&asoc->base.inqueue, sctp_assoc_bh_rcv); base 239 net/sctp/associola.c if (asoc->base.sk->sk_family == PF_INET6) base 277 net/sctp/associola.c sock_put(asoc->base.sk); base 313 net/sctp/associola.c struct sock *sk = asoc->base.sk; base 334 net/sctp/associola.c asoc->base.dead = true; base 343 net/sctp/associola.c sctp_inq_free(&asoc->base.inqueue); base 354 net/sctp/associola.c sctp_bind_addr_free(&asoc->base.bind_addr); base 399 net/sctp/associola.c if (unlikely(!asoc->base.dead)) { base 405 net/sctp/associola.c sock_put(asoc->base.sk); base 582 net/sctp/associola.c struct net *net = sock_net(asoc->base.sk); base 587 net/sctp/associola.c sp = sctp_sk(asoc->base.sk); base 669 net/sctp/associola.c sctp_packet_init(&peer->packet, peer, asoc->base.bind_addr.port, base 858 net/sctp/associola.c refcount_inc(&asoc->base.refcnt); base 866 net/sctp/associola.c if (refcount_dec_and_test(&asoc->base.refcnt)) base 980 net/sctp/associola.c base.inqueue.immediate); base 981 net/sctp/associola.c struct net *net = sock_net(asoc->base.sk); base 993 net/sctp/associola.c inqueue = &asoc->base.inqueue; base 1055 net/sctp/associola.c if (asoc->base.dead) base 1072 net/sctp/associola.c struct sock *oldsk = assoc->base.sk; base 1085 net/sctp/associola.c sock_put(assoc->base.sk); base 1092 net/sctp/associola.c assoc->base.sk = newsk; base 1093 net/sctp/associola.c sock_hold(assoc->base.sk); base 1398 net/sctp/associola.c int frag = sctp_mtu_payload(sctp_sk(asoc->base.sk), asoc->pathmtu, base 1449 net/sctp/associola.c struct net *net = sock_net(asoc->base.sk); base 1457 net/sctp/associola.c (asoc->base.sk->sk_rcvbuf >> net->sctp.rwnd_upd_shift), base 1540 net/sctp/associola.c rx_count = atomic_read(&asoc->base.sk->sk_rmem_alloc); base 1547 net/sctp/associola.c if (rx_count >= asoc->base.sk->sk_rcvbuf) base 1577 net/sctp/associola.c flags = (PF_INET6 == asoc->base.sk->sk_family) ? SCTP_ADDR6_ALLOWED : 0; base 1583 net/sctp/associola.c return sctp_bind_addr_copy(sock_net(asoc->base.sk), base 1584 net/sctp/associola.c &asoc->base.bind_addr, base 1585 net/sctp/associola.c &asoc->ep->base.bind_addr, base 1598 net/sctp/associola.c return sctp_raw_to_bind_addrs(&asoc->base.bind_addr, raw, var_size3, base 1599 net/sctp/associola.c asoc->ep->base.bind_addr.port, gfp); base 1608 net/sctp/associola.c if ((asoc->base.bind_addr.port == ntohs(laddr->v4.sin_port)) && base 1609 net/sctp/associola.c sctp_bind_addr_match(&asoc->base.bind_addr, laddr, base 1610 net/sctp/associola.c sctp_sk(asoc->base.sk))) base 328 net/sctp/bind_addr.c struct sctp_bind_addr *bp2 = &sp2->ep->base.bind_addr; base 329 net/sctp/bind_addr.c struct sctp_bind_addr *bp = &sp->ep->base.bind_addr; base 541 net/sctp/bind_addr.c bp = &sctp_sk(sk)->ep->base.bind_addr; base 178 net/sctp/chunk.c max_data = sctp_min_frag_point(sctp_sk(asoc->base.sk), base 230 net/sctp/chunk.c SCTP_INC_STATS(sock_net(asoc->base.sk), base 34 net/sctp/diag.c laddr = list_entry(asoc->base.bind_addr.address_list.next, base 40 net/sctp/diag.c r->id.idiag_sport = htons(asoc->base.bind_addr.port); base 200 net/sctp/diag.c addr_list = asoc ? &asoc->base.bind_addr.address_list base 201 net/sctp/diag.c : &ep->base.bind_addr.address_list; base 235 net/sctp/diag.c list_for_each_entry_rcu(laddr, &asoc->base.bind_addr.address_list, base 251 net/sctp/diag.c struct sock *sk = tsp->asoc->base.sk; base 270 net/sctp/diag.c if (sk != assoc->base.sk) { base 272 net/sctp/diag.c sk = assoc->base.sk; base 299 net/sctp/diag.c struct sock *sk = ep->base.sk; base 311 net/sctp/diag.c if (r->id.idiag_sport != htons(assoc->base.bind_addr.port) && base 353 net/sctp/diag.c struct sock *sk = ep->base.sk; base 371 net/sctp/diag.c struct sock *sk = ep->base.sk; base 65 net/sctp/endpointola.c ep->base.type = SCTP_EP_TYPE_SOCKET; base 68 net/sctp/endpointola.c refcount_set(&ep->base.refcnt, 1); base 69 net/sctp/endpointola.c ep->base.dead = false; base 72 net/sctp/endpointola.c sctp_inq_init(&ep->base.inqueue); base 75 net/sctp/endpointola.c sctp_inq_set_th_handler(&ep->base.inqueue, sctp_endpoint_bh_rcv); base 78 net/sctp/endpointola.c sctp_bind_addr_init(&ep->base.bind_addr, 0); base 112 net/sctp/endpointola.c ep->base.sk = sk; base 113 net/sctp/endpointola.c ep->base.net = sock_net(sk); base 114 net/sctp/endpointola.c sock_hold(ep->base.sk); base 154 net/sctp/endpointola.c struct sock *sk = ep->base.sk; base 176 net/sctp/endpointola.c ep->base.dead = true; base 178 net/sctp/endpointola.c inet_sk_set_state(ep->base.sk, SCTP_SS_CLOSED); base 191 net/sctp/endpointola.c if (unlikely(!ep->base.dead)) { base 206 net/sctp/endpointola.c sctp_inq_free(&ep->base.inqueue); base 207 net/sctp/endpointola.c sctp_bind_addr_free(&ep->base.bind_addr); base 211 net/sctp/endpointola.c sk = ep->base.sk; base 227 net/sctp/endpointola.c refcount_inc(&ep->base.refcnt); base 235 net/sctp/endpointola.c if (refcount_dec_and_test(&ep->base.refcnt)) base 246 net/sctp/endpointola.c if ((htons(ep->base.bind_addr.port) == laddr->v4.sin_port) && base 247 net/sctp/endpointola.c net_eq(sock_net(ep->base.sk), net)) { base 248 net/sctp/endpointola.c if (sctp_bind_addr_match(&ep->base.bind_addr, laddr, base 249 net/sctp/endpointola.c sctp_sk(ep->base.sk))) base 273 net/sctp/endpointola.c if (!ep->base.bind_addr.port) base 296 net/sctp/endpointola.c struct net *net = sock_net(ep->base.sk); base 298 net/sctp/endpointola.c bp = &ep->base.bind_addr; base 317 net/sctp/endpointola.c base.inqueue.immediate); base 329 net/sctp/endpointola.c if (ep->base.dead) base 333 net/sctp/endpointola.c inqueue = &ep->base.inqueue; base 334 net/sctp/endpointola.c sk = ep->base.sk; base 387 net/sctp/endpointola.c SCTP_INC_STATS(sock_net(ep->base.sk), SCTP_MIB_INCTRLCHUNKS); base 165 net/sctp/input.c rcvr = asoc ? &asoc->base : &ep->base; base 184 net/sctp/input.c rcvr = &ep->base; base 503 net/sctp/input.c sk = asoc->base.sk; base 720 net/sctp/input.c struct sock *sk = ep->base.sk; base 725 net/sctp/input.c epb = &ep->base; base 735 net/sctp/input.c list_for_each(list, &ep->base.bind_addr.address_list) base 786 net/sctp/input.c struct sock *sk = ep->base.sk; base 790 net/sctp/input.c epb = &ep->base; base 852 net/sctp/input.c sk = ep->base.sk; base 885 net/sctp/input.c if (!net_eq(t->asoc->base.net, x->net)) base 887 net/sctp/input.c if (x->lport != htons(t->asoc->base.bind_addr.port)) base 900 net/sctp/input.c return sctp_hashfn(t->asoc->base.net, base 901 net/sctp/input.c htons(t->asoc->base.bind_addr.port), base 940 net/sctp/input.c arg.net = sock_net(t->asoc->base.sk); base 942 net/sctp/input.c arg.lport = htons(t->asoc->base.bind_addr.port); base 993 net/sctp/input.c if (sctp_bind_addr_match(&t->asoc->base.bind_addr, base 994 net/sctp/input.c laddr, sctp_sk(t->asoc->base.sk))) base 1007 net/sctp/input.c struct net *net = sock_net(ep->base.sk); base 1013 net/sctp/input.c .lport = htons(ep->base.bind_addr.port), base 177 net/sctp/inqueue.c sock_rps_save_rxhash(chunk->asoc->base.sk, chunk->skb); base 249 net/sctp/ipv6.c fl6->flowi6_oif = asoc->base.sk->sk_bound_dev_if; base 265 net/sctp/ipv6.c fl6->fl6_sport = htons(asoc->base.bind_addr.port); base 286 net/sctp/ipv6.c bp = &asoc->base.bind_addr; base 834 net/sctp/ipv6.c *addrlen = sctp_v6_addr_to_user(sctp_sk(asoc->base.sk), addr); base 92 net/sctp/output.c sk = asoc->base.sk; base 285 net/sctp/output.c SCTP_INC_STATS(sock_net(asoc->base.sk), base 703 net/sctp/output.c if ((sctp_sk(asoc->base.sk)->nodelay || inflight == 0) && base 200 net/sctp/outqueue.c sctp_sched_set_sched(asoc, sctp_sk(asoc->base.sk)->default_ss); base 282 net/sctp/outqueue.c struct net *net = sock_net(q->asoc->base.sk); base 536 net/sctp/outqueue.c struct net *net = sock_net(q->asoc->base.sk); base 764 net/sctp/outqueue.c const __u16 sport = asoc->base.bind_addr.port; base 906 net/sctp/outqueue.c ctx->asoc->base.sk->sk_err = -error; base 995 net/sctp/outqueue.c ctx->asoc->base.sk->sk_err = -error; base 1148 net/sctp/outqueue.c ctx->q->asoc->base.sk->sk_err = -error; base 1887 net/sctp/outqueue.c SCTP_INC_STATS(sock_net(asoc->base.sk), SCTP_MIB_OUTCTRLCHUNKS); base 249 net/sctp/proc.c epb = &assoc->base; base 428 net/sctp/protocol.c fl4->flowi4_tos = RT_CONN_FLAGS_TOS(asoc->base.sk, tos); base 429 net/sctp/protocol.c fl4->flowi4_oif = asoc->base.sk->sk_bound_dev_if; base 430 net/sctp/protocol.c fl4->fl4_sport = htons(asoc->base.bind_addr.port); base 454 net/sctp/protocol.c bp = &asoc->base.bind_addr; base 494 net/sctp/protocol.c asoc->base.sk->sk_bound_dev_if, base 495 net/sctp/protocol.c RT_CONN_FLAGS_TOS(asoc->base.sk, tos), base 113 net/sctp/sm_make_chunk.c skb->sk = asoc ? asoc->base.sk : NULL; base 242 net/sctp/sm_make_chunk.c sp = sctp_sk(asoc->base.sk); base 400 net/sctp/sm_make_chunk.c addrs = sctp_bind_addrs_to_raw(&asoc->base.bind_addr, &addrs_len, gfp); base 419 net/sctp/sm_make_chunk.c sp = sctp_sk(asoc->base.sk); base 1252 net/sctp/sm_make_chunk.c sp = sctp_sk(asoc->base.sk); base 1408 net/sctp/sm_make_chunk.c sk = asoc ? asoc->base.sk : NULL; base 1593 net/sctp/sm_make_chunk.c asoc = sctp_association_new(ep, ep->base.sk, scope, gfp); base 1672 net/sctp/sm_make_chunk.c if (sctp_sk(ep->base.sk)->hmac) { base 1673 net/sctp/sm_make_chunk.c SHASH_DESC_ON_STACK(desc, sctp_sk(ep->base.sk)->hmac); base 1677 net/sctp/sm_make_chunk.c desc->tfm = sctp_sk(ep->base.sk)->hmac; base 1739 net/sctp/sm_make_chunk.c if (!sctp_sk(ep->base.sk)->hmac) base 1744 net/sctp/sm_make_chunk.c SHASH_DESC_ON_STACK(desc, sctp_sk(ep->base.sk)->hmac); base 1747 net/sctp/sm_make_chunk.c desc->tfm = sctp_sk(ep->base.sk)->hmac; base 1793 net/sctp/sm_make_chunk.c if (sock_flag(ep->base.sk, SOCK_TIMESTAMP)) base 1823 net/sctp/sm_make_chunk.c retval = sctp_association_new(ep, ep->base.sk, scope, gfp); base 1842 net/sctp/sm_make_chunk.c if (list_empty(&retval->base.bind_addr.address_list)) { base 1843 net/sctp/sm_make_chunk.c sctp_add_bind_addr(&retval->base.bind_addr, &chunk->dest, base 2314 net/sctp/sm_make_chunk.c struct net *net = sock_net(asoc->base.sk); base 2498 net/sctp/sm_make_chunk.c struct net *net = sock_net(asoc->base.sk); base 2515 net/sctp/sm_make_chunk.c if (PF_INET6 != asoc->base.sk->sk_family) base 2521 net/sctp/sm_make_chunk.c if (ipv6_only_sock(asoc->base.sk)) base 2575 net/sctp/sm_make_chunk.c if (PF_INET6 == asoc->base.sk->sk_family) base 3067 net/sctp/sm_make_chunk.c if (security_sctp_bind_connect(asoc->ep->base.sk, base 3139 net/sctp/sm_make_chunk.c if (security_sctp_bind_connect(asoc->ep->base.sk, base 3314 net/sctp/sm_make_chunk.c struct sctp_bind_addr *bp = &asoc->base.bind_addr; base 236 net/sctp/sm_sideeffect.c struct sock *sk = asoc->base.sk; base 273 net/sctp/sm_sideeffect.c struct sock *sk = asoc->base.sk; base 291 net/sctp/sm_sideeffect.c if (asoc->base.dead) base 366 net/sctp/sm_sideeffect.c struct sock *sk = asoc->base.sk; base 412 net/sctp/sm_sideeffect.c struct sock *sk = asoc->base.sk; base 429 net/sctp/sm_sideeffect.c if (asoc->base.dead) base 447 net/sctp/sm_sideeffect.c struct sock *sk = asoc->base.sk; base 519 net/sctp/sm_sideeffect.c struct net *net = sock_net(asoc->base.sk); base 796 net/sctp/sm_sideeffect.c struct net *net = sock_net(asoc->base.sk); base 832 net/sctp/sm_sideeffect.c struct net *net = sock_net(asoc->base.sk); base 855 net/sctp/sm_sideeffect.c struct sock *sk = asoc->base.sk; base 919 net/sctp/sm_sideeffect.c struct sock *sk = asoc->base.sk; base 1021 net/sctp/sm_sideeffect.c struct sock *sk = asoc->base.sk; base 1120 net/sctp/sm_sideeffect.c asoc, sctp_state_tbl[(asoc && sctp_id2assoc(ep->base.sk, \ base 1262 net/sctp/sm_sideeffect.c struct sctp_sock *sp = sctp_sk(ep->base.sk); base 361 net/sctp/sm_statefuns.c if (sctp_sstate(ep->base.sk, CLOSING)) base 720 net/sctp/sm_statefuns.c sk = ep->base.sk; base 927 net/sctp/sm_statefuns.c security_inet_conn_established(ep->base.sk, chunk->skb); base 1333 net/sctp/sm_statefuns.c struct net *net = sock_net(new_asoc->base.sk); base 1861 net/sctp/sm_statefuns.c (sctp_sstate(asoc->base.sk, CLOSING) || base 1862 net/sctp/sm_statefuns.c sock_flag(asoc->base.sk, SOCK_DEAD))) { base 2266 net/sctp/sm_statefuns.c sctp_bind_addr_state(&asoc->base.bind_addr, &chunk->dest)) base 2312 net/sctp/sm_statefuns.c sctp_bind_addr_state(&asoc->base.bind_addr, &chunk->dest)) base 2474 net/sctp/sm_statefuns.c bp = (struct sctp_bind_addr *) &asoc->base.bind_addr; base 2582 net/sctp/sm_statefuns.c sctp_bind_addr_state(&asoc->base.bind_addr, &chunk->dest)) base 3391 net/sctp/sm_statefuns.c abort->skb->sk = ep->base.sk; base 3655 net/sctp/sm_statefuns.c shut->skb->sk = ep->base.sk; base 4616 net/sctp/sm_statefuns.c abort->skb->sk = ep->base.sk; base 4841 net/sctp/sm_statefuns.c repl = sctp_make_init(asoc, &asoc->base.bind_addr, GFP_ATOMIC, 0); base 5767 net/sctp/sm_statefuns.c bp = (struct sctp_bind_addr *) &asoc->base.bind_addr; base 6203 net/sctp/sm_statefuns.c abort->skb->sk = ep->base.sk; base 6313 net/sctp/sm_statefuns.c err_chunk->skb->sk = ep->base.sk; base 6330 net/sctp/sm_statefuns.c struct sock *sk = asoc->base.sk; base 107 net/sctp/socket.c struct sock *sk = asoc->base.sk; base 125 net/sctp/socket.c struct sock *sk = asoc->base.sk; base 156 net/sctp/socket.c if ((clear && asoc->base.sk == c->skb->sk) || \ base 157 net/sctp/socket.c (!clear && asoc->base.sk != c->skb->sk)) \ base 256 net/sctp/socket.c if (asoc && (asoc->base.sk != sk || asoc->base.dead)) base 316 net/sctp/socket.c if (!sctp_sk(sk)->ep->base.bind_addr.port) base 366 net/sctp/socket.c struct sctp_bind_addr *bp = &ep->base.bind_addr; base 454 net/sctp/socket.c struct net *net = sock_net(asoc->base.sk); base 601 net/sctp/socket.c bp = &asoc->base.bind_addr; base 637 net/sctp/socket.c sctp_sk(asoc->base.sk)); base 667 net/sctp/socket.c struct sctp_bind_addr *bp = &ep->base.bind_addr; base 807 net/sctp/socket.c bp = &asoc->base.bind_addr; base 880 net/sctp/socket.c sctp_sk(asoc->base.sk)); base 901 net/sctp/socket.c addr->v4.sin_port = htons(sp->ep->base.bind_addr.port); base 1067 net/sctp/socket.c struct sock *sk = ep->base.sk; base 1075 net/sctp/socket.c if (!ep->base.bind_addr.port) { base 1079 net/sctp/socket.c if (ep->base.bind_addr.port < inet_prot_sock(net) && base 1136 net/sctp/socket.c err = sctp_verify_addr(ep->base.sk, daddr, addr_len); base 1758 net/sctp/socket.c struct sock *sk = asoc->base.sk; base 1797 net/sctp/socket.c struct sock *sk = asoc->base.sk; base 2446 net/sctp/socket.c struct net *net = sock_net(trans->asoc->base.sk); base 4420 net/sctp/socket.c if (sctp_sk(sk)->ep->base.bind_addr.port) base 5240 net/sctp/socket.c list_for_each(pos, &asoc->base.inqueue.in_chunk_list) base 5326 net/sctp/socket.c if (net_eq(sock_net(t->asoc->base.sk), net) && base 6289 net/sctp/socket.c bp = &sctp_sk(sk)->ep->base.bind_addr; base 6294 net/sctp/socket.c bp = &asoc->base.bind_addr; base 8273 net/sctp/socket.c if (sctp_bind_addr_conflict(&ep2->base.bind_addr, base 8384 net/sctp/socket.c if (!ep->base.bind_addr.port) { base 8909 net/sctp/socket.c struct sock *sk = asoc->base.sk; base 8951 net/sctp/socket.c if (asoc->base.dead) base 8985 net/sctp/socket.c struct sock *sk = asoc->base.sk; base 9042 net/sctp/socket.c struct sock *sk = asoc->base.sk; base 9057 net/sctp/socket.c if (asoc->base.dead) base 9077 net/sctp/socket.c if (sk != asoc->base.sk) base 9153 net/sctp/socket.c struct sock *sk = asoc->base.sk; base 9171 net/sctp/socket.c asoc->base.dead) base 9397 net/sctp/socket.c err = sctp_bind_addr_dup(&newsp->ep->base.bind_addr, base 9398 net/sctp/socket.c &oldsp->ep->base.bind_addr, GFP_KERNEL); base 225 net/sctp/stream.c struct net *net = sock_net(asoc->base.sk); base 244 net/sctp/stream_interleave.c retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), base 327 net/sctp/stream_interleave.c pd_point = sctp_sk(asoc->base.sk)->pd_point; base 329 net/sctp/stream_interleave.c retval = sctp_make_reassembled_event(sock_net(asoc->base.sk), base 340 net/sctp/stream_interleave.c retval = sctp_make_reassembled_event(sock_net(asoc->base.sk), base 474 net/sctp/stream_interleave.c struct sock *sk = ulpq->asoc->base.sk; base 633 net/sctp/stream_interleave.c retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), base 717 net/sctp/stream_interleave.c pd_point = sctp_sk(asoc->base.sk)->pd_point; base 719 net/sctp/stream_interleave.c retval = sctp_make_reassembled_event(sock_net(asoc->base.sk), base 730 net/sctp/stream_interleave.c retval = sctp_make_reassembled_event(sock_net(asoc->base.sk), base 817 net/sctp/stream_interleave.c retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), base 924 net/sctp/stream_interleave.c retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), base 973 net/sctp/stream_interleave.c if (skb_queue_empty(&asoc->base.sk->sk_receive_queue)) { base 986 net/sctp/stream_interleave.c sk_mem_reclaim(asoc->base.sk); base 992 net/sctp/stream_interleave.c struct sock *sk = ulpq->asoc->base.sk; base 1162 net/sctp/stream_interleave.c SCTP_INC_STATS(sock_net(asoc->base.sk), SCTP_MIB_OUTCTRLCHUNKS); base 249 net/sctp/transport.c struct sock *sk = t->asoc->base.sk; base 311 net/sctp/transport.c opt->pf->to_sk_saddr(&transport->saddr, asoc->base.sk); base 337 net/sctp/transport.c struct net *net = sock_net(tp->asoc->base.sk); base 89 net/sctp/ulpevent.c sctp_skb_set_owner_r(skb, asoc->base.sk); base 91 net/sctp/ulpevent.c chunk->head_skb->sk = asoc->base.sk; base 329 net/sctp/ulpevent.c sctp_get_pf_specific(asoc->base.sk->sk_family)->addr_to_user( base 330 net/sctp/ulpevent.c sctp_sk(asoc->base.sk), base 623 net/sctp/ulpevent.c struct sock *sk = asoc->base.sk; base 168 net/sctp/ulpqueue.c struct sctp_sock *sp = sctp_sk(ulpq->asoc->base.sk); base 179 net/sctp/ulpqueue.c return sctp_clear_pd(ulpq->asoc->base.sk, ulpq->asoc); base 184 net/sctp/ulpqueue.c struct sock *sk = ulpq->asoc->base.sk; base 482 net/sctp/ulpqueue.c if (!sctp_sk(asoc->base.sk)->frag_interleave && base 483 net/sctp/ulpqueue.c atomic_read(&sctp_sk(asoc->base.sk)->pd_mode)) base 487 net/sctp/ulpqueue.c pd_point = sctp_sk(asoc->base.sk)->pd_point; base 489 net/sctp/ulpqueue.c retval = sctp_make_reassembled_event(sock_net(asoc->base.sk), base 500 net/sctp/ulpqueue.c retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), base 566 net/sctp/ulpqueue.c retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), base 667 net/sctp/ulpqueue.c retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), base 1036 net/sctp/ulpqueue.c sp = sctp_sk(asoc->base.sk); base 1086 net/sctp/ulpqueue.c if (skb_queue_empty(&asoc->base.sk->sk_receive_queue)) { base 1092 net/sctp/ulpqueue.c if (sk_rmem_schedule(asoc->base.sk, chunk->skb, needed) && base 1105 net/sctp/ulpqueue.c sk_mem_reclaim(asoc->base.sk); base 1122 net/sctp/ulpqueue.c sk = ulpq->asoc->base.sk; base 223 net/smc/smc_cdc.c char *base; base 231 net/smc/smc_cdc.c base = (char *)conn->rmb_desc->cpu_addr + conn->rx_off; base 233 net/smc/smc_cdc.c conn->urg_rx_byte = *(base + conn->urg_curs.count - 1); base 235 net/smc/smc_cdc.c conn->urg_rx_byte = *(base + conn->rmb_desc->len - 1); base 656 net/sunrpc/auth_gss/gss_krb5_crypto.c xdr_extend_head(struct xdr_buf *buf, unsigned int base, unsigned int shiftlen) base 666 net/sunrpc/auth_gss/gss_krb5_crypto.c p = buf->head[0].iov_base + base; base 668 net/sunrpc/auth_gss/gss_krb5_crypto.c memmove(p + shiftlen, p, buf->head[0].iov_len - base); base 437 net/sunrpc/auth_gss/gss_krb5_wrap.c static void rotate_left(u32 base, struct xdr_buf *buf, unsigned int shift) base 441 net/sunrpc/auth_gss/gss_krb5_wrap.c xdr_buf_subsegment(buf, &subbuf, base, buf->len - base); base 838 net/sunrpc/auth_gss/svcauth_gss.c read_u32_from_xdr_buf(struct xdr_buf *buf, int base, u32 *obj) base 843 net/sunrpc/auth_gss/svcauth_gss.c status = read_bytes_from_xdr_buf(buf, base, &raw, sizeof(*obj)); base 1244 net/sunrpc/clnt.c unsigned int base, unsigned int len, base 1252 net/sunrpc/clnt.c xdr_inline_pages(&req->rq_rcv_buf, hdrsize << 2, pages, base, len); base 74 net/sunrpc/socklib.c xdr_partial_copy_from_skb(struct xdr_buf *xdr, unsigned int base, struct xdr_skb_reader *desc, xdr_skb_read_actor copy_actor) base 82 net/sunrpc/socklib.c if (base < len) { base 83 net/sunrpc/socklib.c len -= base; base 84 net/sunrpc/socklib.c ret = copy_actor(desc, (char *)xdr->head[0].iov_base + base, len); base 88 net/sunrpc/socklib.c base = 0; base 90 net/sunrpc/socklib.c base -= len; base 94 net/sunrpc/socklib.c if (unlikely(base >= pglen)) { base 95 net/sunrpc/socklib.c base -= pglen; base 98 net/sunrpc/socklib.c if (base || xdr->page_base) { base 99 net/sunrpc/socklib.c pglen -= base; base 100 net/sunrpc/socklib.c base += xdr->page_base; base 101 net/sunrpc/socklib.c ppage += base >> PAGE_SHIFT; base 102 net/sunrpc/socklib.c base &= ~PAGE_MASK; base 120 net/sunrpc/socklib.c if (base) { base 121 net/sunrpc/socklib.c len -= base; base 124 net/sunrpc/socklib.c ret = copy_actor(desc, kaddr + base, len); base 125 net/sunrpc/socklib.c base = 0; base 140 net/sunrpc/socklib.c if (base < len) base 141 net/sunrpc/socklib.c copied += copy_actor(desc, (char *)xdr->tail[0].iov_base + base, len - base); base 187 net/sunrpc/svcsock.c size_t base = xdr->page_base; base 207 net/sunrpc/svcsock.c size = PAGE_SIZE - base < pglen ? PAGE_SIZE - base : pglen; base 211 net/sunrpc/svcsock.c result = kernel_sendpage(sock, *ppage, base, size, flags); base 219 net/sunrpc/svcsock.c base = 0; base 323 net/sunrpc/svcsock.c unsigned int nr, size_t buflen, unsigned int base) base 334 net/sunrpc/svcsock.c if (base != 0) { base 335 net/sunrpc/svcsock.c iov_iter_advance(&msg.msg_iter, base); base 336 net/sunrpc/svcsock.c buflen -= base; base 1039 net/sunrpc/svcsock.c unsigned int want, base; base 1053 net/sunrpc/svcsock.c base = svc_tcp_restore_pages(svsk, rqstp); base 1058 net/sunrpc/svcsock.c pnum = copy_pages_to_kvecs(&vec[0], &rqstp->rq_pages[0], base + want); base 1064 net/sunrpc/svcsock.c len = svc_recvfrom(rqstp, vec, pnum, base + want, base); base 178 net/sunrpc/xdr.c struct page **pages, unsigned int base, unsigned int len) base 188 net/sunrpc/xdr.c xdr->page_base = base; base 757 net/sunrpc/xdr.c void xdr_write_pages(struct xdr_stream *xdr, struct page **pages, unsigned int base, base 763 net/sunrpc/xdr.c buf->page_base = base; base 796 net/sunrpc/xdr.c unsigned int base, unsigned int len) base 805 net/sunrpc/xdr.c if (base >= maxlen) base 807 net/sunrpc/xdr.c maxlen -= base; base 811 net/sunrpc/xdr.c base += xdr->buf->page_base; base 813 net/sunrpc/xdr.c pgnr = base >> PAGE_SHIFT; base 817 net/sunrpc/xdr.c pgoff = base & ~PAGE_MASK; base 1110 net/sunrpc/xdr.c unsigned int base, unsigned int len) base 1113 net/sunrpc/xdr.c if (base < buf->head[0].iov_len) { base 1114 net/sunrpc/xdr.c subbuf->head[0].iov_base = buf->head[0].iov_base + base; base 1116 net/sunrpc/xdr.c buf->head[0].iov_len - base); base 1118 net/sunrpc/xdr.c base = 0; base 1120 net/sunrpc/xdr.c base -= buf->head[0].iov_len; base 1124 net/sunrpc/xdr.c if (base < buf->page_len) { base 1125 net/sunrpc/xdr.c subbuf->page_len = min(buf->page_len - base, len); base 1126 net/sunrpc/xdr.c base += buf->page_base; base 1127 net/sunrpc/xdr.c subbuf->page_base = base & ~PAGE_MASK; base 1128 net/sunrpc/xdr.c subbuf->pages = &buf->pages[base >> PAGE_SHIFT]; base 1130 net/sunrpc/xdr.c base = 0; base 1132 net/sunrpc/xdr.c base -= buf->page_len; base 1136 net/sunrpc/xdr.c if (base < buf->tail[0].iov_len) { base 1137 net/sunrpc/xdr.c subbuf->tail[0].iov_base = buf->tail[0].iov_base + base; base 1139 net/sunrpc/xdr.c buf->tail[0].iov_len - base); base 1141 net/sunrpc/xdr.c base = 0; base 1143 net/sunrpc/xdr.c base -= buf->tail[0].iov_len; base 1147 net/sunrpc/xdr.c if (base || len) base 1212 net/sunrpc/xdr.c int read_bytes_from_xdr_buf(struct xdr_buf *buf, unsigned int base, void *obj, unsigned int len) base 1217 net/sunrpc/xdr.c status = xdr_buf_subsegment(buf, &subbuf, base, len); base 1243 net/sunrpc/xdr.c int write_bytes_to_xdr_buf(struct xdr_buf *buf, unsigned int base, void *obj, unsigned int len) base 1248 net/sunrpc/xdr.c status = xdr_buf_subsegment(buf, &subbuf, base, len); base 1257 net/sunrpc/xdr.c xdr_decode_word(struct xdr_buf *buf, unsigned int base, u32 *obj) base 1262 net/sunrpc/xdr.c status = read_bytes_from_xdr_buf(buf, base, &raw, sizeof(*obj)); base 1271 net/sunrpc/xdr.c xdr_encode_word(struct xdr_buf *buf, unsigned int base, u32 obj) base 1275 net/sunrpc/xdr.c return write_bytes_to_xdr_buf(buf, base, &raw, sizeof(obj)); base 1336 net/sunrpc/xdr.c xdr_xcode_array2(struct xdr_buf *buf, unsigned int base, base 1345 net/sunrpc/xdr.c if (xdr_encode_word(buf, base, desc->array_len) != 0) base 1348 net/sunrpc/xdr.c if (xdr_decode_word(buf, base, &desc->array_len) != 0 || base 1350 net/sunrpc/xdr.c (unsigned long) base + 4 + desc->array_len * base 1354 net/sunrpc/xdr.c base += 4; base 1362 net/sunrpc/xdr.c if (todo && base < buf->head->iov_len) { base 1363 net/sunrpc/xdr.c c = buf->head->iov_base + base; base 1365 net/sunrpc/xdr.c buf->head->iov_len - base); base 1391 net/sunrpc/xdr.c base = buf->head->iov_len; /* align to start of pages */ base 1395 net/sunrpc/xdr.c base -= buf->head->iov_len; base 1396 net/sunrpc/xdr.c if (todo && base < buf->page_len) { base 1399 net/sunrpc/xdr.c avail_here = min(todo, buf->page_len - base); base 1402 net/sunrpc/xdr.c base += buf->page_base; base 1403 net/sunrpc/xdr.c ppages = buf->pages + (base >> PAGE_SHIFT); base 1404 net/sunrpc/xdr.c base &= ~PAGE_MASK; base 1405 net/sunrpc/xdr.c avail_page = min_t(unsigned int, PAGE_SIZE - base, base 1407 net/sunrpc/xdr.c c = kmap(*ppages) + base; base 1491 net/sunrpc/xdr.c base = buf->page_len; /* align to start of tail */ base 1495 net/sunrpc/xdr.c base -= buf->page_len; base 1497 net/sunrpc/xdr.c c = buf->tail->iov_base + base; base 1530 net/sunrpc/xdr.c xdr_decode_array2(struct xdr_buf *buf, unsigned int base, base 1533 net/sunrpc/xdr.c if (base >= buf->len) base 1536 net/sunrpc/xdr.c return xdr_xcode_array2(buf, base, desc, 0); base 1541 net/sunrpc/xdr.c xdr_encode_array2(struct xdr_buf *buf, unsigned int base, base 1544 net/sunrpc/xdr.c if ((unsigned long) base + 4 + desc->array_len * desc->elem_size > base 1548 net/sunrpc/xdr.c return xdr_xcode_array2(buf, base, desc, 1); base 198 net/sunrpc/xprtrdma/rpc_rdma.c char *base; base 200 net/sunrpc/xprtrdma/rpc_rdma.c base = vec->iov_base; base 201 net/sunrpc/xprtrdma/rpc_rdma.c page_offset = offset_in_page(base); base 205 net/sunrpc/xprtrdma/rpc_rdma.c seg->mr_offset = base; base 208 net/sunrpc/xprtrdma/rpc_rdma.c base += seg->mr_len; base 1168 net/sunrpc/xprtrdma/rpc_rdma.c char *base; base 1183 net/sunrpc/xprtrdma/rpc_rdma.c base = (char *)xdr_inline_decode(xdr, 0); base 1186 net/sunrpc/xprtrdma/rpc_rdma.c rpcrdma_inline_fixup(rqst, base, rpclen, writelist & 3); base 513 net/sunrpc/xprtrdma/svc_rdma_sendto.c unsigned char *base, base 516 net/sunrpc/xprtrdma/svc_rdma_sendto.c return svc_rdma_dma_map_page(rdma, ctxt, virt_to_page(base), base 517 net/sunrpc/xprtrdma/svc_rdma_sendto.c offset_in_page(base), len); base 649 net/sunrpc/xprtrdma/svc_rdma_sendto.c unsigned char *base; base 669 net/sunrpc/xprtrdma/svc_rdma_sendto.c base = xdr->tail[0].iov_base; base 674 net/sunrpc/xprtrdma/svc_rdma_sendto.c base += xdr_pad; base 697 net/sunrpc/xprtrdma/svc_rdma_sendto.c base = xdr->tail[0].iov_base; base 702 net/sunrpc/xprtrdma/svc_rdma_sendto.c ret = svc_rdma_dma_map_buf(rdma, ctxt, base, len); base 765 net/sunrpc/xprtsock.c static int xs_send_pagedata(struct socket *sock, struct msghdr *msg, struct xdr_buf *xdr, size_t base) base 776 net/sunrpc/xprtsock.c return xs_sendmsg(sock, msg, base + xdr->page_base); base 787 net/sunrpc/xprtsock.c rpc_fraghdr marker, struct kvec *vec, size_t base) base 799 net/sunrpc/xprtsock.c return xs_sendmsg(sock, msg, base); base 813 net/sunrpc/xprtsock.c static int xs_sendpages(struct socket *sock, struct sockaddr *addr, int addrlen, struct xdr_buf *xdr, unsigned int base, rpc_fraghdr rm, int *sent_p) base 821 net/sunrpc/xprtsock.c unsigned int remainder = rmsize + xdr->len - base; base 829 net/sunrpc/xprtsock.c if (base < want) { base 830 net/sunrpc/xprtsock.c unsigned int len = want - base; base 836 net/sunrpc/xprtsock.c &xdr->head[0], base); base 838 net/sunrpc/xprtsock.c err = xs_send_kvec(sock, &msg, &xdr->head[0], base); base 842 net/sunrpc/xprtsock.c base = 0; base 844 net/sunrpc/xprtsock.c base -= want; base 846 net/sunrpc/xprtsock.c if (base < xdr->page_len) { base 847 net/sunrpc/xprtsock.c unsigned int len = xdr->page_len - base; base 851 net/sunrpc/xprtsock.c err = xs_send_pagedata(sock, &msg, xdr, base); base 855 net/sunrpc/xprtsock.c base = 0; base 857 net/sunrpc/xprtsock.c base -= xdr->page_len; base 859 net/sunrpc/xprtsock.c if (base >= xdr->tail[0].iov_len) base 862 net/sunrpc/xprtsock.c err = xs_send_kvec(sock, &msg, &xdr->tail[0], base); base 66 net/tls/tls_main.c struct proto *base); base 724 net/tls/tls_main.c struct proto *base) base 726 net/tls/tls_main.c prot[TLS_BASE][TLS_BASE] = *base; base 761 net/tls/tls_main.c prot[TLS_HW_RECORD][TLS_HW_RECORD] = *base; base 1135 net/wireless/util.c static const u32 base[4][10] = { base 1206 net/wireless/util.c bitrate = base[idx][rate->mcs]; base 55 samples/bpf/tracex3_kern.c u64 *value, l, base; base 76 samples/bpf/tracex3_kern.c base = 1ll << l; base 77 samples/bpf/tracex3_kern.c index = (l * 64 + (delta - base) * 64 / base) * 3 / 64; base 135 samples/vfio-mdev/mbochs.c struct vfio_region_info base; base 1023 samples/vfio-mdev/mbochs.c struct vfio_region_info *region_info = &ext->base; base 1054 samples/vfio-mdev/mbochs.c ext->base.argsz = sizeof(*ext); base 1055 samples/vfio-mdev/mbochs.c ext->base.offset = MBOCHS_EDID_OFFSET; base 1056 samples/vfio-mdev/mbochs.c ext->base.size = MBOCHS_EDID_SIZE; base 1057 samples/vfio-mdev/mbochs.c ext->base.flags = (VFIO_REGION_INFO_FLAG_READ | base 1060 samples/vfio-mdev/mbochs.c ext->base.cap_offset = offsetof(typeof(*ext), type); base 1215 samples/vfio-mdev/mbochs.c minsz = offsetofend(typeof(info), base.offset); base 1220 samples/vfio-mdev/mbochs.c outsz = info.base.argsz; base 164 samples/vfio-mdev/mdpy-fb.c info->apertures->ranges[0].base = info->fix.smem_start; base 566 scripts/dtc/flattree.c char *base, *limit, *ptr; base 569 scripts/dtc/flattree.c static void inbuf_init(struct inbuf *inb, void *base, void *limit) base 571 scripts/dtc/flattree.c inb->base = base; base 573 scripts/dtc/flattree.c inb->ptr = inb->base; base 590 scripts/dtc/flattree.c assert(((inb->ptr - inb->base) % sizeof(val)) == 0); base 599 scripts/dtc/flattree.c int off = inb->ptr - inb->base; base 601 scripts/dtc/flattree.c inb->ptr = inb->base + ALIGN(off, align); base 648 scripts/dtc/flattree.c p = inb->base + offset; base 650 scripts/dtc/flattree.c if (p >= inb->limit || p < inb->base) base 660 scripts/dtc/flattree.c return xstrdup(inb->base + offset); base 43 scripts/dtc/libfdt/fdt.c uint32_t base, uint32_t size) base 45 scripts/dtc/libfdt/fdt.c if (!check_off_(hdrsize, totalsize, base)) base 47 scripts/dtc/libfdt/fdt.c if ((base + size) < base) base 49 scripts/dtc/libfdt/fdt.c if (!check_off_(hdrsize, totalsize, base + size)) base 590 scripts/gcc-plugins/latent_entropy_plugin.c .base = &latent_entropy_decl, base 99 scripts/gcc-plugins/sancov_plugin.c .base = &sancov_fndecl, base 346 scripts/gcc-plugins/stackleak_plugin.c .base = &track_function_decl, base 101 scripts/kconfig/symbol.c static long long sym_get_range_val(struct symbol *sym, int base) base 106 scripts/kconfig/symbol.c base = 10; base 109 scripts/kconfig/symbol.c base = 16; base 114 scripts/kconfig/symbol.c return strtoll(sym->curr.val, NULL, base); base 120 scripts/kconfig/symbol.c int base; base 126 scripts/kconfig/symbol.c base = 10; base 129 scripts/kconfig/symbol.c base = 16; base 137 scripts/kconfig/symbol.c val = strtoll(sym->curr.val, NULL, base); base 138 scripts/kconfig/symbol.c val2 = sym_get_range_val(prop->expr->left.sym, base); base 140 scripts/kconfig/symbol.c val2 = sym_get_range_val(prop->expr->right.sym, base); base 308 scripts/mod/sumversion.c const char *base; base 314 scripts/mod/sumversion.c base = strrchr(objfile, '/'); base 315 scripts/mod/sumversion.c if (base) { base 316 scripts/mod/sumversion.c base++; base 317 scripts/mod/sumversion.c dirlen = base - objfile; base 318 scripts/mod/sumversion.c sprintf(cmd, "%.*s.%s.cmd", dirlen, objfile, base); base 1071 security/apparmor/apparmorfs.c seq_printf(seq, "%s\n", profile->base.name); base 1098 security/apparmor/apparmorfs.c seq_printf(seq, "%s\n", profile->base.name); base 1194 security/apparmor/apparmorfs.c seq_printf(seq, "%s\n", labels_ns(label)->base.name); base 1425 security/apparmor/apparmorfs.c list_for_each_entry(child, &profile->base.profiles, base.list) base 1603 security/apparmor/apparmorfs.c len = mangle_name(profile->base.name, NULL); base 1612 security/apparmor/apparmorfs.c mangle_name(profile->base.name, profile->dirname); base 1673 security/apparmor/apparmorfs.c list_for_each_entry(child, &profile->base.profiles, base.list) { base 1811 security/apparmor/apparmorfs.c list_for_each_entry(child, &ns->base.profiles, base.list) base 1814 security/apparmor/apparmorfs.c list_for_each_entry(sub, &ns->sub_ns, base.list) { base 1922 security/apparmor/apparmorfs.c name = ns->base.name; base 1937 security/apparmor/apparmorfs.c list_for_each_entry(child, &ns->base.profiles, base.list) { base 1944 security/apparmor/apparmorfs.c list_for_each_entry(sub, &ns->sub_ns, base.list) { base 1988 security/apparmor/apparmorfs.c next = list_first_entry(&ns->sub_ns, typeof(*ns), base.list); base 1997 security/apparmor/apparmorfs.c next = list_next_entry(ns, base.list); base 1998 security/apparmor/apparmorfs.c if (!list_entry_is_head(next, &parent->sub_ns, base.list)) { base 2024 security/apparmor/apparmorfs.c if (!list_empty(&ns->base.profiles)) base 2025 security/apparmor/apparmorfs.c return list_first_entry(&ns->base.profiles, base 2026 security/apparmor/apparmorfs.c struct aa_profile, base.list); base 2048 security/apparmor/apparmorfs.c if (!list_empty(&p->base.profiles)) base 2049 security/apparmor/apparmorfs.c return list_first_entry(&p->base.profiles, typeof(*p), base 2050 security/apparmor/apparmorfs.c base.list); base 2056 security/apparmor/apparmorfs.c p = list_next_entry(p, base.list); base 2057 security/apparmor/apparmorfs.c if (!list_entry_is_head(p, &parent->base.profiles, base.list)) base 2065 security/apparmor/apparmorfs.c p = list_next_entry(p, base.list); base 2066 security/apparmor/apparmorfs.c if (!list_entry_is_head(p, &ns->base.profiles, base.list)) base 85 security/apparmor/audit.c profile->ns->base.hname); base 88 security/apparmor/audit.c audit_log_untrustedstring(ab, profile->base.hname); base 106 security/apparmor/domain.c return aa_dfa_match(profile->file.dfa, state, tp->base.hname); base 113 security/apparmor/domain.c return aa_dfa_match(profile->file.dfa, state, tp->base.hname); base 394 security/apparmor/domain.c list_for_each_entry_rcu(profile, head, base.list) { base 467 security/apparmor/domain.c } else if (!strcmp(profile->base.name, name)) { base 579 security/apparmor/domain.c new = find_attach(bprm, ns, &profile->base.profiles, base 583 security/apparmor/domain.c new = find_attach(bprm, ns, &ns->base.profiles, base 605 security/apparmor/domain.c struct aa_label *base = new; base 607 security/apparmor/domain.c new = aa_label_parse(base, stack, GFP_ATOMIC, true, false); base 610 security/apparmor/domain.c aa_put_label(base); base 650 security/apparmor/domain.c &profile->ns->base.profiles, name, &info); base 1038 security/apparmor/domain.c name, hat ? hat->base.hname : NULL, base 1110 security/apparmor/domain.c if (!list_empty(&profile->base.profiles)) { base 326 security/apparmor/include/label.h struct aa_label *aa_label_strn_parse(struct aa_label *base, const char *str, base 329 security/apparmor/include/label.h struct aa_label *aa_label_parse(struct aa_label *base, const char *str, base 130 security/apparmor/include/policy.h struct aa_policy base; base 181 security/apparmor/include/policy.h const char *base, gfp_t gfp); base 188 security/apparmor/include/policy.h struct aa_profile *aa_fqlookupn_profile(struct aa_label *base, base 59 security/apparmor/include/policy_ns.h struct aa_policy base; base 153 security/apparmor/include/policy_ns.h static inline struct aa_ns *__aa_lookup_ns(struct aa_ns *base, base 156 security/apparmor/include/policy_ns.h return __aa_lookupn_ns(base, hname, strlen(hname)); base 113 security/apparmor/label.c AA_BUG(!a->base.hname); base 114 security/apparmor/label.c AA_BUG(!b->base.hname); base 123 security/apparmor/label.c return strcmp(a->base.hname, b->base.hname); base 143 security/apparmor/label.c AA_BUG(!a->base.hname); base 144 security/apparmor/label.c AA_BUG(!b->base.hname); base 146 security/apparmor/label.c if (a == b || a->base.hname == b->base.hname) base 152 security/apparmor/label.c return strcmp(a->base.hname, b->base.hname); base 384 security/apparmor/label.c on_list_rcu(&label->vec[0]->base.profiles)); base 386 security/apparmor/label.c on_list_rcu(&label->vec[0]->base.list)); base 1248 security/apparmor/label.c return aa_dfa_match(profile->policy.dfa, state, tp->base.hname); base 1255 security/apparmor/label.c return aa_dfa_match(profile->policy.dfa, state, tp->base.hname); base 1514 security/apparmor/label.c profile->base.hname, modestr); base 1515 security/apparmor/label.c return snprintf(str, size, "%s (%s)", profile->base.hname, base 1521 security/apparmor/label.c profile->base.hname); base 1522 security/apparmor/label.c return snprintf(str, size, "%s", profile->base.hname); base 1833 security/apparmor/label.c static struct aa_profile *fqlookupn_profile(struct aa_label *base, base 1840 security/apparmor/label.c return aa_fqlookupn_profile(base, str, n); base 1857 security/apparmor/label.c struct aa_label *aa_label_strn_parse(struct aa_label *base, const char *str, base 1862 security/apparmor/label.c struct aa_label *label, *currbase = base; base 1867 security/apparmor/label.c AA_BUG(!base); base 1871 security/apparmor/label.c if (str == NULL || (*str == '=' && base != &root_ns->unconfined->label)) base 1877 security/apparmor/label.c stack = base->size; base 1888 security/apparmor/label.c vec[i] = aa_get_profile(base->vec[i]); base 1892 security/apparmor/label.c vec[i] = fqlookupn_profile(base, currbase, str, split - str); base 1906 security/apparmor/label.c vec[i] = fqlookupn_profile(base, currbase, str, end - str); base 1938 security/apparmor/label.c struct aa_label *aa_label_parse(struct aa_label *base, const char *str, base 1941 security/apparmor/label.c return aa_label_strn_parse(base, str, strlen(str), gfp, create, base 2128 security/apparmor/label.c list_for_each_entry(child, &ns->sub_ns, base.list) { base 370 security/apparmor/match.c #define match_char(state, def, base, next, check, C) \ base 372 security/apparmor/match.c u32 b = (base)[(state)]; \ base 404 security/apparmor/match.c u32 *base = BASE_TABLE(dfa); base 417 security/apparmor/match.c match_char(state, def, base, next, check, base 422 security/apparmor/match.c match_char(state, def, base, next, check, (u8) *str++); base 444 security/apparmor/match.c u32 *base = BASE_TABLE(dfa); base 458 security/apparmor/match.c match_char(state, def, base, next, check, base 463 security/apparmor/match.c match_char(state, def, base, next, check, (u8) *str++); base 483 security/apparmor/match.c u32 *base = BASE_TABLE(dfa); base 491 security/apparmor/match.c match_char(state, def, base, next, check, equiv[(u8) c]); base 493 security/apparmor/match.c match_char(state, def, base, next, check, (u8) c); base 515 security/apparmor/match.c u32 *base = BASE_TABLE(dfa); base 530 security/apparmor/match.c pos = base_idx(base[state]) + equiv[(u8) *str++]; base 541 security/apparmor/match.c pos = base_idx(base[state]) + (u8) *str++; base 576 security/apparmor/match.c u32 *base = BASE_TABLE(dfa); base 592 security/apparmor/match.c pos = base_idx(base[state]) + equiv[(u8) *str++]; base 603 security/apparmor/match.c pos = base_idx(base[state]) + (u8) *str++; base 652 security/apparmor/match.c u32 *base = BASE_TABLE(dfa); base 675 security/apparmor/match.c pos = base_idx(base[state]) + equiv[(u8) *str++]; base 694 security/apparmor/match.c pos = base_idx(base[state]) + (u8) *str++; base 118 security/apparmor/policy.c list_add_rcu(&profile->base.list, list); base 144 security/apparmor/policy.c list_del_rcu(&profile->base.list); base 161 security/apparmor/policy.c __aa_profile_list_release(&profile->base.profiles); base 177 security/apparmor/policy.c list_for_each_entry_safe(profile, tmp, head, base.list) base 216 security/apparmor/policy.c aa_policy_destroy(&profile->base); base 267 security/apparmor/policy.c if (!aa_policy_init(&profile->base, NULL, hname, gfp)) base 281 security/apparmor/policy.c profile->label.hname = profile->base.hname; base 339 security/apparmor/policy.c profile = __find_child(&parent->base.profiles, name); base 367 security/apparmor/policy.c policy = &ns->base; base 374 security/apparmor/policy.c policy = &profile->base; base 379 security/apparmor/policy.c return &ns->base; base 380 security/apparmor/policy.c return &profile->base; base 395 security/apparmor/policy.c static struct aa_profile *__lookupn_profile(struct aa_policy *base, base 403 security/apparmor/policy.c profile = __strn_find_child(&base->profiles, hname, base 408 security/apparmor/policy.c base = &profile->base; base 414 security/apparmor/policy.c return __strn_find_child(&base->profiles, hname, n); base 418 security/apparmor/policy.c static struct aa_profile *__lookup_profile(struct aa_policy *base, base 421 security/apparmor/policy.c return __lookupn_profile(base, hname, strlen(hname)); base 439 security/apparmor/policy.c profile = __lookupn_profile(&ns->base, hname, n); base 456 security/apparmor/policy.c struct aa_profile *aa_fqlookupn_profile(struct aa_label *base, base 466 security/apparmor/policy.c ns = aa_lookupn_ns(labels_ns(base), ns_name, ns_len); base 470 security/apparmor/policy.c ns = aa_get_ns(labels_ns(base)); base 503 security/apparmor/policy.c const char *base, gfp_t gfp) base 511 security/apparmor/policy.c if (base) { base 512 security/apparmor/policy.c name = kmalloc(strlen(parent->base.hname) + 8 + strlen(base), base 515 security/apparmor/policy.c sprintf(name, "%s//null-%s", parent->base.hname, base); base 521 security/apparmor/policy.c name = kmalloc(strlen(parent->base.hname) + 2 + 7 + 8, gfp); base 524 security/apparmor/policy.c sprintf(name, "%s//null-%x", parent->base.hname, base 551 security/apparmor/policy.c p = __find_child(&parent->base.profiles, bname); base 556 security/apparmor/policy.c __add_profile(&parent->base.profiles, profile); base 707 security/apparmor/policy.c const char *base = basename(profile->base.hname); base 708 security/apparmor/policy.c long len = base - profile->base.hname; base 719 security/apparmor/policy.c if (strncmp(ent->new->base.hname, profile->base.hname, len) == base 720 security/apparmor/policy.c 0 && ent->new->base.hname[len] == 0) base 744 security/apparmor/policy.c if (!list_empty(&old->base.profiles)) { base 746 security/apparmor/policy.c list_splice_init_rcu(&old->base.profiles, &lh, synchronize_rcu); base 748 security/apparmor/policy.c list_for_each_entry_safe(child, tmp, &lh, base.list) { base 751 security/apparmor/policy.c list_del_init(&child->base.list); base 752 security/apparmor/policy.c p = __find_child(&new->base.profiles, child->base.name); base 764 security/apparmor/policy.c list_add_rcu(&child->base.list, &new->base.profiles); base 777 security/apparmor/policy.c if (list_empty(&new->base.list)) { base 779 security/apparmor/policy.c list_replace_rcu(&old->base.list, &new->base.list); base 800 security/apparmor/policy.c *p = aa_get_profile(__lookup_profile(&ns->base, hname)); base 814 security/apparmor/policy.c aa_put_str(new->base.hname); base 815 security/apparmor/policy.c aa_get_str(old->base.hname); base 816 security/apparmor/policy.c new->base.hname = old->base.hname; base 817 security/apparmor/policy.c new->base.name = old->base.name; base 932 security/apparmor/policy.c error = __lookup_replace(ns, ent->new->base.hname, base 953 security/apparmor/policy.c policy = __lookup_parent(ns, ent->new->base.hname); base 963 security/apparmor/policy.c } else if (policy != &ns->base) { base 1006 security/apparmor/policy.c audit_policy(label, op, ns_name, ent->new->base.hname, base 1019 security/apparmor/policy.c audit_policy(label, op, ns_name, ent->new->base.hname, NULL, base 1032 security/apparmor/policy.c lh = &parent->base.profiles; base 1034 security/apparmor/policy.c lh = &ns->base.profiles; base 1057 security/apparmor/policy.c audit_policy(label, op, ns_name, ent ? ent->new->base.hname : NULL, base 1068 security/apparmor/policy.c audit_policy(label, op, ns_name, tmp->new->base.hname, info, base 1133 security/apparmor/policy.c profile = aa_get_profile(__lookup_profile(&ns->base, name)); base 1139 security/apparmor/policy.c name = profile->base.hname; base 74 security/apparmor/policy_ns.c return view->base.hname + strlen(curr->base.hname) + 2; base 95 security/apparmor/policy_ns.c if (!aa_policy_init(&ns->base, prefix, name, GFP_KERNEL)) base 124 security/apparmor/policy_ns.c kzfree(ns->base.hname); base 142 security/apparmor/policy_ns.c aa_policy_destroy(&ns->base); base 252 security/apparmor/policy_ns.c ns = alloc_ns(parent->base.hname, name); base 260 security/apparmor/policy_ns.c ns->base.name); base 266 security/apparmor/policy_ns.c list_add_rcu(&ns->base.list, &parent->sub_ns); base 337 security/apparmor/policy_ns.c __aa_profile_list_release(&ns->base.profiles); base 363 security/apparmor/policy_ns.c list_del_rcu(&ns->base.list); base 378 security/apparmor/policy_ns.c list_for_each_entry_safe(ns, tmp, head, base.list) base 114 security/apparmor/policy_unpack.c aad(&sa)->name = new->base.hname; base 291 security/keys/dh.c dlen = dh_data_from_key(pcopy.base, &dh_inputs.g); base 5195 security/selinux/hooks.c struct sk_security_struct *sksec = ep->base.sk->sk_security; base 5212 security/selinux/hooks.c err = selinux_skb_peerlbl_sid(skb, ep->base.sk->sk_family, base 5236 security/selinux/hooks.c ad.u.net->sk = ep->base.sk; base 276 security/selinux/netlabel.c struct sk_security_struct *sksec = ep->base.sk->sk_security; base 280 security/selinux/netlabel.c if (ep->base.sk->sk_family != PF_INET && base 281 security/selinux/netlabel.c ep->base.sk->sk_family != PF_INET6) base 296 security/selinux/netlabel.c rc = netlbl_conn_setattr(ep->base.sk, (void *)&addr4, &secattr); base 300 security/selinux/netlabel.c rc = netlbl_conn_setattr(ep->base.sk, (void *)&addr6, &secattr); base 187 security/tomoyo/util.c int base = 10; base 193 security/tomoyo/util.c base = 16; base 196 security/tomoyo/util.c base = 8; base 200 security/tomoyo/util.c *result = simple_strtoul(cp, &ep, base); base 204 security/tomoyo/util.c switch (base) { base 91 sound/aoa/soundbus/i2sbus/control.c if (macio == NULL || macio->base == NULL) base 130 sound/aoa/soundbus/i2sbus/control.c if (macio == NULL || macio->base == NULL) base 173 sound/aoa/soundbus/i2sbus/control.c if (macio == NULL || macio->base == NULL) base 44 sound/arm/aaci.c v = readl(aaci->base + AACI_SLFR); base 46 sound/arm/aaci.c readl(aaci->base + AACI_SL2RX); base 48 sound/arm/aaci.c readl(aaci->base + AACI_SL1RX); base 50 sound/arm/aaci.c if (maincr != readl(aaci->base + AACI_MAINCR)) { base 51 sound/arm/aaci.c writel(maincr, aaci->base + AACI_MAINCR); base 52 sound/arm/aaci.c readl(aaci->base + AACI_MAINCR); base 84 sound/arm/aaci.c writel(val << 4, aaci->base + AACI_SL2TX); base 85 sound/arm/aaci.c writel(reg << 12, aaci->base + AACI_SL1TX); base 94 sound/arm/aaci.c v = readl(aaci->base + AACI_SLFR); base 123 sound/arm/aaci.c writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); base 132 sound/arm/aaci.c v = readl(aaci->base + AACI_SLFR); base 149 sound/arm/aaci.c v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); base 159 sound/arm/aaci.c v = readl(aaci->base + AACI_SL1RX) >> 12; base 161 sound/arm/aaci.c v = readl(aaci->base + AACI_SL2RX) >> 4; base 187 sound/arm/aaci.c val = readl(aacirun->base + AACI_SR); base 200 sound/arm/aaci.c writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR); base 205 sound/arm/aaci.c writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR); base 215 sound/arm/aaci.c writel(0, aacirun->base + AACI_IE); base 233 sound/arm/aaci.c val = readl(aacirun->base + AACI_SR); base 265 sound/arm/aaci.c writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR); base 275 sound/arm/aaci.c writel(0, aacirun->base + AACI_IE); base 293 sound/arm/aaci.c val = readl(aacirun->base + AACI_SR); base 330 sound/arm/aaci.c mask = readl(aaci->base + AACI_ALLINTS); base 574 sound/arm/aaci.c ie = readl(aacirun->base + AACI_IE); base 576 sound/arm/aaci.c writel(ie, aacirun->base + AACI_IE); base 579 sound/arm/aaci.c writel(aacirun->cr, aacirun->base + AACI_TXCR); base 589 sound/arm/aaci.c ie = readl(aacirun->base + AACI_IE); base 591 sound/arm/aaci.c writel(ie, aacirun->base + AACI_IE); base 592 sound/arm/aaci.c writel(aacirun->cr, aacirun->base + AACI_TXCR); base 652 sound/arm/aaci.c ie = readl(aacirun->base + AACI_IE); base 654 sound/arm/aaci.c writel(ie, aacirun->base+AACI_IE); base 658 sound/arm/aaci.c writel(aacirun->cr, aacirun->base + AACI_RXCR); base 673 sound/arm/aaci.c writel(aacirun->cr, aacirun->base + AACI_RXCR); base 675 sound/arm/aaci.c ie = readl(aacirun->base + AACI_IE); base 677 sound/arm/aaci.c writel(ie, aacirun->base + AACI_IE); base 841 sound/arm/aaci.c writel(0, aaci->base + AACI_RESET); base 843 sound/arm/aaci.c writel(RESET_NRST, aaci->base + AACI_RESET); base 889 sound/arm/aaci.c iounmap(aaci->base); base 957 sound/arm/aaci.c writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR); base 959 sound/arm/aaci.c for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++) base 962 sound/arm/aaci.c writel(0, aacirun->base + AACI_TXCR); base 969 sound/arm/aaci.c writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR); base 970 sound/arm/aaci.c readl(aaci->base + AACI_MAINCR); base 972 sound/arm/aaci.c writel(aaci->maincr, aaci->base + AACI_MAINCR); base 1000 sound/arm/aaci.c aaci->base = ioremap(dev->res.start, resource_size(&dev->res)); base 1001 sound/arm/aaci.c if (!aaci->base) { base 1010 sound/arm/aaci.c aaci->playback.base = aaci->base + AACI_CSCH1; base 1011 sound/arm/aaci.c aaci->playback.fifo = aaci->base + AACI_DR1; base 1017 sound/arm/aaci.c aaci->capture.base = aaci->base + AACI_CSCH1; base 1018 sound/arm/aaci.c aaci->capture.fifo = aaci->base + AACI_DR1; base 1021 sound/arm/aaci.c void __iomem *base = aaci->base + i * 0x14; base 1023 sound/arm/aaci.c writel(0, base + AACI_IE); base 1024 sound/arm/aaci.c writel(0, base + AACI_TXCR); base 1025 sound/arm/aaci.c writel(0, base + AACI_RXCR); base 1028 sound/arm/aaci.c writel(0x1fff, aaci->base + AACI_INTCLR); base 1029 sound/arm/aaci.c writel(aaci->maincr, aaci->base + AACI_MAINCR); base 1034 sound/arm/aaci.c readl(aaci->base + AACI_CSCH1); base 1076 sound/arm/aaci.c writel(0, aaci->base + AACI_MAINCR); base 200 sound/arm/aaci.h void __iomem *base; base 225 sound/arm/aaci.h void __iomem *base; base 46 sound/core/hrtimer.c delta = ktime_sub(hrt->base->get_time(), hrtimer_get_expires(hrt)); base 704 sound/core/seq/seq_queue.c ev->data.queue.param.skew.base) == 0) { base 240 sound/core/seq/seq_timer.c unsigned int base) base 248 sound/core/seq/seq_timer.c if (base != SKEW_BASE) { base 249 sound/core/seq/seq_timer.c pr_debug("ALSA: seq: invalid skew base 0x%x\n", base); base 122 sound/core/seq/seq_timer.h int snd_seq_timer_set_skew(struct snd_seq_timer *tmr, unsigned int skew, unsigned int base); base 934 sound/drivers/mts64.c card->shortname, p->base, p->irq); base 949 sound/drivers/mts64.c snd_printd("Cannot claim parport 0x%lx\n", pardev->port->base); base 984 sound/drivers/mts64.c snd_printk(KERN_INFO "ESI Miditerminal 4140 on 0x%lx\n", p->base); base 733 sound/drivers/portman2x4.c card->shortname, p->base, p->irq); base 748 sound/drivers/portman2x4.c snd_printd("Cannot claim parport 0x%lx\n", pardev->port->base); base 783 sound/drivers/portman2x4.c snd_printk(KERN_INFO "Portman 2x4 on 0x%lx\n", p->base); base 62 sound/drivers/serial-u16550.c static int base[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 115200}; /* baud base */ base 80 sound/drivers/serial-u16550.c module_param_array(base, int, NULL, 0444); base 81 sound/drivers/serial-u16550.c MODULE_PARM_DESC(base, "Base for divisor in bauds."); base 118 sound/drivers/serial-u16550.c unsigned long base; base 181 sound/drivers/serial-u16550.c outb(uart->tx_buff[buff_out], uart->base + UART_TX); base 203 sound/drivers/serial-u16550.c while ((status = inb(uart->base + UART_LSR)) & UART_LSR_DR) { base 205 sound/drivers/serial-u16550.c c = inb(uart->base + UART_RX); base 231 sound/drivers/serial-u16550.c uart->rmidi->name, uart->base); base 245 sound/drivers/serial-u16550.c status = inb(uart->base + UART_MSR); base 249 sound/drivers/serial-u16550.c status = inb(uart->base + UART_MSR); base 292 sound/drivers/serial-u16550.c inb(uart->base + UART_IIR); base 318 sound/drivers/serial-u16550.c unsigned long io_base = uart->base; base 378 sound/drivers/serial-u16550.c ,uart->base + UART_FCR); /* FIFO Control Register */ base 380 sound/drivers/serial-u16550.c if ((inb(uart->base + UART_IIR) & 0xf0) == 0xc0) base 383 sound/drivers/serial-u16550.c uart->old_line_ctrl_reg = inb(uart->base + UART_LCR); base 385 sound/drivers/serial-u16550.c ,uart->base + UART_LCR); /* Line Control Register */ base 386 sound/drivers/serial-u16550.c uart->old_divisor_lsb = inb(uart->base + UART_DLL); base 387 sound/drivers/serial-u16550.c uart->old_divisor_msb = inb(uart->base + UART_DLM); base 390 sound/drivers/serial-u16550.c ,uart->base + UART_DLL); /* Divisor Latch Low */ base 392 sound/drivers/serial-u16550.c ,uart->base + UART_DLM); /* Divisor Latch High */ base 400 sound/drivers/serial-u16550.c ,uart->base + UART_LCR); /* Line Control Register */ base 409 sound/drivers/serial-u16550.c ,uart->base + UART_MCR); /* Modem Control Register */ base 416 sound/drivers/serial-u16550.c uart->base + UART_MCR); base 422 sound/drivers/serial-u16550.c uart->base + UART_MCR); base 444 sound/drivers/serial-u16550.c outb(byte, uart->base + UART_IER); /* Interrupt enable Register */ base 446 sound/drivers/serial-u16550.c inb(uart->base + UART_LSR); /* Clear any pre-existing overrun indication */ base 447 sound/drivers/serial-u16550.c inb(uart->base + UART_IIR); /* Clear any pre-existing transmit interrupt */ base 448 sound/drivers/serial-u16550.c inb(uart->base + UART_RX); /* Clear any pre-existing receive interrupt */ base 462 sound/drivers/serial-u16550.c ,uart->base + UART_IER); /* Interrupt enable Register */ base 469 sound/drivers/serial-u16550.c ,uart->base + UART_MCR); /* Modem Control Register */ base 476 sound/drivers/serial-u16550.c uart->base + UART_MCR); base 482 sound/drivers/serial-u16550.c uart->base + UART_MCR); base 486 sound/drivers/serial-u16550.c inb(uart->base + UART_IIR); /* Clear any outstanding interrupts */ base 491 sound/drivers/serial-u16550.c ,uart->base + UART_LCR); /* Line Control Register */ base 493 sound/drivers/serial-u16550.c ,uart->base + UART_DLL); /* Divisor Latch Low */ base 495 sound/drivers/serial-u16550.c ,uart->base + UART_DLM); /* Divisor Latch High */ base 498 sound/drivers/serial-u16550.c ,uart->base + UART_LCR); /* Line Control Register */ base 606 sound/drivers/serial-u16550.c && (inb(uart->base + UART_MSR) & UART_MSR_CTS)))) { /* CTS? */ base 609 sound/drivers/serial-u16550.c if ((inb(uart->base + UART_LSR) & UART_LSR_THRE) != 0) { base 612 sound/drivers/serial-u16550.c outb(midi_byte, uart->base + UART_TX); base 616 sound/drivers/serial-u16550.c outb(midi_byte, uart->base + UART_TX); base 627 sound/drivers/serial-u16550.c uart->rmidi->name, uart->base); base 775 sound/drivers/serial-u16550.c unsigned int base, base 793 sound/drivers/serial-u16550.c uart->base = iobase; base 811 sound/drivers/serial-u16550.c uart->divisor = base / speed; base 812 sound/drivers/serial-u16550.c uart->speed = base / (unsigned int)uart->divisor; base 813 sound/drivers/serial-u16550.c uart->speed_base = base; base 832 sound/drivers/serial-u16550.c outb(UART_MCR_RTS | (0&UART_MCR_DTR), uart->base + UART_MCR); base 837 sound/drivers/serial-u16550.c outb(UART_MCR_RTS | UART_MCR_DTR, uart->base + UART_MCR); base 940 sound/drivers/serial-u16550.c base[dev], base 953 sound/drivers/serial-u16550.c uart->base, base 692 sound/hda/hdac_device.c #define HDA_RATE(base, mult, div) \ base 693 sound/hda/hdac_device.c (AC_FMT_BASE_##base##K | (((mult) - 1) << AC_FMT_MULT_SHIFT) | \ base 84 sound/i2c/other/pt2258.c int base = kcontrol->private_value; base 87 sound/i2c/other/pt2258.c ucontrol->value.integer.value[0] = 79 - pt->volume[base]; base 88 sound/i2c/other/pt2258.c ucontrol->value.integer.value[1] = 79 - pt->volume[base + 1]; base 96 sound/i2c/other/pt2258.c int base = kcontrol->private_value; base 104 sound/i2c/other/pt2258.c if (val0 == pt->volume[base] && val1 == pt->volume[base + 1]) base 107 sound/i2c/other/pt2258.c pt->volume[base] = val0; base 108 sound/i2c/other/pt2258.c bytes[0] = pt2258_channel_code[2 * base] | (val0 / 10); base 109 sound/i2c/other/pt2258.c bytes[1] = pt2258_channel_code[2 * base + 1] | (val0 % 10); base 115 sound/i2c/other/pt2258.c pt->volume[base + 1] = val1; base 116 sound/i2c/other/pt2258.c bytes[0] = pt2258_channel_code[2 * base + 2] | (val1 / 10); base 117 sound/i2c/other/pt2258.c bytes[1] = pt2258_channel_code[2 * base + 3] | (val1 % 10); base 44 sound/isa/msnd/msnd.c void snd_msnd_init_queue(void __iomem *base, int start, int size) base 46 sound/isa/msnd/msnd.c writew(PCTODSP_BASED(start), base + JQS_wStart); base 47 sound/isa/msnd/msnd.c writew(PCTODSP_OFFSET(size) - 1, base + JQS_wSize); base 48 sound/isa/msnd/msnd.c writew(0, base + JQS_wHead); base 49 sound/isa/msnd/msnd.c writew(0, base + JQS_wTail); base 282 sound/isa/msnd/msnd.c (char *)(chip->base + bank * DAR_BUFF_SIZE), base 226 sound/isa/msnd/msnd.h unsigned long base; base 273 sound/isa/msnd/msnd.h void snd_msnd_init_queue(void __iomem *base, int start, int size); base 233 sound/isa/msnd/msnd_pinnacle.c chip->base, chip->base + 0x7fff); base 294 sound/isa/msnd/msnd_pinnacle.c chip->base, chip->base + 0x7fff); base 546 sound/isa/msnd/msnd_pinnacle.c if (!request_mem_region(chip->base, BUFFSIZE, card->shortname)) { base 549 sound/isa/msnd/msnd_pinnacle.c chip->base, chip->base + BUFFSIZE - 1); base 554 sound/isa/msnd/msnd_pinnacle.c chip->mappedbase = ioremap_nocache(chip->base, 0x8000); base 558 sound/isa/msnd/msnd_pinnacle.c chip->base, chip->base + BUFFSIZE - 1); base 618 sound/isa/msnd/msnd_pinnacle.c release_mem_region(chip->base, BUFFSIZE); base 630 sound/isa/msnd/msnd_pinnacle.c release_mem_region(chip->base, BUFFSIZE); base 1011 sound/isa/msnd/msnd_pinnacle.c chip->base = mem[idx]; base 1136 sound/isa/msnd/msnd_pinnacle.c chip->base = mem[idx]; base 284 sound/isa/wavefront/wavefront.c acard->wavefront.midi.base = port; base 412 sound/isa/wavefront/wavefront.c acard->wavefront.base = ics2115_port[dev]; base 250 sound/isa/wavefront/wavefront_fx.c dev->base + firmware->data[i]); base 1635 sound/pci/cs46xx/cs46xx.h unsigned long base; base 3908 sound/pci/cs46xx/cs46xx_lib.c region->base = chip->ba0_addr; base 3913 sound/pci/cs46xx/cs46xx_lib.c region->base = chip->ba1_addr + BA1_SP_DMEM0; base 3918 sound/pci/cs46xx/cs46xx_lib.c region->base = chip->ba1_addr + BA1_SP_DMEM1; base 3923 sound/pci/cs46xx/cs46xx_lib.c region->base = chip->ba1_addr + BA1_SP_PMEM; base 3928 sound/pci/cs46xx/cs46xx_lib.c region->base = chip->ba1_addr + BA1_SP_REG; base 3974 sound/pci/cs46xx/cs46xx_lib.c if ((region->resource = request_mem_region(region->base, region->size, base 3978 sound/pci/cs46xx/cs46xx_lib.c region->base, region->base + region->size - 1); base 3982 sound/pci/cs46xx/cs46xx_lib.c region->remap_addr = ioremap_nocache(region->base, region->size); base 467 sound/pci/es1968.c u16 base[4]; /* offset for ptr */ base 913 sound/pci/es1968.c offset -= es->base[0]; base 938 sound/pci/es1968.c __apu_set_register(chip, es->apu[0], 5, es->base[0]); base 941 sound/pci/es1968.c __apu_set_register(chip, es->apu[2], 5, es->base[2]); base 945 sound/pci/es1968.c __apu_set_register(chip, es->apu[1], 5, es->base[1]); base 948 sound/pci/es1968.c __apu_set_register(chip, es->apu[3], 5, es->base[3]); base 1026 sound/pci/es1968.c es->base[channel] = pa & 0xFFFF; base 1109 sound/pci/es1968.c es->base[channel] = pa & 0xFFFF; base 353 sound/pci/hda/hda_controller.c static u64 azx_scale64(u64 base, u32 num, u32 den) base 357 sound/pci/hda/hda_controller.c rem = do_div(base, den); base 359 sound/pci/hda/hda_controller.c base *= num; base 364 sound/pci/hda/hda_controller.c return base + rem; base 96 sound/pci/intel8x0.c #define DEFINE_REGSET(name,base) \ base 98 sound/pci/intel8x0.c ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ base 99 sound/pci/intel8x0.c ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ base 100 sound/pci/intel8x0.c ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ base 101 sound/pci/intel8x0.c ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ base 102 sound/pci/intel8x0.c ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ base 103 sound/pci/intel8x0.c ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ base 104 sound/pci/intel8x0.c ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ base 66 sound/pci/intel8x0m.c #define DEFINE_REGSET(name,base) \ base 68 sound/pci/intel8x0m.c ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ base 69 sound/pci/intel8x0m.c ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ base 70 sound/pci/intel8x0m.c ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ base 71 sound/pci/intel8x0m.c ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ base 72 sound/pci/intel8x0m.c ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ base 73 sound/pci/intel8x0m.c ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ base 74 sound/pci/intel8x0m.c ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ base 375 sound/pci/nm256/nm256.c u32 base = chip->all_coeff_buf; base 378 sound/pci/nm256/nm256.c snd_nm256_writel(chip, addr, base + offset); base 381 sound/pci/nm256/nm256.c snd_nm256_writel(chip, addr + 4, base + end_offset); base 1237 sound/pci/nm256/nm256.c u32 base; base 1242 sound/pci/nm256/nm256.c base = chip->mixer_base; base 1248 sound/pci/nm256/nm256.c snd_nm256_writew(chip, base + reg, val); base 194 sound/pci/sis7019.c void __iomem *base = voice->ctrl_base; base 205 sound/pci/sis7019.c writew(voice->sso & 0xffff, base + SIS_PLAY_DMA_SSO_ESO + 2); base 775 sound/pci/via82xx.c unsigned int size, base, res; base 778 sound/pci/via82xx.c base = viadev->idx_table[idx].offset; base 779 sound/pci/via82xx.c res = base + size - count; base 799 sound/pci/via82xx.c res = base; base 811 sound/pci/via82xx.c res = base + size; base 175 sound/pci/ymfpci/ymfpci.h __le32 base; /* 32-bit address */ base 206 sound/pci/ymfpci/ymfpci.h __le32 base; /* 32-bit address */ base 213 sound/pci/ymfpci/ymfpci.h __le32 base; /* 32-bit address */ base 540 sound/pci/ymfpci/ymfpci_main.c bank->base = cpu_to_le32(runtime->dma_addr); base 594 sound/pci/ymfpci/ymfpci_main.c chip->bank_effect[3][0]->base = base 595 sound/pci/ymfpci/ymfpci_main.c chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr); base 598 sound/pci/ymfpci/ymfpci_main.c chip->bank_effect[4][0]->base = base 599 sound/pci/ymfpci/ymfpci_main.c chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048); base 737 sound/pci/ymfpci/ymfpci_main.c bank->base = cpu_to_le32(runtime->dma_addr); base 116 sound/ppc/burgundy.c #define BASE2ADDR(base) ((base) << 12) base 1087 sound/ppc/tumbler.c const u32 *base; base 1101 sound/ppc/tumbler.c base = of_get_property(node, "AAPL,address", NULL); base 1102 sound/ppc/tumbler.c if (! base) { base 1103 sound/ppc/tumbler.c base = of_get_property(node, "reg", NULL); base 1104 sound/ppc/tumbler.c if (!base) { base 1110 sound/ppc/tumbler.c addr = *base; base 1114 sound/ppc/tumbler.c addr = *base; base 1118 sound/ppc/tumbler.c base = of_get_property(node, "audio-gpio-active-state", NULL); base 1119 sound/ppc/tumbler.c if (base) { base 1120 sound/ppc/tumbler.c gp->active_state = *base; base 1121 sound/ppc/tumbler.c gp->active_val = (*base) ? 0x5 : 0x4; base 1122 sound/ppc/tumbler.c gp->inactive_val = (*base) ? 0x4 : 0x5; base 190 sound/soc/adi/axi-i2s.c void __iomem *base; base 202 sound/soc/adi/axi-i2s.c base = devm_ioremap_resource(&pdev->dev, res); base 203 sound/soc/adi/axi-i2s.c if (IS_ERR(base)) base 204 sound/soc/adi/axi-i2s.c return PTR_ERR(base); base 206 sound/soc/adi/axi-i2s.c i2s->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 183 sound/soc/adi/axi-spdif.c void __iomem *base; base 193 sound/soc/adi/axi-spdif.c base = devm_ioremap_resource(&pdev->dev, res); base 194 sound/soc/adi/axi-spdif.c if (IS_ERR(base)) base 195 sound/soc/adi/axi-spdif.c return PTR_ERR(base); base 197 sound/soc/adi/axi-spdif.c spdif->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 596 sound/soc/atmel/atmel-i2s.c void __iomem *base; base 614 sound/soc/atmel/atmel-i2s.c base = devm_ioremap_resource(&pdev->dev, mem); base 615 sound/soc/atmel/atmel-i2s.c if (IS_ERR(base)) base 616 sound/soc/atmel/atmel-i2s.c return PTR_ERR(base); base 618 sound/soc/atmel/atmel-i2s.c regmap = devm_regmap_init_mmio(&pdev->dev, base, base 70 sound/soc/atmel/atmel-pcm.h #define ssc_readx(base, reg) (__raw_readl((base) + (reg))) base 71 sound/soc/atmel/atmel-pcm.h #define ssc_writex(base, reg, value) __raw_writel((value), (base) + (reg)) base 886 sound/soc/atmel/mchp-i2s-mcc.c void __iomem *base; base 896 sound/soc/atmel/mchp-i2s-mcc.c base = devm_ioremap_resource(&pdev->dev, mem); base 897 sound/soc/atmel/mchp-i2s-mcc.c if (IS_ERR(base)) base 898 sound/soc/atmel/mchp-i2s-mcc.c return PTR_ERR(base); base 900 sound/soc/atmel/mchp-i2s-mcc.c regmap = devm_regmap_init_mmio(&pdev->dev, base, base 831 sound/soc/bcm/bcm2835-i2s.c void __iomem *base; base 850 sound/soc/bcm/bcm2835-i2s.c base = devm_platform_ioremap_resource(pdev, 0); base 851 sound/soc/bcm/bcm2835-i2s.c if (IS_ERR(base)) base 852 sound/soc/bcm/bcm2835-i2s.c return PTR_ERR(base); base 854 sound/soc/bcm/bcm2835-i2s.c dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base, base 700 sound/soc/bcm/cygnus-pcm.c unsigned int res = 0, cur = 0, base = 0; base 715 sound/soc/bcm/cygnus-pcm.c base = readl(aio->cygaud->audio + p_rbuf->baseaddr); base 721 sound/soc/bcm/cygnus-pcm.c res = (cur & 0x7fffffff) - (base & 0x7fffffff); base 1446 sound/soc/codecs/arizona.c int lrclk, bclk, mode, base; base 1448 sound/soc/codecs/arizona.c base = dai->driver->base; base 1518 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL, base 1522 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL, base 1526 sound/soc/codecs/arizona.c base + ARIZONA_AIF_RX_PIN_CTRL, base 1529 sound/soc/codecs/arizona.c regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FORMAT, base 1681 sound/soc/codecs/arizona.c int base = dai->driver->base; base 1729 sound/soc/codecs/arizona.c if (base) base 1731 sound/soc/codecs/arizona.c base + ARIZONA_AIF_RATE_CTRL, base 1739 sound/soc/codecs/arizona.c if (base) base 1741 sound/soc/codecs/arizona.c base + ARIZONA_AIF_RATE_CTRL, base 1754 sound/soc/codecs/arizona.c int base, int bclk, int lrclk, int frame) base 1758 sound/soc/codecs/arizona.c val = snd_soc_component_read32(component, base + ARIZONA_AIF_BCLK_CTRL); base 1762 sound/soc/codecs/arizona.c val = snd_soc_component_read32(component, base + ARIZONA_AIF_TX_BCLK_RATE); base 1766 sound/soc/codecs/arizona.c val = snd_soc_component_read32(component, base + ARIZONA_AIF_FRAME_CTRL_1); base 1781 sound/soc/codecs/arizona.c int base = dai->driver->base; base 1816 sound/soc/codecs/arizona.c val = snd_soc_component_read32(component, base + ARIZONA_AIF_FORMAT); base 1844 sound/soc/codecs/arizona.c reconfig = arizona_aif_cfg_changed(component, base, bclk, lrclk, frame); base 1849 sound/soc/codecs/arizona.c base + ARIZONA_AIF_TX_ENABLES); base 1851 sound/soc/codecs/arizona.c base + ARIZONA_AIF_RX_ENABLES); base 1854 sound/soc/codecs/arizona.c base + ARIZONA_AIF_TX_ENABLES, base 1857 sound/soc/codecs/arizona.c base + ARIZONA_AIF_RX_ENABLES, 0xff, 0x0); base 1866 sound/soc/codecs/arizona.c base + ARIZONA_AIF_BCLK_CTRL, base 1869 sound/soc/codecs/arizona.c base + ARIZONA_AIF_TX_BCLK_RATE, base 1872 sound/soc/codecs/arizona.c base + ARIZONA_AIF_RX_BCLK_RATE, base 1875 sound/soc/codecs/arizona.c base + ARIZONA_AIF_FRAME_CTRL_1, base 1879 sound/soc/codecs/arizona.c base + ARIZONA_AIF_FRAME_CTRL_2, base 1888 sound/soc/codecs/arizona.c base + ARIZONA_AIF_TX_ENABLES, base 1891 sound/soc/codecs/arizona.c base + ARIZONA_AIF_RX_ENABLES, base 1958 sound/soc/codecs/arizona.c int base = dai->driver->base; base 1967 sound/soc/codecs/arizona.c base + ARIZONA_AIF_RATE_CTRL, base 1972 sound/soc/codecs/arizona.c unsigned int base, base 1985 sound/soc/codecs/arizona.c regmap_write(arizona->regmap, base + i, slot); base 2000 sound/soc/codecs/arizona.c int base = dai->driver->base; base 2013 sound/soc/codecs/arizona.c arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_3, base 2015 sound/soc/codecs/arizona.c arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_11, base 2328 sound/soc/codecs/arizona.c static void arizona_apply_fll(struct arizona *arizona, unsigned int base, base 2332 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, base + 3, base 2334 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, base + 4, base 2336 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, base + 5, base 2339 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, base + 6, base 2346 sound/soc/codecs/arizona.c regmap_update_bits(arizona->regmap, base + 0x7, base 2350 sound/soc/codecs/arizona.c regmap_update_bits(arizona->regmap, base + 0x5, base 2353 sound/soc/codecs/arizona.c regmap_update_bits(arizona->regmap, base + 0x9, base 2358 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, base + 2, base 2363 sound/soc/codecs/arizona.c static int arizona_is_enabled_fll(struct arizona_fll *fll, int base) base 2369 sound/soc/codecs/arizona.c ret = regmap_read(arizona->regmap, base + 1, ®); base 2379 sound/soc/codecs/arizona.c static int arizona_set_fll_clks(struct arizona_fll *fll, int base, bool ena) base 2386 sound/soc/codecs/arizona.c ret = regmap_read(arizona->regmap, base + 6, &val); base 2419 sound/soc/codecs/arizona.c int already_enabled = arizona_is_enabled_fll(fll, fll->base); base 2420 sound/soc/codecs/arizona.c int sync_enabled = arizona_is_enabled_fll(fll, fll->base + 0x10); base 2432 sound/soc/codecs/arizona.c regmap_update_bits(fll->arizona->regmap, fll->base + 1, base 2435 sound/soc/codecs/arizona.c regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x9, base 2438 sound/soc/codecs/arizona.c if (arizona_is_enabled_fll(fll, fll->base + 0x10) > 0) base 2439 sound/soc/codecs/arizona.c arizona_set_fll_clks(fll, fll->base + 0x10, false); base 2440 sound/soc/codecs/arizona.c arizona_set_fll_clks(fll, fll->base, false); base 2455 sound/soc/codecs/arizona.c arizona_apply_fll(arizona, fll->base, &cfg, fll->ref_src, base 2460 sound/soc/codecs/arizona.c arizona_apply_fll(arizona, fll->base + 0x10, &cfg, base 2467 sound/soc/codecs/arizona.c arizona_apply_fll(arizona, fll->base, &cfg, base 2470 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, fll->base + 0x11, base 2485 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, fll->base + 0x17, base 2488 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, fll->base + 0x17, base 2496 sound/soc/codecs/arizona.c arizona_set_fll_clks(fll, fll->base + 0x10, true); base 2497 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, fll->base + 0x11, base 2501 sound/soc/codecs/arizona.c arizona_set_fll_clks(fll, fll->base, true); base 2502 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, fll->base + 1, base 2506 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, fll->base + 1, base 2536 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, fll->base + 1, base 2538 sound/soc/codecs/arizona.c regmap_update_bits_check(arizona->regmap, fll->base + 1, base 2540 sound/soc/codecs/arizona.c regmap_update_bits_check(arizona->regmap, fll->base + 0x11, base 2542 sound/soc/codecs/arizona.c regmap_update_bits_async(arizona->regmap, fll->base + 1, base 2546 sound/soc/codecs/arizona.c arizona_set_fll_clks(fll, fll->base + 0x10, false); base 2549 sound/soc/codecs/arizona.c arizona_set_fll_clks(fll, fll->base, false); base 2612 sound/soc/codecs/arizona.c int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq, base 2618 sound/soc/codecs/arizona.c fll->base = base; base 2638 sound/soc/codecs/arizona.c regmap_update_bits(arizona->regmap, fll->base + 1, base 2752 sound/soc/codecs/arizona.c ret = regmap_read(arizona->regmap, params->base, &val); base 2759 sound/soc/codecs/arizona.c ret = regmap_raw_write(arizona->regmap, params->base, data, len); base 106 sound/soc/codecs/arizona.h #define ARIZONA_GAINMUX_CONTROLS(name, base) \ base 107 sound/soc/codecs/arizona.h SOC_SINGLE_RANGE_TLV(name " Input Volume", base + 1, \ base 111 sound/soc/codecs/arizona.h #define ARIZONA_MIXER_CONTROLS(name, base) \ base 112 sound/soc/codecs/arizona.h SOC_SINGLE_RANGE_TLV(name " Input 1 Volume", base + 1, \ base 115 sound/soc/codecs/arizona.h SOC_SINGLE_RANGE_TLV(name " Input 2 Volume", base + 3, \ base 118 sound/soc/codecs/arizona.h SOC_SINGLE_RANGE_TLV(name " Input 3 Volume", base + 5, \ base 121 sound/soc/codecs/arizona.h SOC_SINGLE_RANGE_TLV(name " Input 4 Volume", base + 7, \ base 212 sound/soc/codecs/arizona.h ((unsigned long)&(struct soc_bytes) { .base = xbase, \ base 219 sound/soc/codecs/arizona.h ((unsigned long)&(struct soc_bytes) { .base = xbase, \ base 284 sound/soc/codecs/arizona.h unsigned int base; base 303 sound/soc/codecs/arizona.h int arizona_init_fll(struct arizona *arizona, int id, int base, base 49 sound/soc/codecs/cs47l15.c { .type = WMFW_ADSP2_PM, .base = 0x080000 }, base 50 sound/soc/codecs/cs47l15.c { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 }, base 51 sound/soc/codecs/cs47l15.c { .type = WMFW_ADSP2_XM, .base = 0x0a0000 }, base 52 sound/soc/codecs/cs47l15.c { .type = WMFW_ADSP2_YM, .base = 0x0c0000 }, base 99 sound/soc/codecs/cs47l15.c #define CS47L15_NG_SRC(name, base) \ base 100 sound/soc/codecs/cs47l15.c SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ base 101 sound/soc/codecs/cs47l15.c SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ base 102 sound/soc/codecs/cs47l15.c SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ base 103 sound/soc/codecs/cs47l15.c SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ base 104 sound/soc/codecs/cs47l15.c SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0) base 1140 sound/soc/codecs/cs47l15.c .base = MADERA_AIF1_BCLK_CTRL, base 1162 sound/soc/codecs/cs47l15.c .base = MADERA_AIF2_BCLK_CTRL, base 1184 sound/soc/codecs/cs47l15.c .base = MADERA_AIF3_BCLK_CTRL, base 1399 sound/soc/codecs/cs47l15.c cs47l15->core.adsp[0].base = MADERA_DSP1_CONFIG_1; base 41 sound/soc/codecs/cs47l24.c { .type = WMFW_ADSP2_PM, .base = 0x200000 }, base 42 sound/soc/codecs/cs47l24.c { .type = WMFW_ADSP2_ZM, .base = 0x280000 }, base 43 sound/soc/codecs/cs47l24.c { .type = WMFW_ADSP2_XM, .base = 0x290000 }, base 44 sound/soc/codecs/cs47l24.c { .type = WMFW_ADSP2_YM, .base = 0x2a8000 }, base 48 sound/soc/codecs/cs47l24.c { .type = WMFW_ADSP2_PM, .base = 0x300000 }, base 49 sound/soc/codecs/cs47l24.c { .type = WMFW_ADSP2_ZM, .base = 0x380000 }, base 50 sound/soc/codecs/cs47l24.c { .type = WMFW_ADSP2_XM, .base = 0x390000 }, base 51 sound/soc/codecs/cs47l24.c { .type = WMFW_ADSP2_YM, .base = 0x3a8000 }, base 85 sound/soc/codecs/cs47l24.c #define CS47L24_NG_SRC(name, base) \ base 86 sound/soc/codecs/cs47l24.c SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ base 87 sound/soc/codecs/cs47l24.c SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ base 88 sound/soc/codecs/cs47l24.c SOC_SINGLE(name " NG SPKOUT Switch", base, 6, 1, 0) base 964 sound/soc/codecs/cs47l24.c .base = ARIZONA_AIF1_BCLK_CTRL, base 986 sound/soc/codecs/cs47l24.c .base = ARIZONA_AIF2_BCLK_CTRL, base 1008 sound/soc/codecs/cs47l24.c .base = ARIZONA_AIF3_BCLK_CTRL, base 1242 sound/soc/codecs/cs47l24.c cs47l24->core.adsp[i].base = ARIZONA_DSP1_CONTROL_1 + base 41 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_PM, .base = 0x080000 }, base 42 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 }, base 43 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_XM, .base = 0x0a0000 }, base 44 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_YM, .base = 0x0c0000 }, base 48 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_PM, .base = 0x100000 }, base 49 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_ZM, .base = 0x160000 }, base 50 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_XM, .base = 0x120000 }, base 51 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_YM, .base = 0x140000 }, base 55 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_PM, .base = 0x180000 }, base 56 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 }, base 57 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_XM, .base = 0x1a0000 }, base 58 sound/soc/codecs/cs47l35.c { .type = WMFW_ADSP2_YM, .base = 0x1c0000 }, base 120 sound/soc/codecs/cs47l35.c #define CS47L35_NG_SRC(name, base) \ base 121 sound/soc/codecs/cs47l35.c SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ base 122 sound/soc/codecs/cs47l35.c SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ base 123 sound/soc/codecs/cs47l35.c SOC_SINGLE(name " NG SPKOUT Switch", base, 6, 1, 0), \ base 124 sound/soc/codecs/cs47l35.c SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ base 125 sound/soc/codecs/cs47l35.c SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0) base 1357 sound/soc/codecs/cs47l35.c .base = MADERA_AIF1_BCLK_CTRL, base 1379 sound/soc/codecs/cs47l35.c .base = MADERA_AIF2_BCLK_CTRL, base 1401 sound/soc/codecs/cs47l35.c .base = MADERA_AIF3_BCLK_CTRL, base 1692 sound/soc/codecs/cs47l35.c cs47l35->core.adsp[i].base = wm_adsp2_control_bases[i]; base 41 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_PM, .base = 0x080000 }, base 42 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 }, base 43 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_XM, .base = 0x0a0000 }, base 44 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_YM, .base = 0x0c0000 }, base 48 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_PM, .base = 0x100000 }, base 49 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_ZM, .base = 0x160000 }, base 50 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_XM, .base = 0x120000 }, base 51 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_YM, .base = 0x140000 }, base 55 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_PM, .base = 0x180000 }, base 56 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 }, base 57 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_XM, .base = 0x1a0000 }, base 58 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_YM, .base = 0x1c0000 }, base 62 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_PM, .base = 0x200000 }, base 63 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_ZM, .base = 0x260000 }, base 64 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_XM, .base = 0x220000 }, base 65 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_YM, .base = 0x240000 }, base 69 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_PM, .base = 0x280000 }, base 70 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_ZM, .base = 0x2e0000 }, base 71 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_XM, .base = 0x2a0000 }, base 72 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_YM, .base = 0x2c0000 }, base 76 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_PM, .base = 0x300000 }, base 77 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_ZM, .base = 0x360000 }, base 78 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_XM, .base = 0x320000 }, base 79 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_YM, .base = 0x340000 }, base 83 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_PM, .base = 0x380000 }, base 84 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_ZM, .base = 0x3e0000 }, base 85 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_XM, .base = 0x3a0000 }, base 86 sound/soc/codecs/cs47l85.c { .type = WMFW_ADSP2_YM, .base = 0x3c0000 }, base 144 sound/soc/codecs/cs47l85.c #define CS47L85_NG_SRC(name, base) \ base 145 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ base 146 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ base 147 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \ base 148 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \ base 149 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \ base 150 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \ base 151 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ base 152 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \ base 153 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ base 154 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0), \ base 155 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG SPKDAT2L Switch", base, 10, 1, 0), \ base 156 sound/soc/codecs/cs47l85.c SOC_SINGLE(name " NG SPKDAT2R Switch", base, 11, 1, 0) base 2255 sound/soc/codecs/cs47l85.c .base = MADERA_AIF1_BCLK_CTRL, base 2277 sound/soc/codecs/cs47l85.c .base = MADERA_AIF2_BCLK_CTRL, base 2299 sound/soc/codecs/cs47l85.c .base = MADERA_AIF3_BCLK_CTRL, base 2321 sound/soc/codecs/cs47l85.c .base = MADERA_AIF4_BCLK_CTRL, base 2640 sound/soc/codecs/cs47l85.c cs47l85->core.adsp[i].base = wm_adsp2_control_bases[i]; base 41 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_PM, .base = 0x080000 }, base 42 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 }, base 43 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_XM, .base = 0x0a0000 }, base 44 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_YM, .base = 0x0c0000 }, base 48 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_PM, .base = 0x100000 }, base 49 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_ZM, .base = 0x160000 }, base 50 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_XM, .base = 0x120000 }, base 51 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_YM, .base = 0x140000 }, base 55 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_PM, .base = 0x180000 }, base 56 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 }, base 57 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_XM, .base = 0x1a0000 }, base 58 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_YM, .base = 0x1c0000 }, base 62 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_PM, .base = 0x200000 }, base 63 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_ZM, .base = 0x260000 }, base 64 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_XM, .base = 0x220000 }, base 65 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_YM, .base = 0x240000 }, base 69 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_PM, .base = 0x280000 }, base 70 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_ZM, .base = 0x2e0000 }, base 71 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_XM, .base = 0x2a0000 }, base 72 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_YM, .base = 0x2c0000 }, base 76 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_PM, .base = 0x300000 }, base 77 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_ZM, .base = 0x360000 }, base 78 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_XM, .base = 0x320000 }, base 79 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_YM, .base = 0x340000 }, base 83 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_PM, .base = 0x380000 }, base 84 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_ZM, .base = 0x3e0000 }, base 85 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_XM, .base = 0x3a0000 }, base 86 sound/soc/codecs/cs47l90.c { .type = WMFW_ADSP2_YM, .base = 0x3c0000 }, base 141 sound/soc/codecs/cs47l90.c #define CS47L90_NG_SRC(name, base) \ base 142 sound/soc/codecs/cs47l90.c SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ base 143 sound/soc/codecs/cs47l90.c SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ base 144 sound/soc/codecs/cs47l90.c SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \ base 145 sound/soc/codecs/cs47l90.c SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \ base 146 sound/soc/codecs/cs47l90.c SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \ base 147 sound/soc/codecs/cs47l90.c SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \ base 148 sound/soc/codecs/cs47l90.c SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ base 149 sound/soc/codecs/cs47l90.c SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0) base 2166 sound/soc/codecs/cs47l90.c .base = MADERA_AIF1_BCLK_CTRL, base 2188 sound/soc/codecs/cs47l90.c .base = MADERA_AIF2_BCLK_CTRL, base 2210 sound/soc/codecs/cs47l90.c .base = MADERA_AIF3_BCLK_CTRL, base 2232 sound/soc/codecs/cs47l90.c .base = MADERA_AIF4_BCLK_CTRL, base 2543 sound/soc/codecs/cs47l90.c cs47l90->core.adsp[i].base = cs47l90_dsp_control_bases[i]; base 41 sound/soc/codecs/cs47l92.c { .type = WMFW_ADSP2_PM, .base = 0x080000 }, base 42 sound/soc/codecs/cs47l92.c { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 }, base 43 sound/soc/codecs/cs47l92.c { .type = WMFW_ADSP2_XM, .base = 0x0a0000 }, base 44 sound/soc/codecs/cs47l92.c { .type = WMFW_ADSP2_YM, .base = 0x0c0000 }, base 166 sound/soc/codecs/cs47l92.c #define CS47L92_NG_SRC(name, base) \ base 167 sound/soc/codecs/cs47l92.c SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ base 168 sound/soc/codecs/cs47l92.c SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ base 169 sound/soc/codecs/cs47l92.c SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \ base 170 sound/soc/codecs/cs47l92.c SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \ base 171 sound/soc/codecs/cs47l92.c SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \ base 172 sound/soc/codecs/cs47l92.c SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \ base 173 sound/soc/codecs/cs47l92.c SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ base 174 sound/soc/codecs/cs47l92.c SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0) base 1639 sound/soc/codecs/cs47l92.c .base = MADERA_AIF1_BCLK_CTRL, base 1661 sound/soc/codecs/cs47l92.c .base = MADERA_AIF2_BCLK_CTRL, base 1683 sound/soc/codecs/cs47l92.c .base = MADERA_AIF3_BCLK_CTRL, base 1951 sound/soc/codecs/cs47l92.c cs47l92->core.adsp[0].base = MADERA_DSP1_CONFIG_1; base 954 sound/soc/codecs/da732x.c reg_aif = dai->driver->base; base 1206 sound/soc/codecs/da732x.c .base = DA732X_REG_AIFA1, base 1226 sound/soc/codecs/da732x.c .base = DA732X_REG_AIFB1, base 28 sound/soc/codecs/inno_rk3036.c void __iomem *base; base 408 sound/soc/codecs/inno_rk3036.c void __iomem *base; base 416 sound/soc/codecs/inno_rk3036.c base = devm_platform_ioremap_resource(pdev, 0); base 417 sound/soc/codecs/inno_rk3036.c if (IS_ERR(base)) base 418 sound/soc/codecs/inno_rk3036.c return PTR_ERR(base); base 420 sound/soc/codecs/inno_rk3036.c priv->base = base; base 421 sound/soc/codecs/inno_rk3036.c priv->regmap = devm_regmap_init_mmio(&pdev->dev, priv->base, base 141 sound/soc/codecs/jz4725b.c void __iomem *base; base 471 sound/soc/codecs/jz4725b.c return readl_poll_timeout(icdc->base + ICDC_RGADW_OFFSET, reg, base 487 sound/soc/codecs/jz4725b.c tmp = readl(icdc->base + ICDC_RGADW_OFFSET); base 490 sound/soc/codecs/jz4725b.c writel(tmp, icdc->base + ICDC_RGADW_OFFSET); base 494 sound/soc/codecs/jz4725b.c *val = readl(icdc->base + ICDC_RGDATA_OFFSET) & base 511 sound/soc/codecs/jz4725b.c icdc->base + ICDC_RGADW_OFFSET); base 554 sound/soc/codecs/jz4725b.c icdc->base = devm_platform_ioremap_resource(pdev, 0); base 555 sound/soc/codecs/jz4725b.c if (IS_ERR(icdc->base)) base 556 sound/soc/codecs/jz4725b.c return PTR_ERR(icdc->base); base 321 sound/soc/codecs/jz4740.c void __iomem *base; base 328 sound/soc/codecs/jz4740.c base = devm_platform_ioremap_resource(pdev, 0); base 329 sound/soc/codecs/jz4740.c if (IS_ERR(base)) base 330 sound/soc/codecs/jz4740.c return PTR_ERR(base); base 332 sound/soc/codecs/jz4740.c jz4740_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 862 sound/soc/codecs/madera.c if (!madera_can_change_grp_rate(priv, priv->adsp[adsp_num].base)) { base 936 sound/soc/codecs/madera.c dsp->base + MADERA_DSP_CONFIG_2_OFFS, freq); base 943 sound/soc/codecs/madera.c dsp->base + MADERA_DSP_CONFIG_1_OFFS, base 975 sound/soc/codecs/madera.c ret = regmap_read(dsp->regmap, dsp->base, &cur); base 2722 sound/soc/codecs/madera.c int lrclk, bclk, mode, base; base 2724 sound/soc/codecs/madera.c base = dai->driver->base; base 2796 sound/soc/codecs/madera.c regmap_update_bits(madera->regmap, base + MADERA_AIF_BCLK_CTRL, base 2799 sound/soc/codecs/madera.c regmap_update_bits(madera->regmap, base + MADERA_AIF_TX_PIN_CTRL, base 2802 sound/soc/codecs/madera.c regmap_update_bits(madera->regmap, base + MADERA_AIF_RX_PIN_CTRL, base 2805 sound/soc/codecs/madera.c regmap_update_bits(madera->regmap, base + MADERA_AIF_FORMAT, base 2955 sound/soc/codecs/madera.c int base = dai->driver->base; base 3000 sound/soc/codecs/madera.c if (!base) base 3004 sound/soc/codecs/madera.c base + MADERA_AIF_RATE_CTRL, &cur); base 3015 sound/soc/codecs/madera.c if (!madera_can_change_grp_rate(priv, base + MADERA_AIF_RATE_CTRL)) { base 3023 sound/soc/codecs/madera.c snd_soc_component_update_bits(component, base + MADERA_AIF_RATE_CTRL, base 3034 sound/soc/codecs/madera.c int base, int bclk, int lrclk, int frame) base 3039 sound/soc/codecs/madera.c ret = snd_soc_component_read(component, base + MADERA_AIF_BCLK_CTRL, base 3046 sound/soc/codecs/madera.c ret = snd_soc_component_read(component, base + MADERA_AIF_RX_BCLK_RATE, base 3053 sound/soc/codecs/madera.c ret = snd_soc_component_read(component, base + MADERA_AIF_FRAME_CTRL_1, base 3071 sound/soc/codecs/madera.c int base = dai->driver->base; base 3112 sound/soc/codecs/madera.c ret = snd_soc_component_read(component, base + MADERA_AIF_FORMAT, &val); base 3142 sound/soc/codecs/madera.c reconfig = madera_aif_cfg_changed(component, base, bclk, lrclk, frame); base 3148 sound/soc/codecs/madera.c regmap_read(madera->regmap, base + MADERA_AIF_TX_ENABLES, base 3150 sound/soc/codecs/madera.c regmap_read(madera->regmap, base + MADERA_AIF_RX_ENABLES, base 3154 sound/soc/codecs/madera.c base + MADERA_AIF_TX_ENABLES, 0xff, 0x0); base 3156 sound/soc/codecs/madera.c base + MADERA_AIF_RX_ENABLES, 0xff, 0x0); base 3165 sound/soc/codecs/madera.c base + MADERA_AIF_BCLK_CTRL, base 3168 sound/soc/codecs/madera.c base + MADERA_AIF_RX_BCLK_RATE, base 3171 sound/soc/codecs/madera.c base + MADERA_AIF_FRAME_CTRL_1, base 3175 sound/soc/codecs/madera.c base + MADERA_AIF_FRAME_CTRL_2, base 3184 sound/soc/codecs/madera.c base + MADERA_AIF_TX_ENABLES, base 3187 sound/soc/codecs/madera.c base + MADERA_AIF_RX_ENABLES, base 3261 sound/soc/codecs/madera.c int base = dai->driver->base; base 3271 sound/soc/codecs/madera.c base + MADERA_AIF_RATE_CTRL, base 3280 sound/soc/codecs/madera.c unsigned int base, base 3293 sound/soc/codecs/madera.c regmap_write(madera->regmap, base + i, slot); base 3307 sound/soc/codecs/madera.c int base = dai->driver->base; base 3320 sound/soc/codecs/madera.c madera_set_channels_to_mask(dai, base + MADERA_AIF_FRAME_CTRL_3, base 3322 sound/soc/codecs/madera.c madera_set_channels_to_mask(dai, base + MADERA_AIF_FRAME_CTRL_11, base 3684 sound/soc/codecs/madera.c static bool madera_write_fll(struct madera *madera, unsigned int base, base 3692 sound/soc/codecs/madera.c base + MADERA_FLL_CONTROL_3_OFFS, base 3697 sound/soc/codecs/madera.c base + MADERA_FLL_CONTROL_4_OFFS, base 3702 sound/soc/codecs/madera.c base + MADERA_FLL_CONTROL_5_OFFS, base 3708 sound/soc/codecs/madera.c base + MADERA_FLL_CONTROL_6_OFFS, base 3718 sound/soc/codecs/madera.c base + MADERA_FLL_SYNCHRONISER_7_OFFS, base 3725 sound/soc/codecs/madera.c base + MADERA_FLL_CONTROL_7_OFFS, base 3733 sound/soc/codecs/madera.c base + MADERA_FLL_CONTROL_2_OFFS, base 3741 sound/soc/codecs/madera.c static int madera_is_enabled_fll(struct madera_fll *fll, int base) base 3748 sound/soc/codecs/madera.c base + MADERA_FLL_CONTROL_1_OFFS, ®); base 3804 sound/soc/codecs/madera.c fll->base + MADERA_FLL_EFS_2_OFFS, base 3820 sound/soc/codecs/madera.c sync_base = fll->base + CS47L35_FLL_SYNCHRONISER_OFFS; base 3823 sound/soc/codecs/madera.c sync_base = fll->base + MADERA_FLL_SYNCHRONISER_OFFS; base 3830 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 3833 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 3839 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 3852 sound/soc/codecs/madera.c int already_enabled = madera_is_enabled_fll(fll, fll->base); base 3880 sound/soc/codecs/madera.c sync_base = fll->base + CS47L35_FLL_SYNCHRONISER_OFFS; base 3883 sound/soc/codecs/madera.c sync_base = fll->base + MADERA_FLL_SYNCHRONISER_OFFS; base 3894 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 3899 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_7_OFFS, base 3958 sound/soc/codecs/madera.c fll_change |= madera_write_fll(madera, fll->base, base 3985 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 3990 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 4048 sound/soc/codecs/madera.c ret = madera_is_enabled_fll(fll, fll->base); base 4066 sound/soc/codecs/madera.c int madera_init_fll(struct madera *madera, int id, int base, base 4070 sound/soc/codecs/madera.c fll->base = base; base 4076 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 4137 sound/soc/codecs/madera.c int already_enabled = madera_is_enabled_fll(fll, fll->base); base 4152 sound/soc/codecs/madera.c fll->base + MADERA_FLLAO_CONTROL_1_OFFS, base 4169 sound/soc/codecs/madera.c fll->base + MADERA_FLLAO_CONTROL_1_OFFS, base 4174 sound/soc/codecs/madera.c fll->base + MADERA_FLLAO_CONTROL_1_OFFS, base 4191 sound/soc/codecs/madera.c fll->base + MADERA_FLLAO_CONTROL_1_OFFS, base 4194 sound/soc/codecs/madera.c fll->base + MADERA_FLLAO_CONTROL_1_OFFS, base 4208 sound/soc/codecs/madera.c fll->base + MADERA_FLLAO_CONTROL_2_OFFS, base 4276 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_11_OFFS, base 4279 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 4282 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 4295 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_2_OFFS, base 4409 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_2_OFFS, base 4412 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_3_OFFS, base 4416 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_4_OFFS, base 4420 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_5_OFFS, base 4424 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_6_OFFS, base 4428 sound/soc/codecs/madera.c fll->base + MADERA_FLL_GAIN_OFFS, base 4434 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_10_OFFS, base 4438 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_11_OFFS, base 4442 sound/soc/codecs/madera.c fll->base + MADERA_FLL1_DIGITAL_TEST_1_OFFS, base 4453 sound/soc/codecs/madera.c int already_enabled = madera_is_enabled_fll(fll, fll->base); base 4467 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 4478 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 4483 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 4489 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_11_OFFS, base 4494 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_2_OFFS, base 4500 sound/soc/codecs/madera.c fll->base + MADERA_FLL_CONTROL_1_OFFS, base 4651 sound/soc/codecs/madera.c ret = regmap_read(madera->regmap, params->base, &val); base 4658 sound/soc/codecs/madera.c ret = regmap_raw_write(madera->regmap, params->base, data, len); base 159 sound/soc/codecs/madera.h unsigned int base; base 186 sound/soc/codecs/madera.h #define MADERA_GAINMUX_CONTROLS(name, base) \ base 187 sound/soc/codecs/madera.h SOC_SINGLE_RANGE_TLV(name " Input Volume", base + 1, \ base 191 sound/soc/codecs/madera.h #define MADERA_MIXER_CONTROLS(name, base) \ base 192 sound/soc/codecs/madera.h SOC_SINGLE_RANGE_TLV(name " Input 1 Volume", base + 1, \ base 195 sound/soc/codecs/madera.h SOC_SINGLE_RANGE_TLV(name " Input 2 Volume", base + 3, \ base 198 sound/soc/codecs/madera.h SOC_SINGLE_RANGE_TLV(name " Input 3 Volume", base + 5, \ base 201 sound/soc/codecs/madera.h SOC_SINGLE_RANGE_TLV(name " Input 4 Volume", base + 7, \ base 299 sound/soc/codecs/madera.h ((unsigned long)&(struct soc_bytes) { .base = xbase, \ base 306 sound/soc/codecs/madera.h ((unsigned long)&(struct soc_bytes) { .base = xbase, \ base 406 sound/soc/codecs/madera.h int madera_init_fll(struct madera *madera, int id, int base, base 1173 sound/soc/codecs/msm8916-wcd-digital.c void __iomem *base; base 1181 sound/soc/codecs/msm8916-wcd-digital.c base = devm_platform_ioremap_resource(pdev, 0); base 1182 sound/soc/codecs/msm8916-wcd-digital.c if (IS_ERR(base)) base 1183 sound/soc/codecs/msm8916-wcd-digital.c return PTR_ERR(base); base 1186 sound/soc/codecs/msm8916-wcd-digital.c devm_regmap_init_mmio(&pdev->dev, base, base 436 sound/soc/codecs/rk3328_codec.c void __iomem *base; base 484 sound/soc/codecs/rk3328_codec.c base = devm_platform_ioremap_resource(pdev, 0); base 485 sound/soc/codecs/rk3328_codec.c if (IS_ERR(base)) base 486 sound/soc/codecs/rk3328_codec.c return PTR_ERR(base); base 488 sound/soc/codecs/rk3328_codec.c rk3328->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 4678 sound/soc/codecs/rt5677.c rt5677->gpio_chip.base = -1; base 461 sound/soc/codecs/sirf-audio-codec.c void __iomem *base; base 470 sound/soc/codecs/sirf-audio-codec.c base = devm_platform_ioremap_resource(pdev, 0); base 471 sound/soc/codecs/sirf-audio-codec.c if (IS_ERR(base)) base 472 sound/soc/codecs/sirf-audio-codec.c return PTR_ERR(base); base 474 sound/soc/codecs/sirf-audio-codec.c sirf_audio_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 260 sound/soc/codecs/tlv320aic23.c int base = mclk / bosr_usb_divisor_table[i]; base 269 sound/soc/codecs/tlv320aic23.c adc = base * sr_adc_mult_table[j]; base 270 sound/soc/codecs/tlv320aic23.c dac = base * sr_dac_mult_table[j]; base 157 sound/soc/codecs/wm2200.c { .type = WMFW_ADSP1_PM, .base = WM2200_DSP1_PM_BASE }, base 158 sound/soc/codecs/wm2200.c { .type = WMFW_ADSP1_DM, .base = WM2200_DSP1_DM_BASE }, base 159 sound/soc/codecs/wm2200.c { .type = WMFW_ADSP1_ZM, .base = WM2200_DSP1_ZM_BASE }, base 163 sound/soc/codecs/wm2200.c { .type = WMFW_ADSP1_PM, .base = WM2200_DSP2_PM_BASE }, base 164 sound/soc/codecs/wm2200.c { .type = WMFW_ADSP1_DM, .base = WM2200_DSP2_DM_BASE }, base 165 sound/soc/codecs/wm2200.c { .type = WMFW_ADSP1_ZM, .base = WM2200_DSP2_ZM_BASE }, base 1069 sound/soc/codecs/wm2200.c #define WM2200_MIXER_CONTROLS(name, base) \ base 1070 sound/soc/codecs/wm2200.c SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \ base 1072 sound/soc/codecs/wm2200.c SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \ base 1074 sound/soc/codecs/wm2200.c SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \ base 1076 sound/soc/codecs/wm2200.c SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \ base 2223 sound/soc/codecs/wm2200.c wm2200->dsp[0].base = WM2200_DSP1_CONTROL_1; base 2227 sound/soc/codecs/wm2200.c wm2200->dsp[1].base = WM2200_DSP2_CONTROL_1; base 375 sound/soc/codecs/wm5100.c #define WM5100_MIXER_CONTROLS(name, base) \ base 376 sound/soc/codecs/wm5100.c SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \ base 378 sound/soc/codecs/wm5100.c SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \ base 380 sound/soc/codecs/wm5100.c SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \ base 382 sound/soc/codecs/wm5100.c SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \ base 1282 sound/soc/codecs/wm5100.c int lrclk, bclk, mask, base; base 1284 sound/soc/codecs/wm5100.c base = dai->driver->base; base 1338 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 1, WM5100_AIF1_BCLK_MSTR | base 1340 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 2, WM5100_AIF1TX_LRCLK_MSTR | base 1342 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 3, WM5100_AIF1TX_LRCLK_MSTR | base 1344 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 5, WM5100_AIF1_FMT_MASK, mask); base 1402 sound/soc/codecs/wm5100.c int i, base, bclk, aif_rate, lrclk, wl, fl, sr; base 1405 sound/soc/codecs/wm5100.c base = dai->driver->base; base 1474 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk); base 1480 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 7, base 1483 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 6, base 1488 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 9, base 1492 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 8, base 1496 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 4, WM5100_AIF1_RATE_MASK, sr); base 1761 sound/soc/codecs/wm5100.c int ret, base, lock, i, timeout; base 1767 sound/soc/codecs/wm5100.c base = WM5100_FLL1_CONTROL_1 - 1; base 1772 sound/soc/codecs/wm5100.c base = WM5100_FLL2_CONTROL_2 - 1; base 1785 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, 0); base 1808 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, 0); base 1810 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 2, base 1814 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 3, WM5100_FLL1_THETA_MASK, base 1816 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 5, WM5100_FLL1_N_MASK, factors.n); base 1817 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 6, base 1822 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 7, WM5100_FLL1_LAMBDA_MASK, base 1830 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA); base 1887 sound/soc/codecs/wm5100.c .base = WM5100_AUDIO_IF_1_1 - 1, base 1907 sound/soc/codecs/wm5100.c .base = WM5100_AUDIO_IF_2_1 - 1, base 1927 sound/soc/codecs/wm5100.c .base = WM5100_AUDIO_IF_3_1 - 1, base 2304 sound/soc/codecs/wm5100.c wm5100->gpio_chip.base = wm5100->pdata.gpio_base; base 2306 sound/soc/codecs/wm5100.c wm5100->gpio_chip.base = -1; base 48 sound/soc/codecs/wm5102.c { .type = WMFW_ADSP2_PM, .base = 0x100000 }, base 49 sound/soc/codecs/wm5102.c { .type = WMFW_ADSP2_ZM, .base = 0x180000 }, base 50 sound/soc/codecs/wm5102.c { .type = WMFW_ADSP2_XM, .base = 0x190000 }, base 51 sound/soc/codecs/wm5102.c { .type = WMFW_ADSP2_YM, .base = 0x1a8000 }, base 742 sound/soc/codecs/wm5102.c #define WM5102_NG_SRC(name, base) \ base 743 sound/soc/codecs/wm5102.c SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ base 744 sound/soc/codecs/wm5102.c SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ base 745 sound/soc/codecs/wm5102.c SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \ base 746 sound/soc/codecs/wm5102.c SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \ base 747 sound/soc/codecs/wm5102.c SOC_SINGLE(name " NG EPOUT Switch", base, 4, 1, 0), \ base 748 sound/soc/codecs/wm5102.c SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ base 749 sound/soc/codecs/wm5102.c SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \ base 750 sound/soc/codecs/wm5102.c SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ base 751 sound/soc/codecs/wm5102.c SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0) base 1769 sound/soc/codecs/wm5102.c .base = ARIZONA_AIF1_BCLK_CTRL, base 1791 sound/soc/codecs/wm5102.c .base = ARIZONA_AIF2_BCLK_CTRL, base 1813 sound/soc/codecs/wm5102.c .base = ARIZONA_AIF3_BCLK_CTRL, base 2053 sound/soc/codecs/wm5102.c wm5102->core.adsp[0].base = ARIZONA_DSP1_CONTROL_1; base 49 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_PM, .base = 0x100000 }, base 50 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_ZM, .base = 0x180000 }, base 51 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_XM, .base = 0x190000 }, base 52 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_YM, .base = 0x1a8000 }, base 56 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_PM, .base = 0x200000 }, base 57 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_ZM, .base = 0x280000 }, base 58 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_XM, .base = 0x290000 }, base 59 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_YM, .base = 0x2a8000 }, base 63 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_PM, .base = 0x300000 }, base 64 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_ZM, .base = 0x380000 }, base 65 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_XM, .base = 0x390000 }, base 66 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_YM, .base = 0x3a8000 }, base 70 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_PM, .base = 0x400000 }, base 71 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_ZM, .base = 0x480000 }, base 72 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_XM, .base = 0x490000 }, base 73 sound/soc/codecs/wm5110.c { .type = WMFW_ADSP2_YM, .base = 0x4a8000 }, base 588 sound/soc/codecs/wm5110.c #define WM5110_NG_SRC(name, base) \ base 589 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ base 590 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ base 591 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \ base 592 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \ base 593 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \ base 594 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \ base 595 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ base 596 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \ base 597 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ base 598 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0), \ base 599 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG SPKDAT2L Switch", base, 10, 1, 0), \ base 600 sound/soc/codecs/wm5110.c SOC_SINGLE(name " NG SPKDAT2R Switch", base, 11, 1, 0) base 2076 sound/soc/codecs/wm5110.c .base = ARIZONA_AIF1_BCLK_CTRL, base 2098 sound/soc/codecs/wm5110.c .base = ARIZONA_AIF2_BCLK_CTRL, base 2120 sound/soc/codecs/wm5110.c .base = ARIZONA_AIF3_BCLK_CTRL, base 2416 sound/soc/codecs/wm5110.c wm5110->core.adsp[i].base = ARIZONA_DSP1_CONTROL_1 base 1860 sound/soc/codecs/wm8903.c wm8903->gpio_chip.base = pdata->gpio_base; base 1862 sound/soc/codecs/wm8903.c wm8903->gpio_chip.base = -1; base 3377 sound/soc/codecs/wm8962.c wm8962->gpio_chip.base = pdata->gpio_base; base 3379 sound/soc/codecs/wm8962.c wm8962->gpio_chip.base = -1; base 323 sound/soc/codecs/wm8994.c int base = wm8994_drc_base[drc]; base 328 sound/soc/codecs/wm8994.c save = snd_soc_component_read32(component, base); base 333 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, base + i, 0xffff, base 336 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_DRC_ENA | base 395 sound/soc/codecs/wm8994.c int base = wm8994_retune_mobile_base[block]; base 438 sound/soc/codecs/wm8994.c save = snd_soc_component_read32(component, base); base 442 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, base + i, 0xffff, base 445 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_EQ_ENA, save); base 338 sound/soc/codecs/wm8996.c int base, best, best_val, save, i, cfg, iface; base 345 sound/soc/codecs/wm8996.c base = WM8996_DSP1_RX_EQ_GAINS_1; base 353 sound/soc/codecs/wm8996.c base = WM8996_DSP1_RX_EQ_GAINS_2; base 389 sound/soc/codecs/wm8996.c save = snd_soc_component_read32(component, base); base 393 sound/soc/codecs/wm8996.c snd_soc_component_update_bits(component, base + i, 0xffff, base 396 sound/soc/codecs/wm8996.c snd_soc_component_update_bits(component, base, WM8996_DSP1RX_EQ_ENA, save); base 2202 sound/soc/codecs/wm8996.c wm8996->gpio_chip.base = wm8996->pdata.gpio_base; base 2204 sound/soc/codecs/wm8996.c wm8996->gpio_chip.base = -1; base 137 sound/soc/codecs/wm8997.c #define WM8997_NG_SRC(name, base) \ base 138 sound/soc/codecs/wm8997.c SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ base 139 sound/soc/codecs/wm8997.c SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ base 140 sound/soc/codecs/wm8997.c SOC_SINGLE(name " NG EPOUT Switch", base, 4, 1, 0), \ base 141 sound/soc/codecs/wm8997.c SOC_SINGLE(name " NG SPKOUT Switch", base, 6, 1, 0), \ base 142 sound/soc/codecs/wm8997.c SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ base 143 sound/soc/codecs/wm8997.c SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0) base 956 sound/soc/codecs/wm8997.c .base = ARIZONA_AIF1_BCLK_CTRL, base 978 sound/soc/codecs/wm8997.c .base = ARIZONA_AIF2_BCLK_CTRL, base 186 sound/soc/codecs/wm8998.c #define WM8998_NG_SRC(name, base) \ base 187 sound/soc/codecs/wm8998.c SOC_SINGLE(name " NG HPOUTL Switch", base, 0, 1, 0), \ base 188 sound/soc/codecs/wm8998.c SOC_SINGLE(name " NG HPOUTR Switch", base, 1, 1, 0), \ base 189 sound/soc/codecs/wm8998.c SOC_SINGLE(name " NG LINEOUTL Switch", base, 2, 1, 0), \ base 190 sound/soc/codecs/wm8998.c SOC_SINGLE(name " NG LINEOUTR Switch", base, 3, 1, 0), \ base 191 sound/soc/codecs/wm8998.c SOC_SINGLE(name " NG EPOUT Switch", base, 4, 1, 0), \ base 192 sound/soc/codecs/wm8998.c SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ base 193 sound/soc/codecs/wm8998.c SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0) base 1148 sound/soc/codecs/wm8998.c .base = ARIZONA_AIF1_BCLK_CTRL, base 1170 sound/soc/codecs/wm8998.c .base = ARIZONA_AIF2_BCLK_CTRL, base 1192 sound/soc/codecs/wm8998.c .base = ARIZONA_AIF3_BCLK_CTRL, base 843 sound/soc/codecs/wm_adsp.c return mem->base + (offset * 3); base 848 sound/soc/codecs/wm_adsp.c return mem->base + (offset * 2); base 861 sound/soc/codecs/wm_adsp.c return mem->base + (offset * 4); base 864 sound/soc/codecs/wm_adsp.c return (mem->base + (offset * 3)) & ~0x3; base 866 sound/soc/codecs/wm_adsp.c return mem->base + (offset * 5); base 880 sound/soc/codecs/wm_adsp.c ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]); base 941 sound/soc/codecs/wm_adsp.c *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset); base 2007 sound/soc/codecs/wm_adsp.c ctl->alg_region.base = alg_region->base; base 2079 sound/soc/codecs/wm_adsp.c __be32 base) base 2089 sound/soc/codecs/wm_adsp.c alg_region->base = be32_to_cpu(base); base 2139 sound/soc/codecs/wm_adsp.c int *type, __be32 *base) base 2145 sound/soc/codecs/wm_adsp.c alg_region = wm_adsp_create_region(dsp, type[i], id, base[i]); base 2167 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id, base 2268 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id, base 2408 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id, base 2577 sound/soc/codecs/wm_adsp.c reg = alg_region->base; base 2715 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, base 2733 sound/soc/codecs/wm_adsp.c dsp->base + ADSP1_CONTROL_31, base 2767 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, base 2779 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, base 2782 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, base 2785 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, base 2804 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, base 2820 sound/soc/codecs/wm_adsp.c ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); base 2844 sound/soc/codecs/wm_adsp.c ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL, base 2861 sound/soc/codecs/wm_adsp.c lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0; base 2884 sound/soc/codecs/wm_adsp.c return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, base 2890 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, base 2896 sound/soc/codecs/wm_adsp.c regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); base 2897 sound/soc/codecs/wm_adsp.c regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); base 2898 sound/soc/codecs/wm_adsp.c regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); base 2900 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, base 2906 sound/soc/codecs/wm_adsp.c regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); base 2907 sound/soc/codecs/wm_adsp.c regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); base 2908 sound/soc/codecs/wm_adsp.c regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); base 2971 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 }, base 2972 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA }, base 2973 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF }, base 2974 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF }, base 2975 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions }, base 2976 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions }, base 2977 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions }, base 2978 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF }, base 2979 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF }, base 2980 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions }, base 2981 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions }, base 2982 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions }, base 2983 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF }, base 2984 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF }, base 2985 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions }, base 2986 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions }, base 2987 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions }, base 2988 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF }, base 2989 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF }, base 2990 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions }, base 2991 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions }, base 2992 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions }, base 2993 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_LOCK_CONFIG, 0 }, base 3006 sound/soc/codecs/wm_adsp.c ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING, base 3061 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG, base 3067 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL, base 3115 sound/soc/codecs/wm_adsp.c return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, base 3122 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, base 3230 sound/soc/codecs/wm_adsp.c dsp->base + HALO_CCM_CORE_CONTROL, base 3236 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, base 3240 sound/soc/codecs/wm_adsp.c regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET, base 3281 sound/soc/codecs/wm_adsp.c ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, base 3711 sound/soc/codecs/wm_adsp.c addr = alg_region->base + xmalg + ALG_XM_FIELD(magic); base 3719 sound/soc/codecs/wm_adsp.c addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr); base 4258 sound/soc/codecs/wm_adsp.c ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); base 4277 sound/soc/codecs/wm_adsp.c ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); base 4289 sound/soc/codecs/wm_adsp.c dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, base 4305 sound/soc/codecs/wm_adsp.c regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, base 4321 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 }, base 4322 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 }, base 4323 sound/soc/codecs/wm_adsp.c { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 }, base 4350 sound/soc/codecs/wm_adsp.c ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR, base 42 sound/soc/codecs/wm_adsp.h unsigned int base; base 49 sound/soc/codecs/wm_adsp.h unsigned int base; base 69 sound/soc/codecs/wm_adsp.h unsigned int base; base 901 sound/soc/fsl/fsl_sai.c void __iomem *base; base 916 sound/soc/fsl/fsl_sai.c base = devm_ioremap_resource(&pdev->dev, res); base 917 sound/soc/fsl/fsl_sai.c if (IS_ERR(base)) base 918 sound/soc/fsl/fsl_sai.c return PTR_ERR(base); base 927 sound/soc/fsl/fsl_sai.c "bus", base, &fsl_sai_regmap_config); base 932 sound/soc/fsl/fsl_sai.c "sai", base, &fsl_sai_regmap_config); base 1344 sound/soc/fsl/fsl_ssi.c ssi->fiq_params.base = iomem; base 361 sound/soc/fsl/imx-pcm-fiq.c imx_ssi_fiq_base = (unsigned long)params->base; base 35 sound/soc/fsl/imx-pcm.h void __iomem *base; base 60 sound/soc/fsl/imx-ssi.c sccr = readl(ssi->base + SSI_STCCR); base 63 sound/soc/fsl/imx-ssi.c writel(sccr, ssi->base + SSI_STCCR); base 65 sound/soc/fsl/imx-ssi.c sccr = readl(ssi->base + SSI_SRCCR); base 68 sound/soc/fsl/imx-ssi.c writel(sccr, ssi->base + SSI_SRCCR); base 70 sound/soc/fsl/imx-ssi.c writel(~tx_mask, ssi->base + SSI_STMSK); base 71 sound/soc/fsl/imx-ssi.c writel(~rx_mask, ssi->base + SSI_SRMSK); base 85 sound/soc/fsl/imx-ssi.c scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET); base 145 sound/soc/fsl/imx-ssi.c writel(strcr, ssi->base + SSI_STCR); base 146 sound/soc/fsl/imx-ssi.c writel(strcr, ssi->base + SSI_SRCR); base 147 sound/soc/fsl/imx-ssi.c writel(scr, ssi->base + SSI_SCR); base 162 sound/soc/fsl/imx-ssi.c scr = readl(ssi->base + SSI_SCR); base 175 sound/soc/fsl/imx-ssi.c writel(scr, ssi->base + SSI_SCR); base 190 sound/soc/fsl/imx-ssi.c stccr = readl(ssi->base + SSI_STCCR); base 191 sound/soc/fsl/imx-ssi.c srccr = readl(ssi->base + SSI_SRCCR); base 222 sound/soc/fsl/imx-ssi.c writel(stccr, ssi->base + SSI_STCCR); base 223 sound/soc/fsl/imx-ssi.c writel(srccr, ssi->base + SSI_SRCCR); base 248 sound/soc/fsl/imx-ssi.c sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK; base 263 sound/soc/fsl/imx-ssi.c writel(sccr, ssi->base + reg); base 275 sound/soc/fsl/imx-ssi.c scr = readl(ssi->base + SSI_SCR); base 276 sound/soc/fsl/imx-ssi.c sier = readl(ssi->base + SSI_SIER); base 323 sound/soc/fsl/imx-ssi.c writel(scr, ssi->base + SSI_SCR); base 325 sound/soc/fsl/imx-ssi.c writel(sier, ssi->base + SSI_SIER); base 348 sound/soc/fsl/imx-ssi.c writel(val, ssi->base + SSI_SFCSR); base 400 sound/soc/fsl/imx-ssi.c void __iomem *base = imx_ssi->base; base 402 sound/soc/fsl/imx-ssi.c writel(0x0, base + SSI_SCR); base 403 sound/soc/fsl/imx-ssi.c writel(0x0, base + SSI_STCR); base 404 sound/soc/fsl/imx-ssi.c writel(0x0, base + SSI_SRCR); base 406 sound/soc/fsl/imx-ssi.c writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR); base 411 sound/soc/fsl/imx-ssi.c SSI_SFCSR_TFWM1(8), base + SSI_SFCSR); base 413 sound/soc/fsl/imx-ssi.c writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR); base 414 sound/soc/fsl/imx-ssi.c writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR); base 416 sound/soc/fsl/imx-ssi.c writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR); base 417 sound/soc/fsl/imx-ssi.c writel(SSI_SOR_WAIT(3), base + SSI_SOR); base 421 sound/soc/fsl/imx-ssi.c base + SSI_SCR); base 423 sound/soc/fsl/imx-ssi.c writel(SSI_SACNT_DEFAULT, base + SSI_SACNT); base 424 sound/soc/fsl/imx-ssi.c writel(0xff, base + SSI_SACCDIS); base 425 sound/soc/fsl/imx-ssi.c writel(0x300, base + SSI_SACCEN); base 434 sound/soc/fsl/imx-ssi.c void __iomem *base = imx_ssi->base; base 444 sound/soc/fsl/imx-ssi.c writel(lreg, base + SSI_SACADD); base 447 sound/soc/fsl/imx-ssi.c writel(lval , base + SSI_SACDAT); base 449 sound/soc/fsl/imx-ssi.c writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT); base 457 sound/soc/fsl/imx-ssi.c void __iomem *base = imx_ssi->base; base 463 sound/soc/fsl/imx-ssi.c writel(lreg, base + SSI_SACADD); base 464 sound/soc/fsl/imx-ssi.c writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT); base 468 sound/soc/fsl/imx-ssi.c val = (readl(base + SSI_SACDAT) >> 4) & 0xffff; base 538 sound/soc/fsl/imx-ssi.c ssi->base = devm_ioremap_resource(&pdev->dev, res); base 539 sound/soc/fsl/imx-ssi.c if (IS_ERR(ssi->base)) { base 540 sound/soc/fsl/imx-ssi.c ret = PTR_ERR(ssi->base); base 556 sound/soc/fsl/imx-ssi.c writel(0x0, ssi->base + SSI_SIER); base 595 sound/soc/fsl/imx-ssi.c ssi->fiq_params.base = ssi->base; base 194 sound/soc/fsl/imx-ssi.h void __iomem *base; base 40 sound/soc/hisilicon/hi6210-i2s.c void __iomem *base; base 83 sound/soc/hisilicon/hi6210-i2s.c writel(val, i2s->base + reg); base 88 sound/soc/hisilicon/hi6210-i2s.c return readl(i2s->base + reg); base 558 sound/soc/hisilicon/hi6210-i2s.c i2s->base = devm_ioremap_resource(dev, res); base 559 sound/soc/hisilicon/hi6210-i2s.c if (IS_ERR(i2s->base)) base 560 sound/soc/hisilicon/hi6210-i2s.c return PTR_ERR(i2s->base); base 53 sound/soc/img/img-i2s-in.c void __iomem *base; base 90 sound/soc/img/img-i2s-in.c writel(val, i2s->base + reg); base 95 sound/soc/img/img-i2s-in.c return readl(i2s->base + reg); base 421 sound/soc/img/img-i2s-in.c void __iomem *base; base 436 sound/soc/img/img-i2s-in.c base = devm_ioremap_resource(dev, res); base 437 sound/soc/img/img-i2s-in.c if (IS_ERR(base)) base 438 sound/soc/img/img-i2s-in.c return PTR_ERR(base); base 440 sound/soc/img/img-i2s-in.c i2s->base = base; base 450 sound/soc/img/img-i2s-in.c i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20); base 52 sound/soc/img/img-i2s-out.c void __iomem *base; base 101 sound/soc/img/img-i2s-out.c writel(val, i2s->base + reg); base 106 sound/soc/img/img-i2s-out.c return readl(i2s->base + reg); base 427 sound/soc/img/img-i2s-out.c void __iomem *base; base 442 sound/soc/img/img-i2s-out.c base = devm_ioremap_resource(&pdev->dev, res); base 443 sound/soc/img/img-i2s-out.c if (IS_ERR(base)) base 444 sound/soc/img/img-i2s-out.c return PTR_ERR(base); base 446 sound/soc/img/img-i2s-out.c i2s->base = base; base 456 sound/soc/img/img-i2s-out.c i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20); base 36 sound/soc/img/img-parallel-out.c void __iomem *base; base 70 sound/soc/img/img-parallel-out.c writel(val, prl->base + reg); base 75 sound/soc/img/img-parallel-out.c return readl(prl->base + reg); base 211 sound/soc/img/img-parallel-out.c void __iomem *base; base 224 sound/soc/img/img-parallel-out.c base = devm_ioremap_resource(&pdev->dev, res); base 225 sound/soc/img/img-parallel-out.c if (IS_ERR(base)) base 226 sound/soc/img/img-parallel-out.c return PTR_ERR(base); base 228 sound/soc/img/img-parallel-out.c prl->base = base; base 72 sound/soc/img/img-spdif-in.c void __iomem *base; base 116 sound/soc/img/img-spdif-in.c writel(val, spdif->base + reg); base 121 sound/soc/img/img-spdif-in.c return readl(spdif->base + reg); base 721 sound/soc/img/img-spdif-in.c void __iomem *base; base 736 sound/soc/img/img-spdif-in.c base = devm_ioremap_resource(&pdev->dev, res); base 737 sound/soc/img/img-spdif-in.c if (IS_ERR(base)) base 738 sound/soc/img/img-spdif-in.c return PTR_ERR(base); base 740 sound/soc/img/img-spdif-in.c spdif->base = base; base 41 sound/soc/img/img-spdif-out.c void __iomem *base; base 86 sound/soc/img/img-spdif-out.c writel(val, spdif->base + reg); base 91 sound/soc/img/img-spdif-out.c return readl(spdif->base + reg); base 326 sound/soc/img/img-spdif-out.c void __iomem *base; base 339 sound/soc/img/img-spdif-out.c base = devm_ioremap_resource(&pdev->dev, res); base 340 sound/soc/img/img-spdif-out.c if (IS_ERR(base)) base 341 sound/soc/img/img-spdif-out.c return PTR_ERR(base); base 343 sound/soc/img/img-spdif-out.c spdif->base = base; base 98 sound/soc/jz4740/jz4740-i2s.c void __iomem *base; base 113 sound/soc/jz4740/jz4740-i2s.c return readl(i2s->base + reg); base 119 sound/soc/jz4740/jz4740-i2s.c writel(value, i2s->base + reg); base 511 sound/soc/jz4740/jz4740-i2s.c i2s->base = devm_ioremap_resource(&pdev->dev, mem); base 512 sound/soc/jz4740/jz4740-i2s.c if (IS_ERR(i2s->base)) base 513 sound/soc/jz4740/jz4740-i2s.c return PTR_ERR(i2s->base); base 77 sound/soc/kirkwood/kirkwood-dma.c kirkwood_dma_conf_mbus_windows(void __iomem *base, int win, base 84 sound/soc/kirkwood/kirkwood-dma.c writel(0, base + KIRKWOOD_AUDIO_WIN_CTRL_REG(win)); base 85 sound/soc/kirkwood/kirkwood-dma.c writel(0, base + KIRKWOOD_AUDIO_WIN_BASE_REG(win)); base 90 sound/soc/kirkwood/kirkwood-dma.c if ((cs->base & 0xffff0000) < (dma & 0xffff0000)) { base 91 sound/soc/kirkwood/kirkwood-dma.c writel(cs->base & 0xffff0000, base 92 sound/soc/kirkwood/kirkwood-dma.c base + KIRKWOOD_AUDIO_WIN_BASE_REG(win)); base 96 sound/soc/kirkwood/kirkwood-dma.c base + KIRKWOOD_AUDIO_WIN_CTRL_REG(win)); base 102 sound/soc/mxs/mxs-saif.c scr = __raw_readl(master_saif->base + SAIF_CTRL); base 155 sound/soc/mxs/mxs-saif.c __raw_writel(scr, master_saif->base + SAIF_CTRL); base 197 sound/soc/mxs/mxs-saif.c __raw_writel(scr, master_saif->base + SAIF_CTRL); base 213 sound/soc/mxs/mxs-saif.c stat = __raw_readl(saif->base + SAIF_STAT); base 223 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_SET_ADDR); base 225 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_CLR_ADDR); base 251 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_CLR_ADDR); base 255 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_CLR_ADDR); base 263 sound/soc/mxs/mxs-saif.c stat = __raw_readl(saif->base + SAIF_STAT); base 280 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_SET_ADDR); base 296 sound/soc/mxs/mxs-saif.c stat = __raw_readl(saif->base + SAIF_STAT); base 307 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_CLR_ADDR); base 309 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_CLR_ADDR); base 312 sound/soc/mxs/mxs-saif.c scr0 = __raw_readl(saif->base + SAIF_CTRL); base 368 sound/soc/mxs/mxs-saif.c __raw_writel(scr | scr0, saif->base + SAIF_CTRL); base 389 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_CLR_ADDR); base 393 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_CLR_ADDR); base 433 sound/soc/mxs/mxs-saif.c stat = __raw_readl(saif->base + SAIF_STAT); base 469 sound/soc/mxs/mxs-saif.c scr = __raw_readl(saif->base + SAIF_CTRL); base 498 sound/soc/mxs/mxs-saif.c __raw_writel(scr, saif->base + SAIF_CTRL); base 509 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_SET_ADDR); base 554 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_SET_ADDR); base 559 sound/soc/mxs/mxs-saif.c master_saif->base + SAIF_CTRL + MXS_SET_ADDR); base 569 sound/soc/mxs/mxs-saif.c __raw_writel(0, saif->base + SAIF_DATA); base 570 sound/soc/mxs/mxs-saif.c __raw_writel(0, saif->base + SAIF_DATA); base 579 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_DATA); base 580 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_DATA); base 587 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_CTRL), base 588 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_STAT)); base 591 sound/soc/mxs/mxs-saif.c __raw_readl(master_saif->base + SAIF_CTRL), base 592 sound/soc/mxs/mxs-saif.c __raw_readl(master_saif->base + SAIF_STAT)); base 607 sound/soc/mxs/mxs-saif.c master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); base 614 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL + MXS_CLR_ADDR); base 681 sound/soc/mxs/mxs-saif.c stat = __raw_readl(saif->base + SAIF_STAT); base 689 sound/soc/mxs/mxs-saif.c saif->base + SAIF_STAT + MXS_CLR_ADDR); base 695 sound/soc/mxs/mxs-saif.c saif->base + SAIF_STAT + MXS_CLR_ADDR); base 699 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_CTRL), base 700 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_STAT)); base 714 sound/soc/mxs/mxs-saif.c saif->base + SAIF_CTRL, base 788 sound/soc/mxs/mxs-saif.c saif->base = devm_platform_ioremap_resource(pdev, 0); base 789 sound/soc/mxs/mxs-saif.c if (IS_ERR(saif->base)) base 790 sound/soc/mxs/mxs-saif.c return PTR_ERR(saif->base); base 105 sound/soc/mxs/mxs-saif.h void __iomem *base; base 620 sound/soc/samsung/s3c-i2s-v2.c unsigned long base) base 65 sound/soc/samsung/s3c-i2s-v2.h unsigned long base; base 87 sound/soc/samsung/s3c-i2s-v2.h unsigned long base); base 248 sound/soc/sh/fsi.c void __iomem *base; base 293 sound/soc/sh/fsi.c void __iomem *base; base 335 sound/soc/sh/fsi.c __fsi_reg_write((p->base + REG_##r), d) base 338 sound/soc/sh/fsi.c __fsi_reg_read((p->base + REG_##r)) base 341 sound/soc/sh/fsi.c __fsi_reg_mask_set((p->base + REG_##r), m, d) base 351 sound/soc/sh/fsi.c ret = __fsi_reg_read(master->base + reg); base 365 sound/soc/sh/fsi.c __fsi_reg_mask_set(master->base + reg, mask, data); base 389 sound/soc/sh/fsi.c return fsi->master->base == fsi->base; base 1957 sound/soc/sh/fsi.c master->base = devm_ioremap_nocache(&pdev->dev, base 1959 sound/soc/sh/fsi.c if (!master->base) { base 1970 sound/soc/sh/fsi.c fsi->base = master->base; base 1983 sound/soc/sh/fsi.c fsi->base = master->base + 0x40; base 47 sound/soc/sh/rcar/dma.c void __iomem *base; base 392 sound/soc/sh/rcar/dma.c (dmac->base + 0x20 + reg + \ base 841 sound/soc/sh/rcar/dma.c dmac->base = devm_ioremap_resource(dev, res); base 842 sound/soc/sh/rcar/dma.c if (IS_ERR(dmac->base)) base 843 sound/soc/sh/rcar/dma.c return PTR_ERR(dmac->base); base 24 sound/soc/sh/rcar/gen.c void __iomem *base[RSND_BASE_MAX]; base 161 sound/soc/sh/rcar/gen.c void __iomem *base; base 176 sound/soc/sh/rcar/gen.c base = devm_ioremap_resource(dev, res); base 177 sound/soc/sh/rcar/gen.c if (IS_ERR(base)) base 178 sound/soc/sh/rcar/gen.c return PTR_ERR(base); base 180 sound/soc/sh/rcar/gen.c regmap = devm_regmap_init_mmio(dev, base, ®c); base 185 sound/soc/sh/rcar/gen.c gen->base[reg_id] = base; base 97 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; base 102 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SRCTL, 0); base 111 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SRCTL, 0x301); base 114 sound/soc/sh/siu_dai.c siu_write32(base + SIU_CKCTL, 0x40400000); base 117 sound/soc/sh/siu_dai.c siu_write32(base + SIU_BRGASEL, 0); base 118 sound/soc/sh/siu_dai.c siu_write32(base + SIU_BRRA, 0); base 121 sound/soc/sh/siu_dai.c siu_write32(base + SIU_BRGBSEL, 1); base 122 sound/soc/sh/siu_dai.c siu_write32(base + SIU_BRRB, 0); base 124 sound/soc/sh/siu_dai.c siu_write32(base + SIU_IFCTL, 0x44440000); base 127 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SFORM, 0x0c0c0000); base 133 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SBDVCA, port_info->playback.volume); base 134 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SBDVCB, port_info->capture.volume); base 140 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; base 143 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SRCTL, 0); base 194 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; base 197 sound/soc/sh/siu_dai.c srctl = siu_read32(base + SIU_SRCTL); base 198 sound/soc/sh/siu_dai.c ifctl = siu_read32(base + SIU_IFCTL); base 213 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SRCTL, srctl); base 215 sound/soc/sh/siu_dai.c siu_write32(base + SIU_IFCTL, ifctl); base 225 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; base 228 sound/soc/sh/siu_dai.c dpak = siu_read32(base + SIU_DPAK); base 239 sound/soc/sh/siu_dai.c siu_write32(base + SIU_DPAK, dpak); base 245 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; base 283 sound/soc/sh/siu_dai.c siu_write32(base + SIU_TRDAT, port_info->trdat); base 288 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SBACTIV, 0); base 290 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SBCTL, 0xc0000000); base 293 sound/soc/sh/siu_dai.c while (--cnt && siu_read32(base + SIU_SBCTL) != 0x80000000) base 300 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SBPSET, 0x00400000); base 302 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SBACTIV, 0xc0000000); base 310 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; base 312 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SBACTIV, 0); base 314 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SBCTL, 0); base 389 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; base 409 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SBDVCA, new_vol); base 415 sound/soc/sh/siu_dai.c siu_write32(base + SIU_SBDVCB, new_vol); base 593 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; base 619 sound/soc/sh/siu_dai.c siu_read32(base + SIU_IFCTL); base 620 sound/soc/sh/siu_dai.c siu_write32(base + SIU_IFCTL, ifctl); base 40 sound/soc/sh/siu_pcm.c u32 __iomem *base = info->reg; base 48 sound/soc/sh/siu_pcm.c stfifo = siu_read32(base + SIU_STFIFO); base 49 sound/soc/sh/siu_pcm.c siu_write32(base + SIU_STFIFO, stfifo & ~0x0c180c18); base 106 sound/soc/sh/siu_pcm.c u32 __iomem *base = info->reg; base 142 sound/soc/sh/siu_pcm.c stfifo = siu_read32(base + SIU_STFIFO); base 143 sound/soc/sh/siu_pcm.c siu_write32(base + SIU_STFIFO, stfifo | (port_info->stfifo & 0x0c180c18)); base 154 sound/soc/sh/siu_pcm.c u32 __iomem *base = info->reg; base 192 sound/soc/sh/siu_pcm.c stfifo = siu_read32(base + SIU_STFIFO); base 193 sound/soc/sh/siu_pcm.c siu_write32(base + SIU_STFIFO, siu_read32(base + SIU_STFIFO) | base 264 sound/soc/sh/siu_pcm.c u32 __iomem *base = info->reg; base 273 sound/soc/sh/siu_pcm.c stfifo = siu_read32(base + SIU_STFIFO); base 274 sound/soc/sh/siu_pcm.c siu_write32(base + SIU_STFIFO, stfifo & ~0x13071307); base 484 sound/soc/sh/siu_pcm.c u32 __iomem *base = info->reg; base 505 sound/soc/sh/siu_pcm.c __func__, info->port_id, siu_read32(base + SIU_EVNTC), base 506 sound/soc/sh/siu_pcm.c siu_read32(base + SIU_SBFSTS), ptr, siu_stream->buf_bytes, base 361 sound/soc/sirf/sirf-usp.c void __iomem *base; base 370 sound/soc/sirf/sirf-usp.c base = devm_platform_ioremap_resource(pdev, 0); base 371 sound/soc/sirf/sirf-usp.c if (IS_ERR(base)) base 372 sound/soc/sirf/sirf-usp.c return PTR_ERR(base); base 373 sound/soc/sirf/sirf-usp.c usp->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 143 sound/soc/soc-ac97.c gpio_priv->gpio_chip.base = -1; base 643 sound/soc/soc-ops.c ret = regmap_raw_read(component->regmap, params->base, base 696 sound/soc/soc-ops.c ret = regmap_read(component->regmap, params->base, &val); base 745 sound/soc/soc-ops.c ret = regmap_raw_write(component->regmap, params->base, base 334 sound/soc/sof/debug.c void __iomem *base, size_t size, base 348 sound/soc/sof/debug.c dfse->io_mem = base; base 377 sound/soc/sof/debug.c void *base, size_t size, base 390 sound/soc/sof/debug.c dfse->buf = base; base 190 sound/soc/sof/imx/imx8.c u32 base, size; base 266 sound/soc/sof/imx/imx8.c base = mmio->start; base 274 sound/soc/sof/imx/imx8.c sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size); base 277 sound/soc/sof/imx/imx8.c base, size); base 301 sound/soc/sof/imx/imx8.c base, size); base 432 sound/soc/sof/intel/bdw.c u32 base, size; base 439 sound/soc/sof/intel/bdw.c base = mmio->start; base 447 sound/soc/sof/intel/bdw.c dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); base 448 sound/soc/sof/intel/bdw.c sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size); base 452 sound/soc/sof/intel/bdw.c base, size); base 466 sound/soc/sof/intel/bdw.c base = mmio->start; base 474 sound/soc/sof/intel/bdw.c dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size); base 475 sound/soc/sof/intel/bdw.c sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size); base 479 sound/soc/sof/intel/bdw.c base, size); base 398 sound/soc/sof/intel/byt.c u32 base, size; base 409 sound/soc/sof/intel/byt.c base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET; base 412 sound/soc/sof/intel/byt.c dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); base 413 sound/soc/sof/intel/byt.c sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); base 416 sound/soc/sof/intel/byt.c base, size); base 425 sound/soc/sof/intel/byt.c base = pci_resource_start(pci, desc->resindex_imr_base); base 429 sound/soc/sof/intel/byt.c if (base == 0x55aa55aa || base == 0x0) { base 434 sound/soc/sof/intel/byt.c dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); base 435 sound/soc/sof/intel/byt.c sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); base 438 sound/soc/sof/intel/byt.c base, size); base 535 sound/soc/sof/intel/byt.c u32 base, size; base 549 sound/soc/sof/intel/byt.c base = mmio->start; base 557 sound/soc/sof/intel/byt.c dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size); base 558 sound/soc/sof/intel/byt.c sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size); base 561 sound/soc/sof/intel/byt.c base, size); base 577 sound/soc/sof/intel/byt.c base = mmio->start; base 586 sound/soc/sof/intel/byt.c if (base == 0x55aa55aa || base == 0x0) { base 591 sound/soc/sof/intel/byt.c dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size); base 592 sound/soc/sof/intel/byt.c sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size); base 595 sound/soc/sof/intel/byt.c base, size); base 573 sound/soc/sof/sof-priv.h void __iomem *base, size_t size, base 577 sound/soc/sof/sof-priv.h void *base, size_t size, base 110 sound/soc/sprd/sprd-mcdt.c void __iomem *base; base 121 sound/soc/sprd/sprd-mcdt.c u32 orig = readl_relaxed(mcdt->base + reg); base 125 sound/soc/sprd/sprd-mcdt.c writel_relaxed(tmp, mcdt->base + reg); base 187 sound/soc/sprd/sprd-mcdt.c writel_relaxed(val, mcdt->base + reg); base 195 sound/soc/sprd/sprd-mcdt.c *val = readl_relaxed(mcdt->base + reg); base 385 sound/soc/sprd/sprd-mcdt.c return !!(readl_relaxed(mcdt->base + reg) & BIT(shift)); base 403 sound/soc/sprd/sprd-mcdt.c u32 r_addr = (readl_relaxed(mcdt->base + reg) >> base 405 sound/soc/sprd/sprd-mcdt.c u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK; base 416 sound/soc/sprd/sprd-mcdt.c u32 r_addr = (readl_relaxed(mcdt->base + reg) >> base 418 sound/soc/sprd/sprd-mcdt.c u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK; base 519 sound/soc/sprd/sprd-mcdt.c return !!(readl_relaxed(mcdt->base + reg) & BIT(shift)); base 953 sound/soc/sprd/sprd-mcdt.c mcdt->base = devm_ioremap_resource(&pdev->dev, res); base 954 sound/soc/sprd/sprd-mcdt.c if (IS_ERR(mcdt->base)) base 955 sound/soc/sprd/sprd-mcdt.c return PTR_ERR(mcdt->base); base 420 sound/soc/sti/sti_uniperif.c uni->base = devm_ioremap_resource(dev, uni->mem_region); base 422 sound/soc/sti/sti_uniperif.c if (IS_ERR(uni->base)) base 423 sound/soc/sti/sti_uniperif.c return PTR_ERR(uni->base); base 20 sound/soc/sti/uniperif.h ((readl_relaxed(ip->base + offset) >> shift) & mask) base 22 sound/soc/sti/uniperif.h writel_relaxed(((readl_relaxed(ip->base + offset) & \ base 23 sound/soc/sti/uniperif.h ~(mask << shift)) | (((value) & mask) << shift)), ip->base + offset) base 25 sound/soc/sti/uniperif.h writel_relaxed((((value) & mask) << shift), ip->base + offset) base 34 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_SOFT_RST_OFFSET(ip)) : 0) base 36 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_SOFT_RST_OFFSET(ip)) base 58 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_FIFO_DATA_OFFSET(ip)) base 66 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_CHANNEL_STA_REGN(ip, n)) base 68 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + \ base 73 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_CHANNEL_STA_REG0_OFFSET(ip)) base 75 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG0_OFFSET(ip)) base 79 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_CHANNEL_STA_REG1_OFFSET(ip)) base 81 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG1_OFFSET(ip)) base 85 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_CHANNEL_STA_REG2_OFFSET(ip)) base 87 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG2_OFFSET(ip)) base 91 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_CHANNEL_STA_REG3_OFFSET(ip)) base 93 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG3_OFFSET(ip)) base 97 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_CHANNEL_STA_REG4_OFFSET(ip)) base 99 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG4_OFFSET(ip)) base 103 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_CHANNEL_STA_REG5_OFFSET(ip)) base 105 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG5_OFFSET(ip)) base 113 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_ITS_OFFSET(ip)) base 160 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_ITS_BCLR_OFFSET(ip)) base 168 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_ITM_OFFSET(ip)) base 196 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_ITM_BCLR_OFFSET(ip)) base 221 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_ITM_BSET_OFFSET(ip)) base 274 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_CONFIG_OFFSET(ip)) base 276 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_CONFIG_OFFSET(ip)) base 546 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_CTRL_OFFSET(ip)) base 548 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_CTRL_OFFSET(ip)) base 792 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_I2S_FMT_OFFSET(ip)) base 794 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_I2S_FMT_OFFSET(ip)) base 991 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_BIT_CONTROL_OFFSET(ip)) base 993 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_BIT_CONTROL_OFFSET(ip)) base 1029 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_STATUS_1_OFFSET(ip)) base 1031 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_STATUS_1_OFFSET(ip)) base 1054 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_CHANNEL_STA_REGN(ip, n)) base 1056 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + \ base 1065 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_USER_VALIDITY_OFFSET(ip)) base 1067 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_USER_VALIDITY_OFFSET(ip)) base 1108 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_TDM_ENABLE_OFFSET(ip)) base 1110 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + UNIPERIF_TDM_ENABLE_OFFSET(ip)) base 1136 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_TDM_FS_REF_FREQ_OFFSET(ip)) base 1138 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + \ base 1183 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_TDM_FS_REF_DIV_OFFSET(ip)) base 1185 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + \ base 1211 sound/soc/sti/uniperif.h readl_relaxed(ip->base + UNIPERIF_TDM_WORD_POS_##words##_OFFSET(ip)) base 1213 sound/soc/sti/uniperif.h writel_relaxed(value, ip->base + \ base 1309 sound/soc/sti/uniperif.h void __iomem *base; base 233 sound/soc/stm/stm32_i2s.c void __iomem *base; base 825 sound/soc/stm/stm32_i2s.c i2s->base = devm_ioremap_resource(&pdev->dev, res); base 826 sound/soc/stm/stm32_i2s.c if (IS_ERR(i2s->base)) base 827 sound/soc/stm/stm32_i2s.c return PTR_ERR(i2s->base); base 904 sound/soc/stm/stm32_i2s.c i2s->base, i2s->regmap_conf); base 77 sound/soc/stm/stm32_sai.c writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base); base 98 sound/soc/stm/stm32_sai.c prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base)); base 107 sound/soc/stm/stm32_sai.c writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base); base 163 sound/soc/stm/stm32_sai.c sai->base = devm_platform_ioremap_resource(pdev, 0); base 164 sound/soc/stm/stm32_sai.c if (IS_ERR(sai->base)) base 165 sound/soc/stm/stm32_sai.c return PTR_ERR(sai->base); base 215 sound/soc/stm/stm32_sai.c readl_relaxed(sai->base + STM_SAI_IDR)); base 217 sound/soc/stm/stm32_sai.c val = readl_relaxed(sai->base + STM_SAI_HWCFGR); base 222 sound/soc/stm/stm32_sai.c val = readl_relaxed(sai->base + STM_SAI_VERR); base 253 sound/soc/stm/stm32_sai.c sai->gcr = readl_relaxed(sai->base); base 268 sound/soc/stm/stm32_sai.c writel_relaxed(sai->gcr, sai->base); base 293 sound/soc/stm/stm32_sai.h void __iomem *base; base 1356 sound/soc/stm/stm32_sai_sub.c void __iomem *base; base 1364 sound/soc/stm/stm32_sai_sub.c base = devm_ioremap_resource(&pdev->dev, res); base 1365 sound/soc/stm/stm32_sai_sub.c if (IS_ERR(base)) base 1366 sound/soc/stm/stm32_sai_sub.c return PTR_ERR(base); base 1380 sound/soc/stm/stm32_sai_sub.c sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 230 sound/soc/stm/stm32_spdifrx.c void __iomem *base; base 910 sound/soc/stm/stm32_spdifrx.c spdifrx->base = devm_ioremap_resource(&pdev->dev, res); base 911 sound/soc/stm/stm32_spdifrx.c if (IS_ERR(spdifrx->base)) base 912 sound/soc/stm/stm32_spdifrx.c return PTR_ERR(spdifrx->base); base 953 sound/soc/stm/stm32_spdifrx.c spdifrx->base, base 1698 sound/soc/sunxi/sun4i-codec.c void __iomem *base; base 1708 sound/soc/sunxi/sun4i-codec.c base = devm_ioremap_resource(&pdev->dev, res); base 1709 sound/soc/sunxi/sun4i-codec.c if (IS_ERR(base)) { base 1711 sound/soc/sunxi/sun4i-codec.c return PTR_ERR(base); base 1720 sound/soc/sunxi/sun4i-codec.c scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 506 sound/soc/sunxi/sun4i-spdif.c void __iomem *base; base 522 sound/soc/sunxi/sun4i-spdif.c base = devm_ioremap_resource(&pdev->dev, res); base 523 sound/soc/sunxi/sun4i-spdif.c if (IS_ERR(base)) base 524 sound/soc/sunxi/sun4i-spdif.c return PTR_ERR(base); base 533 sound/soc/sunxi/sun4i-spdif.c host->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 463 sound/soc/sunxi/sun50i-codec-analog.c void __iomem *base; base 465 sound/soc/sunxi/sun50i-codec-analog.c base = devm_platform_ioremap_resource(pdev, 0); base 466 sound/soc/sunxi/sun50i-codec-analog.c if (IS_ERR(base)) { base 468 sound/soc/sunxi/sun50i-codec-analog.c return PTR_ERR(base); base 471 sound/soc/sunxi/sun50i-codec-analog.c regmap = sun8i_adda_pr_regmap_init(&pdev->dev, base); base 31 sound/soc/sunxi/sun8i-adda-pr-regmap.c void __iomem *base = (void __iomem *)context; base 35 sound/soc/sunxi/sun8i-adda-pr-regmap.c writel(readl(base) | ADDA_PR_RESET, base); base 38 sound/soc/sunxi/sun8i-adda-pr-regmap.c writel(readl(base) & ~ADDA_PR_WRITE, base); base 41 sound/soc/sunxi/sun8i-adda-pr-regmap.c tmp = readl(base); base 44 sound/soc/sunxi/sun8i-adda-pr-regmap.c writel(tmp, base); base 47 sound/soc/sunxi/sun8i-adda-pr-regmap.c *val = readl(base) & ADDA_PR_DATA_OUT_MASK; base 54 sound/soc/sunxi/sun8i-adda-pr-regmap.c void __iomem *base = (void __iomem *)context; base 58 sound/soc/sunxi/sun8i-adda-pr-regmap.c writel(readl(base) | ADDA_PR_RESET, base); base 61 sound/soc/sunxi/sun8i-adda-pr-regmap.c tmp = readl(base); base 64 sound/soc/sunxi/sun8i-adda-pr-regmap.c writel(tmp, base); base 67 sound/soc/sunxi/sun8i-adda-pr-regmap.c tmp = readl(base); base 70 sound/soc/sunxi/sun8i-adda-pr-regmap.c writel(tmp, base); base 73 sound/soc/sunxi/sun8i-adda-pr-regmap.c writel(readl(base) | ADDA_PR_WRITE, base); base 76 sound/soc/sunxi/sun8i-adda-pr-regmap.c writel(readl(base) & ~ADDA_PR_WRITE, base); base 93 sound/soc/sunxi/sun8i-adda-pr-regmap.c void __iomem *base) base 95 sound/soc/sunxi/sun8i-adda-pr-regmap.c return devm_regmap_init(dev, NULL, base, &adda_pr_regmap_cfg); base 7 sound/soc/sunxi/sun8i-adda-pr-regmap.h void __iomem *base); base 823 sound/soc/sunxi/sun8i-codec-analog.c void __iomem *base; base 825 sound/soc/sunxi/sun8i-codec-analog.c base = devm_platform_ioremap_resource(pdev, 0); base 826 sound/soc/sunxi/sun8i-codec-analog.c if (IS_ERR(base)) { base 828 sound/soc/sunxi/sun8i-codec-analog.c return PTR_ERR(base); base 831 sound/soc/sunxi/sun8i-codec-analog.c regmap = sun8i_adda_pr_regmap_init(&pdev->dev, base); base 538 sound/soc/sunxi/sun8i-codec.c void __iomem *base; base 559 sound/soc/sunxi/sun8i-codec.c base = devm_platform_ioremap_resource(pdev, 0); base 560 sound/soc/sunxi/sun8i-codec.c if (IS_ERR(base)) { base 562 sound/soc/sunxi/sun8i-codec.c return PTR_ERR(base); base 565 sound/soc/sunxi/sun8i-codec.c scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, base 132 sound/soc/ti/davinci-i2s.c void __iomem *base; base 169 sound/soc/ti/davinci-i2s.c __raw_writel(val, dev->base + reg); base 174 sound/soc/ti/davinci-i2s.c return __raw_readl(dev->base + reg); base 675 sound/soc/ti/davinci-i2s.c dev->base = io_base; base 78 sound/soc/ti/davinci-mcasp.c void __iomem *base; base 130 sound/soc/ti/davinci-mcasp.c void __iomem *reg = mcasp->base + offset; base 137 sound/soc/ti/davinci-mcasp.c void __iomem *reg = mcasp->base + offset; base 144 sound/soc/ti/davinci-mcasp.c void __iomem *reg = mcasp->base + offset; base 151 sound/soc/ti/davinci-mcasp.c __raw_writel(val, mcasp->base + offset); base 156 sound/soc/ti/davinci-mcasp.c return (u32)__raw_readl(mcasp->base + offset); base 2059 sound/soc/ti/davinci-mcasp.c .base = -1, base 2139 sound/soc/ti/davinci-mcasp.c mcasp->base = devm_ioremap_resource(&pdev->dev, mem); base 2140 sound/soc/ti/davinci-mcasp.c if (IS_ERR(mcasp->base)) base 2141 sound/soc/ti/davinci-mcasp.c return PTR_ERR(mcasp->base); base 51 sound/soc/ti/davinci-vcif.c w = readl(davinci_vc->base + DAVINCI_VC_CTRL); base 58 sound/soc/ti/davinci-vcif.c writel(w, davinci_vc->base + DAVINCI_VC_CTRL); base 70 sound/soc/ti/davinci-vcif.c w = readl(davinci_vc->base + DAVINCI_VC_CTRL); base 76 sound/soc/ti/davinci-vcif.c writel(w, davinci_vc->base + DAVINCI_VC_CTRL); base 92 sound/soc/ti/davinci-vcif.c writel(DAVINCI_VC_CTRL_MASK, davinci_vc->base + DAVINCI_VC_CTRL); base 94 sound/soc/ti/davinci-vcif.c writel(DAVINCI_VC_INT_MASK, davinci_vc->base + DAVINCI_VC_INTCLR); base 96 sound/soc/ti/davinci-vcif.c writel(DAVINCI_VC_INT_MASK, davinci_vc->base + DAVINCI_VC_INTEN); base 98 sound/soc/ti/davinci-vcif.c w = readl(davinci_vc->base + DAVINCI_VC_CTRL); base 126 sound/soc/ti/davinci-vcif.c writel(w, davinci_vc->base + DAVINCI_VC_CTRL); base 41 sound/soc/txx9/txx9aclc-ac97.c return __raw_readl(drvdata->base + ACINTSTS) & ACINT_REGACCRDY; base 49 sound/soc/txx9/txx9aclc-ac97.c void __iomem *base = drvdata->base; base 52 sound/soc/txx9/txx9aclc-ac97.c if (!(__raw_readl(base + ACINTSTS) & ACINT_CODECRDY(ac97->num))) base 56 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(dat, base + ACREGACC); base 57 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(ACINT_REGACCRDY, base + ACINTEN); base 59 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(ACINT_REGACCRDY, base + ACINTDIS); base 64 sound/soc/txx9/txx9aclc-ac97.c dat = __raw_readl(base + ACREGACC); base 73 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(ACINT_REGACCRDY, base + ACINTDIS); base 82 sound/soc/txx9/txx9aclc-ac97.c void __iomem *base = drvdata->base; base 86 sound/soc/txx9/txx9aclc-ac97.c base + ACREGACC); base 87 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(ACINT_REGACCRDY, base + ACINTEN); base 92 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(ACINT_REGACCRDY, base + ACINTDIS); base 98 sound/soc/txx9/txx9aclc-ac97.c void __iomem *base = drvdata->base; base 101 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(ACCTL_ENLINK, base + ACCTLDIS); base 103 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(ACCTL_ENLINK, base + ACCTLEN); base 105 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(ready, base + ACINTEN); base 107 sound/soc/txx9/txx9aclc-ac97.c (__raw_readl(base + ACINTSTS) & ready) == ready, base 111 sound/soc/txx9/txx9aclc-ac97.c __raw_readl(base + ACINTSTS)); base 113 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(ACINT_REGACCRDY, base + ACINTSTS); base 114 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(ready, base + ACINTDIS); base 127 sound/soc/txx9/txx9aclc-ac97.c void __iomem *base = drvdata->base; base 129 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(__raw_readl(base + ACINTMSTS), base + ACINTDIS); base 145 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(ACCTL_ENLINK, drvdata->base + ACCTLDIS); base 188 sound/soc/txx9/txx9aclc-ac97.c drvdata->base = devm_ioremap_resource(&pdev->dev, r); base 189 sound/soc/txx9/txx9aclc-ac97.c if (IS_ERR(drvdata->base)) base 190 sound/soc/txx9/txx9aclc-ac97.c return PTR_ERR(drvdata->base); base 161 sound/soc/txx9/txx9aclc.c void __iomem *base = drvdata->base; base 175 sound/soc/txx9/txx9aclc.c __raw_writel(ctlbit, base + ACCTLEN); base 210 sound/soc/txx9/txx9aclc.c void __iomem *base = drvdata->base; base 225 sound/soc/txx9/txx9aclc.c __raw_writel(ctlbit, base + ACCTLDIS); base 229 sound/soc/txx9/txx9aclc.c __raw_writel(ctlbit, base + ACCTLEN); base 387 sound/soc/txx9/txx9aclc.c void __iomem *base = drvdata->base; base 391 sound/soc/txx9/txx9aclc.c __raw_writel(ACCTL_AUDODMA | ACCTL_AUDIDMA, base + ACCTLDIS); base 393 sound/soc/txx9/txx9aclc.c __raw_writel(__raw_readl(base + ACAUDIDAT), base + ACAUDODAT); base 61 sound/soc/txx9/txx9aclc.h void __iomem *base; base 28 sound/soc/xilinx/xlnx_i2s.c void __iomem *base = snd_soc_dai_get_drvdata(cpu_dai); base 33 sound/soc/xilinx/xlnx_i2s.c writel(div, base + I2S_I2STIM_OFFSET); base 43 sound/soc/xilinx/xlnx_i2s.c void __iomem *base = snd_soc_dai_get_drvdata(i2s_dai); base 49 sound/soc/xilinx/xlnx_i2s.c writel(chan_id, base + reg_off); base 59 sound/soc/xilinx/xlnx_i2s.c void __iomem *base = snd_soc_dai_get_drvdata(i2s_dai); base 65 sound/soc/xilinx/xlnx_i2s.c writel(1, base + I2S_CORE_CTRL_OFFSET); base 70 sound/soc/xilinx/xlnx_i2s.c writel(0, base + I2S_CORE_CTRL_OFFSET); base 98 sound/soc/xilinx/xlnx_i2s.c void __iomem *base; base 109 sound/soc/xilinx/xlnx_i2s.c base = devm_platform_ioremap_resource(pdev, 0); base 110 sound/soc/xilinx/xlnx_i2s.c if (IS_ERR(base)) base 111 sound/soc/xilinx/xlnx_i2s.c return PTR_ERR(base); base 156 sound/soc/xilinx/xlnx_i2s.c dev_set_drvdata(&pdev->dev, base); base 50 sound/soc/xilinx/xlnx_spdif.c void __iomem *base; base 60 sound/soc/xilinx/xlnx_spdif.c val = readl(ctx->base + XSPDIF_IRQ_STS_REG); base 63 sound/soc/xilinx/xlnx_spdif.c ctx->base + XSPDIF_IRQ_STS_REG); base 64 sound/soc/xilinx/xlnx_spdif.c val = readl(ctx->base + base 67 sound/soc/xilinx/xlnx_spdif.c ctx->base + XSPDIF_IRQ_ENABLE_REG); base 83 sound/soc/xilinx/xlnx_spdif.c val = readl(ctx->base + XSPDIF_CONTROL_REG); base 85 sound/soc/xilinx/xlnx_spdif.c writel(val, ctx->base + XSPDIF_CONTROL_REG); base 89 sound/soc/xilinx/xlnx_spdif.c ctx->base + XSPDIF_IRQ_ENABLE_REG); base 91 sound/soc/xilinx/xlnx_spdif.c ctx->base + XSPDIF_GLOBAL_IRQ_ENABLE_REG); base 102 sound/soc/xilinx/xlnx_spdif.c writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG); base 141 sound/soc/xilinx/xlnx_spdif.c val = readl(ctx->base + XSPDIF_CONTROL_REG); base 144 sound/soc/xilinx/xlnx_spdif.c writel(val, ctx->base + XSPDIF_CONTROL_REG); base 175 sound/soc/xilinx/xlnx_spdif.c val = readl(ctx->base + XSPDIF_CONTROL_REG); base 181 sound/soc/xilinx/xlnx_spdif.c writel(val, ctx->base + XSPDIF_CONTROL_REG); base 189 sound/soc/xilinx/xlnx_spdif.c writel(val, ctx->base + XSPDIF_CONTROL_REG); base 263 sound/soc/xilinx/xlnx_spdif.c ctx->base = devm_platform_ioremap_resource(pdev, 0); base 264 sound/soc/xilinx/xlnx_spdif.c if (IS_ERR(ctx->base)) { base 265 sound/soc/xilinx/xlnx_spdif.c ret = PTR_ERR(ctx->base); base 310 sound/soc/xilinx/xlnx_spdif.c writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG); base 101 sound/soc/zte/zx-i2s.c static void zx_i2s_tx_en(void __iomem *base, bool on) base 105 sound/soc/zte/zx-i2s.c val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL); base 110 sound/soc/zte/zx-i2s.c writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL); base 113 sound/soc/zte/zx-i2s.c static void zx_i2s_rx_en(void __iomem *base, bool on) base 117 sound/soc/zte/zx-i2s.c val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL); base 122 sound/soc/zte/zx-i2s.c writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL); base 125 sound/soc/zte/zx-i2s.c static void zx_i2s_tx_dma_en(void __iomem *base, bool on) base 129 sound/soc/zte/zx-i2s.c val = readl_relaxed(base + ZX_I2S_FIFO_CTRL); base 135 sound/soc/zte/zx-i2s.c writel_relaxed(val, base + ZX_I2S_FIFO_CTRL); base 138 sound/soc/zte/zx-i2s.c static void zx_i2s_rx_dma_en(void __iomem *base, bool on) base 142 sound/soc/zte/zx-i2s.c val = readl_relaxed(base + ZX_I2S_FIFO_CTRL); base 148 sound/soc/zte/zx-i2s.c writel_relaxed(val, base + ZX_I2S_FIFO_CTRL); base 93 sound/soc/zte/zx-spdif.c static int zx_spdif_chanstats(void __iomem *base, unsigned int rate) base 131 sound/soc/zte/zx-spdif.c writel_relaxed(cstas1, base + ZX_CH_STA_1); base 193 sound/soc/zte/zx-spdif.c static void zx_spdif_cfg_tx(void __iomem *base, int on) base 197 sound/soc/zte/zx-spdif.c val = readl_relaxed(base + ZX_CTRL); base 200 sound/soc/zte/zx-spdif.c writel_relaxed(val, base + ZX_CTRL); base 202 sound/soc/zte/zx-spdif.c val = readl_relaxed(base + ZX_FIFOCTRL); base 206 sound/soc/zte/zx-spdif.c writel_relaxed(val, base + ZX_FIFOCTRL); base 290 sound/soc/zte/zx-spdif.c static void zx_spdif_dev_init(void __iomem *base) base 294 sound/soc/zte/zx-spdif.c writel_relaxed(0, base + ZX_CTRL); base 295 sound/soc/zte/zx-spdif.c writel_relaxed(0, base + ZX_INT_MASK); base 296 sound/soc/zte/zx-spdif.c writel_relaxed(0xf, base + ZX_INT_STATUS); base 297 sound/soc/zte/zx-spdif.c writel_relaxed(0x1, base + ZX_FIFOCTRL); base 299 sound/soc/zte/zx-spdif.c val = readl_relaxed(base + ZX_FIFOCTRL); base 302 sound/soc/zte/zx-spdif.c writel_relaxed(val, base + ZX_FIFOCTRL); base 1678 sound/sparc/cs4231.c struct sbus_dma_info *base = &dma_cont->sbus_info; base 1682 sound/sparc/cs4231.c spin_lock_irqsave(&base->lock, flags); base 1683 sound/sparc/cs4231.c csr = sbus_readl(base->regs + APCCSR); base 1686 sound/sparc/cs4231.c if (base->dir == APC_PLAY) base 1692 sound/sparc/cs4231.c if (base->dir == APC_PLAY) base 1697 sound/sparc/cs4231.c sbus_writel(bus_addr, base->regs + base->dir + APCNVA); base 1698 sound/sparc/cs4231.c sbus_writel(len, base->regs + base->dir + APCNC); base 1700 sound/sparc/cs4231.c spin_unlock_irqrestore(&base->lock, flags); base 1708 sound/sparc/cs4231.c struct sbus_dma_info *base = &dma_cont->sbus_info; base 1710 sound/sparc/cs4231.c spin_lock_irqsave(&base->lock, flags); base 1711 sound/sparc/cs4231.c csr = sbus_readl(base->regs + APCCSR); base 1715 sound/sparc/cs4231.c if (base->dir == APC_RECORD) base 1719 sound/sparc/cs4231.c sbus_writel(csr, base->regs + APCCSR); base 1720 sound/sparc/cs4231.c spin_unlock_irqrestore(&base->lock, flags); base 1727 sound/sparc/cs4231.c struct sbus_dma_info *base = &dma_cont->sbus_info; base 1729 sound/sparc/cs4231.c spin_lock_irqsave(&base->lock, flags); base 1731 sound/sparc/cs4231.c sbus_writel(0, base->regs + base->dir + APCNC); base 1732 sound/sparc/cs4231.c sbus_writel(0, base->regs + base->dir + APCNVA); base 1733 sound/sparc/cs4231.c if (base->dir == APC_PLAY) { base 1734 sound/sparc/cs4231.c sbus_writel(0, base->regs + base->dir + APCC); base 1735 sound/sparc/cs4231.c sbus_writel(0, base->regs + base->dir + APCVA); base 1740 sound/sparc/cs4231.c csr = sbus_readl(base->regs + APCCSR); base 1742 sound/sparc/cs4231.c if (base->dir == APC_PLAY) base 1748 sound/sparc/cs4231.c sbus_writel(csr, base->regs + APCCSR); base 1753 sound/sparc/cs4231.c sbus_writel(csr, base->regs + APCCSR); base 1755 sound/sparc/cs4231.c spin_unlock_irqrestore(&base->lock, flags); base 1760 sound/sparc/cs4231.c struct sbus_dma_info *base = &dma_cont->sbus_info; base 1762 sound/sparc/cs4231.c return sbus_readl(base->regs + base->dir + APCVA); base 132 tools/arch/x86/include/uapi/asm/kvm.h __u64 base; base 142 tools/arch/x86/include/uapi/asm/kvm.h __u64 base; base 346 tools/arch/x86/lib/insn.c insn_byte_t mod, rm, base; base 372 tools/arch/x86/lib/insn.c base = X86_SIB_BASE(insn->sib.value); base 386 tools/arch/x86/lib/insn.c (mod == 0 && base == 5)) { base 178 tools/bpf/bpf_jit_disasm.c unsigned long base; base 204 tools/bpf/bpf_jit_disasm.c &flen, &proglen, &pass, &base); base 245 tools/bpf/bpf_jit_disasm.c printf("%lx + <x>:\n", base); base 333 tools/bpf/bpftool/map.c unsigned int i = 0, base = 0; base 337 tools/bpf/bpftool/map.c base = 16; base 342 tools/bpf/bpftool/map.c val[i] = strtoul(argv[i], &endptr, base); base 7 tools/build/feature/test-dwarf_getlocations.c Dwarf_Addr base, start, end; base 12 tools/build/feature/test-dwarf_getlocations.c return (int)dwarf_getlocations(&attr, offset, &base, &start, &end, &op, &nops); base 51 tools/include/linux/ring_buffer.h static inline u64 ring_buffer_read_head(struct perf_event_mmap_page *base) base 59 tools/include/linux/ring_buffer.h return smp_load_acquire(&base->data_head); base 61 tools/include/linux/ring_buffer.h u64 head = READ_ONCE(base->data_head); base 68 tools/include/linux/ring_buffer.h static inline void ring_buffer_write_tail(struct perf_event_mmap_page *base, base 71 tools/include/linux/ring_buffer.h smp_store_release(&base->data_tail, tail); base 983 tools/include/uapi/drm/drm.h struct drm_event base; base 995 tools/include/uapi/drm/drm.h struct drm_event base; base 1649 tools/include/uapi/drm/i915_drm.h struct i915_user_extension base; base 1661 tools/include/uapi/drm/i915_drm.h struct i915_user_extension base; \ base 1685 tools/include/uapi/drm/i915_drm.h struct i915_user_extension base; base 1699 tools/include/uapi/drm/i915_drm.h struct i915_user_extension base; \ base 1722 tools/include/uapi/drm/i915_drm.h struct i915_user_extension base; base 1728 tools/include/uapi/drm/i915_drm.h struct i915_user_extension base; base 321 tools/lib/api/fs/fs.c unsigned long long *value, int base) base 330 tools/lib/api/fs/fs.c *value = strtoull(line, NULL, base); base 438 tools/lib/api/fs/fs.c unsigned long long *value, int base) base 448 tools/lib/api/fs/fs.c return filename__read_ull_base(path, value, base); base 5258 tools/lib/bpf/libbpf.c void *base = ((__u8 *)header) + page_size; base 5264 tools/lib/bpf/libbpf.c ehdr = base + (data_tail & (mmap_size - 1)); base 5267 tools/lib/bpf/libbpf.c if (((void *)ehdr) + ehdr_size > base + mmap_size) { base 5269 tools/lib/bpf/libbpf.c size_t len_first = base + mmap_size - copy_start; base 5284 tools/lib/bpf/libbpf.c memcpy(*copy_mem + len_first, base, len_secnd); base 5315 tools/lib/bpf/libbpf.c void *base; /* mmap()'ed memory */ base 5343 tools/lib/bpf/libbpf.c if (cpu_buf->base && base 5344 tools/lib/bpf/libbpf.c munmap(cpu_buf->base, pb->mmap_size + pb->page_size)) base 5400 tools/lib/bpf/libbpf.c cpu_buf->base = mmap(NULL, pb->mmap_size + pb->page_size, base 5403 tools/lib/bpf/libbpf.c if (cpu_buf->base == MAP_FAILED) { base 5404 tools/lib/bpf/libbpf.c cpu_buf->base = NULL; base 5636 tools/lib/bpf/libbpf.c ret = bpf_perf_event_read_simple(cpu_buf->base, pb->mmap_size, base 488 tools/objtool/arch/x86/decode.c state->regs[i].base = CFI_UNDEFINED; base 493 tools/objtool/arch/x86/decode.c state->cfa.base = CFI_SP; base 497 tools/objtool/arch/x86/decode.c state->regs[16].base = CFI_CFA; base 34 tools/objtool/cfi.h int base; base 217 tools/objtool/check.c state->cfa.base = CFI_UNDEFINED; base 219 tools/objtool/check.c state->regs[i].base = CFI_UNDEFINED; base 220 tools/objtool/check.c state->vals[i].base = CFI_UNDEFINED; base 1214 tools/objtool/check.c cfa->base = CFI_UNDEFINED; base 1217 tools/objtool/check.c cfa->base = CFI_SP; base 1220 tools/objtool/check.c cfa->base = CFI_BP; base 1223 tools/objtool/check.c cfa->base = CFI_SP_INDIRECT; base 1226 tools/objtool/check.c cfa->base = CFI_R10; base 1229 tools/objtool/check.c cfa->base = CFI_R13; base 1232 tools/objtool/check.c cfa->base = CFI_DI; base 1235 tools/objtool/check.c cfa->base = CFI_DX; base 1374 tools/objtool/check.c if (state->cfa.base != initial_func_cfi.cfa.base || base 1381 tools/objtool/check.c if (state->regs[i].base != initial_func_cfi.regs[i].base || base 1390 tools/objtool/check.c if (state->cfa.base == CFI_BP && state->regs[CFI_BP].base == CFI_CFA && base 1394 tools/objtool/check.c if (state->drap && state->regs[CFI_BP].base == CFI_BP) base 1405 tools/objtool/check.c if (cfa->base != CFI_SP && cfa->base != CFI_SP_INDIRECT) base 1424 tools/objtool/check.c static void save_reg(struct insn_state *state, unsigned char reg, int base, base 1428 tools/objtool/check.c state->regs[reg].base == CFI_UNDEFINED) { base 1429 tools/objtool/check.c state->regs[reg].base = base; base 1436 tools/objtool/check.c state->regs[reg].base = CFI_UNDEFINED; base 1500 tools/objtool/check.c if (cfa->base == CFI_UNDEFINED) { base 1518 tools/objtool/check.c cfa->base == CFI_SP && base 1519 tools/objtool/check.c regs[CFI_BP].base == CFI_CFA && base 1523 tools/objtool/check.c cfa->base = op->dest.reg; base 1531 tools/objtool/check.c regs[CFI_BP].base = CFI_BP; base 1536 tools/objtool/check.c else if (op->src.reg == CFI_SP && cfa->base == CFI_SP) { base 1548 tools/objtool/check.c state->vals[op->dest.reg].base = CFI_CFA; base 1553 tools/objtool/check.c cfa->base == CFI_BP) { base 1563 tools/objtool/check.c else if (op->dest.reg == cfa->base) { base 1566 tools/objtool/check.c if (cfa->base == CFI_SP && base 1567 tools/objtool/check.c state->vals[op->src.reg].base == CFI_CFA) { base 1581 tools/objtool/check.c cfa->base = CFI_UNDEFINED; base 1593 tools/objtool/check.c if (cfa->base == CFI_SP) base 1605 tools/objtool/check.c if (op->src.reg == CFI_SP && cfa->base == CFI_SP) { base 1620 tools/objtool/check.c state->vals[op->dest.reg].base = CFI_CFA; base 1631 tools/objtool/check.c cfa->base = CFI_SP; base 1638 tools/objtool/check.c if (op->dest.reg == state->cfa.base) { base 1648 tools/objtool/check.c (state->drap_reg != CFI_UNDEFINED && cfa->base != CFI_SP) || base 1649 tools/objtool/check.c (state->drap_reg == CFI_UNDEFINED && cfa->base != CFI_BP)) { base 1657 tools/objtool/check.c cfa->base = state->drap_reg; base 1672 tools/objtool/check.c op->dest.reg == cfa->base) { base 1675 tools/objtool/check.c cfa->base = CFI_SP; base 1678 tools/objtool/check.c if (state->drap && cfa->base == CFI_BP_INDIRECT && base 1684 tools/objtool/check.c cfa->base = state->drap_reg; base 1695 tools/objtool/check.c if (cfa->base == CFI_SP) base 1705 tools/objtool/check.c cfa->base = state->drap_reg; base 1716 tools/objtool/check.c } else if (op->src.reg == cfa->base && base 1737 tools/objtool/check.c if (cfa->base == CFI_SP) base 1744 tools/objtool/check.c if (op->src.reg == cfa->base && op->src.reg == state->drap_reg) { base 1747 tools/objtool/check.c cfa->base = CFI_BP_INDIRECT; base 1753 tools/objtool/check.c } else if (op->src.reg == CFI_BP && cfa->base == state->drap_reg) { base 1758 tools/objtool/check.c } else if (regs[op->src.reg].base == CFI_UNDEFINED) { base 1772 tools/objtool/check.c cfa->base != CFI_BP) base 1779 tools/objtool/check.c if (op->src.reg == cfa->base && op->src.reg == state->drap_reg) { base 1782 tools/objtool/check.c cfa->base = CFI_BP_INDIRECT; base 1789 tools/objtool/check.c else if (regs[op->src.reg].base == CFI_UNDEFINED) { base 1795 tools/objtool/check.c } else if (op->dest.reg == cfa->base) { base 1806 tools/objtool/check.c if ((!state->drap && cfa->base != CFI_BP) || base 1807 tools/objtool/check.c (state->drap && cfa->base != state->drap_reg)) { base 1819 tools/objtool/check.c cfa->base = CFI_SP; base 1834 tools/objtool/check.c if (cfa->base == CFI_SP) base 1856 tools/objtool/check.c state1->cfa.base, state1->cfa.offset, base 1857 tools/objtool/check.c state2->cfa.base, state2->cfa.offset); base 1867 tools/objtool/check.c i, state1->regs[i].base, state1->regs[i].offset, base 1868 tools/objtool/check.c i, state2->regs[i].base, state2->regs[i].offset); base 2210 tools/objtool/check.c if (state.cfa.base == CFI_UNDEFINED) base 361 tools/objtool/elf.c sec->base = find_section_by_name(elf, sec->name + 5); base 362 tools/objtool/elf.c if (!sec->base) { base 368 tools/objtool/elf.c sec->base->rela = sec; base 562 tools/objtool/elf.c struct section *elf_create_rela_section(struct elf *elf, struct section *base) base 567 tools/objtool/elf.c relaname = malloc(strlen(base->name) + strlen(".rela") + 1); base 573 tools/objtool/elf.c strcat(relaname, base->name); base 580 tools/objtool/elf.c base->rela = sec; base 581 tools/objtool/elf.c sec->base = base; base 586 tools/objtool/elf.c sec->sh.sh_info = base->idx; base 33 tools/objtool/elf.h struct section *base, *rela; base 89 tools/objtool/elf.h struct section *elf_create_rela_section(struct elf *elf, struct section *base); base 24 tools/objtool/orc_gen.c if (cfa->base == CFI_UNDEFINED) { base 29 tools/objtool/orc_gen.c switch (cfa->base) { base 56 tools/objtool/orc_gen.c insn->sec, insn->offset, cfa->base); base 60 tools/objtool/orc_gen.c switch(bp->base) { base 72 tools/objtool/orc_gen.c insn->sec, insn->offset, bp->base); base 96 tools/perf/arch/x86/tests/perf-time-to-tsc.c pc = evlist->mmap[0].core.base; base 81 tools/perf/arch/x86/util/intel-bts.c pc = session->evlist->mmap[0].core.base; base 358 tools/perf/arch/x86/util/intel-pt.c pc = session->evlist->mmap[0].core.base; base 363 tools/perf/builtin-record.c if (map->core.base) base 609 tools/perf/builtin-record.c if (!map->auxtrace_mmap.base) base 973 tools/perf/builtin-record.c if (map->core.base) { base 999 tools/perf/builtin-record.c if (map->auxtrace_mmap.base && !rec->opts.auxtrace_snapshot_mode && base 1201 tools/perf/builtin-record.c if (evlist->mmap && evlist->mmap[0].core.base) base 1202 tools/perf/builtin-record.c return evlist->mmap[0].core.base; base 1203 tools/perf/builtin-record.c if (evlist->overwrite_mmap && evlist->overwrite_mmap[0].core.base) base 1204 tools/perf/builtin-record.c return evlist->overwrite_mmap[0].core.base; base 133 tools/perf/jvmti/jvmti_agent.c char *base, *p; base 141 tools/perf/jvmti/jvmti_agent.c base = getenv("JITDUMPDIR"); base 142 tools/perf/jvmti/jvmti_agent.c if (!base) base 143 tools/perf/jvmti/jvmti_agent.c base = getenv("HOME"); base 144 tools/perf/jvmti/jvmti_agent.c if (!base) base 145 tools/perf/jvmti/jvmti_agent.c base = "."; base 149 tools/perf/jvmti/jvmti_agent.c ret = snprintf(jit_path, PATH_MAX, "%s/.debug/", base); base 153 tools/perf/jvmti/jvmti_agent.c " HOME variables", base); base 164 tools/perf/jvmti/jvmti_agent.c ret = snprintf(jit_path, PATH_MAX, "%s/.debug/jit", base); base 168 tools/perf/jvmti/jvmti_agent.c " JITDUMPDIR, and HOME variables", base); base 179 tools/perf/jvmti/jvmti_agent.c ret = snprintf(jit_path, PATH_MAX, "%s/.debug/jit/%s.XXXXXXXX", base, str); base 184 tools/perf/jvmti/jvmti_agent.c base, str); base 19 tools/perf/lib/include/internal/mmap.h void *base; base 955 tools/perf/pmu-events/jevents.c bname = (char *) fpath + ftwbuf->base - 2; base 963 tools/perf/pmu-events/jevents.c bname = (char *) fpath + ftwbuf->base; base 447 tools/perf/tests/builtin-test.c #define for_each_shell_test(dir, base, ent) \ base 449 tools/perf/tests/builtin-test.c if (!is_directory(base, ent) && ent->d_name[0] != '.') base 627 tools/perf/ui/browsers/annotate.c switch_percent_type(struct annotation_options *opts, bool base) base 631 tools/perf/ui/browsers/annotate.c if (base) base 637 tools/perf/ui/browsers/annotate.c if (base) base 643 tools/perf/ui/browsers/annotate.c if (base) base 649 tools/perf/ui/browsers/annotate.c if (base) base 72 tools/perf/util/auxtrace.c WARN_ONCE(mm->base, "Uninitialized auxtrace_mmap\n"); base 83 tools/perf/util/auxtrace.c mm->base = NULL; base 95 tools/perf/util/auxtrace.c mm->base = mmap(NULL, mp->len, mp->prot, MAP_SHARED, fd, mp->offset); base 96 tools/perf/util/auxtrace.c if (mm->base == MAP_FAILED) { base 98 tools/perf/util/auxtrace.c mm->base = NULL; base 107 tools/perf/util/auxtrace.c if (mm->base) { base 108 tools/perf/util/auxtrace.c munmap(mm->base, mm->len); base 109 tools/perf/util/auxtrace.c mm->base = NULL; base 1238 tools/perf/util/auxtrace.c unsigned char *data = mm->base; base 272 tools/perf/util/auxtrace.h void *base; base 148 tools/perf/util/dsos.c char *base, *lname; base 152 tools/perf/util/dsos.c if (asprintf(&base, "[JIT] tid %d", tid) < 0) base 168 tools/perf/util/dsos.c base = strdup(basename(lname)); base 172 tools/perf/util/dsos.c if (!base) base 175 tools/perf/util/dsos.c dso__set_short_name(dso, base, true); base 321 tools/perf/util/dwarf-aux.c Dwarf_Addr base, end; base 329 tools/perf/util/dwarf-aux.c return dwarf_ranges(dw_die, 0, &base, addr, &end) < 0 ? -ENOENT : 0; base 1037 tools/perf/util/dwarf-aux.c Dwarf_Addr base; base 1060 tools/perf/util/dwarf-aux.c while ((offset = dwarf_ranges(&scopes[1], offset, &base, base 1097 tools/perf/util/dwarf-aux.c Dwarf_Addr base; base 1118 tools/perf/util/dwarf-aux.c while ((offset = dwarf_getlocations(&attr, offset, &base, base 35 tools/perf/util/mmap.c unsigned char *data = map->core.base + page_size; base 110 tools/perf/util/mmap.c return perf_mmap__read_head(map) == map->core.prev && !map->auxtrace_mmap.base; base 120 tools/perf/util/mmap.c BUG_ON(map->core.base && refcount_read(&map->core.refcnt) == 0); base 321 tools/perf/util/mmap.c if (map->core.base != NULL) { base 322 tools/perf/util/mmap.c munmap(map->core.base, perf_mmap__mmap_len(map)); base 323 tools/perf/util/mmap.c map->core.base = NULL; base 374 tools/perf/util/mmap.c map->core.base = mmap(NULL, perf_mmap__mmap_len(map), mp->prot, base 376 tools/perf/util/mmap.c if (map->core.base == MAP_FAILED) { base 379 tools/perf/util/mmap.c map->core.base = NULL; base 403 tools/perf/util/mmap.c &mp->auxtrace_mp, map->core.base, fd)) base 448 tools/perf/util/mmap.c unsigned char *data = md->core.base + page_size; base 493 tools/perf/util/mmap.c unsigned char *data = md->core.base + page_size; base 54 tools/perf/util/mmap.h return ring_buffer_read_head(mm->core.base); base 59 tools/perf/util/mmap.h ring_buffer_write_tail(md->core.base, tail); base 2595 tools/perf/util/probe-event.c static int get_new_event_name(char *buf, size_t len, const char *base, base 2602 tools/perf/util/probe-event.c if (*base == '.') base 2603 tools/perf/util/probe-event.c base++; base 2604 tools/perf/util/probe-event.c nbase = strdup(base); base 62 tools/perf/util/srcline.c const char *base = strrchr(path, '/'); base 64 tools/perf/util/srcline.c return base ? base + 1 : path; base 732 tools/perf/util/synthetic-events.c int base = 0; base 752 tools/perf/util/synthetic-events.c dirent, base, n); base 780 tools/perf/util/synthetic-events.c base = args[i-1].start + args[i-1].num; base 783 tools/perf/util/synthetic-events.c args[j].start = base + (j - i) * args[i].num; base 410 tools/perf/util/unwind-libunwind-local.c unw_word_t base = is_exec ? 0 : map->start; base 419 tools/perf/util/unwind-libunwind-local.c if (dwarf_find_debug_frame(0, &di, ip, base, symfile, base 2654 tools/testing/nvdimm/test/nfit.c memcpy(mmio->addr.base + dpa, iobuf, len); base 2656 tools/testing/nvdimm/test/nfit.c memcpy(iobuf, mmio->addr.base + dpa, len); base 2659 tools/testing/nvdimm/test/nfit.c arch_invalidate_pmem(mmio->addr.base + dpa, len); base 148 tools/testing/radix-tree/idr-test.c void idr_get_next_test(int base) base 153 tools/testing/radix-tree/idr-test.c idr_init_base(&idr, base); base 210 tools/testing/radix-tree/idr-test.c void idr_u32_test(int base) base 213 tools/testing/radix-tree/idr-test.c idr_init_base(&idr, base); base 316 tools/testing/selftests/bpf/test_sockmap.c bool base; base 614 tools/testing/selftests/bpf/test_sockmap.c if (opt->base) base 1052 tools/testing/selftests/bpf/test_sockmap.c options->base = false; base 1056 tools/testing/selftests/bpf/test_sockmap.c options->base = false; base 1060 tools/testing/selftests/bpf/test_sockmap.c options->base = true; base 1064 tools/testing/selftests/bpf/test_sockmap.c options->base = true; base 1203 tools/testing/selftests/bpf/test_sockmap.c opt.base = false; base 1561 tools/testing/selftests/kvm/lib/kvm_util.c sparsebit_idx_t pg, base; base 1571 tools/testing/selftests/kvm/lib/kvm_util.c base = pg = paddr_min >> vm->page_shift; base 1574 tools/testing/selftests/kvm/lib/kvm_util.c for (; pg < base + num; ++pg) { base 1576 tools/testing/selftests/kvm/lib/kvm_util.c base = pg = sparsebit_next_set(region->unused_phy_pages, pg); base 1580 tools/testing/selftests/kvm/lib/kvm_util.c } while (pg && pg != base + num); base 1591 tools/testing/selftests/kvm/lib/kvm_util.c for (pg = base; pg < base + num; ++pg) base 1594 tools/testing/selftests/kvm/lib/kvm_util.c return base * vm->page_size; base 137 tools/testing/selftests/kvm/lib/x86_64/processor.c indent, "", segment->base, segment->limit, base 168 tools/testing/selftests/kvm/lib/x86_64/processor.c indent, "", dtable->base, dtable->limit, base 447 tools/testing/selftests/kvm/lib/x86_64/processor.c desc->base0 = segp->base & 0xFFFF; base 448 tools/testing/selftests/kvm/lib/x86_64/processor.c desc->base1 = segp->base >> 16; base 457 tools/testing/selftests/kvm/lib/x86_64/processor.c desc->base2 = segp->base >> 24; base 459 tools/testing/selftests/kvm/lib/x86_64/processor.c desc->base3 = segp->base >> 32; base 591 tools/testing/selftests/kvm/lib/x86_64/processor.c dt->base = vm->gdt; base 604 tools/testing/selftests/kvm/lib/x86_64/processor.c segp->base = vm->tss; base 195 tools/testing/selftests/net/psock_tpacket.c static inline int __v1_v2_rx_kernel_ready(void *base, int version) base 199 tools/testing/selftests/net/psock_tpacket.c return __v1_rx_kernel_ready(base); base 201 tools/testing/selftests/net/psock_tpacket.c return __v2_rx_kernel_ready(base); base 208 tools/testing/selftests/net/psock_tpacket.c static inline void __v1_v2_rx_user_ready(void *base, int version) base 212 tools/testing/selftests/net/psock_tpacket.c __v1_rx_user_ready(base); base 215 tools/testing/selftests/net/psock_tpacket.c __v2_rx_user_ready(base); base 312 tools/testing/selftests/net/psock_tpacket.c static inline int __tx_kernel_ready(void *base, int version) base 316 tools/testing/selftests/net/psock_tpacket.c return __v1_tx_kernel_ready(base); base 318 tools/testing/selftests/net/psock_tpacket.c return __v2_tx_kernel_ready(base); base 320 tools/testing/selftests/net/psock_tpacket.c return __v3_tx_kernel_ready(base); base 327 tools/testing/selftests/net/psock_tpacket.c static inline void __tx_user_ready(void *base, int version) base 331 tools/testing/selftests/net/psock_tpacket.c __v1_tx_user_ready(base); base 334 tools/testing/selftests/net/psock_tpacket.c __v2_tx_user_ready(base); base 337 tools/testing/selftests/net/psock_tpacket.c __v3_tx_user_ready(base); base 77 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) base 78 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) base 79 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) base 80 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) base 82 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) base 83 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) base 84 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base) base 85 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_NVGPRS(base) lmw 13, GPR0+4*13(base) base 88 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) base 89 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) base 90 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) base 91 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) base 92 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) base 93 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) base 94 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) base 95 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) base 97 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) base 98 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) base 99 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) base 100 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) base 101 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) base 102 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) base 103 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) base 104 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) base 105 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) base 106 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) base 107 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) base 108 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) base 110 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b base 111 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) base 112 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) base 113 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) base 114 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) base 115 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) base 116 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b base 117 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) base 118 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) base 119 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) base 120 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) base 121 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) base 124 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) base 125 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) base 127 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ base 128 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h STXVD2X(n,b,base); \ base 131 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ base 135 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) base 136 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) base 137 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) base 138 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) base 139 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) base 140 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) base 141 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) base 142 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) base 143 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) base 144 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) base 145 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) base 146 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) base 44 tools/testing/selftests/vDSO/parse_vdso.c extern void vdso_init_from_sysinfo_ehdr(uintptr_t base); base 94 tools/testing/selftests/vDSO/parse_vdso.c void vdso_init_from_sysinfo_ehdr(uintptr_t base) base 101 tools/testing/selftests/vDSO/parse_vdso.c vdso_info.load_addr = base; base 103 tools/testing/selftests/vDSO/parse_vdso.c ELF(Ehdr) *hdr = (ELF(Ehdr)*)base; base 120 tools/testing/selftests/vDSO/parse_vdso.c vdso_info.load_offset = base base 124 tools/testing/selftests/vDSO/parse_vdso.c dyn = (ELF(Dyn)*)(base + pt[i].p_offset); base 20 tools/testing/selftests/vDSO/vdso_standalone_test_x86.c extern void vdso_init_from_sysinfo_ehdr(uintptr_t base); base 21 tools/testing/selftests/vDSO/vdso_test.c extern void vdso_init_from_sysinfo_ehdr(uintptr_t base); base 192 tools/testing/selftests/x86/entry_from_vm86.c unsigned long base; base 196 tools/testing/selftests/x86/entry_from_vm86.c struct table_desc gdt1 = { .base = 0x3c3c3c3c, .limit = 0x9999 }; base 197 tools/testing/selftests/x86/entry_from_vm86.c struct table_desc gdt2 = { .base = 0x1a1a1a1a, .limit = 0xaeae }; base 198 tools/testing/selftests/x86/entry_from_vm86.c struct table_desc idt1 = { .base = 0x7b7b7b7b, .limit = 0xf1f1 }; base 199 tools/testing/selftests/x86/entry_from_vm86.c struct table_desc idt2 = { .base = 0x89898989, .limit = 0x1313 }; base 220 tools/testing/selftests/x86/entry_from_vm86.c idt1.limit, idt1.base); base 222 tools/testing/selftests/x86/entry_from_vm86.c gdt1.limit, gdt1.base); base 161 tools/testing/selftests/x86/fsgsbase.c unsigned long base; base 169 tools/testing/selftests/x86/fsgsbase.c base = read_base(GS); base 170 tools/testing/selftests/x86/fsgsbase.c if (base == value) { base 176 tools/testing/selftests/x86/fsgsbase.c base, sel); base 179 tools/testing/selftests/x86/fsgsbase.c if (syscall(SYS_arch_prctl, ARCH_GET_GS, &base) != 0) base 181 tools/testing/selftests/x86/fsgsbase.c if (base == value) { base 187 tools/testing/selftests/x86/fsgsbase.c base, sel); base 193 tools/testing/selftests/x86/fsgsbase.c unsigned long base, arch_base; base 203 tools/testing/selftests/x86/fsgsbase.c base = read_base(GS); base 206 tools/testing/selftests/x86/fsgsbase.c if (base == arch_base) { base 207 tools/testing/selftests/x86/fsgsbase.c printf("[OK]\tGSBASE is 0x%lx\n", base); base 210 tools/testing/selftests/x86/fsgsbase.c printf("[FAIL]\tGSBASE changed to 0x%lx but kernel reports 0x%lx\n", base, arch_base); base 306 tools/testing/selftests/x86/fsgsbase.c void test_wrbase(unsigned short index, unsigned long base) base 311 tools/testing/selftests/x86/fsgsbase.c printf("[RUN]\tGS = 0x%hx, GSBASE = 0x%lx\n", index, base); base 314 tools/testing/selftests/x86/fsgsbase.c wrgsbase(base); base 325 tools/testing/selftests/x86/fsgsbase.c if (newindex == index && newbase == base) { base 365 tools/testing/selftests/x86/fsgsbase.c unsigned long base; base 409 tools/testing/selftests/x86/fsgsbase.c base = read_base(GS); base 410 tools/testing/selftests/x86/fsgsbase.c if (base == local && sel_pre_sched == sel_post_sched) { base 416 tools/testing/selftests/x86/fsgsbase.c sel_pre_sched, local, sel_post_sched, base); base 422 tools/testing/selftests/x86/fsgsbase.c unsigned long base; base 434 tools/testing/selftests/x86/fsgsbase.c base = read_base(GS); base 435 tools/testing/selftests/x86/fsgsbase.c if (base == 0) { base 439 tools/testing/selftests/x86/fsgsbase.c printf("[FAIL]\tGSBASE changed to 0x%lx\n", base); base 468 tools/testing/selftests/x86/fsgsbase.c unsigned long gs, base; base 484 tools/testing/selftests/x86/fsgsbase.c base = ptrace(PTRACE_PEEKUSER, child, base_offset, NULL); base 492 tools/testing/selftests/x86/fsgsbase.c if (gs == 0 && base == 0xFF) { base 496 tools/testing/selftests/x86/fsgsbase.c printf("[FAIL]\tGS=0x%lx, GSBASE=0x%lx (should be 0, 0xFF)\n", gs, base); base 445 tools/thermal/tmon/tui.c int base = 0; base 450 tools/thermal/tmon/tui.c base = (ch < 'a') ? 'A' : 'a'; base 451 tools/thermal/tmon/tui.c cdev_id = ch - base; base 782 virt/kvm/arm/mmu.c unsigned long base; base 796 virt/kvm/arm/mmu.c base = io_map_base - size; base 803 virt/kvm/arm/mmu.c if ((base ^ io_map_base) & BIT(VA_BITS - 1)) base 806 virt/kvm/arm/mmu.c io_map_base = base; base 817 virt/kvm/arm/mmu.c base, base + size, base 822 virt/kvm/arm/mmu.c *haddr = base + offset_in_page(phys_addr); base 901 virt/kvm/arm/vgic/vgic-its.c phys_addr_t base = GITS_BASER_ADDR_48_to_52(baser); base 927 virt/kvm/arm/vgic/vgic-its.c addr = base + id * esz; base 943 virt/kvm/arm/vgic/vgic-its.c base + index * sizeof(indirect_ptr), base 2079 virt/kvm/arm/vgic/vgic-its.c static int scan_its_table(struct vgic_its *its, gpa_t base, int size, u32 esz, base 2085 virt/kvm/arm/vgic/vgic-its.c gpa_t gpa = base; base 2200 virt/kvm/arm/vgic/vgic-its.c gpa_t base = device->itt_addr; base 2208 virt/kvm/arm/vgic/vgic-its.c gpa_t gpa = base + ite->event_id * ite_esz; base 2237 virt/kvm/arm/vgic/vgic-its.c gpa_t base = dev->itt_addr; base 2242 virt/kvm/arm/vgic/vgic-its.c ret = scan_its_table(its, base, max_size, ite_esz, 0, base 95 virt/kvm/arm/vgic/vgic-kvm-device.c addr_ptr = &rdreg->base; base 110 virt/kvm/arm/vgic/vgic-kvm-device.c gpa_t base = *addr & KVM_VGIC_V3_RDIST_BASE_MASK; base 120 virt/kvm/arm/vgic/vgic-kvm-device.c base, count); base 131 virt/kvm/arm/vgic/vgic-kvm-device.c *addr |= rdreg->base; base 211 virt/kvm/arm/vgic/vgic-mmio-v3.c gpa_t last_rdist_typer = rdreg->base + GICR_TYPER + base 633 virt/kvm/arm/vgic/vgic-mmio-v3.c rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE; base 701 virt/kvm/arm/vgic/vgic-mmio-v3.c gpa_t base, uint32_t count) base 714 virt/kvm/arm/vgic/vgic-mmio-v3.c if (base + size < base) base 737 virt/kvm/arm/vgic/vgic-mmio-v3.c vgic_dist_overlap(kvm, base, size)) base 741 virt/kvm/arm/vgic/vgic-mmio-v3.c if (vgic_v3_rdist_overlap(kvm, base, size)) base 748 virt/kvm/arm/vgic/vgic-mmio-v3.c rdreg->base = VGIC_ADDR_UNDEF; base 750 virt/kvm/arm/vgic/vgic-mmio-v3.c ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K); base 754 virt/kvm/arm/vgic/vgic-mmio-v3.c rdreg->base = base; base 16 virt/kvm/arm/vgic/vgic-v2.c void __iomem *base = kvm_vgic_global_state.vctrl_base; base 18 virt/kvm/arm/vgic/vgic-v2.c writel_relaxed(val, base + GICH_LR0 + (lr * 4)); base 427 virt/kvm/arm/vgic/vgic-v2.c static void save_lrs(struct kvm_vcpu *vcpu, void __iomem *base) base 434 virt/kvm/arm/vgic/vgic-v2.c elrsr = readl_relaxed(base + GICH_ELRSR0); base 436 virt/kvm/arm/vgic/vgic-v2.c elrsr |= ((u64)readl_relaxed(base + GICH_ELRSR1)) << 32; base 442 virt/kvm/arm/vgic/vgic-v2.c cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4)); base 444 virt/kvm/arm/vgic/vgic-v2.c writel_relaxed(0, base + GICH_LR0 + (i * 4)); base 450 virt/kvm/arm/vgic/vgic-v2.c void __iomem *base = kvm_vgic_global_state.vctrl_base; base 453 virt/kvm/arm/vgic/vgic-v2.c if (!base) base 457 virt/kvm/arm/vgic/vgic-v2.c save_lrs(vcpu, base); base 458 virt/kvm/arm/vgic/vgic-v2.c writel_relaxed(0, base + GICH_HCR); base 465 virt/kvm/arm/vgic/vgic-v2.c void __iomem *base = kvm_vgic_global_state.vctrl_base; base 469 virt/kvm/arm/vgic/vgic-v2.c if (!base) base 473 virt/kvm/arm/vgic/vgic-v2.c writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR); base 476 virt/kvm/arm/vgic/vgic-v2.c base + GICH_LR0 + (i * 4)); base 420 virt/kvm/arm/vgic/vgic-v3.c bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size) base 426 virt/kvm/arm/vgic/vgic-v3.c if ((base + size > rdreg->base) && base 427 virt/kvm/arm/vgic/vgic-v3.c (base < rdreg->base + vgic_v3_rd_region_size(kvm, rdreg))) base 447 virt/kvm/arm/vgic/vgic-v3.c if (rdreg->base + vgic_v3_rd_region_size(kvm, rdreg) < base 448 virt/kvm/arm/vgic/vgic-v3.c rdreg->base) base 297 virt/kvm/arm/vgic/vgic.h bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size); base 299 virt/kvm/arm/vgic/vgic.h static inline bool vgic_dist_overlap(struct kvm *kvm, gpa_t base, size_t size) base 303 virt/kvm/arm/vgic/vgic.h return (base + size > d->vgic_dist_base) && base 304 virt/kvm/arm/vgic/vgic.h (base < d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE);