bank 184 arch/alpha/kernel/sys_ruffian.c unsigned long bank_addr, bank, ret = 0; bank 189 arch/alpha/kernel/sys_ruffian.c bank = *(vulp)bank_addr; bank 192 arch/alpha/kernel/sys_ruffian.c if (bank & 0x01) { bank 205 arch/alpha/kernel/sys_ruffian.c bank = (bank & 0x1e) >> 1; bank 206 arch/alpha/kernel/sys_ruffian.c if (bank < ARRAY_SIZE(size)) bank 207 arch/alpha/kernel/sys_ruffian.c ret = size[bank]; bank 110 arch/arm/kernel/tcm.c static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks, bank 126 arch/arm/kernel/tcm.c : "r" (bank)); bank 139 arch/arm/kernel/tcm.c type ? "I" : "D", bank); bank 143 arch/arm/kernel/tcm.c type ? "I" : "D", bank); bank 148 arch/arm/kernel/tcm.c bank, bank 175 arch/arm/kernel/tcm.c bank, bank 112 arch/arm/mach-imx/hardware.h #define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) bank 48 arch/arm/mach-mxs/mach-mxs.c #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) bank 70 arch/arm/mach-omap1/irq.c static inline unsigned int irq_bank_readl(int bank, int offset) bank 72 arch/arm/mach-omap1/irq.c return readl_relaxed(irq_banks[bank].va + offset); bank 74 arch/arm/mach-omap1/irq.c static inline void irq_bank_writel(unsigned long value, int bank, int offset) bank 76 arch/arm/mach-omap1/irq.c writel_relaxed(value, irq_banks[bank].va + offset); bank 104 arch/arm/mach-omap1/irq.c signed int bank; bank 107 arch/arm/mach-omap1/irq.c bank = IRQ_BANK(irq); bank 109 arch/arm/mach-omap1/irq.c fiq = bank ? 0 : (fiq & 0x1); bank 112 arch/arm/mach-omap1/irq.c irq_bank_writel(val, bank, offset); bank 47 arch/arm/mach-omap2/powerdomain-common.c u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank) bank 49 arch/arm/mach-omap2/powerdomain-common.c switch (bank) { bank 67 arch/arm/mach-omap2/powerdomain-common.c u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank) bank 69 arch/arm/mach-omap2/powerdomain-common.c switch (bank) { bank 87 arch/arm/mach-omap2/powerdomain-common.c u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank) bank 89 arch/arm/mach-omap2/powerdomain-common.c switch (bank) { bank 665 arch/arm/mach-omap2/powerdomain.c int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) bank 672 arch/arm/mach-omap2/powerdomain.c if (pwrdm->banks < (bank + 1)) bank 675 arch/arm/mach-omap2/powerdomain.c if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst))) bank 679 arch/arm/mach-omap2/powerdomain.c pwrdm->name, bank, pwrst); bank 682 arch/arm/mach-omap2/powerdomain.c ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst); bank 703 arch/arm/mach-omap2/powerdomain.c int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) bank 710 arch/arm/mach-omap2/powerdomain.c if (pwrdm->banks < (bank + 1)) bank 713 arch/arm/mach-omap2/powerdomain.c if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst))) bank 717 arch/arm/mach-omap2/powerdomain.c pwrdm->name, bank, pwrst); bank 720 arch/arm/mach-omap2/powerdomain.c ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst); bank 799 arch/arm/mach-omap2/powerdomain.c int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) bank 806 arch/arm/mach-omap2/powerdomain.c if (pwrdm->banks < (bank + 1)) bank 810 arch/arm/mach-omap2/powerdomain.c bank = 1; bank 813 arch/arm/mach-omap2/powerdomain.c ret = arch_pwrdm->pwrdm_read_mem_pwrst(pwrdm, bank); bank 829 arch/arm/mach-omap2/powerdomain.c int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) bank 836 arch/arm/mach-omap2/powerdomain.c if (pwrdm->banks < (bank + 1)) bank 840 arch/arm/mach-omap2/powerdomain.c bank = 1; bank 843 arch/arm/mach-omap2/powerdomain.c ret = arch_pwrdm->pwrdm_read_prev_mem_pwrst(pwrdm, bank); bank 858 arch/arm/mach-omap2/powerdomain.c int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) bank 865 arch/arm/mach-omap2/powerdomain.c if (pwrdm->banks < (bank + 1)) bank 869 arch/arm/mach-omap2/powerdomain.c ret = arch_pwrdm->pwrdm_read_mem_retst(pwrdm, bank); bank 185 arch/arm/mach-omap2/powerdomain.h int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); bank 186 arch/arm/mach-omap2/powerdomain.h int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); bank 190 arch/arm/mach-omap2/powerdomain.h int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); bank 191 arch/arm/mach-omap2/powerdomain.h int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); bank 192 arch/arm/mach-omap2/powerdomain.h int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); bank 228 arch/arm/mach-omap2/powerdomain.h int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); bank 229 arch/arm/mach-omap2/powerdomain.h int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); bank 234 arch/arm/mach-omap2/powerdomain.h int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); bank 235 arch/arm/mach-omap2/powerdomain.h int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); bank 236 arch/arm/mach-omap2/powerdomain.h int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); bank 266 arch/arm/mach-omap2/powerdomain.h extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); bank 267 arch/arm/mach-omap2/powerdomain.h extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); bank 268 arch/arm/mach-omap2/powerdomain.h extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); bank 111 arch/arm/mach-omap2/prm2xxx_3xxx.c int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, bank 116 arch/arm/mach-omap2/prm2xxx_3xxx.c m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); bank 124 arch/arm/mach-omap2/prm2xxx_3xxx.c int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, bank 129 arch/arm/mach-omap2/prm2xxx_3xxx.c m = omap2_pwrdm_get_mem_bank_retst_mask(bank); bank 137 arch/arm/mach-omap2/prm2xxx_3xxx.c int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) bank 141 arch/arm/mach-omap2/prm2xxx_3xxx.c m = omap2_pwrdm_get_mem_bank_stst_mask(bank); bank 147 arch/arm/mach-omap2/prm2xxx_3xxx.c int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) bank 151 arch/arm/mach-omap2/prm2xxx_3xxx.c m = omap2_pwrdm_get_mem_bank_retst_mask(bank); bank 110 arch/arm/mach-omap2/prm2xxx_3xxx.h extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, bank 112 arch/arm/mach-omap2/prm2xxx_3xxx.h extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, bank 114 arch/arm/mach-omap2/prm2xxx_3xxx.h extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); bank 115 arch/arm/mach-omap2/prm2xxx_3xxx.h extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); bank 235 arch/arm/mach-omap2/prm33xx.c static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, bank 240 arch/arm/mach-omap2/prm33xx.c m = pwrdm->mem_on_mask[bank]; bank 250 arch/arm/mach-omap2/prm33xx.c static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, bank 255 arch/arm/mach-omap2/prm33xx.c m = pwrdm->mem_ret_mask[bank]; bank 265 arch/arm/mach-omap2/prm33xx.c static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) bank 269 arch/arm/mach-omap2/prm33xx.c m = pwrdm->mem_pwrst_mask[bank]; bank 280 arch/arm/mach-omap2/prm33xx.c static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) bank 284 arch/arm/mach-omap2/prm33xx.c m = pwrdm->mem_retst_mask[bank]; bank 587 arch/arm/mach-omap2/prm3xxx.c static int omap3_get_mem_bank_lastmemst_mask(u8 bank) bank 589 arch/arm/mach-omap2/prm3xxx.c switch (bank) { bank 605 arch/arm/mach-omap2/prm3xxx.c static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) bank 609 arch/arm/mach-omap2/prm3xxx.c m = omap3_get_mem_bank_lastmemst_mask(bank); bank 502 arch/arm/mach-omap2/prm44xx.c static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, bank 507 arch/arm/mach-omap2/prm44xx.c m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); bank 516 arch/arm/mach-omap2/prm44xx.c static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, bank 521 arch/arm/mach-omap2/prm44xx.c m = omap2_pwrdm_get_mem_bank_retst_mask(bank); bank 582 arch/arm/mach-omap2/prm44xx.c static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) bank 586 arch/arm/mach-omap2/prm44xx.c m = omap2_pwrdm_get_mem_bank_stst_mask(bank); bank 596 arch/arm/mach-omap2/prm44xx.c static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) bank 600 arch/arm/mach-omap2/prm44xx.c m = omap2_pwrdm_get_mem_bank_retst_mask(bank); bank 624 arch/arm/mach-omap2/prm44xx.c static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) bank 636 arch/arm/mach-omap2/prm44xx.c return omap4_pwrdm_read_mem_retst(pwrdm, bank); bank 20 arch/arm/mach-pxa/generic.h mi->bank[__nr].start = (__start), \ bank 21 arch/arm/mach-pxa/generic.h mi->bank[__nr].size = (__size) bank 55 arch/arm/mach-pxa/mfp-pxa2xx.c int bank = gpio_to_bank(gpio); bank 65 arch/arm/mach-pxa/mfp-pxa2xx.c gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank); bank 69 arch/arm/mach-pxa/mfp-pxa2xx.c GAFR_L(bank) = gafr; bank 71 arch/arm/mach-pxa/mfp-pxa2xx.c GAFR_U(bank) = gafr; bank 81 arch/arm/mach-pxa/mfp-pxa2xx.c PGSR(bank) |= mask; bank 85 arch/arm/mach-pxa/mfp-pxa2xx.c PGSR(bank) &= ~mask; bank 99 arch/arm/mach-pxa/mfp-pxa2xx.c gpdr_lpm[bank] |= mask; bank 101 arch/arm/mach-pxa/mfp-pxa2xx.c gpdr_lpm[bank] &= ~mask; bank 35 arch/arm/mach-s3c24xx/iotiming-s3c2410.c int bank; bank 37 arch/arm/mach-s3c24xx/iotiming-s3c2410.c for (bank = 0; bank < MAX_BANKS; bank++) { bank 38 arch/arm/mach-s3c24xx/iotiming-s3c2410.c bt = timings->bank[bank].io_2410; bank 43 arch/arm/mach-s3c24xx/iotiming-s3c2410.c "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank, bank 56 arch/arm/mach-s3c24xx/iotiming-s3c2410.c static inline void __iomem *bank_reg(unsigned int bank) bank 58 arch/arm/mach-s3c24xx/iotiming-s3c2410.c return S3C2410_BANKCON0 + (bank << 2); bank 362 arch/arm/mach-s3c24xx/iotiming-s3c2410.c int bank; bank 365 arch/arm/mach-s3c24xx/iotiming-s3c2410.c for (bank = 0; bank < MAX_BANKS; bank++) { bank 366 arch/arm/mach-s3c24xx/iotiming-s3c2410.c bankcon = __raw_readl(bank_reg(bank)); bank 367 arch/arm/mach-s3c24xx/iotiming-s3c2410.c bt = iot->bank[bank].io_2410; bank 377 arch/arm/mach-s3c24xx/iotiming-s3c2410.c __func__, bank); bank 382 arch/arm/mach-s3c24xx/iotiming-s3c2410.c __func__, bank, bt->bankcon); bank 403 arch/arm/mach-s3c24xx/iotiming-s3c2410.c int bank; bank 407 arch/arm/mach-s3c24xx/iotiming-s3c2410.c for (bank = 0; bank < MAX_BANKS; bank++) { bank 408 arch/arm/mach-s3c24xx/iotiming-s3c2410.c bt = iot->bank[bank].io_2410; bank 412 arch/arm/mach-s3c24xx/iotiming-s3c2410.c __raw_writel(bt->bankcon, bank_reg(bank)); bank 437 arch/arm/mach-s3c24xx/iotiming-s3c2410.c int bank; bank 443 arch/arm/mach-s3c24xx/iotiming-s3c2410.c for (bank = 0; bank < MAX_BANKS; bank++) { bank 444 arch/arm/mach-s3c24xx/iotiming-s3c2410.c bankcon = __raw_readl(bank_reg(bank)); bank 450 arch/arm/mach-s3c24xx/iotiming-s3c2410.c __func__, bank, bankcon); bank 458 arch/arm/mach-s3c24xx/iotiming-s3c2410.c if (bank != 0) { bank 459 arch/arm/mach-s3c24xx/iotiming-s3c2410.c unsigned long tmp = S3C2410_BWSCON_GET(bwscon, bank); bank 464 arch/arm/mach-s3c24xx/iotiming-s3c2410.c timings->bank[bank].io_2410 = bt; bank 41 arch/arm/mach-s3c24xx/iotiming-s3c2412.c unsigned int bank; bank 43 arch/arm/mach-s3c24xx/iotiming-s3c2412.c for (bank = 0; bank < MAX_BANKS; bank++) { bank 44 arch/arm/mach-s3c24xx/iotiming-s3c2412.c bt = iot->bank[bank].io_2412; bank 49 arch/arm/mach-s3c24xx/iotiming-s3c2412.c "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank, bank 142 arch/arm/mach-s3c24xx/iotiming-s3c2412.c int bank; bank 145 arch/arm/mach-s3c24xx/iotiming-s3c2412.c for (bank = 0; bank < MAX_BANKS; bank++) { bank 146 arch/arm/mach-s3c24xx/iotiming-s3c2412.c bt = iot->bank[bank].io_2412; bank 153 arch/arm/mach-s3c24xx/iotiming-s3c2412.c __func__, bank); bank 176 arch/arm/mach-s3c24xx/iotiming-s3c2412.c int bank; bank 180 arch/arm/mach-s3c24xx/iotiming-s3c2412.c for (bank = 0; bank < MAX_BANKS; bank++) { bank 181 arch/arm/mach-s3c24xx/iotiming-s3c2412.c bt = iot->bank[bank].io_2412; bank 185 arch/arm/mach-s3c24xx/iotiming-s3c2412.c regs = S3C2412_SSMC_BANK(bank); bank 203 arch/arm/mach-s3c24xx/iotiming-s3c2412.c unsigned int bank) bank 206 arch/arm/mach-s3c24xx/iotiming-s3c2412.c void __iomem *regs = S3C2412_SSMC_BANK(bank); bank 220 arch/arm/mach-s3c24xx/iotiming-s3c2412.c static inline bool bank_is_io(unsigned int bank, u32 bankcfg) bank 222 arch/arm/mach-s3c24xx/iotiming-s3c2412.c if (bank < 2) bank 225 arch/arm/mach-s3c24xx/iotiming-s3c2412.c return !(bankcfg & (1 << bank)); bank 233 arch/arm/mach-s3c24xx/iotiming-s3c2412.c unsigned int bank; bank 237 arch/arm/mach-s3c24xx/iotiming-s3c2412.c for (bank = 0; bank < MAX_BANKS; bank++) { bank 238 arch/arm/mach-s3c24xx/iotiming-s3c2412.c if (!bank_is_io(bank, bankcfg)) bank 245 arch/arm/mach-s3c24xx/iotiming-s3c2412.c timings->bank[bank].io_2412 = bt; bank 246 arch/arm/mach-s3c24xx/iotiming-s3c2412.c s3c2412_iotiming_getbank(cfg, bt, bank); bank 18 arch/arm/mach-sa1100/generic.h mi->bank[__nr].start = (__start), \ bank 19 arch/arm/mach-sa1100/generic.h mi->bank[__nr].size = (__size) bank 88 arch/arm/plat-samsung/include/plat/cpu-freq-core.h union s3c_iobank bank[MAX_BANKS]; bank 42 arch/ia64/include/asm/numa.h int bank; /* which mem bank on this node */ bank 458 arch/ia64/include/asm/sal.h bank : 1, bank 477 arch/ia64/include/asm/sal.h u16 bank; bank 472 arch/ia64/kernel/acpi.c int bank; bank 474 arch/ia64/kernel/acpi.c bank = 0; bank 477 arch/ia64/kernel/acpi.c node_memblk[j].bank = bank++; bank 897 arch/ia64/kernel/mca.c const u64 *bank; bank 930 arch/ia64/kernel/mca.c bank = ms->pmsa_bank1_gr; bank 932 arch/ia64/kernel/mca.c bank = ms->pmsa_bank0_gr; bank 933 arch/ia64/kernel/mca.c copy_reg(&bank[16-16], ms->pmsa_nat_bits, ®s->r16, nat); bank 934 arch/ia64/kernel/mca.c copy_reg(&bank[17-16], ms->pmsa_nat_bits, ®s->r17, nat); bank 935 arch/ia64/kernel/mca.c copy_reg(&bank[18-16], ms->pmsa_nat_bits, ®s->r18, nat); bank 936 arch/ia64/kernel/mca.c copy_reg(&bank[19-16], ms->pmsa_nat_bits, ®s->r19, nat); bank 937 arch/ia64/kernel/mca.c copy_reg(&bank[20-16], ms->pmsa_nat_bits, ®s->r20, nat); bank 938 arch/ia64/kernel/mca.c copy_reg(&bank[21-16], ms->pmsa_nat_bits, ®s->r21, nat); bank 939 arch/ia64/kernel/mca.c copy_reg(&bank[22-16], ms->pmsa_nat_bits, ®s->r22, nat); bank 940 arch/ia64/kernel/mca.c copy_reg(&bank[23-16], ms->pmsa_nat_bits, ®s->r23, nat); bank 941 arch/ia64/kernel/mca.c copy_reg(&bank[24-16], ms->pmsa_nat_bits, ®s->r24, nat); bank 942 arch/ia64/kernel/mca.c copy_reg(&bank[25-16], ms->pmsa_nat_bits, ®s->r25, nat); bank 943 arch/ia64/kernel/mca.c copy_reg(&bank[26-16], ms->pmsa_nat_bits, ®s->r26, nat); bank 944 arch/ia64/kernel/mca.c copy_reg(&bank[27-16], ms->pmsa_nat_bits, ®s->r27, nat); bank 945 arch/ia64/kernel/mca.c copy_reg(&bank[28-16], ms->pmsa_nat_bits, ®s->r28, nat); bank 946 arch/ia64/kernel/mca.c copy_reg(&bank[29-16], ms->pmsa_nat_bits, ®s->r29, nat); bank 947 arch/ia64/kernel/mca.c copy_reg(&bank[30-16], ms->pmsa_nat_bits, ®s->r30, nat); bank 948 arch/ia64/kernel/mca.c copy_reg(&bank[31-16], ms->pmsa_nat_bits, ®s->r31, nat); bank 27 arch/mips/jz4740/setup.c u32 ctrl, bus, bank, rows, cols; bank 33 arch/mips/jz4740/setup.c bank = 1 + ((ctrl >> 19) & 1); bank 38 arch/mips/jz4740/setup.c bus, bank, rows, cols); bank 41 arch/mips/jz4740/setup.c size = 1 << (bus + bank + cols + rows); bank 37 arch/mips/sgi-ip22/ip22-mc.c static inline unsigned int get_bank_config(int bank) bank 39 arch/mips/sgi-ip22/ip22-mc.c unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0; bank 40 arch/mips/sgi-ip22/ip22-mc.c return bank % 2 ? res & 0xffff : res >> 16; bank 54 arch/mips/sgi-ip22/ip22-mc.c struct mem bank[4]; bank 58 arch/mips/sgi-ip22/ip22-mc.c for (i = 0; i < ARRAY_SIZE(bank); i++) { bank 63 arch/mips/sgi-ip22/ip22-mc.c bank[cnt].size = get_bank_size(tmp); bank 64 arch/mips/sgi-ip22/ip22-mc.c bank[cnt].addr = get_bank_addr(tmp); bank 66 arch/mips/sgi-ip22/ip22-mc.c i, bank[cnt].size / 1024 / 1024, bank[cnt].addr); bank 76 arch/mips/sgi-ip22/ip22-mc.c if (bank[i-1].addr > bank[i].addr) { bank 77 arch/mips/sgi-ip22/ip22-mc.c addr = bank[i].addr; bank 78 arch/mips/sgi-ip22/ip22-mc.c size = bank[i].size; bank 79 arch/mips/sgi-ip22/ip22-mc.c bank[i].addr = bank[i-1].addr; bank 80 arch/mips/sgi-ip22/ip22-mc.c bank[i].size = bank[i-1].size; bank 81 arch/mips/sgi-ip22/ip22-mc.c bank[i-1].addr = addr; bank 82 arch/mips/sgi-ip22/ip22-mc.c bank[i-1].size = size; bank 91 arch/mips/sgi-ip22/ip22-mc.c if (space[j].addr + space[j].size == bank[i].addr) { bank 92 arch/mips/sgi-ip22/ip22-mc.c space[j].size += bank[i].size; bank 99 arch/mips/sgi-ip22/ip22-mc.c bank[i].addr); bank 25 arch/mips/sgi-ip32/ip32-memory.c int bank; bank 29 arch/mips/sgi-ip32/ip32-memory.c for (bank=0; bank < CRIME_MAXBANKS; bank++) { bank 30 arch/mips/sgi-ip32/ip32-memory.c u64 bankctl = crime->bank_ctrl[bank]; bank 32 arch/mips/sgi-ip32/ip32-memory.c if (bank != 0 && base == 0) bank 40 arch/mips/sgi-ip32/ip32-memory.c bank, base, size >> 20); bank 204 arch/powerpc/boot/4xx.c u32 cs, col, row, bank, dpath; bank 247 arch/powerpc/boot/4xx.c bank = 8; /* 8 banks */ bank 249 arch/powerpc/boot/4xx.c bank = 4; /* 4 banks */ bank 251 arch/powerpc/boot/4xx.c memsize = cs * (1 << (col+row)) * bank * dpath; bank 91 arch/powerpc/include/asm/fsl_lbc.h struct fsl_lbc_bank bank[12]; bank 233 arch/powerpc/platforms/85xx/p1022_ds.c br0 = in_be32(&lbc->bank[0].br); bank 234 arch/powerpc/platforms/85xx/p1022_ds.c br1 = in_be32(&lbc->bank[1].br); bank 235 arch/powerpc/platforms/85xx/p1022_ds.c or0 = in_be32(&lbc->bank[0].or); bank 236 arch/powerpc/platforms/85xx/p1022_ds.c or1 = in_be32(&lbc->bank[1].or); bank 252 arch/powerpc/platforms/85xx/p1022_ds.c out_be32(&lbc->bank[0].br, br0); bank 253 arch/powerpc/platforms/85xx/p1022_ds.c out_be32(&lbc->bank[0].or, or0); bank 258 arch/powerpc/platforms/85xx/p1022_ds.c out_be32(&lbc->bank[1].br, br1); bank 259 arch/powerpc/platforms/85xx/p1022_ds.c out_be32(&lbc->bank[1].or, or1); bank 79 arch/powerpc/platforms/powermac/nvram.c static int (*core99_write_bank)(int bank, u8* datas); bank 80 arch/powerpc/platforms/powermac/nvram.c static int (*core99_erase_bank)(int bank); bank 280 arch/powerpc/platforms/powermac/nvram.c static int sm_erase_bank(int bank) bank 287 arch/powerpc/platforms/powermac/nvram.c DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank); bank 311 arch/powerpc/platforms/powermac/nvram.c static int sm_write_bank(int bank, u8* datas) bank 318 arch/powerpc/platforms/powermac/nvram.c DBG("nvram: Sharp/Micron Writing bank %d...\n", bank); bank 345 arch/powerpc/platforms/powermac/nvram.c static int amd_erase_bank(int bank) bank 352 arch/powerpc/platforms/powermac/nvram.c DBG("nvram: AMD Erasing bank %d...\n", bank); bank 391 arch/powerpc/platforms/powermac/nvram.c static int amd_write_bank(int bank, u8* datas) bank 398 arch/powerpc/platforms/powermac/nvram.c DBG("nvram: AMD Writing bank %d...\n", bank); bank 73 arch/powerpc/sysdev/fsl_lbc.c for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) { bank 74 arch/powerpc/sysdev/fsl_lbc.c u32 br = in_be32(&lbc->bank[i].br); bank 75 arch/powerpc/sysdev/fsl_lbc.c u32 or = in_be32(&lbc->bank[i].or); bank 96 arch/powerpc/sysdev/fsl_lbc.c int bank; bank 100 arch/powerpc/sysdev/fsl_lbc.c bank = fsl_lbc_find(addr_base); bank 101 arch/powerpc/sysdev/fsl_lbc.c if (bank < 0) bank 102 arch/powerpc/sysdev/fsl_lbc.c return bank; bank 108 arch/powerpc/sysdev/fsl_lbc.c br = in_be32(&lbc->bank[bank].br); bank 81 arch/um/drivers/pty.c char *pty, *bank, *cp; bank 85 arch/um/drivers/pty.c for (bank = "pqrs"; *bank; bank++) { bank 86 arch/um/drivers/pty.c line[strlen("/dev/pty")] = *bank; bank 26 arch/unicore32/include/asm/memblock.h struct membank bank[NR_BANKS]; bank 34 arch/unicore32/include/asm/memblock.h #define bank_pfn_start(bank) __phys_to_pfn((bank)->start) bank 35 arch/unicore32/include/asm/memblock.h #define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size) bank 36 arch/unicore32/include/asm/memblock.h #define bank_pfn_size(bank) ((bank)->size >> PAGE_SHIFT) bank 37 arch/unicore32/include/asm/memblock.h #define bank_phys_start(bank) ((bank)->start) bank 38 arch/unicore32/include/asm/memblock.h #define bank_phys_end(bank) ((bank)->start + (bank)->size) bank 39 arch/unicore32/include/asm/memblock.h #define bank_phys_size(bank) ((bank)->size) bank 132 arch/unicore32/kernel/setup.c struct membank *bank = &meminfo.bank[meminfo.nr_banks]; bank 146 arch/unicore32/kernel/setup.c bank->start = PAGE_ALIGN(start); bank 147 arch/unicore32/kernel/setup.c bank->size = size & PAGE_MASK; bank 153 arch/unicore32/kernel/setup.c if (bank->size == 0) bank 203 arch/unicore32/kernel/setup.c if (mi->bank[i].size == 0) bank 212 arch/unicore32/kernel/setup.c res->start = mi->bank[i].start; bank 213 arch/unicore32/kernel/setup.c res->end = mi->bank[i].start + mi->bank[i].size - 1; bank 47 arch/unicore32/mm/init.c struct membank *bank = &mi->bank[i]; bank 50 arch/unicore32/mm/init.c start = bank_pfn_start(bank); bank 51 arch/unicore32/mm/init.c end = bank_pfn_end(bank); bank 57 arch/unicore32/mm/init.c if (bank->highmem) bank 127 arch/unicore32/mm/init.c sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), bank 131 arch/unicore32/mm/init.c memblock_add(mi->bank[i].start, mi->bank[i].size); bank 239 arch/unicore32/mm/init.c struct membank *bank = &mi->bank[i]; bank 241 arch/unicore32/mm/init.c bank_start = bank_pfn_start(bank); bank 255 arch/unicore32/mm/init.c prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES); bank 288 arch/unicore32/mm/mmu.c struct membank *bank = &meminfo.bank[j]; bank 289 arch/unicore32/mm/mmu.c *bank = meminfo.bank[i]; bank 159 arch/x86/events/amd/iommu.c u32 shift, bank, cntr; bank 165 arch/x86/events/amd/iommu.c for (bank = 0, shift = 0; bank < max_banks; bank++) { bank 167 arch/x86/events/amd/iommu.c shift = bank + (bank*3) + cntr; bank 172 arch/x86/events/amd/iommu.c event->hw.iommu_bank = bank; bank 186 arch/x86/events/amd/iommu.c u8 bank, u8 cntr) bank 195 arch/x86/events/amd/iommu.c if ((bank > max_banks) || (cntr > max_cntrs)) bank 198 arch/x86/events/amd/iommu.c shift = bank + cntr + (bank*3); bank 242 arch/x86/events/amd/iommu.c u8 bank = hwc->iommu_bank; bank 247 arch/x86/events/amd/iommu.c amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, ®); bank 253 arch/x86/events/amd/iommu.c amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, ®); bank 259 arch/x86/events/amd/iommu.c amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_PASID_MATCH_REG, ®); bank 265 arch/x86/events/amd/iommu.c amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DOMID_MATCH_REG, ®); bank 35 arch/x86/events/amd/iommu.h extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, bank 38 arch/x86/events/amd/iommu.h extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, bank 37 arch/x86/include/asm/amd_nb.h unsigned int bank; /* MCA bank the block belongs to */ bank 236 arch/x86/include/asm/mce.h extern void mce_disable_bank(int bank); bank 27 arch/x86/include/uapi/asm/mce.h __u8 bank; /* Machine check bank reporting the error */ bank 119 arch/x86/kernel/cpu/mce/amd.c static enum smca_bank_types smca_get_bank_type(unsigned int bank) bank 123 arch/x86/kernel/cpu/mce/amd.c if (bank >= MAX_NR_BANKS) bank 126 arch/x86/kernel/cpu/mce/amd.c b = &smca_banks[bank]; bank 207 arch/x86/kernel/cpu/mce/amd.c static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) bank 215 arch/x86/kernel/cpu/mce/amd.c if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) bank 221 arch/x86/kernel/cpu/mce/amd.c if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) bank 225 arch/x86/kernel/cpu/mce/amd.c per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); bank 229 arch/x86/kernel/cpu/mce/amd.c static void smca_configure(unsigned int bank, unsigned int cpu) bank 234 arch/x86/kernel/cpu/mce/amd.c u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); bank 266 arch/x86/kernel/cpu/mce/amd.c smca_set_misc_banks_map(bank, cpu); bank 269 arch/x86/kernel/cpu/mce/amd.c if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0) bank 272 arch/x86/kernel/cpu/mce/amd.c if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { bank 273 arch/x86/kernel/cpu/mce/amd.c pr_warn("Failed to read MCA_IPID for bank %d\n", bank); bank 283 arch/x86/kernel/cpu/mce/amd.c smca_banks[bank].hwid = s_hwid; bank 284 arch/x86/kernel/cpu/mce/amd.c smca_banks[bank].id = low; bank 285 arch/x86/kernel/cpu/mce/amd.c smca_banks[bank].sysfs_id = s_hwid->count++; bank 299 arch/x86/kernel/cpu/mce/amd.c static inline bool is_shared_bank(int bank) bank 309 arch/x86/kernel/cpu/mce/amd.c return (bank == 4); bank 332 arch/x86/kernel/cpu/mce/amd.c static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) bank 337 arch/x86/kernel/cpu/mce/amd.c if (bank == 4) bank 354 arch/x86/kernel/cpu/mce/amd.c b->bank, b->block, b->address, hi, lo); bank 369 arch/x86/kernel/cpu/mce/amd.c b->cpu, apic, b->bank, b->block, b->address, hi, lo); bank 478 arch/x86/kernel/cpu/mce/amd.c static u32 smca_get_block_address(unsigned int bank, unsigned int block, bank 482 arch/x86/kernel/cpu/mce/amd.c return MSR_AMD64_SMCA_MCx_MISC(bank); bank 484 arch/x86/kernel/cpu/mce/amd.c if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank))) bank 487 arch/x86/kernel/cpu/mce/amd.c return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); bank 491 arch/x86/kernel/cpu/mce/amd.c unsigned int bank, unsigned int block, bank 496 arch/x86/kernel/cpu/mce/amd.c if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) bank 500 arch/x86/kernel/cpu/mce/amd.c return smca_get_block_address(bank, block, cpu); bank 505 arch/x86/kernel/cpu/mce/amd.c addr = msr_ops.misc(bank); bank 519 arch/x86/kernel/cpu/mce/amd.c prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, bank 528 arch/x86/kernel/cpu/mce/amd.c per_cpu(bank_map, cpu) |= (1 << bank); bank 532 arch/x86/kernel/cpu/mce/amd.c b.bank = bank; bank 535 arch/x86/kernel/cpu/mce/amd.c b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); bank 567 arch/x86/kernel/cpu/mce/amd.c enum smca_bank_types bank_type = smca_get_bank_type(m->bank); bank 586 arch/x86/kernel/cpu/mce/amd.c void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) bank 593 arch/x86/kernel/cpu/mce/amd.c if (c->x86 == 0x15 && bank == 4) { bank 600 arch/x86/kernel/cpu/mce/amd.c if (smca_get_bank_type(bank) != SMCA_IF) bank 603 arch/x86/kernel/cpu/mce/amd.c msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); bank 628 arch/x86/kernel/cpu/mce/amd.c unsigned int bank, block, cpu = smp_processor_id(); bank 633 arch/x86/kernel/cpu/mce/amd.c for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { bank 635 arch/x86/kernel/cpu/mce/amd.c smca_configure(bank, cpu); bank 637 arch/x86/kernel/cpu/mce/amd.c disable_err_thresholding(c, bank); bank 640 arch/x86/kernel/cpu/mce/amd.c address = get_block_address(address, low, high, bank, block, cpu); bank 654 arch/x86/kernel/cpu/mce/amd.c offset = prepare_threshold_block(bank, block, address, offset, high); bank 868 arch/x86/kernel/cpu/mce/amd.c return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0; bank 870 arch/x86/kernel/cpu/mce/amd.c return m->bank == 4 && xec == 0x8; bank 873 arch/x86/kernel/cpu/mce/amd.c static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) bank 881 arch/x86/kernel/cpu/mce/amd.c m.bank = bank; bank 899 arch/x86/kernel/cpu/mce/amd.c rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); bank 902 arch/x86/kernel/cpu/mce/amd.c rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); bank 922 arch/x86/kernel/cpu/mce/amd.c _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) bank 933 arch/x86/kernel/cpu/mce/amd.c __log_error(bank, status, addr, misc); bank 949 arch/x86/kernel/cpu/mce/amd.c static void log_error_deferred(unsigned int bank) bank 953 arch/x86/kernel/cpu/mce/amd.c defrd = _log_error_bank(bank, msr_ops.status(bank), bank 954 arch/x86/kernel/cpu/mce/amd.c msr_ops.addr(bank), 0); bank 961 arch/x86/kernel/cpu/mce/amd.c wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); bank 969 arch/x86/kernel/cpu/mce/amd.c _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), bank 970 arch/x86/kernel/cpu/mce/amd.c MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); bank 976 arch/x86/kernel/cpu/mce/amd.c unsigned int bank; bank 978 arch/x86/kernel/cpu/mce/amd.c for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) bank 979 arch/x86/kernel/cpu/mce/amd.c log_error_deferred(bank); bank 982 arch/x86/kernel/cpu/mce/amd.c static void log_error_thresholding(unsigned int bank, u64 misc) bank 984 arch/x86/kernel/cpu/mce/amd.c _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); bank 1002 arch/x86/kernel/cpu/mce/amd.c log_error_thresholding(block->bank, ((u64)high << 32) | low); bank 1017 arch/x86/kernel/cpu/mce/amd.c unsigned int bank, cpu = smp_processor_id(); bank 1019 arch/x86/kernel/cpu/mce/amd.c for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { bank 1020 arch/x86/kernel/cpu/mce/amd.c if (!(per_cpu(bank_map, cpu) & (1 << bank))) bank 1023 arch/x86/kernel/cpu/mce/amd.c first_block = per_cpu(threshold_banks, cpu)[bank]->blocks; bank 1172 arch/x86/kernel/cpu/mce/amd.c static const char *get_name(unsigned int bank, struct threshold_block *b) bank 1177 arch/x86/kernel/cpu/mce/amd.c if (b && bank == 4) bank 1180 arch/x86/kernel/cpu/mce/amd.c return th_names[bank]; bank 1183 arch/x86/kernel/cpu/mce/amd.c bank_type = smca_get_bank_type(bank); bank 1193 arch/x86/kernel/cpu/mce/amd.c if (smca_banks[bank].hwid->count == 1) bank 1198 arch/x86/kernel/cpu/mce/amd.c smca_banks[bank].sysfs_id); bank 1203 arch/x86/kernel/cpu/mce/amd.c unsigned int bank, unsigned int block, bank 1210 arch/x86/kernel/cpu/mce/amd.c if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) bank 1232 arch/x86/kernel/cpu/mce/amd.c b->bank = bank; bank 1236 arch/x86/kernel/cpu/mce/amd.c b->interrupt_capable = lvt_interrupt_supported(bank, high); bank 1253 arch/x86/kernel/cpu/mce/amd.c err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(bank, b)); bank 1257 arch/x86/kernel/cpu/mce/amd.c address = get_block_address(address, low, high, bank, ++block, cpu); bank 1261 arch/x86/kernel/cpu/mce/amd.c err = allocate_threshold_blocks(cpu, tb, bank, block, address); bank 1303 arch/x86/kernel/cpu/mce/amd.c static int threshold_create_bank(unsigned int cpu, unsigned int bank) bank 1308 arch/x86/kernel/cpu/mce/amd.c const char *name = get_name(bank, NULL); bank 1314 arch/x86/kernel/cpu/mce/amd.c if (is_shared_bank(bank)) { bank 1325 arch/x86/kernel/cpu/mce/amd.c per_cpu(threshold_banks, cpu)[bank] = b; bank 1346 arch/x86/kernel/cpu/mce/amd.c if (is_shared_bank(bank)) { bank 1356 arch/x86/kernel/cpu/mce/amd.c err = allocate_threshold_blocks(cpu, b, bank, 0, msr_ops.misc(bank)); bank 1360 arch/x86/kernel/cpu/mce/amd.c per_cpu(threshold_banks, cpu)[bank] = b; bank 1376 arch/x86/kernel/cpu/mce/amd.c static void deallocate_threshold_block(unsigned int cpu, unsigned int bank) bank 1380 arch/x86/kernel/cpu/mce/amd.c struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; bank 1404 arch/x86/kernel/cpu/mce/amd.c static void threshold_remove_bank(unsigned int cpu, int bank) bank 1409 arch/x86/kernel/cpu/mce/amd.c b = per_cpu(threshold_banks, cpu)[bank]; bank 1416 arch/x86/kernel/cpu/mce/amd.c if (is_shared_bank(bank)) { bank 1419 arch/x86/kernel/cpu/mce/amd.c per_cpu(threshold_banks, cpu)[bank] = NULL; bank 1431 arch/x86/kernel/cpu/mce/amd.c deallocate_threshold_block(cpu, bank); bank 1437 arch/x86/kernel/cpu/mce/amd.c per_cpu(threshold_banks, cpu)[bank] = NULL; bank 1442 arch/x86/kernel/cpu/mce/amd.c unsigned int bank; bank 1444 arch/x86/kernel/cpu/mce/amd.c for (bank = 0; bank < per_cpu(mce_num_banks, cpu); ++bank) { bank 1445 arch/x86/kernel/cpu/mce/amd.c if (!(per_cpu(bank_map, cpu) & (1 << bank))) bank 1447 arch/x86/kernel/cpu/mce/amd.c threshold_remove_bank(cpu, bank); bank 1457 arch/x86/kernel/cpu/mce/amd.c unsigned int bank; bank 1472 arch/x86/kernel/cpu/mce/amd.c for (bank = 0; bank < per_cpu(mce_num_banks, cpu); ++bank) { bank 1473 arch/x86/kernel/cpu/mce/amd.c if (!(per_cpu(bank_map, cpu) & (1 << bank))) bank 1475 arch/x86/kernel/cpu/mce/amd.c err = threshold_create_bank(cpu, bank); bank 37 arch/x86/kernel/cpu/mce/apei.c m.bank = -1; bank 81 arch/x86/kernel/cpu/mce/core.c u8 bank; /* bank number */ bank 124 arch/x86/kernel/cpu/mce/core.c static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); bank 197 arch/x86/kernel/cpu/mce/core.c static inline u32 ctl_reg(int bank) bank 199 arch/x86/kernel/cpu/mce/core.c return MSR_IA32_MCx_CTL(bank); bank 202 arch/x86/kernel/cpu/mce/core.c static inline u32 status_reg(int bank) bank 204 arch/x86/kernel/cpu/mce/core.c return MSR_IA32_MCx_STATUS(bank); bank 207 arch/x86/kernel/cpu/mce/core.c static inline u32 addr_reg(int bank) bank 209 arch/x86/kernel/cpu/mce/core.c return MSR_IA32_MCx_ADDR(bank); bank 212 arch/x86/kernel/cpu/mce/core.c static inline u32 misc_reg(int bank) bank 214 arch/x86/kernel/cpu/mce/core.c return MSR_IA32_MCx_MISC(bank); bank 217 arch/x86/kernel/cpu/mce/core.c static inline u32 smca_ctl_reg(int bank) bank 219 arch/x86/kernel/cpu/mce/core.c return MSR_AMD64_SMCA_MCx_CTL(bank); bank 222 arch/x86/kernel/cpu/mce/core.c static inline u32 smca_status_reg(int bank) bank 224 arch/x86/kernel/cpu/mce/core.c return MSR_AMD64_SMCA_MCx_STATUS(bank); bank 227 arch/x86/kernel/cpu/mce/core.c static inline u32 smca_addr_reg(int bank) bank 229 arch/x86/kernel/cpu/mce/core.c return MSR_AMD64_SMCA_MCx_ADDR(bank); bank 232 arch/x86/kernel/cpu/mce/core.c static inline u32 smca_misc_reg(int bank) bank 234 arch/x86/kernel/cpu/mce/core.c return MSR_AMD64_SMCA_MCx_MISC(bank); bank 249 arch/x86/kernel/cpu/mce/core.c m->mcgstatus, m->bank, m->status); bank 376 arch/x86/kernel/cpu/mce/core.c unsigned bank = __this_cpu_read(injectm.bank); bank 380 arch/x86/kernel/cpu/mce/core.c if (msr == msr_ops.status(bank)) bank 382 arch/x86/kernel/cpu/mce/core.c if (msr == msr_ops.addr(bank)) bank 384 arch/x86/kernel/cpu/mce/core.c if (msr == msr_ops.misc(bank)) bank 719 arch/x86/kernel/cpu/mce/core.c m.bank = i; bank 824 arch/x86/kernel/cpu/mce/core.c m->bank = i; bank 1163 arch/x86/kernel/cpu/mce/core.c m->bank = i; bank 1612 arch/x86/kernel/cpu/mce/core.c static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) bank 1614 arch/x86/kernel/cpu/mce/core.c if (bank != 0) bank 1916 arch/x86/kernel/cpu/mce/core.c int bank = *((int *)arg); bank 1917 arch/x86/kernel/cpu/mce/core.c __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); bank 1918 arch/x86/kernel/cpu/mce/core.c cmci_disable_bank(bank); bank 1921 arch/x86/kernel/cpu/mce/core.c void mce_disable_bank(int bank) bank 1923 arch/x86/kernel/cpu/mce/core.c if (bank >= this_cpu_read(mce_num_banks)) { bank 1926 arch/x86/kernel/cpu/mce/core.c bank); bank 1929 arch/x86/kernel/cpu/mce/core.c set_bit(bank, mce_banks_ce_disabled); bank 1930 arch/x86/kernel/cpu/mce/core.c on_each_cpu(__mce_disable_bank, &bank, 1); bank 2120 arch/x86/kernel/cpu/mce/core.c u8 bank = attr_to_bank(attr)->bank; bank 2123 arch/x86/kernel/cpu/mce/core.c if (bank >= per_cpu(mce_num_banks, s->id)) bank 2126 arch/x86/kernel/cpu/mce/core.c b = &per_cpu(mce_banks_array, s->id)[bank]; bank 2137 arch/x86/kernel/cpu/mce/core.c u8 bank = attr_to_bank(attr)->bank; bank 2144 arch/x86/kernel/cpu/mce/core.c if (bank >= per_cpu(mce_num_banks, s->id)) bank 2147 arch/x86/kernel/cpu/mce/core.c b = &per_cpu(mce_banks_array, s->id)[bank]; bank 2415 arch/x86/kernel/cpu/mce/core.c b->bank = i; bank 460 arch/x86/kernel/cpu/mce/inject.c u8 b = m.bank; bank 486 arch/x86/kernel/cpu/mce/inject.c u8 b = i_mce.bank; bank 576 arch/x86/kernel/cpu/mce/inject.c m->bank = val; bank 585 arch/x86/kernel/cpu/mce/inject.c MCE_INJECT_GET(bank); bank 155 arch/x86/kernel/cpu/mce/intel.c int bank; bank 160 arch/x86/kernel/cpu/mce/intel.c for_each_set_bit(bank, owned, MAX_NR_BANKS) { bank 161 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCx_CTL2(bank), val); bank 168 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCx_CTL2(bank), val); bank 353 arch/x86/kernel/cpu/mce/intel.c static void __cmci_disable_bank(int bank) bank 357 arch/x86/kernel/cpu/mce/intel.c if (!test_bit(bank, this_cpu_ptr(mce_banks_owned))) bank 359 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCx_CTL2(bank), val); bank 361 arch/x86/kernel/cpu/mce/intel.c wrmsrl(MSR_IA32_MCx_CTL2(bank), val); bank 362 arch/x86/kernel/cpu/mce/intel.c __clear_bit(bank, this_cpu_ptr(mce_banks_owned)); bank 413 arch/x86/kernel/cpu/mce/intel.c void cmci_disable_bank(int bank) bank 422 arch/x86/kernel/cpu/mce/intel.c __cmci_disable_bank(bank); bank 47 arch/x86/kernel/cpu/mce/internal.h void cmci_disable_bank(int bank); bank 52 arch/x86/kernel/cpu/mce/internal.h static inline void cmci_disable_bank(int bank) { } bank 91 arch/x86/kernel/cpu/mce/internal.h return m1->bank != m2->bank || bank 158 arch/x86/kernel/cpu/mce/internal.h u32 (*ctl) (int bank); bank 159 arch/x86/kernel/cpu/mce/internal.h u32 (*status) (int bank); bank 160 arch/x86/kernel/cpu/mce/internal.h u32 (*addr) (int bank); bank 161 arch/x86/kernel/cpu/mce/internal.h u32 (*misc) (int bank); bank 223 arch/x86/kernel/cpu/mce/severity.c u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); bank 1330 arch/x86/kvm/hyperv.c int i, bank, sbank = 0; bank 1334 arch/x86/kvm/hyperv.c for_each_set_bit(bank, (unsigned long *)&valid_bank_mask, bank 1336 arch/x86/kvm/hyperv.c vp_bitmap[bank] = sparse_banks[sbank++]; bank 3696 arch/x86/kvm/x86.c unsigned bank_num = mcg_cap & 0xff, bank; bank 3709 arch/x86/kvm/x86.c for (bank = 0; bank < bank_num; bank++) bank 3710 arch/x86/kvm/x86.c vcpu->arch.mce_banks[bank*4] = ~(u64)0; bank 3724 arch/x86/kvm/x86.c if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) bank 3733 arch/x86/kvm/x86.c banks += 4 * mce->bank; bank 51 arch/x86/platform/scx200/scx200_32.c int bank; bank 54 arch/x86/platform/scx200/scx200_32.c for (bank = 0; bank < 2; ++bank) bank 55 arch/x86/platform/scx200/scx200_32.c scx200_gpio_shadow[bank] = inl(scx200_gpio_base + 0x10 * bank); bank 64 drivers/acpi/acpi_extlog.c #define ELOG_IDX(cpu, bank) \ bank 65 drivers/acpi/acpi_extlog.c (cpu_physical_id(cpu) * l1_percpu_entry + (bank)) bank 73 drivers/acpi/acpi_extlog.c static struct acpi_hest_generic_status *extlog_elog_entry_check(int cpu, int bank) bank 80 drivers/acpi/acpi_extlog.c idx = ELOG_IDX(cpu, bank); bank 139 drivers/acpi/acpi_extlog.c int bank = mce->bank; bank 148 drivers/acpi/acpi_extlog.c estatus = extlog_elog_entry_check(cpu, bank); bank 35 drivers/bus/uniphier-system-bus.c struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; bank 39 drivers/bus/uniphier-system-bus.c int bank, u32 addr, u64 paddr, u32 size) bank 45 drivers/bus/uniphier-system-bus.c bank, addr, paddr, size); bank 47 drivers/bus/uniphier-system-bus.c if (bank >= ARRAY_SIZE(priv->bank)) { bank 48 drivers/bus/uniphier-system-bus.c dev_err(priv->dev, "unsupported bank number %d\n", bank); bank 52 drivers/bus/uniphier-system-bus.c if (priv->bank[bank].base || priv->bank[bank].end) { bank 54 drivers/bus/uniphier-system-bus.c "range for bank %d has already been specified\n", bank); bank 86 drivers/bus/uniphier-system-bus.c priv->bank[bank].base = paddr; bank 87 drivers/bus/uniphier-system-bus.c priv->bank[bank].end = end; bank 90 drivers/bus/uniphier-system-bus.c bank, priv->bank[bank].base, priv->bank[bank].end); bank 100 drivers/bus/uniphier-system-bus.c for (i = 0; i < ARRAY_SIZE(priv->bank); i++) { bank 101 drivers/bus/uniphier-system-bus.c for (j = i + 1; j < ARRAY_SIZE(priv->bank); j++) { bank 102 drivers/bus/uniphier-system-bus.c if (priv->bank[i].end > priv->bank[j].base && bank 103 drivers/bus/uniphier-system-bus.c priv->bank[i].base < priv->bank[j].end) { bank 130 drivers/bus/uniphier-system-bus.c swap(priv->bank[0], priv->bank[1]); bank 140 drivers/bus/uniphier-system-bus.c for (i = 0; i < ARRAY_SIZE(priv->bank); i++) { bank 141 drivers/bus/uniphier-system-bus.c base = priv->bank[i].base; bank 142 drivers/bus/uniphier-system-bus.c end = priv->bank[i].end; bank 182 drivers/bus/uniphier-system-bus.c int pna, bank, rlen, rone, ret; bank 226 drivers/bus/uniphier-system-bus.c bank = be32_to_cpup(ranges++); bank 234 drivers/bus/uniphier-system-bus.c ret = uniphier_system_bus_add_bank(priv, bank, addr, bank 815 drivers/char/tpm/tpm2-cmd.c struct tpm_bank_info *bank = chip->allocated_banks + bank_index; bank 816 drivers/char/tpm/tpm2-cmd.c struct tpm_digest digest = { .alg_id = bank->alg_id }; bank 826 drivers/char/tpm/tpm2-cmd.c if (bank->alg_id != tpm2_hash_map[i].tpm_id) bank 829 drivers/char/tpm/tpm2-cmd.c bank->digest_size = hash_digest_size[crypto_algo]; bank 830 drivers/char/tpm/tpm2-cmd.c bank->crypto_id = crypto_algo; bank 834 drivers/char/tpm/tpm2-cmd.c bank->crypto_id = HASH_ALGO__LAST; bank 836 drivers/char/tpm/tpm2-cmd.c return tpm2_pcr_read(chip, 0, &digest, &bank->digest_size); bank 58 drivers/clk/qcom/clk-rcg.c static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) bank 60 drivers/clk/qcom/clk-rcg.c bank &= BIT(rcg->mux_sel_bit); bank 61 drivers/clk/qcom/clk-rcg.c return !!bank; bank 69 drivers/clk/qcom/clk-rcg.c int bank; bank 76 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); bank 77 drivers/clk/qcom/clk-rcg.c s = &rcg->s[bank]; bank 79 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); bank 201 drivers/clk/qcom/clk-rcg.c int bank, new_bank, ret, index; bank 216 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); bank 217 drivers/clk/qcom/clk-rcg.c new_bank = enabled ? !bank : bank; bank 295 drivers/clk/qcom/clk-rcg.c int bank; bank 301 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); bank 303 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); bank 306 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md); bank 307 drivers/clk/qcom/clk-rcg.c f.m = md_to_m(&rcg->mn[bank], md); bank 308 drivers/clk/qcom/clk-rcg.c f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m); bank 312 drivers/clk/qcom/clk-rcg.c f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1; bank 314 drivers/clk/qcom/clk-rcg.c f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index); bank 371 drivers/clk/qcom/clk-rcg.c int bank; bank 377 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); bank 379 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); bank 383 drivers/clk/qcom/clk-rcg.c mn = &rcg->mn[bank]; bank 384 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md); bank 394 drivers/clk/qcom/clk-rcg.c pre_div = ns_to_pre_div(&rcg->p[bank], ns); bank 449 drivers/clk/qcom/clk-rcg.c int bank; bank 453 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); bank 454 drivers/clk/qcom/clk-rcg.c s = &rcg->s[bank]; bank 28 drivers/clk/rockchip/softrst.c int bank = id / softrst->num_per_reg; bank 33 drivers/clk/rockchip/softrst.c softrst->reg_base + (bank * 4)); bank 40 drivers/clk/rockchip/softrst.c reg = readl(softrst->reg_base + (bank * 4)); bank 41 drivers/clk/rockchip/softrst.c writel(reg | BIT(offset), softrst->reg_base + (bank * 4)); bank 55 drivers/clk/rockchip/softrst.c int bank = id / softrst->num_per_reg; bank 59 drivers/clk/rockchip/softrst.c writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); bank 66 drivers/clk/rockchip/softrst.c reg = readl(softrst->reg_base + (bank * 4)); bank 67 drivers/clk/rockchip/softrst.c writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4)); bank 137 drivers/clk/tegra/clk-periph.c const struct tegra_clk_periph_regs *bank; bank 153 drivers/clk/tegra/clk-periph.c bank = get_reg_bank(periph->gate.clk_num); bank 154 drivers/clk/tegra/clk-periph.c if (!bank) bank 163 drivers/clk/tegra/clk-periph.c periph->gate.regs = bank; bank 214 drivers/clk/tegra/clk-sdmmc-mux.c const struct tegra_clk_periph_regs *bank; bank 223 drivers/clk/tegra/clk-sdmmc-mux.c bank = get_reg_bank(clk_num); bank 224 drivers/clk/tegra/clk-sdmmc-mux.c if (!bank) bank 236 drivers/clk/tegra/clk-sdmmc-mux.c sdmmc_mux->gate.regs = bank; bank 880 drivers/clk/tegra/clk-tegra-periph.c const struct tegra_clk_periph_regs *bank; bank 889 drivers/clk/tegra/clk-tegra-periph.c bank = get_reg_bank(data->periph.gate.clk_num); bank 890 drivers/clk/tegra/clk-tegra-periph.c if (!bank) bank 893 drivers/clk/tegra/clk-tegra-periph.c data->periph.gate.regs = bank; bank 102 drivers/cpufreq/s3c24xx-cpufreq-debugfs.c int bank; bank 124 drivers/cpufreq/s3c24xx-cpufreq-debugfs.c for (bank = 0; bank < MAX_BANKS; bank++) { bank 125 drivers/cpufreq/s3c24xx-cpufreq-debugfs.c iob = &iot->bank[bank]; bank 127 drivers/cpufreq/s3c24xx-cpufreq-debugfs.c seq_printf(seq, "bank %d: ", bank); bank 111 drivers/crypto/qat/qat_common/adf_hw_arbiter.c WRITE_CSR_ARB_RINGSRVARBEN(ring->bank->csr_addr, bank 112 drivers/crypto/qat/qat_common/adf_hw_arbiter.c ring->bank->bank_number, bank 113 drivers/crypto/qat/qat_common/adf_hw_arbiter.c ring->bank->ring_mask & 0xFF); bank 96 drivers/crypto/qat/qat_common/adf_isr.c struct adf_etr_bank_data *bank = bank_ptr; bank 98 drivers/crypto/qat/qat_common/adf_isr.c WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, 0); bank 99 drivers/crypto/qat/qat_common/adf_isr.c tasklet_hi_schedule(&bank->resp_handler); bank 175 drivers/crypto/qat/qat_common/adf_isr.c struct adf_etr_bank_data *bank = &etr_data->banks[i]; bank 182 drivers/crypto/qat/qat_common/adf_isr.c adf_msix_isr_bundle, 0, name, bank); bank 80 drivers/crypto/qat/qat_common/adf_transport.c static int adf_reserve_ring(struct adf_etr_bank_data *bank, uint32_t ring) bank 82 drivers/crypto/qat/qat_common/adf_transport.c spin_lock(&bank->lock); bank 83 drivers/crypto/qat/qat_common/adf_transport.c if (bank->ring_mask & (1 << ring)) { bank 84 drivers/crypto/qat/qat_common/adf_transport.c spin_unlock(&bank->lock); bank 87 drivers/crypto/qat/qat_common/adf_transport.c bank->ring_mask |= (1 << ring); bank 88 drivers/crypto/qat/qat_common/adf_transport.c spin_unlock(&bank->lock); bank 92 drivers/crypto/qat/qat_common/adf_transport.c static void adf_unreserve_ring(struct adf_etr_bank_data *bank, uint32_t ring) bank 94 drivers/crypto/qat/qat_common/adf_transport.c spin_lock(&bank->lock); bank 95 drivers/crypto/qat/qat_common/adf_transport.c bank->ring_mask &= ~(1 << ring); bank 96 drivers/crypto/qat/qat_common/adf_transport.c spin_unlock(&bank->lock); bank 99 drivers/crypto/qat/qat_common/adf_transport.c static void adf_enable_ring_irq(struct adf_etr_bank_data *bank, uint32_t ring) bank 101 drivers/crypto/qat/qat_common/adf_transport.c spin_lock_bh(&bank->lock); bank 102 drivers/crypto/qat/qat_common/adf_transport.c bank->irq_mask |= (1 << ring); bank 103 drivers/crypto/qat/qat_common/adf_transport.c spin_unlock_bh(&bank->lock); bank 104 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_INT_COL_EN(bank->csr_addr, bank->bank_number, bank->irq_mask); bank 105 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_INT_COL_CTL(bank->csr_addr, bank->bank_number, bank 106 drivers/crypto/qat/qat_common/adf_transport.c bank->irq_coalesc_timer); bank 109 drivers/crypto/qat/qat_common/adf_transport.c static void adf_disable_ring_irq(struct adf_etr_bank_data *bank, uint32_t ring) bank 111 drivers/crypto/qat/qat_common/adf_transport.c spin_lock_bh(&bank->lock); bank 112 drivers/crypto/qat/qat_common/adf_transport.c bank->irq_mask &= ~(1 << ring); bank 113 drivers/crypto/qat/qat_common/adf_transport.c spin_unlock_bh(&bank->lock); bank 114 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_INT_COL_EN(bank->csr_addr, bank->bank_number, bank->irq_mask); bank 131 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_TAIL(ring->bank->csr_addr, ring->bank->bank_number, bank 153 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_HEAD(ring->bank->csr_addr, bank 154 drivers/crypto/qat/qat_common/adf_transport.c ring->bank->bank_number, bank 163 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_CONFIG(ring->bank->csr_addr, ring->bank->bank_number, bank 174 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_CONFIG(ring->bank->csr_addr, ring->bank->bank_number, bank 180 drivers/crypto/qat/qat_common/adf_transport.c struct adf_etr_bank_data *bank = ring->bank; bank 181 drivers/crypto/qat/qat_common/adf_transport.c struct adf_accel_dev *accel_dev = bank->accel_dev; bank 210 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_BASE(ring->bank->csr_addr, ring->bank->bank_number, bank 224 drivers/crypto/qat/qat_common/adf_transport.c dma_free_coherent(&GET_DEV(ring->bank->accel_dev), bank 237 drivers/crypto/qat/qat_common/adf_transport.c struct adf_etr_bank_data *bank; bank 271 drivers/crypto/qat/qat_common/adf_transport.c bank = &transport_data->banks[bank_num]; bank 272 drivers/crypto/qat/qat_common/adf_transport.c if (adf_reserve_ring(bank, ring_num)) { bank 277 drivers/crypto/qat/qat_common/adf_transport.c ring = &bank->rings[ring_num]; bank 279 drivers/crypto/qat/qat_common/adf_transport.c ring->bank = bank; bank 302 drivers/crypto/qat/qat_common/adf_transport.c adf_enable_ring_irq(bank, ring->ring_number); bank 307 drivers/crypto/qat/qat_common/adf_transport.c adf_unreserve_ring(bank, ring_num); bank 314 drivers/crypto/qat/qat_common/adf_transport.c struct adf_etr_bank_data *bank = ring->bank; bank 317 drivers/crypto/qat/qat_common/adf_transport.c adf_disable_ring_irq(bank, ring->ring_number); bank 320 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_CONFIG(bank->csr_addr, bank->bank_number, bank 322 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_BASE(bank->csr_addr, bank->bank_number, bank 325 drivers/crypto/qat/qat_common/adf_transport.c adf_unreserve_ring(bank, ring->ring_number); bank 331 drivers/crypto/qat/qat_common/adf_transport.c static void adf_ring_response_handler(struct adf_etr_bank_data *bank) bank 335 drivers/crypto/qat/qat_common/adf_transport.c empty_rings = READ_CSR_E_STAT(bank->csr_addr, bank->bank_number); bank 336 drivers/crypto/qat/qat_common/adf_transport.c empty_rings = ~empty_rings & bank->irq_mask; bank 340 drivers/crypto/qat/qat_common/adf_transport.c adf_handle_response(&bank->rings[i]); bank 346 drivers/crypto/qat/qat_common/adf_transport.c struct adf_etr_bank_data *bank = (void *)bank_addr; bank 349 drivers/crypto/qat/qat_common/adf_transport.c adf_ring_response_handler(bank); bank 350 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, bank 351 drivers/crypto/qat/qat_common/adf_transport.c bank->irq_mask); bank 371 drivers/crypto/qat/qat_common/adf_transport.c static void adf_get_coalesc_timer(struct adf_etr_bank_data *bank, bank 375 drivers/crypto/qat/qat_common/adf_transport.c if (adf_get_cfg_int(bank->accel_dev, section, bank 377 drivers/crypto/qat/qat_common/adf_transport.c bank_num_in_accel, &bank->irq_coalesc_timer)) bank 378 drivers/crypto/qat/qat_common/adf_transport.c bank->irq_coalesc_timer = ADF_COALESCING_DEF_TIME; bank 380 drivers/crypto/qat/qat_common/adf_transport.c if (ADF_COALESCING_MAX_TIME < bank->irq_coalesc_timer || bank 381 drivers/crypto/qat/qat_common/adf_transport.c ADF_COALESCING_MIN_TIME > bank->irq_coalesc_timer) bank 382 drivers/crypto/qat/qat_common/adf_transport.c bank->irq_coalesc_timer = ADF_COALESCING_DEF_TIME; bank 386 drivers/crypto/qat/qat_common/adf_transport.c struct adf_etr_bank_data *bank, bank 394 drivers/crypto/qat/qat_common/adf_transport.c memset(bank, 0, sizeof(*bank)); bank 395 drivers/crypto/qat/qat_common/adf_transport.c bank->bank_number = bank_num; bank 396 drivers/crypto/qat/qat_common/adf_transport.c bank->csr_addr = csr_addr; bank 397 drivers/crypto/qat/qat_common/adf_transport.c bank->accel_dev = accel_dev; bank 398 drivers/crypto/qat/qat_common/adf_transport.c spin_lock_init(&bank->lock); bank 406 drivers/crypto/qat/qat_common/adf_transport.c adf_get_coalesc_timer(bank, "Accelerator0", bank_num); bank 408 drivers/crypto/qat/qat_common/adf_transport.c bank->irq_coalesc_timer = ADF_COALESCING_MIN_TIME; bank 413 drivers/crypto/qat/qat_common/adf_transport.c ring = &bank->rings[i]; bank 427 drivers/crypto/qat/qat_common/adf_transport.c tx_ring = &bank->rings[i - hw_data->tx_rx_gap]; bank 431 drivers/crypto/qat/qat_common/adf_transport.c if (adf_bank_debugfs_add(bank)) { bank 442 drivers/crypto/qat/qat_common/adf_transport.c ring = &bank->rings[i]; bank 509 drivers/crypto/qat/qat_common/adf_transport.c static void cleanup_bank(struct adf_etr_bank_data *bank) bank 514 drivers/crypto/qat/qat_common/adf_transport.c struct adf_accel_dev *accel_dev = bank->accel_dev; bank 516 drivers/crypto/qat/qat_common/adf_transport.c struct adf_etr_ring_data *ring = &bank->rings[i]; bank 518 drivers/crypto/qat/qat_common/adf_transport.c if (bank->ring_mask & (1 << i)) bank 524 drivers/crypto/qat/qat_common/adf_transport.c adf_bank_debugfs_rm(bank); bank 525 drivers/crypto/qat/qat_common/adf_transport.c memset(bank, 0, sizeof(*bank)); bank 121 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ bank 122 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 124 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ bank 125 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 127 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define READ_CSR_E_STAT(csr_base_addr, bank) \ bank 128 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 130 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ bank 131 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 133 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ bank 138 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 140 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 143 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ bank 144 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 146 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ bank 147 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 149 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ bank 150 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ bank 152 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ bank 154 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 156 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 159 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ bank 160 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 162 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ bank 163 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 166 drivers/crypto/qat/qat_common/adf_transport_access_macros.h #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ bank 167 drivers/crypto/qat/qat_common/adf_transport_access_macros.h ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ bank 88 drivers/crypto/qat/qat_common/adf_transport_debug.c struct adf_etr_bank_data *bank = ring->bank; bank 89 drivers/crypto/qat/qat_common/adf_transport_debug.c void __iomem *csr = ring->bank->csr_addr; bank 94 drivers/crypto/qat/qat_common/adf_transport_debug.c head = READ_CSR_RING_HEAD(csr, bank->bank_number, bank 96 drivers/crypto/qat/qat_common/adf_transport_debug.c tail = READ_CSR_RING_TAIL(csr, bank->bank_number, bank 98 drivers/crypto/qat/qat_common/adf_transport_debug.c empty = READ_CSR_E_STAT(csr, bank->bank_number); bank 104 drivers/crypto/qat/qat_common/adf_transport_debug.c ring->ring_number, ring->bank->bank_number); bank 164 drivers/crypto/qat/qat_common/adf_transport_debug.c ring->bank->bank_debug_dir, bank 201 drivers/crypto/qat/qat_common/adf_transport_debug.c struct adf_etr_bank_data *bank = sfile->private; bank 205 drivers/crypto/qat/qat_common/adf_transport_debug.c bank->bank_number); bank 208 drivers/crypto/qat/qat_common/adf_transport_debug.c struct adf_etr_ring_data *ring = &bank->rings[ring_id]; bank 209 drivers/crypto/qat/qat_common/adf_transport_debug.c void __iomem *csr = bank->csr_addr; bank 212 drivers/crypto/qat/qat_common/adf_transport_debug.c if (!(bank->ring_mask & 1 << ring_id)) bank 215 drivers/crypto/qat/qat_common/adf_transport_debug.c head = READ_CSR_RING_HEAD(csr, bank->bank_number, bank 217 drivers/crypto/qat/qat_common/adf_transport_debug.c tail = READ_CSR_RING_TAIL(csr, bank->bank_number, bank 219 drivers/crypto/qat/qat_common/adf_transport_debug.c empty = READ_CSR_E_STAT(csr, bank->bank_number); bank 261 drivers/crypto/qat/qat_common/adf_transport_debug.c int adf_bank_debugfs_add(struct adf_etr_bank_data *bank) bank 263 drivers/crypto/qat/qat_common/adf_transport_debug.c struct adf_accel_dev *accel_dev = bank->accel_dev; bank 267 drivers/crypto/qat/qat_common/adf_transport_debug.c snprintf(name, sizeof(name), "bank_%02d", bank->bank_number); bank 268 drivers/crypto/qat/qat_common/adf_transport_debug.c bank->bank_debug_dir = debugfs_create_dir(name, parent); bank 269 drivers/crypto/qat/qat_common/adf_transport_debug.c bank->bank_debug_cfg = debugfs_create_file("config", S_IRUSR, bank 270 drivers/crypto/qat/qat_common/adf_transport_debug.c bank->bank_debug_dir, bank, bank 275 drivers/crypto/qat/qat_common/adf_transport_debug.c void adf_bank_debugfs_rm(struct adf_etr_bank_data *bank) bank 277 drivers/crypto/qat/qat_common/adf_transport_debug.c debugfs_remove(bank->bank_debug_cfg); bank 278 drivers/crypto/qat/qat_common/adf_transport_debug.c debugfs_remove(bank->bank_debug_dir); bank 64 drivers/crypto/qat/qat_common/adf_transport_internal.h struct adf_etr_bank_data *bank; bank 97 drivers/crypto/qat/qat_common/adf_transport_internal.h int adf_bank_debugfs_add(struct adf_etr_bank_data *bank); bank 98 drivers/crypto/qat/qat_common/adf_transport_internal.h void adf_bank_debugfs_rm(struct adf_etr_bank_data *bank); bank 102 drivers/crypto/qat/qat_common/adf_transport_internal.h static inline int adf_bank_debugfs_add(struct adf_etr_bank_data *bank) bank 107 drivers/crypto/qat/qat_common/adf_transport_internal.h #define adf_bank_debugfs_rm(bank) do {} while (0) bank 224 drivers/crypto/qat/qat_common/adf_vf_isr.c struct adf_etr_bank_data *bank = &etr_data->banks[0]; bank 227 drivers/crypto/qat/qat_common/adf_vf_isr.c WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, bank 229 drivers/crypto/qat/qat_common/adf_vf_isr.c tasklet_hi_schedule(&bank->resp_handler); bank 245 drivers/crypto/qat/qat_common/qat_crypto.c unsigned long bank; bank 274 drivers/crypto/qat/qat_common/qat_crypto.c if (kstrtoul(val, 10, &bank)) bank 295 drivers/crypto/qat/qat_common/qat_crypto.c if (adf_create_ring(accel_dev, SEC, bank, num_msg_sym, bank 301 drivers/crypto/qat/qat_common/qat_crypto.c if (adf_create_ring(accel_dev, SEC, bank, num_msg_asym, bank 307 drivers/crypto/qat/qat_common/qat_crypto.c if (adf_create_ring(accel_dev, SEC, bank, num_msg_sym, bank 313 drivers/crypto/qat/qat_common/qat_crypto.c if (adf_create_ring(accel_dev, SEC, bank, num_msg_asym, bank 72 drivers/dma/ipu/ipu_irq.c struct ipu_irq_bank *bank; bank 96 drivers/dma/ipu/ipu_irq.c struct ipu_irq_bank *bank; bank 102 drivers/dma/ipu/ipu_irq.c bank = map->bank; bank 103 drivers/dma/ipu/ipu_irq.c if (!bank) { bank 109 drivers/dma/ipu/ipu_irq.c reg = ipu_read_reg(bank->ipu, bank->control); bank 111 drivers/dma/ipu/ipu_irq.c ipu_write_reg(bank->ipu, reg, bank->control); bank 119 drivers/dma/ipu/ipu_irq.c struct ipu_irq_bank *bank; bank 125 drivers/dma/ipu/ipu_irq.c bank = map->bank; bank 126 drivers/dma/ipu/ipu_irq.c if (!bank) { bank 132 drivers/dma/ipu/ipu_irq.c reg = ipu_read_reg(bank->ipu, bank->control); bank 134 drivers/dma/ipu/ipu_irq.c ipu_write_reg(bank->ipu, reg, bank->control); bank 142 drivers/dma/ipu/ipu_irq.c struct ipu_irq_bank *bank; bank 147 drivers/dma/ipu/ipu_irq.c bank = map->bank; bank 148 drivers/dma/ipu/ipu_irq.c if (!bank) { bank 154 drivers/dma/ipu/ipu_irq.c ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status); bank 167 drivers/dma/ipu/ipu_irq.c struct ipu_irq_bank *bank; bank 172 drivers/dma/ipu/ipu_irq.c bank = map->bank; bank 173 drivers/dma/ipu/ipu_irq.c ret = bank && ipu_read_reg(bank->ipu, bank->status) & bank 214 drivers/dma/ipu/ipu_irq.c irq_map[i].bank = irq_bank + source / 32; bank 253 drivers/dma/ipu/ipu_irq.c irq_map[i].bank = NULL; bank 273 drivers/dma/ipu/ipu_irq.c struct ipu_irq_bank *bank = irq_bank + i; bank 276 drivers/dma/ipu/ipu_irq.c status = ipu_read_reg(ipu, bank->status); bank 282 drivers/dma/ipu/ipu_irq.c status &= ipu_read_reg(ipu, bank->control); bank 1466 drivers/dma/ti/edma.c u32 bank; bank 1480 drivers/dma/ti/edma.c bank = 1; bank 1483 drivers/dma/ti/edma.c bank = 0; bank 1494 drivers/dma/ti/edma.c channel = (bank << 5) | slot; bank 1496 drivers/dma/ti/edma.c edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); bank 83 drivers/edac/armada_xp_edac.c uint8_t cs, uint8_t bank, uint16_t row, bank 91 drivers/edac/armada_xp_edac.c ((bank & 0x7) << 16) | bank 96 drivers/edac/armada_xp_edac.c ((bank & 0x7) << 13) | bank 103 drivers/edac/armada_xp_edac.c ((bank & 0x7) << 16) | bank 108 drivers/edac/armada_xp_edac.c ((bank & 0x7) << 12) | bank 115 drivers/edac/armada_xp_edac.c ((bank & 0x7) << 16) | bank 120 drivers/edac/armada_xp_edac.c ((bank & 0x7) << 11) | bank 438 drivers/edac/cpc925_edac.c u32 bcnt, rank, col, bank, row; bank 446 drivers/edac/cpc925_edac.c bank = (mear & MEAR_BANK_MASK) >> MEAR_BANK_SHIFT; bank 471 drivers/edac/cpc925_edac.c pa |= bank << 19; bank 343 drivers/edac/ghes_edac.c p += sprintf(p, "bank:%d ", mem_err->bank); bank 351 drivers/edac/ghes_edac.c const char *bank = NULL, *device = NULL; bank 354 drivers/edac/ghes_edac.c dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device); bank 355 drivers/edac/ghes_edac.c if (bank != NULL && device != NULL) bank 356 drivers/edac/ghes_edac.c p += sprintf(p, "DIMM location:%s %s ", bank, device); bank 468 drivers/edac/i5000_edac.c int bank; bank 481 drivers/edac/i5000_edac.c bank = NREC_BANK(info->nrecmema); bank 488 drivers/edac/i5000_edac.c rank, channel, bank, bank 525 drivers/edac/i5000_edac.c bank, ras, cas, allErrors, specific); bank 553 drivers/edac/i5000_edac.c int bank; bank 576 drivers/edac/i5000_edac.c bank = NREC_BANK(info->nrecmema); bank 583 drivers/edac/i5000_edac.c rank, channel, channel + 1, branch >> 1, bank, bank 624 drivers/edac/i5000_edac.c rank, bank, ras, cas, ue_errors, specific); bank 648 drivers/edac/i5000_edac.c bank = REC_BANK(info->recmema); bank 655 drivers/edac/i5000_edac.c rank, channel, branch >> 1, bank, bank 676 drivers/edac/i5000_edac.c "CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank, bank 439 drivers/edac/i5100_edac.c unsigned bank, bank 451 drivers/edac/i5100_edac.c bank, cas, ras); bank 461 drivers/edac/i5100_edac.c unsigned bank, bank 473 drivers/edac/i5100_edac.c bank, cas, ras); bank 491 drivers/edac/i5100_edac.c unsigned bank; bank 510 drivers/edac/i5100_edac.c bank = i5100_recmema_bank(dw2); bank 524 drivers/edac/i5100_edac.c i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); bank 532 drivers/edac/i5100_edac.c bank = i5100_nrecmema_bank(dw2); bank 546 drivers/edac/i5100_edac.c i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); bank 518 drivers/edac/i5400_edac.c int bank; bank 544 drivers/edac/i5400_edac.c bank = nrec_bank(info); bank 552 drivers/edac/i5400_edac.c rank, channel, channel + 1, branch >> 1, bank, bank 561 drivers/edac/i5400_edac.c bank, buf_id, ras, cas, allErrors, error_name[errnum]); bank 583 drivers/edac/i5400_edac.c int bank; bank 615 drivers/edac/i5400_edac.c bank = rec_bank(info); bank 625 drivers/edac/i5400_edac.c rank, channel, branch >> 1, bank, bank 632 drivers/edac/i5400_edac.c branch >> 1, bank, rdwr_str(rdwr), ras, cas, bank 411 drivers/edac/i7300_edac.c unsigned branch, channel, bank, rank, cas, ras; bank 432 drivers/edac/i7300_edac.c bank = NRECMEMA_BANK(val16); bank 447 drivers/edac/i7300_edac.c bank, ras, cas, errors, specific); bank 471 drivers/edac/i7300_edac.c bank = RECMEMA_BANK(val16); bank 494 drivers/edac/i7300_edac.c bank, ras, cas, errors, specific); bank 218 drivers/edac/i7core_edac.c int channel, dimm, rank, bank, page, col; bank 416 drivers/edac/i7core_edac.c static inline int numbank(u32 bank) bank 420 drivers/edac/i7core_edac.c return banks[bank & 0x3]; bank 855 drivers/edac/i7core_edac.c DECLARE_ADDR_MATCH(bank, 32); bank 862 drivers/edac/i7core_edac.c ATTR_ADDR_MATCH(bank); bank 957 drivers/edac/i7core_edac.c if (pvt->inject.bank < 0) bank 960 drivers/edac/i7core_edac.c mask |= (pvt->inject.bank & 0x15LL) << 30; bank 1832 drivers/edac/i7core_edac.c if (mce->bank != 8) bank 2213 drivers/edac/i7core_edac.c pvt->inject.bank = -1; bank 953 drivers/edac/mce_amd.c if (m->bank >= ARRAY_SIZE(smca_banks)) bank 956 drivers/edac/mce_amd.c hwid = smca_banks[m->bank].hwid; bank 963 drivers/edac/mce_amd.c pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank); bank 1013 drivers/edac/mce_amd.c if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5 && !report_gart_errors) bank 1050 drivers/edac/mce_amd.c m->bank, bank 1060 drivers/edac/mce_amd.c u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); bank 1078 drivers/edac/mce_amd.c if (fam != 0x15 || m->bank != 4) bank 1108 drivers/edac/mce_amd.c switch (m->bank) { bank 33 drivers/edac/octeon_edac-lmc.c unsigned long bank; bank 95 drivers/edac/octeon_edac-lmc.c fadr.cn61xx.fbank = pvt->bank; bank 158 drivers/edac/octeon_edac-lmc.c TEMPLATE_SHOW(bank); bank 159 drivers/edac/octeon_edac-lmc.c TEMPLATE_STORE(bank); bank 205 drivers/edac/octeon_edac-lmc.c static DEVICE_ATTR(bank, S_IRUGO | S_IWUSR, bank 55 drivers/edac/pnd2_edac.c int bank; bank 933 drivers/edac/pnd2_edac.c int column = 0, bank = 0, row = 0, rank = 0; bank 962 drivers/edac/pnd2_edac.c bank |= (bit << idx); bank 964 drivers/edac/pnd2_edac.c bank ^= bank_hash(pmiaddr, idx, d->addrdec); bank 985 drivers/edac/pnd2_edac.c daddr->bank = bank; bank 1010 drivers/edac/pnd2_edac.c daddr->bank = dnv_get_bit(pmiaddr, dmap[pmiidx].ba0 + 6, 0); bank 1011 drivers/edac/pnd2_edac.c daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].ba1 + 6, 1); bank 1012 drivers/edac/pnd2_edac.c daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].bg0 + 6, 2); bank 1014 drivers/edac/pnd2_edac.c daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].bg1 + 6, 3); bank 1017 drivers/edac/pnd2_edac.c daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row6 + 6, 0); bank 1018 drivers/edac/pnd2_edac.c daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row7 + 6, 1); bank 1021 drivers/edac/pnd2_edac.c daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca3 + 6, 2); bank 1024 drivers/edac/pnd2_edac.c daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca4 + 6, 2); bank 1025 drivers/edac/pnd2_edac.c daddr->bank ^= dnv_get_bit(pmiaddr, dmap2[pmiidx].row2 + 6, 3); bank 1027 drivers/edac/pnd2_edac.c daddr->bank ^= dnv_get_bit(pmiaddr, dmap2[pmiidx].row2 + 6, 0); bank 1028 drivers/edac/pnd2_edac.c daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row6 + 6, 1); bank 1030 drivers/edac/pnd2_edac.c daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca3 + 6, 2); bank 1032 drivers/edac/pnd2_edac.c daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca4 + 6, 2); bank 1138 drivers/edac/pnd2_edac.c addr, pmiaddr, daddr->chan, daddr->dimm, daddr->rank, daddr->bank, daddr->row, daddr->col); bank 1208 drivers/edac/pnd2_edac.c errcode, daddr->chan, daddr->dimm, daddr->rank, daddr->row, daddr->bank, daddr->col); bank 1422 drivers/edac/pnd2_edac.c mce->extcpu, type, mce->mcgstatus, mce->bank, mce->status); bank 1466 drivers/edac/pnd2_edac.c m.addr, daddr.chan, daddr.dimm, daddr.rank, daddr.bank, daddr.row, daddr.col); bank 281 drivers/edac/ppc4xx_edac.c unsigned int bank) bank 283 drivers/edac/ppc4xx_edac.c switch (bank) { bank 208 drivers/edac/qcom_edac.c dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) bank 216 drivers/edac/qcom_edac.c ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, bank 226 drivers/edac/qcom_edac.c drv->offsets[bank] + reg_data.count_status_reg, bank 237 drivers/edac/qcom_edac.c drv->offsets[bank] + reg_data.ways_status_reg, bank 253 drivers/edac/qcom_edac.c dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) bank 258 drivers/edac/qcom_edac.c ret = dump_syn_reg_values(drv, bank, err_type); bank 264 drivers/edac/qcom_edac.c edac_device_handle_ce(edev_ctl, 0, bank, bank 268 drivers/edac/qcom_edac.c edac_device_handle_ue(edev_ctl, 0, bank, bank 272 drivers/edac/qcom_edac.c edac_device_handle_ce(edev_ctl, 0, bank, bank 276 drivers/edac/qcom_edac.c edac_device_handle_ue(edev_ctl, 0, bank, bank 327 drivers/edac/sb_edac.c u8 (*get_ha)(u8 bank); bank 1010 drivers/edac/sb_edac.c static u8 sbridge_get_ha(u8 bank) bank 1020 drivers/edac/sb_edac.c static u8 ibridge_get_ha(u8 bank) bank 1022 drivers/edac/sb_edac.c switch (bank) { bank 1024 drivers/edac/sb_edac.c return bank - 7; bank 1026 drivers/edac/sb_edac.c return (bank - 9) / 4; bank 1033 drivers/edac/sb_edac.c static u8 knl_get_ha(u8 bank) bank 2262 drivers/edac/sb_edac.c *ha = pvt->info.get_ha(m->bank); bank 2264 drivers/edac/sb_edac.c sprintf(msg, "Impossible bank %d", m->bank); bank 3034 drivers/edac/sb_edac.c m->bank); bank 3044 drivers/edac/sb_edac.c channel = knl_channel_remap(m->bank == 16, channel); bank 3176 drivers/edac/sb_edac.c mce->mcgstatus, mce->bank, mce->status); bank 607 drivers/edac/skx_common.c mce->mcgstatus, mce->bank, mce->status); bank 282 drivers/edac/synopsys_edac.c u32 bank; bank 381 drivers/edac/synopsys_edac.c p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; bank 395 drivers/edac/synopsys_edac.c p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; bank 435 drivers/edac/synopsys_edac.c p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> bank 453 drivers/edac/synopsys_edac.c p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> bank 483 drivers/edac/synopsys_edac.c "CE", pinf->row, pinf->bank, pinf->col, bank 488 drivers/edac/synopsys_edac.c "CE", pinf->row, pinf->bank, pinf->col, bank 503 drivers/edac/synopsys_edac.c "UE", pinf->row, pinf->bank, pinf->col); bank 507 drivers/edac/synopsys_edac.c "UE", pinf->row, pinf->bank, pinf->col, bank 921 drivers/edac/synopsys_edac.c int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval; bank 945 drivers/edac/synopsys_edac.c bank |= (((hif_addr >> priv->bank_shift[index]) & bank 967 drivers/edac/synopsys_edac.c regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK; bank 494 drivers/edac/thunderx_edac.c int bank, xbits; bank 502 drivers/edac/thunderx_edac.c bank = LMC_FADR_FBANK(faddr) << lmc->bank_lsb; bank 505 drivers/edac/thunderx_edac.c bank ^= get_bits(addr, 12 + lmc->xbits, lmc->bank_width); bank 507 drivers/edac/thunderx_edac.c addr |= bank << lmc->bank_lsb; bank 181 drivers/edac/xgene_edac.c u32 bank; bank 208 drivers/edac/xgene_edac.c bank = readl(ctx->mcu_csr + MCUEBLRR0 + bank 216 drivers/edac/xgene_edac.c rank, MCU_EBLRR_ERRBANK_RD(bank), bank 35 drivers/firmware/dmi_scan.c const char *bank; bank 402 drivers/firmware/dmi_scan.c dmi_memdev[nr].bank = dmi_string(dm, d[0x11]); bank 1101 drivers/firmware/dmi_scan.c void dmi_memdev_name(u16 handle, const char **bank, const char **device) bank 1110 drivers/firmware/dmi_scan.c *bank = dmi_memdev[n].bank; bank 234 drivers/firmware/efi/cper.c n += scnprintf(msg + n, len - n, "bank: %d ", mem->bank); bank 261 drivers/firmware/efi/cper.c const char *bank = NULL, *device = NULL; bank 268 drivers/firmware/efi/cper.c dmi_memdev_name(mem->mem_dev_handle, &bank, &device); bank 269 drivers/firmware/efi/cper.c if (bank && device) bank 270 drivers/firmware/efi/cper.c n = snprintf(msg, len, "DIMM location: %s %s ", bank, device); bank 287 drivers/firmware/efi/cper.c cmem->bank = mem->bank; bank 43 drivers/gpio/gpio-74x164.c u8 bank = chip->registers - 1 - offset / 8; bank 48 drivers/gpio/gpio-74x164.c ret = (chip->buffer[bank] >> pin) & 0x1; bank 58 drivers/gpio/gpio-74x164.c u8 bank = chip->registers - 1 - offset / 8; bank 63 drivers/gpio/gpio-74x164.c chip->buffer[bank] |= (1 << pin); bank 65 drivers/gpio/gpio-74x164.c chip->buffer[bank] &= ~(1 << pin); bank 76 drivers/gpio/gpio-74x164.c u8 bank, bankmask; bank 79 drivers/gpio/gpio-74x164.c for (i = 0, bank = chip->registers - 1; i < chip->registers; bank 80 drivers/gpio/gpio-74x164.c i++, bank--) { bank 87 drivers/gpio/gpio-74x164.c chip->buffer[bank] &= ~bankmask; bank 88 drivers/gpio/gpio-74x164.c chip->buffer[bank] |= bankmask & (bits[idx] >> shift); bank 68 drivers/gpio/gpio-adp5588.c unsigned bank = ADP5588_BANK(off); bank 74 drivers/gpio/gpio-adp5588.c if (dev->dir[bank] & bit) bank 75 drivers/gpio/gpio-adp5588.c val = dev->dat_out[bank]; bank 77 drivers/gpio/gpio-adp5588.c val = adp5588_gpio_read(dev->client, GPIO_DAT_STAT1 + bank); bank 87 drivers/gpio/gpio-adp5588.c unsigned bank, bit; bank 90 drivers/gpio/gpio-adp5588.c bank = ADP5588_BANK(off); bank 95 drivers/gpio/gpio-adp5588.c dev->dat_out[bank] |= bit; bank 97 drivers/gpio/gpio-adp5588.c dev->dat_out[bank] &= ~bit; bank 99 drivers/gpio/gpio-adp5588.c adp5588_gpio_write(dev->client, GPIO_DAT_OUT1 + bank, bank 100 drivers/gpio/gpio-adp5588.c dev->dat_out[bank]); bank 107 drivers/gpio/gpio-adp5588.c unsigned bank; bank 110 drivers/gpio/gpio-adp5588.c bank = ADP5588_BANK(off); bank 113 drivers/gpio/gpio-adp5588.c dev->dir[bank] &= ~ADP5588_BIT(off); bank 114 drivers/gpio/gpio-adp5588.c ret = adp5588_gpio_write(dev->client, GPIO_DIR1 + bank, dev->dir[bank]); bank 124 drivers/gpio/gpio-adp5588.c unsigned bank, bit; bank 127 drivers/gpio/gpio-adp5588.c bank = ADP5588_BANK(off); bank 131 drivers/gpio/gpio-adp5588.c dev->dir[bank] |= bit; bank 134 drivers/gpio/gpio-adp5588.c dev->dat_out[bank] |= bit; bank 136 drivers/gpio/gpio-adp5588.c dev->dat_out[bank] &= ~bit; bank 138 drivers/gpio/gpio-adp5588.c ret = adp5588_gpio_write(dev->client, GPIO_DAT_OUT1 + bank, bank 139 drivers/gpio/gpio-adp5588.c dev->dat_out[bank]); bank 140 drivers/gpio/gpio-adp5588.c ret |= adp5588_gpio_write(dev->client, GPIO_DIR1 + bank, bank 141 drivers/gpio/gpio-adp5588.c dev->dir[bank]); bank 212 drivers/gpio/gpio-adp5588.c unsigned bank, bit; bank 214 drivers/gpio/gpio-adp5588.c bank = ADP5588_BANK(gpio); bank 217 drivers/gpio/gpio-adp5588.c dev->int_lvl_low[bank] &= ~bit; bank 218 drivers/gpio/gpio-adp5588.c dev->int_lvl_high[bank] &= ~bit; bank 221 drivers/gpio/gpio-adp5588.c dev->int_lvl_high[bank] |= bit; bank 224 drivers/gpio/gpio-adp5588.c dev->int_lvl_low[bank] |= bit; bank 226 drivers/gpio/gpio-adp5588.c dev->int_input_en[bank] |= bit; bank 259 drivers/gpio/gpio-adp5588.c int bank = ADP5588_BANK(gpio); bank 262 drivers/gpio/gpio-adp5588.c if ((lvl && dev->int_lvl_high[bank] & bit) || bank 263 drivers/gpio/gpio-adp5588.c (!lvl && dev->int_lvl_low[bank] & bit)) bank 32 drivers/gpio/gpio-aspeed.c unsigned int bank; bank 209 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank, bank 214 drivers/gpio/gpio-aspeed.c return gpio->base + bank->val_regs + GPIO_VAL_VALUE; bank 216 drivers/gpio/gpio-aspeed.c return gpio->base + bank->rdata_reg; bank 218 drivers/gpio/gpio-aspeed.c return gpio->base + bank->val_regs + GPIO_VAL_DIR; bank 220 drivers/gpio/gpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; bank 222 drivers/gpio/gpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; bank 224 drivers/gpio/gpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; bank 226 drivers/gpio/gpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; bank 228 drivers/gpio/gpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; bank 230 drivers/gpio/gpio-aspeed.c return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; bank 232 drivers/gpio/gpio-aspeed.c return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; bank 234 drivers/gpio/gpio-aspeed.c return gpio->base + bank->tolerance_regs; bank 236 drivers/gpio/gpio-aspeed.c return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; bank 238 drivers/gpio/gpio-aspeed.c return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; bank 253 drivers/gpio/gpio-aspeed.c unsigned int bank = GPIO_BANK(offset); bank 255 drivers/gpio/gpio-aspeed.c WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); bank 256 drivers/gpio/gpio-aspeed.c return &aspeed_gpio_banks[bank]; bank 270 drivers/gpio/gpio-aspeed.c if (props->bank == GPIO_BANK(offset)) bank 281 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = to_bank(offset); bank 284 drivers/gpio/gpio-aspeed.c return bank->names[group][0] != '\0' && bank 306 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank, bank 309 drivers/gpio/gpio-aspeed.c void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0); bank 310 drivers/gpio/gpio-aspeed.c void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1); bank 340 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = to_bank(offset); bank 353 drivers/gpio/gpio-aspeed.c aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM); bank 356 drivers/gpio/gpio-aspeed.c gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); bank 364 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = to_bank(offset); bank 374 drivers/gpio/gpio-aspeed.c aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, bank 384 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = to_bank(offset); bank 386 drivers/gpio/gpio-aspeed.c return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); bank 393 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = to_bank(offset); bank 397 drivers/gpio/gpio-aspeed.c addr = bank_reg(gpio, bank, reg_val); bank 429 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = to_bank(offset); bank 430 drivers/gpio/gpio-aspeed.c void __iomem *addr = bank_reg(gpio, bank, reg_dir); bank 457 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = to_bank(offset); bank 458 drivers/gpio/gpio-aspeed.c void __iomem *addr = bank_reg(gpio, bank, reg_dir); bank 485 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = to_bank(offset); bank 497 drivers/gpio/gpio-aspeed.c val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); bank 507 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank **bank, bank 521 drivers/gpio/gpio-aspeed.c *bank = to_bank(*offset); bank 529 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank; bank 537 drivers/gpio/gpio-aspeed.c rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); bank 541 drivers/gpio/gpio-aspeed.c status_addr = bank_reg(gpio, bank, reg_irq_status); bank 555 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank; bank 563 drivers/gpio/gpio-aspeed.c rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); bank 567 drivers/gpio/gpio-aspeed.c addr = bank_reg(gpio, bank, reg_irq_enable); bank 600 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank; bank 608 drivers/gpio/gpio-aspeed.c rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); bank 636 drivers/gpio/gpio-aspeed.c addr = bank_reg(gpio, bank, reg_irq_type0); bank 641 drivers/gpio/gpio-aspeed.c addr = bank_reg(gpio, bank, reg_irq_type1); bank 646 drivers/gpio/gpio-aspeed.c addr = bank_reg(gpio, bank, reg_irq_type2); bank 673 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; bank 675 drivers/gpio/gpio-aspeed.c reg = ioread32(bank_reg(data, bank, reg_irq_status)); bank 700 drivers/gpio/gpio-aspeed.c unsigned int i = props->bank * 32 + offset; bank 827 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = to_bank(offset); bank 835 drivers/gpio/gpio-aspeed.c addr = bank_reg(gpio, bank, reg_debounce_sel1); bank 839 drivers/gpio/gpio-aspeed.c addr = bank_reg(gpio, bank, reg_debounce_sel2); bank 1011 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = to_bank(offset); bank 1033 drivers/gpio/gpio-aspeed.c aspeed_gpio_change_cmd_source(gpio, bank, bindex, bank 1037 drivers/gpio/gpio-aspeed.c *vreg_offset = bank->val_regs; bank 1039 drivers/gpio/gpio-aspeed.c *dreg_offset = bank->rdata_reg; bank 1057 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = to_bank(offset); bank 1078 drivers/gpio/gpio-aspeed.c aspeed_gpio_change_cmd_source(gpio, bank, bindex, bank 1197 drivers/gpio/gpio-aspeed.c const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; bank 1198 drivers/gpio/gpio-aspeed.c void __iomem *addr = bank_reg(gpio, bank, reg_rdata); bank 1200 drivers/gpio/gpio-aspeed.c aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM); bank 1201 drivers/gpio/gpio-aspeed.c aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM); bank 1202 drivers/gpio/gpio-aspeed.c aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM); bank 1203 drivers/gpio/gpio-aspeed.c aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM); bank 38 drivers/gpio/gpio-bcm-kona.c #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) bank 39 drivers/gpio/gpio-bcm-kona.c #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) bank 40 drivers/gpio/gpio-bcm-kona.c #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) bank 41 drivers/gpio/gpio-bcm-kona.c #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) bank 42 drivers/gpio/gpio-bcm-kona.c #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) bank 43 drivers/gpio/gpio-bcm-kona.c #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) bank 44 drivers/gpio/gpio-bcm-kona.c #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) bank 45 drivers/gpio/gpio-bcm-kona.c #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) bank 453 drivers/gpio/gpio-bcm-kona.c struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc); bank 463 drivers/gpio/gpio-bcm-kona.c reg_base = bank->kona_gpio->reg_base; bank 464 drivers/gpio/gpio-bcm-kona.c bank_id = bank->id; bank 471 drivers/gpio/gpio-bcm-kona.c irq_find_mapping(bank->kona_gpio->irq_domain, bank 571 drivers/gpio/gpio-bcm-kona.c struct bcm_kona_gpio_bank *bank; bank 627 drivers/gpio/gpio-bcm-kona.c bank = &kona_gpio->banks[i]; bank 628 drivers/gpio/gpio-bcm-kona.c bank->id = i; bank 629 drivers/gpio/gpio-bcm-kona.c bank->irq = platform_get_irq(pdev, i); bank 630 drivers/gpio/gpio-bcm-kona.c bank->kona_gpio = kona_gpio; bank 631 drivers/gpio/gpio-bcm-kona.c if (bank->irq < 0) { bank 648 drivers/gpio/gpio-bcm-kona.c bank = &kona_gpio->banks[i]; bank 649 drivers/gpio/gpio-bcm-kona.c irq_set_chained_handler_and_data(bank->irq, bank 651 drivers/gpio/gpio-bcm-kona.c bank); bank 36 drivers/gpio/gpio-brcmstb.c #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) bank 37 drivers/gpio/gpio-brcmstb.c #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) bank 38 drivers/gpio/gpio-brcmstb.c #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) bank 39 drivers/gpio/gpio-brcmstb.c #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) bank 40 drivers/gpio/gpio-brcmstb.c #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) bank 41 drivers/gpio/gpio-brcmstb.c #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) bank 42 drivers/gpio/gpio-brcmstb.c #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) bank 43 drivers/gpio/gpio-brcmstb.c #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) bank 44 drivers/gpio/gpio-brcmstb.c #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) bank 76 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); bank 77 drivers/gpio/gpio-brcmstb.c return bank->parent_priv; bank 81 drivers/gpio/gpio-brcmstb.c __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) bank 83 drivers/gpio/gpio-brcmstb.c void __iomem *reg_base = bank->parent_priv->reg_base; bank 85 drivers/gpio/gpio-brcmstb.c return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) & bank 86 drivers/gpio/gpio-brcmstb.c bank->gc.read_reg(reg_base + GIO_MASK(bank->id)); bank 90 drivers/gpio/gpio-brcmstb.c brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) bank 95 drivers/gpio/gpio-brcmstb.c spin_lock_irqsave(&bank->gc.bgpio_lock, flags); bank 96 drivers/gpio/gpio-brcmstb.c status = __brcmstb_gpio_get_active_irqs(bank); bank 97 drivers/gpio/gpio-brcmstb.c spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); bank 103 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank) bank 105 drivers/gpio/gpio-brcmstb.c return hwirq - (bank->gc.base - bank->parent_priv->gpio_base); bank 108 drivers/gpio/gpio-brcmstb.c static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, bank 111 drivers/gpio/gpio-brcmstb.c struct gpio_chip *gc = &bank->gc; bank 112 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_priv *priv = bank->parent_priv; bank 113 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); bank 118 drivers/gpio/gpio-brcmstb.c imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); bank 123 drivers/gpio/gpio-brcmstb.c gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); bank 143 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); bank 145 drivers/gpio/gpio-brcmstb.c brcmstb_gpio_set_imask(bank, d->hwirq, false); bank 151 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); bank 153 drivers/gpio/gpio-brcmstb.c brcmstb_gpio_set_imask(bank, d->hwirq, true); bank 159 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); bank 160 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_priv *priv = bank->parent_priv; bank 161 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); bank 163 drivers/gpio/gpio-brcmstb.c gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask); bank 169 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); bank 170 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_priv *priv = bank->parent_priv; bank 171 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); bank 207 drivers/gpio/gpio-brcmstb.c spin_lock_irqsave(&bank->gc.bgpio_lock, flags); bank 209 drivers/gpio/gpio-brcmstb.c iedge_config = bank->gc.read_reg(priv->reg_base + bank 210 drivers/gpio/gpio-brcmstb.c GIO_EC(bank->id)) & ~mask; bank 211 drivers/gpio/gpio-brcmstb.c iedge_insensitive = bank->gc.read_reg(priv->reg_base + bank 212 drivers/gpio/gpio-brcmstb.c GIO_EI(bank->id)) & ~mask; bank 213 drivers/gpio/gpio-brcmstb.c ilevel = bank->gc.read_reg(priv->reg_base + bank 214 drivers/gpio/gpio-brcmstb.c GIO_LEVEL(bank->id)) & ~mask; bank 216 drivers/gpio/gpio-brcmstb.c bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id), bank 218 drivers/gpio/gpio-brcmstb.c bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id), bank 220 drivers/gpio/gpio-brcmstb.c bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), bank 223 drivers/gpio/gpio-brcmstb.c spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); bank 245 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); bank 246 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_priv *priv = bank->parent_priv; bank 247 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); bank 254 drivers/gpio/gpio-brcmstb.c bank->wake_active |= mask; bank 256 drivers/gpio/gpio-brcmstb.c bank->wake_active &= ~mask; bank 272 drivers/gpio/gpio-brcmstb.c static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank) bank 274 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_priv *priv = bank->parent_priv; bank 276 drivers/gpio/gpio-brcmstb.c int hwbase = bank->gc.base - priv->gpio_base; bank 279 drivers/gpio/gpio-brcmstb.c while ((status = brcmstb_gpio_get_active_irqs(bank))) { bank 283 drivers/gpio/gpio-brcmstb.c if (offset >= bank->width) bank 286 drivers/gpio/gpio-brcmstb.c bank->id, offset); bank 298 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank; bank 304 drivers/gpio/gpio-brcmstb.c list_for_each_entry(bank, &priv->bank_list, node) bank 305 drivers/gpio/gpio-brcmstb.c brcmstb_gpio_irq_bank_handler(bank); bank 312 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank; bank 316 drivers/gpio/gpio-brcmstb.c list_for_each_entry_reverse(bank, &priv->bank_list, node) { bank 317 drivers/gpio/gpio-brcmstb.c i += bank->gc.ngpio; bank 319 drivers/gpio/gpio-brcmstb.c return bank; bank 336 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank = bank 341 drivers/gpio/gpio-brcmstb.c if (!bank) bank 345 drivers/gpio/gpio-brcmstb.c irq, (int)hwirq, bank->id); bank 346 drivers/gpio/gpio-brcmstb.c ret = irq_set_chip_data(irq, &bank->gc); bank 388 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank; bank 412 drivers/gpio/gpio-brcmstb.c list_for_each_entry(bank, &priv->bank_list, node) bank 413 drivers/gpio/gpio-brcmstb.c gpiochip_remove(&bank->gc); bank 422 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); bank 437 drivers/gpio/gpio-brcmstb.c if (unlikely(offset >= bank->width)) { bank 514 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank) bank 516 drivers/gpio/gpio-brcmstb.c struct gpio_chip *gc = &bank->gc; bank 520 drivers/gpio/gpio-brcmstb.c bank->saved_regs[i] = gc->read_reg(priv->reg_base + bank 521 drivers/gpio/gpio-brcmstb.c GIO_BANK_OFF(bank->id, i)); bank 527 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank; bank 535 drivers/gpio/gpio-brcmstb.c list_for_each_entry(bank, &priv->bank_list, node) { bank 536 drivers/gpio/gpio-brcmstb.c gc = &bank->gc; bank 539 drivers/gpio/gpio-brcmstb.c brcmstb_gpio_bank_save(priv, bank); bank 543 drivers/gpio/gpio-brcmstb.c imask = bank->wake_active; bank 546 drivers/gpio/gpio-brcmstb.c gc->write_reg(priv->reg_base + GIO_MASK(bank->id), bank 559 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank) bank 561 drivers/gpio/gpio-brcmstb.c struct gpio_chip *gc = &bank->gc; bank 565 drivers/gpio/gpio-brcmstb.c gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i), bank 566 drivers/gpio/gpio-brcmstb.c bank->saved_regs[i]); bank 578 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank; bank 581 drivers/gpio/gpio-brcmstb.c list_for_each_entry(bank, &priv->bank_list, node) { bank 582 drivers/gpio/gpio-brcmstb.c need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); bank 583 drivers/gpio/gpio-brcmstb.c brcmstb_gpio_bank_restore(priv, bank); bank 662 drivers/gpio/gpio-brcmstb.c struct brcmstb_gpio_bank *bank; bank 677 drivers/gpio/gpio-brcmstb.c bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); bank 678 drivers/gpio/gpio-brcmstb.c if (!bank) { bank 683 drivers/gpio/gpio-brcmstb.c bank->parent_priv = priv; bank 684 drivers/gpio/gpio-brcmstb.c bank->id = num_banks; bank 690 drivers/gpio/gpio-brcmstb.c bank->width = bank_width; bank 697 drivers/gpio/gpio-brcmstb.c gc = &bank->gc; bank 699 drivers/gpio/gpio-brcmstb.c reg_base + GIO_DATA(bank->id), bank 701 drivers/gpio/gpio-brcmstb.c reg_base + GIO_IODIR(bank->id), flags); bank 726 drivers/gpio/gpio-brcmstb.c need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); bank 727 drivers/gpio/gpio-brcmstb.c gc->write_reg(reg_base + GIO_MASK(bank->id), 0); bank 729 drivers/gpio/gpio-brcmstb.c err = gpiochip_add_data(gc, bank); bank 732 drivers/gpio/gpio-brcmstb.c bank->id); bank 737 drivers/gpio/gpio-brcmstb.c dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, bank 738 drivers/gpio/gpio-brcmstb.c gc->base, gc->ngpio, bank->width); bank 741 drivers/gpio/gpio-brcmstb.c list_add(&bank->node, &priv->bank_list); bank 93 drivers/gpio/gpio-davinci.c int bank = offset / 32; bank 96 drivers/gpio/gpio-davinci.c g = d->regs[bank]; bank 133 drivers/gpio/gpio-davinci.c int bank = offset / 32; bank 135 drivers/gpio/gpio-davinci.c g = d->regs[bank]; bank 148 drivers/gpio/gpio-davinci.c int bank = offset / 32; bank 150 drivers/gpio/gpio-davinci.c g = d->regs[bank]; bank 192 drivers/gpio/gpio-davinci.c int bank, i, ret = 0; bank 271 drivers/gpio/gpio-davinci.c for (bank = 0; bank < nbank; bank++) bank 272 drivers/gpio/gpio-davinci.c chips->regs[bank] = gpio_base + offset_array[bank]; bank 490 drivers/gpio/gpio-davinci.c unsigned gpio, bank; bank 591 drivers/gpio/gpio-davinci.c for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { bank 596 drivers/gpio/gpio-davinci.c g = chips->regs[bank / 2]; bank 615 drivers/gpio/gpio-davinci.c irqdata->bank_num = bank; bank 618 drivers/gpio/gpio-davinci.c irq_set_chained_handler_and_data(chips->irqs[bank], bank 621 drivers/gpio/gpio-davinci.c binten |= BIT(bank); bank 132 drivers/gpio/gpio-eic-sprd.c unsigned int bank) bank 134 drivers/gpio/gpio-eic-sprd.c if (bank >= SPRD_EIC_MAX_BANK) bank 137 drivers/gpio/gpio-eic-sprd.c return sprd_eic->base[bank]; bank 504 drivers/gpio/gpio-eic-sprd.c u32 bank, n, girq; bank 506 drivers/gpio/gpio-eic-sprd.c for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) { bank 507 drivers/gpio/gpio-eic-sprd.c void __iomem *base = sprd_eic_offset_base(sprd_eic, bank); bank 533 drivers/gpio/gpio-eic-sprd.c u32 offset = bank * SPRD_EIC_PER_BANK_NR + n; bank 332 drivers/gpio/gpio-ep93xx.c struct ep93xx_gpio_bank *bank) bank 334 drivers/gpio/gpio-ep93xx.c void __iomem *data = epg->base + bank->data; bank 335 drivers/gpio/gpio-ep93xx.c void __iomem *dir = epg->base + bank->dir; bank 344 drivers/gpio/gpio-ep93xx.c gc->label = bank->label; bank 345 drivers/gpio/gpio-ep93xx.c gc->base = bank->base; bank 348 drivers/gpio/gpio-ep93xx.c if (bank->has_irq || bank->has_hierarchical_irq) { bank 353 drivers/gpio/gpio-ep93xx.c if (bank->has_irq) { bank 366 drivers/gpio/gpio-ep93xx.c girq->first = bank->irq_base; bank 370 drivers/gpio/gpio-ep93xx.c if (bank->has_hierarchical_irq) { bank 419 drivers/gpio/gpio-ep93xx.c struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; bank 421 drivers/gpio/gpio-ep93xx.c if (ep93xx_gpio_add_bank(gc, pdev, epg, bank)) bank 423 drivers/gpio/gpio-ep93xx.c bank->label); bank 67 drivers/gpio/gpio-f7188x.c struct f7188x_gpio_bank *bank; bank 240 drivers/gpio/gpio-f7188x.c struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); bank 241 drivers/gpio/gpio-f7188x.c struct f7188x_sio *sio = bank->data->sio; bank 249 drivers/gpio/gpio-f7188x.c dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); bank 259 drivers/gpio/gpio-f7188x.c struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); bank 260 drivers/gpio/gpio-f7188x.c struct f7188x_sio *sio = bank->data->sio; bank 268 drivers/gpio/gpio-f7188x.c dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); bank 270 drivers/gpio/gpio-f7188x.c superio_outb(sio->addr, gpio_dir(bank->regbase), dir); bank 280 drivers/gpio/gpio-f7188x.c struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); bank 281 drivers/gpio/gpio-f7188x.c struct f7188x_sio *sio = bank->data->sio; bank 289 drivers/gpio/gpio-f7188x.c dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); bank 292 drivers/gpio/gpio-f7188x.c data = superio_inb(sio->addr, gpio_data_out(bank->regbase)); bank 294 drivers/gpio/gpio-f7188x.c data = superio_inb(sio->addr, gpio_data_in(bank->regbase)); bank 305 drivers/gpio/gpio-f7188x.c struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); bank 306 drivers/gpio/gpio-f7188x.c struct f7188x_sio *sio = bank->data->sio; bank 314 drivers/gpio/gpio-f7188x.c data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase)); bank 319 drivers/gpio/gpio-f7188x.c superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out); bank 321 drivers/gpio/gpio-f7188x.c dir = superio_inb(sio->addr, gpio_dir(bank->regbase)); bank 323 drivers/gpio/gpio-f7188x.c superio_outb(sio->addr, gpio_dir(bank->regbase), dir); bank 333 drivers/gpio/gpio-f7188x.c struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); bank 334 drivers/gpio/gpio-f7188x.c struct f7188x_sio *sio = bank->data->sio; bank 342 drivers/gpio/gpio-f7188x.c data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase)); bank 347 drivers/gpio/gpio-f7188x.c superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out); bank 357 drivers/gpio/gpio-f7188x.c struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); bank 358 drivers/gpio/gpio-f7188x.c struct f7188x_sio *sio = bank->data->sio; bank 370 drivers/gpio/gpio-f7188x.c data = superio_inb(sio->addr, gpio_out_mode(bank->regbase)); bank 375 drivers/gpio/gpio-f7188x.c superio_outb(sio->addr, gpio_out_mode(bank->regbase), data); bank 399 drivers/gpio/gpio-f7188x.c data->bank = f71869_gpio_bank; bank 403 drivers/gpio/gpio-f7188x.c data->bank = f71869a_gpio_bank; bank 407 drivers/gpio/gpio-f7188x.c data->bank = f71882_gpio_bank; bank 411 drivers/gpio/gpio-f7188x.c data->bank = f71889a_gpio_bank; bank 415 drivers/gpio/gpio-f7188x.c data->bank = f71889_gpio_bank; bank 419 drivers/gpio/gpio-f7188x.c data->bank = f81866_gpio_bank; bank 423 drivers/gpio/gpio-f7188x.c data->bank = f81804_gpio_bank; bank 434 drivers/gpio/gpio-f7188x.c struct f7188x_gpio_bank *bank = &data->bank[i]; bank 436 drivers/gpio/gpio-f7188x.c bank->chip.parent = &pdev->dev; bank 437 drivers/gpio/gpio-f7188x.c bank->data = data; bank 439 drivers/gpio/gpio-f7188x.c err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank); bank 495 drivers/gpio/gpio-lpc32xx.c u32 bank = gpiospec->args[0]; bank 496 drivers/gpio/gpio-lpc32xx.c if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) || bank 497 drivers/gpio/gpio-lpc32xx.c (gc != &lpc32xx_gpiochip[bank].chip))) bank 36 drivers/gpio/gpio-mt7621.c int bank; bank 72 drivers/gpio/gpio-mt7621.c offset = (rg->bank * GPIO_BANK_STRIDE) + offset; bank 82 drivers/gpio/gpio-mt7621.c offset = (rg->bank * GPIO_BANK_STRIDE) + offset; bank 200 drivers/gpio/gpio-mt7621.c if (rg->bank != gpio / MTK_BANK_WIDTH) bank 211 drivers/gpio/gpio-mt7621.c struct device_node *node, int bank) bank 218 drivers/gpio/gpio-mt7621.c rg = &mtk->gc_map[bank]; bank 223 drivers/gpio/gpio-mt7621.c rg->bank = bank; bank 225 drivers/gpio/gpio-mt7621.c dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE); bank 226 drivers/gpio/gpio-mt7621.c set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE); bank 227 drivers/gpio/gpio-mt7621.c ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); bank 228 drivers/gpio/gpio-mt7621.c diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); bank 240 drivers/gpio/gpio-mt7621.c dev_name(dev), bank); bank 75 drivers/gpio/gpio-omap.c void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); bank 81 drivers/gpio/gpio-omap.c #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) bank 106 drivers/gpio/gpio-omap.c static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, bank 109 drivers/gpio/gpio-omap.c bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, bank 115 drivers/gpio/gpio-omap.c static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, bank 118 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; bank 122 drivers/gpio/gpio-omap.c reg += bank->regs->set_dataout; bank 123 drivers/gpio/gpio-omap.c bank->context.dataout |= l; bank 125 drivers/gpio/gpio-omap.c reg += bank->regs->clr_dataout; bank 126 drivers/gpio/gpio-omap.c bank->context.dataout &= ~l; bank 133 drivers/gpio/gpio-omap.c static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, bank 136 drivers/gpio/gpio-omap.c bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, bank 140 drivers/gpio/gpio-omap.c static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) bank 142 drivers/gpio/gpio-omap.c if (bank->dbck_enable_mask && !bank->dbck_enabled) { bank 143 drivers/gpio/gpio-omap.c clk_enable(bank->dbck); bank 144 drivers/gpio/gpio-omap.c bank->dbck_enabled = true; bank 146 drivers/gpio/gpio-omap.c writel_relaxed(bank->dbck_enable_mask, bank 147 drivers/gpio/gpio-omap.c bank->base + bank->regs->debounce_en); bank 151 drivers/gpio/gpio-omap.c static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) bank 153 drivers/gpio/gpio-omap.c if (bank->dbck_enable_mask && bank->dbck_enabled) { bank 159 drivers/gpio/gpio-omap.c writel_relaxed(0, bank->base + bank->regs->debounce_en); bank 161 drivers/gpio/gpio-omap.c clk_disable(bank->dbck); bank 162 drivers/gpio/gpio-omap.c bank->dbck_enabled = false; bank 178 drivers/gpio/gpio-omap.c static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, bank 185 drivers/gpio/gpio-omap.c if (!bank->dbck_flag) bank 196 drivers/gpio/gpio-omap.c clk_enable(bank->dbck); bank 197 drivers/gpio/gpio-omap.c writel_relaxed(debounce, bank->base + bank->regs->debounce); bank 199 drivers/gpio/gpio-omap.c val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); bank 200 drivers/gpio/gpio-omap.c bank->dbck_enable_mask = val; bank 202 drivers/gpio/gpio-omap.c clk_disable(bank->dbck); bank 211 drivers/gpio/gpio-omap.c omap_gpio_dbck_enable(bank); bank 212 drivers/gpio/gpio-omap.c if (bank->dbck_enable_mask) { bank 213 drivers/gpio/gpio-omap.c bank->context.debounce = debounce; bank 214 drivers/gpio/gpio-omap.c bank->context.debounce_en = val; bank 230 drivers/gpio/gpio-omap.c static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) bank 234 drivers/gpio/gpio-omap.c if (!bank->dbck_flag) bank 237 drivers/gpio/gpio-omap.c if (!(bank->dbck_enable_mask & gpio_bit)) bank 240 drivers/gpio/gpio-omap.c bank->dbck_enable_mask &= ~gpio_bit; bank 241 drivers/gpio/gpio-omap.c bank->context.debounce_en &= ~gpio_bit; bank 242 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.debounce_en, bank 243 drivers/gpio/gpio-omap.c bank->base + bank->regs->debounce_en); bank 245 drivers/gpio/gpio-omap.c if (!bank->dbck_enable_mask) { bank 246 drivers/gpio/gpio-omap.c bank->context.debounce = 0; bank 247 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.debounce, bank->base + bank 248 drivers/gpio/gpio-omap.c bank->regs->debounce); bank 249 drivers/gpio/gpio-omap.c clk_disable(bank->dbck); bank 250 drivers/gpio/gpio-omap.c bank->dbck_enabled = false; bank 260 drivers/gpio/gpio-omap.c static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) bank 262 drivers/gpio/gpio-omap.c u32 no_wake = bank->non_wakeup_gpios; bank 270 drivers/gpio/gpio-omap.c static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, bank 273 drivers/gpio/gpio-omap.c void __iomem *base = bank->base; bank 276 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit, bank 278 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit, bank 286 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit, bank 288 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit, bank 291 drivers/gpio/gpio-omap.c bank->context.leveldetect0 = bank 292 drivers/gpio/gpio-omap.c readl_relaxed(bank->base + bank->regs->leveldetect0); bank 293 drivers/gpio/gpio-omap.c bank->context.leveldetect1 = bank 294 drivers/gpio/gpio-omap.c readl_relaxed(bank->base + bank->regs->leveldetect1); bank 295 drivers/gpio/gpio-omap.c bank->context.risingdetect = bank 296 drivers/gpio/gpio-omap.c readl_relaxed(bank->base + bank->regs->risingdetect); bank 297 drivers/gpio/gpio-omap.c bank->context.fallingdetect = bank 298 drivers/gpio/gpio-omap.c readl_relaxed(bank->base + bank->regs->fallingdetect); bank 300 drivers/gpio/gpio-omap.c bank->level_mask = bank->context.leveldetect0 | bank 301 drivers/gpio/gpio-omap.c bank->context.leveldetect1; bank 304 drivers/gpio/gpio-omap.c if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { bank 312 drivers/gpio/gpio-omap.c bank->enabled_non_wakeup_gpios |= gpio_bit; bank 314 drivers/gpio/gpio-omap.c bank->enabled_non_wakeup_gpios &= ~gpio_bit; bank 322 drivers/gpio/gpio-omap.c static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) bank 324 drivers/gpio/gpio-omap.c if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) { bank 325 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->irqctrl; bank 331 drivers/gpio/gpio-omap.c static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, bank 334 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; bank 337 drivers/gpio/gpio-omap.c if (bank->regs->leveldetect0 && bank->regs->wkup_en) { bank 338 drivers/gpio/gpio-omap.c omap_set_gpio_trigger(bank, gpio, trigger); bank 339 drivers/gpio/gpio-omap.c } else if (bank->regs->irqctrl) { bank 340 drivers/gpio/gpio-omap.c reg += bank->regs->irqctrl; bank 344 drivers/gpio/gpio-omap.c bank->toggle_mask |= BIT(gpio); bank 353 drivers/gpio/gpio-omap.c } else if (bank->regs->edgectrl1) { bank 355 drivers/gpio/gpio-omap.c reg += bank->regs->edgectrl2; bank 357 drivers/gpio/gpio-omap.c reg += bank->regs->edgectrl1; bank 371 drivers/gpio/gpio-omap.c static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) bank 373 drivers/gpio/gpio-omap.c if (bank->regs->pinctrl) { bank 374 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->pinctrl; bank 380 drivers/gpio/gpio-omap.c if (bank->regs->ctrl && !BANK_USED(bank)) { bank 381 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->ctrl; bank 388 drivers/gpio/gpio-omap.c bank->context.ctrl = ctrl; bank 392 drivers/gpio/gpio-omap.c static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) bank 394 drivers/gpio/gpio-omap.c if (bank->regs->ctrl && !BANK_USED(bank)) { bank 395 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->ctrl; bank 402 drivers/gpio/gpio-omap.c bank->context.ctrl = ctrl; bank 406 drivers/gpio/gpio-omap.c static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) bank 408 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->direction; bank 413 drivers/gpio/gpio-omap.c static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) bank 415 drivers/gpio/gpio-omap.c if (!LINE_USED(bank->mod_usage, offset)) { bank 416 drivers/gpio/gpio-omap.c omap_enable_gpio_module(bank, offset); bank 417 drivers/gpio/gpio-omap.c omap_set_gpio_direction(bank, offset, 1); bank 419 drivers/gpio/gpio-omap.c bank->irq_usage |= BIT(offset); bank 424 drivers/gpio/gpio-omap.c struct gpio_bank *bank = omap_irq_data_get_bank(d); bank 432 drivers/gpio/gpio-omap.c if (!bank->regs->leveldetect0 && bank 436 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 437 drivers/gpio/gpio-omap.c retval = omap_set_gpio_triggering(bank, offset, type); bank 439 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 442 drivers/gpio/gpio-omap.c omap_gpio_init_irq(bank, offset); bank 443 drivers/gpio/gpio-omap.c if (!omap_gpio_is_input(bank, offset)) { bank 444 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 448 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 467 drivers/gpio/gpio-omap.c static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) bank 469 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; bank 471 drivers/gpio/gpio-omap.c reg += bank->regs->irqstatus; bank 475 drivers/gpio/gpio-omap.c if (bank->regs->irqstatus2) { bank 476 drivers/gpio/gpio-omap.c reg = bank->base + bank->regs->irqstatus2; bank 484 drivers/gpio/gpio-omap.c static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, bank 487 drivers/gpio/gpio-omap.c omap_clear_gpio_irqbank(bank, BIT(offset)); bank 490 drivers/gpio/gpio-omap.c static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) bank 492 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; bank 494 drivers/gpio/gpio-omap.c u32 mask = (BIT(bank->width)) - 1; bank 496 drivers/gpio/gpio-omap.c reg += bank->regs->irqenable; bank 498 drivers/gpio/gpio-omap.c if (bank->regs->irqenable_inv) bank 504 drivers/gpio/gpio-omap.c static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, bank 507 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; bank 510 drivers/gpio/gpio-omap.c if (bank->regs->set_irqenable && bank->regs->clr_irqenable) { bank 512 drivers/gpio/gpio-omap.c reg += bank->regs->set_irqenable; bank 513 drivers/gpio/gpio-omap.c bank->context.irqenable1 |= gpio_mask; bank 515 drivers/gpio/gpio-omap.c reg += bank->regs->clr_irqenable; bank 516 drivers/gpio/gpio-omap.c bank->context.irqenable1 &= ~gpio_mask; bank 520 drivers/gpio/gpio-omap.c bank->context.irqenable1 = bank 521 drivers/gpio/gpio-omap.c omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask, bank 522 drivers/gpio/gpio-omap.c enable ^ bank->regs->irqenable_inv); bank 531 drivers/gpio/gpio-omap.c if (bank->regs->wkup_en && bank 532 drivers/gpio/gpio-omap.c (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) { bank 533 drivers/gpio/gpio-omap.c bank->context.wake_en = bank 534 drivers/gpio/gpio-omap.c omap_gpio_rmw(bank->base + bank->regs->wkup_en, bank 542 drivers/gpio/gpio-omap.c struct gpio_bank *bank = omap_irq_data_get_bank(d); bank 544 drivers/gpio/gpio-omap.c return irq_set_irq_wake(bank->irq, enable); bank 561 drivers/gpio/gpio-omap.c struct gpio_bank *bank = gpiobank; bank 565 drivers/gpio/gpio-omap.c isr_reg = bank->base + bank->regs->irqstatus; bank 569 drivers/gpio/gpio-omap.c if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), bank 574 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, lock_flags); bank 576 drivers/gpio/gpio-omap.c enabled = omap_get_gpio_irqbank_mask(bank); bank 584 drivers/gpio/gpio-omap.c edge = isr & ~bank->level_mask; bank 586 drivers/gpio/gpio-omap.c omap_clear_gpio_irqbank(bank, edge); bank 588 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, lock_flags); bank 597 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, lock_flags); bank 605 drivers/gpio/gpio-omap.c if (bank->toggle_mask & (BIT(bit))) bank 606 drivers/gpio/gpio-omap.c omap_toggle_gpio_edge_triggering(bank, bit); bank 608 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, lock_flags); bank 610 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); bank 612 drivers/gpio/gpio-omap.c generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, bank 615 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->wa_lock, bank 625 drivers/gpio/gpio-omap.c struct gpio_bank *bank = omap_irq_data_get_bank(d); bank 629 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 631 drivers/gpio/gpio-omap.c if (!LINE_USED(bank->mod_usage, offset)) bank 632 drivers/gpio/gpio-omap.c omap_set_gpio_direction(bank, offset, 1); bank 633 drivers/gpio/gpio-omap.c omap_enable_gpio_module(bank, offset); bank 634 drivers/gpio/gpio-omap.c bank->irq_usage |= BIT(offset); bank 636 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 644 drivers/gpio/gpio-omap.c struct gpio_bank *bank = omap_irq_data_get_bank(d); bank 648 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 649 drivers/gpio/gpio-omap.c bank->irq_usage &= ~(BIT(offset)); bank 650 drivers/gpio/gpio-omap.c omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); bank 651 drivers/gpio/gpio-omap.c omap_clear_gpio_irqstatus(bank, offset); bank 652 drivers/gpio/gpio-omap.c omap_set_gpio_irqenable(bank, offset, 0); bank 653 drivers/gpio/gpio-omap.c if (!LINE_USED(bank->mod_usage, offset)) bank 654 drivers/gpio/gpio-omap.c omap_clear_gpio_debounce(bank, offset); bank 655 drivers/gpio/gpio-omap.c omap_disable_gpio_module(bank, offset); bank 656 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 661 drivers/gpio/gpio-omap.c struct gpio_bank *bank = omap_irq_data_get_bank(data); bank 663 drivers/gpio/gpio-omap.c pm_runtime_get_sync(bank->chip.parent); bank 668 drivers/gpio/gpio-omap.c struct gpio_bank *bank = omap_irq_data_get_bank(data); bank 670 drivers/gpio/gpio-omap.c pm_runtime_put(bank->chip.parent); bank 675 drivers/gpio/gpio-omap.c struct gpio_bank *bank = omap_irq_data_get_bank(d); bank 679 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 680 drivers/gpio/gpio-omap.c omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); bank 681 drivers/gpio/gpio-omap.c omap_set_gpio_irqenable(bank, offset, 0); bank 682 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 687 drivers/gpio/gpio-omap.c struct gpio_bank *bank = omap_irq_data_get_bank(d); bank 692 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 693 drivers/gpio/gpio-omap.c omap_set_gpio_irqenable(bank, offset, 1); bank 700 drivers/gpio/gpio-omap.c if (bank->regs->leveldetect0 && bank->regs->wkup_en && bank 702 drivers/gpio/gpio-omap.c omap_clear_gpio_irqstatus(bank, offset); bank 705 drivers/gpio/gpio-omap.c omap_set_gpio_triggering(bank, offset, trigger); bank 707 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 714 drivers/gpio/gpio-omap.c struct gpio_bank *bank = dev_get_drvdata(dev); bank 715 drivers/gpio/gpio-omap.c void __iomem *mask_reg = bank->base + bank 716 drivers/gpio/gpio-omap.c OMAP_MPUIO_GPIO_MASKIT / bank->stride; bank 719 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 720 drivers/gpio/gpio-omap.c writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); bank 721 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 728 drivers/gpio/gpio-omap.c struct gpio_bank *bank = dev_get_drvdata(dev); bank 729 drivers/gpio/gpio-omap.c void __iomem *mask_reg = bank->base + bank 730 drivers/gpio/gpio-omap.c OMAP_MPUIO_GPIO_MASKIT / bank->stride; bank 733 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 734 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.wake_en, mask_reg); bank 735 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 762 drivers/gpio/gpio-omap.c static inline void omap_mpuio_init(struct gpio_bank *bank) bank 764 drivers/gpio/gpio-omap.c platform_set_drvdata(&omap_mpuio_device, bank); bank 774 drivers/gpio/gpio-omap.c struct gpio_bank *bank = gpiochip_get_data(chip); bank 779 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 780 drivers/gpio/gpio-omap.c omap_enable_gpio_module(bank, offset); bank 781 drivers/gpio/gpio-omap.c bank->mod_usage |= BIT(offset); bank 782 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 789 drivers/gpio/gpio-omap.c struct gpio_bank *bank = gpiochip_get_data(chip); bank 792 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 793 drivers/gpio/gpio-omap.c bank->mod_usage &= ~(BIT(offset)); bank 794 drivers/gpio/gpio-omap.c if (!LINE_USED(bank->irq_usage, offset)) { bank 795 drivers/gpio/gpio-omap.c omap_set_gpio_direction(bank, offset, 1); bank 796 drivers/gpio/gpio-omap.c omap_clear_gpio_debounce(bank, offset); bank 798 drivers/gpio/gpio-omap.c omap_disable_gpio_module(bank, offset); bank 799 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 806 drivers/gpio/gpio-omap.c struct gpio_bank *bank = gpiochip_get_data(chip); bank 808 drivers/gpio/gpio-omap.c return !!(readl_relaxed(bank->base + bank->regs->direction) & bank 814 drivers/gpio/gpio-omap.c struct gpio_bank *bank; bank 817 drivers/gpio/gpio-omap.c bank = gpiochip_get_data(chip); bank 818 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 819 drivers/gpio/gpio-omap.c omap_set_gpio_direction(bank, offset, 1); bank 820 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 826 drivers/gpio/gpio-omap.c struct gpio_bank *bank = gpiochip_get_data(chip); bank 829 drivers/gpio/gpio-omap.c if (omap_gpio_is_input(bank, offset)) bank 830 drivers/gpio/gpio-omap.c reg = bank->base + bank->regs->datain; bank 832 drivers/gpio/gpio-omap.c reg = bank->base + bank->regs->dataout; bank 839 drivers/gpio/gpio-omap.c struct gpio_bank *bank; bank 842 drivers/gpio/gpio-omap.c bank = gpiochip_get_data(chip); bank 843 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 844 drivers/gpio/gpio-omap.c bank->set_dataout(bank, offset, value); bank 845 drivers/gpio/gpio-omap.c omap_set_gpio_direction(bank, offset, 0); bank 846 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 853 drivers/gpio/gpio-omap.c struct gpio_bank *bank = gpiochip_get_data(chip); bank 854 drivers/gpio/gpio-omap.c void __iomem *base = bank->base; bank 857 drivers/gpio/gpio-omap.c direction = readl_relaxed(base + bank->regs->direction); bank 861 drivers/gpio/gpio-omap.c val |= readl_relaxed(base + bank->regs->datain) & m; bank 865 drivers/gpio/gpio-omap.c val |= readl_relaxed(base + bank->regs->dataout) & m; bank 875 drivers/gpio/gpio-omap.c struct gpio_bank *bank; bank 879 drivers/gpio/gpio-omap.c bank = gpiochip_get_data(chip); bank 881 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 882 drivers/gpio/gpio-omap.c ret = omap2_set_gpio_debounce(bank, offset, debounce); bank 883 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 907 drivers/gpio/gpio-omap.c struct gpio_bank *bank; bank 910 drivers/gpio/gpio-omap.c bank = gpiochip_get_data(chip); bank 911 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 912 drivers/gpio/gpio-omap.c bank->set_dataout(bank, offset, value); bank 913 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 919 drivers/gpio/gpio-omap.c struct gpio_bank *bank = gpiochip_get_data(chip); bank 920 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->dataout; bank 924 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 927 drivers/gpio/gpio-omap.c bank->context.dataout = l; bank 928 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 933 drivers/gpio/gpio-omap.c static void omap_gpio_show_rev(struct gpio_bank *bank) bank 938 drivers/gpio/gpio-omap.c if (called || bank->regs->revision == USHRT_MAX) bank 941 drivers/gpio/gpio-omap.c rev = readw_relaxed(bank->base + bank->regs->revision); bank 948 drivers/gpio/gpio-omap.c static void omap_gpio_mod_init(struct gpio_bank *bank) bank 950 drivers/gpio/gpio-omap.c void __iomem *base = bank->base; bank 953 drivers/gpio/gpio-omap.c if (bank->width == 16) bank 956 drivers/gpio/gpio-omap.c if (bank->is_mpuio) { bank 957 drivers/gpio/gpio-omap.c writel_relaxed(l, bank->base + bank->regs->irqenable); bank 961 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->irqenable, l, bank 962 drivers/gpio/gpio-omap.c bank->regs->irqenable_inv); bank 963 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->irqstatus, l, bank 964 drivers/gpio/gpio-omap.c !bank->regs->irqenable_inv); bank 965 drivers/gpio/gpio-omap.c if (bank->regs->debounce_en) bank 966 drivers/gpio/gpio-omap.c writel_relaxed(0, base + bank->regs->debounce_en); bank 969 drivers/gpio/gpio-omap.c bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); bank 971 drivers/gpio/gpio-omap.c if (bank->regs->ctrl) bank 972 drivers/gpio/gpio-omap.c writel_relaxed(0, base + bank->regs->ctrl); bank 975 drivers/gpio/gpio-omap.c static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) bank 987 drivers/gpio/gpio-omap.c bank->chip.request = omap_gpio_request; bank 988 drivers/gpio/gpio-omap.c bank->chip.free = omap_gpio_free; bank 989 drivers/gpio/gpio-omap.c bank->chip.get_direction = omap_gpio_get_direction; bank 990 drivers/gpio/gpio-omap.c bank->chip.direction_input = omap_gpio_input; bank 991 drivers/gpio/gpio-omap.c bank->chip.get = omap_gpio_get; bank 992 drivers/gpio/gpio-omap.c bank->chip.get_multiple = omap_gpio_get_multiple; bank 993 drivers/gpio/gpio-omap.c bank->chip.direction_output = omap_gpio_output; bank 994 drivers/gpio/gpio-omap.c bank->chip.set_config = omap_gpio_set_config; bank 995 drivers/gpio/gpio-omap.c bank->chip.set = omap_gpio_set; bank 996 drivers/gpio/gpio-omap.c bank->chip.set_multiple = omap_gpio_set_multiple; bank 997 drivers/gpio/gpio-omap.c if (bank->is_mpuio) { bank 998 drivers/gpio/gpio-omap.c bank->chip.label = "mpuio"; bank 999 drivers/gpio/gpio-omap.c if (bank->regs->wkup_en) bank 1000 drivers/gpio/gpio-omap.c bank->chip.parent = &omap_mpuio_device.dev; bank 1001 drivers/gpio/gpio-omap.c bank->chip.base = OMAP_MPUIO(0); bank 1003 drivers/gpio/gpio-omap.c label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", bank 1004 drivers/gpio/gpio-omap.c gpio, gpio + bank->width - 1); bank 1007 drivers/gpio/gpio-omap.c bank->chip.label = label; bank 1008 drivers/gpio/gpio-omap.c bank->chip.base = gpio; bank 1010 drivers/gpio/gpio-omap.c bank->chip.ngpio = bank->width; bank 1017 drivers/gpio/gpio-omap.c irq_base = devm_irq_alloc_descs(bank->chip.parent, bank 1018 drivers/gpio/gpio-omap.c -1, 0, bank->width, 0); bank 1020 drivers/gpio/gpio-omap.c dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); bank 1026 drivers/gpio/gpio-omap.c if (bank->is_mpuio && !bank->regs->wkup_en) bank 1029 drivers/gpio/gpio-omap.c irq = &bank->chip.irq; bank 1034 drivers/gpio/gpio-omap.c irq->parents = &bank->irq; bank 1037 drivers/gpio/gpio-omap.c ret = gpiochip_add_data(&bank->chip, bank); bank 1039 drivers/gpio/gpio-omap.c dev_err(bank->chip.parent, bank 1044 drivers/gpio/gpio-omap.c ret = devm_request_irq(bank->chip.parent, bank->irq, bank 1046 drivers/gpio/gpio-omap.c 0, dev_name(bank->chip.parent), bank); bank 1048 drivers/gpio/gpio-omap.c gpiochip_remove(&bank->chip); bank 1050 drivers/gpio/gpio-omap.c if (!bank->is_mpuio) bank 1051 drivers/gpio/gpio-omap.c gpio += bank->width; bank 1075 drivers/gpio/gpio-omap.c static void omap_gpio_restore_context(struct gpio_bank *bank) bank 1077 drivers/gpio/gpio-omap.c const struct omap_gpio_reg_offs *regs = bank->regs; bank 1078 drivers/gpio/gpio-omap.c void __iomem *base = bank->base; bank 1080 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.wake_en, base + regs->wkup_en); bank 1081 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.ctrl, base + regs->ctrl); bank 1082 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0); bank 1083 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1); bank 1084 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.risingdetect, base + regs->risingdetect); bank 1085 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect); bank 1086 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.dataout, base + regs->dataout); bank 1087 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.oe, base + regs->direction); bank 1089 drivers/gpio/gpio-omap.c if (bank->dbck_enable_mask) { bank 1090 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.debounce, base + regs->debounce); bank 1091 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.debounce_en, bank 1095 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.irqenable1, base + regs->irqenable); bank 1096 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.irqenable2, base + regs->irqenable2); bank 1099 drivers/gpio/gpio-omap.c static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) bank 1101 drivers/gpio/gpio-omap.c struct device *dev = bank->chip.parent; bank 1102 drivers/gpio/gpio-omap.c void __iomem *base = bank->base; bank 1105 drivers/gpio/gpio-omap.c bank->saved_datain = readl_relaxed(base + bank->regs->datain); bank 1107 drivers/gpio/gpio-omap.c if (!bank->enabled_non_wakeup_gpios) bank 1111 drivers/gpio/gpio-omap.c mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect; bank 1112 drivers/gpio/gpio-omap.c mask &= ~bank->context.risingdetect; bank 1113 drivers/gpio/gpio-omap.c bank->saved_datain |= mask; bank 1116 drivers/gpio/gpio-omap.c mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect; bank 1117 drivers/gpio/gpio-omap.c mask &= ~bank->context.fallingdetect; bank 1118 drivers/gpio/gpio-omap.c bank->saved_datain &= ~mask; bank 1128 drivers/gpio/gpio-omap.c if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { bank 1129 drivers/gpio/gpio-omap.c nowake = bank->enabled_non_wakeup_gpios; bank 1130 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake); bank 1131 drivers/gpio/gpio-omap.c omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake); bank 1135 drivers/gpio/gpio-omap.c if (bank->get_context_loss_count) bank 1136 drivers/gpio/gpio-omap.c bank->context_loss_count = bank 1137 drivers/gpio/gpio-omap.c bank->get_context_loss_count(dev); bank 1139 drivers/gpio/gpio-omap.c omap_gpio_dbck_disable(bank); bank 1142 drivers/gpio/gpio-omap.c static void omap_gpio_unidle(struct gpio_bank *bank) bank 1144 drivers/gpio/gpio-omap.c struct device *dev = bank->chip.parent; bank 1153 drivers/gpio/gpio-omap.c if (bank->loses_context && !bank->context_valid) { bank 1154 drivers/gpio/gpio-omap.c omap_gpio_init_context(bank); bank 1156 drivers/gpio/gpio-omap.c if (bank->get_context_loss_count) bank 1157 drivers/gpio/gpio-omap.c bank->context_loss_count = bank 1158 drivers/gpio/gpio-omap.c bank->get_context_loss_count(dev); bank 1161 drivers/gpio/gpio-omap.c omap_gpio_dbck_enable(bank); bank 1163 drivers/gpio/gpio-omap.c if (bank->loses_context) { bank 1164 drivers/gpio/gpio-omap.c if (!bank->get_context_loss_count) { bank 1165 drivers/gpio/gpio-omap.c omap_gpio_restore_context(bank); bank 1167 drivers/gpio/gpio-omap.c c = bank->get_context_loss_count(dev); bank 1168 drivers/gpio/gpio-omap.c if (c != bank->context_loss_count) { bank 1169 drivers/gpio/gpio-omap.c omap_gpio_restore_context(bank); bank 1176 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.fallingdetect, bank 1177 drivers/gpio/gpio-omap.c bank->base + bank->regs->fallingdetect); bank 1178 drivers/gpio/gpio-omap.c writel_relaxed(bank->context.risingdetect, bank 1179 drivers/gpio/gpio-omap.c bank->base + bank->regs->risingdetect); bank 1182 drivers/gpio/gpio-omap.c l = readl_relaxed(bank->base + bank->regs->datain); bank 1190 drivers/gpio/gpio-omap.c l ^= bank->saved_datain; bank 1191 drivers/gpio/gpio-omap.c l &= bank->enabled_non_wakeup_gpios; bank 1197 drivers/gpio/gpio-omap.c gen0 = l & bank->context.fallingdetect; bank 1198 drivers/gpio/gpio-omap.c gen0 &= bank->saved_datain; bank 1200 drivers/gpio/gpio-omap.c gen1 = l & bank->context.risingdetect; bank 1201 drivers/gpio/gpio-omap.c gen1 &= ~(bank->saved_datain); bank 1204 drivers/gpio/gpio-omap.c gen = l & (~(bank->context.fallingdetect) & bank 1205 drivers/gpio/gpio-omap.c ~(bank->context.risingdetect)); bank 1212 drivers/gpio/gpio-omap.c old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); bank 1213 drivers/gpio/gpio-omap.c old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); bank 1215 drivers/gpio/gpio-omap.c if (!bank->regs->irqstatus_raw0) { bank 1216 drivers/gpio/gpio-omap.c writel_relaxed(old0 | gen, bank->base + bank 1217 drivers/gpio/gpio-omap.c bank->regs->leveldetect0); bank 1218 drivers/gpio/gpio-omap.c writel_relaxed(old1 | gen, bank->base + bank 1219 drivers/gpio/gpio-omap.c bank->regs->leveldetect1); bank 1222 drivers/gpio/gpio-omap.c if (bank->regs->irqstatus_raw0) { bank 1223 drivers/gpio/gpio-omap.c writel_relaxed(old0 | l, bank->base + bank 1224 drivers/gpio/gpio-omap.c bank->regs->leveldetect0); bank 1225 drivers/gpio/gpio-omap.c writel_relaxed(old1 | l, bank->base + bank 1226 drivers/gpio/gpio-omap.c bank->regs->leveldetect1); bank 1228 drivers/gpio/gpio-omap.c writel_relaxed(old0, bank->base + bank->regs->leveldetect0); bank 1229 drivers/gpio/gpio-omap.c writel_relaxed(old1, bank->base + bank->regs->leveldetect1); bank 1236 drivers/gpio/gpio-omap.c struct gpio_bank *bank; bank 1239 drivers/gpio/gpio-omap.c bank = container_of(nb, struct gpio_bank, nb); bank 1241 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 1244 drivers/gpio/gpio-omap.c if (bank->is_suspended) bank 1246 drivers/gpio/gpio-omap.c omap_gpio_idle(bank, true); bank 1250 drivers/gpio/gpio-omap.c if (bank->is_suspended) bank 1252 drivers/gpio/gpio-omap.c omap_gpio_unidle(bank); bank 1255 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 1349 drivers/gpio/gpio-omap.c struct gpio_bank *bank; bank 1359 drivers/gpio/gpio-omap.c bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); bank 1360 drivers/gpio/gpio-omap.c if (!bank) bank 1380 drivers/gpio/gpio-omap.c bank->irq = platform_get_irq(pdev, 0); bank 1381 drivers/gpio/gpio-omap.c if (bank->irq <= 0) { bank 1382 drivers/gpio/gpio-omap.c if (!bank->irq) bank 1383 drivers/gpio/gpio-omap.c bank->irq = -ENXIO; bank 1384 drivers/gpio/gpio-omap.c if (bank->irq != -EPROBE_DEFER) bank 1386 drivers/gpio/gpio-omap.c "can't get irq resource ret=%d\n", bank->irq); bank 1387 drivers/gpio/gpio-omap.c return bank->irq; bank 1390 drivers/gpio/gpio-omap.c bank->chip.parent = dev; bank 1391 drivers/gpio/gpio-omap.c bank->chip.owner = THIS_MODULE; bank 1392 drivers/gpio/gpio-omap.c bank->dbck_flag = pdata->dbck_flag; bank 1393 drivers/gpio/gpio-omap.c bank->stride = pdata->bank_stride; bank 1394 drivers/gpio/gpio-omap.c bank->width = pdata->bank_width; bank 1395 drivers/gpio/gpio-omap.c bank->is_mpuio = pdata->is_mpuio; bank 1396 drivers/gpio/gpio-omap.c bank->non_wakeup_gpios = pdata->non_wakeup_gpios; bank 1397 drivers/gpio/gpio-omap.c bank->regs = pdata->regs; bank 1399 drivers/gpio/gpio-omap.c bank->chip.of_node = of_node_get(node); bank 1404 drivers/gpio/gpio-omap.c bank->loses_context = true; bank 1406 drivers/gpio/gpio-omap.c bank->loses_context = pdata->loses_context; bank 1408 drivers/gpio/gpio-omap.c if (bank->loses_context) bank 1409 drivers/gpio/gpio-omap.c bank->get_context_loss_count = bank 1413 drivers/gpio/gpio-omap.c if (bank->regs->set_dataout && bank->regs->clr_dataout) bank 1414 drivers/gpio/gpio-omap.c bank->set_dataout = omap_set_gpio_dataout_reg; bank 1416 drivers/gpio/gpio-omap.c bank->set_dataout = omap_set_gpio_dataout_mask; bank 1418 drivers/gpio/gpio-omap.c raw_spin_lock_init(&bank->lock); bank 1419 drivers/gpio/gpio-omap.c raw_spin_lock_init(&bank->wa_lock); bank 1422 drivers/gpio/gpio-omap.c bank->base = devm_platform_ioremap_resource(pdev, 0); bank 1423 drivers/gpio/gpio-omap.c if (IS_ERR(bank->base)) { bank 1424 drivers/gpio/gpio-omap.c return PTR_ERR(bank->base); bank 1427 drivers/gpio/gpio-omap.c if (bank->dbck_flag) { bank 1428 drivers/gpio/gpio-omap.c bank->dbck = devm_clk_get(dev, "dbclk"); bank 1429 drivers/gpio/gpio-omap.c if (IS_ERR(bank->dbck)) { bank 1432 drivers/gpio/gpio-omap.c bank->dbck_flag = false; bank 1434 drivers/gpio/gpio-omap.c clk_prepare(bank->dbck); bank 1438 drivers/gpio/gpio-omap.c platform_set_drvdata(pdev, bank); bank 1443 drivers/gpio/gpio-omap.c if (bank->is_mpuio) bank 1444 drivers/gpio/gpio-omap.c omap_mpuio_init(bank); bank 1446 drivers/gpio/gpio-omap.c omap_gpio_mod_init(bank); bank 1448 drivers/gpio/gpio-omap.c ret = omap_gpio_chip_init(bank, irqc); bank 1452 drivers/gpio/gpio-omap.c if (bank->dbck_flag) bank 1453 drivers/gpio/gpio-omap.c clk_unprepare(bank->dbck); bank 1457 drivers/gpio/gpio-omap.c omap_gpio_show_rev(bank); bank 1459 drivers/gpio/gpio-omap.c bank->nb.notifier_call = gpio_omap_cpu_notifier; bank 1460 drivers/gpio/gpio-omap.c cpu_pm_register_notifier(&bank->nb); bank 1469 drivers/gpio/gpio-omap.c struct gpio_bank *bank = platform_get_drvdata(pdev); bank 1471 drivers/gpio/gpio-omap.c cpu_pm_unregister_notifier(&bank->nb); bank 1472 drivers/gpio/gpio-omap.c gpiochip_remove(&bank->chip); bank 1474 drivers/gpio/gpio-omap.c if (bank->dbck_flag) bank 1475 drivers/gpio/gpio-omap.c clk_unprepare(bank->dbck); bank 1482 drivers/gpio/gpio-omap.c struct gpio_bank *bank = dev_get_drvdata(dev); bank 1485 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 1486 drivers/gpio/gpio-omap.c omap_gpio_idle(bank, true); bank 1487 drivers/gpio/gpio-omap.c bank->is_suspended = true; bank 1488 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 1495 drivers/gpio/gpio-omap.c struct gpio_bank *bank = dev_get_drvdata(dev); bank 1498 drivers/gpio/gpio-omap.c raw_spin_lock_irqsave(&bank->lock, flags); bank 1499 drivers/gpio/gpio-omap.c omap_gpio_unidle(bank); bank 1500 drivers/gpio/gpio-omap.c bank->is_suspended = false; bank 1501 drivers/gpio/gpio-omap.c raw_spin_unlock_irqrestore(&bank->lock, flags); bank 220 drivers/gpio/gpio-pca953x.c int bank = (reg & REG_ADDR_MASK) >> bank_shift; bank 227 drivers/gpio/gpio-pca953x.c bank += 8; bank 231 drivers/gpio/gpio-pca953x.c if (!(BIT(bank) & checkbank)) bank 244 drivers/gpio/gpio-pca953x.c u32 bank; bank 247 drivers/gpio/gpio-pca953x.c bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | bank 250 drivers/gpio/gpio-pca953x.c bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | bank 256 drivers/gpio/gpio-pca953x.c bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | bank 261 drivers/gpio/gpio-pca953x.c return pca953x_check_register(chip, reg, bank); bank 267 drivers/gpio/gpio-pca953x.c u32 bank; bank 270 drivers/gpio/gpio-pca953x.c bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | bank 273 drivers/gpio/gpio-pca953x.c bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | bank 278 drivers/gpio/gpio-pca953x.c bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | bank 281 drivers/gpio/gpio-pca953x.c return pca953x_check_register(chip, reg, bank); bank 287 drivers/gpio/gpio-pca953x.c u32 bank; bank 290 drivers/gpio/gpio-pca953x.c bank = PCA953x_BANK_INPUT; bank 292 drivers/gpio/gpio-pca953x.c bank = PCA957x_BANK_INPUT; bank 295 drivers/gpio/gpio-pca953x.c bank |= PCAL9xxx_BANK_IRQ_STAT; bank 297 drivers/gpio/gpio-pca953x.c return pca953x_check_register(chip, reg, bank); bank 460 drivers/gpio/gpio-pca953x.c int bank; bank 469 drivers/gpio/gpio-pca953x.c for (bank = 0; bank < NBANK(chip); bank++) { bank 470 drivers/gpio/gpio-pca953x.c bank_mask = mask[bank / sizeof(*mask)] >> bank 471 drivers/gpio/gpio-pca953x.c ((bank % sizeof(*mask)) * 8); bank 473 drivers/gpio/gpio-pca953x.c bank_val = bits[bank / sizeof(*bits)] >> bank 474 drivers/gpio/gpio-pca953x.c ((bank % sizeof(*bits)) * 8); bank 476 drivers/gpio/gpio-pca953x.c reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; bank 163 drivers/gpio/gpio-pxa.c struct pxa_gpio_bank *bank = p->banks + (gpio / 32); bank 165 drivers/gpio/gpio-pxa.c return bank->regbase; bank 350 drivers/gpio/gpio-pxa.c struct pxa_gpio_bank *bank; bank 377 drivers/gpio/gpio-pxa.c bank = pchip->banks + i; bank 378 drivers/gpio/gpio-pxa.c bank->regbase = regbase + BANK_OFF(i); bank 43 drivers/gpio/gpio-sprd.c unsigned int bank) bank 45 drivers/gpio/gpio-sprd.c return sprd_gpio->base + SPRD_GPIO_BANK_SIZE * bank; bank 189 drivers/gpio/gpio-sprd.c u32 bank, n, girq; bank 193 drivers/gpio/gpio-sprd.c for (bank = 0; bank * SPRD_GPIO_BANK_NR < chip->ngpio; bank++) { bank 194 drivers/gpio/gpio-sprd.c void __iomem *base = sprd_gpio_bank_base(sprd_gpio, bank); bank 200 drivers/gpio/gpio-sprd.c bank * SPRD_GPIO_BANK_NR + n); bank 255 drivers/gpio/gpio-stmpe.c u8 bank = offset / 8; bank 256 drivers/gpio/gpio-stmpe.c u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank]; bank 303 drivers/gpio/gpio-stmpe.c edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank]; bank 310 drivers/gpio/gpio-stmpe.c rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank]; bank 311 drivers/gpio/gpio-stmpe.c fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank]; bank 324 drivers/gpio/gpio-stmpe.c irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank]; bank 396 drivers/gpio/gpio-stmpe.c int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i : bank 398 drivers/gpio/gpio-stmpe.c unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; bank 407 drivers/gpio/gpio-stmpe.c int line = bank * 8 + bit; bank 62 drivers/gpio/gpio-tegra.c unsigned int bank; bank 107 drivers/gpio/gpio-tegra.c static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, bank 110 drivers/gpio/gpio-tegra.c return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); bank 225 drivers/gpio/gpio-tegra.c struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; bank 242 drivers/gpio/gpio-tegra.c spin_lock_irqsave(&bank->dbc_lock[port], flags); bank 243 drivers/gpio/gpio-tegra.c if (bank->dbc_cnt[port] < debounce_ms) { bank 245 drivers/gpio/gpio-tegra.c bank->dbc_cnt[port] = debounce_ms; bank 247 drivers/gpio/gpio-tegra.c spin_unlock_irqrestore(&bank->dbc_lock[port], flags); bank 275 drivers/gpio/gpio-tegra.c struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); bank 276 drivers/gpio/gpio-tegra.c struct tegra_gpio_info *tgi = bank->tgi; bank 284 drivers/gpio/gpio-tegra.c struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); bank 285 drivers/gpio/gpio-tegra.c struct tegra_gpio_info *tgi = bank->tgi; bank 293 drivers/gpio/gpio-tegra.c struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); bank 294 drivers/gpio/gpio-tegra.c struct tegra_gpio_info *tgi = bank->tgi; bank 303 drivers/gpio/gpio-tegra.c struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); bank 304 drivers/gpio/gpio-tegra.c struct tegra_gpio_info *tgi = bank->tgi; bank 334 drivers/gpio/gpio-tegra.c spin_lock_irqsave(&bank->lvl_lock[port], flags); bank 341 drivers/gpio/gpio-tegra.c spin_unlock_irqrestore(&bank->lvl_lock[port], flags); bank 364 drivers/gpio/gpio-tegra.c struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); bank 365 drivers/gpio/gpio-tegra.c struct tegra_gpio_info *tgi = bank->tgi; bank 379 drivers/gpio/gpio-tegra.c struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc); bank 380 drivers/gpio/gpio-tegra.c struct tegra_gpio_info *tgi = bank->tgi; bank 385 drivers/gpio/gpio-tegra.c gpio = tegra_gpio_compose(bank->bank, port, 0); bank 423 drivers/gpio/gpio-tegra.c struct tegra_gpio_bank *bank = &tgi->bank_info[b]; bank 425 drivers/gpio/gpio-tegra.c for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { bank 428 drivers/gpio/gpio-tegra.c tegra_gpio_writel(tgi, bank->cnf[p], bank 432 drivers/gpio/gpio-tegra.c tegra_gpio_writel(tgi, bank->dbc_cnt[p], bank 434 drivers/gpio/gpio-tegra.c tegra_gpio_writel(tgi, bank->dbc_enb[p], bank 438 drivers/gpio/gpio-tegra.c tegra_gpio_writel(tgi, bank->out[p], bank 440 drivers/gpio/gpio-tegra.c tegra_gpio_writel(tgi, bank->oe[p], bank 442 drivers/gpio/gpio-tegra.c tegra_gpio_writel(tgi, bank->int_lvl[p], bank 444 drivers/gpio/gpio-tegra.c tegra_gpio_writel(tgi, bank->int_enb[p], bank 461 drivers/gpio/gpio-tegra.c struct tegra_gpio_bank *bank = &tgi->bank_info[b]; bank 463 drivers/gpio/gpio-tegra.c for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { bank 466 drivers/gpio/gpio-tegra.c bank->cnf[p] = tegra_gpio_readl(tgi, bank 468 drivers/gpio/gpio-tegra.c bank->out[p] = tegra_gpio_readl(tgi, bank 470 drivers/gpio/gpio-tegra.c bank->oe[p] = tegra_gpio_readl(tgi, bank 473 drivers/gpio/gpio-tegra.c bank->dbc_enb[p] = tegra_gpio_readl(tgi, bank 475 drivers/gpio/gpio-tegra.c bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | bank 476 drivers/gpio/gpio-tegra.c bank->dbc_enb[p]; bank 479 drivers/gpio/gpio-tegra.c bank->int_enb[p] = tegra_gpio_readl(tgi, bank 481 drivers/gpio/gpio-tegra.c bank->int_lvl[p] = tegra_gpio_readl(tgi, bank 485 drivers/gpio/gpio-tegra.c tegra_gpio_writel(tgi, bank->wake_enb[p], bank 495 drivers/gpio/gpio-tegra.c struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); bank 504 drivers/gpio/gpio-tegra.c bank->wake_enb[port] |= mask; bank 506 drivers/gpio/gpio-tegra.c bank->wake_enb[port] &= ~mask; bank 508 drivers/gpio/gpio-tegra.c return irq_set_irq_wake(bank->irq, enable); bank 564 drivers/gpio/gpio-tegra.c struct tegra_gpio_bank *bank; bank 631 drivers/gpio/gpio-tegra.c bank = &tgi->bank_info[i]; bank 632 drivers/gpio/gpio-tegra.c bank->bank = i; bank 633 drivers/gpio/gpio-tegra.c bank->irq = ret; bank 634 drivers/gpio/gpio-tegra.c bank->tgi = tgi; bank 659 drivers/gpio/gpio-tegra.c bank = &tgi->bank_info[GPIO_BANK(gpio)]; bank 661 drivers/gpio/gpio-tegra.c irq_set_chip_data(irq, bank); bank 666 drivers/gpio/gpio-tegra.c bank = &tgi->bank_info[i]; bank 668 drivers/gpio/gpio-tegra.c irq_set_chained_handler_and_data(bank->irq, bank 669 drivers/gpio/gpio-tegra.c tegra_gpio_irq_handler, bank); bank 672 drivers/gpio/gpio-tegra.c spin_lock_init(&bank->lvl_lock[j]); bank 673 drivers/gpio/gpio-tegra.c spin_lock_init(&bank->dbc_lock[j]); bank 124 drivers/gpio/gpio-thunderx.c int bank = line / 64; bank 128 drivers/gpio/gpio-thunderx.c (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR); bank 183 drivers/gpio/gpio-thunderx.c int bank = line / 64; bank 187 drivers/gpio/gpio-thunderx.c void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET; bank 259 drivers/gpio/gpio-thunderx.c int bank = line / 64; bank 261 drivers/gpio/gpio-thunderx.c u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT); bank 274 drivers/gpio/gpio-thunderx.c int bank; bank 278 drivers/gpio/gpio-thunderx.c for (bank = 0; bank <= chip->ngpio / 64; bank++) { bank 279 drivers/gpio/gpio-thunderx.c set_bits = bits[bank] & mask[bank]; bank 280 drivers/gpio/gpio-thunderx.c clear_bits = ~bits[bank] & mask[bank]; bank 281 drivers/gpio/gpio-thunderx.c writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); bank 282 drivers/gpio/gpio-thunderx.c writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); bank 39 drivers/gpio/gpio-uniphier.c static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank) bank 43 drivers/gpio/gpio-uniphier.c reg = (bank + 1) * 8; bank 56 drivers/gpio/gpio-uniphier.c unsigned int *bank, u32 *mask) bank 58 drivers/gpio/gpio-uniphier.c *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK; bank 76 drivers/gpio/gpio-uniphier.c static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank, bank 84 drivers/gpio/gpio-uniphier.c uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg, bank 92 drivers/gpio/gpio-uniphier.c unsigned int bank; bank 95 drivers/gpio/gpio-uniphier.c uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); bank 97 drivers/gpio/gpio-uniphier.c uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0); bank 104 drivers/gpio/gpio-uniphier.c unsigned int bank, reg_offset; bank 107 drivers/gpio/gpio-uniphier.c uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); bank 108 drivers/gpio/gpio-uniphier.c reg_offset = uniphier_gpio_bank_to_reg(bank) + reg; bank 150 drivers/gpio/gpio-uniphier.c unsigned int bank, shift, bank_mask, bank_bits; bank 154 drivers/gpio/gpio-uniphier.c bank = i / UNIPHIER_GPIO_LINES_PER_BANK; bank 160 drivers/gpio/gpio-uniphier.c uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA, bank 132 drivers/gpio/gpio-xgene.c unsigned int bank; bank 134 drivers/gpio/gpio-xgene.c for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) { bank 135 drivers/gpio/gpio-xgene.c bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE; bank 136 drivers/gpio/gpio-xgene.c gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset); bank 145 drivers/gpio/gpio-xgene.c unsigned int bank; bank 147 drivers/gpio/gpio-xgene.c for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) { bank 148 drivers/gpio/gpio-xgene.c bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE; bank 149 drivers/gpio/gpio-xgene.c iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset); bank 189 drivers/gpio/gpio-zynq.c int bank; bank 191 drivers/gpio/gpio-zynq.c for (bank = 0; bank < gpio->p_data->max_bank; bank++) { bank 192 drivers/gpio/gpio-zynq.c if ((pin_num >= gpio->p_data->bank_min[bank]) && bank 193 drivers/gpio/gpio-zynq.c (pin_num <= gpio->p_data->bank_max[bank])) { bank 194 drivers/gpio/gpio-zynq.c *bank_num = bank; bank 196 drivers/gpio/gpio-zynq.c gpio->p_data->bank_min[bank]; bank 90 drivers/gpio/sgpio-aspeed.c const struct aspeed_sgpio_bank *bank, bank 95 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->val_regs + GPIO_VAL_VALUE; bank 97 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->rdata_reg; bank 99 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; bank 101 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; bank 103 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; bank 105 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; bank 107 drivers/gpio/sgpio-aspeed.c return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; bank 120 drivers/gpio/sgpio-aspeed.c unsigned int bank = GPIO_BANK(offset); bank 122 drivers/gpio/sgpio-aspeed.c WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks)); bank 123 drivers/gpio/sgpio-aspeed.c return &aspeed_sgpio_banks[bank]; bank 129 drivers/gpio/sgpio-aspeed.c const struct aspeed_sgpio_bank *bank = to_bank(offset); bank 139 drivers/gpio/sgpio-aspeed.c rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); bank 149 drivers/gpio/sgpio-aspeed.c const struct aspeed_sgpio_bank *bank = to_bank(offset); bank 153 drivers/gpio/sgpio-aspeed.c addr = bank_reg(gpio, bank, reg_val); bank 219 drivers/gpio/sgpio-aspeed.c const struct aspeed_sgpio_bank **bank, bank 229 drivers/gpio/sgpio-aspeed.c *bank = to_bank(*offset); bank 235 drivers/gpio/sgpio-aspeed.c const struct aspeed_sgpio_bank *bank; bank 242 drivers/gpio/sgpio-aspeed.c irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); bank 244 drivers/gpio/sgpio-aspeed.c status_addr = bank_reg(gpio, bank, reg_irq_status); bank 255 drivers/gpio/sgpio-aspeed.c const struct aspeed_sgpio_bank *bank; bank 262 drivers/gpio/sgpio-aspeed.c irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); bank 263 drivers/gpio/sgpio-aspeed.c addr = bank_reg(gpio, bank, reg_irq_enable); bank 294 drivers/gpio/sgpio-aspeed.c const struct aspeed_sgpio_bank *bank; bank 301 drivers/gpio/sgpio-aspeed.c irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); bank 326 drivers/gpio/sgpio-aspeed.c addr = bank_reg(gpio, bank, reg_irq_type0); bank 331 drivers/gpio/sgpio-aspeed.c addr = bank_reg(gpio, bank, reg_irq_type1); bank 336 drivers/gpio/sgpio-aspeed.c addr = bank_reg(gpio, bank, reg_irq_type2); bank 359 drivers/gpio/sgpio-aspeed.c const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i]; bank 361 drivers/gpio/sgpio-aspeed.c reg = ioread32(bank_reg(data, bank, reg_irq_status)); bank 385 drivers/gpio/sgpio-aspeed.c const struct aspeed_sgpio_bank *bank; bank 396 drivers/gpio/sgpio-aspeed.c bank = &aspeed_sgpio_banks[i]; bank 398 drivers/gpio/sgpio-aspeed.c iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable)); bank 400 drivers/gpio/sgpio-aspeed.c iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status)); bank 414 drivers/gpio/sgpio-aspeed.c bank = &aspeed_sgpio_banks[i]; bank 416 drivers/gpio/sgpio-aspeed.c iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0)); bank 418 drivers/gpio/sgpio-aspeed.c iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1)); bank 420 drivers/gpio/sgpio-aspeed.c iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_type2)); bank 422 drivers/gpio/sgpio-aspeed.c iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_enable)); bank 695 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; bank 708 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c bank = (*pos & GENMASK_ULL(61, 60)) >> 60; bank 718 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c if (bank == 0) { bank 192 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c buff[i++] = record->bank; bank 219 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c record->bank = buff[i++]; bank 72 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h unsigned char bank; bank 3667 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 tmp, width, row, column, bank, density; bank 3681 drivers/gpu/drm/amd/amdgpu/si_dpm.c bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; bank 3683 drivers/gpu/drm/amd/amdgpu/si_dpm.c density = (1 << (row + column - 20 + bank)) * width; bank 40 drivers/gpu/drm/i915/gt/intel_gt_irq.c const unsigned int bank, const unsigned int bit) bank 48 drivers/gpu/drm/i915/gt/intel_gt_irq.c raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); bank 56 drivers/gpu/drm/i915/gt/intel_gt_irq.c ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank)); bank 62 drivers/gpu/drm/i915/gt/intel_gt_irq.c bank, bit, ident); bank 66 drivers/gpu/drm/i915/gt/intel_gt_irq.c raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank), bank 125 drivers/gpu/drm/i915/gt/intel_gt_irq.c gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank) bank 133 drivers/gpu/drm/i915/gt/intel_gt_irq.c intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); bank 136 drivers/gpu/drm/i915/gt/intel_gt_irq.c const u32 ident = gen11_gt_engine_identity(gt, bank, bit); bank 142 drivers/gpu/drm/i915/gt/intel_gt_irq.c raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw); bank 147 drivers/gpu/drm/i915/gt/intel_gt_irq.c unsigned int bank; bank 151 drivers/gpu/drm/i915/gt/intel_gt_irq.c for (bank = 0; bank < 2; bank++) { bank 152 drivers/gpu/drm/i915/gt/intel_gt_irq.c if (master_ctl & GEN11_GT_DW_IRQ(bank)) bank 153 drivers/gpu/drm/i915/gt/intel_gt_irq.c gen11_gt_bank_handler(gt, bank); bank 160 drivers/gpu/drm/i915/gt/intel_gt_irq.c const unsigned int bank, const unsigned int bit) bank 167 drivers/gpu/drm/i915/gt/intel_gt_irq.c dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); bank 173 drivers/gpu/drm/i915/gt/intel_gt_irq.c gen11_gt_engine_identity(gt, bank, bit); bank 181 drivers/gpu/drm/i915/gt/intel_gt_irq.c raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit)); bank 27 drivers/gpu/drm/i915/gt/intel_gt_irq.h const unsigned int bank, bank 1282 drivers/gpu/drm/i915/i915_irq.c u32 error_status, row, bank, subbank; bank 1314 drivers/gpu/drm/i915/i915_irq.c bank = GEN7_PARITY_ERROR_BANK(error_status); bank 1322 drivers/gpu/drm/i915/i915_irq.c parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); bank 1331 drivers/gpu/drm/i915/i915_irq.c slice, row, bank, subbank); bank 2284 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u8 bank[GPC_MAX] = {}, gpc, i, j; bank 2289 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c data |= bank[gr->tile[i + j]] << (j * 4); bank 2290 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c bank[gr->tile[i + j]]++; bank 129 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c u8 bank[GPC_MAX] = {}, gpc, i, j; bank 134 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c data |= bank[gr->tile[i + j]] << (j * 4); bank 135 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c bank[gr->tile[i + j]]++; bank 3208 drivers/gpu/drm/radeon/si_dpm.c u32 tmp, width, row, column, bank, density; bank 3222 drivers/gpu/drm/radeon/si_dpm.c bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; bank 3224 drivers/gpu/drm/radeon/si_dpm.c density = (1 << (row + column - 20 + bank)) * width; bank 737 drivers/hwmon/abituguru3.c static int abituguru3_read(struct abituguru3_data *data, u8 bank, u8 offset, bank 750 drivers/hwmon/abituguru3.c "sending 0x1A, status: 0x%02x\n", (unsigned int)bank, bank 755 drivers/hwmon/abituguru3.c outb(bank, data->addr + ABIT_UGURU3_CMD); bank 760 drivers/hwmon/abituguru3.c (unsigned int)bank, (unsigned int)offset, x); bank 769 drivers/hwmon/abituguru3.c (unsigned int)bank, (unsigned int)offset, x); bank 778 drivers/hwmon/abituguru3.c (unsigned int)bank, (unsigned int)offset, x); bank 787 drivers/hwmon/abituguru3.c (unsigned int)bank, (unsigned int)offset, x); bank 800 drivers/hwmon/abituguru3.c u8 bank, u8 offset, u8 count, bank 806 drivers/hwmon/abituguru3.c x = abituguru3_read(data, bank, offset + i, count, bank 848 drivers/hwmon/asb100.c int res, bank; bank 852 drivers/hwmon/asb100.c bank = (reg >> 8) & 0x0f; bank 853 drivers/hwmon/asb100.c if (bank > 2) bank 855 drivers/hwmon/asb100.c i2c_smbus_write_byte_data(client, ASB100_REG_BANK, bank); bank 857 drivers/hwmon/asb100.c if (bank == 0 || bank > 2) { bank 861 drivers/hwmon/asb100.c cl = data->lm75[bank - 1]; bank 881 drivers/hwmon/asb100.c if (bank > 2) bank 893 drivers/hwmon/asb100.c int bank; bank 897 drivers/hwmon/asb100.c bank = (reg >> 8) & 0x0f; bank 898 drivers/hwmon/asb100.c if (bank > 2) bank 900 drivers/hwmon/asb100.c i2c_smbus_write_byte_data(client, ASB100_REG_BANK, bank); bank 902 drivers/hwmon/asb100.c if (bank == 0 || bank > 2) { bank 906 drivers/hwmon/asb100.c cl = data->lm75[bank - 1]; bank 922 drivers/hwmon/asb100.c if (bank > 2) bank 1144 drivers/hwmon/nct6775.c u8 bank; /* current register bank */ bank 1418 drivers/hwmon/nct6775.c u8 bank = reg >> 8; bank 1420 drivers/hwmon/nct6775.c if (data->bank != bank) { bank 1422 drivers/hwmon/nct6775.c outb_p(bank, data->addr + DATA_REG_OFFSET); bank 1423 drivers/hwmon/nct6775.c data->bank = bank; bank 3823 drivers/hwmon/nct6775.c data->bank = 0xff; /* Force initial bank selection */ bank 4651 drivers/hwmon/nct6775.c data->bank = 0xff; /* Force initial bank selection */ bank 111 drivers/hwmon/nct7904.c static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank) bank 116 drivers/hwmon/nct7904.c if (data->bank_sel == bank) bank 118 drivers/hwmon/nct7904.c ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank); bank 120 drivers/hwmon/nct7904.c data->bank_sel = bank; bank 133 drivers/hwmon/nct7904.c unsigned int bank, unsigned int reg) bank 138 drivers/hwmon/nct7904.c ret = nct7904_bank_lock(data, bank); bank 151 drivers/hwmon/nct7904.c unsigned int bank, unsigned int reg) bank 156 drivers/hwmon/nct7904.c ret = nct7904_bank_lock(data, bank); bank 173 drivers/hwmon/nct7904.c unsigned int bank, unsigned int reg, u8 val) bank 178 drivers/hwmon/nct7904.c ret = nct7904_bank_lock(data, bank); bank 220 drivers/hwmon/pc87360.c static int pc87360_read_value(struct pc87360_data *data, u8 ldi, u8 bank, bank 222 drivers/hwmon/pc87360.c static void pc87360_write_value(struct pc87360_data *data, u8 ldi, u8 bank, bank 1361 drivers/hwmon/pc87360.c static int pc87360_read_value(struct pc87360_data *data, u8 ldi, u8 bank, bank 1367 drivers/hwmon/pc87360.c if (bank != NO_BANK) bank 1368 drivers/hwmon/pc87360.c outb_p(bank, data->address[ldi] + PC87365_REG_BANK); bank 1375 drivers/hwmon/pc87360.c static void pc87360_write_value(struct pc87360_data *data, u8 ldi, u8 bank, bank 1379 drivers/hwmon/pc87360.c if (bank != NO_BANK) bank 1380 drivers/hwmon/pc87360.c outb_p(bank, data->address[ldi] + PC87365_REG_BANK); bank 151 drivers/hwmon/pc87427.c u8 bank, u8 reg) bank 153 drivers/hwmon/pc87427.c outb(bank, data->address[ldi] + PC87427_REG_BANK); bank 159 drivers/hwmon/pc87427.c u8 bank, u8 reg, u8 value) bank 161 drivers/hwmon/pc87427.c outb(bank, data->address[ldi] + PC87427_REG_BANK); bank 450 drivers/hwmon/w83627ehf.c u8 bank; /* current register bank */ bank 519 drivers/hwmon/w83627ehf.c u8 bank = reg >> 8; bank 520 drivers/hwmon/w83627ehf.c if (data->bank != bank) { bank 522 drivers/hwmon/w83627ehf.c outb_p(bank, data->addr + DATA_REG_OFFSET); bank 523 drivers/hwmon/w83627ehf.c data->bank = bank; bank 2067 drivers/hwmon/w83627ehf.c data->bank = 0xff; /* Force initial bank selection */ bank 2622 drivers/hwmon/w83627ehf.c data->bank = 0xff; /* Force initial bank selection */ bank 1260 drivers/hwmon/w83781d.c int res, bank; bank 1263 drivers/hwmon/w83781d.c bank = (reg >> 8) & 0x0f; bank 1264 drivers/hwmon/w83781d.c if (bank > 2) bank 1267 drivers/hwmon/w83781d.c bank); bank 1268 drivers/hwmon/w83781d.c if (bank == 0 || bank > 2) { bank 1272 drivers/hwmon/w83781d.c cl = data->lm75[bank - 1]; bank 1290 drivers/hwmon/w83781d.c if (bank > 2) bank 1300 drivers/hwmon/w83781d.c int bank; bank 1303 drivers/hwmon/w83781d.c bank = (reg >> 8) & 0x0f; bank 1304 drivers/hwmon/w83781d.c if (bank > 2) bank 1307 drivers/hwmon/w83781d.c bank); bank 1308 drivers/hwmon/w83781d.c if (bank == 0 || bank > 2) { bank 1313 drivers/hwmon/w83781d.c cl = data->lm75[bank - 1]; bank 1327 drivers/hwmon/w83781d.c if (bank > 2) bank 214 drivers/hwmon/w83793.c u8 bank; bank 1611 drivers/hwmon/w83793.c u8 tmp, bank, chip_id; bank 1618 drivers/hwmon/w83793.c bank = i2c_smbus_read_byte_data(client, W83793_REG_BANKSEL); bank 1620 drivers/hwmon/w83793.c tmp = bank & 0x80 ? 0x5c : 0xa3; bank 1631 drivers/hwmon/w83793.c if ((bank & 0x07) == 0 bank 1668 drivers/hwmon/w83793.c data->bank = i2c_smbus_read_byte_data(client, W83793_REG_BANKSEL); bank 2102 drivers/hwmon/w83793.c new_bank |= data->bank & 0xfc; bank 2103 drivers/hwmon/w83793.c if (data->bank != new_bank) { bank 2106 drivers/hwmon/w83793.c data->bank = new_bank; bank 2111 drivers/hwmon/w83793.c new_bank, data->bank, reg); bank 2128 drivers/hwmon/w83793.c new_bank |= data->bank & 0xfc; bank 2129 drivers/hwmon/w83793.c if (data->bank != new_bank) { bank 2136 drivers/hwmon/w83793.c new_bank, data->bank, reg); bank 2139 drivers/hwmon/w83793.c data->bank = new_bank; bank 326 drivers/hwmon/w83795.c u8 bank; bank 393 drivers/hwmon/w83795.c static int w83795_set_bank(struct i2c_client *client, u8 bank) bank 399 drivers/hwmon/w83795.c if ((data->bank & 0x07) == bank) bank 403 drivers/hwmon/w83795.c bank |= data->bank & ~0x07; bank 404 drivers/hwmon/w83795.c err = i2c_smbus_write_byte_data(client, W83795_REG_BANKSEL, bank); bank 408 drivers/hwmon/w83795.c (int)bank, err); bank 411 drivers/hwmon/w83795.c data->bank = bank; bank 1905 drivers/hwmon/w83795.c int bank, vendor_id, device_id, expected, i2c_addr, config; bank 1912 drivers/hwmon/w83795.c bank = i2c_smbus_read_byte_data(client, W83795_REG_BANKSEL); bank 1913 drivers/hwmon/w83795.c if (bank < 0 || (bank & 0x7c)) { bank 1922 drivers/hwmon/w83795.c expected = bank & 0x80 ? 0x5c : 0xa3; bank 1944 drivers/hwmon/w83795.c if ((bank & 0x07) == 0) { bank 1961 drivers/hwmon/w83795.c if ((bank & 0x07) != 0) bank 1963 drivers/hwmon/w83795.c bank & ~0x07); bank 2152 drivers/hwmon/w83795.c data->bank = i2c_smbus_read_byte_data(client, W83795_REG_BANKSEL); bank 132 drivers/hwspinlock/hwspinlock_core.c ret = hwlock->bank->ops->trylock(hwlock); bank 238 drivers/hwspinlock/hwspinlock_core.c if (hwlock->bank->ops->relax) bank 239 drivers/hwspinlock/hwspinlock_core.c hwlock->bank->ops->relax(hwlock); bank 284 drivers/hwspinlock/hwspinlock_core.c hwlock->bank->ops->unlock(hwlock); bank 370 drivers/hwspinlock/hwspinlock_core.c if (hwlock->bank->dev->of_node == args.np) { bank 380 drivers/hwspinlock/hwspinlock_core.c if (id < 0 || id >= hwlock->bank->num_locks) { bank 384 drivers/hwspinlock/hwspinlock_core.c id += hwlock->bank->base_id; bank 486 drivers/hwspinlock/hwspinlock_core.c int hwspin_lock_register(struct hwspinlock_device *bank, struct device *dev, bank 492 drivers/hwspinlock/hwspinlock_core.c if (!bank || !ops || !dev || !num_locks || !ops->trylock || bank 498 drivers/hwspinlock/hwspinlock_core.c bank->dev = dev; bank 499 drivers/hwspinlock/hwspinlock_core.c bank->ops = ops; bank 500 drivers/hwspinlock/hwspinlock_core.c bank->base_id = base_id; bank 501 drivers/hwspinlock/hwspinlock_core.c bank->num_locks = num_locks; bank 504 drivers/hwspinlock/hwspinlock_core.c hwlock = &bank->lock[i]; bank 507 drivers/hwspinlock/hwspinlock_core.c hwlock->bank = bank; bank 534 drivers/hwspinlock/hwspinlock_core.c int hwspin_lock_unregister(struct hwspinlock_device *bank) bank 539 drivers/hwspinlock/hwspinlock_core.c for (i = 0; i < bank->num_locks; i++) { bank 540 drivers/hwspinlock/hwspinlock_core.c hwlock = &bank->lock[i]; bank 542 drivers/hwspinlock/hwspinlock_core.c tmp = hwspin_lock_unregister_single(bank->base_id + i); bank 562 drivers/hwspinlock/hwspinlock_core.c struct hwspinlock_device **bank = res; bank 564 drivers/hwspinlock/hwspinlock_core.c if (WARN_ON(!bank || !*bank)) bank 567 drivers/hwspinlock/hwspinlock_core.c return *bank == data; bank 584 drivers/hwspinlock/hwspinlock_core.c struct hwspinlock_device *bank) bank 589 drivers/hwspinlock/hwspinlock_core.c devm_hwspin_lock_device_match, bank); bank 613 drivers/hwspinlock/hwspinlock_core.c struct hwspinlock_device *bank, bank 624 drivers/hwspinlock/hwspinlock_core.c ret = hwspin_lock_register(bank, dev, ops, base_id, num_locks); bank 626 drivers/hwspinlock/hwspinlock_core.c *ptr = bank; bank 648 drivers/hwspinlock/hwspinlock_core.c struct device *dev = hwlock->bank->dev; bank 809 drivers/hwspinlock/hwspinlock_core.c dev = hwlock->bank->dev; bank 41 drivers/hwspinlock/hwspinlock_internal.h struct hwspinlock_device *bank; bank 64 drivers/hwspinlock/hwspinlock_internal.h int local_id = hwlock - &hwlock->bank->lock[0]; bank 66 drivers/hwspinlock/hwspinlock_internal.h return hwlock->bank->base_id + local_id; bank 77 drivers/hwspinlock/omap_hwspinlock.c struct hwspinlock_device *bank; bank 127 drivers/hwspinlock/omap_hwspinlock.c bank = kzalloc(struct_size(bank, lock, num_locks), GFP_KERNEL); bank 128 drivers/hwspinlock/omap_hwspinlock.c if (!bank) { bank 133 drivers/hwspinlock/omap_hwspinlock.c platform_set_drvdata(pdev, bank); bank 135 drivers/hwspinlock/omap_hwspinlock.c for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++) bank 138 drivers/hwspinlock/omap_hwspinlock.c ret = hwspin_lock_register(bank, &pdev->dev, &omap_hwspinlock_ops, bank 149 drivers/hwspinlock/omap_hwspinlock.c kfree(bank); bank 158 drivers/hwspinlock/omap_hwspinlock.c struct hwspinlock_device *bank = platform_get_drvdata(pdev); bank 159 drivers/hwspinlock/omap_hwspinlock.c void __iomem *io_base = bank->lock[0].priv - LOCK_BASE_OFFSET; bank 162 drivers/hwspinlock/omap_hwspinlock.c ret = hwspin_lock_unregister(bank); bank 170 drivers/hwspinlock/omap_hwspinlock.c kfree(bank); bank 76 drivers/hwspinlock/qcom_hwspinlock.c struct hwspinlock_device *bank; bank 110 drivers/hwspinlock/qcom_hwspinlock.c bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL); bank 111 drivers/hwspinlock/qcom_hwspinlock.c if (!bank) bank 114 drivers/hwspinlock/qcom_hwspinlock.c platform_set_drvdata(pdev, bank); bank 121 drivers/hwspinlock/qcom_hwspinlock.c bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev, bank 127 drivers/hwspinlock/qcom_hwspinlock.c ret = hwspin_lock_register(bank, &pdev->dev, &qcom_hwspinlock_ops, bank 137 drivers/hwspinlock/qcom_hwspinlock.c struct hwspinlock_device *bank = platform_get_drvdata(pdev); bank 140 drivers/hwspinlock/qcom_hwspinlock.c ret = hwspin_lock_unregister(bank); bank 24 drivers/hwspinlock/sirf_hwspinlock.c struct hwspinlock_device bank; bank 65 drivers/hwspinlock/sirf_hwspinlock.c struct_size(hwspin, bank.lock, bank 77 drivers/hwspinlock/sirf_hwspinlock.c hwlock = &hwspin->bank.lock[idx]; bank 85 drivers/hwspinlock/sirf_hwspinlock.c ret = hwspin_lock_register(&hwspin->bank, &pdev->dev, bank 105 drivers/hwspinlock/sirf_hwspinlock.c ret = hwspin_lock_unregister(&hwspin->bank); bank 39 drivers/hwspinlock/sprd_hwspinlock.c struct hwspinlock_device bank; bank 46 drivers/hwspinlock/sprd_hwspinlock.c dev_get_drvdata(lock->bank->dev); bank 56 drivers/hwspinlock/sprd_hwspinlock.c dev_warn(sprd_hwlock->bank.dev, bank 116 drivers/hwspinlock/sprd_hwspinlock.c lock = &sprd_hwlock->bank.lock[i]; bank 123 drivers/hwspinlock/sprd_hwspinlock.c ret = hwspin_lock_register(&sprd_hwlock->bank, &pdev->dev, bank 138 drivers/hwspinlock/sprd_hwspinlock.c hwspin_lock_unregister(&sprd_hwlock->bank); bank 25 drivers/hwspinlock/stm32_hwspinlock.c struct hwspinlock_device bank; bank 80 drivers/hwspinlock/stm32_hwspinlock.c hw->bank.lock[i].priv = io_base + i * sizeof(u32); bank 85 drivers/hwspinlock/stm32_hwspinlock.c ret = hwspin_lock_register(&hw->bank, &pdev->dev, &stm32_hwspinlock_ops, bank 99 drivers/hwspinlock/stm32_hwspinlock.c ret = hwspin_lock_unregister(&hw->bank); bank 89 drivers/hwspinlock/u8500_hsem.c struct hwspinlock_device *bank; bank 114 drivers/hwspinlock/u8500_hsem.c bank = kzalloc(struct_size(bank, lock, num_locks), GFP_KERNEL); bank 115 drivers/hwspinlock/u8500_hsem.c if (!bank) { bank 120 drivers/hwspinlock/u8500_hsem.c platform_set_drvdata(pdev, bank); bank 122 drivers/hwspinlock/u8500_hsem.c for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++) bank 128 drivers/hwspinlock/u8500_hsem.c ret = hwspin_lock_register(bank, &pdev->dev, &u8500_hwspinlock_ops, bank 137 drivers/hwspinlock/u8500_hsem.c kfree(bank); bank 145 drivers/hwspinlock/u8500_hsem.c struct hwspinlock_device *bank = platform_get_drvdata(pdev); bank 146 drivers/hwspinlock/u8500_hsem.c void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET; bank 152 drivers/hwspinlock/u8500_hsem.c ret = hwspin_lock_unregister(bank); bank 160 drivers/hwspinlock/u8500_hsem.c kfree(bank); bank 761 drivers/iio/gyro/mpu3050-core.c u8 bank, bank 770 drivers/iio/gyro/mpu3050-core.c bank); bank 77 drivers/input/keyboard/adp5588-keys.c unsigned int bank = ADP5588_BANK(kpad->gpiomap[off]); bank 83 drivers/input/keyboard/adp5588-keys.c if (kpad->dir[bank] & bit) bank 84 drivers/input/keyboard/adp5588-keys.c val = kpad->dat_out[bank]; bank 86 drivers/input/keyboard/adp5588-keys.c val = adp5588_read(kpad->client, GPIO_DAT_STAT1 + bank); bank 97 drivers/input/keyboard/adp5588-keys.c unsigned int bank = ADP5588_BANK(kpad->gpiomap[off]); bank 103 drivers/input/keyboard/adp5588-keys.c kpad->dat_out[bank] |= bit; bank 105 drivers/input/keyboard/adp5588-keys.c kpad->dat_out[bank] &= ~bit; bank 107 drivers/input/keyboard/adp5588-keys.c adp5588_write(kpad->client, GPIO_DAT_OUT1 + bank, bank 108 drivers/input/keyboard/adp5588-keys.c kpad->dat_out[bank]); bank 116 drivers/input/keyboard/adp5588-keys.c unsigned int bank = ADP5588_BANK(kpad->gpiomap[off]); bank 122 drivers/input/keyboard/adp5588-keys.c kpad->dir[bank] &= ~bit; bank 123 drivers/input/keyboard/adp5588-keys.c ret = adp5588_write(kpad->client, GPIO_DIR1 + bank, kpad->dir[bank]); bank 134 drivers/input/keyboard/adp5588-keys.c unsigned int bank = ADP5588_BANK(kpad->gpiomap[off]); bank 140 drivers/input/keyboard/adp5588-keys.c kpad->dir[bank] |= bit; bank 143 drivers/input/keyboard/adp5588-keys.c kpad->dat_out[bank] |= bit; bank 145 drivers/input/keyboard/adp5588-keys.c kpad->dat_out[bank] &= ~bit; bank 147 drivers/input/keyboard/adp5588-keys.c ret = adp5588_write(kpad->client, GPIO_DAT_OUT1 + bank, bank 148 drivers/input/keyboard/adp5588-keys.c kpad->dat_out[bank]); bank 149 drivers/input/keyboard/adp5588-keys.c ret |= adp5588_write(kpad->client, GPIO_DIR1 + bank, bank 150 drivers/input/keyboard/adp5588-keys.c kpad->dir[bank]); bank 224 drivers/input/keyboard/adp5589-keys.c u8 (*bank) (u8 offset); bank 286 drivers/input/keyboard/adp5589-keys.c .bank = adp5589_bank, bank 367 drivers/input/keyboard/adp5589-keys.c .bank = adp5585_bank, bank 391 drivers/input/keyboard/adp5589-keys.c unsigned int bank = kpad->var->bank(kpad->gpiomap[off]); bank 395 drivers/input/keyboard/adp5589-keys.c kpad->var->reg(ADP5589_GPI_STATUS_A) + bank) & bank 403 drivers/input/keyboard/adp5589-keys.c unsigned int bank = kpad->var->bank(kpad->gpiomap[off]); bank 409 drivers/input/keyboard/adp5589-keys.c kpad->dat_out[bank] |= bit; bank 411 drivers/input/keyboard/adp5589-keys.c kpad->dat_out[bank] &= ~bit; bank 414 drivers/input/keyboard/adp5589-keys.c bank, kpad->dat_out[bank]); bank 422 drivers/input/keyboard/adp5589-keys.c unsigned int bank = kpad->var->bank(kpad->gpiomap[off]); bank 428 drivers/input/keyboard/adp5589-keys.c kpad->dir[bank] &= ~bit; bank 430 drivers/input/keyboard/adp5589-keys.c kpad->var->reg(ADP5589_GPIO_DIRECTION_A) + bank, bank 431 drivers/input/keyboard/adp5589-keys.c kpad->dir[bank]); bank 442 drivers/input/keyboard/adp5589-keys.c unsigned int bank = kpad->var->bank(kpad->gpiomap[off]); bank 448 drivers/input/keyboard/adp5589-keys.c kpad->dir[bank] |= bit; bank 451 drivers/input/keyboard/adp5589-keys.c kpad->dat_out[bank] |= bit; bank 453 drivers/input/keyboard/adp5589-keys.c kpad->dat_out[bank] &= ~bit; bank 456 drivers/input/keyboard/adp5589-keys.c + bank, kpad->dat_out[bank]); bank 458 drivers/input/keyboard/adp5589-keys.c kpad->var->reg(ADP5589_GPIO_DIRECTION_A) + bank, bank 459 drivers/input/keyboard/adp5589-keys.c kpad->dir[bank]); bank 535 drivers/input/keyboard/adp5589-keys.c for (i = 0; i <= kpad->var->bank(kpad->var->maxgpio); i++) { bank 164 drivers/input/misc/pmic8xxx-pwrkey.c u8 vref_sel, vlow_sel, band, vprog, bank; bank 167 drivers/input/misc/pmic8xxx-pwrkey.c bank = PM8058_REGULATOR_BANK_SEL(7); bank 168 drivers/input/misc/pmic8xxx-pwrkey.c error = regmap_write(regmap, test2_addr, bank); bank 210 drivers/input/misc/pmic8xxx-pwrkey.c bank = PM8058_REGULATOR_BANK_SEL(1); bank 211 drivers/input/misc/pmic8xxx-pwrkey.c error = regmap_write(regmap, test2_addr, bank); bank 224 drivers/input/misc/pmic8xxx-pwrkey.c bank = PM8058_REGULATOR_BANK_SEL(7); bank 225 drivers/input/misc/pmic8xxx-pwrkey.c error = regmap_write(regmap, test2_addr, bank); bank 1658 drivers/iommu/amd_iommu_init.c static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, bank 3132 drivers/iommu/amd_iommu_init.c static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, bank 3146 drivers/iommu/amd_iommu_init.c offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); bank 3170 drivers/iommu/amd_iommu_init.c int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) bank 3175 drivers/iommu/amd_iommu_init.c return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); bank 3179 drivers/iommu/amd_iommu_init.c int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) bank 3184 drivers/iommu/amd_iommu_init.c return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); bank 196 drivers/irqchip/irq-bcm2835.c static u32 armctrl_translate_bank(int bank) bank 198 drivers/irqchip/irq-bcm2835.c u32 stat = readl_relaxed(intc.pending[bank]); bank 200 drivers/irqchip/irq-bcm2835.c return MAKE_HWIRQ(bank, ffs(stat) - 1); bank 203 drivers/irqchip/irq-bcm2835.c static u32 armctrl_translate_shortcut(int bank, u32 stat) bank 205 drivers/irqchip/irq-bcm2835.c return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]); bank 628 drivers/irqchip/irq-stm32-exti.c int p_irq, bank; bank 631 drivers/irqchip/irq-stm32-exti.c bank = hwirq / IRQS_PER_BANK; bank 632 drivers/irqchip/irq-stm32-exti.c chip_data = &host_data->chips_data[bank]; bank 58 drivers/leds/leds-mc13783.c unsigned int reg, bank, off, shift; bank 77 drivers/leds/leds-mc13783.c bank = off / 3; bank 78 drivers/leds/leds-mc13783.c reg = 3 + bank; bank 79 drivers/leds/leds-mc13783.c shift = (off - bank * 3) * 5 + 6; bank 92 drivers/leds/leds-mc13783.c bank = off / 2; bank 93 drivers/leds/leds-mc13783.c reg = 2 + bank; bank 94 drivers/leds/leds-mc13783.c shift = (off - bank * 2) * 12 + 3; bank 176 drivers/leds/leds-tca6507.c } bank[3]; bank 187 drivers/leds/leds-tca6507.c int bank; /* Bank used, or -1 */ bank 293 drivers/leds/leds-tca6507.c static void set_code(struct tca6507_chip *tca, int reg, int bank, int new) bank 297 drivers/leds/leds-tca6507.c if (bank) { bank 310 drivers/leds/leds-tca6507.c static void set_level(struct tca6507_chip *tca, int bank, int level) bank 312 drivers/leds/leds-tca6507.c switch (bank) { bank 315 drivers/leds/leds-tca6507.c set_code(tca, TCA6507_MAX_INTENSITY, bank, level); bank 321 drivers/leds/leds-tca6507.c tca->bank[bank].level = level; bank 325 drivers/leds/leds-tca6507.c static void set_times(struct tca6507_chip *tca, int bank) bank 330 drivers/leds/leds-tca6507.c result = choose_times(tca->bank[bank].ontime, &c1, &c2); bank 336 drivers/leds/leds-tca6507.c c2, time_codes[c2], tca->bank[bank].ontime); bank 337 drivers/leds/leds-tca6507.c set_code(tca, TCA6507_FADE_ON, bank, c2); bank 338 drivers/leds/leds-tca6507.c set_code(tca, TCA6507_FULL_ON, bank, c1); bank 339 drivers/leds/leds-tca6507.c tca->bank[bank].ontime = result; bank 341 drivers/leds/leds-tca6507.c result = choose_times(tca->bank[bank].offtime, &c1, &c2); bank 345 drivers/leds/leds-tca6507.c c2, time_codes[c2], tca->bank[bank].offtime); bank 346 drivers/leds/leds-tca6507.c set_code(tca, TCA6507_FADE_OFF, bank, c2); bank 347 drivers/leds/leds-tca6507.c set_code(tca, TCA6507_FIRST_OFF, bank, c1); bank 348 drivers/leds/leds-tca6507.c set_code(tca, TCA6507_SECOND_OFF, bank, c1); bank 349 drivers/leds/leds-tca6507.c tca->bank[bank].offtime = result; bank 351 drivers/leds/leds-tca6507.c set_code(tca, TCA6507_INITIALIZE, bank, INIT_CODE); bank 380 drivers/leds/leds-tca6507.c if (led->bank >= 0) { bank 381 drivers/leds/leds-tca6507.c struct bank *b = tca->bank + led->bank; bank 387 drivers/leds/leds-tca6507.c led->bank = -1; bank 398 drivers/leds/leds-tca6507.c struct bank *b; bank 424 drivers/leds/leds-tca6507.c if (tca->bank[i].level == level || bank 425 drivers/leds/leds-tca6507.c tca->bank[i].level_use == 0) { bank 429 drivers/leds/leds-tca6507.c d = abs(level - tca->bank[i].level); bank 442 drivers/leds/leds-tca6507.c if (!tca->bank[best].level_use) bank 445 drivers/leds/leds-tca6507.c tca->bank[best].level_use++; bank 446 drivers/leds/leds-tca6507.c led->bank = best; bank 448 drivers/leds/leds-tca6507.c led->led_cdev.brightness = TO_BRIGHT(tca->bank[best].level); bank 463 drivers/leds/leds-tca6507.c if (tca->bank[i].level_use == 0) bank 466 drivers/leds/leds-tca6507.c if (tca->bank[i].level != level) bank 473 drivers/leds/leds-tca6507.c if (tca->bank[i].time_use == 0) bank 477 drivers/leds/leds-tca6507.c if (!(tca->bank[i].on_dflt || bank 479 drivers/leds/leds-tca6507.c tca->bank[i].ontime == led->ontime)) bank 483 drivers/leds/leds-tca6507.c if (!(tca->bank[i].off_dflt || bank 485 drivers/leds/leds-tca6507.c tca->bank[i].offtime == led->offtime)) bank 497 drivers/leds/leds-tca6507.c b = &tca->bank[i]; bank 501 drivers/leds/leds-tca6507.c led->bank = i; bank 795 drivers/leds/leds-tca6507.c l->bank = -1; bank 76 drivers/media/common/b2c2/flexcop-sram.c static void flexcop_sram_write(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len) bank 82 drivers/media/common/b2c2/flexcop-sram.c command = bank | addr | 0x04000000 | (*buf << 0x10); bank 101 drivers/media/common/b2c2/flexcop-sram.c static void flex_sram_read(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len) bank 107 drivers/media/common/b2c2/flexcop-sram.c command = bank | addr | 0x04008000; bank 142 drivers/media/common/b2c2/flexcop-sram.c u32 bank; bank 144 drivers/media/common/b2c2/flexcop-sram.c bank = 0; bank 147 drivers/media/common/b2c2/flexcop-sram.c bank = (addr & 0x18000) << 0x0d; bank 152 drivers/media/common/b2c2/flexcop-sram.c bank = 0x20000000; bank 154 drivers/media/common/b2c2/flexcop-sram.c bank = 0x10000000; bank 156 drivers/media/common/b2c2/flexcop-sram.c flex_sram_write(adapter, bank, addr & 0x7fff, buf, len); bank 161 drivers/media/common/b2c2/flexcop-sram.c u32 bank; bank 162 drivers/media/common/b2c2/flexcop-sram.c bank = 0; bank 165 drivers/media/common/b2c2/flexcop-sram.c bank = (addr & 0x18000) << 0x0d; bank 170 drivers/media/common/b2c2/flexcop-sram.c bank = 0x20000000; bank 172 drivers/media/common/b2c2/flexcop-sram.c bank = 0x10000000; bank 174 drivers/media/common/b2c2/flexcop-sram.c flex_sram_read(adapter, bank, addr & 0x7fff, buf, len); bank 1859 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c 0x00, tnr_dmd->cfg_mem[i].bank); bank 1877 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c u8 bank, u8 address, u8 value, u8 bit_mask) bank 1888 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c tnr_dmd->cfg_mem[i].bank == bank && bank 1904 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c tnr_dmd->cfg_mem[tnr_dmd->cfg_mem_last_entry].bank = bank; bank 3248 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c u8 bank, u8 address, bank 3260 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c ret = tnr_dmd->io->write_reg(tnr_dmd->io, tgt, 0x00, bank); bank 3269 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.c return set_cfg_mem(tnr_dmd, tgt, bank, address, value, bit_mask); bank 154 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.h u8 bank; bank 319 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd.h u8 bank, u8 address, bank 428 drivers/media/i2c/max2175.c u8 bank, const u16 *coeffs) bank 433 drivers/media/i2c/max2175.c mxm_dbg(ctx, "set_filter_coeffs: m_sel %d bank %d\n", m_sel, bank); bank 440 drivers/media/i2c/max2175.c coeff_addr = i + bank * 24; bank 166 drivers/media/i2c/rj54n1cb0c.c u8 bank; bank 436 drivers/media/i2c/rj54n1cb0c.c if (rj54n1->bank != reg >> 8) { bank 441 drivers/media/i2c/rj54n1cb0c.c rj54n1->bank = reg >> 8; bank 453 drivers/media/i2c/rj54n1cb0c.c if (rj54n1->bank != reg >> 8) { bank 458 drivers/media/i2c/rj54n1cb0c.c rj54n1->bank = reg >> 8; bank 206 drivers/media/pci/ttpci/dvb_filter.h int bank; bank 242 drivers/media/rc/winbond-cir.c wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank) bank 244 drivers/media/rc/winbond-cir.c outb(bank, data->sbase + WBCIR_REG_SP3_BSR); bank 69 drivers/memory/jz4780-nemc.c unsigned int bank, count = 0; bank 74 drivers/memory/jz4780-nemc.c bank = of_read_number(prop, 1); bank 75 drivers/memory/jz4780-nemc.c if (!(referenced & BIT(bank))) { bank 76 drivers/memory/jz4780-nemc.c referenced |= BIT(bank); bank 91 drivers/memory/jz4780-nemc.c void jz4780_nemc_set_type(struct device *dev, unsigned int bank, bank 102 drivers/memory/jz4780-nemc.c nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank)); bank 105 drivers/memory/jz4780-nemc.c nfcsr &= ~NEMC_NFCSR_TNFEn(bank); bank 106 drivers/memory/jz4780-nemc.c nfcsr |= NEMC_NFCSR_NFEn(bank); bank 123 drivers/memory/jz4780-nemc.c void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert) bank 131 drivers/memory/jz4780-nemc.c nfcsr |= NEMC_NFCSR_NFCEn(bank); bank 133 drivers/memory/jz4780-nemc.c nfcsr &= ~NEMC_NFCSR_NFCEn(bank); bank 157 drivers/memory/jz4780-nemc.c unsigned int bank, bank 185 drivers/memory/jz4780-nemc.c smcr = readl(nemc->base + NEMC_SMCRn(bank)); bank 264 drivers/memory/jz4780-nemc.c writel(smcr, nemc->base + NEMC_SMCRn(bank)); bank 275 drivers/memory/jz4780-nemc.c unsigned int bank; bank 328 drivers/memory/jz4780-nemc.c bank = of_read_number(prop, 1); bank 329 drivers/memory/jz4780-nemc.c if (bank < 1 || bank >= JZ4780_NEMC_NUM_BANKS) { bank 332 drivers/memory/jz4780-nemc.c child, bank); bank 339 drivers/memory/jz4780-nemc.c referenced |= BIT(bank); bank 353 drivers/memory/jz4780-nemc.c for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) { bank 354 drivers/memory/jz4780-nemc.c if (!jz4780_nemc_configure_bank(nemc, bank, child)) { bank 70 drivers/memory/samsung/exynos-srom.c u32 bank, width, pmc = 0; bank 74 drivers/memory/samsung/exynos-srom.c if (of_property_read_u32(np, "reg", &bank)) bank 84 drivers/memory/samsung/exynos-srom.c bank *= 4; /* Convert bank into shift/offset */ bank 91 drivers/memory/samsung/exynos-srom.c bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank); bank 100 drivers/memory/samsung/exynos-srom.c srom->reg_base + EXYNOS_SROM_BC0 + bank); bank 107 drivers/mfd/ab3100-core.c u8 bank, u8 reg, u8 value) bank 207 drivers/mfd/ab3100-core.c static int get_register_interruptible(struct device *dev, u8 bank, u8 reg, bank 270 drivers/mfd/ab3100-core.c static int get_register_page_interruptible(struct device *dev, u8 bank, bank 348 drivers/mfd/ab3100-core.c static int mask_and_set_register_interruptible(struct device *dev, u8 bank, bank 211 drivers/mfd/ab8500-core.c static int set_register_interruptible(struct ab8500 *ab8500, u8 bank, bank 219 drivers/mfd/ab8500-core.c u16 addr = ((u16)bank) << 8 | reg; bank 234 drivers/mfd/ab8500-core.c static int ab8500_set_register(struct device *dev, u8 bank, bank 241 drivers/mfd/ab8500-core.c ret = set_register_interruptible(ab8500, bank, reg, value); bank 246 drivers/mfd/ab8500-core.c static int get_register_interruptible(struct ab8500 *ab8500, u8 bank, bank 250 drivers/mfd/ab8500-core.c u16 addr = ((u16)bank) << 8 | reg; bank 267 drivers/mfd/ab8500-core.c static int ab8500_get_register(struct device *dev, u8 bank, bank 274 drivers/mfd/ab8500-core.c ret = get_register_interruptible(ab8500, bank, reg, value); bank 279 drivers/mfd/ab8500-core.c static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank, bank 283 drivers/mfd/ab8500-core.c u16 addr = ((u16)bank) << 8 | reg; bank 319 drivers/mfd/ab8500-core.c u8 bank, u8 reg, u8 bitmask, u8 bitvalues) bank 325 drivers/mfd/ab8500-core.c ret = mask_and_set_register_interruptible(ab8500, bank, reg, bank 137 drivers/mfd/ab8500-debugfs.c u32 bank; /* target bank */ bank 1280 drivers/mfd/ab8500-debugfs.c static int ab8500_registers_print(struct device *dev, u32 bank, bank 1285 drivers/mfd/ab8500-debugfs.c for (i = 0; i < debug_ranges[bank].num_ranges; i++) { bank 1288 drivers/mfd/ab8500-debugfs.c for (reg = debug_ranges[bank].range[i].first; bank 1289 drivers/mfd/ab8500-debugfs.c reg <= debug_ranges[bank].range[i].last; bank 1295 drivers/mfd/ab8500-debugfs.c (u8)bank, (u8)reg, &value); bank 1303 drivers/mfd/ab8500-debugfs.c bank, reg, value); bank 1312 drivers/mfd/ab8500-debugfs.c bank, reg, value); bank 1323 drivers/mfd/ab8500-debugfs.c u32 bank = debug_bank; bank 1327 drivers/mfd/ab8500-debugfs.c seq_printf(s, " bank 0x%02X:\n", bank); bank 1329 drivers/mfd/ab8500-debugfs.c return ab8500_registers_print(dev, bank, s); bank 1560 drivers/mfd/ab8500-debugfs.c (u8)hwreg_cfg.bank, (u8)hwreg_cfg.addr, ®value); bank 1598 drivers/mfd/ab8500-debugfs.c u32 bank = AB8500_REGU_CTRL2; bank 1618 drivers/mfd/ab8500-debugfs.c seq_printf(s, " bank 0x%02X:\n", bank); bank 1625 drivers/mfd/ab8500-debugfs.c bank, reg, &value); bank 1629 drivers/mfd/ab8500-debugfs.c seq_printf(s, " [0x%02X/0x%02X]: 0x%02X\n", bank, reg, value); bank 2315 drivers/mfd/ab8500-debugfs.c .bank = 0, /* default: invalid phys addr */ bank 2369 drivers/mfd/ab8500-debugfs.c ret = kstrtouint(b, 0, &loc.bank); bank 2404 drivers/mfd/ab8500-debugfs.c (u8)cfg->bank, (u8)cfg->addr, ®value); bank 2421 drivers/mfd/ab8500-debugfs.c (u8)cfg->bank, (u8)cfg->addr, (u8)val); bank 93 drivers/mfd/ab8500-sysctrl.c static inline bool valid_bank(u8 bank) bank 95 drivers/mfd/ab8500-sysctrl.c return ((bank == AB8500_SYS_CTRL1_BLOCK) || bank 96 drivers/mfd/ab8500-sysctrl.c (bank == AB8500_SYS_CTRL2_BLOCK)); bank 101 drivers/mfd/ab8500-sysctrl.c u8 bank; bank 106 drivers/mfd/ab8500-sysctrl.c bank = (reg >> 8); bank 107 drivers/mfd/ab8500-sysctrl.c if (!valid_bank(bank)) bank 110 drivers/mfd/ab8500-sysctrl.c return abx500_get_register_interruptible(sysctrl_dev, bank, bank 117 drivers/mfd/ab8500-sysctrl.c u8 bank; bank 122 drivers/mfd/ab8500-sysctrl.c bank = (reg >> 8); bank 123 drivers/mfd/ab8500-sysctrl.c if (!valid_bank(bank)) { bank 128 drivers/mfd/ab8500-sysctrl.c return abx500_mask_and_set_register_interruptible(sysctrl_dev, bank, bank 62 drivers/mfd/abx500-core.c int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg, bank 69 drivers/mfd/abx500-core.c return ops->set_register(dev, bank, reg, value); bank 75 drivers/mfd/abx500-core.c int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg, bank 82 drivers/mfd/abx500-core.c return ops->get_register(dev, bank, reg, value); bank 88 drivers/mfd/abx500-core.c int abx500_get_register_page_interruptible(struct device *dev, u8 bank, bank 95 drivers/mfd/abx500-core.c return ops->get_register_page(dev, bank, bank 102 drivers/mfd/abx500-core.c int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank, bank 109 drivers/mfd/abx500-core.c return ops->mask_and_set_register(dev, bank, bank 150 drivers/mfd/asic3.c int bank; bank 162 drivers/mfd/asic3.c for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) { bank 163 drivers/mfd/asic3.c if (status & (1 << bank)) { bank 167 drivers/mfd/asic3.c + bank * ASIC3_GPIO_BASE_INCR; bank 186 drivers/mfd/asic3.c (ASIC3_GPIOS_PER_BANK * bank) bank 189 drivers/mfd/asic3.c if (asic->irq_bothedge[bank] & bit) bank 225 drivers/mfd/asic3.c u32 val, bank, index; bank 228 drivers/mfd/asic3.c bank = asic3_irq_to_bank(asic, data->irq); bank 232 drivers/mfd/asic3.c val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); bank 234 drivers/mfd/asic3.c asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); bank 262 drivers/mfd/asic3.c u32 val, bank, index; bank 265 drivers/mfd/asic3.c bank = asic3_irq_to_bank(asic, data->irq); bank 269 drivers/mfd/asic3.c val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); bank 271 drivers/mfd/asic3.c asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); bank 299 drivers/mfd/asic3.c u32 bank, index; bank 303 drivers/mfd/asic3.c bank = asic3_irq_to_bank(asic, data->irq); bank 309 drivers/mfd/asic3.c bank + ASIC3_GPIO_LEVEL_TRIGGER); bank 311 drivers/mfd/asic3.c bank + ASIC3_GPIO_EDGE_TRIGGER); bank 313 drivers/mfd/asic3.c bank + ASIC3_GPIO_TRIGGER_TYPE); bank 343 drivers/mfd/asic3.c asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER, bank 345 drivers/mfd/asic3.c asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER, bank 347 drivers/mfd/asic3.c asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE, bank 356 drivers/mfd/asic3.c u32 bank, index; bank 359 drivers/mfd/asic3.c bank = asic3_irq_to_bank(asic, data->irq); bank 363 drivers/mfd/asic3.c asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on); bank 21 drivers/mfd/ezx-pcap.c u8 bank; bank 258 drivers/mfd/ezx-pcap.c if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1) bank 305 drivers/mfd/ezx-pcap.c int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[], bank 316 drivers/mfd/ezx-pcap.c req->bank = bank; bank 349 drivers/mfd/ezx-pcap.c int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[], bank 356 drivers/mfd/ezx-pcap.c ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb, bank 1110 drivers/mfd/stmpe.c int bank = num - i - 1; bank 1114 drivers/mfd/stmpe.c status &= stmpe->ier[bank]; bank 1121 drivers/mfd/stmpe.c int line = bank * 8 + bit; bank 1915 drivers/mtd/chips/jedec_probe.c int bank = 0; bank 1922 drivers/mtd/chips/jedec_probe.c uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi); bank 1927 drivers/mtd/chips/jedec_probe.c bank++; bank 196 drivers/mtd/devices/spear_smi.c u32 bank; bank 221 drivers/mtd/devices/spear_smi.c static int spear_smi_read_sr(struct spear_smi *dev, u32 bank) bank 234 drivers/mtd/devices/spear_smi.c writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE, bank 264 drivers/mtd/devices/spear_smi.c static int spear_smi_wait_till_ready(struct spear_smi *dev, u32 bank, bank 272 drivers/mtd/devices/spear_smi.c status = spear_smi_read_sr(dev, bank); bank 379 drivers/mtd/devices/spear_smi.c static int spear_smi_write_enable(struct spear_smi *dev, u32 bank) bank 392 drivers/mtd/devices/spear_smi.c writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2); bank 407 drivers/mtd/devices/spear_smi.c if (dev->status & (1 << (bank + WM_SHIFT))) bank 445 drivers/mtd/devices/spear_smi.c u32 bank, u32 command, u32 bytes) bank 450 drivers/mtd/devices/spear_smi.c ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT); bank 454 drivers/mtd/devices/spear_smi.c ret = spear_smi_write_enable(dev, bank); bank 466 drivers/mtd/devices/spear_smi.c writel((bank << BANK_SHIFT) | SEND | TFIE | (bytes << TX_LEN_SHIFT), bank 498 drivers/mtd/devices/spear_smi.c u32 addr, command, bank; bank 504 drivers/mtd/devices/spear_smi.c bank = flash->bank; bank 505 drivers/mtd/devices/spear_smi.c if (bank > dev->num_flashes - 1) { bank 519 drivers/mtd/devices/spear_smi.c ret = spear_smi_erase_sector(dev, bank, command, 4); bank 557 drivers/mtd/devices/spear_smi.c if (flash->bank > dev->num_flashes - 1) { bank 568 drivers/mtd/devices/spear_smi.c ret = spear_smi_wait_till_ready(dev, flash->bank, SMI_MAX_TIME_OUT); bank 615 drivers/mtd/devices/spear_smi.c static inline int spear_smi_cpy_toio(struct spear_smi *dev, u32 bank, bank 622 drivers/mtd/devices/spear_smi.c ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT); bank 627 drivers/mtd/devices/spear_smi.c ret = spear_smi_write_enable(dev, bank); bank 686 drivers/mtd/devices/spear_smi.c if (flash->bank > dev->num_flashes - 1) { bank 699 drivers/mtd/devices/spear_smi.c ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf, len); bank 708 drivers/mtd/devices/spear_smi.c ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf, bank 721 drivers/mtd/devices/spear_smi.c ret = spear_smi_cpy_toio(dev, flash->bank, dest + i, bank 745 drivers/mtd/devices/spear_smi.c static int spear_smi_probe_flash(struct spear_smi *dev, u32 bank) bank 750 drivers/mtd/devices/spear_smi.c ret = spear_smi_wait_till_ready(dev, bank, SMI_PROBE_TIMEOUT); bank 764 drivers/mtd/devices/spear_smi.c val = (bank << BANK_SHIFT) | SEND | (1 << TX_LEN_SHIFT) | bank 845 drivers/mtd/devices/spear_smi.c u32 bank, struct device_node *np) bank 857 drivers/mtd/devices/spear_smi.c if (bank > pdata->num_flashes - 1) bank 860 drivers/mtd/devices/spear_smi.c flash_info = &pdata->board_flash_info[bank]; bank 867 drivers/mtd/devices/spear_smi.c flash->bank = bank; bank 872 drivers/mtd/devices/spear_smi.c flash_index = spear_smi_probe_flash(dev, bank); bank 874 drivers/mtd/devices/spear_smi.c dev_info(&dev->pdev->dev, "smi-nor%d not found\n", bank); bank 883 drivers/mtd/devices/spear_smi.c dev->flash[bank] = flash; bank 109 drivers/mtd/nand/raw/denali.c int bank, u32 irq_status) bank 112 drivers/mtd/nand/raw/denali.c iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); bank 199 drivers/mtd/nand/raw/denali.c denali->active_bank = sel->bank; bank 444 drivers/mtd/nand/raw/denali.c int bank = denali->active_bank; bank 448 drivers/mtd/nand/raw/denali.c ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); bank 449 drivers/mtd/nand/raw/denali.c ecc_cor >>= ECC_COR_INFO__SHIFT(bank); bank 1169 drivers/mtd/nand/raw/denali.c unsigned int bank = dchip->sels[i].bank; bank 1171 drivers/mtd/nand/raw/denali.c if (bank >= denali->nbanks) { bank 1172 drivers/mtd/nand/raw/denali.c dev_err(denali->dev, "unsupported bank %d\n", bank); bank 1177 drivers/mtd/nand/raw/denali.c if (bank == dchip->sels[j].bank) { bank 1180 drivers/mtd/nand/raw/denali.c bank); bank 1187 drivers/mtd/nand/raw/denali.c if (bank == dchip2->sels[j].bank) { bank 1190 drivers/mtd/nand/raw/denali.c bank); bank 18 drivers/mtd/nand/raw/denali.h #define DEVICE_RESET__BANK(bank) BIT(bank) bank 36 drivers/mtd/nand/raw/denali.h #define RB_PIN_ENABLED__BANK(bank) BIT(bank) bank 208 drivers/mtd/nand/raw/denali.h #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) bank 209 drivers/mtd/nand/raw/denali.h #define INTR_EN(bank) (0x420 + (bank) * 0x50) bank 230 drivers/mtd/nand/raw/denali.h #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) bank 231 drivers/mtd/nand/raw/denali.h #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50) bank 232 drivers/mtd/nand/raw/denali.h #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50) bank 254 drivers/mtd/nand/raw/denali.h #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) bank 255 drivers/mtd/nand/raw/denali.h #define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8) bank 308 drivers/mtd/nand/raw/denali.h int bank; bank 78 drivers/mtd/nand/raw/denali_dt.c u32 bank; bank 93 drivers/mtd/nand/raw/denali_dt.c ret = of_property_read_u32_index(chip_np, "reg", i, &bank); bank 97 drivers/mtd/nand/raw/denali_dt.c dchip->sels[i].bank = bank; bank 121 drivers/mtd/nand/raw/denali_dt.c dchip->sels[i].bank = i; bank 108 drivers/mtd/nand/raw/denali_pci.c dchip->sels[i].bank = i; bank 42 drivers/mtd/nand/raw/fsl_elbc_nand.c int bank; /* Chip select bank number */ bank 223 drivers/mtd/nand/raw/fsl_elbc_nand.c in_be32(&lbc->fbcr), priv->bank); bank 227 drivers/mtd/nand/raw/fsl_elbc_nand.c out_be32(&lbc->lsor, priv->bank); bank 689 drivers/mtd/nand/raw/fsl_elbc_nand.c dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); bank 697 drivers/mtd/nand/raw/fsl_elbc_nand.c if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) bank 738 drivers/mtd/nand/raw/fsl_elbc_nand.c if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == bank 812 drivers/mtd/nand/raw/fsl_elbc_nand.c clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); bank 815 drivers/mtd/nand/raw/fsl_elbc_nand.c setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); bank 840 drivers/mtd/nand/raw/fsl_elbc_nand.c elbc_fcm_ctrl->chips[priv->bank] = NULL; bank 856 drivers/mtd/nand/raw/fsl_elbc_nand.c int bank; bank 874 drivers/mtd/nand/raw/fsl_elbc_nand.c for (bank = 0; bank < MAX_BANKS; bank++) bank 875 drivers/mtd/nand/raw/fsl_elbc_nand.c if ((in_be32(&lbc->bank[bank].br) & BR_V) && bank 876 drivers/mtd/nand/raw/fsl_elbc_nand.c (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM && bank 877 drivers/mtd/nand/raw/fsl_elbc_nand.c (in_be32(&lbc->bank[bank].br) & bank 878 drivers/mtd/nand/raw/fsl_elbc_nand.c in_be32(&lbc->bank[bank].or) & BR_BA) bank 882 drivers/mtd/nand/raw/fsl_elbc_nand.c if (bank >= MAX_BANKS) { bank 908 drivers/mtd/nand/raw/fsl_elbc_nand.c elbc_fcm_ctrl->chips[bank] = priv; bank 909 drivers/mtd/nand/raw/fsl_elbc_nand.c priv->bank = bank; bank 944 drivers/mtd/nand/raw/fsl_elbc_nand.c (unsigned long long)res.start, priv->bank); bank 35 drivers/mtd/nand/raw/fsl_ifc_nand.c int bank; /* Chip select bank number */ bank 183 drivers/mtd/nand/raw/fsl_ifc_nand.c ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT, bank 759 drivers/mtd/nand/raw/fsl_ifc_nand.c uint32_t cs = priv->bank; bank 846 drivers/mtd/nand/raw/fsl_ifc_nand.c if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)) bank 869 drivers/mtd/nand/raw/fsl_ifc_nand.c if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr) bank 883 drivers/mtd/nand/raw/fsl_ifc_nand.c csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor); bank 955 drivers/mtd/nand/raw/fsl_ifc_nand.c ifc_nand_ctrl->chips[priv->bank] = NULL; bank 960 drivers/mtd/nand/raw/fsl_ifc_nand.c static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank, bank 963 drivers/mtd/nand/raw/fsl_ifc_nand.c u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr); bank 983 drivers/mtd/nand/raw/fsl_ifc_nand.c int bank; bank 999 drivers/mtd/nand/raw/fsl_ifc_nand.c for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) { bank 1000 drivers/mtd/nand/raw/fsl_ifc_nand.c if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start)) bank 1004 drivers/mtd/nand/raw/fsl_ifc_nand.c if (bank >= fsl_ifc_ctrl_dev->banks) { bank 1033 drivers/mtd/nand/raw/fsl_ifc_nand.c ifc_nand_ctrl->chips[bank] = priv; bank 1034 drivers/mtd/nand/raw/fsl_ifc_nand.c priv->bank = bank; bank 1081 drivers/mtd/nand/raw/fsl_ifc_nand.c (unsigned long long)res.start, priv->bank); bank 56 drivers/mtd/nand/raw/fsmc_nand.c #define FSMC_NOR_REG(base, bank, reg) ((base) + \ bank 57 drivers/mtd/nand/raw/fsmc_nand.c (FSMC_NOR_BANK_SZ * (bank)) + \ bank 139 drivers/mtd/nand/raw/fsmc_nand.c unsigned int bank; bank 863 drivers/mtd/nand/raw/fsmc_nand.c host->bank = 0; bank 869 drivers/mtd/nand/raw/fsmc_nand.c host->bank = val; bank 1016 drivers/mtd/nand/raw/fsmc_nand.c (host->bank * FSMC_NAND_BANK_SZ); bank 41 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c unsigned int bank; bank 154 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c jz4780_nemc_assert(nfc->dev, cs->bank, false); bank 172 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE); bank 324 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c cs->bank = be32_to_cpu(*reg); bank 326 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND); bank 357 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c cs->bank); bank 377 drivers/net/can/flexcan.c bool bank; bank 384 drivers/net/can/flexcan.c bank = mb_index >= bank_size; bank 385 drivers/net/can/flexcan.c if (bank) bank 389 drivers/net/can/flexcan.c (&priv->regs->mb[bank][priv->mb_size * mb_index]); bank 5819 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 bank; bank 5834 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; bank 5835 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { bank 5837 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bank, bank 5846 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bank, bank 5903 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 bank, i = 0; bank 5906 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; bank 5907 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { bank 5909 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bank, bank 5914 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; bank 5915 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { bank 5917 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bank, bank 99 drivers/net/ethernet/intel/e1000e/ich8lan.c static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); bank 3117 drivers/net/ethernet/intel/e1000e/ich8lan.c static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) bank 3134 drivers/net/ethernet/intel/e1000e/ich8lan.c *bank = 0; bank 3144 drivers/net/ethernet/intel/e1000e/ich8lan.c *bank = 0; bank 3157 drivers/net/ethernet/intel/e1000e/ich8lan.c *bank = 1; bank 3169 drivers/net/ethernet/intel/e1000e/ich8lan.c *bank = 1; bank 3171 drivers/net/ethernet/intel/e1000e/ich8lan.c *bank = 0; bank 3179 drivers/net/ethernet/intel/e1000e/ich8lan.c *bank = 0; bank 3188 drivers/net/ethernet/intel/e1000e/ich8lan.c *bank = 0; bank 3200 drivers/net/ethernet/intel/e1000e/ich8lan.c *bank = 1; bank 3225 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 bank = 0; bank 3239 drivers/net/ethernet/intel/e1000e/ich8lan.c ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); bank 3242 drivers/net/ethernet/intel/e1000e/ich8lan.c bank = 0; bank 3245 drivers/net/ethernet/intel/e1000e/ich8lan.c act_offset = (bank) ? nvm->flash_bank_size : 0; bank 3318 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 bank = 0; bank 3330 drivers/net/ethernet/intel/e1000e/ich8lan.c ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); bank 3333 drivers/net/ethernet/intel/e1000e/ich8lan.c bank = 0; bank 3336 drivers/net/ethernet/intel/e1000e/ich8lan.c act_offset = (bank) ? nvm->flash_bank_size : 0; bank 3745 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 i, act_offset, new_bank_offset, old_bank_offset, bank; bank 3762 drivers/net/ethernet/intel/e1000e/ich8lan.c ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); bank 3765 drivers/net/ethernet/intel/e1000e/ich8lan.c bank = 0; bank 3768 drivers/net/ethernet/intel/e1000e/ich8lan.c if (bank == 0) { bank 3913 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 i, act_offset, new_bank_offset, old_bank_offset, bank; bank 3930 drivers/net/ethernet/intel/e1000e/ich8lan.c ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); bank 3933 drivers/net/ethernet/intel/e1000e/ich8lan.c bank = 0; bank 3936 drivers/net/ethernet/intel/e1000e/ich8lan.c if (bank == 0) { bank 4405 drivers/net/ethernet/intel/e1000e/ich8lan.c static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) bank 4455 drivers/net/ethernet/intel/e1000e/ich8lan.c flash_linear_addr += (bank) ? flash_bank_size : 0; bank 5614 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 bank = 0; bank 5648 drivers/net/ethernet/intel/e1000e/ich8lan.c if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { bank 89 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int bank = index / mcam->banksize; bank 93 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c return bank ? 2 : 0; bank 95 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c return bank; bank 101 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int bank = npc_get_bank(mcam, index); bank 105 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank)); bank 112 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int bank = npc_get_bank(mcam, index); bank 113 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int actbank = bank; bank 116 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c for (; bank < (actbank + mcam->banks_per_entry); bank++) { bank 118 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_CFG(index, bank), bank 206 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int bank = npc_get_bank(mcam, index); bank 210 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c actbank = bank; /* Save bank id, to set action later on */ bank 220 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) { bank 223 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), bank 226 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), bank 232 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1); bank 234 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0); bank 238 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1); bank 240 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0); bank 264 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int bank, i; bank 270 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c for (bank = 0; bank < mcam->banks_per_entry; bank++) { bank 271 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0); bank 272 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0); bank 301 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int bank = npc_get_bank(mcam, index); bank 305 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); bank 518 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int blkaddr, index, bank; bank 538 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c bank = npc_get_bank(mcam, index); bank 542 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); bank 553 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action); bank 562 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c bank = npc_get_bank(mcam, index); bank 566 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_ACTION(index, bank), bank 578 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int index, bank, blkaddr; bank 600 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c bank = npc_get_bank(mcam, index); bank 602 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_ACTION(index & (mcam->banksize - 1), bank)); bank 1105 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int blkaddr, entry, bank, err; bank 1116 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c for (bank = 0; bank < ((cfg >> 44) & 0xF); bank++) { bank 1119 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0); bank 1237 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c u16 bank = npc_get_bank(mcam, entry); bank 1244 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), bank 1253 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c u16 bank = npc_get_bank(mcam, entry); bank 1260 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00); bank 3162 drivers/net/ethernet/mellanox/mlxsw/reg.h u8 state, u8 bank, u32 bf_index) bank 3169 drivers/net/ethernet/mellanox/mlxsw/reg.h mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); bank 171 drivers/net/ethernet/micrel/ks8842.c static inline void ks8842_select_bank(struct ks8842_adapter *adapter, u16 bank) bank 173 drivers/net/ethernet/micrel/ks8842.c iowrite16(bank, adapter->hw_addr + REG_SELECT_BANK); bank 176 drivers/net/ethernet/micrel/ks8842.c static inline void ks8842_write8(struct ks8842_adapter *adapter, u16 bank, bank 179 drivers/net/ethernet/micrel/ks8842.c ks8842_select_bank(adapter, bank); bank 183 drivers/net/ethernet/micrel/ks8842.c static inline void ks8842_write16(struct ks8842_adapter *adapter, u16 bank, bank 186 drivers/net/ethernet/micrel/ks8842.c ks8842_select_bank(adapter, bank); bank 190 drivers/net/ethernet/micrel/ks8842.c static inline void ks8842_enable_bits(struct ks8842_adapter *adapter, u16 bank, bank 194 drivers/net/ethernet/micrel/ks8842.c ks8842_select_bank(adapter, bank); bank 200 drivers/net/ethernet/micrel/ks8842.c static inline void ks8842_clear_bits(struct ks8842_adapter *adapter, u16 bank, bank 204 drivers/net/ethernet/micrel/ks8842.c ks8842_select_bank(adapter, bank); bank 210 drivers/net/ethernet/micrel/ks8842.c static inline void ks8842_write32(struct ks8842_adapter *adapter, u16 bank, bank 213 drivers/net/ethernet/micrel/ks8842.c ks8842_select_bank(adapter, bank); bank 217 drivers/net/ethernet/micrel/ks8842.c static inline u8 ks8842_read8(struct ks8842_adapter *adapter, u16 bank, bank 220 drivers/net/ethernet/micrel/ks8842.c ks8842_select_bank(adapter, bank); bank 224 drivers/net/ethernet/micrel/ks8842.c static inline u16 ks8842_read16(struct ks8842_adapter *adapter, u16 bank, bank 227 drivers/net/ethernet/micrel/ks8842.c ks8842_select_bank(adapter, bank); bank 231 drivers/net/ethernet/micrel/ks8842.c static inline u32 ks8842_read32(struct ks8842_adapter *adapter, u16 bank, bank 234 drivers/net/ethernet/micrel/ks8842.c ks8842_select_bank(adapter, bank); bank 64 drivers/net/ethernet/microchip/enc28j60.c u8 bank; /* current register bank selected */ bank 206 drivers/net/ethernet/microchip/enc28j60.c if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) { bank 214 drivers/net/ethernet/microchip/enc28j60.c if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) { bank 222 drivers/net/ethernet/microchip/enc28j60.c priv->bank = b; bank 663 drivers/net/ethernet/microchip/enc28j60.c priv->bank = 0; bank 26 drivers/net/ethernet/microchip/encx24j600-regmap.c int bank) bank 29 drivers/net/ethernet/microchip/encx24j600-regmap.c int bank_opcode = BANK_SELECT(bank); bank 33 drivers/net/ethernet/microchip/encx24j600-regmap.c ctx->bank = bank; bank 70 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); bank 78 drivers/net/ethernet/microchip/encx24j600-regmap.c if ((banked_reg < 0x16) && (ctx->bank != bank)) bank 79 drivers/net/ethernet/microchip/encx24j600-regmap.c ret = encx24j600_switch_bank(ctx, bank); bank 121 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); bank 132 drivers/net/ethernet/microchip/encx24j600-regmap.c if ((banked_reg < 0x16) && (ctx->bank != bank)) bank 133 drivers/net/ethernet/microchip/encx24j600-regmap.c ret = encx24j600_switch_bank(ctx, bank); bank 15 drivers/net/ethernet/microchip/encx24j600_hw.h int bank; bank 22 drivers/net/ethernet/microchip/encx24j600_hw.h #define BANK_SELECT(bank) (0xC0 | ((bank & (BANK_MASK >> BANK_SHIFT)) << 1)) bank 848 drivers/net/ethernet/smsc/smc9194.c unsigned int bank; bank 868 drivers/net/ethernet/smsc/smc9194.c bank = inw( ioaddr + BANK_SELECT ); bank 869 drivers/net/ethernet/smsc/smc9194.c if ( (bank & 0xFF00) != 0x3300 ) { bank 876 drivers/net/ethernet/smsc/smc9194.c bank = inw( ioaddr + BANK_SELECT ); bank 877 drivers/net/ethernet/smsc/smc9194.c if ( (bank & 0xFF00 ) != 0x3300 ) { bank 846 drivers/net/ethernet/smsc/smc91x.h #define SMC_REG(lp, reg, bank) \ bank 849 drivers/net/ethernet/smsc/smc91x.h if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ bank 857 drivers/net/ethernet/smsc/smc91x.h #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) bank 738 drivers/net/fddi/skfp/h/skfbi.h #define GET_PAGE(bank) outpd(ADDR(B2_FAR),bank) bank 73 drivers/net/phy/meson-gxl.c unsigned int bank, unsigned int reg) bank 82 drivers/net/phy/meson-gxl.c FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) | bank 96 drivers/net/phy/meson-gxl.c unsigned int bank, unsigned int reg, bank 110 drivers/net/phy/meson-gxl.c FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) | bank 45 drivers/net/phy/microchip_t1.c u8 bank; bank 51 drivers/net/phy/microchip_t1.c static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank, bank 57 drivers/net/phy/microchip_t1.c if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX) bank 60 drivers/net/phy/microchip_t1.c if (bank == PHYACC_ATTR_BANK_SMI) { bank 77 drivers/net/phy/microchip_t1.c ereg |= (bank << 8) | offset; bank 90 drivers/net/phy/microchip_t1.c u8 bank, u8 offset, u16 val, u16 mask) bank 94 drivers/net/phy/microchip_t1.c if (bank > PHYACC_ATTR_BANK_MAX) bank 97 drivers/net/phy/microchip_t1.c rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val); bank 102 drivers/net/phy/microchip_t1.c rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new); bank 168 drivers/net/phy/microchip_t1.c rc = access_ereg_modify_changed(phydev, init[i].bank, bank 173 drivers/net/phy/microchip_t1.c rc = access_ereg(phydev, init[i].mode, init[i].bank, bank 197 drivers/net/wireless/ath/ath5k/phy.c u8 offset, bank, num_bits, col, position; bank 220 drivers/net/wireless/ath/ath5k/phy.c bank = rfreg->bank; bank 229 drivers/net/wireless/ath/ath5k/phy.c offset = ah->ah_offset[bank]; bank 821 drivers/net/wireless/ath/ath5k/phy.c int i, obdb = -1, bank = -1; bank 907 drivers/net/wireless/ath/ath5k/phy.c if (bank != ini_rfb[i].rfb_bank) { bank 908 drivers/net/wireless/ath/ath5k/phy.c bank = ini_rfb[i].rfb_bank; bank 909 drivers/net/wireless/ath/ath5k/phy.c ah->ah_offset[bank] = i; bank 94 drivers/net/wireless/ath/ath5k/rfbuffer.h u8 bank; bank 24 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u8 bank, reg; bank 29 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c bank = MT_RF_BANK(offset); bank 32 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8)) bank 44 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | bank 54 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c bank, reg, ret); bank 63 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u8 bank, reg; bank 68 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c bank = MT_RF_BANK(offset); bank 71 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8)) bank 80 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | bank 89 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) bank 97 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c bank, reg, ret); bank 21 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF(bank, reg) ((bank) << 16 | (reg)) bank 10 drivers/net/wireless/mediatek/mt7601u/initvals_phy.h #define RF_REG_PAIR(bank, reg, value) \ bank 11 drivers/net/wireless/mediatek/mt7601u/initvals_phy.h { MT_MCU_MEMMAP_RF | (bank) << 16 | (reg), value } bank 19 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_rf_wr(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 value) bank 38 drivers/net/wireless/mediatek/mt7601u/phy.c FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | bank 42 drivers/net/wireless/mediatek/mt7601u/phy.c trace_rf_write(dev, bank, offset, value); bank 48 drivers/net/wireless/mediatek/mt7601u/phy.c bank, offset, ret); bank 54 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_rf_rr(struct mt7601u_dev *dev, u8 bank, u8 offset) bank 71 drivers/net/wireless/mediatek/mt7601u/phy.c FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | bank 80 drivers/net/wireless/mediatek/mt7601u/phy.c FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) { bank 82 drivers/net/wireless/mediatek/mt7601u/phy.c trace_rf_read(dev, bank, offset, ret); bank 89 drivers/net/wireless/mediatek/mt7601u/phy.c bank, offset, ret); bank 95 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val) bank 99 drivers/net/wireless/mediatek/mt7601u/phy.c ret = mt7601u_rf_rr(dev, bank, offset); bank 103 drivers/net/wireless/mediatek/mt7601u/phy.c ret = mt7601u_rf_wr(dev, bank, offset, val); bank 111 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val) bank 113 drivers/net/wireless/mediatek/mt7601u/phy.c return mt7601u_rf_rmw(dev, bank, offset, 0, val); bank 117 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask) bank 119 drivers/net/wireless/mediatek/mt7601u/phy.c return mt7601u_rf_rmw(dev, bank, offset, mask, 0); bank 142 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), bank 143 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, bank, reg, val), bank 146 drivers/net/wireless/mediatek/mt7601u/trace.h __field(u8, bank) bank 153 drivers/net/wireless/mediatek/mt7601u/trace.h __entry->bank = bank; bank 157 drivers/net/wireless/mediatek/mt7601u/trace.h DEV_PR_ARG, __entry->bank, __entry->reg, __entry->val bank 162 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), bank 163 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, bank, reg, val) bank 167 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), bank 168 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, bank, reg, val) bank 181 drivers/net/wireless/ralink/rt2x00/rt2800lib.c static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, bank 184 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); bank 255 drivers/net/wireless/ralink/rt2x00/rt2800lib.c static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, bank 258 drivers/net/wireless/ralink/rt2x00/rt2800lib.c return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); bank 45 drivers/nvmem/imx-iim.c int bank = i >> 5; bank 48 drivers/nvmem/imx-iim.c *buf8++ = readl(iim->base + IIM_BANK_BASE(bank) + reg * 4); bank 303 drivers/perf/xgene_pmu.c XGENE_PMU_EVENT_ATTR(bank-fifo-full, 0x0b), bank 306 drivers/perf/xgene_pmu.c XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue, 0x0e), bank 307 drivers/perf/xgene_pmu.c XGENE_PMU_EVENT_ATTR(bank-fifo-issue, 0x0f), bank 403 drivers/perf/xgene_pmu.c XGENE_PMU_EVENT_ATTR(tq-bank-conflict-issue-stall, 0x0b), bank 202 drivers/phy/broadcom/phy-brcm-sata.c static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank, bank 207 drivers/phy/broadcom/phy-brcm-sata.c writel(bank, pcb_base + SATA_PCB_BANK_OFFSET); bank 213 drivers/phy/broadcom/phy-brcm-sata.c static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs) bank 215 drivers/phy/broadcom/phy-brcm-sata.c writel(bank, pcb_base + SATA_PCB_BANK_OFFSET); bank 699 drivers/phy/mediatek/phy-mtk-tphy.c struct u3phy_banks *bank = &instance->u3_banks; bank 702 drivers/phy/mediatek/phy-mtk-tphy.c tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); bank 704 drivers/phy/mediatek/phy-mtk-tphy.c writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); bank 706 drivers/phy/mediatek/phy-mtk-tphy.c tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); bank 708 drivers/phy/mediatek/phy-mtk-tphy.c writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); bank 715 drivers/phy/mediatek/phy-mtk-tphy.c struct u3phy_banks *bank = &instance->u3_banks; bank 718 drivers/phy/mediatek/phy-mtk-tphy.c tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); bank 720 drivers/phy/mediatek/phy-mtk-tphy.c writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); bank 722 drivers/phy/mediatek/phy-mtk-tphy.c tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); bank 724 drivers/phy/mediatek/phy-mtk-tphy.c writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); bank 276 drivers/phy/st/phy-miphy28lp.c int bank; bank 293 drivers/phy/st/phy-miphy28lp.c .bank = 0x00, bank 306 drivers/phy/st/phy-miphy28lp.c .bank = 0x01, bank 319 drivers/phy/st/phy-miphy28lp.c .bank = 0x02, bank 335 drivers/phy/st/phy-miphy28lp.c .bank = 0x00, bank 349 drivers/phy/st/phy-miphy28lp.c .bank = 0x01, bank 438 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->bank, base + MIPHY_CONF); bank 465 drivers/phy/st/phy-miphy28lp.c writeb_relaxed(gen->bank, base + MIPHY_CONF); bank 359 drivers/pinctrl/bcm/pinctrl-bcm2835.c unsigned int bank, u32 mask) bank 365 drivers/pinctrl/bcm/pinctrl-bcm2835.c events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); bank 367 drivers/pinctrl/bcm/pinctrl-bcm2835.c events &= pc->enabled_irq_map[bank]; bank 369 drivers/pinctrl/bcm/pinctrl-bcm2835.c gpio = (32 * bank) + offset; bank 459 drivers/pinctrl/bcm/pinctrl-bcm2835.c unsigned bank = GPIO_REG_OFFSET(gpio); bank 462 drivers/pinctrl/bcm/pinctrl-bcm2835.c raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); bank 463 drivers/pinctrl/bcm/pinctrl-bcm2835.c set_bit(offset, &pc->enabled_irq_map[bank]); bank 465 drivers/pinctrl/bcm/pinctrl-bcm2835.c raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); bank 474 drivers/pinctrl/bcm/pinctrl-bcm2835.c unsigned bank = GPIO_REG_OFFSET(gpio); bank 477 drivers/pinctrl/bcm/pinctrl-bcm2835.c raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); bank 481 drivers/pinctrl/bcm/pinctrl-bcm2835.c clear_bit(offset, &pc->enabled_irq_map[bank]); bank 482 drivers/pinctrl/bcm/pinctrl-bcm2835.c raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); bank 581 drivers/pinctrl/bcm/pinctrl-bcm2835.c unsigned bank = GPIO_REG_OFFSET(gpio); bank 585 drivers/pinctrl/bcm/pinctrl-bcm2835.c raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); bank 587 drivers/pinctrl/bcm/pinctrl-bcm2835.c if (test_bit(offset, &pc->enabled_irq_map[bank])) bank 597 drivers/pinctrl/bcm/pinctrl-bcm2835.c raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); bank 206 drivers/pinctrl/freescale/pinctrl-mxs.c u8 bank, shift; bank 211 drivers/pinctrl/freescale/pinctrl-mxs.c bank = PINID_TO_BANK(g->pins[i]); bank 214 drivers/pinctrl/freescale/pinctrl-mxs.c reg += bank * 0x20 + pin / 16 * 0x10; bank 260 drivers/pinctrl/freescale/pinctrl-mxs.c u8 ma, vol, pull, bank, shift; bank 274 drivers/pinctrl/freescale/pinctrl-mxs.c bank = PINID_TO_BANK(g->pins[i]); bank 279 drivers/pinctrl/freescale/pinctrl-mxs.c reg += bank * 0x40 + pin / 8 * 0x10; bank 299 drivers/pinctrl/freescale/pinctrl-mxs.c reg += bank * 0x10; bank 17 drivers/pinctrl/freescale/pinctrl-mxs.h #define PINID(bank, pin) ((bank) * 32 + (pin)) bank 31 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c struct meson_pmx_bank **bank) bank 39 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c *bank = &pmx->pmx_banks[i]; bank 46 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c static int meson_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank, bank 52 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c shift = pin - bank->first; bank 54 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c *reg = bank->reg + (bank->offset + (shift << 2)) / 32; bank 55 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c *offset = (bank->offset + (shift << 2)) % 32; bank 66 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c struct meson_pmx_bank *bank; bank 68 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c ret = meson_axg_pmx_get_bank(pc, pin, &bank); bank 72 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c meson_pmx_calc_reg_and_offset(bank, pin, ®, &offset); bank 69 drivers/pinctrl/meson/pinctrl-meson.c struct meson_bank **bank) bank 76 drivers/pinctrl/meson/pinctrl-meson.c *bank = &pc->data->banks[i]; bank 93 drivers/pinctrl/meson/pinctrl-meson.c static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, bank 97 drivers/pinctrl/meson/pinctrl-meson.c struct meson_reg_desc *desc = &bank->regs[reg_type]; bank 100 drivers/pinctrl/meson/pinctrl-meson.c *bit = desc->bit + pin - bank->first; bank 176 drivers/pinctrl/meson/pinctrl-meson.c struct meson_bank *bank; bank 180 drivers/pinctrl/meson/pinctrl-meson.c ret = meson_get_bank(pc, pin, &bank); bank 184 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); bank 193 drivers/pinctrl/meson/pinctrl-meson.c struct meson_bank *bank; bank 197 drivers/pinctrl/meson/pinctrl-meson.c ret = meson_get_bank(pc, pin, &bank); bank 201 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); bank 256 drivers/pinctrl/meson/pinctrl-meson.c struct meson_bank *bank; bank 260 drivers/pinctrl/meson/pinctrl-meson.c ret = meson_get_bank(pc, pin, &bank); bank 264 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); bank 275 drivers/pinctrl/meson/pinctrl-meson.c struct meson_bank *bank; bank 279 drivers/pinctrl/meson/pinctrl-meson.c ret = meson_get_bank(pc, pin, &bank); bank 283 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); bank 291 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); bank 303 drivers/pinctrl/meson/pinctrl-meson.c struct meson_bank *bank; bank 312 drivers/pinctrl/meson/pinctrl-meson.c ret = meson_get_bank(pc, pin, &bank); bank 316 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); bank 395 drivers/pinctrl/meson/pinctrl-meson.c struct meson_bank *bank; bank 399 drivers/pinctrl/meson/pinctrl-meson.c ret = meson_get_bank(pc, pin, &bank); bank 403 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); bank 412 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); bank 431 drivers/pinctrl/meson/pinctrl-meson.c struct meson_bank *bank; bank 439 drivers/pinctrl/meson/pinctrl-meson.c ret = meson_get_bank(pc, pin, &bank); bank 443 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); bank 573 drivers/pinctrl/meson/pinctrl-meson.c struct meson_bank *bank; bank 576 drivers/pinctrl/meson/pinctrl-meson.c ret = meson_get_bank(pc, gpio, &bank); bank 580 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); bank 250 drivers/pinctrl/nomadik/pinctrl-nomadik.c unsigned int bank; bank 253 drivers/pinctrl/nomadik/pinctrl-nomadik.c u32 (*get_latent_status)(unsigned int bank); bank 839 drivers/pinctrl/nomadik/pinctrl-nomadik.c u32 status = nmk_chip->get_latent_status(nmk_chip->bank); bank 1073 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_chip->bank = id; bank 1096 drivers/pinctrl/nomadik/pinctrl-nomadik.c BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); bank 1122 drivers/pinctrl/nomadik/pinctrl-nomadik.c dev->id = nmk_chip->bank; bank 132 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = gpiochip_get_data(chip); bank 135 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c bank->gc.base / bank->gc.ngpio, bank 136 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c bank->gc.base, bank 137 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c bank->gc.base + bank->gc.ngpio); bank 139 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_DIN), bank 140 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_DOUT), bank 141 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_IEM), bank 142 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OE)); bank 144 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_PU), bank 145 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_PD), bank 146 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_DBNC), bank 147 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_POL)); bank 149 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_EVTYP), bank 150 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_EVBE), bank 151 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_EVEN), bank 152 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_EVST)); bank 154 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OTYP), bank 155 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OSRC), bank 156 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_ODSC)); bank 158 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OBL0), bank 159 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OBL1), bank 160 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OBL2), bank 161 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_OBL3)); bank 163 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_SPLCK), bank 164 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ioread32(bank->base + NPCM7XX_GP_N_MPLCK)); bank 169 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = gpiochip_get_data(chip); bank 176 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c return bank->direction_input(chip, offset); bank 183 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = gpiochip_get_data(chip); bank 193 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c return bank->direction_output(chip, offset, value); bank 198 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = gpiochip_get_data(chip); bank 206 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c return bank->request(chip, offset); bank 219 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank; bank 223 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c bank = gpiochip_get_data(gc); bank 227 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); bank 228 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); bank 240 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = bank 249 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); bank 250 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); bank 254 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); bank 255 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); bank 259 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); bank 263 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); bank 267 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); bank 275 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); bank 279 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); bank 288 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = bank 293 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); bank 299 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = bank 305 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); bank 311 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = bank 317 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); bank 1441 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c static int npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank, bank 1445 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int gpio = (pin % bank->gc.ngpio); bank 1449 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c return ioread32(bank->base + NPCM7XX_GP_N_OSRC) bank 1461 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c static int npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank, bank 1465 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int gpio = BIT(pin % bank->gc.ngpio); bank 1470 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, bank 1474 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, bank 1505 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = bank 1507 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int gpio = (pin % bank->gc.ngpio); bank 1515 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c val = ioread32(bank->base + NPCM7XX_GP_N_ODSC) bank 1518 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c dev_dbg(bank->gc.parent, bank 1531 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = bank 1533 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int gpio = BIT(pin % bank->gc.ngpio); bank 1539 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c dev_dbg(bank->gc.parent, bank 1541 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); bank 1544 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c dev_dbg(bank->gc.parent, bank 1546 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); bank 1690 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = bank 1692 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int gpio = BIT(offset % bank->gc.ngpio); bank 1694 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset, bank 1697 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); bank 1699 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); bank 1720 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = bank 1722 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int gpio = (pin % bank->gc.ngpio); bank 1731 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask; bank 1732 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask; bank 1742 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask; bank 1743 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask; bank 1750 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask); bank 1753 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask; bank 1756 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask; bank 1764 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin); bank 1783 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c struct npcm7xx_gpio *bank = bank 1785 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int gpio = BIT(pin % bank->gc.ngpio); bank 1787 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin); bank 1790 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); bank 1791 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); bank 1794 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); bank 1795 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); bank 1798 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); bank 1799 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); bank 1802 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); bank 1803 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c bank->direction_input(&bank->gc, pin % bank->gc.ngpio); bank 1806 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); bank 1807 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); bank 1810 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); bank 1813 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); bank 1816 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio); bank 1819 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); bank 198 drivers/pinctrl/pinctrl-amd.c unsigned int bank, i, pin_num; bank 215 drivers/pinctrl/pinctrl-amd.c for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { bank 216 drivers/pinctrl/pinctrl-amd.c seq_printf(s, "GPIO bank%d\t", bank); bank 218 drivers/pinctrl/pinctrl-amd.c switch (bank) { bank 87 drivers/pinctrl/pinctrl-at91-pio4.c unsigned bank; bank 144 drivers/pinctrl/pinctrl-at91-pio4.c unsigned int bank, unsigned int reg) bank 147 drivers/pinctrl/pinctrl-at91-pio4.c + ATMEL_PIO_BANK_OFFSET * bank + reg); bank 151 drivers/pinctrl/pinctrl-at91-pio4.c unsigned int bank, unsigned int reg, bank 155 drivers/pinctrl/pinctrl-at91-pio4.c + ATMEL_PIO_BANK_OFFSET * bank + reg); bank 172 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, bank 174 drivers/pinctrl/pinctrl-at91-pio4.c reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); bank 203 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); bank 213 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, bank 222 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, bank 231 drivers/pinctrl/pinctrl-at91-pio4.c int bank = ATMEL_PIO_BANK(d->hwirq); bank 235 drivers/pinctrl/pinctrl-at91-pio4.c irq_set_irq_wake(atmel_pioctrl->irqs[bank], on); bank 238 drivers/pinctrl/pinctrl-at91-pio4.c atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); bank 240 drivers/pinctrl/pinctrl-at91-pio4.c atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); bank 270 drivers/pinctrl/pinctrl-at91-pio4.c int n, bank = -1; bank 275 drivers/pinctrl/pinctrl-at91-pio4.c bank = n; bank 280 drivers/pinctrl/pinctrl-at91-pio4.c if (bank < 0) { bank 289 drivers/pinctrl/pinctrl-at91-pio4.c isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, bank 291 drivers/pinctrl/pinctrl-at91-pio4.c isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, bank 299 drivers/pinctrl/pinctrl-at91-pio4.c bank * ATMEL_PIO_NPINS_PER_BANK + n)); bank 311 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, bank 313 drivers/pinctrl/pinctrl-at91-pio4.c reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); bank 315 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); bank 326 drivers/pinctrl/pinctrl-at91-pio4.c reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); bank 338 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, bank 342 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, bank 344 drivers/pinctrl/pinctrl-at91-pio4.c reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); bank 346 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); bank 356 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, bank 375 drivers/pinctrl/pinctrl-at91-pio4.c unsigned bank = atmel_pioctrl->pins[pin_id]->bank; bank 378 drivers/pinctrl/pinctrl-at91-pio4.c + bank * ATMEL_PIO_BANK_OFFSET; bank 391 drivers/pinctrl/pinctrl-at91-pio4.c unsigned bank = atmel_pioctrl->pins[pin_id]->bank; bank 394 drivers/pinctrl/pinctrl-at91-pio4.c + bank * ATMEL_PIO_BANK_OFFSET; bank 712 drivers/pinctrl/pinctrl-at91-pio4.c unsigned bank, pin, pin_id = grp->pin; bank 768 drivers/pinctrl/pinctrl-at91-pio4.c bank = ATMEL_PIO_BANK(pin_id); bank 774 drivers/pinctrl/pinctrl-at91-pio4.c bank * ATMEL_PIO_BANK_OFFSET + bank 778 drivers/pinctrl/pinctrl-at91-pio4.c bank * ATMEL_PIO_BANK_OFFSET + bank 1000 drivers/pinctrl/pinctrl-at91-pio4.c unsigned bank = ATMEL_PIO_BANK(i); bank 1009 drivers/pinctrl/pinctrl-at91-pio4.c atmel_pioctrl->pins[i]->bank = bank; bank 1015 drivers/pinctrl/pinctrl-at91-pio4.c bank + 'A', line); bank 1020 drivers/pinctrl/pinctrl-at91-pio4.c dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); bank 122 drivers/pinctrl/pinctrl-at91.c uint32_t bank; bank 338 drivers/pinctrl/pinctrl-at91.c unsigned int bank) bank 340 drivers/pinctrl/pinctrl-at91.c if (!gpio_chips[bank]) bank 343 drivers/pinctrl/pinctrl-at91.c return gpio_chips[bank]->regbase; bank 758 drivers/pinctrl/pinctrl-at91.c pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); bank 761 drivers/pinctrl/pinctrl-at91.c pin->bank + 'A', pin->pin, pin->conf); bank 771 drivers/pinctrl/pinctrl-at91.c if (pin->bank >= gpio_banks) { bank 773 drivers/pinctrl/pinctrl-at91.c name, index, pin->bank, gpio_banks); bank 777 drivers/pinctrl/pinctrl-at91.c if (!gpio_chips[pin->bank]) { bank 779 drivers/pinctrl/pinctrl-at91.c name, index, pin->bank); bank 800 drivers/pinctrl/pinctrl-at91.c if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { bank 802 drivers/pinctrl/pinctrl-at91.c name, index, mux, pin->bank + 'A', pin->pin); bank 846 drivers/pinctrl/pinctrl-at91.c pio = pin_to_controller(info, pin->bank); bank 1209 drivers/pinctrl/pinctrl-at91.c pin->bank = be32_to_cpu(*list++); bank 1211 drivers/pinctrl/pinctrl-at91.c grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; bank 1621 drivers/pinctrl/pinctrl-at91.c unsigned bank = at91_gpio->pioc_idx; bank 1624 drivers/pinctrl/pinctrl-at91.c if (unlikely(bank >= MAX_GPIO_BANKS)) bank 1628 drivers/pinctrl/pinctrl-at91.c wakeups[bank] |= mask; bank 1630 drivers/pinctrl/pinctrl-at91.c wakeups[bank] &= ~mask; bank 93 drivers/pinctrl/pinctrl-falcon.c static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len) bank 95 drivers/pinctrl/pinctrl-falcon.c int base = bank * PINS; bank 102 drivers/pinctrl/pinctrl-falcon.c pad_count[bank] = len; bank 435 drivers/pinctrl/pinctrl-falcon.c const __be32 *bank = of_get_property(np, "lantiq,bank", NULL); bank 447 drivers/pinctrl/pinctrl-falcon.c if (!bank || *bank >= PORTS) bank 451 drivers/pinctrl/pinctrl-falcon.c falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL); bank 452 drivers/pinctrl/pinctrl-falcon.c if (IS_ERR(falcon_info.clk[*bank])) { bank 455 drivers/pinctrl/pinctrl-falcon.c return PTR_ERR(falcon_info.clk[*bank]); bank 457 drivers/pinctrl/pinctrl-falcon.c falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev, bank 459 drivers/pinctrl/pinctrl-falcon.c if (IS_ERR(falcon_info.membase[*bank])) { bank 461 drivers/pinctrl/pinctrl-falcon.c return PTR_ERR(falcon_info.membase[*bank]); bank 464 drivers/pinctrl/pinctrl-falcon.c avail = pad_r32(falcon_info.membase[*bank], bank 467 drivers/pinctrl/pinctrl-falcon.c lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins); bank 469 drivers/pinctrl/pinctrl-falcon.c clk_enable(falcon_info.clk[*bank]); bank 1943 drivers/pinctrl/pinctrl-ingenic.c unsigned int bank; bank 1946 drivers/pinctrl/pinctrl-ingenic.c err = of_property_read_u32(node, "reg", &bank); bank 1957 drivers/pinctrl/pinctrl-ingenic.c jzgc->reg_base = bank * 0x100; bank 1959 drivers/pinctrl/pinctrl-ingenic.c jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); bank 1967 drivers/pinctrl/pinctrl-ingenic.c jzgc->gc.base = bank * 32; bank 30 drivers/pinctrl/pinctrl-oxnas.c #define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK) bank 71 drivers/pinctrl/pinctrl-oxnas.c unsigned int bank; bank 275 drivers/pinctrl/pinctrl-oxnas.c .bank = _pin / PINS_PER_BANK, \ bank 601 drivers/pinctrl/pinctrl-oxnas.c fname, pg->bank, pg->pin, bank 605 drivers/pinctrl/pinctrl-oxnas.c (pg->bank ? bank 612 drivers/pinctrl/pinctrl-oxnas.c (pg->bank ? bank 619 drivers/pinctrl/pinctrl-oxnas.c (pg->bank ? bank 645 drivers/pinctrl/pinctrl-oxnas.c unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0); bank 652 drivers/pinctrl/pinctrl-oxnas.c fname, pg->bank, pg->pin, bank 697 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); bank 698 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset - bank->gpio_chip.base); bank 701 drivers/pinctrl/pinctrl-oxnas.c offset, bank->gpio_chip.base, bank->id, mask); bank 704 drivers/pinctrl/pinctrl-oxnas.c (bank->id ? bank 709 drivers/pinctrl/pinctrl-oxnas.c (bank->id ? bank 714 drivers/pinctrl/pinctrl-oxnas.c (bank->id ? bank 727 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); bank 728 drivers/pinctrl/pinctrl-oxnas.c unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); bank 729 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset - bank->gpio_chip.base); bank 732 drivers/pinctrl/pinctrl-oxnas.c offset, bank->gpio_chip.base, bank->id, mask); bank 756 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); bank 759 drivers/pinctrl/pinctrl-oxnas.c return !(readl_relaxed(bank->reg_base + OUTPUT_EN) & mask); bank 765 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); bank 768 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR); bank 775 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); bank 778 drivers/pinctrl/pinctrl-oxnas.c return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0; bank 784 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); bank 788 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_SET); bank 790 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR); bank 796 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); bank 800 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET); bank 841 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); bank 843 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pin - bank->gpio_chip.base); bank 850 drivers/pinctrl/pinctrl-oxnas.c (bank->id ? bank 872 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); bank 874 drivers/pinctrl/pinctrl-oxnas.c unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); bank 875 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pin - bank->gpio_chip.base); bank 903 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); bank 906 drivers/pinctrl/pinctrl-oxnas.c u32 offset = pin - bank->gpio_chip.base; bank 910 drivers/pinctrl/pinctrl-oxnas.c pin, bank->gpio_chip.base, mask); bank 919 drivers/pinctrl/pinctrl-oxnas.c (bank->id ? bank 939 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); bank 940 drivers/pinctrl/pinctrl-oxnas.c unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); bank 943 drivers/pinctrl/pinctrl-oxnas.c u32 offset = pin - bank->gpio_chip.base; bank 947 drivers/pinctrl/pinctrl-oxnas.c pin, bank->gpio_chip.base, mask); bank 984 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); bank 987 drivers/pinctrl/pinctrl-oxnas.c writel(mask, bank->reg_base + IRQ_PENDING); bank 993 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); bank 998 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask, bank 999 drivers/pinctrl/pinctrl-oxnas.c bank->reg_base + RE_IRQ_ENABLE); bank 1002 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask, bank 1003 drivers/pinctrl/pinctrl-oxnas.c bank->reg_base + FE_IRQ_ENABLE); bank 1009 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = gpiochip_get_data(chip); bank 1014 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask, bank 1015 drivers/pinctrl/pinctrl-oxnas.c bank->reg_base + RE_IRQ_ENABLE); bank 1018 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask, bank 1019 drivers/pinctrl/pinctrl-oxnas.c bank->reg_base + FE_IRQ_ENABLE); bank 1045 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank = gpiochip_get_data(gc); bank 1052 drivers/pinctrl/pinctrl-oxnas.c stat = readl(bank->reg_base + IRQ_PENDING); bank 1196 drivers/pinctrl/pinctrl-oxnas.c struct oxnas_gpio_bank *bank; bank 1220 drivers/pinctrl/pinctrl-oxnas.c bank = &oxnas_gpio_banks[id]; bank 1223 drivers/pinctrl/pinctrl-oxnas.c bank->reg_base = devm_ioremap_resource(&pdev->dev, res); bank 1224 drivers/pinctrl/pinctrl-oxnas.c if (IS_ERR(bank->reg_base)) bank 1225 drivers/pinctrl/pinctrl-oxnas.c return PTR_ERR(bank->reg_base); bank 1231 drivers/pinctrl/pinctrl-oxnas.c bank->id = id; bank 1232 drivers/pinctrl/pinctrl-oxnas.c bank->gpio_chip.parent = &pdev->dev; bank 1233 drivers/pinctrl/pinctrl-oxnas.c bank->gpio_chip.of_node = np; bank 1234 drivers/pinctrl/pinctrl-oxnas.c bank->gpio_chip.ngpio = ngpios; bank 1235 drivers/pinctrl/pinctrl-oxnas.c ret = gpiochip_add_data(&bank->gpio_chip, bank); bank 1242 drivers/pinctrl/pinctrl-oxnas.c ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip, bank 1247 drivers/pinctrl/pinctrl-oxnas.c gpiochip_remove(&bank->gpio_chip); bank 1251 drivers/pinctrl/pinctrl-oxnas.c gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip, bank 41 drivers/pinctrl/pinctrl-pic32.c #define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK) bank 1802 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc); bank 1803 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset - bank->gpio_chip.base); bank 1806 drivers/pinctrl/pinctrl-pic32.c offset, bank->gpio_chip.base, mask); bank 1808 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); bank 1816 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = gpiochip_get_data(chip); bank 1819 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(TRIS_REG)); bank 1826 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = gpiochip_get_data(chip); bank 1828 drivers/pinctrl/pinctrl-pic32.c return !!(readl(bank->reg_base + PORT_REG) & BIT(offset)); bank 1834 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = gpiochip_get_data(chip); bank 1838 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(PORT_REG)); bank 1840 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(PORT_REG)); bank 1846 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = gpiochip_get_data(chip); bank 1850 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG)); bank 1882 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin); bank 1884 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(pin - bank->gpio_chip.base); bank 1889 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + CNPU_REG) & mask); bank 1892 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + CNPD_REG) & mask); bank 1895 drivers/pinctrl/pinctrl-pic32.c arg = !(readl(bank->reg_base + ANSEL_REG) & mask); bank 1898 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + ANSEL_REG) & mask); bank 1901 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + ODCU_REG) & mask); bank 1904 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + TRIS_REG) & mask); bank 1907 drivers/pinctrl/pinctrl-pic32.c arg = !(readl(bank->reg_base + TRIS_REG) & mask); bank 1923 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin); bank 1927 drivers/pinctrl/pinctrl-pic32.c u32 offset = pin - bank->gpio_chip.base; bank 1931 drivers/pinctrl/pinctrl-pic32.c pin, bank->gpio_chip.base, mask); bank 1940 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base +PIC32_SET(CNPU_REG)); bank 1944 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNPD_REG)); bank 1948 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); bank 1952 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG)); bank 1956 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(ODCU_REG)); bank 1959 drivers/pinctrl/pinctrl-pic32.c pic32_gpio_direction_input(&bank->gpio_chip, offset); bank 1962 drivers/pinctrl/pinctrl-pic32.c pic32_gpio_direction_output(&bank->gpio_chip, bank 1991 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = gpiochip_get_data(chip); bank 1993 drivers/pinctrl/pinctrl-pic32.c return !!(readl(bank->reg_base + TRIS_REG) & BIT(offset)); bank 1998 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = irqd_to_bank(data); bank 2000 drivers/pinctrl/pinctrl-pic32.c writel(0, bank->reg_base + CNF_REG); bank 2005 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = irqd_to_bank(data); bank 2007 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG)); bank 2012 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = irqd_to_bank(data); bank 2014 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG)); bank 2029 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = irqd_to_bank(data); bank 2035 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); bank 2037 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG)); bank 2039 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); bank 2043 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG)); bank 2045 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); bank 2047 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); bank 2051 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); bank 2053 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); bank 2055 drivers/pinctrl/pinctrl-pic32.c writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); bank 2068 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = gpiochip_get_data(gc); bank 2073 drivers/pinctrl/pinctrl-pic32.c cnen_rise = readl(bank->reg_base + CNEN_REG); bank 2074 drivers/pinctrl/pinctrl-pic32.c cnne_fall = readl(bank->reg_base + CNNE_REG); bank 2089 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank = gpiochip_get_data(gc); bank 2097 drivers/pinctrl/pinctrl-pic32.c stat = readl(bank->reg_base + CNF_REG); bank 2202 drivers/pinctrl/pinctrl-pic32.c struct pic32_gpio_bank *bank; bank 2217 drivers/pinctrl/pinctrl-pic32.c bank = &pic32_gpio_banks[id]; bank 2220 drivers/pinctrl/pinctrl-pic32.c bank->reg_base = devm_ioremap_resource(&pdev->dev, res); bank 2221 drivers/pinctrl/pinctrl-pic32.c if (IS_ERR(bank->reg_base)) bank 2222 drivers/pinctrl/pinctrl-pic32.c return PTR_ERR(bank->reg_base); bank 2228 drivers/pinctrl/pinctrl-pic32.c bank->clk = devm_clk_get(&pdev->dev, NULL); bank 2229 drivers/pinctrl/pinctrl-pic32.c if (IS_ERR(bank->clk)) { bank 2230 drivers/pinctrl/pinctrl-pic32.c ret = PTR_ERR(bank->clk); bank 2235 drivers/pinctrl/pinctrl-pic32.c ret = clk_prepare_enable(bank->clk); bank 2241 drivers/pinctrl/pinctrl-pic32.c bank->gpio_chip.parent = &pdev->dev; bank 2242 drivers/pinctrl/pinctrl-pic32.c bank->gpio_chip.of_node = np; bank 2243 drivers/pinctrl/pinctrl-pic32.c ret = gpiochip_add_data(&bank->gpio_chip, bank); bank 2250 drivers/pinctrl/pinctrl-pic32.c ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip, bank 2255 drivers/pinctrl/pinctrl-pic32.c gpiochip_remove(&bank->gpio_chip); bank 2259 drivers/pinctrl/pinctrl-pic32.c gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip, bank 57 drivers/pinctrl/pinctrl-pistachio.c #define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank)) bank 846 drivers/pinctrl/pinctrl-pistachio.c static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg) bank 848 drivers/pinctrl/pinctrl-pistachio.c return readl(bank->base + reg); bank 851 drivers/pinctrl/pinctrl-pistachio.c static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val, bank 854 drivers/pinctrl/pinctrl-pistachio.c writel(val, bank->base + reg); bank 857 drivers/pinctrl/pinctrl-pistachio.c static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank, bank 864 drivers/pinctrl/pinctrl-pistachio.c gpio_writel(bank, (0x10000 | val) << bit, reg); bank 867 drivers/pinctrl/pinctrl-pistachio.c static inline void gpio_enable(struct pistachio_gpio_bank *bank, bank 870 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_BIT_EN, offset, 1); bank 873 drivers/pinctrl/pinctrl-pistachio.c static inline void gpio_disable(struct pistachio_gpio_bank *bank, bank 876 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_BIT_EN, offset, 0); bank 1167 drivers/pinctrl/pinctrl-pistachio.c struct pistachio_gpio_bank *bank = gpiochip_get_data(chip); bank 1169 drivers/pinctrl/pinctrl-pistachio.c return !(gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset)); bank 1174 drivers/pinctrl/pinctrl-pistachio.c struct pistachio_gpio_bank *bank = gpiochip_get_data(chip); bank 1177 drivers/pinctrl/pinctrl-pistachio.c if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset)) bank 1182 drivers/pinctrl/pinctrl-pistachio.c return !!(gpio_readl(bank, reg) & BIT(offset)); bank 1188 drivers/pinctrl/pinctrl-pistachio.c struct pistachio_gpio_bank *bank = gpiochip_get_data(chip); bank 1190 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value); bank 1196 drivers/pinctrl/pinctrl-pistachio.c struct pistachio_gpio_bank *bank = gpiochip_get_data(chip); bank 1198 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 0); bank 1199 drivers/pinctrl/pinctrl-pistachio.c gpio_enable(bank, offset); bank 1207 drivers/pinctrl/pinctrl-pistachio.c struct pistachio_gpio_bank *bank = gpiochip_get_data(chip); bank 1210 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 1); bank 1211 drivers/pinctrl/pinctrl-pistachio.c gpio_enable(bank, offset); bank 1218 drivers/pinctrl/pinctrl-pistachio.c struct pistachio_gpio_bank *bank = irqd_to_bank(data); bank 1220 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0); bank 1225 drivers/pinctrl/pinctrl-pistachio.c struct pistachio_gpio_bank *bank = irqd_to_bank(data); bank 1227 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0); bank 1232 drivers/pinctrl/pinctrl-pistachio.c struct pistachio_gpio_bank *bank = irqd_to_bank(data); bank 1234 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1); bank 1249 drivers/pinctrl/pinctrl-pistachio.c struct pistachio_gpio_bank *bank = irqd_to_bank(data); bank 1253 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1); bank 1254 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq, bank 1256 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq, bank 1260 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0); bank 1261 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq, bank 1263 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq, bank 1267 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq, bank 1269 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq, bank 1273 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1); bank 1274 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq, bank 1278 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0); bank 1279 drivers/pinctrl/pinctrl-pistachio.c gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq, bank 1297 drivers/pinctrl/pinctrl-pistachio.c struct pistachio_gpio_bank *bank = gpiochip_get_data(gc); bank 1303 drivers/pinctrl/pinctrl-pistachio.c pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) & bank 1304 drivers/pinctrl/pinctrl-pistachio.c gpio_readl(bank, GPIO_INTERRUPT_EN); bank 1348 drivers/pinctrl/pinctrl-pistachio.c struct pistachio_gpio_bank *bank; bank 1380 drivers/pinctrl/pinctrl-pistachio.c bank = &pctl->gpio_banks[i]; bank 1381 drivers/pinctrl/pinctrl-pistachio.c bank->pctl = pctl; bank 1382 drivers/pinctrl/pinctrl-pistachio.c bank->base = pctl->base + GPIO_BANK_BASE(i); bank 1384 drivers/pinctrl/pinctrl-pistachio.c bank->gpio_chip.parent = pctl->dev; bank 1385 drivers/pinctrl/pinctrl-pistachio.c bank->gpio_chip.of_node = child; bank 1386 drivers/pinctrl/pinctrl-pistachio.c ret = gpiochip_add_data(&bank->gpio_chip, bank); bank 1393 drivers/pinctrl/pinctrl-pistachio.c ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip, bank 1398 drivers/pinctrl/pinctrl-pistachio.c gpiochip_remove(&bank->gpio_chip); bank 1401 drivers/pinctrl/pinctrl-pistachio.c gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip, bank 1404 drivers/pinctrl/pinctrl-pistachio.c ret = gpiochip_add_pin_range(&bank->gpio_chip, bank 1406 drivers/pinctrl/pinctrl-pistachio.c bank->pin_base, bank->npins); bank 1410 drivers/pinctrl/pinctrl-pistachio.c gpiochip_remove(&bank->gpio_chip); bank 1418 drivers/pinctrl/pinctrl-pistachio.c bank = &pctl->gpio_banks[i - 1]; bank 1419 drivers/pinctrl/pinctrl-pistachio.c gpiochip_remove(&bank->gpio_chip); bank 342 drivers/pinctrl/pinctrl-rockchip.c void (*pull_calc_reg)(struct rockchip_pin_bank *bank, bank 345 drivers/pinctrl/pinctrl-rockchip.c void (*drv_calc_reg)(struct rockchip_pin_bank *bank, bank 348 drivers/pinctrl/pinctrl-rockchip.c int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, bank 681 drivers/pinctrl/pinctrl-rockchip.c static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, bank 684 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 691 drivers/pinctrl/pinctrl-rockchip.c if (data->num == bank->bank_num && bank 1112 drivers/pinctrl/pinctrl-rockchip.c static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, bank 1115 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1122 drivers/pinctrl/pinctrl-rockchip.c if ((data->bank_num == bank->bank_num) && bank 1137 drivers/pinctrl/pinctrl-rockchip.c static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) bank 1139 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1149 drivers/pinctrl/pinctrl-rockchip.c if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { bank 1154 drivers/pinctrl/pinctrl-rockchip.c if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) bank 1157 drivers/pinctrl/pinctrl-rockchip.c regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) bank 1161 drivers/pinctrl/pinctrl-rockchip.c mux_type = bank->iomux[iomux_num].type; bank 1162 drivers/pinctrl/pinctrl-rockchip.c reg = bank->iomux[iomux_num].offset; bank 1178 drivers/pinctrl/pinctrl-rockchip.c if (bank->recalced_mask & BIT(pin)) bank 1179 drivers/pinctrl/pinctrl-rockchip.c rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); bank 1188 drivers/pinctrl/pinctrl-rockchip.c static int rockchip_verify_mux(struct rockchip_pin_bank *bank, bank 1191 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1197 drivers/pinctrl/pinctrl-rockchip.c if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { bank 1202 drivers/pinctrl/pinctrl-rockchip.c if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { bank 1226 drivers/pinctrl/pinctrl-rockchip.c static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) bank 1228 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1235 drivers/pinctrl/pinctrl-rockchip.c ret = rockchip_verify_mux(bank, pin, mux); bank 1239 drivers/pinctrl/pinctrl-rockchip.c if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) bank 1243 drivers/pinctrl/pinctrl-rockchip.c bank->bank_num, pin, mux); bank 1245 drivers/pinctrl/pinctrl-rockchip.c regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) bank 1249 drivers/pinctrl/pinctrl-rockchip.c mux_type = bank->iomux[iomux_num].type; bank 1250 drivers/pinctrl/pinctrl-rockchip.c reg = bank->iomux[iomux_num].offset; bank 1266 drivers/pinctrl/pinctrl-rockchip.c if (bank->recalced_mask & BIT(pin)) bank 1267 drivers/pinctrl/pinctrl-rockchip.c rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); bank 1269 drivers/pinctrl/pinctrl-rockchip.c if (bank->route_mask & BIT(pin)) { bank 1270 drivers/pinctrl/pinctrl-rockchip.c if (rockchip_get_mux_route(bank, pin, mux, &route_location, bank 1304 drivers/pinctrl/pinctrl-rockchip.c static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, bank 1308 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1311 drivers/pinctrl/pinctrl-rockchip.c if (bank->bank_num == 0) { bank 1320 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; bank 1334 drivers/pinctrl/pinctrl-rockchip.c static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, bank 1338 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1341 drivers/pinctrl/pinctrl-rockchip.c if (bank->bank_num == 0) { bank 1350 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; bank 1364 drivers/pinctrl/pinctrl-rockchip.c static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, bank 1369 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1372 drivers/pinctrl/pinctrl-rockchip.c if (bank->bank_num == 0) { bank 1380 drivers/pinctrl/pinctrl-rockchip.c *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; bank 1395 drivers/pinctrl/pinctrl-rockchip.c static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, bank 1399 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1402 drivers/pinctrl/pinctrl-rockchip.c if (bank->bank_num == 0) { bank 1410 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; bank 1424 drivers/pinctrl/pinctrl-rockchip.c static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, bank 1428 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1431 drivers/pinctrl/pinctrl-rockchip.c if (bank->bank_num == 0) { bank 1440 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; bank 1454 drivers/pinctrl/pinctrl-rockchip.c static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, bank 1459 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1462 drivers/pinctrl/pinctrl-rockchip.c if (bank->bank_num == 0) { bank 1470 drivers/pinctrl/pinctrl-rockchip.c *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; bank 1482 drivers/pinctrl/pinctrl-rockchip.c static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, bank 1486 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1490 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; bank 1498 drivers/pinctrl/pinctrl-rockchip.c static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, bank 1502 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1506 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; bank 1518 drivers/pinctrl/pinctrl-rockchip.c static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, bank 1522 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1525 drivers/pinctrl/pinctrl-rockchip.c if (bank->bank_num == 0 && pin_num < 12) { bank 1527 drivers/pinctrl/pinctrl-rockchip.c : bank->regmap_pull; bank 1539 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; bank 1553 drivers/pinctrl/pinctrl-rockchip.c static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, bank 1557 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1560 drivers/pinctrl/pinctrl-rockchip.c if (bank->bank_num == 0) { bank 1573 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; bank 1587 drivers/pinctrl/pinctrl-rockchip.c static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, bank 1591 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1594 drivers/pinctrl/pinctrl-rockchip.c if (bank->bank_num == 0) { bank 1607 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; bank 1617 drivers/pinctrl/pinctrl-rockchip.c static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, bank 1621 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1625 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; bank 1634 drivers/pinctrl/pinctrl-rockchip.c static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, bank 1638 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1642 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; bank 1652 drivers/pinctrl/pinctrl-rockchip.c static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, bank 1656 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1659 drivers/pinctrl/pinctrl-rockchip.c if (bank->bank_num == 0) { bank 1672 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; bank 1683 drivers/pinctrl/pinctrl-rockchip.c static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, bank 1687 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1690 drivers/pinctrl/pinctrl-rockchip.c if (bank->bank_num == 0) { bank 1703 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; bank 1715 drivers/pinctrl/pinctrl-rockchip.c static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, bank 1719 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1722 drivers/pinctrl/pinctrl-rockchip.c if ((bank->bank_num == 0) || (bank->bank_num == 1)) { bank 1726 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; bank 1737 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; bank 1745 drivers/pinctrl/pinctrl-rockchip.c static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, bank 1749 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1753 drivers/pinctrl/pinctrl-rockchip.c if ((bank->bank_num == 0) || (bank->bank_num == 1)) bank 1758 drivers/pinctrl/pinctrl-rockchip.c *reg = bank->drv[drv_num].offset; bank 1759 drivers/pinctrl/pinctrl-rockchip.c if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || bank 1760 drivers/pinctrl/pinctrl-rockchip.c (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) bank 1774 drivers/pinctrl/pinctrl-rockchip.c static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, bank 1777 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1783 drivers/pinctrl/pinctrl-rockchip.c int drv_type = bank->drv[pin_num / 8].drv_type; bank 1785 drivers/pinctrl/pinctrl-rockchip.c ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); bank 1851 drivers/pinctrl/pinctrl-rockchip.c static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, bank 1854 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1860 drivers/pinctrl/pinctrl-rockchip.c int drv_type = bank->drv[pin_num / 8].drv_type; bank 1863 drivers/pinctrl/pinctrl-rockchip.c bank->bank_num, pin_num, strength); bank 1865 drivers/pinctrl/pinctrl-rockchip.c ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); bank 1960 drivers/pinctrl/pinctrl-rockchip.c static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) bank 1962 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 1973 drivers/pinctrl/pinctrl-rockchip.c ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); bank 1991 drivers/pinctrl/pinctrl-rockchip.c pull_type = bank->pull_type[pin_num / 8]; bank 2002 drivers/pinctrl/pinctrl-rockchip.c static int rockchip_set_pull(struct rockchip_pin_bank *bank, bank 2005 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 2013 drivers/pinctrl/pinctrl-rockchip.c bank->bank_num, pin_num, pull); bank 2019 drivers/pinctrl/pinctrl-rockchip.c ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); bank 2035 drivers/pinctrl/pinctrl-rockchip.c pull_type = bank->pull_type[pin_num / 8]; bank 2071 drivers/pinctrl/pinctrl-rockchip.c static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, bank 2076 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 2081 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; bank 2088 drivers/pinctrl/pinctrl-rockchip.c static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) bank 2090 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 2097 drivers/pinctrl/pinctrl-rockchip.c ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); bank 2109 drivers/pinctrl/pinctrl-rockchip.c static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, bank 2112 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pinctrl *info = bank->drvdata; bank 2120 drivers/pinctrl/pinctrl-rockchip.c bank->bank_num, pin_num, enable); bank 2122 drivers/pinctrl/pinctrl-rockchip.c ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); bank 2170 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank; bank 2181 drivers/pinctrl/pinctrl-rockchip.c bank = pin_to_bank(info, pins[cnt]); bank 2182 drivers/pinctrl/pinctrl-rockchip.c ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, bank 2191 drivers/pinctrl/pinctrl-rockchip.c rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); bank 2201 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = gpiochip_get_data(chip); bank 2205 drivers/pinctrl/pinctrl-rockchip.c ret = clk_enable(bank->clk); bank 2207 drivers/pinctrl/pinctrl-rockchip.c dev_err(bank->drvdata->dev, bank 2208 drivers/pinctrl/pinctrl-rockchip.c "failed to enable clock for bank %s\n", bank->name); bank 2211 drivers/pinctrl/pinctrl-rockchip.c data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); bank 2212 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 2225 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank; bank 2230 drivers/pinctrl/pinctrl-rockchip.c bank = gpiochip_get_data(chip); bank 2232 drivers/pinctrl/pinctrl-rockchip.c ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); bank 2236 drivers/pinctrl/pinctrl-rockchip.c clk_enable(bank->clk); bank 2237 drivers/pinctrl/pinctrl-rockchip.c raw_spin_lock_irqsave(&bank->slock, flags); bank 2239 drivers/pinctrl/pinctrl-rockchip.c data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); bank 2245 drivers/pinctrl/pinctrl-rockchip.c writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); bank 2247 drivers/pinctrl/pinctrl-rockchip.c raw_spin_unlock_irqrestore(&bank->slock, flags); bank 2248 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 2312 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = pin_to_bank(info, pin); bank 2324 drivers/pinctrl/pinctrl-rockchip.c rc = rockchip_set_pull(bank, pin - bank->pin_base, bank 2339 drivers/pinctrl/pinctrl-rockchip.c rc = rockchip_set_pull(bank, pin - bank->pin_base, bank 2345 drivers/pinctrl/pinctrl-rockchip.c rockchip_gpio_set(&bank->gpio_chip, bank 2346 drivers/pinctrl/pinctrl-rockchip.c pin - bank->pin_base, arg); bank 2347 drivers/pinctrl/pinctrl-rockchip.c rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, bank 2348 drivers/pinctrl/pinctrl-rockchip.c pin - bank->pin_base, false); bank 2357 drivers/pinctrl/pinctrl-rockchip.c rc = rockchip_set_drive_perpin(bank, bank 2358 drivers/pinctrl/pinctrl-rockchip.c pin - bank->pin_base, arg); bank 2366 drivers/pinctrl/pinctrl-rockchip.c rc = rockchip_set_schmitt(bank, bank 2367 drivers/pinctrl/pinctrl-rockchip.c pin - bank->pin_base, arg); bank 2385 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = pin_to_bank(info, pin); bank 2392 drivers/pinctrl/pinctrl-rockchip.c if (rockchip_get_pull(bank, pin - bank->pin_base) != param) bank 2404 drivers/pinctrl/pinctrl-rockchip.c if (rockchip_get_pull(bank, pin - bank->pin_base) != param) bank 2410 drivers/pinctrl/pinctrl-rockchip.c rc = rockchip_get_mux(bank, pin - bank->pin_base); bank 2414 drivers/pinctrl/pinctrl-rockchip.c rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); bank 2425 drivers/pinctrl/pinctrl-rockchip.c rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); bank 2435 drivers/pinctrl/pinctrl-rockchip.c rc = rockchip_get_schmitt(bank, pin - bank->pin_base); bank 2482 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank; bank 2522 drivers/pinctrl/pinctrl-rockchip.c bank = bank_num_to_bank(info, num); bank 2523 drivers/pinctrl/pinctrl-rockchip.c if (IS_ERR(bank)) bank 2524 drivers/pinctrl/pinctrl-rockchip.c return PTR_ERR(bank); bank 2526 drivers/pinctrl/pinctrl-rockchip.c grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); bank 2633 drivers/pinctrl/pinctrl-rockchip.c int pin, bank, ret; bank 2652 drivers/pinctrl/pinctrl-rockchip.c for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { bank 2653 drivers/pinctrl/pinctrl-rockchip.c pin_bank = &info->ctrl->pin_banks[bank]; bank 2672 drivers/pinctrl/pinctrl-rockchip.c for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { bank 2673 drivers/pinctrl/pinctrl-rockchip.c pin_bank = &info->ctrl->pin_banks[bank]; bank 2675 drivers/pinctrl/pinctrl-rockchip.c pin_bank->grange.id = bank; bank 2692 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = gpiochip_get_data(gc); bank 2693 drivers/pinctrl/pinctrl-rockchip.c void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; bank 2697 drivers/pinctrl/pinctrl-rockchip.c clk_enable(bank->clk); bank 2698 drivers/pinctrl/pinctrl-rockchip.c raw_spin_lock_irqsave(&bank->slock, flags); bank 2706 drivers/pinctrl/pinctrl-rockchip.c raw_spin_unlock_irqrestore(&bank->slock, flags); bank 2707 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 2716 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = gpiochip_get_data(gc); bank 2719 drivers/pinctrl/pinctrl-rockchip.c clk_enable(bank->clk); bank 2720 drivers/pinctrl/pinctrl-rockchip.c data = readl(bank->reg_base + GPIO_EXT_PORT); bank 2721 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 2752 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = gpiochip_get_data(gc); bank 2753 drivers/pinctrl/pinctrl-rockchip.c void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; bank 2757 drivers/pinctrl/pinctrl-rockchip.c clk_enable(bank->clk); bank 2758 drivers/pinctrl/pinctrl-rockchip.c raw_spin_lock_irqsave(&bank->slock, flags); bank 2767 drivers/pinctrl/pinctrl-rockchip.c raw_spin_unlock_irqrestore(&bank->slock, flags); bank 2768 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 2807 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = gpiochip_get_data(gc); bank 2810 drivers/pinctrl/pinctrl-rockchip.c if (!bank->domain) bank 2813 drivers/pinctrl/pinctrl-rockchip.c virq = irq_create_mapping(bank->domain, offset); bank 2838 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); bank 2841 drivers/pinctrl/pinctrl-rockchip.c dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); bank 2845 drivers/pinctrl/pinctrl-rockchip.c pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); bank 2852 drivers/pinctrl/pinctrl-rockchip.c virq = irq_linear_revmap(bank->domain, irq); bank 2855 drivers/pinctrl/pinctrl-rockchip.c dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); bank 2859 drivers/pinctrl/pinctrl-rockchip.c dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); bank 2865 drivers/pinctrl/pinctrl-rockchip.c if (bank->toggle_edge_mode & BIT(irq)) { bank 2869 drivers/pinctrl/pinctrl-rockchip.c data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); bank 2871 drivers/pinctrl/pinctrl-rockchip.c raw_spin_lock_irqsave(&bank->slock, flags); bank 2873 drivers/pinctrl/pinctrl-rockchip.c polarity = readl_relaxed(bank->reg_base + bank 2880 drivers/pinctrl/pinctrl-rockchip.c bank->reg_base + GPIO_INT_POLARITY); bank 2882 drivers/pinctrl/pinctrl-rockchip.c raw_spin_unlock_irqrestore(&bank->slock, flags); bank 2885 drivers/pinctrl/pinctrl-rockchip.c data = readl_relaxed(bank->reg_base + bank 2899 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = gc->private; bank 2908 drivers/pinctrl/pinctrl-rockchip.c ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); bank 2912 drivers/pinctrl/pinctrl-rockchip.c clk_enable(bank->clk); bank 2913 drivers/pinctrl/pinctrl-rockchip.c raw_spin_lock_irqsave(&bank->slock, flags); bank 2915 drivers/pinctrl/pinctrl-rockchip.c data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); bank 2917 drivers/pinctrl/pinctrl-rockchip.c writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); bank 2919 drivers/pinctrl/pinctrl-rockchip.c raw_spin_unlock_irqrestore(&bank->slock, flags); bank 2926 drivers/pinctrl/pinctrl-rockchip.c raw_spin_lock_irqsave(&bank->slock, flags); bank 2934 drivers/pinctrl/pinctrl-rockchip.c bank->toggle_edge_mode |= mask; bank 2941 drivers/pinctrl/pinctrl-rockchip.c data = readl(bank->reg_base + GPIO_EXT_PORT); bank 2948 drivers/pinctrl/pinctrl-rockchip.c bank->toggle_edge_mode &= ~mask; bank 2953 drivers/pinctrl/pinctrl-rockchip.c bank->toggle_edge_mode &= ~mask; bank 2958 drivers/pinctrl/pinctrl-rockchip.c bank->toggle_edge_mode &= ~mask; bank 2963 drivers/pinctrl/pinctrl-rockchip.c bank->toggle_edge_mode &= ~mask; bank 2969 drivers/pinctrl/pinctrl-rockchip.c raw_spin_unlock_irqrestore(&bank->slock, flags); bank 2970 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 2978 drivers/pinctrl/pinctrl-rockchip.c raw_spin_unlock_irqrestore(&bank->slock, flags); bank 2979 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 2987 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = gc->private; bank 2989 drivers/pinctrl/pinctrl-rockchip.c clk_enable(bank->clk); bank 2990 drivers/pinctrl/pinctrl-rockchip.c bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); bank 2992 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 2998 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = gc->private; bank 3000 drivers/pinctrl/pinctrl-rockchip.c clk_enable(bank->clk); bank 3001 drivers/pinctrl/pinctrl-rockchip.c irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); bank 3002 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 3008 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = gc->private; bank 3010 drivers/pinctrl/pinctrl-rockchip.c clk_enable(bank->clk); bank 3017 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = gc->private; bank 3020 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 3027 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = ctrl->pin_banks; bank 3033 drivers/pinctrl/pinctrl-rockchip.c for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { bank 3034 drivers/pinctrl/pinctrl-rockchip.c if (!bank->valid) { bank 3036 drivers/pinctrl/pinctrl-rockchip.c bank->name); bank 3040 drivers/pinctrl/pinctrl-rockchip.c ret = clk_enable(bank->clk); bank 3043 drivers/pinctrl/pinctrl-rockchip.c bank->name); bank 3047 drivers/pinctrl/pinctrl-rockchip.c bank->domain = irq_domain_add_linear(bank->of_node, 32, bank 3049 drivers/pinctrl/pinctrl-rockchip.c if (!bank->domain) { bank 3051 drivers/pinctrl/pinctrl-rockchip.c bank->name); bank 3052 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 3056 drivers/pinctrl/pinctrl-rockchip.c ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, bank 3061 drivers/pinctrl/pinctrl-rockchip.c bank->name); bank 3062 drivers/pinctrl/pinctrl-rockchip.c irq_domain_remove(bank->domain); bank 3063 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 3072 drivers/pinctrl/pinctrl-rockchip.c writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); bank 3073 drivers/pinctrl/pinctrl-rockchip.c writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); bank 3075 drivers/pinctrl/pinctrl-rockchip.c gc = irq_get_domain_generic_chip(bank->domain, 0); bank 3076 drivers/pinctrl/pinctrl-rockchip.c gc->reg_base = bank->reg_base; bank 3077 drivers/pinctrl/pinctrl-rockchip.c gc->private = bank; bank 3089 drivers/pinctrl/pinctrl-rockchip.c gc->wake_enabled = IRQ_MSK(bank->nr_pins); bank 3091 drivers/pinctrl/pinctrl-rockchip.c irq_set_chained_handler_and_data(bank->irq, bank 3092 drivers/pinctrl/pinctrl-rockchip.c rockchip_irq_demux, bank); bank 3096 drivers/pinctrl/pinctrl-rockchip.c irq_create_mapping(bank->domain, j); bank 3098 drivers/pinctrl/pinctrl-rockchip.c clk_disable(bank->clk); bank 3108 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = ctrl->pin_banks; bank 3113 drivers/pinctrl/pinctrl-rockchip.c for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { bank 3114 drivers/pinctrl/pinctrl-rockchip.c if (!bank->valid) { bank 3116 drivers/pinctrl/pinctrl-rockchip.c bank->name); bank 3120 drivers/pinctrl/pinctrl-rockchip.c bank->gpio_chip = rockchip_gpiolib_chip; bank 3122 drivers/pinctrl/pinctrl-rockchip.c gc = &bank->gpio_chip; bank 3123 drivers/pinctrl/pinctrl-rockchip.c gc->base = bank->pin_base; bank 3124 drivers/pinctrl/pinctrl-rockchip.c gc->ngpio = bank->nr_pins; bank 3126 drivers/pinctrl/pinctrl-rockchip.c gc->of_node = bank->of_node; bank 3127 drivers/pinctrl/pinctrl-rockchip.c gc->label = bank->name; bank 3129 drivers/pinctrl/pinctrl-rockchip.c ret = gpiochip_add_data(gc, bank); bank 3142 drivers/pinctrl/pinctrl-rockchip.c for (--i, --bank; i >= 0; --i, --bank) { bank 3143 drivers/pinctrl/pinctrl-rockchip.c if (!bank->valid) bank 3145 drivers/pinctrl/pinctrl-rockchip.c gpiochip_remove(&bank->gpio_chip); bank 3154 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank = ctrl->pin_banks; bank 3157 drivers/pinctrl/pinctrl-rockchip.c for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { bank 3158 drivers/pinctrl/pinctrl-rockchip.c if (!bank->valid) bank 3160 drivers/pinctrl/pinctrl-rockchip.c gpiochip_remove(&bank->gpio_chip); bank 3166 drivers/pinctrl/pinctrl-rockchip.c static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, bank 3172 drivers/pinctrl/pinctrl-rockchip.c if (of_address_to_resource(bank->of_node, 0, &res)) { bank 3177 drivers/pinctrl/pinctrl-rockchip.c bank->reg_base = devm_ioremap_resource(info->dev, &res); bank 3178 drivers/pinctrl/pinctrl-rockchip.c if (IS_ERR(bank->reg_base)) bank 3179 drivers/pinctrl/pinctrl-rockchip.c return PTR_ERR(bank->reg_base); bank 3185 drivers/pinctrl/pinctrl-rockchip.c if (of_device_is_compatible(bank->of_node, bank 3189 drivers/pinctrl/pinctrl-rockchip.c node = of_parse_phandle(bank->of_node->parent, bank 3192 drivers/pinctrl/pinctrl-rockchip.c if (of_address_to_resource(bank->of_node, 1, &res)) { bank 3204 drivers/pinctrl/pinctrl-rockchip.c bank->regmap_pull = devm_regmap_init_mmio(info->dev, bank 3211 drivers/pinctrl/pinctrl-rockchip.c bank->irq = irq_of_parse_and_map(bank->of_node, 0); bank 3213 drivers/pinctrl/pinctrl-rockchip.c bank->clk = of_clk_get(bank->of_node, 0); bank 3214 drivers/pinctrl/pinctrl-rockchip.c if (IS_ERR(bank->clk)) bank 3215 drivers/pinctrl/pinctrl-rockchip.c return PTR_ERR(bank->clk); bank 3217 drivers/pinctrl/pinctrl-rockchip.c return clk_prepare(bank->clk); bank 3231 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_pin_bank *bank; bank 3241 drivers/pinctrl/pinctrl-rockchip.c bank = ctrl->pin_banks; bank 3242 drivers/pinctrl/pinctrl-rockchip.c for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { bank 3243 drivers/pinctrl/pinctrl-rockchip.c if (!strcmp(bank->name, np->name)) { bank 3244 drivers/pinctrl/pinctrl-rockchip.c bank->of_node = np; bank 3246 drivers/pinctrl/pinctrl-rockchip.c if (!rockchip_get_bank_data(bank, d)) bank 3247 drivers/pinctrl/pinctrl-rockchip.c bank->valid = true; bank 3258 drivers/pinctrl/pinctrl-rockchip.c bank = ctrl->pin_banks; bank 3259 drivers/pinctrl/pinctrl-rockchip.c for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { bank 3262 drivers/pinctrl/pinctrl-rockchip.c raw_spin_lock_init(&bank->slock); bank 3263 drivers/pinctrl/pinctrl-rockchip.c bank->drvdata = d; bank 3264 drivers/pinctrl/pinctrl-rockchip.c bank->pin_base = ctrl->nr_pins; bank 3265 drivers/pinctrl/pinctrl-rockchip.c ctrl->nr_pins += bank->nr_pins; bank 3269 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_iomux *iom = &bank->iomux[j]; bank 3270 drivers/pinctrl/pinctrl-rockchip.c struct rockchip_drv *drv = &bank->drv[j]; bank 3273 drivers/pinctrl/pinctrl-rockchip.c if (bank_pins >= bank->nr_pins) bank 3334 drivers/pinctrl/pinctrl-rockchip.c if (ctrl->iomux_recalced[j].num == bank->bank_num) { bank 3336 drivers/pinctrl/pinctrl-rockchip.c bank->recalced_mask |= BIT(pin); bank 3344 drivers/pinctrl/pinctrl-rockchip.c if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { bank 3346 drivers/pinctrl/pinctrl-rockchip.c bank->route_mask |= BIT(pin); bank 367 drivers/pinctrl/pinctrl-st.c struct st_gpio_bank *bank = gpio_range_to_bank(range); bank 369 drivers/pinctrl/pinctrl-st.c return &bank->pc; bank 665 drivers/pinctrl/pinctrl-st.c static inline void __st_gpio_set(struct st_gpio_bank *bank, bank 669 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_SET_POUT); bank 671 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); bank 674 drivers/pinctrl/pinctrl-st.c static void st_gpio_direction(struct st_gpio_bank *bank, bank 698 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); bank 700 drivers/pinctrl/pinctrl-st.c writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); bank 706 drivers/pinctrl/pinctrl-st.c struct st_gpio_bank *bank = gpiochip_get_data(chip); bank 708 drivers/pinctrl/pinctrl-st.c return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); bank 713 drivers/pinctrl/pinctrl-st.c struct st_gpio_bank *bank = gpiochip_get_data(chip); bank 714 drivers/pinctrl/pinctrl-st.c __st_gpio_set(bank, offset, value); bank 727 drivers/pinctrl/pinctrl-st.c struct st_gpio_bank *bank = gpiochip_get_data(chip); bank 729 drivers/pinctrl/pinctrl-st.c __st_gpio_set(bank, offset, value); bank 737 drivers/pinctrl/pinctrl-st.c struct st_gpio_bank *bank = gpiochip_get_data(chip); bank 738 drivers/pinctrl/pinctrl-st.c struct st_pio_control pc = bank->pc; bank 757 drivers/pinctrl/pinctrl-st.c value = readl(bank->base + REG_PIO_PC(i)); bank 916 drivers/pinctrl/pinctrl-st.c struct st_gpio_bank *bank = gpio_range_to_bank(range); bank 922 drivers/pinctrl/pinctrl-st.c st_pctl_set_function(&bank->pc, gpio, 0); bank 923 drivers/pinctrl/pinctrl-st.c st_gpio_direction(bank, gpio, input ? bank 1047 drivers/pinctrl/pinctrl-st.c int bank, struct st_pio_control *pc) bank 1053 drivers/pinctrl/pinctrl-st.c int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; bank 1083 drivers/pinctrl/pinctrl-st.c int bank, struct st_pio_control *pc) bank 1089 drivers/pinctrl/pinctrl-st.c int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; bank 1107 drivers/pinctrl/pinctrl-st.c int bank, struct st_pio_control *pc) bank 1111 drivers/pinctrl/pinctrl-st.c return st_pctl_dt_setup_retime_packed(info, bank, pc); bank 1113 drivers/pinctrl/pinctrl-st.c return st_pctl_dt_setup_retime_dedicated(info, bank, pc); bank 1120 drivers/pinctrl/pinctrl-st.c struct regmap *regmap, int bank, bank 1123 drivers/pinctrl/pinctrl-st.c struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); bank 1131 drivers/pinctrl/pinctrl-st.c static void st_parse_syscfgs(struct st_pinctrl *info, int bank, bank 1140 drivers/pinctrl/pinctrl-st.c int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; bank 1142 drivers/pinctrl/pinctrl-st.c struct st_pio_control *pc = &info->banks[bank].pc; bank 1146 drivers/pinctrl/pinctrl-st.c pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); bank 1147 drivers/pinctrl/pinctrl-st.c pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); bank 1148 drivers/pinctrl/pinctrl-st.c pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); bank 1149 drivers/pinctrl/pinctrl-st.c pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); bank 1154 drivers/pinctrl/pinctrl-st.c st_pctl_dt_setup_retime(info, bank, pc); bank 1280 drivers/pinctrl/pinctrl-st.c struct st_gpio_bank *bank = gpiochip_get_data(gc); bank 1282 drivers/pinctrl/pinctrl-st.c writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); bank 1288 drivers/pinctrl/pinctrl-st.c struct st_gpio_bank *bank = gpiochip_get_data(gc); bank 1290 drivers/pinctrl/pinctrl-st.c writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); bank 1312 drivers/pinctrl/pinctrl-st.c struct st_gpio_bank *bank = gpiochip_get_data(gc); bank 1334 drivers/pinctrl/pinctrl-st.c comp = st_gpio_get(&bank->gpio_chip, pin); bank 1341 drivers/pinctrl/pinctrl-st.c spin_lock_irqsave(&bank->lock, flags); bank 1342 drivers/pinctrl/pinctrl-st.c bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( bank 1344 drivers/pinctrl/pinctrl-st.c bank->irq_edge_conf |= pin_edge_conf; bank 1345 drivers/pinctrl/pinctrl-st.c spin_unlock_irqrestore(&bank->lock, flags); bank 1347 drivers/pinctrl/pinctrl-st.c val = readl(bank->base + REG_PIO_PCOMP); bank 1350 drivers/pinctrl/pinctrl-st.c writel(val, bank->base + REG_PIO_PCOMP); bank 1379 drivers/pinctrl/pinctrl-st.c static void __gpio_irq_handler(struct st_gpio_bank *bank) bank 1385 drivers/pinctrl/pinctrl-st.c spin_lock_irqsave(&bank->lock, flags); bank 1386 drivers/pinctrl/pinctrl-st.c bank_edge_mask = bank->irq_edge_conf; bank 1387 drivers/pinctrl/pinctrl-st.c spin_unlock_irqrestore(&bank->lock, flags); bank 1390 drivers/pinctrl/pinctrl-st.c port_in = readl(bank->base + REG_PIO_PIN); bank 1391 drivers/pinctrl/pinctrl-st.c port_comp = readl(bank->base + REG_PIO_PCOMP); bank 1392 drivers/pinctrl/pinctrl-st.c port_mask = readl(bank->base + REG_PIO_PMASK); bank 1405 drivers/pinctrl/pinctrl-st.c val = st_gpio_get(&bank->gpio_chip, n); bank 1408 drivers/pinctrl/pinctrl-st.c val ? bank->base + REG_PIO_SET_PCOMP : bank 1409 drivers/pinctrl/pinctrl-st.c bank->base + REG_PIO_CLR_PCOMP); bank 1416 drivers/pinctrl/pinctrl-st.c generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n)); bank 1426 drivers/pinctrl/pinctrl-st.c struct st_gpio_bank *bank = gpiochip_get_data(gc); bank 1429 drivers/pinctrl/pinctrl-st.c __gpio_irq_handler(bank); bank 1475 drivers/pinctrl/pinctrl-st.c struct st_gpio_bank *bank = &info->banks[bank_nr]; bank 1476 drivers/pinctrl/pinctrl-st.c struct pinctrl_gpio_range *range = &bank->range; bank 1485 drivers/pinctrl/pinctrl-st.c bank->base = devm_ioremap_resource(dev, &res); bank 1486 drivers/pinctrl/pinctrl-st.c if (IS_ERR(bank->base)) bank 1487 drivers/pinctrl/pinctrl-st.c return PTR_ERR(bank->base); bank 1489 drivers/pinctrl/pinctrl-st.c bank->gpio_chip = st_gpio_template; bank 1490 drivers/pinctrl/pinctrl-st.c bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; bank 1491 drivers/pinctrl/pinctrl-st.c bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; bank 1492 drivers/pinctrl/pinctrl-st.c bank->gpio_chip.of_node = np; bank 1493 drivers/pinctrl/pinctrl-st.c bank->gpio_chip.parent = dev; bank 1494 drivers/pinctrl/pinctrl-st.c spin_lock_init(&bank->lock); bank 1497 drivers/pinctrl/pinctrl-st.c bank->gpio_chip.label = range->name; bank 1501 drivers/pinctrl/pinctrl-st.c range->npins = bank->gpio_chip.ngpio; bank 1502 drivers/pinctrl/pinctrl-st.c range->gc = &bank->gpio_chip; bank 1503 drivers/pinctrl/pinctrl-st.c err = gpiochip_add_data(&bank->gpio_chip, bank); bank 1531 drivers/pinctrl/pinctrl-st.c gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip, bank 1536 drivers/pinctrl/pinctrl-st.c err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip, bank 1540 drivers/pinctrl/pinctrl-st.c gpiochip_remove(&bank->gpio_chip); bank 1563 drivers/pinctrl/pinctrl-st.c int i = 0, j = 0, k = 0, bank; bank 1624 drivers/pinctrl/pinctrl-st.c bank = 0; bank 1628 drivers/pinctrl/pinctrl-st.c ret = st_gpiolib_register_bank(info, bank, child); bank 1634 drivers/pinctrl/pinctrl-st.c k = info->banks[bank].range.pin_base; bank 1635 drivers/pinctrl/pinctrl-st.c bank_name = info->banks[bank].range.name; bank 1642 drivers/pinctrl/pinctrl-st.c st_parse_syscfgs(info, bank, child); bank 1643 drivers/pinctrl/pinctrl-st.c bank++; bank 131 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c struct pm8xxx_pin_data *pin, int bank) bank 133 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c unsigned int val = bank << 4; bank 138 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c dev_err(pctrl->dev, "failed to select bank %d\n", bank); bank 144 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c dev_err(pctrl->dev, "failed to read register %d\n", bank); bank 153 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c int bank, bank 159 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c val |= bank << 4; bank 54 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); bank 55 drivers/pinctrl/samsung/pinctrl-exynos.c unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; bank 59 drivers/pinctrl/samsung/pinctrl-exynos.c spin_lock_irqsave(&bank->slock, flags); bank 61 drivers/pinctrl/samsung/pinctrl-exynos.c mask = readl(bank->eint_base + reg_mask); bank 63 drivers/pinctrl/samsung/pinctrl-exynos.c writel(mask, bank->eint_base + reg_mask); bank 65 drivers/pinctrl/samsung/pinctrl-exynos.c spin_unlock_irqrestore(&bank->slock, flags); bank 72 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); bank 73 drivers/pinctrl/samsung/pinctrl-exynos.c unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; bank 75 drivers/pinctrl/samsung/pinctrl-exynos.c writel(1 << irqd->hwirq, bank->eint_base + reg_pend); bank 82 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); bank 83 drivers/pinctrl/samsung/pinctrl-exynos.c unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; bank 98 drivers/pinctrl/samsung/pinctrl-exynos.c spin_lock_irqsave(&bank->slock, flags); bank 100 drivers/pinctrl/samsung/pinctrl-exynos.c mask = readl(bank->eint_base + reg_mask); bank 102 drivers/pinctrl/samsung/pinctrl-exynos.c writel(mask, bank->eint_base + reg_mask); bank 104 drivers/pinctrl/samsung/pinctrl-exynos.c spin_unlock_irqrestore(&bank->slock, flags); bank 111 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); bank 114 drivers/pinctrl/samsung/pinctrl-exynos.c unsigned long reg_con = our_chip->eint_con + bank->eint_offset; bank 142 drivers/pinctrl/samsung/pinctrl-exynos.c con = readl(bank->eint_base + reg_con); bank 145 drivers/pinctrl/samsung/pinctrl-exynos.c writel(con, bank->eint_base + reg_con); bank 152 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); bank 153 drivers/pinctrl/samsung/pinctrl-exynos.c const struct samsung_pin_bank_type *bank_type = bank->type; bank 158 drivers/pinctrl/samsung/pinctrl-exynos.c ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); bank 160 drivers/pinctrl/samsung/pinctrl-exynos.c dev_err(bank->gpio_chip.parent, bank 162 drivers/pinctrl/samsung/pinctrl-exynos.c bank->name, irqd->hwirq); bank 166 drivers/pinctrl/samsung/pinctrl-exynos.c reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; bank 170 drivers/pinctrl/samsung/pinctrl-exynos.c spin_lock_irqsave(&bank->slock, flags); bank 172 drivers/pinctrl/samsung/pinctrl-exynos.c con = readl(bank->pctl_base + reg_con); bank 175 drivers/pinctrl/samsung/pinctrl-exynos.c writel(con, bank->pctl_base + reg_con); bank 177 drivers/pinctrl/samsung/pinctrl-exynos.c spin_unlock_irqrestore(&bank->slock, flags); bank 184 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); bank 185 drivers/pinctrl/samsung/pinctrl-exynos.c const struct samsung_pin_bank_type *bank_type = bank->type; bank 189 drivers/pinctrl/samsung/pinctrl-exynos.c reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; bank 193 drivers/pinctrl/samsung/pinctrl-exynos.c spin_lock_irqsave(&bank->slock, flags); bank 195 drivers/pinctrl/samsung/pinctrl-exynos.c con = readl(bank->pctl_base + reg_con); bank 198 drivers/pinctrl/samsung/pinctrl-exynos.c writel(con, bank->pctl_base + reg_con); bank 200 drivers/pinctrl/samsung/pinctrl-exynos.c spin_unlock_irqrestore(&bank->slock, flags); bank 202 drivers/pinctrl/samsung/pinctrl-exynos.c gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); bank 246 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank = d->pin_banks; bank 249 drivers/pinctrl/samsung/pinctrl-exynos.c svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); bank 255 drivers/pinctrl/samsung/pinctrl-exynos.c bank += (group - 1); bank 257 drivers/pinctrl/samsung/pinctrl-exynos.c virq = irq_linear_revmap(bank->irq_domain, pin); bank 276 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank; bank 293 drivers/pinctrl/samsung/pinctrl-exynos.c bank = d->pin_banks; bank 294 drivers/pinctrl/samsung/pinctrl-exynos.c for (i = 0; i < d->nr_banks; ++i, ++bank) { bank 295 drivers/pinctrl/samsung/pinctrl-exynos.c if (bank->eint_type != EINT_TYPE_GPIO) bank 297 drivers/pinctrl/samsung/pinctrl-exynos.c bank->irq_domain = irq_domain_add_linear(bank->of_node, bank 298 drivers/pinctrl/samsung/pinctrl-exynos.c bank->nr_pins, &exynos_eint_irqd_ops, bank); bank 299 drivers/pinctrl/samsung/pinctrl-exynos.c if (!bank->irq_domain) { bank 305 drivers/pinctrl/samsung/pinctrl-exynos.c bank->soc_priv = devm_kzalloc(d->dev, bank 307 drivers/pinctrl/samsung/pinctrl-exynos.c if (!bank->soc_priv) { bank 308 drivers/pinctrl/samsung/pinctrl-exynos.c irq_domain_remove(bank->irq_domain); bank 313 drivers/pinctrl/samsung/pinctrl-exynos.c bank->irq_chip = &exynos_gpio_irq_chip; bank 319 drivers/pinctrl/samsung/pinctrl-exynos.c for (--i, --bank; i >= 0; --i, --bank) { bank 320 drivers/pinctrl/samsung/pinctrl-exynos.c if (bank->eint_type != EINT_TYPE_GPIO) bank 322 drivers/pinctrl/samsung/pinctrl-exynos.c irq_domain_remove(bank->irq_domain); bank 332 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); bank 333 drivers/pinctrl/samsung/pinctrl-exynos.c unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); bank 418 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank = eintd->bank; bank 424 drivers/pinctrl/samsung/pinctrl-exynos.c eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); bank 474 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank; bank 500 drivers/pinctrl/samsung/pinctrl-exynos.c bank = d->pin_banks; bank 501 drivers/pinctrl/samsung/pinctrl-exynos.c for (i = 0; i < d->nr_banks; ++i, ++bank) { bank 502 drivers/pinctrl/samsung/pinctrl-exynos.c if (bank->eint_type != EINT_TYPE_WKUP) bank 505 drivers/pinctrl/samsung/pinctrl-exynos.c bank->irq_domain = irq_domain_add_linear(bank->of_node, bank 506 drivers/pinctrl/samsung/pinctrl-exynos.c bank->nr_pins, &exynos_eint_irqd_ops, bank); bank 507 drivers/pinctrl/samsung/pinctrl-exynos.c if (!bank->irq_domain) { bank 513 drivers/pinctrl/samsung/pinctrl-exynos.c bank->irq_chip = irq_chip; bank 515 drivers/pinctrl/samsung/pinctrl-exynos.c if (!of_find_property(bank->of_node, "interrupts", NULL)) { bank 516 drivers/pinctrl/samsung/pinctrl-exynos.c bank->eint_type = EINT_TYPE_WKUP_MUX; bank 522 drivers/pinctrl/samsung/pinctrl-exynos.c bank->nr_pins, sizeof(*weint_data), bank 529 drivers/pinctrl/samsung/pinctrl-exynos.c for (idx = 0; idx < bank->nr_pins; ++idx) { bank 530 drivers/pinctrl/samsung/pinctrl-exynos.c irq = irq_of_parse_and_map(bank->of_node, idx); bank 533 drivers/pinctrl/samsung/pinctrl-exynos.c bank->name, idx); bank 537 drivers/pinctrl/samsung/pinctrl-exynos.c weint_data[idx].bank = bank; bank 564 drivers/pinctrl/samsung/pinctrl-exynos.c bank = d->pin_banks; bank 566 drivers/pinctrl/samsung/pinctrl-exynos.c for (i = 0; i < d->nr_banks; ++i, ++bank) { bank 567 drivers/pinctrl/samsung/pinctrl-exynos.c if (bank->eint_type != EINT_TYPE_WKUP_MUX) bank 570 drivers/pinctrl/samsung/pinctrl-exynos.c muxed_data->banks[idx++] = bank; bank 600 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank) bank 602 drivers/pinctrl/samsung/pinctrl-exynos.c struct exynos_eint_gpio_save *save = bank->soc_priv; bank 603 drivers/pinctrl/samsung/pinctrl-exynos.c void __iomem *regs = bank->eint_base; bank 606 drivers/pinctrl/samsung/pinctrl-exynos.c + bank->eint_offset); bank 608 drivers/pinctrl/samsung/pinctrl-exynos.c + 2 * bank->eint_offset); bank 610 drivers/pinctrl/samsung/pinctrl-exynos.c + 2 * bank->eint_offset + 4); bank 612 drivers/pinctrl/samsung/pinctrl-exynos.c pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); bank 613 drivers/pinctrl/samsung/pinctrl-exynos.c pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); bank 614 drivers/pinctrl/samsung/pinctrl-exynos.c pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); bank 619 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank = drvdata->pin_banks; bank 623 drivers/pinctrl/samsung/pinctrl-exynos.c for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { bank 624 drivers/pinctrl/samsung/pinctrl-exynos.c if (bank->eint_type == EINT_TYPE_GPIO) bank 625 drivers/pinctrl/samsung/pinctrl-exynos.c exynos_pinctrl_suspend_bank(drvdata, bank); bank 626 drivers/pinctrl/samsung/pinctrl-exynos.c else if (bank->eint_type == EINT_TYPE_WKUP) { bank 628 drivers/pinctrl/samsung/pinctrl-exynos.c irq_chip = bank->irq_chip; bank 631 drivers/pinctrl/samsung/pinctrl-exynos.c } else if (bank->irq_chip != irq_chip) { bank 634 drivers/pinctrl/samsung/pinctrl-exynos.c bank->name); bank 642 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank) bank 644 drivers/pinctrl/samsung/pinctrl-exynos.c struct exynos_eint_gpio_save *save = bank->soc_priv; bank 645 drivers/pinctrl/samsung/pinctrl-exynos.c void __iomem *regs = bank->eint_base; bank 647 drivers/pinctrl/samsung/pinctrl-exynos.c pr_debug("%s: con %#010x => %#010x\n", bank->name, bank 649 drivers/pinctrl/samsung/pinctrl-exynos.c + bank->eint_offset), save->eint_con); bank 650 drivers/pinctrl/samsung/pinctrl-exynos.c pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, bank 652 drivers/pinctrl/samsung/pinctrl-exynos.c + 2 * bank->eint_offset), save->eint_fltcon0); bank 653 drivers/pinctrl/samsung/pinctrl-exynos.c pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, bank 655 drivers/pinctrl/samsung/pinctrl-exynos.c + 2 * bank->eint_offset + 4), save->eint_fltcon1); bank 658 drivers/pinctrl/samsung/pinctrl-exynos.c + bank->eint_offset); bank 660 drivers/pinctrl/samsung/pinctrl-exynos.c + 2 * bank->eint_offset); bank 662 drivers/pinctrl/samsung/pinctrl-exynos.c + 2 * bank->eint_offset + 4); bank 667 drivers/pinctrl/samsung/pinctrl-exynos.c struct samsung_pin_bank *bank = drvdata->pin_banks; bank 670 drivers/pinctrl/samsung/pinctrl-exynos.c for (i = 0; i < drvdata->nr_banks; ++i, ++bank) bank 671 drivers/pinctrl/samsung/pinctrl-exynos.c if (bank->eint_type == EINT_TYPE_GPIO) bank 672 drivers/pinctrl/samsung/pinctrl-exynos.c exynos_pinctrl_resume_bank(drvdata, bank); bank 119 drivers/pinctrl/samsung/pinctrl-exynos.h struct samsung_pin_bank *bank; bank 101 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank; bank 139 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank, int pin) bank 141 drivers/pinctrl/samsung/pinctrl-s3c24xx.c const struct samsung_pin_bank_type *bank_type = bank->type; bank 149 drivers/pinctrl/samsung/pinctrl-s3c24xx.c reg = d->virt_base + bank->pctl_offset; bank 153 drivers/pinctrl/samsung/pinctrl-s3c24xx.c spin_lock_irqsave(&bank->slock, flags); bank 157 drivers/pinctrl/samsung/pinctrl-s3c24xx.c val |= bank->eint_func << shift; bank 160 drivers/pinctrl/samsung/pinctrl-s3c24xx.c spin_unlock_irqrestore(&bank->slock, flags); bank 165 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); bank 166 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pinctrl_drv_data *d = bank->drvdata; bank 167 drivers/pinctrl/samsung/pinctrl-s3c24xx.c int index = bank->eint_offset + data->hwirq; bank 190 drivers/pinctrl/samsung/pinctrl-s3c24xx.c s3c24xx_eint_set_function(d, bank, data->hwirq); bank 199 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); bank 200 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; bank 210 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); bank 211 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; bank 221 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); bank 222 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; bank 256 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); bank 257 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pinctrl_drv_data *d = bank->drvdata; bank 265 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); bank 266 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pinctrl_drv_data *d = bank->drvdata; bank 276 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); bank 277 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pinctrl_drv_data *d = bank->drvdata; bank 316 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); bank 317 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pinctrl_drv_data *d = bank->drvdata; bank 318 drivers/pinctrl/samsung/pinctrl-s3c24xx.c unsigned char index = bank->eint_offset + data->hwirq; bank 325 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); bank 326 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pinctrl_drv_data *d = bank->drvdata; bank 327 drivers/pinctrl/samsung/pinctrl-s3c24xx.c unsigned char index = bank->eint_offset + data->hwirq; bank 337 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); bank 338 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pinctrl_drv_data *d = bank->drvdata; bank 339 drivers/pinctrl/samsung/pinctrl-s3c24xx.c unsigned char index = bank->eint_offset + data->hwirq; bank 418 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = ddata->bank; bank 420 drivers/pinctrl/samsung/pinctrl-s3c24xx.c if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) bank 434 drivers/pinctrl/samsung/pinctrl-s3c24xx.c irq_set_chip_data(virq, bank); bank 447 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank = ddata->bank; bank 449 drivers/pinctrl/samsung/pinctrl-s3c24xx.c if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) bank 453 drivers/pinctrl/samsung/pinctrl-s3c24xx.c irq_set_chip_data(virq, bank); bank 474 drivers/pinctrl/samsung/pinctrl-s3c24xx.c struct samsung_pin_bank *bank; bank 517 drivers/pinctrl/samsung/pinctrl-s3c24xx.c bank = d->pin_banks; bank 518 drivers/pinctrl/samsung/pinctrl-s3c24xx.c for (i = 0; i < d->nr_banks; ++i, ++bank) { bank 524 drivers/pinctrl/samsung/pinctrl-s3c24xx.c if (bank->eint_type != EINT_TYPE_WKUP) bank 531 drivers/pinctrl/samsung/pinctrl-s3c24xx.c ddata->bank = bank; bank 535 drivers/pinctrl/samsung/pinctrl-s3c24xx.c ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops bank 538 drivers/pinctrl/samsung/pinctrl-s3c24xx.c bank->irq_domain = irq_domain_add_linear(bank->of_node, bank 539 drivers/pinctrl/samsung/pinctrl-s3c24xx.c bank->nr_pins, ops, ddata); bank 540 drivers/pinctrl/samsung/pinctrl-s3c24xx.c if (!bank->irq_domain) { bank 545 drivers/pinctrl/samsung/pinctrl-s3c24xx.c irq = bank->eint_offset; bank 546 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask = bank->eint_mask; bank 552 drivers/pinctrl/samsung/pinctrl-s3c24xx.c eint_data->domains[irq] = bank->irq_domain; bank 213 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pin_bank *bank; bank 268 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pin_bank *bank, int pin) bank 270 drivers/pinctrl/samsung/pinctrl-s3c64xx.c const struct samsung_pin_bank_type *bank_type = bank->type; bank 278 drivers/pinctrl/samsung/pinctrl-s3c64xx.c reg = d->virt_base + bank->pctl_offset; bank 289 drivers/pinctrl/samsung/pinctrl-s3c64xx.c spin_lock_irqsave(&bank->slock, flags); bank 293 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val |= bank->eint_func << shift; bank 296 drivers/pinctrl/samsung/pinctrl-s3c64xx.c spin_unlock_irqrestore(&bank->slock, flags); bank 305 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); bank 306 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pinctrl_drv_data *d = bank->drvdata; bank 307 drivers/pinctrl/samsung/pinctrl-s3c64xx.c unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; bank 308 drivers/pinctrl/samsung/pinctrl-s3c64xx.c void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset); bank 331 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); bank 332 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pinctrl_drv_data *d = bank->drvdata; bank 333 drivers/pinctrl/samsung/pinctrl-s3c64xx.c unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; bank 334 drivers/pinctrl/samsung/pinctrl-s3c64xx.c void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset); bank 341 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); bank 342 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pinctrl_drv_data *d = bank->drvdata; bank 357 drivers/pinctrl/samsung/pinctrl-s3c64xx.c reg = d->virt_base + EINTCON_REG(bank->eint_offset); bank 358 drivers/pinctrl/samsung/pinctrl-s3c64xx.c shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq; bank 366 drivers/pinctrl/samsung/pinctrl-s3c64xx.c s3c64xx_irq_set_function(d, bank, irqd->hwirq); bank 385 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pin_bank *bank = h->host_data; bank 387 drivers/pinctrl/samsung/pinctrl-s3c64xx.c if (!(bank->eint_mask & (1 << hw))) bank 392 drivers/pinctrl/samsung/pinctrl-s3c64xx.c irq_set_chip_data(virq, bank); bank 454 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pin_bank *bank; bank 465 drivers/pinctrl/samsung/pinctrl-s3c64xx.c bank = d->pin_banks; bank 466 drivers/pinctrl/samsung/pinctrl-s3c64xx.c for (i = 0; i < d->nr_banks; ++i, ++bank) { bank 470 drivers/pinctrl/samsung/pinctrl-s3c64xx.c if (bank->eint_type != EINT_TYPE_GPIO) bank 473 drivers/pinctrl/samsung/pinctrl-s3c64xx.c mask = bank->eint_mask; bank 476 drivers/pinctrl/samsung/pinctrl-s3c64xx.c bank->irq_domain = irq_domain_add_linear(bank->of_node, bank 477 drivers/pinctrl/samsung/pinctrl-s3c64xx.c nr_eints, &s3c64xx_gpio_irqd_ops, bank); bank 478 drivers/pinctrl/samsung/pinctrl-s3c64xx.c if (!bank->irq_domain) { bank 492 drivers/pinctrl/samsung/pinctrl-s3c64xx.c bank = d->pin_banks; bank 494 drivers/pinctrl/samsung/pinctrl-s3c64xx.c for (i = 0; i < d->nr_banks; ++i, ++bank) { bank 495 drivers/pinctrl/samsung/pinctrl-s3c64xx.c if (bank->eint_type != EINT_TYPE_GPIO) bank 498 drivers/pinctrl/samsung/pinctrl-s3c64xx.c data->domains[nr_domains++] = bank->irq_domain; bank 514 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata; bank 539 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata; bank 549 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pin_bank *bank = ddata->bank; bank 550 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pinctrl_drv_data *d = bank->drvdata; bank 578 drivers/pinctrl/samsung/pinctrl-s3c64xx.c s3c64xx_irq_set_function(d, bank, irqd->hwirq); bank 658 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pin_bank *bank = ddata->bank; bank 660 drivers/pinctrl/samsung/pinctrl-s3c64xx.c if (!(bank->eint_mask & (1 << hw))) bank 693 drivers/pinctrl/samsung/pinctrl-s3c64xx.c struct samsung_pin_bank *bank; bank 729 drivers/pinctrl/samsung/pinctrl-s3c64xx.c bank = d->pin_banks; bank 730 drivers/pinctrl/samsung/pinctrl-s3c64xx.c for (i = 0; i < d->nr_banks; ++i, ++bank) { bank 737 drivers/pinctrl/samsung/pinctrl-s3c64xx.c if (bank->eint_type != EINT_TYPE_WKUP) bank 740 drivers/pinctrl/samsung/pinctrl-s3c64xx.c mask = bank->eint_mask; bank 747 drivers/pinctrl/samsung/pinctrl-s3c64xx.c ddata->bank = bank; bank 749 drivers/pinctrl/samsung/pinctrl-s3c64xx.c bank->irq_domain = irq_domain_add_linear(bank->of_node, bank 751 drivers/pinctrl/samsung/pinctrl-s3c64xx.c if (!bank->irq_domain) { bank 756 drivers/pinctrl/samsung/pinctrl-s3c64xx.c irq = bank->eint_offset; bank 757 drivers/pinctrl/samsung/pinctrl-s3c64xx.c mask = bank->eint_mask; bank 761 drivers/pinctrl/samsung/pinctrl-s3c64xx.c data->domains[irq] = bank->irq_domain; bank 359 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank **bank) bank 371 drivers/pinctrl/samsung/pinctrl-samsung.c if (bank) bank 372 drivers/pinctrl/samsung/pinctrl-samsung.c *bank = b; bank 381 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank; bank 393 drivers/pinctrl/samsung/pinctrl-samsung.c ®, &pin_offset, &bank); bank 394 drivers/pinctrl/samsung/pinctrl-samsung.c type = bank->type; bank 403 drivers/pinctrl/samsung/pinctrl-samsung.c spin_lock_irqsave(&bank->slock, flags); bank 410 drivers/pinctrl/samsung/pinctrl-samsung.c spin_unlock_irqrestore(&bank->slock, flags); bank 436 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank; bank 445 drivers/pinctrl/samsung/pinctrl-samsung.c &pin_offset, &bank); bank 446 drivers/pinctrl/samsung/pinctrl-samsung.c type = bank->type; bank 454 drivers/pinctrl/samsung/pinctrl-samsung.c spin_lock_irqsave(&bank->slock, flags); bank 471 drivers/pinctrl/samsung/pinctrl-samsung.c spin_unlock_irqrestore(&bank->slock, flags); bank 544 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank = gpiochip_get_data(gc); bank 545 drivers/pinctrl/samsung/pinctrl-samsung.c const struct samsung_pin_bank_type *type = bank->type; bank 549 drivers/pinctrl/samsung/pinctrl-samsung.c reg = bank->pctl_base + bank->pctl_offset; bank 561 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank = gpiochip_get_data(gc); bank 564 drivers/pinctrl/samsung/pinctrl-samsung.c spin_lock_irqsave(&bank->slock, flags); bank 566 drivers/pinctrl/samsung/pinctrl-samsung.c spin_unlock_irqrestore(&bank->slock, flags); bank 574 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank = gpiochip_get_data(gc); bank 575 drivers/pinctrl/samsung/pinctrl-samsung.c const struct samsung_pin_bank_type *type = bank->type; bank 577 drivers/pinctrl/samsung/pinctrl-samsung.c reg = bank->pctl_base + bank->pctl_offset; bank 595 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank; bank 599 drivers/pinctrl/samsung/pinctrl-samsung.c bank = gpiochip_get_data(gc); bank 600 drivers/pinctrl/samsung/pinctrl-samsung.c type = bank->type; bank 602 drivers/pinctrl/samsung/pinctrl-samsung.c reg = bank->pctl_base + bank->pctl_offset bank 625 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank = gpiochip_get_data(gc); bank 629 drivers/pinctrl/samsung/pinctrl-samsung.c spin_lock_irqsave(&bank->slock, flags); bank 631 drivers/pinctrl/samsung/pinctrl-samsung.c spin_unlock_irqrestore(&bank->slock, flags); bank 639 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank = gpiochip_get_data(gc); bank 643 drivers/pinctrl/samsung/pinctrl-samsung.c spin_lock_irqsave(&bank->slock, flags); bank 646 drivers/pinctrl/samsung/pinctrl-samsung.c spin_unlock_irqrestore(&bank->slock, flags); bank 657 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank = gpiochip_get_data(gc); bank 660 drivers/pinctrl/samsung/pinctrl-samsung.c if (!bank->irq_domain) bank 663 drivers/pinctrl/samsung/pinctrl-samsung.c virq = irq_create_mapping(bank->irq_domain, offset); bank 861 drivers/pinctrl/samsung/pinctrl-samsung.c int pin, bank, ret; bank 893 drivers/pinctrl/samsung/pinctrl-samsung.c for (bank = 0; bank < drvdata->nr_banks; bank++) { bank 894 drivers/pinctrl/samsung/pinctrl-samsung.c pin_bank = &drvdata->pin_banks[bank]; bank 914 drivers/pinctrl/samsung/pinctrl-samsung.c for (bank = 0; bank < drvdata->nr_banks; ++bank) { bank 915 drivers/pinctrl/samsung/pinctrl-samsung.c pin_bank = &drvdata->pin_banks[bank]; bank 917 drivers/pinctrl/samsung/pinctrl-samsung.c pin_bank->grange.id = bank; bank 933 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank = drvdata->pin_banks; bank 936 drivers/pinctrl/samsung/pinctrl-samsung.c for (i = 0; i < drvdata->nr_banks; ++i, ++bank) bank 937 drivers/pinctrl/samsung/pinctrl-samsung.c pinctrl_remove_gpio_range(drvdata->pctl_dev, &bank->grange); bank 957 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank = drvdata->pin_banks; bank 962 drivers/pinctrl/samsung/pinctrl-samsung.c for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { bank 963 drivers/pinctrl/samsung/pinctrl-samsung.c bank->gpio_chip = samsung_gpiolib_chip; bank 965 drivers/pinctrl/samsung/pinctrl-samsung.c gc = &bank->gpio_chip; bank 966 drivers/pinctrl/samsung/pinctrl-samsung.c gc->base = bank->grange.base; bank 967 drivers/pinctrl/samsung/pinctrl-samsung.c gc->ngpio = bank->nr_pins; bank 969 drivers/pinctrl/samsung/pinctrl-samsung.c gc->of_node = bank->of_node; bank 970 drivers/pinctrl/samsung/pinctrl-samsung.c gc->label = bank->name; bank 972 drivers/pinctrl/samsung/pinctrl-samsung.c ret = devm_gpiochip_add_data(&pdev->dev, gc, bank); bank 1014 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank; bank 1048 drivers/pinctrl/samsung/pinctrl-samsung.c bank = d->pin_banks; bank 1050 drivers/pinctrl/samsung/pinctrl-samsung.c for (i = 0; i < ctrl->nr_banks; ++i, ++bdata, ++bank) { bank 1051 drivers/pinctrl/samsung/pinctrl-samsung.c bank->type = bdata->type; bank 1052 drivers/pinctrl/samsung/pinctrl-samsung.c bank->pctl_offset = bdata->pctl_offset; bank 1053 drivers/pinctrl/samsung/pinctrl-samsung.c bank->nr_pins = bdata->nr_pins; bank 1054 drivers/pinctrl/samsung/pinctrl-samsung.c bank->eint_func = bdata->eint_func; bank 1055 drivers/pinctrl/samsung/pinctrl-samsung.c bank->eint_type = bdata->eint_type; bank 1056 drivers/pinctrl/samsung/pinctrl-samsung.c bank->eint_mask = bdata->eint_mask; bank 1057 drivers/pinctrl/samsung/pinctrl-samsung.c bank->eint_offset = bdata->eint_offset; bank 1058 drivers/pinctrl/samsung/pinctrl-samsung.c bank->name = bdata->name; bank 1060 drivers/pinctrl/samsung/pinctrl-samsung.c spin_lock_init(&bank->slock); bank 1061 drivers/pinctrl/samsung/pinctrl-samsung.c bank->drvdata = d; bank 1062 drivers/pinctrl/samsung/pinctrl-samsung.c bank->pin_base = d->nr_pins; bank 1063 drivers/pinctrl/samsung/pinctrl-samsung.c d->nr_pins += bank->nr_pins; bank 1065 drivers/pinctrl/samsung/pinctrl-samsung.c bank->eint_base = virt_base[0]; bank 1066 drivers/pinctrl/samsung/pinctrl-samsung.c bank->pctl_base = virt_base[bdata->pctl_res_idx]; bank 1078 drivers/pinctrl/samsung/pinctrl-samsung.c bank = d->pin_banks; bank 1079 drivers/pinctrl/samsung/pinctrl-samsung.c for (i = 0; i < d->nr_banks; ++i, ++bank) { bank 1080 drivers/pinctrl/samsung/pinctrl-samsung.c if (of_node_name_eq(np, bank->name)) { bank 1081 drivers/pinctrl/samsung/pinctrl-samsung.c bank->of_node = np; bank 1154 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; bank 1155 drivers/pinctrl/samsung/pinctrl-samsung.c void __iomem *reg = bank->pctl_base + bank->pctl_offset; bank 1156 drivers/pinctrl/samsung/pinctrl-samsung.c const u8 *offs = bank->type->reg_offset; bank 1157 drivers/pinctrl/samsung/pinctrl-samsung.c const u8 *widths = bank->type->fld_width; bank 1166 drivers/pinctrl/samsung/pinctrl-samsung.c bank->pm_save[type] = readl(reg + offs[type]); bank 1168 drivers/pinctrl/samsung/pinctrl-samsung.c if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { bank 1170 drivers/pinctrl/samsung/pinctrl-samsung.c bank->pm_save[PINCFG_TYPE_NUM] = bank 1173 drivers/pinctrl/samsung/pinctrl-samsung.c bank->name, reg, bank 1174 drivers/pinctrl/samsung/pinctrl-samsung.c bank->pm_save[PINCFG_TYPE_FUNC], bank 1175 drivers/pinctrl/samsung/pinctrl-samsung.c bank->pm_save[PINCFG_TYPE_NUM]); bank 1177 drivers/pinctrl/samsung/pinctrl-samsung.c pr_debug("Save %s @ %p (con %#010x)\n", bank->name, bank 1178 drivers/pinctrl/samsung/pinctrl-samsung.c reg, bank->pm_save[PINCFG_TYPE_FUNC]); bank 1207 drivers/pinctrl/samsung/pinctrl-samsung.c struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; bank 1208 drivers/pinctrl/samsung/pinctrl-samsung.c void __iomem *reg = bank->pctl_base + bank->pctl_offset; bank 1209 drivers/pinctrl/samsung/pinctrl-samsung.c const u8 *offs = bank->type->reg_offset; bank 1210 drivers/pinctrl/samsung/pinctrl-samsung.c const u8 *widths = bank->type->fld_width; bank 1217 drivers/pinctrl/samsung/pinctrl-samsung.c if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) { bank 1220 drivers/pinctrl/samsung/pinctrl-samsung.c bank->name, reg, bank 1223 drivers/pinctrl/samsung/pinctrl-samsung.c bank->pm_save[PINCFG_TYPE_FUNC], bank 1224 drivers/pinctrl/samsung/pinctrl-samsung.c bank->pm_save[PINCFG_TYPE_NUM]); bank 1225 drivers/pinctrl/samsung/pinctrl-samsung.c writel(bank->pm_save[PINCFG_TYPE_NUM], bank 1228 drivers/pinctrl/samsung/pinctrl-samsung.c pr_debug("%s @ %p (con %#010x => %#010x)\n", bank->name, bank 1230 drivers/pinctrl/samsung/pinctrl-samsung.c bank->pm_save[PINCFG_TYPE_FUNC]); bank 1234 drivers/pinctrl/samsung/pinctrl-samsung.c writel(bank->pm_save[type], reg + offs[type]); bank 22 drivers/pinctrl/sh-pfc/pfc-r8a7778.c #define PORT_GP_PUP_1(bank, pin, fn, sfx) \ bank 23 drivers/pinctrl/sh-pfc/pfc-r8a7778.c PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) bank 23 drivers/pinctrl/sh-pfc/pfc-sh7734.c #define _GP_DATA(bank, pin, name, sfx, cfg) \ bank 26 drivers/pinctrl/sh-pfc/pfc-sh7734.c #define _GP_INOUTSEL(bank, pin, name, sfx, cfg) name##_IN, name##_OUT bank 27 drivers/pinctrl/sh-pfc/pfc-sh7734.c #define _GP_INDT(bank, pin, name, sfx, cfg) name##_DATA bank 28 drivers/pinctrl/sh-pfc/pfc-sh7734.c #define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused) bank 29 drivers/pinctrl/sh-pfc/pfc-sh7734.c #define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused) bank 444 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ bank 445 drivers/pinctrl/sh-pfc/sh_pfc.h fn(bank, pin, GP_##bank##_##pin, sfx, cfg) bank 446 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) bank 448 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ bank 449 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \ bank 450 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ bank 451 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ bank 452 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) bank 453 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) bank 455 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ bank 456 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_4(bank, fn, sfx, cfg), \ bank 457 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ bank 458 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 5, fn, sfx, cfg) bank 459 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0) bank 461 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ bank 462 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_6(bank, fn, sfx, cfg), \ bank 463 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ bank 464 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) bank 465 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) bank 467 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ bank 468 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_8(bank, fn, sfx, cfg), \ bank 469 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) bank 470 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) bank 472 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \ bank 473 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_9(bank, fn, sfx, cfg), \ bank 474 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 9, fn, sfx, cfg) bank 475 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0) bank 477 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \ bank 478 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_10(bank, fn, sfx, cfg), \ bank 479 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 10, fn, sfx, cfg) bank 480 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0) bank 482 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ bank 483 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_11(bank, fn, sfx, cfg), \ bank 484 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) bank 485 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) bank 487 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ bank 488 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_12(bank, fn, sfx, cfg), \ bank 489 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \ bank 490 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) bank 491 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) bank 493 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ bank 494 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_14(bank, fn, sfx, cfg), \ bank 495 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 14, fn, sfx, cfg) bank 496 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0) bank 498 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ bank 499 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_15(bank, fn, sfx, cfg), \ bank 500 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) bank 501 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) bank 503 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \ bank 504 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_16(bank, fn, sfx, cfg), \ bank 505 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 16, fn, sfx, cfg) bank 506 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0) bank 508 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ bank 509 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_17(bank, fn, sfx, cfg), \ bank 510 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) bank 511 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) bank 513 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ bank 514 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_18(bank, fn, sfx, cfg), \ bank 515 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ bank 516 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 19, fn, sfx, cfg) bank 517 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0) bank 519 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \ bank 520 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_20(bank, fn, sfx, cfg), \ bank 521 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 20, fn, sfx, cfg) bank 522 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0) bank 524 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \ bank 525 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_21(bank, fn, sfx, cfg), \ bank 526 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 21, fn, sfx, cfg) bank 527 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0) bank 529 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ bank 530 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_22(bank, fn, sfx, cfg), \ bank 531 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) bank 532 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) bank 534 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \ bank 535 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_23(bank, fn, sfx, cfg), \ bank 536 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 23, fn, sfx, cfg) bank 537 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0) bank 539 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \ bank 540 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_24(bank, fn, sfx, cfg), \ bank 541 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 24, fn, sfx, cfg) bank 542 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0) bank 544 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ bank 545 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_25(bank, fn, sfx, cfg), \ bank 546 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) bank 547 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) bank 549 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_27(bank, fn, sfx, cfg) \ bank 550 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_26(bank, fn, sfx, cfg), \ bank 551 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 26, fn, sfx, cfg) bank 552 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0) bank 554 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ bank 555 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_27(bank, fn, sfx, cfg), \ bank 556 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) bank 557 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) bank 559 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \ bank 560 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_28(bank, fn, sfx, cfg), \ bank 561 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 28, fn, sfx, cfg) bank 562 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0) bank 564 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ bank 565 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_29(bank, fn, sfx, cfg), \ bank 566 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) bank 567 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) bank 569 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ bank 570 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_30(bank, fn, sfx, cfg), \ bank 571 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \ bank 572 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) bank 573 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) bank 575 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORT_GP_32_REV(bank, fn, sfx) \ bank 576 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ bank 577 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ bank 578 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ bank 579 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ bank 580 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ bank 581 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ bank 582 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ bank 583 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ bank 584 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ bank 585 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ bank 586 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ bank 587 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ bank 588 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ bank 589 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ bank 590 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ bank 591 drivers/pinctrl/sh-pfc/sh_pfc.h PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) bank 594 drivers/pinctrl/sh-pfc/sh_pfc.h #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx bank 598 drivers/pinctrl/sh-pfc/sh_pfc.h #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ bank 600 drivers/pinctrl/sh-pfc/sh_pfc.h .pin = (bank * 32) + _pin, \ bank 608 drivers/pinctrl/sh-pfc/sh_pfc.h #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) bank 620 drivers/pinctrl/sh-pfc/sh_pfc.h #define _GP_ENTRY(bank, pin, name, sfx, cfg) \ bank 621 drivers/pinctrl/sh-pfc/sh_pfc.h deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated bank 750 drivers/pinctrl/sh-pfc/sh_pfc.h #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) bank 236 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 bank; bank 247 drivers/pinctrl/sirf/pinctrl-atlas7.c .bank = b, \ bank 5004 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 bank, u32 ad_sel) bank 5010 drivers/pinctrl/sirf/pinctrl-atlas7.c pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg)); bank 5013 drivers/pinctrl/sirf/pinctrl-atlas7.c regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); bank 5016 drivers/pinctrl/sirf/pinctrl-atlas7.c pmx->regs[bank] + conf->ad_ctrl_reg); bank 5018 drivers/pinctrl/sirf/pinctrl-atlas7.c regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); bank 5020 drivers/pinctrl/sirf/pinctrl-atlas7.c bank, conf->ad_ctrl_reg, regv); bank 5025 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_pad_config *conf, u32 bank) bank 5031 drivers/pinctrl/sirf/pinctrl-atlas7.c return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0); bank 5035 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_pad_config *conf, u32 bank) bank 5041 drivers/pinctrl/sirf/pinctrl-atlas7.c return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1); bank 5048 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 bank; bank 5057 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_pin_to_bank(pin); bank 5061 drivers/pinctrl/sirf/pinctrl-atlas7.c ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank); bank 5070 drivers/pinctrl/sirf/pinctrl-atlas7.c ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank); bank 5080 drivers/pinctrl/sirf/pinctrl-atlas7.c pmx->regs[bank] + CLR_REG(conf->mux_reg)); bank 5083 drivers/pinctrl/sirf/pinctrl-atlas7.c regv = readl(pmx->regs[bank] + conf->mux_reg); bank 5086 drivers/pinctrl/sirf/pinctrl-atlas7.c pmx->regs[bank] + conf->mux_reg); bank 5088 drivers/pinctrl/sirf/pinctrl-atlas7.c regv = readl(pmx->regs[bank] + conf->mux_reg); bank 5090 drivers/pinctrl/sirf/pinctrl-atlas7.c bank, conf->mux_reg, regv); bank 5167 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 bank; bank 5171 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_pin_to_bank(pin); bank 5173 drivers/pinctrl/sirf/pinctrl-atlas7.c pull_sel_reg = pmx->regs[bank] + conf->pupd_reg; bank 5193 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 bank; bank 5200 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_pin_to_bank(pin); bank 5201 drivers/pinctrl/sirf/pinctrl-atlas7.c ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg; bank 5485 drivers/pinctrl/sirf/pinctrl-atlas7.c u32 bank; bank 5491 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_pin_to_bank(idx); bank 5495 drivers/pinctrl/sirf/pinctrl-atlas7.c regv = readl(pmx->regs[bank] + conf->mux_reg); bank 5502 drivers/pinctrl/sirf/pinctrl-atlas7.c regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); bank 5512 drivers/pinctrl/sirf/pinctrl-atlas7.c regv = readl(pmx->regs[bank] + conf->drvstr_reg); bank 5518 drivers/pinctrl/sirf/pinctrl-atlas7.c regv = readl(pmx->regs[bank] + conf->pupd_reg); bank 5623 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 5626 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_gpio_to_bank(a7gc, gpio); bank 5627 drivers/pinctrl/sirf/pinctrl-atlas7.c ofs = gpio - bank->gpio_offset; bank 5628 drivers/pinctrl/sirf/pinctrl-atlas7.c if (ofs >= bank->ngpio) bank 5631 drivers/pinctrl/sirf/pinctrl-atlas7.c return bank->gpio_pins[ofs]; bank 5638 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 5643 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_gpio_to_bank(a7gc, d->hwirq); bank 5644 drivers/pinctrl/sirf/pinctrl-atlas7.c pin_in_bank = d->hwirq - bank->gpio_offset; bank 5645 drivers/pinctrl/sirf/pinctrl-atlas7.c ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); bank 5658 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 5662 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_gpio_to_bank(a7gc, idx); bank 5663 drivers/pinctrl/sirf/pinctrl-atlas7.c pin_in_bank = idx - bank->gpio_offset; bank 5664 drivers/pinctrl/sirf/pinctrl-atlas7.c ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); bank 5689 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 5694 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_gpio_to_bank(a7gc, d->hwirq); bank 5695 drivers/pinctrl/sirf/pinctrl-atlas7.c pin_in_bank = d->hwirq - bank->gpio_offset; bank 5696 drivers/pinctrl/sirf/pinctrl-atlas7.c ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); bank 5713 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 5718 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_gpio_to_bank(a7gc, d->hwirq); bank 5719 drivers/pinctrl/sirf/pinctrl-atlas7.c pin_in_bank = d->hwirq - bank->gpio_offset; bank 5720 drivers/pinctrl/sirf/pinctrl-atlas7.c ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); bank 5782 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank = NULL; bank 5789 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = &a7gc->banks[idx]; bank 5790 drivers/pinctrl/sirf/pinctrl-atlas7.c if (bank->irq == irq) bank 5797 drivers/pinctrl/sirf/pinctrl-atlas7.c status = readl(ATLAS7_GPIO_INT_STATUS(bank)); bank 5806 drivers/pinctrl/sirf/pinctrl-atlas7.c ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank)); bank 5815 drivers/pinctrl/sirf/pinctrl-atlas7.c bank->gpio_offset + pin_in_bank); bank 5818 drivers/pinctrl/sirf/pinctrl-atlas7.c bank->gpio_offset + pin_in_bank)); bank 5821 drivers/pinctrl/sirf/pinctrl-atlas7.c if (++pin_in_bank >= bank->ngpio) bank 5833 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 5837 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_gpio_to_bank(a7gc, gpio); bank 5838 drivers/pinctrl/sirf/pinctrl-atlas7.c pin_in_bank = gpio - bank->gpio_offset; bank 5839 drivers/pinctrl/sirf/pinctrl-atlas7.c ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); bank 5908 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 5912 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_gpio_to_bank(a7gc, gpio); bank 5913 drivers/pinctrl/sirf/pinctrl-atlas7.c pin_in_bank = gpio - bank->gpio_offset; bank 5914 drivers/pinctrl/sirf/pinctrl-atlas7.c ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); bank 5946 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 5950 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_gpio_to_bank(a7gc, gpio); bank 5951 drivers/pinctrl/sirf/pinctrl-atlas7.c pin_in_bank = gpio - bank->gpio_offset; bank 5955 drivers/pinctrl/sirf/pinctrl-atlas7.c val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank)); bank 5966 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 5971 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = atlas7_gpio_to_bank(a7gc, gpio); bank 5972 drivers/pinctrl/sirf/pinctrl-atlas7.c pin_in_bank = gpio - bank->gpio_offset; bank 5973 drivers/pinctrl/sirf/pinctrl-atlas7.c ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); bank 6070 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 6072 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = &a7gc->banks[idx]; bank 6074 drivers/pinctrl/sirf/pinctrl-atlas7.c bank->base = ATLAS7_GPIO_BASE(a7gc, idx); bank 6075 drivers/pinctrl/sirf/pinctrl-atlas7.c bank->gpio_offset = idx * NGPIO_OF_BANK; bank 6086 drivers/pinctrl/sirf/pinctrl-atlas7.c bank->irq = ret; bank 6089 drivers/pinctrl/sirf/pinctrl-atlas7.c bank->irq, atlas7_gpio_handle_irq); bank 6103 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 6108 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = &a7gc->banks[idx]; bank 6109 drivers/pinctrl/sirf/pinctrl-atlas7.c for (pin = 0; pin < bank->ngpio; pin++) { bank 6110 drivers/pinctrl/sirf/pinctrl-atlas7.c ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin); bank 6111 drivers/pinctrl/sirf/pinctrl-atlas7.c bank->sleep_data[pin] = readl(ctrl_reg); bank 6121 drivers/pinctrl/sirf/pinctrl-atlas7.c struct atlas7_gpio_bank *bank; bank 6126 drivers/pinctrl/sirf/pinctrl-atlas7.c bank = &a7gc->banks[idx]; bank 6127 drivers/pinctrl/sirf/pinctrl-atlas7.c for (pin = 0; pin < bank->ngpio; pin++) { bank 6128 drivers/pinctrl/sirf/pinctrl-atlas7.c ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin); bank 6129 drivers/pinctrl/sirf/pinctrl-atlas7.c writel(bank->sleep_data[pin], ctrl_reg); bank 424 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); bank 429 drivers/pinctrl/sirf/pinctrl-sirf.c offset = SIRFSOC_GPIO_CTRL(bank->id, idx); bank 441 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank, bank 447 drivers/pinctrl/sirf/pinctrl-sirf.c offset = SIRFSOC_GPIO_CTRL(bank->id, idx); bank 463 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); bank 465 drivers/pinctrl/sirf/pinctrl-sirf.c __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); bank 472 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); bank 477 drivers/pinctrl/sirf/pinctrl-sirf.c offset = SIRFSOC_GPIO_CTRL(bank->id, idx); bank 493 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); bank 498 drivers/pinctrl/sirf/pinctrl-sirf.c offset = SIRFSOC_GPIO_CTRL(bank->id, idx); bank 555 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank; bank 562 drivers/pinctrl/sirf/pinctrl-sirf.c bank = &sgpio->sgpio_bank[i]; bank 563 drivers/pinctrl/sirf/pinctrl-sirf.c if (bank->parent_irq == irq) bank 570 drivers/pinctrl/sirf/pinctrl-sirf.c status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); bank 574 drivers/pinctrl/sirf/pinctrl-sirf.c __func__, bank->id, status); bank 580 drivers/pinctrl/sirf/pinctrl-sirf.c ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); bank 588 drivers/pinctrl/sirf/pinctrl-sirf.c __func__, bank->id, idx); bank 590 drivers/pinctrl/sirf/pinctrl-sirf.c bank->id * SIRFSOC_GPIO_BANK_SIZE)); bank 613 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); bank 619 drivers/pinctrl/sirf/pinctrl-sirf.c spin_lock_irqsave(&bank->lock, flags); bank 625 drivers/pinctrl/sirf/pinctrl-sirf.c sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); bank 626 drivers/pinctrl/sirf/pinctrl-sirf.c __sirfsoc_gpio_irq_mask(sgpio, bank, offset); bank 628 drivers/pinctrl/sirf/pinctrl-sirf.c spin_unlock_irqrestore(&bank->lock, flags); bank 636 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); bank 639 drivers/pinctrl/sirf/pinctrl-sirf.c spin_lock_irqsave(&bank->lock, flags); bank 641 drivers/pinctrl/sirf/pinctrl-sirf.c __sirfsoc_gpio_irq_mask(sgpio, bank, offset); bank 642 drivers/pinctrl/sirf/pinctrl-sirf.c sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); bank 644 drivers/pinctrl/sirf/pinctrl-sirf.c spin_unlock_irqrestore(&bank->lock, flags); bank 652 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); bank 657 drivers/pinctrl/sirf/pinctrl-sirf.c offset = SIRFSOC_GPIO_CTRL(bank->id, idx); bank 659 drivers/pinctrl/sirf/pinctrl-sirf.c spin_lock_irqsave(&bank->lock, flags); bank 663 drivers/pinctrl/sirf/pinctrl-sirf.c spin_unlock_irqrestore(&bank->lock, flags); bank 669 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank, bank 676 drivers/pinctrl/sirf/pinctrl-sirf.c spin_lock_irqsave(&bank->lock, flags); bank 688 drivers/pinctrl/sirf/pinctrl-sirf.c spin_unlock_irqrestore(&bank->lock, flags); bank 695 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); bank 700 drivers/pinctrl/sirf/pinctrl-sirf.c offset = SIRFSOC_GPIO_CTRL(bank->id, idx); bank 704 drivers/pinctrl/sirf/pinctrl-sirf.c sirfsoc_gpio_set_output(sgpio, bank, offset, value); bank 714 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); bank 718 drivers/pinctrl/sirf/pinctrl-sirf.c spin_lock_irqsave(&bank->lock, flags); bank 720 drivers/pinctrl/sirf/pinctrl-sirf.c val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); bank 722 drivers/pinctrl/sirf/pinctrl-sirf.c spin_unlock_irqrestore(&bank->lock, flags); bank 731 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); bank 735 drivers/pinctrl/sirf/pinctrl-sirf.c spin_lock_irqsave(&bank->lock, flags); bank 737 drivers/pinctrl/sirf/pinctrl-sirf.c ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); bank 742 drivers/pinctrl/sirf/pinctrl-sirf.c writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); bank 744 drivers/pinctrl/sirf/pinctrl-sirf.c spin_unlock_irqrestore(&bank->lock, flags); bank 785 drivers/pinctrl/sirf/pinctrl-sirf.c struct sirfsoc_gpio_bank *bank; bank 837 drivers/pinctrl/sirf/pinctrl-sirf.c bank = &sgpio->sgpio_bank[i]; bank 838 drivers/pinctrl/sirf/pinctrl-sirf.c spin_lock_init(&bank->lock); bank 839 drivers/pinctrl/sirf/pinctrl-sirf.c bank->parent_irq = platform_get_irq(pdev, i); bank 840 drivers/pinctrl/sirf/pinctrl-sirf.c if (bank->parent_irq < 0) { bank 841 drivers/pinctrl/sirf/pinctrl-sirf.c err = bank->parent_irq; bank 847 drivers/pinctrl/sirf/pinctrl-sirf.c bank->parent_irq, bank 35 drivers/pinctrl/sirf/pinctrl-sirf.h #define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index)) bank 151 drivers/pinctrl/stm32/pinctrl-stm32.c static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, bank 154 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); bank 155 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; bank 158 drivers/pinctrl/stm32/pinctrl-stm32.c static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, bank 161 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | bank 163 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; bank 164 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; bank 167 drivers/pinctrl/stm32/pinctrl-stm32.c static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, bank 170 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); bank 171 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; bank 174 drivers/pinctrl/stm32/pinctrl-stm32.c static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, bank 177 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; bank 178 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; bank 181 drivers/pinctrl/stm32/pinctrl-stm32.c static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, bank 184 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; bank 185 drivers/pinctrl/stm32/pinctrl-stm32.c bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; bank 190 drivers/pinctrl/stm32/pinctrl-stm32.c static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, bank 193 drivers/pinctrl/stm32/pinctrl-stm32.c stm32_gpio_backup_value(bank, offset, value); bank 198 drivers/pinctrl/stm32/pinctrl-stm32.c clk_enable(bank->clk); bank 200 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); bank 202 drivers/pinctrl/stm32/pinctrl-stm32.c clk_disable(bank->clk); bank 207 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = gpiochip_get_data(chip); bank 208 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); bank 210 drivers/pinctrl/stm32/pinctrl-stm32.c int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); bank 228 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = gpiochip_get_data(chip); bank 231 drivers/pinctrl/stm32/pinctrl-stm32.c clk_enable(bank->clk); bank 233 drivers/pinctrl/stm32/pinctrl-stm32.c ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); bank 235 drivers/pinctrl/stm32/pinctrl-stm32.c clk_disable(bank->clk); bank 242 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = gpiochip_get_data(chip); bank 244 drivers/pinctrl/stm32/pinctrl-stm32.c __stm32_gpio_set(bank, offset, value); bank 255 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = gpiochip_get_data(chip); bank 257 drivers/pinctrl/stm32/pinctrl-stm32.c __stm32_gpio_set(bank, offset, value); bank 266 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = gpiochip_get_data(chip); bank 269 drivers/pinctrl/stm32/pinctrl-stm32.c fwspec.fwnode = bank->fwnode; bank 279 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = gpiochip_get_data(chip); bank 284 drivers/pinctrl/stm32/pinctrl-stm32.c stm32_pmx_get_mode(bank, pin, &mode, &alt); bank 308 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = irq_data->domain->host_data; bank 309 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); bank 312 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); bank 316 drivers/pinctrl/stm32/pinctrl-stm32.c ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); bank 328 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = irq_data->domain->host_data; bank 330 drivers/pinctrl/stm32/pinctrl-stm32.c gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); bank 362 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = d->host_data; bank 363 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); bank 391 drivers/pinctrl/stm32/pinctrl-stm32.c regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); bank 404 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = d->host_data; bank 405 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); bank 417 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = d->host_data; bank 429 drivers/pinctrl/stm32/pinctrl-stm32.c bank); bank 689 drivers/pinctrl/stm32/pinctrl-stm32.c static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, bank 692 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); bank 699 drivers/pinctrl/stm32/pinctrl-stm32.c clk_enable(bank->clk); bank 700 drivers/pinctrl/stm32/pinctrl-stm32.c spin_lock_irqsave(&bank->lock, flags); bank 710 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + alt_offset); bank 713 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + alt_offset); bank 715 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_MODER); bank 718 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_MODER); bank 723 drivers/pinctrl/stm32/pinctrl-stm32.c stm32_gpio_backup_mode(bank, pin, mode, alt); bank 726 drivers/pinctrl/stm32/pinctrl-stm32.c spin_unlock_irqrestore(&bank->lock, flags); bank 727 drivers/pinctrl/stm32/pinctrl-stm32.c clk_disable(bank->clk); bank 732 drivers/pinctrl/stm32/pinctrl-stm32.c void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, bank 740 drivers/pinctrl/stm32/pinctrl-stm32.c clk_enable(bank->clk); bank 741 drivers/pinctrl/stm32/pinctrl-stm32.c spin_lock_irqsave(&bank->lock, flags); bank 743 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + alt_offset); bank 747 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_MODER); bank 751 drivers/pinctrl/stm32/pinctrl-stm32.c spin_unlock_irqrestore(&bank->lock, flags); bank 752 drivers/pinctrl/stm32/pinctrl-stm32.c clk_disable(bank->clk); bank 763 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank; bank 780 drivers/pinctrl/stm32/pinctrl-stm32.c bank = gpiochip_get_data(range->gc); bank 786 drivers/pinctrl/stm32/pinctrl-stm32.c return stm32_pmx_set_mode(bank, pin, mode, alt); bank 793 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); bank 796 drivers/pinctrl/stm32/pinctrl-stm32.c return stm32_pmx_set_mode(bank, pin, !input, 0); bank 810 drivers/pinctrl/stm32/pinctrl-stm32.c static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, bank 813 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); bank 818 drivers/pinctrl/stm32/pinctrl-stm32.c clk_enable(bank->clk); bank 819 drivers/pinctrl/stm32/pinctrl-stm32.c spin_lock_irqsave(&bank->lock, flags); bank 829 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_TYPER); bank 832 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_TYPER); bank 837 drivers/pinctrl/stm32/pinctrl-stm32.c stm32_gpio_backup_driving(bank, offset, drive); bank 840 drivers/pinctrl/stm32/pinctrl-stm32.c spin_unlock_irqrestore(&bank->lock, flags); bank 841 drivers/pinctrl/stm32/pinctrl-stm32.c clk_disable(bank->clk); bank 846 drivers/pinctrl/stm32/pinctrl-stm32.c static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, bank 852 drivers/pinctrl/stm32/pinctrl-stm32.c clk_enable(bank->clk); bank 853 drivers/pinctrl/stm32/pinctrl-stm32.c spin_lock_irqsave(&bank->lock, flags); bank 855 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_TYPER); bank 858 drivers/pinctrl/stm32/pinctrl-stm32.c spin_unlock_irqrestore(&bank->lock, flags); bank 859 drivers/pinctrl/stm32/pinctrl-stm32.c clk_disable(bank->clk); bank 864 drivers/pinctrl/stm32/pinctrl-stm32.c static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, bank 867 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); bank 872 drivers/pinctrl/stm32/pinctrl-stm32.c clk_enable(bank->clk); bank 873 drivers/pinctrl/stm32/pinctrl-stm32.c spin_lock_irqsave(&bank->lock, flags); bank 883 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); bank 886 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); bank 891 drivers/pinctrl/stm32/pinctrl-stm32.c stm32_gpio_backup_speed(bank, offset, speed); bank 894 drivers/pinctrl/stm32/pinctrl-stm32.c spin_unlock_irqrestore(&bank->lock, flags); bank 895 drivers/pinctrl/stm32/pinctrl-stm32.c clk_disable(bank->clk); bank 900 drivers/pinctrl/stm32/pinctrl-stm32.c static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, bank 906 drivers/pinctrl/stm32/pinctrl-stm32.c clk_enable(bank->clk); bank 907 drivers/pinctrl/stm32/pinctrl-stm32.c spin_lock_irqsave(&bank->lock, flags); bank 909 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); bank 912 drivers/pinctrl/stm32/pinctrl-stm32.c spin_unlock_irqrestore(&bank->lock, flags); bank 913 drivers/pinctrl/stm32/pinctrl-stm32.c clk_disable(bank->clk); bank 918 drivers/pinctrl/stm32/pinctrl-stm32.c static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, bank 921 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); bank 926 drivers/pinctrl/stm32/pinctrl-stm32.c clk_enable(bank->clk); bank 927 drivers/pinctrl/stm32/pinctrl-stm32.c spin_lock_irqsave(&bank->lock, flags); bank 937 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); bank 940 drivers/pinctrl/stm32/pinctrl-stm32.c writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); bank 945 drivers/pinctrl/stm32/pinctrl-stm32.c stm32_gpio_backup_bias(bank, offset, bias); bank 948 drivers/pinctrl/stm32/pinctrl-stm32.c spin_unlock_irqrestore(&bank->lock, flags); bank 949 drivers/pinctrl/stm32/pinctrl-stm32.c clk_disable(bank->clk); bank 954 drivers/pinctrl/stm32/pinctrl-stm32.c static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, bank 960 drivers/pinctrl/stm32/pinctrl-stm32.c clk_enable(bank->clk); bank 961 drivers/pinctrl/stm32/pinctrl-stm32.c spin_lock_irqsave(&bank->lock, flags); bank 963 drivers/pinctrl/stm32/pinctrl-stm32.c val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); bank 966 drivers/pinctrl/stm32/pinctrl-stm32.c spin_unlock_irqrestore(&bank->lock, flags); bank 967 drivers/pinctrl/stm32/pinctrl-stm32.c clk_disable(bank->clk); bank 972 drivers/pinctrl/stm32/pinctrl-stm32.c static bool stm32_pconf_get(struct stm32_gpio_bank *bank, bank 978 drivers/pinctrl/stm32/pinctrl-stm32.c clk_enable(bank->clk); bank 979 drivers/pinctrl/stm32/pinctrl-stm32.c spin_lock_irqsave(&bank->lock, flags); bank 982 drivers/pinctrl/stm32/pinctrl-stm32.c val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & bank 985 drivers/pinctrl/stm32/pinctrl-stm32.c val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & bank 988 drivers/pinctrl/stm32/pinctrl-stm32.c spin_unlock_irqrestore(&bank->lock, flags); bank 989 drivers/pinctrl/stm32/pinctrl-stm32.c clk_disable(bank->clk); bank 1000 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank; bank 1009 drivers/pinctrl/stm32/pinctrl-stm32.c bank = gpiochip_get_data(range->gc); bank 1014 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_driving(bank, offset, 0); bank 1017 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_driving(bank, offset, 1); bank 1020 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_speed(bank, offset, arg); bank 1023 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_bias(bank, offset, 0); bank 1026 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_bias(bank, offset, 1); bank 1029 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_bias(bank, offset, 2); bank 1032 drivers/pinctrl/stm32/pinctrl-stm32.c __stm32_gpio_set(bank, offset, arg); bank 1078 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank; bank 1093 drivers/pinctrl/stm32/pinctrl-stm32.c bank = gpiochip_get_data(range->gc); bank 1096 drivers/pinctrl/stm32/pinctrl-stm32.c stm32_pmx_get_mode(bank, offset, &mode, &alt); bank 1097 drivers/pinctrl/stm32/pinctrl-stm32.c bias = stm32_pconf_get_bias(bank, offset); bank 1104 drivers/pinctrl/stm32/pinctrl-stm32.c val = stm32_pconf_get(bank, offset, true); bank 1112 drivers/pinctrl/stm32/pinctrl-stm32.c drive = stm32_pconf_get_driving(bank, offset); bank 1113 drivers/pinctrl/stm32/pinctrl-stm32.c speed = stm32_pconf_get_speed(bank, offset); bank 1114 drivers/pinctrl/stm32/pinctrl-stm32.c val = stm32_pconf_get(bank, offset, false); bank 1124 drivers/pinctrl/stm32/pinctrl-stm32.c drive = stm32_pconf_get_driving(bank, offset); bank 1125 drivers/pinctrl/stm32/pinctrl-stm32.c speed = stm32_pconf_get_speed(bank, offset); bank 1148 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; bank 1150 drivers/pinctrl/stm32/pinctrl-stm32.c struct pinctrl_gpio_range *range = &bank->range; bank 1165 drivers/pinctrl/stm32/pinctrl-stm32.c bank->base = devm_ioremap_resource(dev, &res); bank 1166 drivers/pinctrl/stm32/pinctrl-stm32.c if (IS_ERR(bank->base)) bank 1167 drivers/pinctrl/stm32/pinctrl-stm32.c return PTR_ERR(bank->base); bank 1169 drivers/pinctrl/stm32/pinctrl-stm32.c bank->clk = of_clk_get_by_name(np, NULL); bank 1170 drivers/pinctrl/stm32/pinctrl-stm32.c if (IS_ERR(bank->clk)) { bank 1171 drivers/pinctrl/stm32/pinctrl-stm32.c dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); bank 1172 drivers/pinctrl/stm32/pinctrl-stm32.c return PTR_ERR(bank->clk); bank 1175 drivers/pinctrl/stm32/pinctrl-stm32.c err = clk_prepare(bank->clk); bank 1181 drivers/pinctrl/stm32/pinctrl-stm32.c bank->gpio_chip = stm32_gpio_template; bank 1183 drivers/pinctrl/stm32/pinctrl-stm32.c of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); bank 1187 drivers/pinctrl/stm32/pinctrl-stm32.c bank->gpio_chip.base = args.args[1]; bank 1190 drivers/pinctrl/stm32/pinctrl-stm32.c bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; bank 1191 drivers/pinctrl/stm32/pinctrl-stm32.c range->name = bank->gpio_chip.label; bank 1196 drivers/pinctrl/stm32/pinctrl-stm32.c range->gc = &bank->gpio_chip; bank 1204 drivers/pinctrl/stm32/pinctrl-stm32.c bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; bank 1206 drivers/pinctrl/stm32/pinctrl-stm32.c bank->gpio_chip.ngpio = npins; bank 1207 drivers/pinctrl/stm32/pinctrl-stm32.c bank->gpio_chip.of_node = np; bank 1208 drivers/pinctrl/stm32/pinctrl-stm32.c bank->gpio_chip.parent = dev; bank 1209 drivers/pinctrl/stm32/pinctrl-stm32.c bank->bank_nr = bank_nr; bank 1210 drivers/pinctrl/stm32/pinctrl-stm32.c bank->bank_ioport_nr = bank_ioport_nr; bank 1211 drivers/pinctrl/stm32/pinctrl-stm32.c spin_lock_init(&bank->lock); bank 1214 drivers/pinctrl/stm32/pinctrl-stm32.c bank->fwnode = of_node_to_fwnode(np); bank 1216 drivers/pinctrl/stm32/pinctrl-stm32.c bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, bank 1217 drivers/pinctrl/stm32/pinctrl-stm32.c STM32_GPIO_IRQ_LINE, bank->fwnode, bank 1218 drivers/pinctrl/stm32/pinctrl-stm32.c &stm32_gpio_domain_ops, bank); bank 1220 drivers/pinctrl/stm32/pinctrl-stm32.c if (!bank->domain) bank 1223 drivers/pinctrl/stm32/pinctrl-stm32.c err = gpiochip_add_data(&bank->gpio_chip, bank); bank 1229 drivers/pinctrl/stm32/pinctrl-stm32.c dev_info(dev, "%s bank added\n", bank->gpio_chip.label); bank 1492 drivers/pinctrl/stm32/pinctrl-stm32.c struct stm32_gpio_bank *bank; bank 1505 drivers/pinctrl/stm32/pinctrl-stm32.c bank = gpiochip_get_data(range->gc); bank 1507 drivers/pinctrl/stm32/pinctrl-stm32.c alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; bank 1509 drivers/pinctrl/stm32/pinctrl-stm32.c mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; bank 1512 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pmx_set_mode(bank, offset, mode, alt); bank 1517 drivers/pinctrl/stm32/pinctrl-stm32.c val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); bank 1519 drivers/pinctrl/stm32/pinctrl-stm32.c __stm32_gpio_set(bank, offset, val); bank 1522 drivers/pinctrl/stm32/pinctrl-stm32.c val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); bank 1524 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_driving(bank, offset, val); bank 1528 drivers/pinctrl/stm32/pinctrl-stm32.c val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; bank 1530 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_speed(bank, offset, val); bank 1534 drivers/pinctrl/stm32/pinctrl-stm32.c val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; bank 1536 drivers/pinctrl/stm32/pinctrl-stm32.c ret = stm32_pconf_set_bias(bank, offset, val); bank 1541 drivers/pinctrl/stm32/pinctrl-stm32.c regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); bank 66 drivers/pinctrl/stm32/pinctrl-stm32.h void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, bank 617 drivers/pinctrl/sunxi/pinctrl-sunxi.c unsigned short bank = pin / PINS_PER_BANK; bank 661 drivers/pinctrl/sunxi/pinctrl-sunxi.c reg &= ~(1 << bank); bank 662 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); bank 764 drivers/pinctrl/sunxi/pinctrl-sunxi.c unsigned short bank = offset / PINS_PER_BANK; bank 765 drivers/pinctrl/sunxi/pinctrl-sunxi.c unsigned short bank_offset = bank - pctl->desc->pin_base / bank 777 drivers/pinctrl/sunxi/pinctrl-sunxi.c snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank); bank 781 drivers/pinctrl/sunxi/pinctrl-sunxi.c 'A' + bank); bank 788 drivers/pinctrl/sunxi/pinctrl-sunxi.c "Couldn't enable bank P%c regulator\n", 'A' + bank); bank 808 drivers/pinctrl/sunxi/pinctrl-sunxi.c unsigned short bank = offset / PINS_PER_BANK; bank 809 drivers/pinctrl/sunxi/pinctrl-sunxi.c unsigned short bank_offset = bank - pctl->desc->pin_base / bank 1124 drivers/pinctrl/sunxi/pinctrl-sunxi.c unsigned long bank, reg, val; bank 1126 drivers/pinctrl/sunxi/pinctrl-sunxi.c for (bank = 0; bank < pctl->desc->irq_banks; bank++) bank 1127 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (irq == pctl->irq[bank]) bank 1130 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (bank == pctl->desc->irq_banks) bank 1133 drivers/pinctrl/sunxi/pinctrl-sunxi.c reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); bank 1142 drivers/pinctrl/sunxi/pinctrl-sunxi.c bank * IRQ_PER_BANK + irqoffset); bank 32 drivers/pinctrl/sunxi/pinctrl-sunxi.h #define SUNXI_PINCTRL_PIN(bank, pin) \ bank 33 drivers/pinctrl/sunxi/pinctrl-sunxi.h PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) bank 237 drivers/pinctrl/sunxi/pinctrl-sunxi.h u8 bank = pin / PINS_PER_BANK; bank 238 drivers/pinctrl/sunxi/pinctrl-sunxi.h u32 offset = bank * BANK_MEM_SIZE; bank 252 drivers/pinctrl/sunxi/pinctrl-sunxi.h u8 bank = pin / PINS_PER_BANK; bank 253 drivers/pinctrl/sunxi/pinctrl-sunxi.h u32 offset = bank * BANK_MEM_SIZE; bank 267 drivers/pinctrl/sunxi/pinctrl-sunxi.h u8 bank = pin / PINS_PER_BANK; bank 268 drivers/pinctrl/sunxi/pinctrl-sunxi.h u32 offset = bank * BANK_MEM_SIZE; bank 282 drivers/pinctrl/sunxi/pinctrl-sunxi.h u8 bank = pin / PINS_PER_BANK; bank 283 drivers/pinctrl/sunxi/pinctrl-sunxi.h u32 offset = bank * BANK_MEM_SIZE; bank 295 drivers/pinctrl/sunxi/pinctrl-sunxi.h static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) bank 298 drivers/pinctrl/sunxi/pinctrl-sunxi.h return bank; bank 300 drivers/pinctrl/sunxi/pinctrl-sunxi.h return desc->irq_bank_map[bank]; bank 306 drivers/pinctrl/sunxi/pinctrl-sunxi.h u8 bank = irq / IRQ_PER_BANK; bank 310 drivers/pinctrl/sunxi/pinctrl-sunxi.h sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg; bank 319 drivers/pinctrl/sunxi/pinctrl-sunxi.h static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) bank 321 drivers/pinctrl/sunxi/pinctrl-sunxi.h return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; bank 327 drivers/pinctrl/sunxi/pinctrl-sunxi.h u8 bank = irq / IRQ_PER_BANK; bank 329 drivers/pinctrl/sunxi/pinctrl-sunxi.h return sunxi_irq_ctrl_reg_from_bank(desc, bank); bank 338 drivers/pinctrl/sunxi/pinctrl-sunxi.h static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) bank 341 drivers/pinctrl/sunxi/pinctrl-sunxi.h sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; bank 344 drivers/pinctrl/sunxi/pinctrl-sunxi.h static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) bank 347 drivers/pinctrl/sunxi/pinctrl-sunxi.h sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; bank 353 drivers/pinctrl/sunxi/pinctrl-sunxi.h u8 bank = irq / IRQ_PER_BANK; bank 355 drivers/pinctrl/sunxi/pinctrl-sunxi.h return sunxi_irq_status_reg_from_bank(desc, bank); bank 366 drivers/pinctrl/sunxi/pinctrl-sunxi.h u8 bank = pin / PINS_PER_BANK; bank 368 drivers/pinctrl/sunxi/pinctrl-sunxi.h return GRP_CFG_REG + bank * 0x4; bank 28 drivers/pinctrl/tegra/pinctrl-tegra.c static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) bank 30 drivers/pinctrl/tegra/pinctrl-tegra.c return readl(pmx->regs[bank] + reg); bank 33 drivers/pinctrl/tegra/pinctrl-tegra.c static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) bank 35 drivers/pinctrl/tegra/pinctrl-tegra.c writel_relaxed(val, pmx->regs[bank] + reg); bank 37 drivers/pinctrl/tegra/pinctrl-tegra.c pmx_readl(pmx, bank, reg); bank 289 drivers/pinctrl/tegra/pinctrl-tegra.c s8 *bank, s32 *reg, s8 *bit, s8 *width) bank 293 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->pupd_bank; bank 299 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->tri_bank; bank 305 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->mux_bank; bank 311 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->mux_bank; bank 317 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->mux_bank; bank 323 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->mux_bank; bank 329 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->mux_bank; bank 336 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->mux_bank; bank 339 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->drv_bank; bank 347 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->mux_bank; bank 350 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->drv_bank; bank 357 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->drv_bank; bank 363 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->drv_bank; bank 369 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->drv_bank; bank 375 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->drv_bank; bank 381 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->drv_bank; bank 388 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->mux_bank; bank 391 drivers/pinctrl/tegra/pinctrl-tegra.c *bank = g->drv_bank; bank 447 drivers/pinctrl/tegra/pinctrl-tegra.c s8 bank, bit, width; bank 453 drivers/pinctrl/tegra/pinctrl-tegra.c ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, bank 458 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); bank 476 drivers/pinctrl/tegra/pinctrl-tegra.c s8 bank, bit, width; bank 486 drivers/pinctrl/tegra/pinctrl-tegra.c ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, bank 491 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); bank 517 drivers/pinctrl/tegra/pinctrl-tegra.c pmx_writel(pmx, val, bank, reg); bank 544 drivers/pinctrl/tegra/pinctrl-tegra.c s8 bank, bit, width; bank 552 drivers/pinctrl/tegra/pinctrl-tegra.c &bank, ®, &bit, &width); bank 556 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); bank 619 drivers/pinctrl/tegra/pinctrl-tegra.c unsigned int bank, reg; bank 622 drivers/pinctrl/tegra/pinctrl-tegra.c bank = g->mux_bank; bank 625 drivers/pinctrl/tegra/pinctrl-tegra.c bank = g->drv_bank; bank 629 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); bank 631 drivers/pinctrl/tegra/pinctrl-tegra.c pmx_writel(pmx, val, bank, reg); bank 72 drivers/pinctrl/tegra/pinctrl-tegra194.c slwf_w, bank) \ bank 74 drivers/pinctrl/tegra/pinctrl-tegra194.c .drv_bank = bank, \ bank 84 drivers/pinctrl/tegra/pinctrl-tegra194.c #define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, e_input, \ bank 90 drivers/pinctrl/tegra/pinctrl-tegra194.c .mux_bank = bank, \ bank 93 drivers/pinctrl/tegra/pinctrl-tegra194.c .pupd_bank = bank, \ bank 96 drivers/pinctrl/tegra/pinctrl-tegra194.c .tri_bank = bank, \ bank 110 drivers/pinctrl/tegra/pinctrl-tegra194.c #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk, \ bank 122 drivers/pinctrl/tegra/pinctrl-tegra194.c PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, \ bank 87 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 bank = WMT_BANK_FROM_PIN(pin); bank 89 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 reg_en = data->banks[bank].reg_en; bank 90 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 reg_dir = data->banks[bank].reg_dir; bank 424 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 bank = WMT_BANK_FROM_PIN(pin); bank 426 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 reg_pull_en = data->banks[bank].reg_pull_en; bank 427 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 reg_pull_cfg = data->banks[bank].reg_pull_cfg; bank 483 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 bank = WMT_BANK_FROM_PIN(offset); bank 485 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 reg_dir = data->banks[bank].reg_dir; bank 496 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 bank = WMT_BANK_FROM_PIN(offset); bank 498 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 reg_data_in = data->banks[bank].reg_data_in; bank 512 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 bank = WMT_BANK_FROM_PIN(offset); bank 514 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 reg_data_out = data->banks[bank].reg_data_out; bank 347 drivers/power/supply/ab8500_charger.c u8 bank; bank 354 drivers/power/supply/ab8500_charger.c bank = 0x15; bank 358 drivers/power/supply/ab8500_charger.c bank = AB8500_SYS_CTRL1_BLOCK; bank 364 drivers/power/supply/ab8500_charger.c ret = abx500_get_register_interruptible(di->dev, bank, reg, &val); bank 385 drivers/power/supply/ab8500_charger.c ret = abx500_set_register_interruptible(di->dev, bank, reg, val); bank 316 drivers/regulator/ab8500.c u8 bank, reg, mask, val; bank 326 drivers/regulator/ab8500.c bank = info->mode_bank; bank 330 drivers/regulator/ab8500.c bank = info->update_bank; bank 374 drivers/regulator/ab8500.c bank, reg, mask, val); bank 384 drivers/regulator/ab8500.c info->desc.name, bank, reg, bank 1066 drivers/regulator/ab8500.c u8 bank; bank 1073 drivers/regulator/ab8500.c .bank = _bank, \ bank 48 drivers/reset/hisilicon/hi6220_reset.c u32 bank = idx >> 8; bank 50 drivers/reset/hisilicon/hi6220_reset.c u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10; bank 60 drivers/reset/hisilicon/hi6220_reset.c u32 bank = idx >> 8; bank 62 drivers/reset/hisilicon/hi6220_reset.c u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10; bank 33 drivers/reset/reset-meson.c unsigned int bank = id / BITS_PER_REG; bank 35 drivers/reset/reset-meson.c void __iomem *reg_addr = data->reg_base + (bank << 2); bank 47 drivers/reset/reset-meson.c unsigned int bank = id / BITS_PER_REG; bank 49 drivers/reset/reset-meson.c void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2); bank 36 drivers/reset/reset-simple.c int bank = id / (reg_width * BITS_PER_BYTE); bank 43 drivers/reset/reset-simple.c reg = readl(data->membase + (bank * reg_width)); bank 48 drivers/reset/reset-simple.c writel(reg, data->membase + (bank * reg_width)); bank 72 drivers/reset/reset-simple.c int bank = id / (reg_width * BITS_PER_BYTE); bank 76 drivers/reset/reset-simple.c reg = readl(data->membase + (bank * reg_width)); bank 32 drivers/reset/reset-stm32mp1.c int bank = id / (reg_width * BITS_PER_BYTE); bank 36 drivers/reset/reset-stm32mp1.c addr = data->membase + (bank * reg_width); bank 62 drivers/reset/reset-stm32mp1.c int bank = id / (reg_width * BITS_PER_BYTE); bank 66 drivers/reset/reset-stm32mp1.c reg = readl(data->membase + (bank * reg_width)); bank 34 drivers/reset/reset-zynq.c int bank = id / BITS_PER_LONG; bank 38 drivers/reset/reset-zynq.c bank, offset); bank 41 drivers/reset/reset-zynq.c priv->offset + (bank * 4), bank 51 drivers/reset/reset-zynq.c int bank = id / BITS_PER_LONG; bank 55 drivers/reset/reset-zynq.c bank, offset); bank 58 drivers/reset/reset-zynq.c priv->offset + (bank * 4), bank 68 drivers/reset/reset-zynq.c int bank = id / BITS_PER_LONG; bank 74 drivers/reset/reset-zynq.c bank, offset); bank 76 drivers/reset/reset-zynq.c ret = regmap_read(priv->slcr, priv->offset + (bank * 4), ®); bank 55 drivers/rtc/rtc-r7301.c u8 bank; bank 117 drivers/rtc/rtc-r7301.c static void rtc7301_select_bank(struct rtc7301_priv *priv, u8 bank) bank 121 drivers/rtc/rtc-r7301.c if (bank == priv->bank) bank 124 drivers/rtc/rtc-r7301.c if (bank & BIT(0)) bank 126 drivers/rtc/rtc-r7301.c if (bank & BIT(1)) bank 133 drivers/rtc/rtc-r7301.c priv->bank = bank; bank 383 drivers/rtc/rtc-r7301.c priv->bank = -1; bank 3656 drivers/scsi/advansys.c static void AscSetBank(PortAddr iop_base, uchar bank) bank 3664 drivers/scsi/advansys.c if (bank == 1) { bank 3666 drivers/scsi/advansys.c } else if (bank == 2) { bank 312 drivers/scsi/cxlflash/common.h return &afu->afu_map->global.bank[CHAN2PORTBANK(i)]; bank 450 drivers/scsi/cxlflash/sislite.h struct fc_port_bank bank[CXLFLASH_MAX_FC_BANKS]; /* pages 2 - 9 */ bank 195 drivers/scsi/qla2xxx/qla_tmpl.c ulong bank = le32_to_cpu(ent->t258.bank); bank 203 drivers/scsi/qla2xxx/qla_tmpl.c qla27xx_write_reg(ISPREG(vha), banksel, bank, buf); bank 215 drivers/scsi/qla2xxx/qla_tmpl.c ulong bank = le32_to_cpu(ent->t259.bank); bank 222 drivers/scsi/qla2xxx/qla_tmpl.c qla27xx_write_reg(ISPREG(vha), banksel, bank, buf); bank 104 drivers/scsi/qla2xxx/qla_tmpl.h __le32 bank; bank 113 drivers/scsi/qla2xxx/qla_tmpl.h __le32 bank; bank 1038 drivers/soundwire/cadence_master.c struct sdw_port_params *p_params, unsigned int bank) bank 1043 drivers/soundwire/cadence_master.c if (bank) bank 1064 drivers/soundwire/cadence_master.c enum sdw_reg_bank bank) bank 1078 drivers/soundwire/cadence_master.c if (bank) { bank 1117 drivers/soundwire/cadence_master.c struct sdw_enable_ch *enable_ch, unsigned int bank) bank 1122 drivers/soundwire/cadence_master.c if (bank) bank 442 drivers/soundwire/stream.c prep_ch.bank = bus->params.next_bank; bank 516 drivers/soundwire/stream.c prep_ch.bank = bus->params.next_bank; bank 579 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c struct adapter *padapter, u8 bank, bool bPseudoTest bank 590 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c DBG_8192C("%s: Efuse switch bank to %d\n", __func__, bank); bank 593 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c pEfuseHal->fakeEfuseBank = bank; bank 595 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c fakeEfuseBank = bank; bank 601 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c switch (bank) { bank 1009 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u8 bank; bank 1035 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c for (bank = 1; bank < 3; bank++) { /* 8723b Max bake 0~2 */ bank 1036 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false) { bank 1047 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c DBG_8192C("%s: efuse[%#X]= 0x%02x (header)\n", __func__, (((bank-1)*EFUSE_REAL_CONTENT_LEN_8723B)+eFuse_Addr-1), efuseHeader); bank 1055 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c DBG_8192C("%s: efuse[%#X]= 0x%02x (ext header)\n", __func__, (((bank-1)*EFUSE_REAL_CONTENT_LEN_8723B)+eFuse_Addr-1), efuseExtHdr); bank 1094 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c DBG_8192C("%s: bank(%d) data end at %#x\n", __func__, bank, eFuse_Addr-1); bank 1110 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c used = (EFUSE_BT_REAL_BANK_CONTENT_LEN*(bank-1)) + eFuse_Addr - 1; bank 1111 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c DBG_8192C("%s: bank(%d) data end at %#x , used =%d\n", __func__, bank, eFuse_Addr-1, used); bank 1251 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u8 bank, startBank; bank 1272 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c for (bank = startBank; bank < 3; bank++) { bank 1273 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false) { bank 1274 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c DBG_8192C(KERN_ERR "%s: switch bank(%d) Fail!!\n", __func__, bank); bank 1280 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c if (bank != startBank) bank 1290 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c DBG_8192C("%s: efuse_OneByteRead ! addr = 0x%X !efuse_data = 0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank); bank 1299 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c DBG_8192C("%s: efuse_OneByteRead EXT_HEADER ! addr = 0x%X !efuse_data = 0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank); bank 1357 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c retU2 = ((bank-1)*EFUSE_BT_REAL_BANK_CONTENT_LEN)+efuse_addr; bank 550 drivers/thermal/mtk_thermal.c static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) bank 552 drivers/thermal/mtk_thermal.c struct mtk_thermal *mt = bank->mt; bank 560 drivers/thermal/mtk_thermal.c val |= bank->id; bank 571 drivers/thermal/mtk_thermal.c static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) bank 573 drivers/thermal/mtk_thermal.c struct mtk_thermal *mt = bank->mt; bank 586 drivers/thermal/mtk_thermal.c static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) bank 588 drivers/thermal/mtk_thermal.c struct mtk_thermal *mt = bank->mt; bank 593 drivers/thermal/mtk_thermal.c for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { bank 595 drivers/thermal/mtk_thermal.c conf->msr[conf->bank_data[bank->id].sensors[i]]); bank 598 drivers/thermal/mtk_thermal.c conf->bank_data[bank->id].sensors[i], bank 623 drivers/thermal/mtk_thermal.c struct mtk_thermal_bank *bank = &mt->banks[i]; bank 625 drivers/thermal/mtk_thermal.c mtk_thermal_get_bank(bank); bank 627 drivers/thermal/mtk_thermal.c tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); bank 629 drivers/thermal/mtk_thermal.c mtk_thermal_put_bank(bank); bank 645 drivers/thermal/mtk_thermal.c struct mtk_thermal_bank *bank = &mt->banks[num]; bank 652 drivers/thermal/mtk_thermal.c bank->id = num; bank 653 drivers/thermal/mtk_thermal.c bank->mt = mt; bank 655 drivers/thermal/mtk_thermal.c mtk_thermal_get_bank(bank); bank 746 drivers/thermal/mtk_thermal.c mtk_thermal_put_bank(bank); bank 58 drivers/uio/uio_fsl_elbc_gpcm.c u32 bank; bank 86 drivers/uio/uio_fsl_elbc_gpcm.c struct fsl_lbc_bank *bank = &priv->lbc->bank[priv->bank]; bank 90 drivers/uio/uio_fsl_elbc_gpcm.c in_be32(&bank->br)); bank 94 drivers/uio/uio_fsl_elbc_gpcm.c in_be32(&bank->or)); bank 105 drivers/uio/uio_fsl_elbc_gpcm.c struct fsl_lbc_bank *bank = &priv->lbc->bank[priv->bank]; bank 117 drivers/uio/uio_fsl_elbc_gpcm.c reg_br_cur = in_be32(&bank->br); bank 118 drivers/uio/uio_fsl_elbc_gpcm.c reg_or_cur = in_be32(&bank->or); bank 132 drivers/uio/uio_fsl_elbc_gpcm.c out_be32(&bank->br, reg_new | BR_V); bank 140 drivers/uio/uio_fsl_elbc_gpcm.c out_be32(&bank->or, reg_new); bank 224 drivers/uio/uio_fsl_elbc_gpcm.c if (priv->bank >= MAX_BANKS) { bank 266 drivers/uio/uio_fsl_elbc_gpcm.c ret = of_property_read_u32(node, "reg", &priv->bank); bank 347 drivers/uio/uio_fsl_elbc_gpcm.c reg_br_cur = in_be32(&priv->lbc->bank[priv->bank].br); bank 348 drivers/uio/uio_fsl_elbc_gpcm.c reg_or_cur = in_be32(&priv->lbc->bank[priv->bank].or); bank 378 drivers/uio/uio_fsl_elbc_gpcm.c out_be32(&priv->lbc->bank[priv->bank].or, reg_or_new); bank 379 drivers/uio/uio_fsl_elbc_gpcm.c out_be32(&priv->lbc->bank[priv->bank].br, reg_br_new); bank 423 drivers/uio/uio_fsl_elbc_gpcm.c priv->name, (unsigned long long)res.start, priv->bank, bank 138 drivers/usb/host/sl811-hcd.c u8 bank, bank 146 drivers/usb/host/sl811-hcd.c addr = SL811HS_PACKET_BUF(bank == 0); bank 152 drivers/usb/host/sl811-hcd.c sl811_write(sl811, bank + SL11H_BUFADDRREG, addr); bank 158 drivers/usb/host/sl811-hcd.c sl811_write(sl811, bank + SL11H_HOSTCTLREG, bank 169 drivers/usb/host/sl811-hcd.c u8 bank, bank 180 drivers/usb/host/sl811-hcd.c sl811_write(sl811, bank + SL11H_BUFADDRREG, 0); bank 189 drivers/usb/host/sl811-hcd.c sl811_write(sl811, bank + SL11H_HOSTCTLREG, control); bank 203 drivers/usb/host/sl811-hcd.c u8 bank, bank 213 drivers/usb/host/sl811-hcd.c addr = SL811HS_PACKET_BUF(bank == 0); bank 220 drivers/usb/host/sl811-hcd.c sl811_write(sl811, bank + SL11H_BUFADDRREG, addr); bank 225 drivers/usb/host/sl811-hcd.c sl811_write(sl811, bank + SL11H_HOSTCTLREG, control); bank 239 drivers/usb/host/sl811-hcd.c u8 bank, bank 257 drivers/usb/host/sl811-hcd.c addr = SL811HS_PACKET_BUF(bank == 0); bank 263 drivers/usb/host/sl811-hcd.c sl811_write(sl811, bank + SL11H_BUFADDRREG, addr); bank 268 drivers/usb/host/sl811-hcd.c sl811_write(sl811, bank + SL11H_HOSTCTLREG, bank 302 drivers/usb/host/sl811-hcd.c static struct sl811h_ep *start(struct sl811 *sl811, u8 bank) bank 327 drivers/usb/host/sl811-hcd.c if ((bank && sl811->active_b == ep) || sl811->active_a == ep) bank 381 drivers/usb/host/sl811-hcd.c in_packet(sl811, ep, urb, bank, control); bank 384 drivers/usb/host/sl811-hcd.c out_packet(sl811, ep, urb, bank, control); bank 387 drivers/usb/host/sl811-hcd.c setup_packet(sl811, ep, urb, bank, control); bank 390 drivers/usb/host/sl811-hcd.c status_packet(sl811, ep, urb, bank, control); bank 475 drivers/usb/host/sl811-hcd.c done(struct sl811 *sl811, struct sl811h_ep *ep, u8 bank) bank 484 drivers/usb/host/sl811-hcd.c status = sl811_read(sl811, bank + SL11H_PKTSTATREG); bank 528 drivers/usb/host/sl811-hcd.c bank + SL11H_XFERCNTREG); bank 534 drivers/usb/host/sl811-hcd.c sl811_read_buf(sl811, SL811HS_PACKET_BUF(bank == 0), bank 567 drivers/usb/host/sl811-hcd.c PACKET("...STALL_%02x qh%p\n", bank, ep); bank 581 drivers/usb/host/sl811-hcd.c bank, status, ep, urbstat); bank 406 drivers/video/backlight/lm3630a_bl.c u32 bank, val; bank 409 drivers/video/backlight/lm3630a_bl.c ret = fwnode_property_read_u32(node, "reg", &bank); bank 413 drivers/video/backlight/lm3630a_bl.c if (bank < LM3630A_BANK_0 || bank > LM3630A_BANK_1) bank 416 drivers/video/backlight/lm3630a_bl.c led_sources = lm3630a_parse_led_sources(node, BIT(bank)); bank 427 drivers/video/backlight/lm3630a_bl.c if (bank) { bank 449 drivers/video/backlight/lm3630a_bl.c if (bank) bank 458 drivers/video/backlight/lm3630a_bl.c if (bank) bank 466 drivers/video/backlight/lm3630a_bl.c if (bank) bank 274 drivers/xen/mcelog.c m.bank = mc_bank->mc_bank; bank 13 include/dt-bindings/gpio/uniphier-gpio.h #define UNIPHIER_GPIO_PORT(bank, line) \ bank 14 include/dt-bindings/gpio/uniphier-gpio.h ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) bank 435 include/linux/cper.h u16 bank; bank 455 include/linux/cper.h u16 bank; bank 475 include/linux/cper.h u16 bank; bank 114 include/linux/dmi.h extern void dmi_memdev_name(u16 handle, const char **bank, const char **device); bank 142 include/linux/dmi.h static inline void dmi_memdev_name(u16 handle, const char **bank, bank 58 include/linux/hwspinlock.h int hwspin_lock_register(struct hwspinlock_device *bank, struct device *dev, bank 60 include/linux/hwspinlock.h int hwspin_lock_unregister(struct hwspinlock_device *bank); bank 76 include/linux/hwspinlock.h struct hwspinlock_device *bank); bank 78 include/linux/hwspinlock.h struct hwspinlock_device *bank, bank 34 include/linux/jz4780-nemc.h extern void jz4780_nemc_set_type(struct device *dev, unsigned int bank, bank 36 include/linux/jz4780-nemc.h extern void jz4780_nemc_assert(struct device *dev, unsigned int bank, bank 26 include/linux/mfd/abx500.h u8 bank; bank 307 include/linux/mfd/abx500.h int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg, bank 309 include/linux/mfd/abx500.h int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg, bank 311 include/linux/mfd/abx500.h int abx500_get_register_page_interruptible(struct device *dev, u8 bank, bank 313 include/linux/mfd/abx500.h int abx500_set_register_page_interruptible(struct device *dev, u8 bank, bank 327 include/linux/mfd/abx500.h int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank, bank 55 include/linux/mfd/asic3.h #define ASIC3_GPIO(bank, gpio) \ bank 56 include/linux/mfd/asic3.h ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio)) bank 75 include/linux/mfd/asic3.h #define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100)) bank 27 include/linux/platform_data/gpio-davinci.h #define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) bank 11 include/linux/scx200_gpio.h #define __SCx200_GPIO_BANK unsigned bank = index>>5 bank 12 include/linux/scx200_gpio.h #define __SCx200_GPIO_IOADDR unsigned short ioaddr = scx200_gpio_base+0x10*bank bank 13 include/linux/scx200_gpio.h #define __SCx200_GPIO_SHADOW unsigned long *shadow = scx200_gpio_shadow+bank bank 36 include/linux/scx200_gpio.h return (scx200_gpio_shadow[bank] & (1<<index)) ? 1 : 0; bank 460 include/linux/soundwire/sdw.h unsigned int bank; bank 478 include/linux/soundwire/sdw.h unsigned int bank; bank 671 include/linux/soundwire/sdw.h unsigned int bank); bank 674 include/linux/soundwire/sdw.h enum sdw_reg_bank bank); bank 678 include/linux/soundwire/sdw.h struct sdw_enable_ch *enable_ch, unsigned int bank); bank 254 include/sound/opl3.h unsigned char bank; bank 363 include/sound/opl3.h int prog, int bank, int type, bank 367 include/sound/opl3.h struct fm_patch *snd_opl3_find_patch(struct snd_opl3 *opl3, int prog, int bank, bank 21 include/sound/soundfont.h unsigned char bank; /* Midi bank for this zone */ bank 103 include/sound/soundfont.h int preset, int bank, bank 34 include/trace/events/mce.h __field( u8, bank ) bank 54 include/trace/events/mce.h __entry->bank = m->bank; bank 61 include/trace/events/mce.h __entry->bank, __entry->status, bank 1069 include/uapi/linux/kvm.h __u8 bank; bank 128 include/uapi/sound/asound_fm.h unsigned char bank; bank 146 include/uapi/sound/sfnt_info.h unsigned char bank; /* midi bank number */ bank 349 include/xen/interface/xen-mca.h __u8 bank; /* machine check bank */ bank 13 scripts/dtc/include-prefixes/dt-bindings/gpio/uniphier-gpio.h #define UNIPHIER_GPIO_PORT(bank, line) \ bank 14 scripts/dtc/include-prefixes/dt-bindings/gpio/uniphier-gpio.h ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) bank 294 sound/drivers/opl3/opl3_midi.c unsigned char prg, bank; bank 316 sound/drivers/opl3/opl3_midi.c bank = 128; bank 319 sound/drivers/opl3/opl3_midi.c bank = chan->gm_bank_select; bank 328 sound/drivers/opl3/opl3_midi.c bank = 127; bank 341 sound/drivers/opl3/opl3_midi.c patch = snd_opl3_find_patch(opl3, prg, bank, 0); bank 590 sound/drivers/opl3/opl3_midi.c bank = 128; bank 594 sound/drivers/opl3/opl3_midi.c bank = 0; bank 201 sound/drivers/opl3/opl3_synth.c err = snd_opl3_load_patch(opl3, inst.prog, inst.bank, type, bank 240 sound/drivers/opl3/opl3_synth.c int prog, int bank, int type, bank 248 sound/drivers/opl3/opl3_synth.c patch = snd_opl3_find_patch(opl3, prog, bank, 1); bank 302 sound/drivers/opl3/opl3_synth.c struct fm_patch *snd_opl3_find_patch(struct snd_opl3 *opl3, int prog, int bank, bank 306 sound/drivers/opl3/opl3_synth.c unsigned int key = (prog + bank) % OPL3_PATCH_HASH_SIZE; bank 310 sound/drivers/opl3/opl3_synth.c if (patch->prog == prog && patch->bank == bank) bank 320 sound/drivers/opl3/opl3_synth.c patch->bank = bank; bank 246 sound/isa/msnd/msnd.c int snd_msnd_DARQ(struct snd_msnd *chip, int bank) bank 261 sound/isa/msnd/msnd.c bank * DAQDS__size + DAQDS_wStart; bank 273 sound/isa/msnd/msnd.c DAQD = bank * DAQDS__size + chip->mappedbase + DARQ_DATA_BUFF; bank 282 sound/isa/msnd/msnd.c (char *)(chip->base + bank * DAR_BUFF_SIZE), bank 21 sound/pci/au88x0/au88x0_wt.h #define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */ bank 22 sound/pci/au88x0/au88x0_wt.h #define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */ bank 23 sound/pci/au88x0/au88x0_wt.h #define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */ bank 24 sound/pci/au88x0/au88x0_wt.h #define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */ bank 25 sound/pci/au88x0/au88x0_wt.h #define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */ bank 26 sound/pci/au88x0/au88x0_wt.h #define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */ bank 310 sound/pci/cs46xx/cs46xx_lib.c unsigned int bank = offset >> 16; bank 315 sound/pci/cs46xx/cs46xx_lib.c dst = chip->region.idx[bank+1].remap_addr + offset; bank 473 sound/pci/cs46xx/cs46xx_lib.c unsigned int bank = offset >> 16; bank 478 sound/pci/cs46xx/cs46xx_lib.c dst = chip->region.idx[bank+1].remap_addr + offset; bank 47 sound/pci/cs46xx/cs46xx_lib.h unsigned int bank = reg >> 16; bank 55 sound/pci/cs46xx/cs46xx_lib.h writel(val, chip->region.idx[bank+1].remap_addr + offset); bank 60 sound/pci/cs46xx/cs46xx_lib.h unsigned int bank = reg >> 16; bank 62 sound/pci/cs46xx/cs46xx_lib.h return readl(chip->region.idx[bank+1].remap_addr + offset); bank 235 sound/pci/ymfpci/ymfpci.h struct snd_ymfpci_playback_bank *bank; bank 301 sound/pci/ymfpci/ymfpci_main.c pos = le32_to_cpu(voice->bank[chip->active_bank].start); bank 324 sound/pci/ymfpci/ymfpci_main.c struct snd_ymfpci_playback_bank *bank; bank 327 sound/pci/ymfpci/ymfpci_main.c bank = &voice->bank[next_bank]; bank 329 sound/pci/ymfpci/ymfpci_main.c bank->left_gain_end = volume; bank 331 sound/pci/ymfpci/ymfpci_main.c bank->eff2_gain_end = volume; bank 333 sound/pci/ymfpci/ymfpci_main.c bank = &ypcm->voices[1]->bank[next_bank]; bank 335 sound/pci/ymfpci/ymfpci_main.c bank->right_gain_end = volume; bank 337 sound/pci/ymfpci/ymfpci_main.c bank->eff3_gain_end = volume; bank 492 sound/pci/ymfpci/ymfpci_main.c struct snd_ymfpci_playback_bank *bank; bank 537 sound/pci/ymfpci/ymfpci_main.c bank = &voice->bank[nbank]; bank 538 sound/pci/ymfpci/ymfpci_main.c memset(bank, 0, sizeof(*bank)); bank 539 sound/pci/ymfpci/ymfpci_main.c bank->format = cpu_to_le32(format); bank 540 sound/pci/ymfpci/ymfpci_main.c bank->base = cpu_to_le32(runtime->dma_addr); bank 541 sound/pci/ymfpci/ymfpci_main.c bank->loop_end = cpu_to_le32(ypcm->buffer_size); bank 542 sound/pci/ymfpci/ymfpci_main.c bank->lpfQ = cpu_to_le32(lpfQ); bank 543 sound/pci/ymfpci/ymfpci_main.c bank->delta = bank 544 sound/pci/ymfpci/ymfpci_main.c bank->delta_end = cpu_to_le32(delta); bank 545 sound/pci/ymfpci/ymfpci_main.c bank->lpfK = bank 546 sound/pci/ymfpci/ymfpci_main.c bank->lpfK_end = cpu_to_le32(lpfK); bank 547 sound/pci/ymfpci/ymfpci_main.c bank->eg_gain = bank 548 sound/pci/ymfpci/ymfpci_main.c bank->eg_gain_end = cpu_to_le32(0x40000000); bank 552 sound/pci/ymfpci/ymfpci_main.c bank->left_gain = bank 553 sound/pci/ymfpci/ymfpci_main.c bank->left_gain_end = vol_left; bank 556 sound/pci/ymfpci/ymfpci_main.c bank->right_gain = bank 557 sound/pci/ymfpci/ymfpci_main.c bank->right_gain_end = vol_right; bank 563 sound/pci/ymfpci/ymfpci_main.c bank->eff2_gain = bank 564 sound/pci/ymfpci/ymfpci_main.c bank->eff2_gain_end = vol_left; bank 567 sound/pci/ymfpci/ymfpci_main.c bank->eff3_gain = bank 568 sound/pci/ymfpci/ymfpci_main.c bank->eff3_gain_end = vol_right; bank 576 sound/pci/ymfpci/ymfpci_main.c bank->eff3_gain = bank 577 sound/pci/ymfpci/ymfpci_main.c bank->eff3_gain_end = vol_left; bank 580 sound/pci/ymfpci/ymfpci_main.c bank->eff2_gain = bank 581 sound/pci/ymfpci/ymfpci_main.c bank->eff2_gain_end = vol_right; bank 706 sound/pci/ymfpci/ymfpci_main.c struct snd_ymfpci_capture_bank * bank; bank 736 sound/pci/ymfpci/ymfpci_main.c bank = chip->bank_capture[ypcm->capture_bank_number][nbank]; bank 737 sound/pci/ymfpci/ymfpci_main.c bank->base = cpu_to_le32(runtime->dma_addr); bank 738 sound/pci/ymfpci/ymfpci_main.c bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift); bank 739 sound/pci/ymfpci/ymfpci_main.c bank->start = 0; bank 740 sound/pci/ymfpci/ymfpci_main.c bank->num_of_loops = 0; bank 754 sound/pci/ymfpci/ymfpci_main.c return le32_to_cpu(voice->bank[chip->active_bank].start); bank 2094 sound/pci/ymfpci/ymfpci_main.c int voice, bank, reg; bank 2126 sound/pci/ymfpci/ymfpci_main.c chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr; bank 2128 sound/pci/ymfpci/ymfpci_main.c for (bank = 0; bank < 2; bank++) { bank 2129 sound/pci/ymfpci/ymfpci_main.c chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr; bank 2139 sound/pci/ymfpci/ymfpci_main.c for (bank = 0; bank < 2; bank++) { bank 2140 sound/pci/ymfpci/ymfpci_main.c chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr; bank 2149 sound/pci/ymfpci/ymfpci_main.c for (bank = 0; bank < 2; bank++) { bank 2150 sound/pci/ymfpci/ymfpci_main.c chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr; bank 503 sound/soc/amd/acp-pcm-dma.c static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, bank 509 sound/soc/amd/acp-pcm-dma.c if (bank < 32) { bank 515 sound/soc/amd/acp-pcm-dma.c bank -= 32; bank 522 sound/soc/amd/acp-pcm-dma.c if (val & (1 << bank)) { bank 526 sound/soc/amd/acp-pcm-dma.c val &= ~(1 << bank); bank 534 sound/soc/amd/acp-pcm-dma.c val |= 1 << bank; bank 543 sound/soc/amd/acp-pcm-dma.c pr_err("ACP SRAM bank %d state change failed\n", bank); bank 553 sound/soc/amd/acp-pcm-dma.c u16 bank; bank 638 sound/soc/amd/acp-pcm-dma.c for (bank = 1; bank < 48; bank++) bank 639 sound/soc/amd/acp-pcm-dma.c acp_set_sram_bank_state(acp_mmio, bank, false); bank 764 sound/soc/amd/acp-pcm-dma.c u16 bank; bank 822 sound/soc/amd/acp-pcm-dma.c for (bank = 1; bank <= 4; bank++) bank 824 sound/soc/amd/acp-pcm-dma.c bank, true); bank 828 sound/soc/amd/acp-pcm-dma.c for (bank = 5; bank <= 8; bank++) bank 830 sound/soc/amd/acp-pcm-dma.c bank, true); bank 1163 sound/soc/amd/acp-pcm-dma.c u16 bank; bank 1187 sound/soc/amd/acp-pcm-dma.c for (bank = 1; bank <= 4; bank++) bank 1189 sound/soc/amd/acp-pcm-dma.c bank, false); bank 1201 sound/soc/amd/acp-pcm-dma.c for (bank = 5; bank <= 8; bank++) bank 1203 sound/soc/amd/acp-pcm-dma.c bank, false); bank 1322 sound/soc/amd/acp-pcm-dma.c u16 bank; bank 1340 sound/soc/amd/acp-pcm-dma.c for (bank = 1; bank <= 4; bank++) bank 1341 sound/soc/amd/acp-pcm-dma.c acp_set_sram_bank_state(adata->acp_mmio, bank, bank 1350 sound/soc/amd/acp-pcm-dma.c for (bank = 5; bank <= 8; bank++) bank 1351 sound/soc/amd/acp-pcm-dma.c acp_set_sram_bank_state(adata->acp_mmio, bank, bank 893 sound/synth/emux/emux_synth.c int preset, bank, def_preset, def_bank; bank 895 sound/synth/emux/emux_synth.c bank = get_bank(port, chan); bank 898 sound/synth/emux/emux_synth.c if (SF_IS_DRUM_BANK(bank)) { bank 900 sound/synth/emux/emux_synth.c def_bank = bank; bank 906 sound/synth/emux/emux_synth.c return snd_soundfont_search_zone(emu->sflist, notep, vel, preset, bank, bank 43 sound/synth/emux/soundfont.c int bank, int instr); bank 54 sound/synth/emux/soundfont.c int bank, int preset, int key); bank 56 sound/synth/emux/soundfont.c int preset, int bank, struct snd_sf_zone **table, bank 58 sound/synth/emux/soundfont.c static int get_index(int bank, int instr, int key); bank 191 sound/synth/emux/soundfont.c int bank, instr; bank 192 sound/synth/emux/soundfont.c bank = ((unsigned short)patch.optarg >> 8) & 0xff; bank 194 sound/synth/emux/soundfont.c if (! remove_info(sflist, sflist->currsf, bank, instr)) bank 435 sound/synth/emux/soundfont.c zp->bank == map.map_bank && bank 457 sound/synth/emux/soundfont.c zp->bank = map.map_bank; bank 478 sound/synth/emux/soundfont.c int bank, int instr) bank 487 sound/synth/emux/soundfont.c p->bank == bank && p->instr == instr) { bank 552 sound/synth/emux/soundfont.c zone->bank == hdr.bank && bank 559 sound/synth/emux/soundfont.c remove_info(sflist, sf, hdr.bank, hdr.instr); bank 574 sound/synth/emux/soundfont.c tmpzone.bank = hdr.bank; bank 587 sound/synth/emux/soundfont.c zone->bank = tmpzone.bank; bank 1101 sound/synth/emux/soundfont.c zone->bank = 0; bank 1168 sound/synth/emux/soundfont.c zone = search_first_zone(sflist, cur->bank, cur->instr, cur->v.low); bank 1184 sound/synth/emux/soundfont.c if ((index = get_index(cur->bank, cur->instr, cur->v.low)) < 0) bank 1200 sound/synth/emux/soundfont.c if ((index = get_index(zp->bank, zp->instr, zp->v.low)) < 0) bank 1222 sound/synth/emux/soundfont.c int preset, int bank, bank 1238 sound/synth/emux/soundfont.c nvoices = search_zones(sflist, notep, vel, preset, bank, bank 1241 sound/synth/emux/soundfont.c if (preset != def_preset || bank != def_bank) bank 1255 sound/synth/emux/soundfont.c search_first_zone(struct snd_sf_list *sflist, int bank, int preset, int key) bank 1260 sound/synth/emux/soundfont.c if ((index = get_index(bank, preset, key)) < 0) bank 1263 sound/synth/emux/soundfont.c if (zp->instr == preset && zp->bank == bank) bank 1275 sound/synth/emux/soundfont.c int preset, int bank, struct snd_sf_zone **table, bank 1281 sound/synth/emux/soundfont.c zp = search_first_zone(sflist, bank, preset, *notep); bank 1290 sound/synth/emux/soundfont.c bank = zp->v.end; bank 1297 sound/synth/emux/soundfont.c preset, bank, table, bank 1319 sound/synth/emux/soundfont.c get_index(int bank, int instr, int key) bank 1322 sound/synth/emux/soundfont.c if (SF_IS_DRUM_BANK(bank)) bank 123 sound/usb/caiaq/control.c int bank = 0; bank 127 sound/usb/caiaq/control.c bank = 0x1e; bank 131 sound/usb/caiaq/control.c snd_usb_caiaq_send_command_bank(cdev, cmd, bank, bank 228 sound/usb/caiaq/device.c unsigned char bank, bank 245 sound/usb/caiaq/device.c cdev->ep1_out_buf[1] = bank; bank 134 sound/usb/caiaq/device.h unsigned char bank, bank 1069 tools/include/uapi/linux/kvm.h __u8 bank;