ath79_set_clk      88 arch/mips/ath79/clock.c 		clk = ath79_set_clk(ATH79_CLK_REF, rate);
ath79_set_clk     119 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk     120 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk     121 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
ath79_set_clk     339 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk     340 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk     341 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
ath79_set_clk     345 arch/mips/ath79/clock.c 		ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
ath79_set_clk     428 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk     429 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk     430 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
ath79_set_clk     511 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk     512 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk     513 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
ath79_set_clk     613 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk     614 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk     615 arch/mips/ath79/clock.c 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);