ath79_reset_rr    157 arch/mips/ath79/clock.c 	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
ath79_reset_rr    245 arch/mips/ath79/clock.c 	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
ath79_reset_rr    360 arch/mips/ath79/clock.c 	bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
ath79_reset_rr    443 arch/mips/ath79/clock.c 	bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
ath79_reset_rr    532 arch/mips/ath79/clock.c 	misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
ath79_reset_rr    536 arch/mips/ath79/clock.c 	bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
ath79_reset_rr    113 arch/mips/ath79/common.c 	t = ath79_reset_rr(reg);
ath79_reset_rr    145 arch/mips/ath79/common.c 	t = ath79_reset_rr(reg);
ath79_reset_rr     62 arch/mips/ath79/setup.c 	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
ath79_reset_rr    422 arch/mips/pci/pci-ar724x.c 	if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)