CACHE_EVENT_ATTR  133 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1);
CACHE_EVENT_ATTR  134 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);
CACHE_EVENT_ATTR  136 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-prefetches,		PM_L1_PREF);
CACHE_EVENT_ATTR  137 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-store-misses,	PM_ST_MISS_L1);
CACHE_EVENT_ATTR  138 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-icache-load-misses,		PM_L1_ICACHE_MISS);
CACHE_EVENT_ATTR  139 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-icache-loads,		PM_INST_FROM_L1);
CACHE_EVENT_ATTR  140 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-icache-prefetches,		PM_IC_PREF_WRITE);
CACHE_EVENT_ATTR  142 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(LLC-load-misses,		PM_DATA_FROM_L3MISS);
CACHE_EVENT_ATTR  143 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(LLC-loads,			PM_DATA_FROM_L3);
CACHE_EVENT_ATTR  144 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(LLC-prefetches,		PM_L3_PREF_ALL);
CACHE_EVENT_ATTR  145 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(LLC-store-misses,		PM_L2_ST_MISS);
CACHE_EVENT_ATTR  146 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(LLC-stores,			PM_L2_ST);
CACHE_EVENT_ATTR  148 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(branch-load-misses,		PM_BR_MPRED_CMPL);
CACHE_EVENT_ATTR  149 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(branch-loads,			PM_BRU_FIN);
CACHE_EVENT_ATTR  150 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(dTLB-load-misses,		PM_DTLB_MISS);
CACHE_EVENT_ATTR  151 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(iTLB-load-misses,		PM_ITLB_MISS);
CACHE_EVENT_ATTR  163 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1_FIN);
CACHE_EVENT_ATTR  164 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);
CACHE_EVENT_ATTR  165 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-prefetches,		PM_L1_PREF);
CACHE_EVENT_ATTR  166 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-store-misses,	PM_ST_MISS_L1);
CACHE_EVENT_ATTR  167 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-icache-load-misses,		PM_L1_ICACHE_MISS);
CACHE_EVENT_ATTR  168 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-icache-loads,		PM_INST_FROM_L1);
CACHE_EVENT_ATTR  169 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-icache-prefetches,		PM_IC_PREF_WRITE);
CACHE_EVENT_ATTR  170 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(LLC-load-misses,		PM_DATA_FROM_L3MISS);
CACHE_EVENT_ATTR  171 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(LLC-loads,			PM_DATA_FROM_L3);
CACHE_EVENT_ATTR  172 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(LLC-prefetches,		PM_L3_PREF_ALL);
CACHE_EVENT_ATTR  173 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(branch-load-misses,		PM_BR_MPRED_CMPL);
CACHE_EVENT_ATTR  174 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(branch-loads,			PM_BR_CMPL);
CACHE_EVENT_ATTR  175 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(dTLB-load-misses,		PM_DTLB_MISS);
CACHE_EVENT_ATTR  176 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(iTLB-load-misses,		PM_ITLB_MISS);