ast_set_index_reg_mask   23 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
ast_set_index_reg_mask   31 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
ast_set_index_reg_mask   68 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
ast_set_index_reg_mask   73 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
ast_set_index_reg_mask  100 drivers/gpu/drm/ast/ast_dp501.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
ast_set_index_reg_mask  122 drivers/gpu/drm/ast/ast_dp501.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
ast_set_index_reg_mask  156 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
ast_set_index_reg_mask  381 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
ast_set_index_reg_mask  410 drivers/gpu/drm/ast/ast_dp501.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00);
ast_set_index_reg_mask  181 drivers/gpu/drm/ast/ast_drv.h void ast_set_index_reg_mask(struct ast_private *ast,
ast_set_index_reg_mask  257 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
ast_set_index_reg_mask  290 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
ast_set_index_reg_mask  295 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
ast_set_index_reg_mask  300 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
ast_set_index_reg_mask  305 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
ast_set_index_reg_mask  312 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
ast_set_index_reg_mask  317 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
ast_set_index_reg_mask  322 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
ast_set_index_reg_mask  324 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
ast_set_index_reg_mask  325 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
ast_set_index_reg_mask  335 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
ast_set_index_reg_mask  344 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
ast_set_index_reg_mask  351 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
ast_set_index_reg_mask  360 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
ast_set_index_reg_mask  369 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
ast_set_index_reg_mask  374 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
ast_set_index_reg_mask  376 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
ast_set_index_reg_mask  377 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
ast_set_index_reg_mask  378 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
ast_set_index_reg_mask  381 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
ast_set_index_reg_mask  383 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
ast_set_index_reg_mask  385 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
ast_set_index_reg_mask  411 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
ast_set_index_reg_mask  412 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
ast_set_index_reg_mask  413 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
ast_set_index_reg_mask  444 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
ast_set_index_reg_mask  445 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
ast_set_index_reg_mask  446 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
ast_set_index_reg_mask  515 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
ast_set_index_reg_mask  523 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
ast_set_index_reg_mask  625 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
ast_set_index_reg_mask 1011 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
ast_set_index_reg_mask 1027 drivers/gpu/drm/ast/ast_mode.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
ast_set_index_reg_mask 1087 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
ast_set_index_reg_mask 1093 drivers/gpu/drm/ast/ast_mode.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
ast_set_index_reg_mask   96 drivers/gpu/drm/ast/ast_post.c 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
ast_set_index_reg_mask  105 drivers/gpu/drm/ast/ast_post.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
ast_set_index_reg_mask  106 drivers/gpu/drm/ast/ast_post.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
ast_set_index_reg_mask  113 drivers/gpu/drm/ast/ast_post.c 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
ast_set_index_reg_mask  395 drivers/gpu/drm/ast/ast_post.c 			ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);	/* Enable DVO */