C 126 arch/arc/include/asm/perf_event.h static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 127 arch/arc/include/asm/perf_event.h [C(L1D)] = { C 128 arch/arc/include/asm/perf_event.h [C(OP_READ)] = { C 129 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC, C 130 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM, C 132 arch/arc/include/asm/perf_event.h [C(OP_WRITE)] = { C 133 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC, C 134 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM, C 136 arch/arc/include/asm/perf_event.h [C(OP_PREFETCH)] = { C 137 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 138 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 141 arch/arc/include/asm/perf_event.h [C(L1I)] = { C 142 arch/arc/include/asm/perf_event.h [C(OP_READ)] = { C 143 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS, C 144 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = PERF_COUNT_ARC_ICM, C 146 arch/arc/include/asm/perf_event.h [C(OP_WRITE)] = { C 147 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 148 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 150 arch/arc/include/asm/perf_event.h [C(OP_PREFETCH)] = { C 151 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 152 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 155 arch/arc/include/asm/perf_event.h [C(LL)] = { C 156 arch/arc/include/asm/perf_event.h [C(OP_READ)] = { C 157 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 158 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 160 arch/arc/include/asm/perf_event.h [C(OP_WRITE)] = { C 161 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 162 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 164 arch/arc/include/asm/perf_event.h [C(OP_PREFETCH)] = { C 165 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 166 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 169 arch/arc/include/asm/perf_event.h [C(DTLB)] = { C 170 arch/arc/include/asm/perf_event.h [C(OP_READ)] = { C 171 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC, C 172 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB, C 175 arch/arc/include/asm/perf_event.h [C(OP_WRITE)] = { C 176 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 177 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 179 arch/arc/include/asm/perf_event.h [C(OP_PREFETCH)] = { C 180 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 181 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 184 arch/arc/include/asm/perf_event.h [C(ITLB)] = { C 185 arch/arc/include/asm/perf_event.h [C(OP_READ)] = { C 186 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 187 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB, C 189 arch/arc/include/asm/perf_event.h [C(OP_WRITE)] = { C 190 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 191 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 193 arch/arc/include/asm/perf_event.h [C(OP_PREFETCH)] = { C 194 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 195 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 198 arch/arc/include/asm/perf_event.h [C(BPU)] = { C 199 arch/arc/include/asm/perf_event.h [C(OP_READ)] = { C 200 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS, C 201 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES, C 203 arch/arc/include/asm/perf_event.h [C(OP_WRITE)] = { C 204 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 205 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 207 arch/arc/include/asm/perf_event.h [C(OP_PREFETCH)] = { C 208 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 209 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 212 arch/arc/include/asm/perf_event.h [C(NODE)] = { C 213 arch/arc/include/asm/perf_event.h [C(OP_READ)] = { C 214 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 215 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 217 arch/arc/include/asm/perf_event.h [C(OP_WRITE)] = { C 218 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 219 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 221 arch/arc/include/asm/perf_event.h [C(OP_PREFETCH)] = { C 222 arch/arc/include/asm/perf_event.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 223 arch/arc/include/asm/perf_event.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 96 arch/arm/kernel/perf_event_v6.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, C 97 arch/arm/kernel/perf_event_v6.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, C 98 arch/arm/kernel/perf_event_v6.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, C 99 arch/arm/kernel/perf_event_v6.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, C 101 arch/arm/kernel/perf_event_v6.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, C 109 arch/arm/kernel/perf_event_v6.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, C 110 arch/arm/kernel/perf_event_v6.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, C 112 arch/arm/kernel/perf_event_v6.c [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, C 113 arch/arm/kernel/perf_event_v6.c [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, C 159 arch/arm/kernel/perf_event_v6.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS, C 160 arch/arm/kernel/perf_event_v6.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDMISS, C 161 arch/arm/kernel/perf_event_v6.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS, C 162 arch/arm/kernel/perf_event_v6.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRMISS, C 164 arch/arm/kernel/perf_event_v6.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, C 172 arch/arm/kernel/perf_event_v6.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS, C 173 arch/arm/kernel/perf_event_v6.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS, C 175 arch/arm/kernel/perf_event_v6.c [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS, C 176 arch/arm/kernel/perf_event_v6.c [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS, C 179 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 180 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 181 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 182 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 184 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, C 185 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, C 187 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, C 188 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, C 189 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, C 190 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, C 192 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, C 193 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, C 195 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 196 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 198 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 199 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 200 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 201 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 229 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 230 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 231 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 232 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 234 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, C 236 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, C 237 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, C 239 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 240 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 242 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 243 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 244 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 245 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 266 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 267 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 268 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 269 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 270 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, C 271 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, C 273 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, C 274 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, C 279 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, C 280 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, C 282 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, C 283 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, C 285 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 286 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 288 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 289 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 290 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 291 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 313 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ, C 314 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ, C 315 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE, C 316 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE, C 323 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, C 324 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, C 326 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ, C 327 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ, C 328 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE, C 329 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE, C 331 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ, C 332 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE, C 334 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 335 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 337 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 338 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 339 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 340 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 367 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 368 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 369 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 370 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 372 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, C 373 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, C 375 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, C 376 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, C 377 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, C 378 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, C 380 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, C 381 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, C 383 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 384 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 386 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 387 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 388 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 389 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 411 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ, C 412 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 413 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE, C 414 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 421 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, C 422 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, C 424 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ, C 425 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, C 426 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE, C 427 arch/arm/kernel/perf_event_v7.c [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, C 429 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, C 430 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, C 431 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL, C 433 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 434 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, C 436 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 437 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 438 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 439 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 472 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 473 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 474 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 475 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 477 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS, C 478 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS, C 480 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, C 481 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, C 483 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, C 484 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, C 486 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 487 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 488 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 489 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 513 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 514 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 515 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, C 516 arch/arm/kernel/perf_event_v7.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, C 517 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS, C 518 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS, C 523 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, C 524 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, C 525 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, C 526 arch/arm/kernel/perf_event_v7.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, C 527 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, C 528 arch/arm/kernel/perf_event_v7.c [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, C 529 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 530 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 531 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, C 532 arch/arm/kernel/perf_event_v7.c [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, C 73 arch/arm/kernel/perf_event_xscale.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, C 74 arch/arm/kernel/perf_event_xscale.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, C 75 arch/arm/kernel/perf_event_xscale.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, C 76 arch/arm/kernel/perf_event_xscale.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, C 78 arch/arm/kernel/perf_event_xscale.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, C 80 arch/arm/kernel/perf_event_xscale.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, C 81 arch/arm/kernel/perf_event_xscale.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, C 83 arch/arm/kernel/perf_event_xscale.c [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, C 84 arch/arm/kernel/perf_event_xscale.c [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, C 80 arch/arm/mach-omap1/mux.c MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0) C 81 arch/arm/mach-omap1/mux.c MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0) C 82 arch/arm/mach-omap1/mux.c MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0) C 83 arch/arm/mach-omap1/mux.c MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0) C 124 arch/arm/mach-omap1/mux.c MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1) C 125 arch/arm/mach-omap1/mux.c MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1) C 126 arch/arm/mach-omap1/mux.c MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1) C 127 arch/arm/mach-omap1/mux.c MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1) C 161 arch/arm/mach-omap1/mux.c MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1) C 162 arch/arm/mach-omap1/mux.c MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1) C 163 arch/arm/mach-omap1/mux.c MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1) C 164 arch/arm/mach-omap1/mux.c MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1) C 165 arch/arm/mach-omap1/mux.c MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1) C 166 arch/arm/mach-omap1/mux.c MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1) C 201 arch/arm/mach-omap1/mux.c MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1) C 207 arch/arm/mach-omap1/mux.c MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0) C 247 arch/arm/mach-omap1/mux.c MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1) C 248 arch/arm/mach-omap1/mux.c MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1) C 249 arch/arm/mach-omap1/mux.c MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1) C 250 arch/arm/mach-omap1/mux.c MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1) C 257 arch/arm/mach-omap1/mux.c MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1) C 258 arch/arm/mach-omap1/mux.c MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1) C 259 arch/arm/mach-omap1/mux.c MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1) C 260 arch/arm/mach-omap1/mux.c MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1) C 267 arch/arm/mach-omap1/mux.c MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1) C 57 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, C 58 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, C 60 arch/arm64/kernel/perf_event.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, C 61 arch/arm64/kernel/perf_event.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, C 63 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL, C 64 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB, C 66 arch/arm64/kernel/perf_event.c [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL, C 67 arch/arm64/kernel/perf_event.c [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB, C 69 arch/arm64/kernel/perf_event.c [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, C 70 arch/arm64/kernel/perf_event.c [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, C 78 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL, C 80 arch/arm64/kernel/perf_event.c [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, C 81 arch/arm64/kernel/perf_event.c [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, C 89 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, C 90 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, C 91 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, C 92 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, C 94 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, C 95 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, C 97 arch/arm64/kernel/perf_event.c [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, C 98 arch/arm64/kernel/perf_event.c [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, C 106 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, C 107 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, C 115 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, C 116 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, C 117 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, C 118 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST, C 119 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS, C 120 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS, C 122 arch/arm64/kernel/perf_event.c [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS, C 123 arch/arm64/kernel/perf_event.c [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS, C 125 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, C 126 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, C 127 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, C 128 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, C 136 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, C 137 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, C 138 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, C 139 arch/arm64/kernel/perf_event.c [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, C 141 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, C 142 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, C 143 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, C 144 arch/arm64/kernel/perf_event.c [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, C 146 arch/arm64/kernel/perf_event.c [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, C 147 arch/arm64/kernel/perf_event.c [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, C 729 arch/csky/kernel/perf_event.c static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 730 arch/csky/kernel/perf_event.c [C(L1D)] = { C 732 arch/csky/kernel/perf_event.c [C(OP_READ)] = { C 733 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 734 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 736 arch/csky/kernel/perf_event.c [C(OP_WRITE)] = { C 737 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 738 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 740 arch/csky/kernel/perf_event.c [C(OP_PREFETCH)] = { C 741 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = 0x5, C 742 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = 0x6, C 745 arch/csky/kernel/perf_event.c [C(OP_READ)] = { C 746 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = 0x14, C 747 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = 0x15, C 749 arch/csky/kernel/perf_event.c [C(OP_WRITE)] = { C 750 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = 0x16, C 751 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = 0x17, C 753 arch/csky/kernel/perf_event.c [C(OP_PREFETCH)] = { C 754 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 755 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 759 arch/csky/kernel/perf_event.c [C(L1I)] = { C 760 arch/csky/kernel/perf_event.c [C(OP_READ)] = { C 761 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = 0x3, C 762 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = 0x4, C 764 arch/csky/kernel/perf_event.c [C(OP_WRITE)] = { C 765 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 766 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 768 arch/csky/kernel/perf_event.c [C(OP_PREFETCH)] = { C 769 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 770 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 773 arch/csky/kernel/perf_event.c [C(LL)] = { C 775 arch/csky/kernel/perf_event.c [C(OP_READ)] = { C 776 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 777 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 779 arch/csky/kernel/perf_event.c [C(OP_WRITE)] = { C 780 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 781 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 783 arch/csky/kernel/perf_event.c [C(OP_PREFETCH)] = { C 784 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = 0x7, C 785 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = 0x8, C 788 arch/csky/kernel/perf_event.c [C(OP_READ)] = { C 789 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = 0x18, C 790 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = 0x19, C 792 arch/csky/kernel/perf_event.c [C(OP_WRITE)] = { C 793 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = 0x1a, C 794 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = 0x1b, C 796 arch/csky/kernel/perf_event.c [C(OP_PREFETCH)] = { C 797 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 798 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 802 arch/csky/kernel/perf_event.c [C(DTLB)] = { C 804 arch/csky/kernel/perf_event.c [C(OP_READ)] = { C 805 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 806 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 808 arch/csky/kernel/perf_event.c [C(OP_WRITE)] = { C 809 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 810 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 813 arch/csky/kernel/perf_event.c [C(OP_READ)] = { C 814 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = 0x14, C 815 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = 0xb, C 817 arch/csky/kernel/perf_event.c [C(OP_WRITE)] = { C 818 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = 0x16, C 819 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = 0xb, C 822 arch/csky/kernel/perf_event.c [C(OP_PREFETCH)] = { C 823 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 824 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 827 arch/csky/kernel/perf_event.c [C(ITLB)] = { C 829 arch/csky/kernel/perf_event.c [C(OP_READ)] = { C 830 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 831 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 834 arch/csky/kernel/perf_event.c [C(OP_READ)] = { C 835 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = 0x3, C 836 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = 0xa, C 839 arch/csky/kernel/perf_event.c [C(OP_WRITE)] = { C 840 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 841 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 843 arch/csky/kernel/perf_event.c [C(OP_PREFETCH)] = { C 844 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 845 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 848 arch/csky/kernel/perf_event.c [C(BPU)] = { C 849 arch/csky/kernel/perf_event.c [C(OP_READ)] = { C 850 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 851 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 853 arch/csky/kernel/perf_event.c [C(OP_WRITE)] = { C 854 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 855 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 857 arch/csky/kernel/perf_event.c [C(OP_PREFETCH)] = { C 858 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 859 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 862 arch/csky/kernel/perf_event.c [C(NODE)] = { C 863 arch/csky/kernel/perf_event.c [C(OP_READ)] = { C 864 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 865 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 867 arch/csky/kernel/perf_event.c [C(OP_WRITE)] = { C 868 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 869 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 871 arch/csky/kernel/perf_event.c [C(OP_PREFETCH)] = { C 872 arch/csky/kernel/perf_event.c [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 873 arch/csky/kernel/perf_event.c [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 5 arch/m68k/fpsp040/fpsp.h | Copyright (C) Motorola, Inc. 1990 C 34 arch/mips/include/asm/bug.h #define BUG_ON(C) __BUG_ON((unsigned long)(C)) C 875 arch/mips/kernel/perf_event_mipsxx.c [C(L1D)] = { C 882 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 883 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, C 884 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, C 886 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 887 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, C 888 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, C 891 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { C 892 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 893 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, C 894 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, C 896 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 897 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, C 898 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, C 900 arch/mips/kernel/perf_event_mipsxx.c [C(OP_PREFETCH)] = { C 901 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T }, C 908 arch/mips/kernel/perf_event_mipsxx.c [C(LL)] = { C 909 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 910 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, C 911 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, C 913 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 914 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, C 915 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, C 918 arch/mips/kernel/perf_event_mipsxx.c [C(DTLB)] = { C 919 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 920 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, C 921 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, C 923 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 924 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, C 925 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, C 928 arch/mips/kernel/perf_event_mipsxx.c [C(ITLB)] = { C 929 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 930 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, C 931 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, C 933 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 934 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, C 935 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, C 938 arch/mips/kernel/perf_event_mipsxx.c [C(BPU)] = { C 940 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 941 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, C 942 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, C 944 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 945 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, C 946 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, C 956 arch/mips/kernel/perf_event_mipsxx.c [C(L1D)] = { C 963 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 964 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, C 965 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, C 967 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 968 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, C 969 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, C 972 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { C 973 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 974 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, C 975 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, C 977 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 978 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, C 979 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, C 981 arch/mips/kernel/perf_event_mipsxx.c [C(OP_PREFETCH)] = { C 982 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T }, C 989 arch/mips/kernel/perf_event_mipsxx.c [C(LL)] = { C 990 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 991 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, C 992 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, C 994 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 995 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, C 996 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, C 1004 arch/mips/kernel/perf_event_mipsxx.c [C(ITLB)] = { C 1005 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1006 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, C 1007 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, C 1009 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1010 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, C 1011 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, C 1014 arch/mips/kernel/perf_event_mipsxx.c [C(BPU)] = { C 1016 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1017 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, C 1018 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, C 1020 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1021 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, C 1022 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, C 1031 arch/mips/kernel/perf_event_mipsxx.c [C(L1D)] = { C 1032 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1033 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x46, CNTR_EVEN | CNTR_ODD }, C 1034 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x49, CNTR_EVEN | CNTR_ODD }, C 1036 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1037 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x47, CNTR_EVEN | CNTR_ODD }, C 1038 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x4a, CNTR_EVEN | CNTR_ODD }, C 1041 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { C 1042 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1043 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x84, CNTR_EVEN | CNTR_ODD }, C 1044 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x85, CNTR_EVEN | CNTR_ODD }, C 1047 arch/mips/kernel/perf_event_mipsxx.c [C(DTLB)] = { C 1049 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1050 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD }, C 1051 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD }, C 1053 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1054 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD }, C 1055 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD }, C 1058 arch/mips/kernel/perf_event_mipsxx.c [C(BPU)] = { C 1060 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1061 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x15, CNTR_EVEN | CNTR_ODD }, C 1062 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x16, CNTR_EVEN | CNTR_ODD }, C 1071 arch/mips/kernel/perf_event_mipsxx.c [C(L1D)] = { C 1078 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1079 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x04, CNTR_ODD }, C 1081 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1082 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x04, CNTR_ODD }, C 1085 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { C 1086 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1087 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x04, CNTR_EVEN }, C 1089 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1090 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x04, CNTR_EVEN }, C 1093 arch/mips/kernel/perf_event_mipsxx.c [C(DTLB)] = { C 1094 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1095 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x09, CNTR_ODD }, C 1097 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1098 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x09, CNTR_ODD }, C 1101 arch/mips/kernel/perf_event_mipsxx.c [C(ITLB)] = { C 1102 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1103 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x0c, CNTR_ODD }, C 1105 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1106 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x0c, CNTR_ODD }, C 1109 arch/mips/kernel/perf_event_mipsxx.c [C(BPU)] = { C 1111 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1112 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN }, C 1113 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x02, CNTR_ODD }, C 1115 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1116 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN }, C 1117 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x02, CNTR_ODD }, C 1127 arch/mips/kernel/perf_event_mipsxx.c [C(L1D)] = { C 1134 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1135 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T }, C 1136 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 12, CNTR_ODD, T }, C 1138 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1139 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T }, C 1140 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 12, CNTR_ODD, T }, C 1143 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { C 1144 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1145 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T }, C 1146 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 10, CNTR_ODD, T }, C 1148 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1149 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T }, C 1150 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 10, CNTR_ODD, T }, C 1152 arch/mips/kernel/perf_event_mipsxx.c [C(OP_PREFETCH)] = { C 1153 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T }, C 1160 arch/mips/kernel/perf_event_mipsxx.c [C(LL)] = { C 1161 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1162 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P }, C 1163 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 28, CNTR_ODD, P }, C 1165 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1166 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P }, C 1167 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 28, CNTR_ODD, P }, C 1170 arch/mips/kernel/perf_event_mipsxx.c [C(BPU)] = { C 1172 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1173 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, C 1175 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1176 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, C 1186 arch/mips/kernel/perf_event_mipsxx.c [C(L1D)] = { C 1187 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1188 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL }, C 1189 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, C 1191 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1192 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL }, C 1195 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { C 1196 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1197 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL }, C 1199 arch/mips/kernel/perf_event_mipsxx.c [C(OP_PREFETCH)] = { C 1200 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL }, C 1203 arch/mips/kernel/perf_event_mipsxx.c [C(DTLB)] = { C 1208 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1209 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, C 1211 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1212 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, C 1215 arch/mips/kernel/perf_event_mipsxx.c [C(ITLB)] = { C 1216 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1217 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, C 1226 arch/mips/kernel/perf_event_mipsxx.c [C(L1D)] = { C 1227 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1228 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */ C 1229 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */ C 1231 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1232 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */ C 1233 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */ C 1236 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { C 1237 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1238 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ C 1239 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ C 1242 arch/mips/kernel/perf_event_mipsxx.c [C(LL)] = { C 1243 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1244 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */ C 1245 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */ C 1247 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1248 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */ C 1249 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */ C 1252 arch/mips/kernel/perf_event_mipsxx.c [C(DTLB)] = { C 1257 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1258 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ C 1260 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1261 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ C 1264 arch/mips/kernel/perf_event_mipsxx.c [C(ITLB)] = { C 1265 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1266 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ C 1268 arch/mips/kernel/perf_event_mipsxx.c [C(OP_WRITE)] = { C 1269 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ C 1272 arch/mips/kernel/perf_event_mipsxx.c [C(BPU)] = { C 1273 arch/mips/kernel/perf_event_mipsxx.c [C(OP_READ)] = { C 1274 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x25, CNTR_ALL }, C 244 arch/nds32/include/asm/pmu.h [C(L1D)] = { C 245 arch/nds32/include/asm/pmu.h [C(OP_READ)] = { C 246 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 248 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 251 arch/nds32/include/asm/pmu.h [C(OP_WRITE)] = { C 252 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 254 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 257 arch/nds32/include/asm/pmu.h [C(OP_PREFETCH)] = { C 258 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 260 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 264 arch/nds32/include/asm/pmu.h [C(L1I)] = { C 265 arch/nds32/include/asm/pmu.h [C(OP_READ)] = { C 266 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 268 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 271 arch/nds32/include/asm/pmu.h [C(OP_WRITE)] = { C 272 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 274 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 277 arch/nds32/include/asm/pmu.h [C(OP_PREFETCH)] = { C 278 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 280 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 284 arch/nds32/include/asm/pmu.h [C(LL)] = { C 285 arch/nds32/include/asm/pmu.h [C(OP_READ)] = { C 286 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 287 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 289 arch/nds32/include/asm/pmu.h [C(OP_WRITE)] = { C 290 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 291 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 293 arch/nds32/include/asm/pmu.h [C(OP_PREFETCH)] = { C 294 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 296 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 304 arch/nds32/include/asm/pmu.h [C(DTLB)] = { C 305 arch/nds32/include/asm/pmu.h [C(OP_READ)] = { C 306 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 308 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 311 arch/nds32/include/asm/pmu.h [C(OP_WRITE)] = { C 312 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 313 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 315 arch/nds32/include/asm/pmu.h [C(OP_PREFETCH)] = { C 316 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 318 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 322 arch/nds32/include/asm/pmu.h [C(ITLB)] = { C 323 arch/nds32/include/asm/pmu.h [C(OP_READ)] = { C 324 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 326 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 329 arch/nds32/include/asm/pmu.h [C(OP_WRITE)] = { C 330 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 332 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 335 arch/nds32/include/asm/pmu.h [C(OP_PREFETCH)] = { C 336 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 338 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 342 arch/nds32/include/asm/pmu.h [C(BPU)] = { /* What is BPU? */ C 343 arch/nds32/include/asm/pmu.h [C(OP_READ)] = { C 344 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 346 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 349 arch/nds32/include/asm/pmu.h [C(OP_WRITE)] = { C 350 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 352 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 355 arch/nds32/include/asm/pmu.h [C(OP_PREFETCH)] = { C 356 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 358 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 362 arch/nds32/include/asm/pmu.h [C(NODE)] = { /* What is NODE? */ C 363 arch/nds32/include/asm/pmu.h [C(OP_READ)] = { C 364 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 365 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 367 arch/nds32/include/asm/pmu.h [C(OP_WRITE)] = { C 368 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, C 369 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, C 371 arch/nds32/include/asm/pmu.h [C(OP_PREFETCH)] = { C 372 arch/nds32/include/asm/pmu.h [C(RESULT_ACCESS)] = C 374 arch/nds32/include/asm/pmu.h [C(RESULT_MISS)] = C 122 arch/powerpc/include/asm/cpm1.h #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) C 207 arch/powerpc/include/asm/cpm2.h #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) C 16 arch/powerpc/math-emu/fmadd.c FP_DECL_D(C); C 26 arch/powerpc/math-emu/fmadd.c FP_UNPACK_DP(C, frC); C 38 arch/powerpc/math-emu/fmadd.c FP_MUL_D(T, A, C); C 17 arch/powerpc/math-emu/fmadds.c FP_DECL_D(C); C 27 arch/powerpc/math-emu/fmadds.c FP_UNPACK_DP(C, frC); C 39 arch/powerpc/math-emu/fmadds.c FP_MUL_D(T, A, C); C 16 arch/powerpc/math-emu/fmsub.c FP_DECL_D(C); C 26 arch/powerpc/math-emu/fmsub.c FP_UNPACK_DP(C, frC); C 38 arch/powerpc/math-emu/fmsub.c FP_MUL_D(T, A, C); C 17 arch/powerpc/math-emu/fmsubs.c FP_DECL_D(C); C 27 arch/powerpc/math-emu/fmsubs.c FP_UNPACK_DP(C, frC); C 39 arch/powerpc/math-emu/fmsubs.c FP_MUL_D(T, A, C); C 16 arch/powerpc/math-emu/fnmadd.c FP_DECL_D(C); C 26 arch/powerpc/math-emu/fnmadd.c FP_UNPACK_DP(C, frC); C 38 arch/powerpc/math-emu/fnmadd.c FP_MUL_D(T, A, C); C 17 arch/powerpc/math-emu/fnmadds.c FP_DECL_D(C); C 27 arch/powerpc/math-emu/fnmadds.c FP_UNPACK_DP(C, frC); C 39 arch/powerpc/math-emu/fnmadds.c FP_MUL_D(T, A, C); C 16 arch/powerpc/math-emu/fnmsub.c FP_DECL_D(C); C 26 arch/powerpc/math-emu/fnmsub.c FP_UNPACK_DP(C, frC); C 38 arch/powerpc/math-emu/fnmsub.c FP_MUL_D(T, A, C); C 17 arch/powerpc/math-emu/fnmsubs.c FP_DECL_D(C); C 27 arch/powerpc/math-emu/fnmsubs.c FP_UNPACK_DP(C, frC); C 39 arch/powerpc/math-emu/fnmsubs.c FP_MUL_D(T, A, C); C 25 arch/powerpc/perf/8xx-pmu.c #define DTLB_LOAD_MISS (C(DTLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16)) C 26 arch/powerpc/perf/8xx-pmu.c #define ITLB_LOAD_MISS (C(ITLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16)) C 34 arch/powerpc/perf/e500-pmu.c static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 39 arch/powerpc/perf/e500-pmu.c [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ C 40 arch/powerpc/perf/e500-pmu.c [C(OP_READ)] = { 27, 0 }, C 41 arch/powerpc/perf/e500-pmu.c [C(OP_WRITE)] = { 28, 0 }, C 42 arch/powerpc/perf/e500-pmu.c [C(OP_PREFETCH)] = { 29, 0 }, C 44 arch/powerpc/perf/e500-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ C 45 arch/powerpc/perf/e500-pmu.c [C(OP_READ)] = { 2, 60 }, C 46 arch/powerpc/perf/e500-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 47 arch/powerpc/perf/e500-pmu.c [C(OP_PREFETCH)] = { 0, 0 }, C 55 arch/powerpc/perf/e500-pmu.c [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ C 56 arch/powerpc/perf/e500-pmu.c [C(OP_READ)] = { 0, 0 }, C 57 arch/powerpc/perf/e500-pmu.c [C(OP_WRITE)] = { 0, 0 }, C 58 arch/powerpc/perf/e500-pmu.c [C(OP_PREFETCH)] = { 0, 0 }, C 66 arch/powerpc/perf/e500-pmu.c [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 67 arch/powerpc/perf/e500-pmu.c [C(OP_READ)] = { 26, 66 }, C 68 arch/powerpc/perf/e500-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 69 arch/powerpc/perf/e500-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 71 arch/powerpc/perf/e500-pmu.c [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ C 72 arch/powerpc/perf/e500-pmu.c [C(OP_READ)] = { 12, 15 }, C 73 arch/powerpc/perf/e500-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 74 arch/powerpc/perf/e500-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 76 arch/powerpc/perf/e500-pmu.c [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ C 77 arch/powerpc/perf/e500-pmu.c [C(OP_READ)] = { -1, -1 }, C 78 arch/powerpc/perf/e500-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 79 arch/powerpc/perf/e500-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 35 arch/powerpc/perf/e6500-pmu.c static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 36 arch/powerpc/perf/e6500-pmu.c [C(L1D)] = { C 38 arch/powerpc/perf/e6500-pmu.c [C(OP_READ)] = { 27, 222 }, C 39 arch/powerpc/perf/e6500-pmu.c [C(OP_WRITE)] = { 28, 223 }, C 40 arch/powerpc/perf/e6500-pmu.c [C(OP_PREFETCH)] = { 29, 0 }, C 42 arch/powerpc/perf/e6500-pmu.c [C(L1I)] = { C 44 arch/powerpc/perf/e6500-pmu.c [C(OP_READ)] = { 2, 254 }, C 45 arch/powerpc/perf/e6500-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 46 arch/powerpc/perf/e6500-pmu.c [C(OP_PREFETCH)] = { 37, 0 }, C 53 arch/powerpc/perf/e6500-pmu.c [C(LL)] = { C 55 arch/powerpc/perf/e6500-pmu.c [C(OP_READ)] = { 0, 0 }, C 56 arch/powerpc/perf/e6500-pmu.c [C(OP_WRITE)] = { 0, 0 }, C 57 arch/powerpc/perf/e6500-pmu.c [C(OP_PREFETCH)] = { 0, 0 }, C 65 arch/powerpc/perf/e6500-pmu.c [C(DTLB)] = { C 67 arch/powerpc/perf/e6500-pmu.c [C(OP_READ)] = { 26, 66 }, C 68 arch/powerpc/perf/e6500-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 69 arch/powerpc/perf/e6500-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 71 arch/powerpc/perf/e6500-pmu.c [C(BPU)] = { C 73 arch/powerpc/perf/e6500-pmu.c [C(OP_READ)] = { 12, 15 }, C 74 arch/powerpc/perf/e6500-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 75 arch/powerpc/perf/e6500-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 77 arch/powerpc/perf/e6500-pmu.c [C(NODE)] = { C 79 arch/powerpc/perf/e6500-pmu.c [C(OP_READ)] = { -1, -1 }, C 80 arch/powerpc/perf/e6500-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 81 arch/powerpc/perf/e6500-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 104 arch/powerpc/perf/generic-compat-pmu.c static int generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 105 arch/powerpc/perf/generic-compat-pmu.c [ C(L1D) ] = { C 106 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_READ) ] = { C 107 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 108 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = 0, C 110 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_WRITE) ] = { C 111 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 112 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = 0, C 114 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_PREFETCH) ] = { C 115 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 116 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = 0, C 119 arch/powerpc/perf/generic-compat-pmu.c [ C(L1I) ] = { C 120 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_READ) ] = { C 121 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 122 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = 0, C 124 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_WRITE) ] = { C 125 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 126 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = -1, C 128 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_PREFETCH) ] = { C 129 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 130 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = 0, C 133 arch/powerpc/perf/generic-compat-pmu.c [ C(LL) ] = { C 134 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_READ) ] = { C 135 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 136 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = 0, C 138 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_WRITE) ] = { C 139 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 140 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = 0, C 142 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_PREFETCH) ] = { C 143 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 144 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = 0, C 147 arch/powerpc/perf/generic-compat-pmu.c [ C(DTLB) ] = { C 148 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_READ) ] = { C 149 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 150 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = 0, C 152 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_WRITE) ] = { C 153 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = -1, C 154 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = -1, C 156 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_PREFETCH) ] = { C 157 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = -1, C 158 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = -1, C 161 arch/powerpc/perf/generic-compat-pmu.c [ C(ITLB) ] = { C 162 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_READ) ] = { C 163 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 164 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = 0, C 166 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_WRITE) ] = { C 167 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = -1, C 168 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = -1, C 170 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_PREFETCH) ] = { C 171 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = -1, C 172 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = -1, C 175 arch/powerpc/perf/generic-compat-pmu.c [ C(BPU) ] = { C 176 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_READ) ] = { C 177 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = 0, C 178 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = 0, C 180 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_WRITE) ] = { C 181 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = -1, C 182 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = -1, C 184 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_PREFETCH) ] = { C 185 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = -1, C 186 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = -1, C 189 arch/powerpc/perf/generic-compat-pmu.c [ C(NODE) ] = { C 190 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_READ) ] = { C 191 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = -1, C 192 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = -1, C 194 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_WRITE) ] = { C 195 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = -1, C 196 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = -1, C 198 arch/powerpc/perf/generic-compat-pmu.c [ C(OP_PREFETCH) ] = { C 199 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_ACCESS) ] = -1, C 200 arch/powerpc/perf/generic-compat-pmu.c [ C(RESULT_MISS) ] = -1, C 357 arch/powerpc/perf/mpc7450-pmu.c static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 358 arch/powerpc/perf/mpc7450-pmu.c [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ C 359 arch/powerpc/perf/mpc7450-pmu.c [C(OP_READ)] = { 0, 0x225 }, C 360 arch/powerpc/perf/mpc7450-pmu.c [C(OP_WRITE)] = { 0, 0x227 }, C 361 arch/powerpc/perf/mpc7450-pmu.c [C(OP_PREFETCH)] = { 0, 0 }, C 363 arch/powerpc/perf/mpc7450-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ C 364 arch/powerpc/perf/mpc7450-pmu.c [C(OP_READ)] = { 0x129, 0x115 }, C 365 arch/powerpc/perf/mpc7450-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 366 arch/powerpc/perf/mpc7450-pmu.c [C(OP_PREFETCH)] = { 0x634, 0 }, C 368 arch/powerpc/perf/mpc7450-pmu.c [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ C 369 arch/powerpc/perf/mpc7450-pmu.c [C(OP_READ)] = { 0, 0 }, C 370 arch/powerpc/perf/mpc7450-pmu.c [C(OP_WRITE)] = { 0, 0 }, C 371 arch/powerpc/perf/mpc7450-pmu.c [C(OP_PREFETCH)] = { 0, 0 }, C 373 arch/powerpc/perf/mpc7450-pmu.c [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 374 arch/powerpc/perf/mpc7450-pmu.c [C(OP_READ)] = { 0, 0x312 }, C 375 arch/powerpc/perf/mpc7450-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 376 arch/powerpc/perf/mpc7450-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 378 arch/powerpc/perf/mpc7450-pmu.c [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 379 arch/powerpc/perf/mpc7450-pmu.c [C(OP_READ)] = { 0, 0x223 }, C 380 arch/powerpc/perf/mpc7450-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 381 arch/powerpc/perf/mpc7450-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 383 arch/powerpc/perf/mpc7450-pmu.c [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ C 384 arch/powerpc/perf/mpc7450-pmu.c [C(OP_READ)] = { 0x122, 0x41c }, C 385 arch/powerpc/perf/mpc7450-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 386 arch/powerpc/perf/mpc7450-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 388 arch/powerpc/perf/mpc7450-pmu.c [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ C 389 arch/powerpc/perf/mpc7450-pmu.c [C(OP_READ)] = { -1, -1 }, C 390 arch/powerpc/perf/mpc7450-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 391 arch/powerpc/perf/mpc7450-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 621 arch/powerpc/perf/power5+-pmu.c static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 622 arch/powerpc/perf/power5+-pmu.c [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ C 623 arch/powerpc/perf/power5+-pmu.c [C(OP_READ)] = { 0x1c10a8, 0x3c1088 }, C 624 arch/powerpc/perf/power5+-pmu.c [C(OP_WRITE)] = { 0x2c10a8, 0xc10c3 }, C 625 arch/powerpc/perf/power5+-pmu.c [C(OP_PREFETCH)] = { 0xc70e7, -1 }, C 627 arch/powerpc/perf/power5+-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ C 628 arch/powerpc/perf/power5+-pmu.c [C(OP_READ)] = { 0, 0 }, C 629 arch/powerpc/perf/power5+-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 630 arch/powerpc/perf/power5+-pmu.c [C(OP_PREFETCH)] = { 0, 0 }, C 632 arch/powerpc/perf/power5+-pmu.c [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ C 633 arch/powerpc/perf/power5+-pmu.c [C(OP_READ)] = { 0, 0 }, C 634 arch/powerpc/perf/power5+-pmu.c [C(OP_WRITE)] = { 0, 0 }, C 635 arch/powerpc/perf/power5+-pmu.c [C(OP_PREFETCH)] = { 0xc50c3, 0 }, C 637 arch/powerpc/perf/power5+-pmu.c [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 638 arch/powerpc/perf/power5+-pmu.c [C(OP_READ)] = { 0xc20e4, 0x800c4 }, C 639 arch/powerpc/perf/power5+-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 640 arch/powerpc/perf/power5+-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 642 arch/powerpc/perf/power5+-pmu.c [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 643 arch/powerpc/perf/power5+-pmu.c [C(OP_READ)] = { 0, 0x800c0 }, C 644 arch/powerpc/perf/power5+-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 645 arch/powerpc/perf/power5+-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 647 arch/powerpc/perf/power5+-pmu.c [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ C 648 arch/powerpc/perf/power5+-pmu.c [C(OP_READ)] = { 0x230e4, 0x230e5 }, C 649 arch/powerpc/perf/power5+-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 650 arch/powerpc/perf/power5+-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 652 arch/powerpc/perf/power5+-pmu.c [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ C 653 arch/powerpc/perf/power5+-pmu.c [C(OP_READ)] = { -1, -1 }, C 654 arch/powerpc/perf/power5+-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 655 arch/powerpc/perf/power5+-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 563 arch/powerpc/perf/power5-pmu.c static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 564 arch/powerpc/perf/power5-pmu.c [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ C 565 arch/powerpc/perf/power5-pmu.c [C(OP_READ)] = { 0x4c1090, 0x3c1088 }, C 566 arch/powerpc/perf/power5-pmu.c [C(OP_WRITE)] = { 0x3c1090, 0xc10c3 }, C 567 arch/powerpc/perf/power5-pmu.c [C(OP_PREFETCH)] = { 0xc70e7, 0 }, C 569 arch/powerpc/perf/power5-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ C 570 arch/powerpc/perf/power5-pmu.c [C(OP_READ)] = { 0, 0 }, C 571 arch/powerpc/perf/power5-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 572 arch/powerpc/perf/power5-pmu.c [C(OP_PREFETCH)] = { 0, 0 }, C 574 arch/powerpc/perf/power5-pmu.c [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ C 575 arch/powerpc/perf/power5-pmu.c [C(OP_READ)] = { 0, 0x3c309b }, C 576 arch/powerpc/perf/power5-pmu.c [C(OP_WRITE)] = { 0, 0 }, C 577 arch/powerpc/perf/power5-pmu.c [C(OP_PREFETCH)] = { 0xc50c3, 0 }, C 579 arch/powerpc/perf/power5-pmu.c [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 580 arch/powerpc/perf/power5-pmu.c [C(OP_READ)] = { 0x2c4090, 0x800c4 }, C 581 arch/powerpc/perf/power5-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 582 arch/powerpc/perf/power5-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 584 arch/powerpc/perf/power5-pmu.c [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 585 arch/powerpc/perf/power5-pmu.c [C(OP_READ)] = { 0, 0x800c0 }, C 586 arch/powerpc/perf/power5-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 587 arch/powerpc/perf/power5-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 589 arch/powerpc/perf/power5-pmu.c [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ C 590 arch/powerpc/perf/power5-pmu.c [C(OP_READ)] = { 0x230e4, 0x230e5 }, C 591 arch/powerpc/perf/power5-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 592 arch/powerpc/perf/power5-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 594 arch/powerpc/perf/power5-pmu.c [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ C 595 arch/powerpc/perf/power5-pmu.c [C(OP_READ)] = { -1, -1 }, C 596 arch/powerpc/perf/power5-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 597 arch/powerpc/perf/power5-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 484 arch/powerpc/perf/power6-pmu.c static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 485 arch/powerpc/perf/power6-pmu.c [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ C 486 arch/powerpc/perf/power6-pmu.c [C(OP_READ)] = { 0x280030, 0x80080 }, C 487 arch/powerpc/perf/power6-pmu.c [C(OP_WRITE)] = { 0x180032, 0x80088 }, C 488 arch/powerpc/perf/power6-pmu.c [C(OP_PREFETCH)] = { 0x810a4, 0 }, C 490 arch/powerpc/perf/power6-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ C 491 arch/powerpc/perf/power6-pmu.c [C(OP_READ)] = { 0, 0x100056 }, C 492 arch/powerpc/perf/power6-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 493 arch/powerpc/perf/power6-pmu.c [C(OP_PREFETCH)] = { 0x4008c, 0 }, C 495 arch/powerpc/perf/power6-pmu.c [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ C 496 arch/powerpc/perf/power6-pmu.c [C(OP_READ)] = { 0x150730, 0x250532 }, C 497 arch/powerpc/perf/power6-pmu.c [C(OP_WRITE)] = { 0x250432, 0x150432 }, C 498 arch/powerpc/perf/power6-pmu.c [C(OP_PREFETCH)] = { 0x810a6, 0 }, C 500 arch/powerpc/perf/power6-pmu.c [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 501 arch/powerpc/perf/power6-pmu.c [C(OP_READ)] = { 0, 0x20000e }, C 502 arch/powerpc/perf/power6-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 503 arch/powerpc/perf/power6-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 505 arch/powerpc/perf/power6-pmu.c [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 506 arch/powerpc/perf/power6-pmu.c [C(OP_READ)] = { 0, 0x420ce }, C 507 arch/powerpc/perf/power6-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 508 arch/powerpc/perf/power6-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 510 arch/powerpc/perf/power6-pmu.c [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ C 511 arch/powerpc/perf/power6-pmu.c [C(OP_READ)] = { 0x430e6, 0x400052 }, C 512 arch/powerpc/perf/power6-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 513 arch/powerpc/perf/power6-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 515 arch/powerpc/perf/power6-pmu.c [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ C 516 arch/powerpc/perf/power6-pmu.c [C(OP_READ)] = { -1, -1 }, C 517 arch/powerpc/perf/power6-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 518 arch/powerpc/perf/power6-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 335 arch/powerpc/perf/power7-pmu.c static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 336 arch/powerpc/perf/power7-pmu.c [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ C 337 arch/powerpc/perf/power7-pmu.c [C(OP_READ)] = { 0xc880, 0x400f0 }, C 338 arch/powerpc/perf/power7-pmu.c [C(OP_WRITE)] = { 0, 0x300f0 }, C 339 arch/powerpc/perf/power7-pmu.c [C(OP_PREFETCH)] = { 0xd8b8, 0 }, C 341 arch/powerpc/perf/power7-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ C 342 arch/powerpc/perf/power7-pmu.c [C(OP_READ)] = { 0, 0x200fc }, C 343 arch/powerpc/perf/power7-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 344 arch/powerpc/perf/power7-pmu.c [C(OP_PREFETCH)] = { 0x408a, 0 }, C 346 arch/powerpc/perf/power7-pmu.c [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ C 347 arch/powerpc/perf/power7-pmu.c [C(OP_READ)] = { 0x16080, 0x26080 }, C 348 arch/powerpc/perf/power7-pmu.c [C(OP_WRITE)] = { 0x16082, 0x26082 }, C 349 arch/powerpc/perf/power7-pmu.c [C(OP_PREFETCH)] = { 0, 0 }, C 351 arch/powerpc/perf/power7-pmu.c [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 352 arch/powerpc/perf/power7-pmu.c [C(OP_READ)] = { 0, 0x300fc }, C 353 arch/powerpc/perf/power7-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 354 arch/powerpc/perf/power7-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 356 arch/powerpc/perf/power7-pmu.c [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 357 arch/powerpc/perf/power7-pmu.c [C(OP_READ)] = { 0, 0x400fc }, C 358 arch/powerpc/perf/power7-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 359 arch/powerpc/perf/power7-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 361 arch/powerpc/perf/power7-pmu.c [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ C 362 arch/powerpc/perf/power7-pmu.c [C(OP_READ)] = { 0x10068, 0x400f6 }, C 363 arch/powerpc/perf/power7-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 364 arch/powerpc/perf/power7-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 366 arch/powerpc/perf/power7-pmu.c [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ C 367 arch/powerpc/perf/power7-pmu.c [C(OP_READ)] = { -1, -1 }, C 368 arch/powerpc/perf/power7-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 369 arch/powerpc/perf/power7-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 256 arch/powerpc/perf/power8-pmu.c static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 257 arch/powerpc/perf/power8-pmu.c [ C(L1D) ] = { C 258 arch/powerpc/perf/power8-pmu.c [ C(OP_READ) ] = { C 259 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = PM_LD_REF_L1, C 260 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = PM_LD_MISS_L1, C 262 arch/powerpc/perf/power8-pmu.c [ C(OP_WRITE) ] = { C 263 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = 0, C 264 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = PM_ST_MISS_L1, C 266 arch/powerpc/perf/power8-pmu.c [ C(OP_PREFETCH) ] = { C 267 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = PM_L1_PREF, C 268 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = 0, C 271 arch/powerpc/perf/power8-pmu.c [ C(L1I) ] = { C 272 arch/powerpc/perf/power8-pmu.c [ C(OP_READ) ] = { C 273 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1, C 274 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, C 276 arch/powerpc/perf/power8-pmu.c [ C(OP_WRITE) ] = { C 277 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE, C 278 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = -1, C 280 arch/powerpc/perf/power8-pmu.c [ C(OP_PREFETCH) ] = { C 281 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE, C 282 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = 0, C 285 arch/powerpc/perf/power8-pmu.c [ C(LL) ] = { C 286 arch/powerpc/perf/power8-pmu.c [ C(OP_READ) ] = { C 287 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3, C 288 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, C 290 arch/powerpc/perf/power8-pmu.c [ C(OP_WRITE) ] = { C 291 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = PM_L2_ST, C 292 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = PM_L2_ST_MISS, C 294 arch/powerpc/perf/power8-pmu.c [ C(OP_PREFETCH) ] = { C 295 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL, C 296 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = 0, C 299 arch/powerpc/perf/power8-pmu.c [ C(DTLB) ] = { C 300 arch/powerpc/perf/power8-pmu.c [ C(OP_READ) ] = { C 301 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = 0, C 302 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = PM_DTLB_MISS, C 304 arch/powerpc/perf/power8-pmu.c [ C(OP_WRITE) ] = { C 305 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = -1, C 306 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = -1, C 308 arch/powerpc/perf/power8-pmu.c [ C(OP_PREFETCH) ] = { C 309 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = -1, C 310 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = -1, C 313 arch/powerpc/perf/power8-pmu.c [ C(ITLB) ] = { C 314 arch/powerpc/perf/power8-pmu.c [ C(OP_READ) ] = { C 315 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = 0, C 316 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = PM_ITLB_MISS, C 318 arch/powerpc/perf/power8-pmu.c [ C(OP_WRITE) ] = { C 319 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = -1, C 320 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = -1, C 322 arch/powerpc/perf/power8-pmu.c [ C(OP_PREFETCH) ] = { C 323 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = -1, C 324 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = -1, C 327 arch/powerpc/perf/power8-pmu.c [ C(BPU) ] = { C 328 arch/powerpc/perf/power8-pmu.c [ C(OP_READ) ] = { C 329 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = PM_BRU_FIN, C 330 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, C 332 arch/powerpc/perf/power8-pmu.c [ C(OP_WRITE) ] = { C 333 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = -1, C 334 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = -1, C 336 arch/powerpc/perf/power8-pmu.c [ C(OP_PREFETCH) ] = { C 337 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = -1, C 338 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = -1, C 341 arch/powerpc/perf/power8-pmu.c [ C(NODE) ] = { C 342 arch/powerpc/perf/power8-pmu.c [ C(OP_READ) ] = { C 343 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = -1, C 344 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = -1, C 346 arch/powerpc/perf/power8-pmu.c [ C(OP_WRITE) ] = { C 347 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = -1, C 348 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = -1, C 350 arch/powerpc/perf/power8-pmu.c [ C(OP_PREFETCH) ] = { C 351 arch/powerpc/perf/power8-pmu.c [ C(RESULT_ACCESS) ] = -1, C 352 arch/powerpc/perf/power8-pmu.c [ C(RESULT_MISS) ] = -1, C 313 arch/powerpc/perf/power9-pmu.c static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 314 arch/powerpc/perf/power9-pmu.c [ C(L1D) ] = { C 315 arch/powerpc/perf/power9-pmu.c [ C(OP_READ) ] = { C 316 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = PM_LD_REF_L1, C 317 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN, C 319 arch/powerpc/perf/power9-pmu.c [ C(OP_WRITE) ] = { C 320 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = 0, C 321 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = PM_ST_MISS_L1, C 323 arch/powerpc/perf/power9-pmu.c [ C(OP_PREFETCH) ] = { C 324 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = PM_L1_PREF, C 325 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = 0, C 328 arch/powerpc/perf/power9-pmu.c [ C(L1I) ] = { C 329 arch/powerpc/perf/power9-pmu.c [ C(OP_READ) ] = { C 330 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1, C 331 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, C 333 arch/powerpc/perf/power9-pmu.c [ C(OP_WRITE) ] = { C 334 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE, C 335 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = -1, C 337 arch/powerpc/perf/power9-pmu.c [ C(OP_PREFETCH) ] = { C 338 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE, C 339 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = 0, C 342 arch/powerpc/perf/power9-pmu.c [ C(LL) ] = { C 343 arch/powerpc/perf/power9-pmu.c [ C(OP_READ) ] = { C 344 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3, C 345 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, C 347 arch/powerpc/perf/power9-pmu.c [ C(OP_WRITE) ] = { C 348 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = 0, C 349 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = 0, C 351 arch/powerpc/perf/power9-pmu.c [ C(OP_PREFETCH) ] = { C 352 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL, C 353 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = 0, C 356 arch/powerpc/perf/power9-pmu.c [ C(DTLB) ] = { C 357 arch/powerpc/perf/power9-pmu.c [ C(OP_READ) ] = { C 358 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = 0, C 359 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = PM_DTLB_MISS, C 361 arch/powerpc/perf/power9-pmu.c [ C(OP_WRITE) ] = { C 362 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = -1, C 363 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = -1, C 365 arch/powerpc/perf/power9-pmu.c [ C(OP_PREFETCH) ] = { C 366 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = -1, C 367 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = -1, C 370 arch/powerpc/perf/power9-pmu.c [ C(ITLB) ] = { C 371 arch/powerpc/perf/power9-pmu.c [ C(OP_READ) ] = { C 372 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = 0, C 373 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = PM_ITLB_MISS, C 375 arch/powerpc/perf/power9-pmu.c [ C(OP_WRITE) ] = { C 376 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = -1, C 377 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = -1, C 379 arch/powerpc/perf/power9-pmu.c [ C(OP_PREFETCH) ] = { C 380 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = -1, C 381 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = -1, C 384 arch/powerpc/perf/power9-pmu.c [ C(BPU) ] = { C 385 arch/powerpc/perf/power9-pmu.c [ C(OP_READ) ] = { C 386 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = PM_BR_CMPL, C 387 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, C 389 arch/powerpc/perf/power9-pmu.c [ C(OP_WRITE) ] = { C 390 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = -1, C 391 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = -1, C 393 arch/powerpc/perf/power9-pmu.c [ C(OP_PREFETCH) ] = { C 394 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = -1, C 395 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = -1, C 398 arch/powerpc/perf/power9-pmu.c [ C(NODE) ] = { C 399 arch/powerpc/perf/power9-pmu.c [ C(OP_READ) ] = { C 400 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = -1, C 401 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = -1, C 403 arch/powerpc/perf/power9-pmu.c [ C(OP_WRITE) ] = { C 404 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = -1, C 405 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = -1, C 407 arch/powerpc/perf/power9-pmu.c [ C(OP_PREFETCH) ] = { C 408 arch/powerpc/perf/power9-pmu.c [ C(RESULT_ACCESS) ] = -1, C 409 arch/powerpc/perf/power9-pmu.c [ C(RESULT_MISS) ] = -1, C 435 arch/powerpc/perf/ppc970-pmu.c static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { C 436 arch/powerpc/perf/ppc970-pmu.c [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ C 437 arch/powerpc/perf/ppc970-pmu.c [C(OP_READ)] = { 0x8810, 0x3810 }, C 438 arch/powerpc/perf/ppc970-pmu.c [C(OP_WRITE)] = { 0x7810, 0x813 }, C 439 arch/powerpc/perf/ppc970-pmu.c [C(OP_PREFETCH)] = { 0x731, 0 }, C 441 arch/powerpc/perf/ppc970-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ C 442 arch/powerpc/perf/ppc970-pmu.c [C(OP_READ)] = { 0, 0 }, C 443 arch/powerpc/perf/ppc970-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 444 arch/powerpc/perf/ppc970-pmu.c [C(OP_PREFETCH)] = { 0, 0 }, C 446 arch/powerpc/perf/ppc970-pmu.c [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ C 447 arch/powerpc/perf/ppc970-pmu.c [C(OP_READ)] = { 0, 0 }, C 448 arch/powerpc/perf/ppc970-pmu.c [C(OP_WRITE)] = { 0, 0 }, C 449 arch/powerpc/perf/ppc970-pmu.c [C(OP_PREFETCH)] = { 0x733, 0 }, C 451 arch/powerpc/perf/ppc970-pmu.c [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 452 arch/powerpc/perf/ppc970-pmu.c [C(OP_READ)] = { 0, 0x704 }, C 453 arch/powerpc/perf/ppc970-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 454 arch/powerpc/perf/ppc970-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 456 arch/powerpc/perf/ppc970-pmu.c [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ C 457 arch/powerpc/perf/ppc970-pmu.c [C(OP_READ)] = { 0, 0x700 }, C 458 arch/powerpc/perf/ppc970-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 459 arch/powerpc/perf/ppc970-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 461 arch/powerpc/perf/ppc970-pmu.c [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ C 462 arch/powerpc/perf/ppc970-pmu.c [C(OP_READ)] = { 0x431, 0x327 }, C 463 arch/powerpc/perf/ppc970-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 464 arch/powerpc/perf/ppc970-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 466 arch/powerpc/perf/ppc970-pmu.c [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ C 467 arch/powerpc/perf/ppc970-pmu.c [C(OP_READ)] = { -1, -1 }, C 468 arch/powerpc/perf/ppc970-pmu.c [C(OP_WRITE)] = { -1, -1 }, C 469 arch/powerpc/perf/ppc970-pmu.c [C(OP_PREFETCH)] = { -1, -1 }, C 2414 arch/powerpc/xmon/ppc-opc.c #define C_MASK C(0xffff) C 6979 arch/powerpc/xmon/ppc-opc.c {"se_illegal", C(0), C_MASK, PPCVLE, 0, {}}, C 6980 arch/powerpc/xmon/ppc-opc.c {"se_isync", C(1), C_MASK, PPCVLE, 0, {}}, C 6981 arch/powerpc/xmon/ppc-opc.c {"se_sc", C(2), C_MASK, PPCVLE, 0, {}}, C 6986 arch/powerpc/xmon/ppc-opc.c {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}}, C 6987 arch/powerpc/xmon/ppc-opc.c {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}}, C 6988 arch/powerpc/xmon/ppc-opc.c {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}}, C 6989 arch/powerpc/xmon/ppc-opc.c {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}}, C 56 arch/riscv/kernel/perf_event.c [C(L1D)] = { C 57 arch/riscv/kernel/perf_event.c [C(OP_READ)] = { C 58 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 59 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 61 arch/riscv/kernel/perf_event.c [C(OP_WRITE)] = { C 62 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 63 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 65 arch/riscv/kernel/perf_event.c [C(OP_PREFETCH)] = { C 66 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 67 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 70 arch/riscv/kernel/perf_event.c [C(L1I)] = { C 71 arch/riscv/kernel/perf_event.c [C(OP_READ)] = { C 72 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 73 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 75 arch/riscv/kernel/perf_event.c [C(OP_WRITE)] = { C 76 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 77 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 79 arch/riscv/kernel/perf_event.c [C(OP_PREFETCH)] = { C 80 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 81 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 84 arch/riscv/kernel/perf_event.c [C(LL)] = { C 85 arch/riscv/kernel/perf_event.c [C(OP_READ)] = { C 86 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 87 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 89 arch/riscv/kernel/perf_event.c [C(OP_WRITE)] = { C 90 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 91 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 93 arch/riscv/kernel/perf_event.c [C(OP_PREFETCH)] = { C 94 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 95 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 98 arch/riscv/kernel/perf_event.c [C(DTLB)] = { C 99 arch/riscv/kernel/perf_event.c [C(OP_READ)] = { C 100 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 101 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 103 arch/riscv/kernel/perf_event.c [C(OP_WRITE)] = { C 104 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 105 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 107 arch/riscv/kernel/perf_event.c [C(OP_PREFETCH)] = { C 108 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 109 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 112 arch/riscv/kernel/perf_event.c [C(ITLB)] = { C 113 arch/riscv/kernel/perf_event.c [C(OP_READ)] = { C 114 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 115 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 117 arch/riscv/kernel/perf_event.c [C(OP_WRITE)] = { C 118 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 119 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 121 arch/riscv/kernel/perf_event.c [C(OP_PREFETCH)] = { C 122 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 123 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 126 arch/riscv/kernel/perf_event.c [C(BPU)] = { C 127 arch/riscv/kernel/perf_event.c [C(OP_READ)] = { C 128 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 129 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 131 arch/riscv/kernel/perf_event.c [C(OP_WRITE)] = { C 132 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 133 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 135 arch/riscv/kernel/perf_event.c [C(OP_PREFETCH)] = { C 136 arch/riscv/kernel/perf_event.c [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, C 137 arch/riscv/kernel/perf_event.c [C(RESULT_MISS)] = RISCV_OP_UNSUPP, C 22 arch/s390/boot/kaslr.c u8 C[112]; C 91 arch/s390/crypto/prng.c u8 C[112]; C 343 arch/s390/crypto/prng.c || memcmp(ws.C, C0, sizeof(C0)) != 0) { C 91 arch/sh/kernel/cpu/sh4/perf_event.c [ C(L1D) ] = { C 92 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_READ) ] = { C 93 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0x0001, C 94 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0x0004, C 96 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_WRITE) ] = { C 97 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0x0002, C 98 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0x0005, C 100 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_PREFETCH) ] = { C 101 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 102 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0, C 106 arch/sh/kernel/cpu/sh4/perf_event.c [ C(L1I) ] = { C 107 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_READ) ] = { C 108 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0x0006, C 109 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0x0008, C 111 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_WRITE) ] = { C 112 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 113 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = -1, C 115 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_PREFETCH) ] = { C 116 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 117 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0, C 121 arch/sh/kernel/cpu/sh4/perf_event.c [ C(LL) ] = { C 122 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_READ) ] = { C 123 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 124 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0, C 126 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_WRITE) ] = { C 127 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 128 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0, C 130 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_PREFETCH) ] = { C 131 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 132 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0, C 136 arch/sh/kernel/cpu/sh4/perf_event.c [ C(DTLB) ] = { C 137 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_READ) ] = { C 138 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 139 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0x0003, C 141 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_WRITE) ] = { C 142 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 143 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0, C 145 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_PREFETCH) ] = { C 146 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 147 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0, C 151 arch/sh/kernel/cpu/sh4/perf_event.c [ C(ITLB) ] = { C 152 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_READ) ] = { C 153 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 154 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = 0x0007, C 156 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_WRITE) ] = { C 157 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 158 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = -1, C 160 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_PREFETCH) ] = { C 161 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 162 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = -1, C 166 arch/sh/kernel/cpu/sh4/perf_event.c [ C(BPU) ] = { C 167 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_READ) ] = { C 168 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 169 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = -1, C 171 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_WRITE) ] = { C 172 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 173 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = -1, C 175 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_PREFETCH) ] = { C 176 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 177 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = -1, C 181 arch/sh/kernel/cpu/sh4/perf_event.c [ C(NODE) ] = { C 182 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_READ) ] = { C 183 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 184 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = -1, C 186 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_WRITE) ] = { C 187 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 188 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = -1, C 190 arch/sh/kernel/cpu/sh4/perf_event.c [ C(OP_PREFETCH) ] = { C 191 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 192 arch/sh/kernel/cpu/sh4/perf_event.c [ C(RESULT_MISS) ] = -1, C 116 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(L1D) ] = { C 117 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_READ) ] = { C 118 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0x0031, C 119 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0x0032, C 121 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_WRITE) ] = { C 122 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0x0039, C 123 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0x003a, C 125 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_PREFETCH) ] = { C 126 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 127 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0, C 131 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(L1I) ] = { C 132 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_READ) ] = { C 133 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0x0029, C 134 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0x002a, C 136 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_WRITE) ] = { C 137 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 138 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = -1, C 140 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_PREFETCH) ] = { C 141 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 142 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0, C 146 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(LL) ] = { C 147 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_READ) ] = { C 148 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0x0030, C 149 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0, C 151 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_WRITE) ] = { C 152 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0x0038, C 153 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0, C 155 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_PREFETCH) ] = { C 156 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 157 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0, C 161 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(DTLB) ] = { C 162 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_READ) ] = { C 163 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0x0222, C 164 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0x0220, C 166 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_WRITE) ] = { C 167 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 168 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0, C 170 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_PREFETCH) ] = { C 171 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 172 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0, C 176 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(ITLB) ] = { C 177 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_READ) ] = { C 178 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = 0, C 179 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = 0x02a0, C 181 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_WRITE) ] = { C 182 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 183 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = -1, C 185 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_PREFETCH) ] = { C 186 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 187 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = -1, C 191 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(BPU) ] = { C 192 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_READ) ] = { C 193 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 194 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = -1, C 196 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_WRITE) ] = { C 197 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 198 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = -1, C 200 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_PREFETCH) ] = { C 201 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 202 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = -1, C 206 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(NODE) ] = { C 207 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_READ) ] = { C 208 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 209 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = -1, C 211 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_WRITE) ] = { C 212 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 213 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = -1, C 215 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(OP_PREFETCH) ] = { C 216 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_ACCESS) ] = -1, C 217 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(RESULT_MISS) ] = -1, C 221 arch/sparc/kernel/perf_event.c [C(L1D)] = { C 222 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 223 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, C 224 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, C 226 arch/sparc/kernel/perf_event.c [C(OP_WRITE)] = { C 227 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER }, C 228 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x0a, PIC_UPPER }, C 230 arch/sparc/kernel/perf_event.c [C(OP_PREFETCH)] = { C 231 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 232 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 235 arch/sparc/kernel/perf_event.c [C(L1I)] = { C 236 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 237 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, C 238 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, C 240 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 241 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, C 242 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, C 244 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 245 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 246 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 249 arch/sparc/kernel/perf_event.c [C(LL)] = { C 250 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 251 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, }, C 252 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, }, C 254 arch/sparc/kernel/perf_event.c [C(OP_WRITE)] = { C 255 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER }, C 256 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x0c, PIC_UPPER }, C 258 arch/sparc/kernel/perf_event.c [C(OP_PREFETCH)] = { C 259 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 260 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 263 arch/sparc/kernel/perf_event.c [C(DTLB)] = { C 264 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 265 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 266 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x12, PIC_UPPER, }, C 268 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 269 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 270 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 272 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 273 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 274 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 277 arch/sparc/kernel/perf_event.c [C(ITLB)] = { C 278 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 279 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 280 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x11, PIC_UPPER, }, C 282 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 283 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 284 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 286 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 287 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 288 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 291 arch/sparc/kernel/perf_event.c [C(BPU)] = { C 292 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 293 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 294 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 296 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 297 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 298 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 300 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 301 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 302 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 305 arch/sparc/kernel/perf_event.c [C(NODE)] = { C 306 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 307 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 308 arch/sparc/kernel/perf_event.c [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 310 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 311 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 312 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 314 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 315 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 316 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 359 arch/sparc/kernel/perf_event.c [C(L1D)] = { C 360 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 361 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 362 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, C 364 arch/sparc/kernel/perf_event.c [C(OP_WRITE)] = { C 365 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 366 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, C 368 arch/sparc/kernel/perf_event.c [C(OP_PREFETCH)] = { C 369 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 370 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 373 arch/sparc/kernel/perf_event.c [C(L1I)] = { C 374 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 375 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER }, C 376 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x02, PIC_LOWER, }, C 378 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 379 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, C 380 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, C 382 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 383 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 384 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 387 arch/sparc/kernel/perf_event.c [C(LL)] = { C 388 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 389 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 390 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, C 392 arch/sparc/kernel/perf_event.c [C(OP_WRITE)] = { C 393 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 394 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, C 396 arch/sparc/kernel/perf_event.c [C(OP_PREFETCH)] = { C 397 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 398 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 401 arch/sparc/kernel/perf_event.c [C(DTLB)] = { C 402 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 403 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 404 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x05, PIC_LOWER, }, C 406 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 407 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 408 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 410 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 411 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 412 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 415 arch/sparc/kernel/perf_event.c [C(ITLB)] = { C 416 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 417 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 418 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x04, PIC_LOWER, }, C 420 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 421 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 422 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 424 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 425 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 426 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 429 arch/sparc/kernel/perf_event.c [C(BPU)] = { C 430 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 431 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 432 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 434 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 435 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 436 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 438 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 439 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 440 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 443 arch/sparc/kernel/perf_event.c [C(NODE)] = { C 444 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 445 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 446 arch/sparc/kernel/perf_event.c [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 448 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 449 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 450 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 452 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 453 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 454 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 494 arch/sparc/kernel/perf_event.c [C(L1D)] = { C 495 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 496 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, C 497 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, C 499 arch/sparc/kernel/perf_event.c [C(OP_WRITE)] = { C 500 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, C 501 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, C 503 arch/sparc/kernel/perf_event.c [C(OP_PREFETCH)] = { C 504 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 505 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 508 arch/sparc/kernel/perf_event.c [C(L1I)] = { C 509 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 510 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, }, C 511 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, }, C 513 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 514 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, C 515 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, C 517 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 518 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 519 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 522 arch/sparc/kernel/perf_event.c [C(LL)] = { C 523 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 524 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, C 525 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, }, C 527 arch/sparc/kernel/perf_event.c [C(OP_WRITE)] = { C 528 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, C 529 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, }, C 531 arch/sparc/kernel/perf_event.c [C(OP_PREFETCH)] = { C 532 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 533 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 536 arch/sparc/kernel/perf_event.c [C(DTLB)] = { C 537 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 538 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 539 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, }, C 541 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 542 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 543 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 545 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 546 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 547 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 550 arch/sparc/kernel/perf_event.c [C(ITLB)] = { C 551 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 552 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 553 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, }, C 555 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 556 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 557 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 559 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 560 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 561 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 564 arch/sparc/kernel/perf_event.c [C(BPU)] = { C 565 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 566 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 567 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 569 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 570 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 571 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 573 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 574 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 575 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 578 arch/sparc/kernel/perf_event.c [C(NODE)] = { C 579 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 580 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 581 arch/sparc/kernel/perf_event.c [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 583 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 584 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 585 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 587 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 588 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 589 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 631 arch/sparc/kernel/perf_event.c [C(L1D)] = { C 632 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 633 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 }, C 634 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { (16 << 6) | 0x07 }, C 636 arch/sparc/kernel/perf_event.c [C(OP_WRITE)] = { C 637 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 }, C 638 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { (16 << 6) | 0x07 }, C 640 arch/sparc/kernel/perf_event.c [C(OP_PREFETCH)] = { C 641 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 642 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 645 arch/sparc/kernel/perf_event.c [C(L1I)] = { C 646 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 647 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { (3 << 6) | 0x3f }, C 648 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { (11 << 6) | 0x03 }, C 650 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 651 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, C 652 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, C 654 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 655 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 656 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 659 arch/sparc/kernel/perf_event.c [C(LL)] = { C 660 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 661 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 }, C 662 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 664 arch/sparc/kernel/perf_event.c [C(OP_WRITE)] = { C 665 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 }, C 666 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 668 arch/sparc/kernel/perf_event.c [C(OP_PREFETCH)] = { C 669 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 670 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 673 arch/sparc/kernel/perf_event.c [C(DTLB)] = { C 674 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 675 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 676 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { (17 << 6) | 0x3f }, C 678 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 679 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 680 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 682 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 683 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 684 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 687 arch/sparc/kernel/perf_event.c [C(ITLB)] = { C 688 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 689 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 690 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { (6 << 6) | 0x3f }, C 692 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 693 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 694 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 696 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 697 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 698 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 701 arch/sparc/kernel/perf_event.c [C(BPU)] = { C 702 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 703 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 704 arch/sparc/kernel/perf_event.c [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, C 706 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 707 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 708 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 710 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 711 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 712 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 715 arch/sparc/kernel/perf_event.c [C(NODE)] = { C 716 arch/sparc/kernel/perf_event.c [C(OP_READ)] = { C 717 arch/sparc/kernel/perf_event.c [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, C 718 arch/sparc/kernel/perf_event.c [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 720 arch/sparc/kernel/perf_event.c [ C(OP_WRITE) ] = { C 721 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 722 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 724 arch/sparc/kernel/perf_event.c [ C(OP_PREFETCH) ] = { C 725 arch/sparc/kernel/perf_event.c [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, C 726 arch/sparc/kernel/perf_event.c [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, C 5 arch/x86/boot/code16gcc.h # This file is added to the assembler via -Wa when compiling 16-bit C code. C 22 arch/x86/events/amd/core.c [ C(L1D) ] = { C 23 arch/x86/events/amd/core.c [ C(OP_READ) ] = { C 24 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ C 25 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */ C 27 arch/x86/events/amd/core.c [ C(OP_WRITE) ] = { C 28 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0, C 29 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0, C 31 arch/x86/events/amd/core.c [ C(OP_PREFETCH) ] = { C 32 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ C 33 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ C 36 arch/x86/events/amd/core.c [ C(L1I ) ] = { C 37 arch/x86/events/amd/core.c [ C(OP_READ) ] = { C 38 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */ C 39 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */ C 41 arch/x86/events/amd/core.c [ C(OP_WRITE) ] = { C 42 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = -1, C 43 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = -1, C 45 arch/x86/events/amd/core.c [ C(OP_PREFETCH) ] = { C 46 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ C 47 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0, C 50 arch/x86/events/amd/core.c [ C(LL ) ] = { C 51 arch/x86/events/amd/core.c [ C(OP_READ) ] = { C 52 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ C 53 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ C 55 arch/x86/events/amd/core.c [ C(OP_WRITE) ] = { C 56 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ C 57 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0, C 59 arch/x86/events/amd/core.c [ C(OP_PREFETCH) ] = { C 60 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0, C 61 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0, C 64 arch/x86/events/amd/core.c [ C(DTLB) ] = { C 65 arch/x86/events/amd/core.c [ C(OP_READ) ] = { C 66 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ C 67 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */ C 69 arch/x86/events/amd/core.c [ C(OP_WRITE) ] = { C 70 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0, C 71 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0, C 73 arch/x86/events/amd/core.c [ C(OP_PREFETCH) ] = { C 74 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0, C 75 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0, C 78 arch/x86/events/amd/core.c [ C(ITLB) ] = { C 79 arch/x86/events/amd/core.c [ C(OP_READ) ] = { C 80 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */ C 81 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */ C 83 arch/x86/events/amd/core.c [ C(OP_WRITE) ] = { C 84 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = -1, C 85 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = -1, C 87 arch/x86/events/amd/core.c [ C(OP_PREFETCH) ] = { C 88 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = -1, C 89 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = -1, C 92 arch/x86/events/amd/core.c [ C(BPU ) ] = { C 93 arch/x86/events/amd/core.c [ C(OP_READ) ] = { C 94 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */ C 95 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */ C 97 arch/x86/events/amd/core.c [ C(OP_WRITE) ] = { C 98 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = -1, C 99 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = -1, C 101 arch/x86/events/amd/core.c [ C(OP_PREFETCH) ] = { C 102 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = -1, C 103 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = -1, C 106 arch/x86/events/amd/core.c [ C(NODE) ] = { C 107 arch/x86/events/amd/core.c [ C(OP_READ) ] = { C 108 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */ C 109 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = 0x98e9, /* CPU Request to Memory, r */ C 111 arch/x86/events/amd/core.c [ C(OP_WRITE) ] = { C 112 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = -1, C 113 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = -1, C 115 arch/x86/events/amd/core.c [ C(OP_PREFETCH) ] = { C 116 arch/x86/events/amd/core.c [ C(RESULT_ACCESS) ] = -1, C 117 arch/x86/events/amd/core.c [ C(RESULT_MISS) ] = -1, C 126 arch/x86/events/amd/core.c [C(L1D)] = { C 127 arch/x86/events/amd/core.c [C(OP_READ)] = { C 128 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0x0040, /* Data Cache Accesses */ C 129 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0xc860, /* L2$ access from DC Miss */ C 131 arch/x86/events/amd/core.c [C(OP_WRITE)] = { C 132 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0, C 133 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0, C 135 arch/x86/events/amd/core.c [C(OP_PREFETCH)] = { C 136 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0xff5a, /* h/w prefetch DC Fills */ C 137 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0, C 140 arch/x86/events/amd/core.c [C(L1I)] = { C 141 arch/x86/events/amd/core.c [C(OP_READ)] = { C 142 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0x0080, /* Instruction cache fetches */ C 143 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0x0081, /* Instruction cache misses */ C 145 arch/x86/events/amd/core.c [C(OP_WRITE)] = { C 146 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = -1, C 147 arch/x86/events/amd/core.c [C(RESULT_MISS)] = -1, C 149 arch/x86/events/amd/core.c [C(OP_PREFETCH)] = { C 150 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0, C 151 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0, C 154 arch/x86/events/amd/core.c [C(LL)] = { C 155 arch/x86/events/amd/core.c [C(OP_READ)] = { C 156 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0, C 157 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0, C 159 arch/x86/events/amd/core.c [C(OP_WRITE)] = { C 160 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0, C 161 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0, C 163 arch/x86/events/amd/core.c [C(OP_PREFETCH)] = { C 164 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0, C 165 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0, C 168 arch/x86/events/amd/core.c [C(DTLB)] = { C 169 arch/x86/events/amd/core.c [C(OP_READ)] = { C 170 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0xff45, /* All L2 DTLB accesses */ C 171 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0xf045, /* L2 DTLB misses (PT walks) */ C 173 arch/x86/events/amd/core.c [C(OP_WRITE)] = { C 174 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0, C 175 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0, C 177 arch/x86/events/amd/core.c [C(OP_PREFETCH)] = { C 178 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0, C 179 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0, C 182 arch/x86/events/amd/core.c [C(ITLB)] = { C 183 arch/x86/events/amd/core.c [C(OP_READ)] = { C 184 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0x0084, /* L1 ITLB misses, L2 ITLB hits */ C 185 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0xff85, /* L1 ITLB misses, L2 misses */ C 187 arch/x86/events/amd/core.c [C(OP_WRITE)] = { C 188 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = -1, C 189 arch/x86/events/amd/core.c [C(RESULT_MISS)] = -1, C 191 arch/x86/events/amd/core.c [C(OP_PREFETCH)] = { C 192 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = -1, C 193 arch/x86/events/amd/core.c [C(RESULT_MISS)] = -1, C 196 arch/x86/events/amd/core.c [C(BPU)] = { C 197 arch/x86/events/amd/core.c [C(OP_READ)] = { C 198 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0x00c2, /* Retired Branch Instr. */ C 199 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0x00c3, /* Retired Mispredicted BI */ C 201 arch/x86/events/amd/core.c [C(OP_WRITE)] = { C 202 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = -1, C 203 arch/x86/events/amd/core.c [C(RESULT_MISS)] = -1, C 205 arch/x86/events/amd/core.c [C(OP_PREFETCH)] = { C 206 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = -1, C 207 arch/x86/events/amd/core.c [C(RESULT_MISS)] = -1, C 210 arch/x86/events/amd/core.c [C(NODE)] = { C 211 arch/x86/events/amd/core.c [C(OP_READ)] = { C 212 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = 0, C 213 arch/x86/events/amd/core.c [C(RESULT_MISS)] = 0, C 215 arch/x86/events/amd/core.c [C(OP_WRITE)] = { C 216 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = -1, C 217 arch/x86/events/amd/core.c [C(RESULT_MISS)] = -1, C 219 arch/x86/events/amd/core.c [C(OP_PREFETCH)] = { C 220 arch/x86/events/amd/core.c [C(RESULT_ACCESS)] = -1, C 221 arch/x86/events/amd/core.c [C(RESULT_MISS)] = -1, C 425 arch/x86/events/intel/core.c [ C(L1D ) ] = { C 426 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 427 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ C 428 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ C 430 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 431 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ C 432 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 434 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 435 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 436 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 439 arch/x86/events/intel/core.c [ C(L1I ) ] = { C 440 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 441 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 442 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ C 444 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 445 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 446 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 448 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 449 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 450 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 453 arch/x86/events/intel/core.c [ C(LL ) ] = { C 454 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 455 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 456 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 458 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 459 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 460 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 462 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 463 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 464 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 467 arch/x86/events/intel/core.c [ C(DTLB) ] = { C 468 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 469 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ C 470 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ C 472 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 473 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ C 474 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ C 476 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 477 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 478 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 481 arch/x86/events/intel/core.c [ C(ITLB) ] = { C 482 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 483 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ C 484 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ C 486 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 487 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 488 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 490 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 491 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 492 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 495 arch/x86/events/intel/core.c [ C(BPU ) ] = { C 496 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 497 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ C 498 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ C 500 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 501 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 502 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 504 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 505 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 506 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 509 arch/x86/events/intel/core.c [ C(NODE) ] = { C 510 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 511 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 512 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 514 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 515 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 516 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 518 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 519 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 520 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 530 arch/x86/events/intel/core.c [ C(LL ) ] = { C 531 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 532 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| C 534 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SKL_DEMAND_READ| C 538 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 539 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| C 541 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| C 545 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 546 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 547 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 550 arch/x86/events/intel/core.c [ C(NODE) ] = { C 551 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 552 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| C 554 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SKL_DEMAND_READ| C 557 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 558 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| C 560 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| C 563 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 564 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 565 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 618 arch/x86/events/intel/core.c [ C(LL ) ] = { C 619 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 620 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, C 621 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, C 623 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 624 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, C 625 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, C 627 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 628 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, C 629 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, C 632 arch/x86/events/intel/core.c [ C(NODE) ] = { C 633 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 634 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, C 635 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, C 637 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 638 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, C 639 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, C 641 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 642 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, C 643 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, C 653 arch/x86/events/intel/core.c [ C(L1D) ] = { C 654 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 655 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ C 656 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ C 658 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 659 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ C 660 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ C 662 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 663 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 664 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ C 667 arch/x86/events/intel/core.c [ C(L1I ) ] = { C 668 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 669 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 670 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ C 672 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 673 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 674 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 676 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 677 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 678 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 681 arch/x86/events/intel/core.c [ C(LL ) ] = { C 682 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 684 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 686 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 688 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 690 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 692 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 694 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 696 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 698 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 701 arch/x86/events/intel/core.c [ C(DTLB) ] = { C 702 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 703 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ C 704 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ C 706 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 707 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ C 708 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ C 710 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 711 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 712 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 715 arch/x86/events/intel/core.c [ C(ITLB) ] = { C 716 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 717 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ C 718 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ C 720 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 721 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 722 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 724 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 725 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 726 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 729 arch/x86/events/intel/core.c [ C(BPU ) ] = { C 730 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 731 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ C 732 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ C 734 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 735 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 736 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 738 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 739 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 740 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 743 arch/x86/events/intel/core.c [ C(NODE) ] = { C 744 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 745 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 746 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 748 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 749 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 750 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 752 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 753 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 754 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 809 arch/x86/events/intel/core.c [ C(L1D ) ] = { C 810 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 811 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ C 812 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ C 814 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 815 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ C 816 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 818 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 819 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 820 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 823 arch/x86/events/intel/core.c [ C(L1I ) ] = { C 824 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 825 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 826 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ C 828 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 829 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 830 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 832 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 833 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 834 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 837 arch/x86/events/intel/core.c [ C(LL ) ] = { C 838 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 839 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 840 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 842 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 843 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 844 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 846 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 847 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 848 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 851 arch/x86/events/intel/core.c [ C(DTLB) ] = { C 852 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 853 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ C 854 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ C 856 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 857 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ C 858 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ C 860 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 861 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 862 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 865 arch/x86/events/intel/core.c [ C(ITLB) ] = { C 866 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 867 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ C 868 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ C 870 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 871 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 872 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 874 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 875 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 876 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 879 arch/x86/events/intel/core.c [ C(BPU ) ] = { C 880 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 881 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ C 882 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ C 884 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 885 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 886 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 888 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 889 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 890 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 893 arch/x86/events/intel/core.c [ C(NODE) ] = { C 894 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 895 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 896 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 898 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 899 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 900 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ C 902 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 903 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 904 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 914 arch/x86/events/intel/core.c [ C(LL ) ] = { C 915 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 916 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| C 918 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = HSW_DEMAND_READ| C 921 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 922 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| C 924 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| C 927 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 928 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 929 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 932 arch/x86/events/intel/core.c [ C(NODE) ] = { C 933 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 934 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| C 937 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = HSW_DEMAND_READ| C 941 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 942 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| C 945 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| C 949 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 950 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 951 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 961 arch/x86/events/intel/core.c [ C(L1D) ] = { C 962 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 963 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ C 964 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ C 966 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 967 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ C 968 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ C 970 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 971 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ C 972 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ C 975 arch/x86/events/intel/core.c [ C(L1I ) ] = { C 976 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 977 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ C 978 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ C 980 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 981 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 982 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 984 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 985 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 986 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 989 arch/x86/events/intel/core.c [ C(LL ) ] = { C 990 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 992 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 994 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1000 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1002 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1004 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1006 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1008 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1010 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1013 arch/x86/events/intel/core.c [ C(DTLB) ] = { C 1014 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1015 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ C 1016 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ C 1018 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1019 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ C 1020 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ C 1022 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1023 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 1024 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 1027 arch/x86/events/intel/core.c [ C(ITLB) ] = { C 1028 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1029 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ C 1030 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ C 1032 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1033 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1034 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1036 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1037 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1038 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1041 arch/x86/events/intel/core.c [ C(BPU ) ] = { C 1042 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1043 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ C 1044 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ C 1046 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1047 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1048 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1050 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1051 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1052 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1055 arch/x86/events/intel/core.c [ C(NODE) ] = { C 1056 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1057 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1058 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1060 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1061 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1062 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1064 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1065 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1066 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1109 arch/x86/events/intel/core.c [ C(LL ) ] = { C 1110 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1111 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, C 1112 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, C 1114 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1115 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, C 1116 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, C 1118 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1119 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, C 1120 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, C 1123 arch/x86/events/intel/core.c [ C(NODE) ] = { C 1124 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1125 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, C 1126 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, C 1128 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1129 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, C 1130 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, C 1132 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1133 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, C 1134 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, C 1144 arch/x86/events/intel/core.c [ C(L1D) ] = { C 1145 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1146 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ C 1147 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ C 1149 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1150 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ C 1151 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ C 1153 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1154 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ C 1155 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ C 1158 arch/x86/events/intel/core.c [ C(L1I ) ] = { C 1159 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1160 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ C 1161 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ C 1163 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1164 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1165 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1167 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1168 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 1169 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 1172 arch/x86/events/intel/core.c [ C(LL ) ] = { C 1173 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1175 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1177 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1183 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1185 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1187 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1189 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1191 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1193 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1196 arch/x86/events/intel/core.c [ C(DTLB) ] = { C 1197 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1198 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ C 1199 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ C 1201 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1202 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ C 1203 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ C 1205 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1206 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 1207 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0, C 1210 arch/x86/events/intel/core.c [ C(ITLB) ] = { C 1211 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1212 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ C 1213 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ C 1215 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1216 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1217 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1219 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1220 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1221 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1224 arch/x86/events/intel/core.c [ C(BPU ) ] = { C 1225 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1226 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ C 1227 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ C 1229 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1230 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1231 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1233 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1234 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1235 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1238 arch/x86/events/intel/core.c [ C(NODE) ] = { C 1239 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1240 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1241 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1243 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1244 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1245 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1247 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1248 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1249 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1259 arch/x86/events/intel/core.c [ C(L1D) ] = { C 1260 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1261 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ C 1262 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ C 1264 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1265 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ C 1266 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ C 1268 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1269 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ C 1270 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1273 arch/x86/events/intel/core.c [ C(L1I ) ] = { C 1274 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1275 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ C 1276 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ C 1278 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1279 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1280 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1282 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1283 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1284 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1287 arch/x86/events/intel/core.c [ C(LL ) ] = { C 1288 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1289 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ C 1290 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ C 1292 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1293 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ C 1294 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ C 1296 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1297 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1298 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1301 arch/x86/events/intel/core.c [ C(DTLB) ] = { C 1302 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1303 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ C 1304 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ C 1306 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1307 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ C 1308 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ C 1310 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1311 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1312 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1315 arch/x86/events/intel/core.c [ C(ITLB) ] = { C 1316 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1317 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ C 1318 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ C 1320 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1321 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1322 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1324 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1325 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1326 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1329 arch/x86/events/intel/core.c [ C(BPU ) ] = { C 1330 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1331 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ C 1332 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ C 1334 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1335 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1336 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1338 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1339 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1340 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1350 arch/x86/events/intel/core.c [ C(L1D) ] = { C 1351 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1352 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ C 1353 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1355 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1356 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ C 1357 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1359 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1360 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0, C 1361 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1364 arch/x86/events/intel/core.c [ C(L1I ) ] = { C 1365 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1366 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ C 1367 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ C 1369 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1370 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1371 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1373 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1374 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1375 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1378 arch/x86/events/intel/core.c [ C(LL ) ] = { C 1379 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1380 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ C 1381 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ C 1383 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1384 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ C 1385 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ C 1387 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1388 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1389 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1392 arch/x86/events/intel/core.c [ C(DTLB) ] = { C 1393 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1394 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ C 1395 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ C 1397 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1398 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ C 1399 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ C 1401 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1402 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1403 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1406 arch/x86/events/intel/core.c [ C(ITLB) ] = { C 1407 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1408 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ C 1409 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ C 1411 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1412 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1413 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1415 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1416 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1417 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1420 arch/x86/events/intel/core.c [ C(BPU ) ] = { C 1421 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1422 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ C 1423 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ C 1425 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1426 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1427 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1429 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1430 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1431 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1480 arch/x86/events/intel/core.c [ C(LL ) ] = { C 1481 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1482 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, C 1483 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1485 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1486 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, C 1487 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, C 1489 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1490 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, C 1491 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, C 1501 arch/x86/events/intel/core.c [ C(L1D) ] = { C 1502 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1503 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1504 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ C 1506 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1507 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1508 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1510 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1511 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1512 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1515 arch/x86/events/intel/core.c [ C(L1I ) ] = { C 1516 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1517 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ C 1518 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ C 1520 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1521 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1522 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1524 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1525 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1526 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1529 arch/x86/events/intel/core.c [ C(LL ) ] = { C 1530 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1532 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1533 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1535 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1537 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1539 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1541 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1543 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x01b7, C 1545 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x01b7, C 1548 arch/x86/events/intel/core.c [ C(DTLB) ] = { C 1549 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1550 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1551 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ C 1553 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1554 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1555 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1557 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1558 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0, C 1559 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0, C 1562 arch/x86/events/intel/core.c [ C(ITLB) ] = { C 1563 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1564 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ C 1565 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ C 1567 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1568 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1569 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1571 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1572 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1573 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1576 arch/x86/events/intel/core.c [ C(BPU ) ] = { C 1577 arch/x86/events/intel/core.c [ C(OP_READ) ] = { C 1578 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ C 1579 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ C 1581 arch/x86/events/intel/core.c [ C(OP_WRITE) ] = { C 1582 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1583 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1585 arch/x86/events/intel/core.c [ C(OP_PREFETCH) ] = { C 1586 arch/x86/events/intel/core.c [ C(RESULT_ACCESS) ] = -1, C 1587 arch/x86/events/intel/core.c [ C(RESULT_MISS) ] = -1, C 1635 arch/x86/events/intel/core.c [C(L1D)] = { C 1636 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1637 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ C 1638 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1640 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1641 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ C 1642 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1644 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1645 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x0, C 1646 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1649 arch/x86/events/intel/core.c [C(L1I)] = { C 1650 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1651 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ C 1652 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ C 1654 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1655 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = -1, C 1656 arch/x86/events/intel/core.c [C(RESULT_MISS)] = -1, C 1658 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1659 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x0, C 1660 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1663 arch/x86/events/intel/core.c [C(LL)] = { C 1664 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1665 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ C 1666 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ C 1668 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1669 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ C 1670 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ C 1672 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1673 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ C 1674 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ C 1677 arch/x86/events/intel/core.c [C(DTLB)] = { C 1678 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1679 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ C 1680 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1682 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1683 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ C 1684 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1686 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1687 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x0, C 1688 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1691 arch/x86/events/intel/core.c [C(ITLB)] = { C 1692 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1693 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ C 1694 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ C 1696 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1697 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = -1, C 1698 arch/x86/events/intel/core.c [C(RESULT_MISS)] = -1, C 1700 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1701 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = -1, C 1702 arch/x86/events/intel/core.c [C(RESULT_MISS)] = -1, C 1705 arch/x86/events/intel/core.c [C(BPU)] = { C 1706 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1707 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ C 1708 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ C 1710 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1711 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = -1, C 1712 arch/x86/events/intel/core.c [C(RESULT_MISS)] = -1, C 1714 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1715 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = -1, C 1716 arch/x86/events/intel/core.c [C(RESULT_MISS)] = -1, C 1725 arch/x86/events/intel/core.c [C(LL)] = { C 1726 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1727 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = GLM_DEMAND_READ| C 1729 arch/x86/events/intel/core.c [C(RESULT_MISS)] = GLM_DEMAND_READ| C 1732 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1733 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| C 1735 arch/x86/events/intel/core.c [C(RESULT_MISS)] = GLM_DEMAND_WRITE| C 1738 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1739 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| C 1741 arch/x86/events/intel/core.c [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| C 1751 arch/x86/events/intel/core.c [C(L1D)] = { C 1752 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1753 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ C 1754 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1756 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1757 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ C 1758 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1760 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1761 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x0, C 1762 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1765 arch/x86/events/intel/core.c [C(L1I)] = { C 1766 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1767 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ C 1768 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ C 1770 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1771 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = -1, C 1772 arch/x86/events/intel/core.c [C(RESULT_MISS)] = -1, C 1774 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1775 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x0, C 1776 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1779 arch/x86/events/intel/core.c [C(LL)] = { C 1780 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1781 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ C 1782 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ C 1784 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1785 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ C 1786 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ C 1788 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1789 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x0, C 1790 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1793 arch/x86/events/intel/core.c [C(DTLB)] = { C 1794 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1795 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ C 1796 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ C 1798 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1799 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ C 1800 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ C 1802 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1803 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x0, C 1804 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1807 arch/x86/events/intel/core.c [C(ITLB)] = { C 1808 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1809 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ C 1810 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ C 1812 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1813 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = -1, C 1814 arch/x86/events/intel/core.c [C(RESULT_MISS)] = -1, C 1816 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1817 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = -1, C 1818 arch/x86/events/intel/core.c [C(RESULT_MISS)] = -1, C 1821 arch/x86/events/intel/core.c [C(BPU)] = { C 1822 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1823 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ C 1824 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ C 1826 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1827 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = -1, C 1828 arch/x86/events/intel/core.c [C(RESULT_MISS)] = -1, C 1830 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1831 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = -1, C 1832 arch/x86/events/intel/core.c [C(RESULT_MISS)] = -1, C 1841 arch/x86/events/intel/core.c [C(LL)] = { C 1842 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1843 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = GLM_DEMAND_READ| C 1845 arch/x86/events/intel/core.c [C(RESULT_MISS)] = GLM_DEMAND_READ| C 1848 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1849 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| C 1851 arch/x86/events/intel/core.c [C(RESULT_MISS)] = GLM_DEMAND_WRITE| C 1854 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1855 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x0, C 1856 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1873 arch/x86/events/intel/core.c [C(LL)] = { C 1874 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1875 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = TNT_DEMAND_READ| C 1877 arch/x86/events/intel/core.c [C(RESULT_MISS)] = TNT_DEMAND_READ| C 1880 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1881 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| C 1883 arch/x86/events/intel/core.c [C(RESULT_MISS)] = TNT_DEMAND_WRITE| C 1886 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1887 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = 0x0, C 1888 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0x0, C 1920 arch/x86/events/intel/core.c [C(LL)] = { C 1921 arch/x86/events/intel/core.c [C(OP_READ)] = { C 1922 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, C 1923 arch/x86/events/intel/core.c [C(RESULT_MISS)] = 0, C 1925 arch/x86/events/intel/core.c [C(OP_WRITE)] = { C 1926 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, C 1927 arch/x86/events/intel/core.c [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, C 1929 arch/x86/events/intel/core.c [C(OP_PREFETCH)] = { C 1930 arch/x86/events/intel/core.c [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, C 1931 arch/x86/events/intel/core.c [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, C 4755 arch/x86/events/intel/core.c hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; C 4852 arch/x86/events/intel/core.c hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ C 4928 arch/x86/events/intel/core.c hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | C 4930 arch/x86/events/intel/core.c hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| C 4932 arch/x86/events/intel/core.c hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| C 4934 arch/x86/events/intel/core.c hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| C 5042 arch/x86/events/intel/core.c hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; C 26 arch/x86/events/intel/knc.c [ C(L1D) ] = { C 27 arch/x86/events/intel/knc.c [ C(OP_READ) ] = { C 32 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT, C 34 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x0003, /* DATA_READ_MISS */ C 36 arch/x86/events/intel/knc.c [ C(OP_WRITE) ] = { C 37 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = 0x0001, /* DATA_WRITE */ C 38 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x0004, /* DATA_WRITE_MISS */ C 40 arch/x86/events/intel/knc.c [ C(OP_PREFETCH) ] = { C 41 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = 0x0011, /* L1_DATA_PF1 */ C 42 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x001c, /* L1_DATA_PF1_MISS */ C 45 arch/x86/events/intel/knc.c [ C(L1I ) ] = { C 46 arch/x86/events/intel/knc.c [ C(OP_READ) ] = { C 47 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = 0x000c, /* CODE_READ */ C 48 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x000e, /* CODE_CACHE_MISS */ C 50 arch/x86/events/intel/knc.c [ C(OP_WRITE) ] = { C 51 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = -1, C 52 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = -1, C 54 arch/x86/events/intel/knc.c [ C(OP_PREFETCH) ] = { C 55 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = 0x0, C 56 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x0, C 59 arch/x86/events/intel/knc.c [ C(LL ) ] = { C 60 arch/x86/events/intel/knc.c [ C(OP_READ) ] = { C 61 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = 0, C 62 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x10cb, /* L2_READ_MISS */ C 64 arch/x86/events/intel/knc.c [ C(OP_WRITE) ] = { C 65 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = 0x10cc, /* L2_WRITE_HIT */ C 66 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0, C 68 arch/x86/events/intel/knc.c [ C(OP_PREFETCH) ] = { C 69 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = 0x10fc, /* L2_DATA_PF2 */ C 70 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x10fe, /* L2_DATA_PF2_MISS */ C 73 arch/x86/events/intel/knc.c [ C(DTLB) ] = { C 74 arch/x86/events/intel/knc.c [ C(OP_READ) ] = { C 75 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT, C 78 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x0002, /* DATA_PAGE_WALK */ C 80 arch/x86/events/intel/knc.c [ C(OP_WRITE) ] = { C 81 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = 0x0001, /* DATA_WRITE */ C 82 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x0002, /* DATA_PAGE_WALK */ C 84 arch/x86/events/intel/knc.c [ C(OP_PREFETCH) ] = { C 85 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = 0x0, C 86 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x0, C 89 arch/x86/events/intel/knc.c [ C(ITLB) ] = { C 90 arch/x86/events/intel/knc.c [ C(OP_READ) ] = { C 91 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = 0x000c, /* CODE_READ */ C 92 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x000d, /* CODE_PAGE_WALK */ C 94 arch/x86/events/intel/knc.c [ C(OP_WRITE) ] = { C 95 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = -1, C 96 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = -1, C 98 arch/x86/events/intel/knc.c [ C(OP_PREFETCH) ] = { C 99 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = -1, C 100 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = -1, C 103 arch/x86/events/intel/knc.c [ C(BPU ) ] = { C 104 arch/x86/events/intel/knc.c [ C(OP_READ) ] = { C 105 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = 0x0012, /* BRANCHES */ C 106 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = 0x002b, /* BRANCHES_MISPREDICTED */ C 108 arch/x86/events/intel/knc.c [ C(OP_WRITE) ] = { C 109 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = -1, C 110 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = -1, C 112 arch/x86/events/intel/knc.c [ C(OP_PREFETCH) ] = { C 113 arch/x86/events/intel/knc.c [ C(RESULT_ACCESS) ] = -1, C 114 arch/x86/events/intel/knc.c [ C(RESULT_MISS) ] = -1, C 519 arch/x86/events/intel/p4.c [ C(L1D ) ] = { C 520 arch/x86/events/intel/p4.c [ C(OP_READ) ] = { C 521 arch/x86/events/intel/p4.c [ C(RESULT_ACCESS) ] = 0x0, C 522 arch/x86/events/intel/p4.c [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS, C 526 arch/x86/events/intel/p4.c [ C(LL ) ] = { C 527 arch/x86/events/intel/p4.c [ C(OP_READ) ] = { C 528 arch/x86/events/intel/p4.c [ C(RESULT_ACCESS) ] = 0x0, C 529 arch/x86/events/intel/p4.c [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS, C 533 arch/x86/events/intel/p4.c [ C(DTLB) ] = { C 534 arch/x86/events/intel/p4.c [ C(OP_READ) ] = { C 535 arch/x86/events/intel/p4.c [ C(RESULT_ACCESS) ] = 0x0, C 536 arch/x86/events/intel/p4.c [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS, C 539 arch/x86/events/intel/p4.c [ C(OP_WRITE) ] = { C 540 arch/x86/events/intel/p4.c [ C(RESULT_ACCESS) ] = 0x0, C 541 arch/x86/events/intel/p4.c [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS, C 545 arch/x86/events/intel/p4.c [ C(ITLB) ] = { C 546 arch/x86/events/intel/p4.c [ C(OP_READ) ] = { C 547 arch/x86/events/intel/p4.c [ C(RESULT_ACCESS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, HIT, C 549 arch/x86/events/intel/p4.c [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, MISS, C 552 arch/x86/events/intel/p4.c [ C(OP_WRITE) ] = { C 553 arch/x86/events/intel/p4.c [ C(RESULT_ACCESS) ] = -1, C 554 arch/x86/events/intel/p4.c [ C(RESULT_MISS) ] = -1, C 556 arch/x86/events/intel/p4.c [ C(OP_PREFETCH) ] = { C 557 arch/x86/events/intel/p4.c [ C(RESULT_ACCESS) ] = -1, C 558 arch/x86/events/intel/p4.c [ C(RESULT_MISS) ] = -1, C 561 arch/x86/events/intel/p4.c [ C(NODE) ] = { C 562 arch/x86/events/intel/p4.c [ C(OP_READ) ] = { C 563 arch/x86/events/intel/p4.c [ C(RESULT_ACCESS) ] = -1, C 564 arch/x86/events/intel/p4.c [ C(RESULT_MISS) ] = -1, C 566 arch/x86/events/intel/p4.c [ C(OP_WRITE) ] = { C 567 arch/x86/events/intel/p4.c [ C(RESULT_ACCESS) ] = -1, C 568 arch/x86/events/intel/p4.c [ C(RESULT_MISS) ] = -1, C 570 arch/x86/events/intel/p4.c [ C(OP_PREFETCH) ] = { C 571 arch/x86/events/intel/p4.c [ C(RESULT_ACCESS) ] = -1, C 572 arch/x86/events/intel/p4.c [ C(RESULT_MISS) ] = -1, C 28 arch/x86/events/intel/p6.c [ C(L1D) ] = { C 29 arch/x86/events/intel/p6.c [ C(OP_READ) ] = { C 30 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */ C 31 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */ C 33 arch/x86/events/intel/p6.c [ C(OP_WRITE) ] = { C 34 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0, C 35 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */ C 37 arch/x86/events/intel/p6.c [ C(OP_PREFETCH) ] = { C 38 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0, C 39 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0, C 42 arch/x86/events/intel/p6.c [ C(L1I ) ] = { C 43 arch/x86/events/intel/p6.c [ C(OP_READ) ] = { C 44 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */ C 45 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0x0f28, /* L2_IFETCH:M:E:S:I */ C 47 arch/x86/events/intel/p6.c [ C(OP_WRITE) ] = { C 48 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = -1, C 49 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = -1, C 51 arch/x86/events/intel/p6.c [ C(OP_PREFETCH) ] = { C 52 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0, C 53 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0, C 56 arch/x86/events/intel/p6.c [ C(LL ) ] = { C 57 arch/x86/events/intel/p6.c [ C(OP_READ) ] = { C 58 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0, C 59 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0, C 61 arch/x86/events/intel/p6.c [ C(OP_WRITE) ] = { C 62 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0, C 63 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0x0025, /* L2_M_LINES_INM */ C 65 arch/x86/events/intel/p6.c [ C(OP_PREFETCH) ] = { C 66 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0, C 67 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0, C 70 arch/x86/events/intel/p6.c [ C(DTLB) ] = { C 71 arch/x86/events/intel/p6.c [ C(OP_READ) ] = { C 72 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */ C 73 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0, C 75 arch/x86/events/intel/p6.c [ C(OP_WRITE) ] = { C 76 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0, C 77 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0, C 79 arch/x86/events/intel/p6.c [ C(OP_PREFETCH) ] = { C 80 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0, C 81 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0, C 84 arch/x86/events/intel/p6.c [ C(ITLB) ] = { C 85 arch/x86/events/intel/p6.c [ C(OP_READ) ] = { C 86 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */ C 87 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0x0085, /* ITLB_MISS */ C 89 arch/x86/events/intel/p6.c [ C(OP_WRITE) ] = { C 90 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = -1, C 91 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = -1, C 93 arch/x86/events/intel/p6.c [ C(OP_PREFETCH) ] = { C 94 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = -1, C 95 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = -1, C 98 arch/x86/events/intel/p6.c [ C(BPU ) ] = { C 99 arch/x86/events/intel/p6.c [ C(OP_READ) ] = { C 100 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED */ C 101 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISS_PRED_RETIRED */ C 103 arch/x86/events/intel/p6.c [ C(OP_WRITE) ] = { C 104 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = -1, C 105 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = -1, C 107 arch/x86/events/intel/p6.c [ C(OP_PREFETCH) ] = { C 108 arch/x86/events/intel/p6.c [ C(RESULT_ACCESS) ] = -1, C 109 arch/x86/events/intel/p6.c [ C(RESULT_MISS) ] = -1, C 1142 arch/x86/xen/enlighten_pv.c C(device); C 1143 arch/x86/xen/enlighten_pv.c C(version); C 1144 arch/x86/xen/enlighten_pv.c C(interface_support); C 1145 arch/x86/xen/enlighten_pv.c C(legacy_max_cylinder); C 1146 arch/x86/xen/enlighten_pv.c C(legacy_max_head); C 1147 arch/x86/xen/enlighten_pv.c C(legacy_sectors_per_track); C 73 arch/xtensa/kernel/perf_event.c static const u32 xtensa_cache_ctl[][C(OP_MAX)][C(RESULT_MAX)] = { C 74 arch/xtensa/kernel/perf_event.c [C(L1D)] = { C 75 arch/xtensa/kernel/perf_event.c [C(OP_READ)] = { C 76 arch/xtensa/kernel/perf_event.c [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(10, 0x1), C 77 arch/xtensa/kernel/perf_event.c [C(RESULT_MISS)] = XTENSA_PMU_MASK(10, 0x2), C 79 arch/xtensa/kernel/perf_event.c [C(OP_WRITE)] = { C 80 arch/xtensa/kernel/perf_event.c [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(11, 0x1), C 81 arch/xtensa/kernel/perf_event.c [C(RESULT_MISS)] = XTENSA_PMU_MASK(11, 0x2), C 84 arch/xtensa/kernel/perf_event.c [C(L1I)] = { C 85 arch/xtensa/kernel/perf_event.c [C(OP_READ)] = { C 86 arch/xtensa/kernel/perf_event.c [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(8, 0x1), C 87 arch/xtensa/kernel/perf_event.c [C(RESULT_MISS)] = XTENSA_PMU_MASK(8, 0x2), C 90 arch/xtensa/kernel/perf_event.c [C(DTLB)] = { C 91 arch/xtensa/kernel/perf_event.c [C(OP_READ)] = { C 92 arch/xtensa/kernel/perf_event.c [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(9, 0x1), C 93 arch/xtensa/kernel/perf_event.c [C(RESULT_MISS)] = XTENSA_PMU_MASK(9, 0x8), C 96 arch/xtensa/kernel/perf_event.c [C(ITLB)] = { C 97 arch/xtensa/kernel/perf_event.c [C(OP_READ)] = { C 98 arch/xtensa/kernel/perf_event.c [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(7, 0x1), C 99 arch/xtensa/kernel/perf_event.c [C(RESULT_MISS)] = XTENSA_PMU_MASK(7, 0x8), C 114 arch/xtensa/kernel/perf_event.c cache_op >= C(OP_MAX) || C 115 arch/xtensa/kernel/perf_event.c cache_result >= C(RESULT_MAX)) C 552 crypto/drbg.c ret = crypto_skcipher_setkey(drbg->ctr_handle, drbg->C, C 665 crypto/drbg.c drbg_kcapi_hmacsetkey(drbg, drbg->C); C 686 crypto/drbg.c ret = drbg_kcapi_hash(drbg, drbg->C, &seedlist); C 689 crypto/drbg.c drbg_kcapi_hmacsetkey(drbg, drbg->C); C 894 crypto/drbg.c ret = drbg_hash_df(drbg, drbg->C, drbg_statelen(drbg), &datalist2); C 1012 crypto/drbg.c drbg->C, drbg_statelen(drbg)); C 1193 crypto/drbg.c memset(drbg->C, 0, drbg_statelen(drbg)); C 1214 crypto/drbg.c drbg->C = NULL; C 1272 crypto/drbg.c drbg->C = PTR_ALIGN(drbg->Cbuf, ret + 1); C 28 crypto/streebog_generic.c static const struct streebog_uint512 C[12] = { C 904 crypto/streebog_generic.c streebog_xlps(Ki, &C[i], Ki); C 967 crypto/streebog_generic.c streebog_xlps(&Ki, &C[11], &Ki); C 782 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), B(0), B(1), B(2), R(0), C 784 drivers/edac/pnd2_edac.c R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14), C 792 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), B(0), B(1), B(2), R(0), C 794 drivers/edac/pnd2_edac.c R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14), C 802 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), B(0), B(1), B(2), R(0), C 804 drivers/edac/pnd2_edac.c R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14), C 812 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), B(0), B(1), B(2), R(0), C 814 drivers/edac/pnd2_edac.c R(10), C(7), C(8), C(9), R(11), RS, C(11), R(12), R(13), C 822 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), C(7), B(0), B(1), B(2), C 824 drivers/edac/pnd2_edac.c R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14), C 832 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), C(7), B(0), B(1), B(2), C 834 drivers/edac/pnd2_edac.c R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14), C 842 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), C(7), B(0), B(1), B(2), C 844 drivers/edac/pnd2_edac.c R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14), C 852 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), C(7), B(0), B(1), B(2), C 854 drivers/edac/pnd2_edac.c R(9), R(10), C(8), C(9), R(11), RS, C(11), R(12), R(13), C 862 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), C(7), C(8), B(0), B(1), C 864 drivers/edac/pnd2_edac.c R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14), C 872 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), C(7), C(8), B(0), B(1), C 874 drivers/edac/pnd2_edac.c R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14), C 882 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), C(7), C(8), B(0), B(1), C 884 drivers/edac/pnd2_edac.c R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14), C 892 drivers/edac/pnd2_edac.c C(2), C(3), C(4), C(5), C(6), C(7), C(8), B(0), B(1), C 894 drivers/edac/pnd2_edac.c R(8), R(9), R(10), C(9), R(11), RS, C(11), R(12), R(13), C 958 drivers/edac/pnd2_edac.c case C(0): C 540 drivers/gpio/gpio-tegra186.c TEGRA186_MAIN_GPIO_PORT( C, 0x3200, 7, 3), C 605 drivers/gpio/gpio-tegra186.c TEGRA194_MAIN_GPIO_PORT( C, 0x4600, 8, 4), C 352 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c clk_src_regs(2, C), C 367 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c clk_src_regs(2, C), C 482 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c clk_src_regs(2, C), C 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c clk_src_regs(2, C), C 605 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c link_regs(2, C), C 336 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c clk_src_regs(2, C), C 402 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h fInt x_new, x_old, C, y; C 411 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h C = num; C 436 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h y = fSubtract(test, C); /*y = f(x) = x^2 - C; */ C 453 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h static void SolveQuadracticEqn(fInt A, fInt B, fInt C, fInt Roots[]) C 462 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h while(GreaterThan(A, f_CONSTANT100) || GreaterThan(B, f_CONSTANT100) || GreaterThan(C, f_CONSTANT100)) { C 465 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h C = fDivide(C, f_CONSTANT10); C 469 drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h temp = fMultiply(temp, C); /* root = 4*A*C */ C 5175 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) C 5176 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) C 5177 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) C 5178 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) C 5179 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) C 5180 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) C 5181 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) C 5182 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) C 5183 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) C 5184 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) C 5185 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) C 5186 drivers/gpu/drm/drm_edid.c #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) C 1151 drivers/gpu/drm/i915/display/intel_dp.c done = wait_event_timeout(i915->gmbus_wait_queue, C, C 5595 drivers/gpu/drm/i915/display/intel_dp.c ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, C 337 drivers/gpu/drm/i915/display/intel_opregion.c if (wait_for(C, dslp)) { C 98 drivers/gpu/drm/i915/selftests/i915_sw_fence.c struct i915_sw_fence *A, *B, *C; C 126 drivers/gpu/drm/i915/selftests/i915_sw_fence.c C = alloc_fence(); C 127 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (!C) { C 132 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (i915_sw_fence_await_sw_fence_gfp(B, C, GFP_KERNEL) == -EINVAL) { C 136 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (i915_sw_fence_await_sw_fence_gfp(C, B, GFP_KERNEL) != -EINVAL) { C 140 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (i915_sw_fence_await_sw_fence_gfp(C, A, GFP_KERNEL) != -EINVAL) { C 144 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (i915_sw_fence_await_sw_fence_gfp(A, C, GFP_KERNEL) == -EINVAL) { C 151 drivers/gpu/drm/i915/selftests/i915_sw_fence.c i915_sw_fence_commit(C); C 154 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (!i915_sw_fence_done(C)) { C 167 drivers/gpu/drm/i915/selftests/i915_sw_fence.c free_fence(C); C 225 drivers/gpu/drm/i915/selftests/i915_sw_fence.c struct i915_sw_fence *A, *B, *C; C 239 drivers/gpu/drm/i915/selftests/i915_sw_fence.c C = alloc_fence(); C 240 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (!C) { C 253 drivers/gpu/drm/i915/selftests/i915_sw_fence.c ret = i915_sw_fence_await_sw_fence_gfp(B, C, GFP_KERNEL); C 279 drivers/gpu/drm/i915/selftests/i915_sw_fence.c i915_sw_fence_commit(C); C 282 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (!i915_sw_fence_done(C)) { C 295 drivers/gpu/drm/i915/selftests/i915_sw_fence.c free_fence(C); C 305 drivers/gpu/drm/i915/selftests/i915_sw_fence.c struct i915_sw_fence *A, *B, *C; C 319 drivers/gpu/drm/i915/selftests/i915_sw_fence.c C = alloc_fence(); C 320 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (!C) { C 325 drivers/gpu/drm/i915/selftests/i915_sw_fence.c ret = i915_sw_fence_await_sw_fence_gfp(A, C, GFP_KERNEL); C 333 drivers/gpu/drm/i915/selftests/i915_sw_fence.c ret = i915_sw_fence_await_sw_fence_gfp(B, C, GFP_KERNEL); C 355 drivers/gpu/drm/i915/selftests/i915_sw_fence.c i915_sw_fence_commit(C); C 356 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (!i915_sw_fence_done(C)) { C 372 drivers/gpu/drm/i915/selftests/i915_sw_fence.c free_fence(C); C 382 drivers/gpu/drm/i915/selftests/i915_sw_fence.c struct i915_sw_fence *A, *B, *C; C 396 drivers/gpu/drm/i915/selftests/i915_sw_fence.c C = alloc_fence(); C 397 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (!C) { C 402 drivers/gpu/drm/i915/selftests/i915_sw_fence.c ret = i915_sw_fence_await_sw_fence_gfp(C, A, GFP_KERNEL); C 410 drivers/gpu/drm/i915/selftests/i915_sw_fence.c ret = i915_sw_fence_await_sw_fence_gfp(C, B, GFP_KERNEL); C 419 drivers/gpu/drm/i915/selftests/i915_sw_fence.c i915_sw_fence_commit(C); C 420 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (i915_sw_fence_done(C)) C 436 drivers/gpu/drm/i915/selftests/i915_sw_fence.c if (!i915_sw_fence_done(C)) { C 442 drivers/gpu/drm/i915/selftests/i915_sw_fence.c free_fence(C); C 71 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c #define ENGINE__(A,B,C) NV_DEVICE_INFO_ENGINE_##A: { int _i; \ C 72 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c for (_i = (B), args->data = 0ULL; _i <= (C); _i++) { \ C 456 drivers/media/dvb-frontends/mb86a16.c unsigned char C, F, B; C 462 drivers/media/dvb-frontends/mb86a16.c C = 1; C 464 drivers/media/dvb-frontends/mb86a16.c C = 2; C 466 drivers/media/dvb-frontends/mb86a16.c C = 3; C 468 drivers/media/dvb-frontends/mb86a16.c C = 4; C 502 drivers/media/dvb-frontends/mb86a16.c rf_val[0] = 0x01 | (C << 3) | (F << 1); C 634 drivers/media/pci/cx18/cx18-av-core.c ch[2] = C; C 638 drivers/media/pci/cx18/cx18-av-core.c ch[1] = C; C 713 drivers/media/pci/cx18/cx18-av-core.c case C: C 718 drivers/media/pci/cx18/cx18-av-core.c if (i == 0 && ch[i] == C) C 562 drivers/mfd/asic3.c asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff); C 840 drivers/mfd/asic3.c while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0) C 106 drivers/mfd/tps80031.c [TPS80031_INT_ID_WKUP] = TPS80031_IRQ(C, 0), C 107 drivers/mfd/tps80031.c [TPS80031_INT_VBUSS_WKUP] = TPS80031_IRQ(C, 1), C 108 drivers/mfd/tps80031.c [TPS80031_INT_ID] = TPS80031_IRQ(C, 2), C 109 drivers/mfd/tps80031.c [TPS80031_INT_VBUS] = TPS80031_IRQ(C, 3), C 110 drivers/mfd/tps80031.c [TPS80031_INT_CHRG_CTRL] = TPS80031_IRQ(C, 4), C 111 drivers/mfd/tps80031.c [TPS80031_INT_EXT_CHRG] = TPS80031_IRQ(C, 5), C 112 drivers/mfd/tps80031.c [TPS80031_INT_INT_CHRG] = TPS80031_IRQ(C, 6), C 113 drivers/mfd/tps80031.c [TPS80031_INT_RES2] = TPS80031_IRQ(C, 7), C 87 drivers/net/ethernet/aeroflex/greth.c #define SKIP_TX(N, C) (((N) + C) & GRETH_TXBD_NUM_MASK) C 7652 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h u8 C[8]; C 7664 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h C[i] = crc & 1; C 7669 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ C 7670 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h C[6] ^ C[7]; C 7673 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C 7674 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h C[6]; C 7677 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h C[0] ^ C[1] ^ C[4] ^ C[5]; C 7680 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h C[1] ^ C[2] ^ C[5] ^ C[6]; C 7683 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; C 7685 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ C 7686 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h C[3] ^ C[4] ^ C[7]; C 7688 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ C 7689 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h C[5]; C 7691 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ C 7692 drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h C[6]; C 190 drivers/net/ethernet/sfc/falcon/nic.c #define REGISTER_CZ(name) REGISTER(name, F, C, Z) C 325 drivers/net/ethernet/sfc/falcon/nic.c REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z, \ C 328 drivers/net/ethernet/sfc/falcon/nic.c #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z) C 191 drivers/net/ethernet/sfc/nic.c #define REGISTER_CZ(name) REGISTER(name, F, C, Z) C 330 drivers/net/ethernet/sfc/nic.c REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z, \ C 333 drivers/net/ethernet/sfc/nic.c #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z) C 494 drivers/net/wan/farsync.c #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E)) C 495 drivers/net/wan/farsync.c #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E)) C 496 drivers/net/wan/farsync.c #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E)) C 498 drivers/net/wan/farsync.c #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E)) C 499 drivers/net/wan/farsync.c #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E)) C 500 drivers/net/wan/farsync.c #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E)) C 474 drivers/nvdimm/security.c C( OP_FREEZE, "freeze", 1), \ C 475 drivers/nvdimm/security.c C( OP_DISABLE, "disable", 2), \ C 476 drivers/nvdimm/security.c C( OP_UPDATE, "update", 3), \ C 477 drivers/nvdimm/security.c C( OP_ERASE, "erase", 2), \ C 478 drivers/nvdimm/security.c C( OP_OVERWRITE, "overwrite", 2), \ C 479 drivers/nvdimm/security.c C( OP_MASTER_UPDATE, "master_update", 3), \ C 480 drivers/nvdimm/security.c C( OP_MASTER_ERASE, "master_erase", 2) C 1812 drivers/pinctrl/actions/pinctrl-s700.c OWL_GPIO_PORT(C, 0x0018, 32, 0x0, 0x4, 0x8, 0x204, 0x218, 0x21C, 0x240, 2), C 1715 drivers/pinctrl/actions/pinctrl-s900.c OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238, 0), C 371 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 376 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 381 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 386 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 390 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), C 394 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), C 400 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), C 405 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), C 410 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), C 415 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), C 420 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), C 425 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), C 430 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), C 436 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), C 442 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), C 448 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), C 454 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), C 458 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), C 462 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), C 466 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), C 471 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20), C 476 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21), C 481 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22), C 486 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23), C 490 drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24), C 91 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 96 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 102 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 107 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 112 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), C 116 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), C 121 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), C 126 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), C 130 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), C 135 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), C 140 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), C 145 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), C 150 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), C 155 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), C 160 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), C 165 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), C 170 drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), C 154 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 159 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 165 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 170 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 175 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), C 180 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), C 185 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), C 190 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), C 194 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), C 199 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), C 204 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), C 209 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), C 214 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), C 219 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), C 224 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), C 229 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), C 234 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), C 107 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 112 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 117 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 122 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 127 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), C 132 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), C 138 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), C 144 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), C 150 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), C 155 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), C 160 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), C 165 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), C 170 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), C 175 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), C 180 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), C 185 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), C 189 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), C 277 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 282 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 287 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 292 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 297 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), C 301 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), C 305 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), C 310 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), C 315 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), C 320 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), C 325 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), C 330 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), C 335 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), C 340 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), C 345 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), C 350 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), C 355 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 16), C 361 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 17), C 367 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 18), C 374 drivers/pinctrl/sunxi/pinctrl-sun5i.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), C 300 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 305 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 310 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 315 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 319 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), C 323 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), C 327 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), C 333 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), C 339 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), C 345 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), C 351 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), C 357 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), C 363 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), C 369 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), C 375 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), C 381 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), C 388 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 16), PINCTRL_SUN6I_A31, C 393 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 17), PINCTRL_SUN6I_A31, C 398 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 18), PINCTRL_SUN6I_A31, C 403 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 19), PINCTRL_SUN6I_A31, C 408 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 20), PINCTRL_SUN6I_A31, C 413 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 21), PINCTRL_SUN6I_A31, C 418 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 22), PINCTRL_SUN6I_A31, C 423 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 23), PINCTRL_SUN6I_A31, C 428 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24), C 434 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25), C 438 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26), C 442 drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27), C 112 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 117 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 122 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 127 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 132 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), C 136 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), C 141 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), C 146 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), C 150 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), C 155 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), C 160 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), C 165 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), C 170 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), C 175 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), C 180 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), C 185 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), C 190 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), C 195 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), C 199 drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), C 72 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 77 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 82 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 87 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 92 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), C 96 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), C 101 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), C 106 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), C 110 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), C 115 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), C 120 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), C 125 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), C 130 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), C 135 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), C 140 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), C 145 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), C 150 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), C 90 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 95 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 100 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 105 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 110 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), C 114 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), C 119 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), C 124 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), C 128 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), C 133 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), C 138 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), C 143 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), C 148 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), C 153 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), C 158 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), C 163 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), C 168 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), C 173 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), C 177 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), C 150 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 155 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 160 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 165 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 170 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), C 174 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), C 179 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), C 184 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), C 188 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), C 193 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), C 198 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), C 203 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), C 208 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), C 213 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), C 218 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), C 223 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), C 228 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), C 105 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 110 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 115 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 120 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 125 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 4), C 130 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 5), C 135 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 6), C 140 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 7), C 145 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 8), C 150 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 9), C 155 drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 10), C 163 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 168 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 173 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 178 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 182 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), C 186 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), C 190 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), C 195 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), C 200 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), C 205 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), C 210 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), C 215 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), C 220 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), C 225 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), C 230 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), C 235 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), C 240 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), C 245 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), C 250 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), C 255 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), C 97 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), C 101 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), C 106 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), C 111 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), C 210 drivers/scsi/aic94xx/aic94xx_dump.c asd_read_reg_byte(_ha, C##_n)) C 212 drivers/scsi/aic94xx/aic94xx_dump.c asd_read_reg_word(_ha, C##_n)) C 214 drivers/scsi/aic94xx/aic94xx_dump.c asd_read_reg_dword(_ha, C##_n)) C 377 drivers/scsi/isci/phy.h C(PHY_INITIAL),\ C 378 drivers/scsi/isci/phy.h C(PHY_STOPPED),\ C 379 drivers/scsi/isci/phy.h C(PHY_STARTING),\ C 380 drivers/scsi/isci/phy.h C(PHY_SUB_INITIAL),\ C 381 drivers/scsi/isci/phy.h C(PHY_SUB_AWAIT_OSSP_EN),\ C 382 drivers/scsi/isci/phy.h C(PHY_SUB_AWAIT_SAS_SPEED_EN),\ C 383 drivers/scsi/isci/phy.h C(PHY_SUB_AWAIT_IAF_UF),\ C 384 drivers/scsi/isci/phy.h C(PHY_SUB_AWAIT_SAS_POWER),\ C 385 drivers/scsi/isci/phy.h C(PHY_SUB_AWAIT_SATA_POWER),\ C 386 drivers/scsi/isci/phy.h C(PHY_SUB_AWAIT_SATA_PHY_EN),\ C 387 drivers/scsi/isci/phy.h C(PHY_SUB_AWAIT_SATA_SPEED_EN),\ C 388 drivers/scsi/isci/phy.h C(PHY_SUB_AWAIT_SIG_FIS_UF),\ C 389 drivers/scsi/isci/phy.h C(PHY_SUB_FINAL),\ C 390 drivers/scsi/isci/phy.h C(PHY_READY),\ C 391 drivers/scsi/isci/phy.h C(PHY_RESETTING),\ C 392 drivers/scsi/isci/phy.h C(PHY_FINAL),\ C 175 drivers/scsi/isci/port.h C(PORT_STOPPED),\ C 176 drivers/scsi/isci/port.h C(PORT_STOPPING),\ C 177 drivers/scsi/isci/port.h C(PORT_READY),\ C 178 drivers/scsi/isci/port.h C(PORT_SUB_WAITING),\ C 179 drivers/scsi/isci/port.h C(PORT_SUB_OPERATIONAL),\ C 180 drivers/scsi/isci/port.h C(PORT_SUB_CONFIGURING),\ C 181 drivers/scsi/isci/port.h C(PORT_RESETTING),\ C 182 drivers/scsi/isci/port.h C(PORT_FAILED),\ C 266 drivers/scsi/isci/remote_device.h C(DEV_INITIAL),\ C 267 drivers/scsi/isci/remote_device.h C(DEV_STOPPED),\ C 268 drivers/scsi/isci/remote_device.h C(DEV_STARTING),\ C 269 drivers/scsi/isci/remote_device.h C(DEV_READY),\ C 270 drivers/scsi/isci/remote_device.h C(STP_DEV_IDLE),\ C 271 drivers/scsi/isci/remote_device.h C(STP_DEV_CMD),\ C 272 drivers/scsi/isci/remote_device.h C(STP_DEV_NCQ),\ C 273 drivers/scsi/isci/remote_device.h C(STP_DEV_NCQ_ERROR),\ C 274 drivers/scsi/isci/remote_device.h C(STP_DEV_ATAPI_ERROR),\ C 275 drivers/scsi/isci/remote_device.h C(STP_DEV_AWAIT_RESET),\ C 276 drivers/scsi/isci/remote_device.h C(SMP_DEV_IDLE),\ C 277 drivers/scsi/isci/remote_device.h C(SMP_DEV_CMD),\ C 278 drivers/scsi/isci/remote_device.h C(DEV_STOPPING),\ C 279 drivers/scsi/isci/remote_device.h C(DEV_FAILED),\ C 280 drivers/scsi/isci/remote_device.h C(DEV_RESETTING),\ C 281 drivers/scsi/isci/remote_device.h C(DEV_FINAL),\ C 123 drivers/scsi/isci/remote_node_context.h C(RNC_INITIAL),\ C 124 drivers/scsi/isci/remote_node_context.h C(RNC_POSTING),\ C 125 drivers/scsi/isci/remote_node_context.h C(RNC_INVALIDATING),\ C 126 drivers/scsi/isci/remote_node_context.h C(RNC_RESUMING),\ C 127 drivers/scsi/isci/remote_node_context.h C(RNC_READY),\ C 128 drivers/scsi/isci/remote_node_context.h C(RNC_TX_SUSPENDED),\ C 129 drivers/scsi/isci/remote_node_context.h C(RNC_TX_RX_SUSPENDED),\ C 130 drivers/scsi/isci/remote_node_context.h C(RNC_AWAIT_SUSPENSION),\ C 228 drivers/scsi/isci/request.h C(REQ_INIT),\ C 229 drivers/scsi/isci/request.h C(REQ_CONSTRUCTED),\ C 230 drivers/scsi/isci/request.h C(REQ_STARTED),\ C 231 drivers/scsi/isci/request.h C(REQ_STP_UDMA_WAIT_TC_COMP),\ C 232 drivers/scsi/isci/request.h C(REQ_STP_UDMA_WAIT_D2H),\ C 233 drivers/scsi/isci/request.h C(REQ_STP_NON_DATA_WAIT_H2D),\ C 234 drivers/scsi/isci/request.h C(REQ_STP_NON_DATA_WAIT_D2H),\ C 235 drivers/scsi/isci/request.h C(REQ_STP_PIO_WAIT_H2D),\ C 236 drivers/scsi/isci/request.h C(REQ_STP_PIO_WAIT_FRAME),\ C 237 drivers/scsi/isci/request.h C(REQ_STP_PIO_DATA_IN),\ C 238 drivers/scsi/isci/request.h C(REQ_STP_PIO_DATA_OUT),\ C 239 drivers/scsi/isci/request.h C(REQ_ATAPI_WAIT_H2D),\ C 240 drivers/scsi/isci/request.h C(REQ_ATAPI_WAIT_PIO_SETUP),\ C 241 drivers/scsi/isci/request.h C(REQ_ATAPI_WAIT_D2H),\ C 242 drivers/scsi/isci/request.h C(REQ_ATAPI_WAIT_TC_COMP),\ C 243 drivers/scsi/isci/request.h C(REQ_TASK_WAIT_TC_COMP),\ C 244 drivers/scsi/isci/request.h C(REQ_TASK_WAIT_TC_RESP),\ C 245 drivers/scsi/isci/request.h C(REQ_SMP_WAIT_RESP),\ C 246 drivers/scsi/isci/request.h C(REQ_SMP_WAIT_TC_COMP),\ C 247 drivers/scsi/isci/request.h C(REQ_COMPLETED),\ C 248 drivers/scsi/isci/request.h C(REQ_ABORTING),\ C 249 drivers/scsi/isci/request.h C(REQ_FINAL),\ C 2695 drivers/scsi/lpfc/lpfc_init.c uint32_t A, B, C, D, E; C 2707 drivers/scsi/lpfc/lpfc_init.c C = HashResultPointer[2]; C 2713 drivers/scsi/lpfc/lpfc_init.c TEMP = ((B & C) | ((~B) & D)) + 0x5A827999; C 2715 drivers/scsi/lpfc/lpfc_init.c TEMP = (B ^ C ^ D) + 0x6ED9EBA1; C 2717 drivers/scsi/lpfc/lpfc_init.c TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC; C 2719 drivers/scsi/lpfc/lpfc_init.c TEMP = (B ^ C ^ D) + 0xCA62C1D6; C 2723 drivers/scsi/lpfc/lpfc_init.c D = C; C 2724 drivers/scsi/lpfc/lpfc_init.c C = S(30, B); C 2731 drivers/scsi/lpfc/lpfc_init.c HashResultPointer[2] += C; C 99 drivers/staging/comedi/drivers/s626.c #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4))) C 100 drivers/staging/comedi/drivers/s626.c #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10))) C 137 drivers/usb/renesas_usbhs/pipe.c CASE_PIPExTRN(C); C 173 drivers/usb/renesas_usbhs/pipe.c CASE_PIPExTRE(C); C 3545 drivers/video/fbdev/sis/init.c int A, B, C, D, E, F, temp; C 3579 drivers/video/fbdev/sis/init.c C = (temp > 0) ? temp : (temp + 64); C 3581 drivers/video/fbdev/sis/init.c D = B - F - C; C 3586 drivers/video/fbdev/sis/init.c var->hsync_len = C * 8; C 3629 drivers/video/fbdev/sis/init.c C = (temp > 0) ? temp : (temp + 32); C 3631 drivers/video/fbdev/sis/init.c D = B - F - C; C 3636 drivers/video/fbdev/sis/init.c var->vsync_len = C; C 385 drivers/video/fbdev/stifb.c #define BA(F,C,S,A,J,B,I) \ C 386 drivers/video/fbdev/stifb.c (((F)<<31)|((C)<<27)|((S)<<24)|((A)<<21)|((J)<<16)|((B)<<12)|(I)) C 1532 fs/afs/internal.h #define ASSERTIF(C, X) \ C 1534 fs/afs/internal.h if (unlikely((C) && !(X))) { \ C 1541 fs/afs/internal.h #define ASSERTIFCMP(C, X, OP, Y) \ C 1543 fs/afs/internal.h if (unlikely((C) && !((X) OP (Y)))) { \ C 1568 fs/afs/internal.h #define ASSERTIF(C, X) \ C 1572 fs/afs/internal.h #define ASSERTIFCMP(C, X, OP, Y) \ C 339 fs/cachefiles/internal.h #define ASSERTIF(C, X) \ C 341 fs/cachefiles/internal.h if (unlikely((C) && !(X))) { \ C 348 fs/cachefiles/internal.h #define ASSERTIFCMP(C, X, OP, Y) \ C 350 fs/cachefiles/internal.h if (unlikely((C) && !((X) OP (Y)))) { \ C 363 fs/cachefiles/internal.h #define ASSERTIF(C, X) do {} while (0) C 364 fs/cachefiles/internal.h #define ASSERTIFCMP(C, X, OP, Y) do {} while (0) C 463 fs/fscache/internal.h #define ASSERTIF(C, X) \ C 465 fs/fscache/internal.h if (unlikely((C) && !(X))) { \ C 472 fs/fscache/internal.h #define ASSERTIFCMP(C, X, OP, Y) \ C 474 fs/fscache/internal.h if (unlikely((C) && !((X) OP (Y)))) { \ C 487 fs/fscache/internal.h #define ASSERTIF(C, X) do {} while (0) C 488 fs/fscache/internal.h #define ASSERTIFCMP(C, X, OP, Y) do {} while (0) C 113 include/crypto/drbg.h unsigned char *C; C 38 include/linux/perf/arm_pmu.h [0 ... C(MAX) - 1] = { \ C 39 include/linux/perf/arm_pmu.h [0 ... C(OP_MAX) - 1] = { \ C 40 include/linux/perf/arm_pmu.h [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \ C 1214 kernel/trace/trace.h C(DISPLAY_GRAPH, "display-graph"), C 1221 kernel/trace/trace.h C(BRANCH, "branch"), C 1228 kernel/trace/trace.h C(FUNCTION, "function-trace"), \ C 1229 kernel/trace/trace.h C(FUNC_FORK, "function-fork"), C 1239 kernel/trace/trace.h C(STACKTRACE, "stacktrace"), C 1252 kernel/trace/trace.h C(PRINT_PARENT, "print-parent"), \ C 1253 kernel/trace/trace.h C(SYM_OFFSET, "sym-offset"), \ C 1254 kernel/trace/trace.h C(SYM_ADDR, "sym-addr"), \ C 1255 kernel/trace/trace.h C(VERBOSE, "verbose"), \ C 1256 kernel/trace/trace.h C(RAW, "raw"), \ C 1257 kernel/trace/trace.h C(HEX, "hex"), \ C 1258 kernel/trace/trace.h C(BIN, "bin"), \ C 1259 kernel/trace/trace.h C(BLOCK, "block"), \ C 1260 kernel/trace/trace.h C(PRINTK, "trace_printk"), \ C 1261 kernel/trace/trace.h C(ANNOTATE, "annotate"), \ C 1262 kernel/trace/trace.h C(USERSTACKTRACE, "userstacktrace"), \ C 1263 kernel/trace/trace.h C(SYM_USEROBJ, "sym-userobj"), \ C 1264 kernel/trace/trace.h C(PRINTK_MSGONLY, "printk-msg-only"), \ C 1265 kernel/trace/trace.h C(CONTEXT_INFO, "context-info"), /* Print pid/cpu/time */ \ C 1266 kernel/trace/trace.h C(LATENCY_FMT, "latency-format"), \ C 1267 kernel/trace/trace.h C(RECORD_CMD, "record-cmd"), \ C 1268 kernel/trace/trace.h C(RECORD_TGID, "record-tgid"), \ C 1269 kernel/trace/trace.h C(OVERWRITE, "overwrite"), \ C 1270 kernel/trace/trace.h C(STOP_ON_FREE, "disable_on_free"), \ C 1271 kernel/trace/trace.h C(IRQ_INFO, "irq-info"), \ C 1272 kernel/trace/trace.h C(MARKERS, "markers"), \ C 1273 kernel/trace/trace.h C(EVENT_FORK, "event-fork"), \ C 25 kernel/trace/trace_events_filter.c C( OP_GLOB, "~" ), \ C 26 kernel/trace/trace_events_filter.c C( OP_NE, "!=" ), \ C 27 kernel/trace/trace_events_filter.c C( OP_EQ, "==" ), \ C 28 kernel/trace/trace_events_filter.c C( OP_LE, "<=" ), \ C 29 kernel/trace/trace_events_filter.c C( OP_LT, "<" ), \ C 30 kernel/trace/trace_events_filter.c C( OP_GE, ">=" ), \ C 31 kernel/trace/trace_events_filter.c C( OP_GT, ">" ), \ C 32 kernel/trace/trace_events_filter.c C( OP_BAND, "&" ), \ C 33 kernel/trace/trace_events_filter.c C( OP_MAX, NULL ) C 53 kernel/trace/trace_events_filter.c C(NONE, "No error"), \ C 54 kernel/trace/trace_events_filter.c C(INVALID_OP, "Invalid operator"), \ C 55 kernel/trace/trace_events_filter.c C(TOO_MANY_OPEN, "Too many '('"), \ C 56 kernel/trace/trace_events_filter.c C(TOO_MANY_CLOSE, "Too few '('"), \ C 57 kernel/trace/trace_events_filter.c C(MISSING_QUOTE, "Missing matching quote"), \ C 58 kernel/trace/trace_events_filter.c C(OPERAND_TOO_LONG, "Operand too long"), \ C 59 kernel/trace/trace_events_filter.c C(EXPECT_STRING, "Expecting string field"), \ C 60 kernel/trace/trace_events_filter.c C(EXPECT_DIGIT, "Expecting numeric field"), \ C 61 kernel/trace/trace_events_filter.c C(ILLEGAL_FIELD_OP, "Illegal operation for field type"), \ C 62 kernel/trace/trace_events_filter.c C(FIELD_NOT_FOUND, "Field not found"), \ C 63 kernel/trace/trace_events_filter.c C(ILLEGAL_INTVAL, "Illegal integer value"), \ C 64 kernel/trace/trace_events_filter.c C(BAD_SUBSYS_FILTER, "Couldn't find or set field in one of a subsystem's events"), \ C 65 kernel/trace/trace_events_filter.c C(TOO_MANY_PREDS, "Too many terms in predicate expression"), \ C 66 kernel/trace/trace_events_filter.c C(INVALID_FILTER, "Meaningless filter expression"), \ C 67 kernel/trace/trace_events_filter.c C(IP_FIELD_ONLY, "Only 'ip' field is supported for function trace"), \ C 68 kernel/trace/trace_events_filter.c C(INVALID_VALUE, "Invalid value (did you forget quotes)?"), \ C 69 kernel/trace/trace_events_filter.c C(ERRNO, "Error"), \ C 70 kernel/trace/trace_events_filter.c C(NO_FILTER, "No filter found") C 31 kernel/trace/trace_events_hist.c C(NONE, "No error"), \ C 32 kernel/trace/trace_events_hist.c C(DUPLICATE_VAR, "Variable already defined"), \ C 33 kernel/trace/trace_events_hist.c C(VAR_NOT_UNIQUE, "Variable name not unique, need to use fully qualified name (subsys.event.var) for variable"), \ C 34 kernel/trace/trace_events_hist.c C(TOO_MANY_VARS, "Too many variables defined"), \ C 35 kernel/trace/trace_events_hist.c C(MALFORMED_ASSIGNMENT, "Malformed assignment"), \ C 36 kernel/trace/trace_events_hist.c C(NAMED_MISMATCH, "Named hist trigger doesn't match existing named trigger (includes variables)"), \ C 37 kernel/trace/trace_events_hist.c C(TRIGGER_EEXIST, "Hist trigger already exists"), \ C 38 kernel/trace/trace_events_hist.c C(TRIGGER_ENOENT_CLEAR, "Can't clear or continue a nonexistent hist trigger"), \ C 39 kernel/trace/trace_events_hist.c C(SET_CLOCK_FAIL, "Couldn't set trace_clock"), \ C 40 kernel/trace/trace_events_hist.c C(BAD_FIELD_MODIFIER, "Invalid field modifier"), \ C 41 kernel/trace/trace_events_hist.c C(TOO_MANY_SUBEXPR, "Too many subexpressions (3 max)"), \ C 42 kernel/trace/trace_events_hist.c C(TIMESTAMP_MISMATCH, "Timestamp units in expression don't match"), \ C 43 kernel/trace/trace_events_hist.c C(TOO_MANY_FIELD_VARS, "Too many field variables defined"), \ C 44 kernel/trace/trace_events_hist.c C(EVENT_FILE_NOT_FOUND, "Event file not found"), \ C 45 kernel/trace/trace_events_hist.c C(HIST_NOT_FOUND, "Matching event histogram not found"), \ C 46 kernel/trace/trace_events_hist.c C(HIST_CREATE_FAIL, "Couldn't create histogram for field"), \ C 47 kernel/trace/trace_events_hist.c C(SYNTH_VAR_NOT_FOUND, "Couldn't find synthetic variable"), \ C 48 kernel/trace/trace_events_hist.c C(SYNTH_EVENT_NOT_FOUND,"Couldn't find synthetic event"), \ C 49 kernel/trace/trace_events_hist.c C(SYNTH_TYPE_MISMATCH, "Param type doesn't match synthetic event field type"), \ C 50 kernel/trace/trace_events_hist.c C(SYNTH_COUNT_MISMATCH, "Param count doesn't match synthetic event field count"), \ C 51 kernel/trace/trace_events_hist.c C(FIELD_VAR_PARSE_FAIL, "Couldn't parse field variable"), \ C 52 kernel/trace/trace_events_hist.c C(VAR_CREATE_FIND_FAIL, "Couldn't create or find variable"), \ C 53 kernel/trace/trace_events_hist.c C(ONX_NOT_VAR, "For onmax(x) or onchange(x), x must be a variable"), \ C 54 kernel/trace/trace_events_hist.c C(ONX_VAR_NOT_FOUND, "Couldn't find onmax or onchange variable"), \ C 55 kernel/trace/trace_events_hist.c C(ONX_VAR_CREATE_FAIL, "Couldn't create onmax or onchange variable"), \ C 56 kernel/trace/trace_events_hist.c C(FIELD_VAR_CREATE_FAIL,"Couldn't create field variable"), \ C 57 kernel/trace/trace_events_hist.c C(TOO_MANY_PARAMS, "Too many action params"), \ C 58 kernel/trace/trace_events_hist.c C(PARAM_NOT_FOUND, "Couldn't find param"), \ C 59 kernel/trace/trace_events_hist.c C(INVALID_PARAM, "Invalid action param"), \ C 60 kernel/trace/trace_events_hist.c C(ACTION_NOT_FOUND, "No action found"), \ C 61 kernel/trace/trace_events_hist.c C(NO_SAVE_PARAMS, "No params found for save()"), \ C 62 kernel/trace/trace_events_hist.c C(TOO_MANY_SAVE_ACTIONS,"Can't have more than one save() action per hist"), \ C 63 kernel/trace/trace_events_hist.c C(ACTION_MISMATCH, "Handler doesn't support action"), \ C 64 kernel/trace/trace_events_hist.c C(NO_CLOSING_PAREN, "No closing paren found"), \ C 65 kernel/trace/trace_events_hist.c C(SUBSYS_NOT_FOUND, "Missing subsystem"), \ C 66 kernel/trace/trace_events_hist.c C(INVALID_SUBSYS_EVENT, "Invalid subsystem or event name"), \ C 67 kernel/trace/trace_events_hist.c C(INVALID_REF_KEY, "Using variable references in keys not supported"), \ C 68 kernel/trace/trace_events_hist.c C(VAR_NOT_FOUND, "Couldn't find variable"), \ C 69 kernel/trace/trace_events_hist.c C(FIELD_NOT_FOUND, "Couldn't find field"), C 396 kernel/trace/trace_probe.h C(FILE_NOT_FOUND, "Failed to find the given file"), \ C 397 kernel/trace/trace_probe.h C(NO_REGULAR_FILE, "Not a regular file"), \ C 398 kernel/trace/trace_probe.h C(BAD_REFCNT, "Invalid reference counter offset"), \ C 399 kernel/trace/trace_probe.h C(REFCNT_OPEN_BRACE, "Reference counter brace is not closed"), \ C 400 kernel/trace/trace_probe.h C(BAD_REFCNT_SUFFIX, "Reference counter has wrong suffix"), \ C 401 kernel/trace/trace_probe.h C(BAD_UPROBE_OFFS, "Invalid uprobe offset"), \ C 402 kernel/trace/trace_probe.h C(MAXACT_NO_KPROBE, "Maxactive is not for kprobe"), \ C 403 kernel/trace/trace_probe.h C(BAD_MAXACT, "Invalid maxactive number"), \ C 404 kernel/trace/trace_probe.h C(MAXACT_TOO_BIG, "Maxactive is too big"), \ C 405 kernel/trace/trace_probe.h C(BAD_PROBE_ADDR, "Invalid probed address or symbol"), \ C 406 kernel/trace/trace_probe.h C(BAD_RETPROBE, "Retprobe address must be an function entry"), \ C 407 kernel/trace/trace_probe.h C(NO_GROUP_NAME, "Group name is not specified"), \ C 408 kernel/trace/trace_probe.h C(GROUP_TOO_LONG, "Group name is too long"), \ C 409 kernel/trace/trace_probe.h C(BAD_GROUP_NAME, "Group name must follow the same rules as C identifiers"), \ C 410 kernel/trace/trace_probe.h C(NO_EVENT_NAME, "Event name is not specified"), \ C 411 kernel/trace/trace_probe.h C(EVENT_TOO_LONG, "Event name is too long"), \ C 412 kernel/trace/trace_probe.h C(BAD_EVENT_NAME, "Event name must follow the same rules as C identifiers"), \ C 413 kernel/trace/trace_probe.h C(RETVAL_ON_PROBE, "$retval is not available on probe"), \ C 414 kernel/trace/trace_probe.h C(BAD_STACK_NUM, "Invalid stack number"), \ C 415 kernel/trace/trace_probe.h C(BAD_ARG_NUM, "Invalid argument number"), \ C 416 kernel/trace/trace_probe.h C(BAD_VAR, "Invalid $-valiable specified"), \ C 417 kernel/trace/trace_probe.h C(BAD_REG_NAME, "Invalid register name"), \ C 418 kernel/trace/trace_probe.h C(BAD_MEM_ADDR, "Invalid memory address"), \ C 419 kernel/trace/trace_probe.h C(BAD_IMM, "Invalid immediate value"), \ C 420 kernel/trace/trace_probe.h C(IMMSTR_NO_CLOSE, "String is not closed with '\"'"), \ C 421 kernel/trace/trace_probe.h C(FILE_ON_KPROBE, "File offset is not available with kprobe"), \ C 422 kernel/trace/trace_probe.h C(BAD_FILE_OFFS, "Invalid file offset value"), \ C 423 kernel/trace/trace_probe.h C(SYM_ON_UPROBE, "Symbol is not available with uprobe"), \ C 424 kernel/trace/trace_probe.h C(TOO_MANY_OPS, "Dereference is too much nested"), \ C 425 kernel/trace/trace_probe.h C(DEREF_NEED_BRACE, "Dereference needs a brace"), \ C 426 kernel/trace/trace_probe.h C(BAD_DEREF_OFFS, "Invalid dereference offset"), \ C 427 kernel/trace/trace_probe.h C(DEREF_OPEN_BRACE, "Dereference brace is not closed"), \ C 428 kernel/trace/trace_probe.h C(COMM_CANT_DEREF, "$comm can not be dereferenced"), \ C 429 kernel/trace/trace_probe.h C(BAD_FETCH_ARG, "Invalid fetch argument"), \ C 430 kernel/trace/trace_probe.h C(ARRAY_NO_CLOSE, "Array is not closed"), \ C 431 kernel/trace/trace_probe.h C(BAD_ARRAY_SUFFIX, "Array has wrong suffix"), \ C 432 kernel/trace/trace_probe.h C(BAD_ARRAY_NUM, "Invalid array size"), \ C 433 kernel/trace/trace_probe.h C(ARRAY_TOO_BIG, "Array number is too big"), \ C 434 kernel/trace/trace_probe.h C(BAD_TYPE, "Unknown type is specified"), \ C 435 kernel/trace/trace_probe.h C(BAD_STRING, "String accepts only memory argument"), \ C 436 kernel/trace/trace_probe.h C(BAD_BITFIELD, "Invalid bitfield"), \ C 437 kernel/trace/trace_probe.h C(ARG_NAME_TOO_LONG, "Argument name is too long"), \ C 438 kernel/trace/trace_probe.h C(NO_ARG_NAME, "Argument name is not specified"), \ C 439 kernel/trace/trace_probe.h C(BAD_ARG_NAME, "Argument name must follow the same rules as C identifiers"), \ C 440 kernel/trace/trace_probe.h C(USED_ARG_NAME, "This argument name is already used"), \ C 441 kernel/trace/trace_probe.h C(ARG_TOO_LONG, "Argument expression is too long"), \ C 442 kernel/trace/trace_probe.h C(NO_ARG_BODY, "No argument expression"), \ C 443 kernel/trace/trace_probe.h C(BAD_INSN_BNDRY, "Probe point is not an instruction boundary"),\ C 444 kernel/trace/trace_probe.h C(FAIL_REG_PROBE, "Failed to register probe event"),\ C 445 kernel/trace/trace_probe.h C(DIFF_PROBE_TYPE, "Probe type is different from existing probe"),\ C 446 kernel/trace/trace_probe.h C(DIFF_ARG_TYPE, "Argument type or name is different from existing probe"),\ C 447 kernel/trace/trace_probe.h C(SAME_PROBE, "There is already the exact same probe event"), C 502 lib/locking-selftest.c LOCK_UNLOCK_2(B, C); \ C 503 lib/locking-selftest.c LOCK_UNLOCK_2(C, A); /* fail */ C 535 lib/locking-selftest.c LOCK_UNLOCK_2(C, A); \ C 536 lib/locking-selftest.c LOCK_UNLOCK_2(B, C); /* fail */ C 568 lib/locking-selftest.c LOCK_UNLOCK_2(B, C); \ C 569 lib/locking-selftest.c LOCK_UNLOCK_2(C, D); \ C 601 lib/locking-selftest.c LOCK_UNLOCK_2(C, D); \ C 634 lib/locking-selftest.c LOCK_UNLOCK_2(C, D); \ C 635 lib/locking-selftest.c LOCK_UNLOCK_2(B, C); \ C 1116 lib/locking-selftest.c I1(A); I1(B); I1(C); I1(D); C 1120 lib/locking-selftest.c I2(A); I2(B); I2(C); I2(D); C 55 lib/sha1.c #define SHA_ROUND(t, input, fn, constant, A, B, C, D, E) do { \ C 60 lib/sha1.c #define T_0_15(t, A, B, C, D, E) SHA_ROUND(t, SHA_SRC, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) C 61 lib/sha1.c #define T_16_19(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) C 62 lib/sha1.c #define T_20_39(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0x6ed9eba1, A, B, C, D, E ) C 63 lib/sha1.c #define T_40_59(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, ((B&C)+(D&(B^C))) , 0x8f1bbcdc, A, B, C, D, E ) C 64 lib/sha1.c #define T_60_79(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0xca62c1d6, A, B, C, D, E ) C 84 lib/sha1.c __u32 A, B, C, D, E; C 88 lib/sha1.c C = digest[2]; C 93 lib/sha1.c T_0_15( 0, A, B, C, D, E); C 94 lib/sha1.c T_0_15( 1, E, A, B, C, D); C 95 lib/sha1.c T_0_15( 2, D, E, A, B, C); C 96 lib/sha1.c T_0_15( 3, C, D, E, A, B); C 97 lib/sha1.c T_0_15( 4, B, C, D, E, A); C 98 lib/sha1.c T_0_15( 5, A, B, C, D, E); C 99 lib/sha1.c T_0_15( 6, E, A, B, C, D); C 100 lib/sha1.c T_0_15( 7, D, E, A, B, C); C 101 lib/sha1.c T_0_15( 8, C, D, E, A, B); C 102 lib/sha1.c T_0_15( 9, B, C, D, E, A); C 103 lib/sha1.c T_0_15(10, A, B, C, D, E); C 104 lib/sha1.c T_0_15(11, E, A, B, C, D); C 105 lib/sha1.c T_0_15(12, D, E, A, B, C); C 106 lib/sha1.c T_0_15(13, C, D, E, A, B); C 107 lib/sha1.c T_0_15(14, B, C, D, E, A); C 108 lib/sha1.c T_0_15(15, A, B, C, D, E); C 111 lib/sha1.c T_16_19(16, E, A, B, C, D); C 112 lib/sha1.c T_16_19(17, D, E, A, B, C); C 113 lib/sha1.c T_16_19(18, C, D, E, A, B); C 114 lib/sha1.c T_16_19(19, B, C, D, E, A); C 117 lib/sha1.c T_20_39(20, A, B, C, D, E); C 118 lib/sha1.c T_20_39(21, E, A, B, C, D); C 119 lib/sha1.c T_20_39(22, D, E, A, B, C); C 120 lib/sha1.c T_20_39(23, C, D, E, A, B); C 121 lib/sha1.c T_20_39(24, B, C, D, E, A); C 122 lib/sha1.c T_20_39(25, A, B, C, D, E); C 123 lib/sha1.c T_20_39(26, E, A, B, C, D); C 124 lib/sha1.c T_20_39(27, D, E, A, B, C); C 125 lib/sha1.c T_20_39(28, C, D, E, A, B); C 126 lib/sha1.c T_20_39(29, B, C, D, E, A); C 127 lib/sha1.c T_20_39(30, A, B, C, D, E); C 128 lib/sha1.c T_20_39(31, E, A, B, C, D); C 129 lib/sha1.c T_20_39(32, D, E, A, B, C); C 130 lib/sha1.c T_20_39(33, C, D, E, A, B); C 131 lib/sha1.c T_20_39(34, B, C, D, E, A); C 132 lib/sha1.c T_20_39(35, A, B, C, D, E); C 133 lib/sha1.c T_20_39(36, E, A, B, C, D); C 134 lib/sha1.c T_20_39(37, D, E, A, B, C); C 135 lib/sha1.c T_20_39(38, C, D, E, A, B); C 136 lib/sha1.c T_20_39(39, B, C, D, E, A); C 139 lib/sha1.c T_40_59(40, A, B, C, D, E); C 140 lib/sha1.c T_40_59(41, E, A, B, C, D); C 141 lib/sha1.c T_40_59(42, D, E, A, B, C); C 142 lib/sha1.c T_40_59(43, C, D, E, A, B); C 143 lib/sha1.c T_40_59(44, B, C, D, E, A); C 144 lib/sha1.c T_40_59(45, A, B, C, D, E); C 145 lib/sha1.c T_40_59(46, E, A, B, C, D); C 146 lib/sha1.c T_40_59(47, D, E, A, B, C); C 147 lib/sha1.c T_40_59(48, C, D, E, A, B); C 148 lib/sha1.c T_40_59(49, B, C, D, E, A); C 149 lib/sha1.c T_40_59(50, A, B, C, D, E); C 150 lib/sha1.c T_40_59(51, E, A, B, C, D); C 151 lib/sha1.c T_40_59(52, D, E, A, B, C); C 152 lib/sha1.c T_40_59(53, C, D, E, A, B); C 153 lib/sha1.c T_40_59(54, B, C, D, E, A); C 154 lib/sha1.c T_40_59(55, A, B, C, D, E); C 155 lib/sha1.c T_40_59(56, E, A, B, C, D); C 156 lib/sha1.c T_40_59(57, D, E, A, B, C); C 157 lib/sha1.c T_40_59(58, C, D, E, A, B); C 158 lib/sha1.c T_40_59(59, B, C, D, E, A); C 161 lib/sha1.c T_60_79(60, A, B, C, D, E); C 162 lib/sha1.c T_60_79(61, E, A, B, C, D); C 163 lib/sha1.c T_60_79(62, D, E, A, B, C); C 164 lib/sha1.c T_60_79(63, C, D, E, A, B); C 165 lib/sha1.c T_60_79(64, B, C, D, E, A); C 166 lib/sha1.c T_60_79(65, A, B, C, D, E); C 167 lib/sha1.c T_60_79(66, E, A, B, C, D); C 168 lib/sha1.c T_60_79(67, D, E, A, B, C); C 169 lib/sha1.c T_60_79(68, C, D, E, A, B); C 170 lib/sha1.c T_60_79(69, B, C, D, E, A); C 171 lib/sha1.c T_60_79(70, A, B, C, D, E); C 172 lib/sha1.c T_60_79(71, E, A, B, C, D); C 173 lib/sha1.c T_60_79(72, D, E, A, B, C); C 174 lib/sha1.c T_60_79(73, C, D, E, A, B); C 175 lib/sha1.c T_60_79(74, B, C, D, E, A); C 176 lib/sha1.c T_60_79(75, A, B, C, D, E); C 177 lib/sha1.c T_60_79(76, E, A, B, C, D); C 178 lib/sha1.c T_60_79(77, D, E, A, B, C); C 179 lib/sha1.c T_60_79(78, C, D, E, A, B); C 180 lib/sha1.c T_60_79(79, B, C, D, E, A); C 184 lib/sha1.c digest[2] += C; C 989 net/core/skbuff.c C(len); C 990 net/core/skbuff.c C(data_len); C 991 net/core/skbuff.c C(mac_len); C 996 net/core/skbuff.c C(pfmemalloc); C 998 net/core/skbuff.c C(tail); C 999 net/core/skbuff.c C(end); C 1000 net/core/skbuff.c C(head); C 1001 net/core/skbuff.c C(head_frag); C 1002 net/core/skbuff.c C(data); C 1003 net/core/skbuff.c C(truesize); C 62 net/netfilter/ipvs/ip_vs_nfct.c #define ARG_CONN(C) IP_VS_DBG_ADDR((C)->af, &((C)->caddr)), \ C 63 net/netfilter/ipvs/ip_vs_nfct.c ntohs((C)->cport), \ C 64 net/netfilter/ipvs/ip_vs_nfct.c IP_VS_DBG_ADDR((C)->af, &((C)->vaddr)), \ C 65 net/netfilter/ipvs/ip_vs_nfct.c ntohs((C)->vport), \ C 66 net/netfilter/ipvs/ip_vs_nfct.c IP_VS_DBG_ADDR((C)->daf, &((C)->daddr)), \ C 67 net/netfilter/ipvs/ip_vs_nfct.c ntohs((C)->dport), \ C 68 net/netfilter/ipvs/ip_vs_nfct.c (C)->protocol, (C)->state C 1273 net/rxrpc/ar-internal.h #define ASSERTIF(C, X) \ C 1275 net/rxrpc/ar-internal.h if (unlikely((C) && !(X))) { \ C 1281 net/rxrpc/ar-internal.h #define ASSERTIFCMP(C, X, OP, Y) \ C 1285 net/rxrpc/ar-internal.h if (unlikely((C) && !(_x OP _y))) { \ C 1303 net/rxrpc/ar-internal.h #define ASSERTIF(C, X) \ C 1307 net/rxrpc/ar-internal.h #define ASSERTIFCMP(C, X, OP, Y) \ C 259 security/apparmor/include/label.h #define LABEL_MEDIATES(L, C) \ C 265 security/apparmor/include/label.h if (PROFILE_MEDIATES(profile, (C))) { \ C 56 security/apparmor/include/path.h #define __get_buffer(C, N) ({ \ C 58 security/apparmor/include/path.h (C)->buf[(N)]; }) C 60 security/apparmor/include/path.h #define __get_buffers(C, X...) EVAL(__get_buffer, C, X) C 370 security/apparmor/match.c #define match_char(state, def, base, next, check, C) \ C 373 security/apparmor/match.c unsigned int pos = base_idx(b) + (C); \ C 92 sound/soc/sh/rcar/mix.c u32 volC = rsnd_mix_get_vol(mix, C); C 514 tools/perf/util/evsel.c #define CACHE_READ (1 << C(OP_READ)) C 515 tools/perf/util/evsel.c #define CACHE_WRITE (1 << C(OP_WRITE)) C 516 tools/perf/util/evsel.c #define CACHE_PREFETCH (1 << C(OP_PREFETCH)) C 524 tools/perf/util/evsel.c static unsigned long perf_evsel__hw_cache_stat[C(MAX)] = { C 525 tools/perf/util/evsel.c [C(L1D)] = (CACHE_READ | CACHE_WRITE | CACHE_PREFETCH), C 526 tools/perf/util/evsel.c [C(L1I)] = (CACHE_READ | CACHE_PREFETCH), C 527 tools/perf/util/evsel.c [C(LL)] = (CACHE_READ | CACHE_WRITE | CACHE_PREFETCH), C 528 tools/perf/util/evsel.c [C(DTLB)] = (CACHE_READ | CACHE_WRITE | CACHE_PREFETCH), C 529 tools/perf/util/evsel.c [C(ITLB)] = (CACHE_READ), C 530 tools/perf/util/evsel.c [C(BPU)] = (CACHE_READ), C 531 tools/perf/util/evsel.c [C(NODE)] = (CACHE_READ | CACHE_WRITE | CACHE_PREFETCH), C 63 tools/testing/selftests/bpf/progs/btf_dump_test_case_namespacing.c enum C c; C 26 tools/testing/selftests/bpf/progs/test_verif_scale1.c #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; C 26 tools/testing/selftests/bpf/progs/test_verif_scale2.c #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; C 26 tools/testing/selftests/bpf/progs/test_verif_scale3.c #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; C 18 tools/testing/selftests/powerpc/benchmarks/futex_bench.c #define futex(A, B, C, D, E, F) syscall(__NR_futex, A, B, C, D, E, F) C 1 tools/virtio/linux/thread_info.h #define check_copy_size(A, B, C) (1) C 21 virt/kvm/async_pf.h #define kvm_async_pf_vcpu_init(C) do {} while (0)