armada_reg_queue_set  353 drivers/gpu/drm/armada/armada_crtc.c 	armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
armada_reg_queue_set  378 drivers/gpu/drm/armada/armada_crtc.c 	armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
armada_reg_queue_set  379 drivers/gpu/drm/armada/armada_crtc.c 	armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
armada_reg_queue_set  380 drivers/gpu/drm/armada/armada_crtc.c 	armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
armada_reg_queue_set  381 drivers/gpu/drm/armada/armada_crtc.c 	armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
armada_reg_queue_set   98 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);
armada_reg_queue_set  101 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);
armada_reg_queue_set  104 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);
armada_reg_queue_set  113 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0),
armada_reg_queue_set  115 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, armada_addr(state, 0, 1),
armada_reg_queue_set  117 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, armada_addr(state, 0, 2),
armada_reg_queue_set  119 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0),
armada_reg_queue_set  121 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, armada_addr(state, 1, 1),
armada_reg_queue_set  123 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, armada_addr(state, 1, 2),
armada_reg_queue_set  127 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);
armada_reg_queue_set  129 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);
armada_reg_queue_set  174 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST);
armada_reg_queue_set  178 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION);
armada_reg_queue_set  180 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE);
armada_reg_queue_set  189 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y);
armada_reg_queue_set  193 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U);
armada_reg_queue_set  197 drivers/gpu/drm/armada/armada_overlay.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V);
armada_reg_queue_set  190 drivers/gpu/drm/armada/armada_plane.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);
armada_reg_queue_set  193 drivers/gpu/drm/armada/armada_plane.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);
armada_reg_queue_set  196 drivers/gpu/drm/armada/armada_plane.c 		armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);
armada_reg_queue_set  201 drivers/gpu/drm/armada/armada_plane.c 		armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0),
armada_reg_queue_set  203 drivers/gpu/drm/armada/armada_plane.c 		armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0),