armada_reg_queue_mod 385 drivers/gpu/drm/armada/armada_crtc.c armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, armada_reg_queue_mod 390 drivers/gpu/drm/armada/armada_crtc.c armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1); armada_reg_queue_mod 407 drivers/gpu/drm/armada/armada_crtc.c armada_reg_queue_mod(regs, i, val, CFG_INV_CSYNC | CFG_INV_HSYNC | armada_reg_queue_mod 28 drivers/gpu/drm/armada/armada_crtc.h armada_reg_queue_mod(_r, _i, _v, ~0, _o) armada_reg_queue_mod 31 drivers/gpu/drm/armada/armada_crtc.h armada_reg_queue_mod(_r, _i, 0, 0, ~0) armada_reg_queue_mod 93 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_mod(regs, idx, armada_reg_queue_mod 168 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_mod(regs, idx, cfg, cfg_mask, armada_reg_queue_mod 184 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK, armada_reg_queue_mod 201 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK | armada_reg_queue_mod 208 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY | armada_reg_queue_mod 235 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0); armada_reg_queue_mod 236 drivers/gpu/drm/armada/armada_overlay.c armada_reg_queue_mod(regs, idx, CFG_PDWN16x66 | CFG_PDWN32x66, 0, armada_reg_queue_mod 186 drivers/gpu/drm/armada/armada_plane.c armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1); armada_reg_queue_mod 205 drivers/gpu/drm/armada/armada_plane.c armada_reg_queue_mod(regs, idx, armada_pitch(state, 0), 0xffff, armada_reg_queue_mod 238 drivers/gpu/drm/armada/armada_plane.c armada_reg_queue_mod(regs, idx, cfg, cfg_mask, armada_reg_queue_mod 265 drivers/gpu/drm/armada/armada_plane.c armada_reg_queue_mod(regs, idx, 0, CFG_GRA_ENA, LCD_SPU_DMA_CTRL0); armada_reg_queue_mod 266 drivers/gpu/drm/armada/armada_plane.c armada_reg_queue_mod(regs, idx, CFG_PDWN256x32 | CFG_PDWN256x24 |