arm_smccc_smc 49 arch/arm/mach-artpec/board-artpec6.c arm_smccc_smc(SECURE_OP_L2C_WRITEREG, reg, val, 0, arm_smccc_smc 340 drivers/char/tpm/tpm_crb.c arm_smccc_smc(func_id, 0, 0, 0, 0, 0, 0, 0, &res); arm_smccc_smc 201 drivers/clk/imx/clk-scu.c arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ, arm_smccc_smc 37 drivers/clk/rockchip/clk-ddr.c arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, drate, 0, arm_smccc_smc 51 drivers/clk/rockchip/clk-ddr.c arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0, arm_smccc_smc 64 drivers/clk/rockchip/clk-ddr.c arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, rate, 0, arm_smccc_smc 106 drivers/devfreq/rk3399_dmc.c arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0, arm_smccc_smc 361 drivers/devfreq/rk3399_dmc.c arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index, arm_smccc_smc 397 drivers/devfreq/rk3399_dmc.c arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0, arm_smccc_smc 523 drivers/edac/altera_edac.c arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0, arm_smccc_smc 545 drivers/edac/altera_edac.c arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0, arm_smccc_smc 2160 drivers/edac/altera_edac.c arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0, arm_smccc_smc 84 drivers/edac/bluefield_edac.c arm_smccc_smc(smc_op, smc_arg, 0, 0, 0, 0, 0, 0, &res); arm_smccc_smc 879 drivers/firmware/arm_sdei.c arm_smccc_smc(function_id, arg0, arg1, arg2, arg3, arg4, 0, 0, res); arm_smccc_smc 75 drivers/firmware/meson/meson_sm.c arm_smccc_smc(cmd, arg0, arg1, arg2, arg3, arg4, 0, 0, &res); arm_smccc_smc 131 drivers/firmware/psci/psci.c arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); arm_smccc_smc 254 drivers/firmware/qcom_scm-64.c arm_smccc_smc(cmd, QCOM_SCM_ARGS(1), cmd & (~BIT(ARM_SMCCC_TYPE_SHIFT)), arm_smccc_smc 666 drivers/firmware/stratix10-svc.c arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res); arm_smccc_smc 87 drivers/firmware/xilinx/zynqmp.c arm_smccc_smc(arg0, arg1, arg2, 0, 0, 0, 0, 0, &res); arm_smccc_smc 245 drivers/gpu/drm/mediatek/mtk_hdmi.c arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, arm_smccc_smc 131 drivers/mailbox/zynqmp-ipi-mailbox.c arm_smccc_smc(a0, a1, a2, a3, 0, 0, 0, 0, res); arm_smccc_smc 50 drivers/mfd/altera-sysmgr.c arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, sysmgr_base + reg, arm_smccc_smc 72 drivers/mfd/altera-sysmgr.c arm_smccc_smc(INTEL_SIP_SMC_REG_READ, sysmgr_base + reg, arm_smccc_smc 55 drivers/nvmem/stm32-romem.c arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res); arm_smccc_smc 116 drivers/phy/marvell/phy-mvebu-a3700-comphy.c arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res); arm_smccc_smc 277 drivers/phy/marvell/phy-mvebu-cp110-comphy.c arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res); arm_smccc_smc 348 drivers/remoteproc/stm32_rproc.c arm_smccc_smc(STM32_SMC_RCC, STM32_SMC_REG_WRITE, arm_smccc_smc 69 drivers/rtc/rtc-imx-sc.c arm_smccc_smc(IMX_SIP_SRTC, IMX_SIP_SRTC_SET_TIME, arm_smccc_smc 365 drivers/soc/tegra/pmc.c arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, arm_smccc_smc 388 drivers/soc/tegra/pmc.c arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, arm_smccc_smc 525 drivers/tee/optee/core.c arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res); arm_smccc_smc 54 drivers/watchdog/imx_sc_wdt.c arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_PING_WDOG, arm_smccc_smc 64 drivers/watchdog/imx_sc_wdt.c arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_START_WDOG, arm_smccc_smc 69 drivers/watchdog/imx_sc_wdt.c arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_SET_WDOG_ACT, arm_smccc_smc 79 drivers/watchdog/imx_sc_wdt.c arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_STOP_WDOG, arm_smccc_smc 91 drivers/watchdog/imx_sc_wdt.c arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_SET_TIMEOUT_WDOG, arm_smccc_smc 107 drivers/watchdog/imx_sc_wdt.c arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_SET_PRETIME_WDOG,