ar5312_rst_reg_read   50 arch/mips/ath25/ar5312.c 	u32 ret = ar5312_rst_reg_read(reg);
ar5312_rst_reg_read   59 arch/mips/ath25/ar5312.c 	u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
ar5312_rst_reg_read   60 arch/mips/ath25/ar5312.c 	u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
ar5312_rst_reg_read   61 arch/mips/ath25/ar5312.c 	u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
ar5312_rst_reg_read   62 arch/mips/ath25/ar5312.c 	u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR);   /* clears error */
ar5312_rst_reg_read   78 arch/mips/ath25/ar5312.c 	u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
ar5312_rst_reg_read   79 arch/mips/ath25/ar5312.c 		      ar5312_rst_reg_read(AR5312_IMR);
ar5312_rst_reg_read   92 arch/mips/ath25/ar5312.c 			ar5312_rst_reg_read(AR5312_TIMER);
ar5312_rst_reg_read  108 arch/mips/ath25/ar5312.c 	ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
ar5312_rst_reg_read  295 arch/mips/ath25/ar5312.c 	scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
ar5312_rst_reg_read  299 arch/mips/ath25/ar5312.c 	devid = ar5312_rst_reg_read(AR5312_REV);
ar5312_rst_reg_read  333 arch/mips/ath25/ar5312.c 	clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
ar5312_rst_reg_read  374 arch/mips/ath25/ar5312.c 	devid = ar5312_rst_reg_read(AR5312_REV);
ar5312_rst_reg_read  380 arch/mips/ath25/ar5312.c 	ar5312_rst_reg_read(AR5312_PROCADDR);
ar5312_rst_reg_read  381 arch/mips/ath25/ar5312.c 	ar5312_rst_reg_read(AR5312_DMAADDR);