ar2315_rst_reg_mask   98 arch/mips/ath25/ar2315.c 	ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
ar2315_rst_reg_mask  103 arch/mips/ath25/ar2315.c 	ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
ar2315_rst_reg_mask  339 arch/mips/ath25/ar2315.c 		ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
ar2315_rst_reg_mask  341 arch/mips/ath25/ar2315.c 		ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
ar2315_rst_reg_mask  345 arch/mips/ath25/ar2315.c 		ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
ar2315_rst_reg_mask  352 arch/mips/ath25/ar2315.c 		ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
ar2315_rst_reg_mask  353 arch/mips/ath25/ar2315.c 		ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |