apic 918 arch/x86/events/amd/core.c .apic = 1, apic 1542 arch/x86/events/core.c if (!x86_pmu.apic || !x86_pmu_initialized()) apic 1628 arch/x86/events/core.c x86_pmu.apic = 0; apic 3889 arch/x86/events/intel/core.c .apic = 1, apic 3935 arch/x86/events/intel/core.c .apic = 1, apic 303 arch/x86/events/intel/knc.c .apic = 1, apic 1320 arch/x86/events/intel/p4.c .apic = 1, apic 214 arch/x86/events/intel/p6.c .apic = 1, apic 597 arch/x86/events/perf_event.h int apic; apic 35 arch/x86/hyperv/hv_apic.c static struct apic orig_apic; apic 252 arch/x86/hyperv/hv_apic.c orig_apic = *apic; apic 254 arch/x86/hyperv/hv_apic.c apic->send_IPI = hv_send_ipi; apic 255 arch/x86/hyperv/hv_apic.c apic->send_IPI_mask = hv_send_ipi_mask; apic 256 arch/x86/hyperv/hv_apic.c apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself; apic 257 arch/x86/hyperv/hv_apic.c apic->send_IPI_allbutself = hv_send_ipi_allbutself; apic 258 arch/x86/hyperv/hv_apic.c apic->send_IPI_all = hv_send_ipi_all; apic 259 arch/x86/hyperv/hv_apic.c apic->send_IPI_self = hv_send_ipi_self; apic 274 arch/x86/hyperv/hv_apic.c apic->read = hv_apic_read; apic 275 arch/x86/hyperv/hv_apic.c apic->write = hv_apic_write; apic 276 arch/x86/hyperv/hv_apic.c apic->icr_write = hv_apic_icr_write; apic 277 arch/x86/hyperv/hv_apic.c apic->icr_read = hv_apic_icr_read; apic 23 arch/x86/hyperv/hv_spinlock.c apic->send_IPI(cpu, X86_PLATFORM_IPI_VECTOR); apic 67 arch/x86/hyperv/hv_spinlock.c if (!hv_pvspin || !apic || apic 364 arch/x86/include/asm/apic.h extern struct apic *apic; apic 375 arch/x86/include/asm/apic.h static const struct apic *__apicdrivers_##sym __used \ apic 376 arch/x86/include/asm/apic.h __aligned(sizeof(struct apic *)) \ apic 380 arch/x86/include/asm/apic.h static struct apic *__apicdrivers_##sym1##sym2[2] __used \ apic 381 arch/x86/include/asm/apic.h __aligned(sizeof(struct apic *)) \ apic 384 arch/x86/include/asm/apic.h extern struct apic *__apicdrivers[], *__apicdrivers_end[]; apic 398 arch/x86/include/asm/apic.h return apic->read(reg); apic 403 arch/x86/include/asm/apic.h apic->write(reg, val); apic 408 arch/x86/include/asm/apic.h apic->eoi_write(APIC_EOI, APIC_EOI_ACK); apic 413 arch/x86/include/asm/apic.h return apic->icr_read(); apic 418 arch/x86/include/asm/apic.h apic->icr_write(low, high); apic 423 arch/x86/include/asm/apic.h apic->wait_icr_idle(); apic 428 arch/x86/include/asm/apic.h return apic->safe_wait_icr_idle(); apic 491 arch/x86/include/asm/apic.h extern struct apic apic_noop; apic 497 arch/x86/include/asm/apic.h return apic->get_apic_id(reg); apic 185 arch/x86/include/asm/io_apic.h extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg); apic 188 arch/x86/include/asm/io_apic.h static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) apic 190 arch/x86/include/asm/io_apic.h return x86_apic_ops.io_apic_read(apic, reg); apic 558 arch/x86/include/asm/kvm_host.h struct kvm_lapic *apic; /* kernel irqchip context */ apic 295 arch/x86/include/asm/x86_init.h unsigned int (*io_apic_read) (unsigned int apic, unsigned int reg); apic 213 arch/x86/kernel/acpi/boot.c if (!apic->apic_id_valid(apic_id)) { apic 244 arch/x86/kernel/apic/apic.c apic = &apic_noop; apic 522 arch/x86/kernel/apic/apic.c apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); apic 1492 arch/x86/kernel/apic/apic.c if (apic->disable_esr) { apic 1618 arch/x86/kernel/apic/apic.c if (lapic_is_integrated() && apic->disable_esr) { apic 1629 arch/x86/kernel/apic/apic.c BUG_ON(!apic->apic_id_registered()); apic 1636 arch/x86/kernel/apic/apic.c apic->init_apic_ldr(); apic 1639 arch/x86/kernel/apic/apic.c if (apic->dest_logical) { apic 2506 arch/x86/kernel/apic/apic.c apic->x86_32_early_logical_apicid(cpu); apic 2529 arch/x86/kernel/apic/apic.c struct apic **drv; apic 2542 arch/x86/kernel/apic/apic.c apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); apic 20 arch/x86/kernel/apic/apic_flat_64.c static struct apic apic_physflat; apic 21 arch/x86/kernel/apic/apic_flat_64.c static struct apic apic_flat; apic 23 arch/x86/kernel/apic/apic_flat_64.c struct apic *apic __ro_after_init = &apic_flat; apic 24 arch/x86/kernel/apic/apic_flat_64.c EXPORT_SYMBOL_GPL(apic); apic 56 arch/x86/kernel/apic/apic_flat_64.c __default_send_IPI_dest_field(mask, vector, apic->dest_logical); apic 109 arch/x86/kernel/apic/apic_flat_64.c static struct apic apic_flat __ro_after_init = { apic 194 arch/x86/kernel/apic/apic_flat_64.c if (apic == &apic_physflat || num_possible_cpus() > 8 || apic 201 arch/x86/kernel/apic/apic_flat_64.c static struct apic apic_physflat __ro_after_init = { apic 89 arch/x86/kernel/apic/apic_noop.c struct apic apic_noop __ro_after_init = { apic 24 arch/x86/kernel/apic/apic_numachip.c static const struct apic apic_numachip1; apic 25 arch/x86/kernel/apic/apic_numachip.c static const struct apic apic_numachip2; apic 162 arch/x86/kernel/apic/apic_numachip.c return apic == &apic_numachip1; apic 167 arch/x86/kernel/apic/apic_numachip.c return apic == &apic_numachip2; apic 242 arch/x86/kernel/apic/apic_numachip.c static const struct apic apic_numachip1 __refconst = { apic 291 arch/x86/kernel/apic/apic_numachip.c static const struct apic apic_numachip2 __refconst = { apic 121 arch/x86/kernel/apic/bigsmp_32.c static struct apic apic_bigsmp __ro_after_init = { apic 178 arch/x86/kernel/apic/bigsmp_32.c apic = &apic_bigsmp; apic 33 arch/x86/kernel/apic/hw_nmi.c apic->send_IPI_mask(mask, NMI_VECTOR); apic 88 arch/x86/kernel/apic/io_apic.c int apic, pin; apic 280 arch/x86/kernel/apic/io_apic.c static inline void io_apic_eoi(unsigned int apic, unsigned int vector) apic 282 arch/x86/kernel/apic/io_apic.c struct io_apic __iomem *io_apic = io_apic_base(apic); apic 286 arch/x86/kernel/apic/io_apic.c unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) apic 288 arch/x86/kernel/apic/io_apic.c struct io_apic __iomem *io_apic = io_apic_base(apic); apic 293 arch/x86/kernel/apic/io_apic.c static void io_apic_write(unsigned int apic, unsigned int reg, apic 296 arch/x86/kernel/apic/io_apic.c struct io_apic __iomem *io_apic = io_apic_base(apic); apic 307 arch/x86/kernel/apic/io_apic.c static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) apic 311 arch/x86/kernel/apic/io_apic.c eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); apic 312 arch/x86/kernel/apic/io_apic.c eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); apic 317 arch/x86/kernel/apic/io_apic.c static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) apic 323 arch/x86/kernel/apic/io_apic.c eu.entry = __ioapic_read_entry(apic, pin); apic 335 arch/x86/kernel/apic/io_apic.c static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) apic 340 arch/x86/kernel/apic/io_apic.c io_apic_write(apic, 0x11 + 2*pin, eu.w2); apic 341 arch/x86/kernel/apic/io_apic.c io_apic_write(apic, 0x10 + 2*pin, eu.w1); apic 344 arch/x86/kernel/apic/io_apic.c static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) apic 349 arch/x86/kernel/apic/io_apic.c __ioapic_write_entry(apic, pin, e); apic 358 arch/x86/kernel/apic/io_apic.c static void ioapic_mask_entry(int apic, int pin) apic 364 arch/x86/kernel/apic/io_apic.c io_apic_write(apic, 0x10 + 2*pin, eu.w1); apic 365 arch/x86/kernel/apic/io_apic.c io_apic_write(apic, 0x11 + 2*pin, eu.w2); apic 375 arch/x86/kernel/apic/io_apic.c int node, int apic, int pin) apic 381 arch/x86/kernel/apic/io_apic.c if (entry->apic == apic && entry->pin == pin) apic 387 arch/x86/kernel/apic/io_apic.c node, apic, pin); apic 390 arch/x86/kernel/apic/io_apic.c entry->apic = apic; apic 397 arch/x86/kernel/apic/io_apic.c static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin) apic 402 arch/x86/kernel/apic/io_apic.c if (entry->apic == apic && entry->pin == pin) { apic 410 arch/x86/kernel/apic/io_apic.c int node, int apic, int pin) apic 412 arch/x86/kernel/apic/io_apic.c if (__add_pin_to_irq_node(data, node, apic, pin)) apic 426 arch/x86/kernel/apic/io_apic.c if (entry->apic == oldapic && entry->pin == oldpin) { apic 427 arch/x86/kernel/apic/io_apic.c entry->apic = newapic; apic 451 arch/x86/kernel/apic/io_apic.c io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1); apic 465 arch/x86/kernel/apic/io_apic.c io_apic = io_apic_base(entry->apic); apic 510 arch/x86/kernel/apic/io_apic.c static void __eoi_ioapic_pin(int apic, int pin, int vector) apic 512 arch/x86/kernel/apic/io_apic.c if (mpc_ioapic_ver(apic) >= 0x20) { apic 513 arch/x86/kernel/apic/io_apic.c io_apic_eoi(apic, vector); apic 517 arch/x86/kernel/apic/io_apic.c entry = entry1 = __ioapic_read_entry(apic, pin); apic 525 arch/x86/kernel/apic/io_apic.c __ioapic_write_entry(apic, pin, entry1); apic 530 arch/x86/kernel/apic/io_apic.c __ioapic_write_entry(apic, pin, entry); apic 541 arch/x86/kernel/apic/io_apic.c __eoi_ioapic_pin(entry->apic, entry->pin, vector); apic 545 arch/x86/kernel/apic/io_apic.c static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) apic 550 arch/x86/kernel/apic/io_apic.c entry = ioapic_read_entry(apic, pin); apic 560 arch/x86/kernel/apic/io_apic.c ioapic_write_entry(apic, pin, entry); apic 561 arch/x86/kernel/apic/io_apic.c entry = ioapic_read_entry(apic, pin); apic 574 arch/x86/kernel/apic/io_apic.c ioapic_write_entry(apic, pin, entry); apic 577 arch/x86/kernel/apic/io_apic.c __eoi_ioapic_pin(apic, pin, entry.vector); apic 585 arch/x86/kernel/apic/io_apic.c ioapic_mask_entry(apic, pin); apic 586 arch/x86/kernel/apic/io_apic.c entry = ioapic_read_entry(apic, pin); apic 589 arch/x86/kernel/apic/io_apic.c mpc_ioapic_id(apic), pin); apic 594 arch/x86/kernel/apic/io_apic.c int apic, pin; apic 596 arch/x86/kernel/apic/io_apic.c for_each_ioapic_pin(apic, pin) apic 597 arch/x86/kernel/apic/io_apic.c clear_IO_APIC_pin(apic, pin); apic 643 arch/x86/kernel/apic/io_apic.c int apic, pin; apic 646 arch/x86/kernel/apic/io_apic.c for_each_ioapic(apic) { apic 647 arch/x86/kernel/apic/io_apic.c if (!ioapics[apic].saved_registers) { apic 652 arch/x86/kernel/apic/io_apic.c for_each_pin(apic, pin) apic 653 arch/x86/kernel/apic/io_apic.c ioapics[apic].saved_registers[pin] = apic 654 arch/x86/kernel/apic/io_apic.c ioapic_read_entry(apic, pin); apic 665 arch/x86/kernel/apic/io_apic.c int apic, pin; apic 667 arch/x86/kernel/apic/io_apic.c for_each_ioapic(apic) { apic 668 arch/x86/kernel/apic/io_apic.c if (!ioapics[apic].saved_registers) apic 671 arch/x86/kernel/apic/io_apic.c for_each_pin(apic, pin) { apic 674 arch/x86/kernel/apic/io_apic.c entry = ioapics[apic].saved_registers[pin]; apic 677 arch/x86/kernel/apic/io_apic.c ioapic_write_entry(apic, pin, entry); apic 688 arch/x86/kernel/apic/io_apic.c int apic, pin; apic 690 arch/x86/kernel/apic/io_apic.c for_each_ioapic(apic) { apic 691 arch/x86/kernel/apic/io_apic.c if (!ioapics[apic].saved_registers) apic 694 arch/x86/kernel/apic/io_apic.c for_each_pin(apic, pin) apic 695 arch/x86/kernel/apic/io_apic.c ioapic_write_entry(apic, pin, apic 696 arch/x86/kernel/apic/io_apic.c ioapics[apic].saved_registers[pin]); apic 1233 arch/x86/kernel/apic/io_apic.c static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries) apic 1240 arch/x86/kernel/apic/io_apic.c printk(KERN_DEBUG "IOAPIC %d:\n", apic); apic 1242 arch/x86/kernel/apic/io_apic.c entry = ioapic_read_entry(apic, i); apic 1356 arch/x86/kernel/apic/io_apic.c pr_cont("-> %d:%d", entry->apic, entry->pin); apic 1364 arch/x86/kernel/apic/io_apic.c static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; apic 1369 arch/x86/kernel/apic/io_apic.c int apic, pin; apic 1377 arch/x86/kernel/apic/io_apic.c for_each_ioapic_pin(apic, pin) { apic 1379 arch/x86/kernel/apic/io_apic.c struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); apic 1385 arch/x86/kernel/apic/io_apic.c ioapic_i8259.apic = apic; apic 1402 arch/x86/kernel/apic/io_apic.c ioapic_i8259.apic = i8259_apic; apic 1405 arch/x86/kernel/apic/io_apic.c if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && apic 1438 arch/x86/kernel/apic/io_apic.c ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); apic 1473 arch/x86/kernel/apic/io_apic.c apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); apic 1499 arch/x86/kernel/apic/io_apic.c if (apic->check_apicid_used(&phys_id_present_map, apic 1514 arch/x86/kernel/apic/io_apic.c apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), apic 1716 arch/x86/kernel/apic/io_apic.c reg = io_apic_read(entry->apic, 0x10 + pin*2); apic 1881 arch/x86/kernel/apic/io_apic.c __ioapic_write_entry(entry->apic, entry->pin, mpd->entry); apic 1928 arch/x86/kernel/apic/io_apic.c rentry = __ioapic_read_entry(p->apic, p->pin); apic 2040 arch/x86/kernel/apic/io_apic.c int apic, pin, i; apic 2049 arch/x86/kernel/apic/io_apic.c apic = find_isa_irq_apic(8, mp_INT); apic 2050 arch/x86/kernel/apic/io_apic.c if (apic == -1) { apic 2055 arch/x86/kernel/apic/io_apic.c entry0 = ioapic_read_entry(apic, pin); apic 2056 arch/x86/kernel/apic/io_apic.c clear_IO_APIC_pin(apic, pin); apic 2068 arch/x86/kernel/apic/io_apic.c ioapic_write_entry(apic, pin, entry1); apic 2085 arch/x86/kernel/apic/io_apic.c clear_IO_APIC_pin(apic, pin); apic 2087 arch/x86/kernel/apic/io_apic.c ioapic_write_entry(apic, pin, entry0); apic 2161 arch/x86/kernel/apic/io_apic.c apic2 = ioapic_i8259.apic; apic 2472 arch/x86/kernel/apic/io_apic.c apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); apic 2488 arch/x86/kernel/apic/io_apic.c if (apic->check_apicid_used(&apic_id_map, apic_id)) { apic 2491 arch/x86/kernel/apic/io_apic.c if (!apic->check_apicid_used(&apic_id_map, i)) apic 2504 arch/x86/kernel/apic/io_apic.c apic->apicid_to_cpu_present(apic_id, &tmp); apic 2958 arch/x86/kernel/apic/io_apic.c entry->delivery_mode = apic->irq_delivery_mode; apic 2959 arch/x86/kernel/apic/io_apic.c entry->dest_mode = apic->irq_dest_mode; apic 54 arch/x86/kernel/apic/ipi.c apic->send_IPI_allbutself(vector); apic 56 arch/x86/kernel/apic/ipi.c apic->send_IPI_mask_allbutself(cpu_online_mask, vector); apic 70 arch/x86/kernel/apic/ipi.c apic->send_IPI(cpu, RESCHEDULE_VECTOR); apic 75 arch/x86/kernel/apic/ipi.c apic->send_IPI(cpu, CALL_FUNCTION_SINGLE_VECTOR); apic 87 arch/x86/kernel/apic/ipi.c apic->send_IPI_all(CALL_FUNCTION_VECTOR); apic 89 arch/x86/kernel/apic/ipi.c apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR); apic 94 arch/x86/kernel/apic/ipi.c apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); apic 226 arch/x86/kernel/apic/ipi.c apic->send_IPI_mask(cpumask_of(cpu), vector); apic 262 arch/x86/kernel/apic/ipi.c vector, apic->dest_logical); apic 281 arch/x86/kernel/apic/ipi.c vector, apic->dest_logical); apic 299 arch/x86/kernel/apic/ipi.c __default_send_IPI_dest_field(mask, vector, apic->dest_logical); apic 35 arch/x86/kernel/apic/msi.c ((apic->irq_dest_mode == 0) ? apic 63 arch/x86/kernel/apic/probe_32.c static struct apic apic_default __ro_after_init = { apic 115 arch/x86/kernel/apic/probe_32.c struct apic *apic __ro_after_init = &apic_default; apic 116 arch/x86/kernel/apic/probe_32.c EXPORT_SYMBOL_GPL(apic); apic 121 arch/x86/kernel/apic/probe_32.c struct apic **drv; apic 128 arch/x86/kernel/apic/probe_32.c apic = *drv; apic 166 arch/x86/kernel/apic/probe_32.c if (!cmdline_apic && apic == &apic_default) apic 170 arch/x86/kernel/apic/probe_32.c if (apic->setup_apic_routing) apic 171 arch/x86/kernel/apic/probe_32.c apic->setup_apic_routing(); apic 180 arch/x86/kernel/apic/probe_32.c struct apic **drv; apic 184 arch/x86/kernel/apic/probe_32.c apic = *drv; apic 192 arch/x86/kernel/apic/probe_32.c printk(KERN_INFO "Using APIC driver %s\n", apic->name); apic 198 arch/x86/kernel/apic/probe_32.c struct apic **drv; apic 207 arch/x86/kernel/apic/probe_32.c apic = *drv; apic 209 arch/x86/kernel/apic/probe_32.c apic->name); apic 20 arch/x86/kernel/apic/probe_64.c struct apic **drv; apic 26 arch/x86/kernel/apic/probe_64.c if (apic != *drv) { apic 27 arch/x86/kernel/apic/probe_64.c apic = *drv; apic 29 arch/x86/kernel/apic/probe_64.c apic->name); apic 41 arch/x86/kernel/apic/probe_64.c struct apic **drv; apic 45 arch/x86/kernel/apic/probe_64.c if (apic != *drv) { apic 46 arch/x86/kernel/apic/probe_64.c apic = *drv; apic 48 arch/x86/kernel/apic/probe_64.c apic->name); apic 125 arch/x86/kernel/apic/vector.c apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); apic 807 arch/x86/kernel/apic/vector.c apic->send_IPI(apicd->cpu, apicd->vector); apic 880 arch/x86/kernel/apic/vector.c apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); apic 899 arch/x86/kernel/apic/vector.c apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); apic 64 arch/x86/kernel/apic/x2apic_cluster.c __x2apic_send_IPI_dest(dest, vector, apic->dest_logical); apic 179 arch/x86/kernel/apic/x2apic_cluster.c static struct apic apic_x2apic_cluster __ro_after_init = { apic 10 arch/x86/kernel/apic/x2apic_phys.c static struct apic apic_x2apic_phys; apic 95 arch/x86/kernel/apic/x2apic_phys.c return apic == &apic_x2apic_phys; apic 143 arch/x86/kernel/apic/x2apic_phys.c static struct apic apic_x2apic_phys __ro_after_init = { apic 50 arch/x86/kernel/apic/x2apic_uv_x.c static struct apic apic_x2apic_uv_x; apic 639 arch/x86/kernel/apic/x2apic_uv_x.c return apic == &apic_x2apic_uv_x; apic 642 arch/x86/kernel/apic/x2apic_uv_x.c static struct apic apic_x2apic_uv_x __ro_after_init = { apic 760 arch/x86/kernel/cpu/common.c c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); apic 768 arch/x86/kernel/cpu/common.c c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & apic 1391 arch/x86/kernel/cpu/common.c c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); apic 1452 arch/x86/kernel/cpu/common.c apicid = apic->cpu_present_to_apicid(cpu); apic 1503 arch/x86/kernel/cpu/common.c c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); apic 347 arch/x86/kernel/cpu/mce/amd.c static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) apic 351 arch/x86/kernel/cpu/mce/amd.c if (apic < 0) { apic 358 arch/x86/kernel/cpu/mce/amd.c if (apic != msr) { apic 369 arch/x86/kernel/cpu/mce/amd.c b->cpu, apic, b->bank, b->block, b->address, hi, lo); apic 255 arch/x86/kernel/cpu/mce/inject.c apic->send_IPI_mask(mce_inject_cpumask, apic 140 arch/x86/kernel/cpu/topology.c c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, apic 142 arch/x86/kernel/cpu/topology.c c->cpu_die_id = apic->phys_pkg_id(c->initial_apicid, apic 144 arch/x86/kernel/cpu/topology.c c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, apic 149 arch/x86/kernel/cpu/topology.c c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); apic 31 arch/x86/kernel/irq_work.c apic->send_IPI_self(IRQ_WORK_VECTOR); apic 306 arch/x86/kernel/kvm.c apic->native_eoi_write(APIC_EOI, APIC_EOI_ACK); apic 510 arch/x86/kernel/kvm.c apic->send_IPI_mask = kvm_send_ipi_mask; apic 511 arch/x86/kernel/kvm.c apic->send_IPI_mask_allbutself = kvm_send_ipi_mask_allbutself; apic 78 arch/x86/kernel/nmi_selftest.c apic->send_IPI_mask(mask, NMI_VECTOR); apic 762 arch/x86/kernel/smpboot.c apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); apic 989 arch/x86/kernel/smpboot.c if (apic->dest_logical == APIC_DEST_LOGICAL) apic 1085 arch/x86/kernel/smpboot.c if (apic->wakeup_secondary_cpu) apic 1086 arch/x86/kernel/smpboot.c boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); apic 1137 arch/x86/kernel/smpboot.c int apicid = apic->cpu_present_to_apicid(cpu); apic 1148 arch/x86/kernel/smpboot.c !apic->apic_id_valid(apicid)) { apic 1285 arch/x86/kernel/smpboot.c if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { apic 1472 arch/x86/kernel/smpboot.c if (apic->cpu_present_to_apicid(0) == BAD_APICID && apic 1473 arch/x86/kernel/smpboot.c apic->apic_id_valid(apicid)) apic 138 arch/x86/kernel/vsmp_64.c apic->phys_pkg_id = apicid_phys_pkg_id; apic 70 arch/x86/kvm/cpuid.c struct kvm_lapic *apic = vcpu->arch.apic; apic 87 arch/x86/kvm/cpuid.c if (apic) { apic 89 arch/x86/kvm/cpuid.c apic->lapic_timer.timer_mode_mask = 3 << 17; apic 91 arch/x86/kvm/cpuid.c apic->lapic_timer.timer_mode_mask = 1 << 17; apic 14 arch/x86/kvm/debugfs.c *val = vcpu->arch.apic->lapic_timer.timer_advance_ns; apic 323 arch/x86/kvm/hyperv.c ret = kvm_irq_delivery_to_apic(vcpu->kvm, vcpu->arch.apic, &irq, NULL); apic 426 arch/x86/kvm/ioapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 453 arch/x86/kvm/ioapic.c kvm_lapic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) apic 78 arch/x86/kvm/irq_comm.c } else if (kvm_apic_sw_enabled(vcpu->arch.apic)) { apic 83 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 85 arch/x86/kvm/lapic.c return apic_test_vector(vector, apic->regs + APIC_ISR) || apic 86 arch/x86/kvm/lapic.c apic_test_vector(vector, apic->regs + APIC_IRR); apic 102 arch/x86/kvm/lapic.c static inline int apic_enabled(struct kvm_lapic *apic) apic 104 arch/x86/kvm/lapic.c return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); apic 114 arch/x86/kvm/lapic.c static inline u32 kvm_x2apic_id(struct kvm_lapic *apic) apic 116 arch/x86/kvm/lapic.c return apic->vcpu->vcpu_id; apic 181 arch/x86/kvm/lapic.c max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); apic 193 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 203 arch/x86/kvm/lapic.c xapic_id = kvm_xapic_id(apic); apic 204 arch/x86/kvm/lapic.c x2apic_id = kvm_x2apic_id(apic); apic 207 arch/x86/kvm/lapic.c if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) && apic 209 arch/x86/kvm/lapic.c new->phys_map[x2apic_id] = apic; apic 214 arch/x86/kvm/lapic.c if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) apic 215 arch/x86/kvm/lapic.c new->phys_map[xapic_id] = apic; apic 217 arch/x86/kvm/lapic.c if (!kvm_apic_sw_enabled(apic)) apic 220 arch/x86/kvm/lapic.c ldr = kvm_lapic_get_reg(apic, APIC_LDR); apic 222 arch/x86/kvm/lapic.c if (apic_x2apic_mode(apic)) { apic 226 arch/x86/kvm/lapic.c if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) apic 236 arch/x86/kvm/lapic.c cluster[ffs(mask) - 1] = apic; apic 250 arch/x86/kvm/lapic.c static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) apic 254 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_SPIV, val); apic 256 arch/x86/kvm/lapic.c if (enabled != apic->sw_enabled) { apic 257 arch/x86/kvm/lapic.c apic->sw_enabled = enabled; apic 263 arch/x86/kvm/lapic.c recalculate_apic_map(apic->vcpu->kvm); apic 267 arch/x86/kvm/lapic.c static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id) apic 269 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_ID, id << 24); apic 270 arch/x86/kvm/lapic.c recalculate_apic_map(apic->vcpu->kvm); apic 273 arch/x86/kvm/lapic.c static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) apic 275 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_LDR, id); apic 276 arch/x86/kvm/lapic.c recalculate_apic_map(apic->vcpu->kvm); apic 284 arch/x86/kvm/lapic.c static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id) apic 288 arch/x86/kvm/lapic.c WARN_ON_ONCE(id != apic->vcpu->vcpu_id); apic 290 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_ID, id); apic 291 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_LDR, ldr); apic 292 arch/x86/kvm/lapic.c recalculate_apic_map(apic->vcpu->kvm); apic 295 arch/x86/kvm/lapic.c static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) apic 297 arch/x86/kvm/lapic.c return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); apic 300 arch/x86/kvm/lapic.c static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) apic 302 arch/x86/kvm/lapic.c return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; apic 305 arch/x86/kvm/lapic.c static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) apic 307 arch/x86/kvm/lapic.c return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; apic 310 arch/x86/kvm/lapic.c static inline int apic_lvtt_period(struct kvm_lapic *apic) apic 312 arch/x86/kvm/lapic.c return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; apic 315 arch/x86/kvm/lapic.c static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) apic 317 arch/x86/kvm/lapic.c return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; apic 327 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 341 arch/x86/kvm/lapic.c feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); apic 345 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_LVR, v); apic 417 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 419 arch/x86/kvm/lapic.c return __kvm_apic_update_irr(pir, apic->regs, max_irr); apic 423 arch/x86/kvm/lapic.c static inline int apic_search_irr(struct kvm_lapic *apic) apic 425 arch/x86/kvm/lapic.c return find_highest_vector(apic->regs + APIC_IRR); apic 428 arch/x86/kvm/lapic.c static inline int apic_find_highest_irr(struct kvm_lapic *apic) apic 436 arch/x86/kvm/lapic.c if (!apic->irr_pending) apic 439 arch/x86/kvm/lapic.c result = apic_search_irr(apic); apic 445 arch/x86/kvm/lapic.c static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) apic 449 arch/x86/kvm/lapic.c vcpu = apic->vcpu; apic 453 arch/x86/kvm/lapic.c kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); apic 455 arch/x86/kvm/lapic.c apic_find_highest_irr(apic)); apic 457 arch/x86/kvm/lapic.c apic->irr_pending = false; apic 458 arch/x86/kvm/lapic.c kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); apic 459 arch/x86/kvm/lapic.c if (apic_search_irr(apic) != -1) apic 460 arch/x86/kvm/lapic.c apic->irr_pending = true; apic 464 arch/x86/kvm/lapic.c static inline void apic_set_isr(int vec, struct kvm_lapic *apic) apic 468 arch/x86/kvm/lapic.c if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) apic 471 arch/x86/kvm/lapic.c vcpu = apic->vcpu; apic 481 arch/x86/kvm/lapic.c ++apic->isr_count; apic 482 arch/x86/kvm/lapic.c BUG_ON(apic->isr_count > MAX_APIC_VECTOR); apic 488 arch/x86/kvm/lapic.c apic->highest_isr_cache = vec; apic 492 arch/x86/kvm/lapic.c static inline int apic_find_highest_isr(struct kvm_lapic *apic) apic 500 arch/x86/kvm/lapic.c if (!apic->isr_count) apic 502 arch/x86/kvm/lapic.c if (likely(apic->highest_isr_cache != -1)) apic 503 arch/x86/kvm/lapic.c return apic->highest_isr_cache; apic 505 arch/x86/kvm/lapic.c result = find_highest_vector(apic->regs + APIC_ISR); apic 511 arch/x86/kvm/lapic.c static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) apic 514 arch/x86/kvm/lapic.c if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) apic 517 arch/x86/kvm/lapic.c vcpu = apic->vcpu; apic 528 arch/x86/kvm/lapic.c apic_find_highest_isr(apic)); apic 530 arch/x86/kvm/lapic.c --apic->isr_count; apic 531 arch/x86/kvm/lapic.c BUG_ON(apic->isr_count < 0); apic 532 arch/x86/kvm/lapic.c apic->highest_isr_cache = -1; apic 543 arch/x86/kvm/lapic.c return apic_find_highest_irr(vcpu->arch.apic); apic 547 arch/x86/kvm/lapic.c static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, apic 554 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 556 arch/x86/kvm/lapic.c return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, apic 668 arch/x86/kvm/lapic.c static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr) apic 671 arch/x86/kvm/lapic.c if (apic->vcpu->arch.apicv_active) apic 672 arch/x86/kvm/lapic.c highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu); apic 674 arch/x86/kvm/lapic.c highest_irr = apic_find_highest_irr(apic); apic 680 arch/x86/kvm/lapic.c static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr) apic 685 arch/x86/kvm/lapic.c old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); apic 686 arch/x86/kvm/lapic.c tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); apic 687 arch/x86/kvm/lapic.c isr = apic_find_highest_isr(apic); apic 697 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); apic 702 arch/x86/kvm/lapic.c static void apic_update_ppr(struct kvm_lapic *apic) apic 706 arch/x86/kvm/lapic.c if (__apic_update_ppr(apic, &ppr) && apic 707 arch/x86/kvm/lapic.c apic_has_interrupt_for_ppr(apic, ppr) != -1) apic 708 arch/x86/kvm/lapic.c kvm_make_request(KVM_REQ_EVENT, apic->vcpu); apic 713 arch/x86/kvm/lapic.c apic_update_ppr(vcpu->arch.apic); apic 717 arch/x86/kvm/lapic.c static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) apic 719 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); apic 720 arch/x86/kvm/lapic.c apic_update_ppr(apic); apic 723 arch/x86/kvm/lapic.c static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) apic 725 arch/x86/kvm/lapic.c return mda == (apic_x2apic_mode(apic) ? apic 729 arch/x86/kvm/lapic.c static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) apic 731 arch/x86/kvm/lapic.c if (kvm_apic_broadcast(apic, mda)) apic 734 arch/x86/kvm/lapic.c if (apic_x2apic_mode(apic)) apic 735 arch/x86/kvm/lapic.c return mda == kvm_x2apic_id(apic); apic 743 arch/x86/kvm/lapic.c if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic)) apic 746 arch/x86/kvm/lapic.c return mda == kvm_xapic_id(apic); apic 749 arch/x86/kvm/lapic.c static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) apic 753 arch/x86/kvm/lapic.c if (kvm_apic_broadcast(apic, mda)) apic 756 arch/x86/kvm/lapic.c logical_id = kvm_lapic_get_reg(apic, APIC_LDR); apic 758 arch/x86/kvm/lapic.c if (apic_x2apic_mode(apic)) apic 764 arch/x86/kvm/lapic.c switch (kvm_lapic_get_reg(apic, APIC_DFR)) { apic 806 arch/x86/kvm/lapic.c struct kvm_lapic *target = vcpu->arch.apic; apic 1024 arch/x86/kvm/lapic.c static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, apic 1029 arch/x86/kvm/lapic.c struct kvm_vcpu *vcpu = apic->vcpu; apic 1042 arch/x86/kvm/lapic.c if (unlikely(!apic_enabled(apic))) apic 1052 arch/x86/kvm/lapic.c if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { apic 1055 arch/x86/kvm/lapic.c apic->regs + APIC_TMR); apic 1058 arch/x86/kvm/lapic.c apic->regs + APIC_TMR); apic 1062 arch/x86/kvm/lapic.c kvm_lapic_set_irr(vector, apic); apic 1091 arch/x86/kvm/lapic.c apic->pending_events = (1UL << KVM_APIC_INIT); apic 1102 arch/x86/kvm/lapic.c apic->sipi_vector = vector; apic 1105 arch/x86/kvm/lapic.c set_bit(KVM_APIC_SIPI, &apic->pending_events); apic 1131 arch/x86/kvm/lapic.c static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) apic 1133 arch/x86/kvm/lapic.c return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); apic 1136 arch/x86/kvm/lapic.c static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) apic 1141 arch/x86/kvm/lapic.c if (!kvm_ioapic_handles_vector(apic, vector)) apic 1145 arch/x86/kvm/lapic.c if (irqchip_split(apic->vcpu->kvm)) { apic 1146 arch/x86/kvm/lapic.c apic->vcpu->arch.pending_ioapic_eoi = vector; apic 1147 arch/x86/kvm/lapic.c kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); apic 1151 arch/x86/kvm/lapic.c if (apic_test_vector(vector, apic->regs + APIC_TMR)) apic 1156 arch/x86/kvm/lapic.c kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); apic 1159 arch/x86/kvm/lapic.c static int apic_set_eoi(struct kvm_lapic *apic) apic 1161 arch/x86/kvm/lapic.c int vector = apic_find_highest_isr(apic); apic 1163 arch/x86/kvm/lapic.c trace_kvm_eoi(apic, vector); apic 1172 arch/x86/kvm/lapic.c apic_clear_isr(vector, apic); apic 1173 arch/x86/kvm/lapic.c apic_update_ppr(apic); apic 1175 arch/x86/kvm/lapic.c if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap)) apic 1176 arch/x86/kvm/lapic.c kvm_hv_synic_send_eoi(apic->vcpu, vector); apic 1178 arch/x86/kvm/lapic.c kvm_ioapic_send_eoi(apic, vector); apic 1179 arch/x86/kvm/lapic.c kvm_make_request(KVM_REQ_EVENT, apic->vcpu); apic 1189 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 1191 arch/x86/kvm/lapic.c trace_kvm_eoi(apic, vector); apic 1193 arch/x86/kvm/lapic.c kvm_ioapic_send_eoi(apic, vector); apic 1194 arch/x86/kvm/lapic.c kvm_make_request(KVM_REQ_EVENT, apic->vcpu); apic 1198 arch/x86/kvm/lapic.c static void apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high) apic 1209 arch/x86/kvm/lapic.c if (apic_x2apic_mode(apic)) apic 1216 arch/x86/kvm/lapic.c kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); apic 1219 arch/x86/kvm/lapic.c static u32 apic_get_tmcct(struct kvm_lapic *apic) apic 1225 arch/x86/kvm/lapic.c ASSERT(apic != NULL); apic 1228 arch/x86/kvm/lapic.c if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || apic 1229 arch/x86/kvm/lapic.c apic->lapic_timer.period == 0) apic 1233 arch/x86/kvm/lapic.c remaining = ktime_sub(apic->lapic_timer.target_expiration, now); apic 1237 arch/x86/kvm/lapic.c ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); apic 1239 arch/x86/kvm/lapic.c (APIC_BUS_CYCLE_NS * apic->divide_count)); apic 1244 arch/x86/kvm/lapic.c static void __report_tpr_access(struct kvm_lapic *apic, bool write) apic 1246 arch/x86/kvm/lapic.c struct kvm_vcpu *vcpu = apic->vcpu; apic 1254 arch/x86/kvm/lapic.c static inline void report_tpr_access(struct kvm_lapic *apic, bool write) apic 1256 arch/x86/kvm/lapic.c if (apic->vcpu->arch.tpr_access_reporting) apic 1257 arch/x86/kvm/lapic.c __report_tpr_access(apic, write); apic 1260 arch/x86/kvm/lapic.c static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) apic 1272 arch/x86/kvm/lapic.c if (apic_lvtt_tscdeadline(apic)) apic 1275 arch/x86/kvm/lapic.c val = apic_get_tmcct(apic); apic 1278 arch/x86/kvm/lapic.c apic_update_ppr(apic); apic 1279 arch/x86/kvm/lapic.c val = kvm_lapic_get_reg(apic, offset); apic 1282 arch/x86/kvm/lapic.c report_tpr_access(apic, false); apic 1285 arch/x86/kvm/lapic.c val = kvm_lapic_get_reg(apic, offset); apic 1301 arch/x86/kvm/lapic.c int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, apic 1332 arch/x86/kvm/lapic.c if (!apic_x2apic_mode(apic)) apic 1338 arch/x86/kvm/lapic.c result = __apic_read(apic, offset & ~0xf); apic 1357 arch/x86/kvm/lapic.c static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) apic 1359 arch/x86/kvm/lapic.c return addr >= apic->base_address && apic 1360 arch/x86/kvm/lapic.c addr < apic->base_address + LAPIC_MMIO_LENGTH; apic 1366 arch/x86/kvm/lapic.c struct kvm_lapic *apic = to_lapic(this); apic 1367 arch/x86/kvm/lapic.c u32 offset = address - apic->base_address; apic 1369 arch/x86/kvm/lapic.c if (!apic_mmio_in_range(apic, address)) apic 1372 arch/x86/kvm/lapic.c if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { apic 1381 arch/x86/kvm/lapic.c kvm_lapic_reg_read(apic, offset, len, data); apic 1386 arch/x86/kvm/lapic.c static void update_divide_count(struct kvm_lapic *apic) apic 1390 arch/x86/kvm/lapic.c tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); apic 1393 arch/x86/kvm/lapic.c apic->divide_count = 0x1 << (tmp2 & 0x7); apic 1396 arch/x86/kvm/lapic.c static void limit_periodic_timer_frequency(struct kvm_lapic *apic) apic 1403 arch/x86/kvm/lapic.c if (apic_lvtt_period(apic) && apic->lapic_timer.period) { apic 1406 arch/x86/kvm/lapic.c if (apic->lapic_timer.period < min_period) { apic 1410 arch/x86/kvm/lapic.c apic->vcpu->vcpu_id, apic 1411 arch/x86/kvm/lapic.c apic->lapic_timer.period, min_period); apic 1412 arch/x86/kvm/lapic.c apic->lapic_timer.period = min_period; apic 1417 arch/x86/kvm/lapic.c static void apic_update_lvtt(struct kvm_lapic *apic) apic 1419 arch/x86/kvm/lapic.c u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & apic 1420 arch/x86/kvm/lapic.c apic->lapic_timer.timer_mode_mask; apic 1422 arch/x86/kvm/lapic.c if (apic->lapic_timer.timer_mode != timer_mode) { apic 1423 arch/x86/kvm/lapic.c if (apic_lvtt_tscdeadline(apic) != (timer_mode == apic 1425 arch/x86/kvm/lapic.c hrtimer_cancel(&apic->lapic_timer.timer); apic 1426 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_TMICT, 0); apic 1427 arch/x86/kvm/lapic.c apic->lapic_timer.period = 0; apic 1428 arch/x86/kvm/lapic.c apic->lapic_timer.tscdeadline = 0; apic 1430 arch/x86/kvm/lapic.c apic->lapic_timer.timer_mode = timer_mode; apic 1431 arch/x86/kvm/lapic.c limit_periodic_timer_frequency(apic); apic 1442 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 1443 arch/x86/kvm/lapic.c u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); apic 1445 arch/x86/kvm/lapic.c if (kvm_apic_hw_enabled(apic)) { apic 1447 arch/x86/kvm/lapic.c void *bitmap = apic->regs + APIC_ISR; apic 1450 arch/x86/kvm/lapic.c bitmap = apic->regs + APIC_IRR; apic 1460 arch/x86/kvm/lapic.c u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns; apic 1481 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 1482 arch/x86/kvm/lapic.c u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns; apic 1504 arch/x86/kvm/lapic.c apic->lapic_timer.timer_advance_ns = timer_advance_ns; apic 1509 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 1512 arch/x86/kvm/lapic.c if (apic->lapic_timer.expired_tscdeadline == 0) apic 1515 arch/x86/kvm/lapic.c tsc_deadline = apic->lapic_timer.expired_tscdeadline; apic 1516 arch/x86/kvm/lapic.c apic->lapic_timer.expired_tscdeadline = 0; apic 1518 arch/x86/kvm/lapic.c apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline; apic 1524 arch/x86/kvm/lapic.c adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta); apic 1534 arch/x86/kvm/lapic.c static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic) apic 1536 arch/x86/kvm/lapic.c struct kvm_timer *ktimer = &apic->lapic_timer; apic 1538 arch/x86/kvm/lapic.c kvm_apic_local_deliver(apic, APIC_LVTT); apic 1539 arch/x86/kvm/lapic.c if (apic_lvtt_tscdeadline(apic)) apic 1541 arch/x86/kvm/lapic.c if (apic_lvtt_oneshot(apic)) { apic 1547 arch/x86/kvm/lapic.c static void apic_timer_expired(struct kvm_lapic *apic) apic 1549 arch/x86/kvm/lapic.c struct kvm_vcpu *vcpu = apic->vcpu; apic 1550 arch/x86/kvm/lapic.c struct kvm_timer *ktimer = &apic->lapic_timer; apic 1552 arch/x86/kvm/lapic.c if (atomic_read(&apic->lapic_timer.pending)) apic 1555 arch/x86/kvm/lapic.c if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use) apic 1558 arch/x86/kvm/lapic.c if (kvm_use_posted_timer_interrupt(apic->vcpu)) { apic 1559 arch/x86/kvm/lapic.c if (apic->lapic_timer.timer_advance_ns) apic 1561 arch/x86/kvm/lapic.c kvm_apic_inject_pending_timer_irqs(apic); apic 1565 arch/x86/kvm/lapic.c atomic_inc(&apic->lapic_timer.pending); apic 1569 arch/x86/kvm/lapic.c static void start_sw_tscdeadline(struct kvm_lapic *apic) apic 1571 arch/x86/kvm/lapic.c struct kvm_timer *ktimer = &apic->lapic_timer; apic 1575 arch/x86/kvm/lapic.c struct kvm_vcpu *vcpu = apic->vcpu; apic 1592 arch/x86/kvm/lapic.c likely(ns > apic->lapic_timer.timer_advance_ns)) { apic 1597 arch/x86/kvm/lapic.c apic_timer_expired(apic); apic 1602 arch/x86/kvm/lapic.c static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) apic 1607 arch/x86/kvm/lapic.c apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) apic 1608 arch/x86/kvm/lapic.c * APIC_BUS_CYCLE_NS * apic->divide_count; apic 1609 arch/x86/kvm/lapic.c limit_periodic_timer_frequency(apic); apic 1612 arch/x86/kvm/lapic.c remaining = ktime_sub(apic->lapic_timer.target_expiration, now); apic 1618 arch/x86/kvm/lapic.c apic->divide_count, old_divisor); apic 1620 arch/x86/kvm/lapic.c apic->lapic_timer.tscdeadline += apic 1621 arch/x86/kvm/lapic.c nsec_to_cycles(apic->vcpu, ns_remaining_new) - apic 1622 arch/x86/kvm/lapic.c nsec_to_cycles(apic->vcpu, ns_remaining_old); apic 1623 arch/x86/kvm/lapic.c apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); apic 1626 arch/x86/kvm/lapic.c static bool set_target_expiration(struct kvm_lapic *apic) apic 1632 arch/x86/kvm/lapic.c apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) apic 1633 arch/x86/kvm/lapic.c * APIC_BUS_CYCLE_NS * apic->divide_count; apic 1635 arch/x86/kvm/lapic.c if (!apic->lapic_timer.period) { apic 1636 arch/x86/kvm/lapic.c apic->lapic_timer.tscdeadline = 0; apic 1640 arch/x86/kvm/lapic.c limit_periodic_timer_frequency(apic); apic 1642 arch/x86/kvm/lapic.c apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + apic 1643 arch/x86/kvm/lapic.c nsec_to_cycles(apic->vcpu, apic->lapic_timer.period); apic 1644 arch/x86/kvm/lapic.c apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period); apic 1649 arch/x86/kvm/lapic.c static void advance_periodic_target_expiration(struct kvm_lapic *apic) apic 1662 arch/x86/kvm/lapic.c apic->lapic_timer.target_expiration = apic 1663 arch/x86/kvm/lapic.c ktime_add_ns(apic->lapic_timer.target_expiration, apic 1664 arch/x86/kvm/lapic.c apic->lapic_timer.period); apic 1665 arch/x86/kvm/lapic.c delta = ktime_sub(apic->lapic_timer.target_expiration, now); apic 1666 arch/x86/kvm/lapic.c apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + apic 1667 arch/x86/kvm/lapic.c nsec_to_cycles(apic->vcpu, delta); apic 1670 arch/x86/kvm/lapic.c static void start_sw_period(struct kvm_lapic *apic) apic 1672 arch/x86/kvm/lapic.c if (!apic->lapic_timer.period) apic 1676 arch/x86/kvm/lapic.c apic->lapic_timer.target_expiration)) { apic 1677 arch/x86/kvm/lapic.c apic_timer_expired(apic); apic 1679 arch/x86/kvm/lapic.c if (apic_lvtt_oneshot(apic)) apic 1682 arch/x86/kvm/lapic.c advance_periodic_target_expiration(apic); apic 1685 arch/x86/kvm/lapic.c hrtimer_start(&apic->lapic_timer.timer, apic 1686 arch/x86/kvm/lapic.c apic->lapic_timer.target_expiration, apic 1695 arch/x86/kvm/lapic.c return vcpu->arch.apic->lapic_timer.hv_timer_in_use; apic 1699 arch/x86/kvm/lapic.c static void cancel_hv_timer(struct kvm_lapic *apic) apic 1702 arch/x86/kvm/lapic.c WARN_ON(!apic->lapic_timer.hv_timer_in_use); apic 1703 arch/x86/kvm/lapic.c kvm_x86_ops->cancel_hv_timer(apic->vcpu); apic 1704 arch/x86/kvm/lapic.c apic->lapic_timer.hv_timer_in_use = false; apic 1707 arch/x86/kvm/lapic.c static bool start_hv_timer(struct kvm_lapic *apic) apic 1709 arch/x86/kvm/lapic.c struct kvm_timer *ktimer = &apic->lapic_timer; apic 1710 arch/x86/kvm/lapic.c struct kvm_vcpu *vcpu = apic->vcpu; apic 1731 arch/x86/kvm/lapic.c if (!apic_lvtt_period(apic)) { apic 1737 arch/x86/kvm/lapic.c cancel_hv_timer(apic); apic 1739 arch/x86/kvm/lapic.c apic_timer_expired(apic); apic 1740 arch/x86/kvm/lapic.c cancel_hv_timer(apic); apic 1749 arch/x86/kvm/lapic.c static void start_sw_timer(struct kvm_lapic *apic) apic 1751 arch/x86/kvm/lapic.c struct kvm_timer *ktimer = &apic->lapic_timer; apic 1754 arch/x86/kvm/lapic.c if (apic->lapic_timer.hv_timer_in_use) apic 1755 arch/x86/kvm/lapic.c cancel_hv_timer(apic); apic 1756 arch/x86/kvm/lapic.c if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) apic 1759 arch/x86/kvm/lapic.c if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) apic 1760 arch/x86/kvm/lapic.c start_sw_period(apic); apic 1761 arch/x86/kvm/lapic.c else if (apic_lvtt_tscdeadline(apic)) apic 1762 arch/x86/kvm/lapic.c start_sw_tscdeadline(apic); apic 1763 arch/x86/kvm/lapic.c trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); apic 1766 arch/x86/kvm/lapic.c static void restart_apic_timer(struct kvm_lapic *apic) apic 1770 arch/x86/kvm/lapic.c if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending)) apic 1773 arch/x86/kvm/lapic.c if (!start_hv_timer(apic)) apic 1774 arch/x86/kvm/lapic.c start_sw_timer(apic); apic 1781 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 1785 arch/x86/kvm/lapic.c if (!apic->lapic_timer.hv_timer_in_use) apic 1788 arch/x86/kvm/lapic.c cancel_hv_timer(apic); apic 1789 arch/x86/kvm/lapic.c apic_timer_expired(apic); apic 1791 arch/x86/kvm/lapic.c if (apic_lvtt_period(apic) && apic->lapic_timer.period) { apic 1792 arch/x86/kvm/lapic.c advance_periodic_target_expiration(apic); apic 1793 arch/x86/kvm/lapic.c restart_apic_timer(apic); apic 1802 arch/x86/kvm/lapic.c restart_apic_timer(vcpu->arch.apic); apic 1808 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 1812 arch/x86/kvm/lapic.c if (apic->lapic_timer.hv_timer_in_use) apic 1813 arch/x86/kvm/lapic.c start_sw_timer(apic); apic 1820 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 1822 arch/x86/kvm/lapic.c WARN_ON(!apic->lapic_timer.hv_timer_in_use); apic 1823 arch/x86/kvm/lapic.c restart_apic_timer(apic); apic 1826 arch/x86/kvm/lapic.c static void start_apic_timer(struct kvm_lapic *apic) apic 1828 arch/x86/kvm/lapic.c atomic_set(&apic->lapic_timer.pending, 0); apic 1830 arch/x86/kvm/lapic.c if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) apic 1831 arch/x86/kvm/lapic.c && !set_target_expiration(apic)) apic 1834 arch/x86/kvm/lapic.c restart_apic_timer(apic); apic 1837 arch/x86/kvm/lapic.c static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) apic 1841 arch/x86/kvm/lapic.c if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { apic 1842 arch/x86/kvm/lapic.c apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; apic 1844 arch/x86/kvm/lapic.c atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); apic 1846 arch/x86/kvm/lapic.c atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); apic 1850 arch/x86/kvm/lapic.c int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) apic 1858 arch/x86/kvm/lapic.c if (!apic_x2apic_mode(apic)) apic 1859 arch/x86/kvm/lapic.c kvm_apic_set_xapic_id(apic, val >> 24); apic 1865 arch/x86/kvm/lapic.c report_tpr_access(apic, true); apic 1866 arch/x86/kvm/lapic.c apic_set_tpr(apic, val & 0xff); apic 1870 arch/x86/kvm/lapic.c apic_set_eoi(apic); apic 1874 arch/x86/kvm/lapic.c if (!apic_x2apic_mode(apic)) apic 1875 arch/x86/kvm/lapic.c kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); apic 1881 arch/x86/kvm/lapic.c if (!apic_x2apic_mode(apic)) { apic 1882 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); apic 1883 arch/x86/kvm/lapic.c recalculate_apic_map(apic->vcpu->kvm); apic 1890 arch/x86/kvm/lapic.c if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) apic 1892 arch/x86/kvm/lapic.c apic_set_spiv(apic, val & mask); apic 1898 arch/x86/kvm/lapic.c lvt_val = kvm_lapic_get_reg(apic, apic 1900 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, apic 1903 arch/x86/kvm/lapic.c apic_update_lvtt(apic); apic 1904 arch/x86/kvm/lapic.c atomic_set(&apic->lapic_timer.pending, 0); apic 1912 arch/x86/kvm/lapic.c apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2)); apic 1913 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_ICR, val); apic 1917 arch/x86/kvm/lapic.c if (!apic_x2apic_mode(apic)) apic 1919 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_ICR2, val); apic 1923 arch/x86/kvm/lapic.c apic_manage_nmi_watchdog(apic, val); apic 1933 arch/x86/kvm/lapic.c if (!kvm_apic_sw_enabled(apic)) apic 1939 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, reg, val); apic 1944 arch/x86/kvm/lapic.c if (!kvm_apic_sw_enabled(apic)) apic 1946 arch/x86/kvm/lapic.c val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); apic 1947 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_LVTT, val); apic 1948 arch/x86/kvm/lapic.c apic_update_lvtt(apic); apic 1952 arch/x86/kvm/lapic.c if (apic_lvtt_tscdeadline(apic)) apic 1955 arch/x86/kvm/lapic.c hrtimer_cancel(&apic->lapic_timer.timer); apic 1956 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_TMICT, val); apic 1957 arch/x86/kvm/lapic.c start_apic_timer(apic); apic 1961 arch/x86/kvm/lapic.c uint32_t old_divisor = apic->divide_count; apic 1963 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_TDCR, val); apic 1964 arch/x86/kvm/lapic.c update_divide_count(apic); apic 1965 arch/x86/kvm/lapic.c if (apic->divide_count != old_divisor && apic 1966 arch/x86/kvm/lapic.c apic->lapic_timer.period) { apic 1967 arch/x86/kvm/lapic.c hrtimer_cancel(&apic->lapic_timer.timer); apic 1968 arch/x86/kvm/lapic.c update_target_expiration(apic, old_divisor); apic 1969 arch/x86/kvm/lapic.c restart_apic_timer(apic); apic 1974 arch/x86/kvm/lapic.c if (apic_x2apic_mode(apic) && val != 0) apic 1979 arch/x86/kvm/lapic.c if (apic_x2apic_mode(apic)) { apic 1980 arch/x86/kvm/lapic.c kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); apic 1996 arch/x86/kvm/lapic.c struct kvm_lapic *apic = to_lapic(this); apic 1997 arch/x86/kvm/lapic.c unsigned int offset = address - apic->base_address; apic 2000 arch/x86/kvm/lapic.c if (!apic_mmio_in_range(apic, address)) apic 2003 arch/x86/kvm/lapic.c if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { apic 2021 arch/x86/kvm/lapic.c kvm_lapic_reg_write(apic, offset & 0xff0, val); apic 2028 arch/x86/kvm/lapic.c kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); apic 2040 arch/x86/kvm/lapic.c kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); apic 2043 arch/x86/kvm/lapic.c kvm_lapic_reg_write(vcpu->arch.apic, offset, val); apic 2049 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2051 arch/x86/kvm/lapic.c if (!vcpu->arch.apic) apic 2054 arch/x86/kvm/lapic.c hrtimer_cancel(&apic->lapic_timer.timer); apic 2059 arch/x86/kvm/lapic.c if (!apic->sw_enabled) apic 2062 arch/x86/kvm/lapic.c if (apic->regs) apic 2063 arch/x86/kvm/lapic.c free_page((unsigned long)apic->regs); apic 2065 arch/x86/kvm/lapic.c kfree(apic); apic 2075 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2078 arch/x86/kvm/lapic.c !apic_lvtt_tscdeadline(apic)) apic 2081 arch/x86/kvm/lapic.c return apic->lapic_timer.tscdeadline; apic 2086 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2088 arch/x86/kvm/lapic.c if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || apic 2089 arch/x86/kvm/lapic.c apic_lvtt_period(apic)) apic 2092 arch/x86/kvm/lapic.c hrtimer_cancel(&apic->lapic_timer.timer); apic 2093 arch/x86/kvm/lapic.c apic->lapic_timer.tscdeadline = data; apic 2094 arch/x86/kvm/lapic.c start_apic_timer(apic); apic 2099 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2101 arch/x86/kvm/lapic.c apic_set_tpr(apic, ((cr8 & 0x0f) << 4) apic 2102 arch/x86/kvm/lapic.c | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4)); apic 2109 arch/x86/kvm/lapic.c tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); apic 2117 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2119 arch/x86/kvm/lapic.c if (!apic) apic 2127 arch/x86/kvm/lapic.c if (!apic) apic 2133 arch/x86/kvm/lapic.c kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); apic 2142 arch/x86/kvm/lapic.c kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); apic 2147 arch/x86/kvm/lapic.c apic->base_address = apic->vcpu->arch.apic_base & apic 2151 arch/x86/kvm/lapic.c apic->base_address != APIC_DEFAULT_PHYS_BASE) apic 2157 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2160 arch/x86/kvm/lapic.c if (!apic) apic 2164 arch/x86/kvm/lapic.c hrtimer_cancel(&apic->lapic_timer.timer); apic 2169 arch/x86/kvm/lapic.c kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); apic 2171 arch/x86/kvm/lapic.c kvm_apic_set_version(apic->vcpu); apic 2174 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); apic 2175 arch/x86/kvm/lapic.c apic_update_lvtt(apic); apic 2178 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_LVT0, apic 2180 arch/x86/kvm/lapic.c apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); apic 2182 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU); apic 2183 arch/x86/kvm/lapic.c apic_set_spiv(apic, 0xff); apic 2184 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); apic 2185 arch/x86/kvm/lapic.c if (!apic_x2apic_mode(apic)) apic 2186 arch/x86/kvm/lapic.c kvm_apic_set_ldr(apic, 0); apic 2187 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_ESR, 0); apic 2188 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_ICR, 0); apic 2189 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_ICR2, 0); apic 2190 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_TDCR, 0); apic 2191 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_TMICT, 0); apic 2193 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); apic 2194 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); apic 2195 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); apic 2197 arch/x86/kvm/lapic.c apic->irr_pending = vcpu->arch.apicv_active; apic 2198 arch/x86/kvm/lapic.c apic->isr_count = vcpu->arch.apicv_active ? 1 : 0; apic 2199 arch/x86/kvm/lapic.c apic->highest_isr_cache = -1; apic 2200 arch/x86/kvm/lapic.c update_divide_count(apic); apic 2201 arch/x86/kvm/lapic.c atomic_set(&apic->lapic_timer.pending, 0); apic 2206 arch/x86/kvm/lapic.c apic_update_ppr(apic); apic 2223 arch/x86/kvm/lapic.c static bool lapic_is_periodic(struct kvm_lapic *apic) apic 2225 arch/x86/kvm/lapic.c return apic_lvtt_period(apic); apic 2230 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2232 arch/x86/kvm/lapic.c if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) apic 2233 arch/x86/kvm/lapic.c return atomic_read(&apic->lapic_timer.pending); apic 2238 arch/x86/kvm/lapic.c int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) apic 2240 arch/x86/kvm/lapic.c u32 reg = kvm_lapic_get_reg(apic, lvt_type); apic 2243 arch/x86/kvm/lapic.c if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { apic 2247 arch/x86/kvm/lapic.c return __apic_accept_irq(apic, mode, vector, 1, trig_mode, apic 2255 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2257 arch/x86/kvm/lapic.c if (apic) apic 2258 arch/x86/kvm/lapic.c kvm_apic_local_deliver(apic, APIC_LVT0); apic 2269 arch/x86/kvm/lapic.c struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); apic 2271 arch/x86/kvm/lapic.c apic_timer_expired(apic); apic 2273 arch/x86/kvm/lapic.c if (lapic_is_periodic(apic)) { apic 2274 arch/x86/kvm/lapic.c advance_periodic_target_expiration(apic); apic 2283 arch/x86/kvm/lapic.c struct kvm_lapic *apic; apic 2287 arch/x86/kvm/lapic.c apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT); apic 2288 arch/x86/kvm/lapic.c if (!apic) apic 2291 arch/x86/kvm/lapic.c vcpu->arch.apic = apic; apic 2293 arch/x86/kvm/lapic.c apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); apic 2294 arch/x86/kvm/lapic.c if (!apic->regs) { apic 2299 arch/x86/kvm/lapic.c apic->vcpu = vcpu; apic 2301 arch/x86/kvm/lapic.c hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, apic 2303 arch/x86/kvm/lapic.c apic->lapic_timer.timer.function = apic_timer_fn; apic 2305 arch/x86/kvm/lapic.c apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT; apic 2308 arch/x86/kvm/lapic.c apic->lapic_timer.timer_advance_ns = timer_advance_ns; apic 2318 arch/x86/kvm/lapic.c kvm_iodevice_init(&apic->dev, &apic_mmio_ops); apic 2322 arch/x86/kvm/lapic.c kfree(apic); apic 2323 arch/x86/kvm/lapic.c vcpu->arch.apic = NULL; apic 2330 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2333 arch/x86/kvm/lapic.c if (!kvm_apic_hw_enabled(apic)) apic 2336 arch/x86/kvm/lapic.c __apic_update_ppr(apic, &ppr); apic 2337 arch/x86/kvm/lapic.c return apic_has_interrupt_for_ppr(apic, ppr); apic 2342 arch/x86/kvm/lapic.c u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); apic 2345 arch/x86/kvm/lapic.c if (!kvm_apic_hw_enabled(vcpu->arch.apic)) apic 2355 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2357 arch/x86/kvm/lapic.c if (atomic_read(&apic->lapic_timer.pending) > 0) { apic 2358 arch/x86/kvm/lapic.c kvm_apic_inject_pending_timer_irqs(apic); apic 2359 arch/x86/kvm/lapic.c atomic_set(&apic->lapic_timer.pending, 0); apic 2366 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2379 arch/x86/kvm/lapic.c apic_clear_irr(vector, apic); apic 2386 arch/x86/kvm/lapic.c apic_update_ppr(apic); apic 2394 arch/x86/kvm/lapic.c apic_set_isr(vector, apic); apic 2395 arch/x86/kvm/lapic.c __apic_update_ppr(apic, &ppr); apic 2404 arch/x86/kvm/lapic.c if (apic_x2apic_mode(vcpu->arch.apic)) { apic 2428 arch/x86/kvm/lapic.c memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); apic 2434 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2440 arch/x86/kvm/lapic.c apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); apic 2445 arch/x86/kvm/lapic.c memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s)); apic 2450 arch/x86/kvm/lapic.c apic_update_ppr(apic); apic 2451 arch/x86/kvm/lapic.c hrtimer_cancel(&apic->lapic_timer.timer); apic 2452 arch/x86/kvm/lapic.c apic_update_lvtt(apic); apic 2453 arch/x86/kvm/lapic.c apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); apic 2454 arch/x86/kvm/lapic.c update_divide_count(apic); apic 2455 arch/x86/kvm/lapic.c start_apic_timer(apic); apic 2456 arch/x86/kvm/lapic.c apic->irr_pending = true; apic 2457 arch/x86/kvm/lapic.c apic->isr_count = vcpu->arch.apicv_active ? apic 2458 arch/x86/kvm/lapic.c 1 : count_vectors(apic->regs + APIC_ISR); apic 2459 arch/x86/kvm/lapic.c apic->highest_isr_cache = -1; apic 2463 arch/x86/kvm/lapic.c apic_find_highest_irr(apic)); apic 2465 arch/x86/kvm/lapic.c apic_find_highest_isr(apic)); apic 2484 arch/x86/kvm/lapic.c timer = &vcpu->arch.apic->lapic_timer.timer; apic 2497 arch/x86/kvm/lapic.c struct kvm_lapic *apic) apic 2522 arch/x86/kvm/lapic.c vector = apic_set_eoi(apic); apic 2523 arch/x86/kvm/lapic.c trace_kvm_pv_eoi(apic, vector); apic 2531 arch/x86/kvm/lapic.c apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); apic 2536 arch/x86/kvm/lapic.c if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, apic 2540 arch/x86/kvm/lapic.c apic_set_tpr(vcpu->arch.apic, data & 0xff); apic 2550 arch/x86/kvm/lapic.c struct kvm_lapic *apic) apic 2554 arch/x86/kvm/lapic.c apic->irr_pending || apic 2556 arch/x86/kvm/lapic.c apic->highest_isr_cache == -1 || apic 2558 arch/x86/kvm/lapic.c kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { apic 2566 arch/x86/kvm/lapic.c pv_eoi_set_pending(apic->vcpu); apic 2573 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2575 arch/x86/kvm/lapic.c apic_sync_pv_eoi_to_guest(vcpu, apic); apic 2580 arch/x86/kvm/lapic.c tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; apic 2581 arch/x86/kvm/lapic.c max_irr = apic_find_highest_irr(apic); apic 2584 arch/x86/kvm/lapic.c max_isr = apic_find_highest_isr(apic); apic 2589 arch/x86/kvm/lapic.c kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, apic 2597 arch/x86/kvm/lapic.c &vcpu->arch.apic->vapic_cache, apic 2605 arch/x86/kvm/lapic.c vcpu->arch.apic->vapic_addr = vapic_addr; apic 2611 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2614 arch/x86/kvm/lapic.c if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) apic 2622 arch/x86/kvm/lapic.c kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); apic 2623 arch/x86/kvm/lapic.c return kvm_lapic_reg_write(apic, reg, (u32)data); apic 2628 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2631 arch/x86/kvm/lapic.c if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) apic 2637 arch/x86/kvm/lapic.c if (kvm_lapic_reg_read(apic, reg, 4, &low)) apic 2640 arch/x86/kvm/lapic.c kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); apic 2649 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2656 arch/x86/kvm/lapic.c kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); apic 2657 arch/x86/kvm/lapic.c return kvm_lapic_reg_write(apic, reg, (u32)data); apic 2662 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2668 arch/x86/kvm/lapic.c if (kvm_lapic_reg_read(apic, reg, 4, &low)) apic 2671 arch/x86/kvm/lapic.c kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); apic 2701 arch/x86/kvm/lapic.c struct kvm_lapic *apic = vcpu->arch.apic; apic 2705 arch/x86/kvm/lapic.c if (!lapic_in_kernel(vcpu) || !apic->pending_events) apic 2718 arch/x86/kvm/lapic.c if (test_bit(KVM_APIC_SIPI, &apic->pending_events)) apic 2719 arch/x86/kvm/lapic.c clear_bit(KVM_APIC_SIPI, &apic->pending_events); apic 2723 arch/x86/kvm/lapic.c pe = xchg(&apic->pending_events, 0); apic 2726 arch/x86/kvm/lapic.c if (kvm_vcpu_is_bsp(apic->vcpu)) apic 2735 arch/x86/kvm/lapic.c sipi_vector = apic->sipi_vector; apic 81 arch/x86/kvm/lapic.h int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val); apic 82 arch/x86/kvm/lapic.h int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, apic 92 arch/x86/kvm/lapic.h int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); apic 142 arch/x86/kvm/lapic.h static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) apic 144 arch/x86/kvm/lapic.h kvm_lapic_set_vector(vec, apic->regs + APIC_IRR); apic 149 arch/x86/kvm/lapic.h apic->irr_pending = true; apic 152 arch/x86/kvm/lapic.h static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) apic 154 arch/x86/kvm/lapic.h return *((u32 *) (apic->regs + reg_off)); apic 157 arch/x86/kvm/lapic.h static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) apic 159 arch/x86/kvm/lapic.h *((u32 *) (apic->regs + reg_off)) = val; apic 167 arch/x86/kvm/lapic.h return vcpu->arch.apic; apic 173 arch/x86/kvm/lapic.h static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) apic 176 arch/x86/kvm/lapic.h return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; apic 182 arch/x86/kvm/lapic.h static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) apic 185 arch/x86/kvm/lapic.h return apic->sw_enabled; apic 191 arch/x86/kvm/lapic.h return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); apic 196 arch/x86/kvm/lapic.h return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); apic 199 arch/x86/kvm/lapic.h static inline int apic_x2apic_mode(struct kvm_lapic *apic) apic 201 arch/x86/kvm/lapic.h return apic->vcpu->arch.apic_base & X2APIC_ENABLE; apic 206 arch/x86/kvm/lapic.h return vcpu->arch.apic && vcpu->arch.apicv_active; apic 211 arch/x86/kvm/lapic.h return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events; apic 222 arch/x86/kvm/lapic.h return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); apic 245 arch/x86/kvm/lapic.h static inline u8 kvm_xapic_id(struct kvm_lapic *apic) apic 247 arch/x86/kvm/lapic.h return kvm_lapic_get_reg(apic, APIC_ID) >> 24; apic 337 arch/x86/kvm/pmu.c kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC); apic 1754 arch/x86/kvm/svm.c if (!svm->vcpu.arch.apic->regs) apic 1757 arch/x86/kvm/svm.c svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs); apic 4527 arch/x86/kvm/svm.c struct kvm_lapic *apic = svm->vcpu.arch.apic; apic 4544 arch/x86/kvm/svm.c kvm_lapic_reg_write(apic, APIC_ICR2, icrh); apic 4545 arch/x86/kvm/svm.c kvm_lapic_reg_write(apic, APIC_ICR, icrl); apic 4551 arch/x86/kvm/svm.c struct kvm_lapic *apic = svm->vcpu.arch.apic; apic 4559 arch/x86/kvm/svm.c bool m = kvm_apic_match_dest(vcpu, apic, apic 4599 arch/x86/kvm/svm.c int apic = ffs(dlid & 0x0f) - 1; apic 4601 arch/x86/kvm/svm.c if ((apic < 0) || (apic > 7) || apic 4604 arch/x86/kvm/svm.c index = (cluster << 2) + apic; apic 4617 arch/x86/kvm/svm.c flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT; apic 4645 arch/x86/kvm/svm.c u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR); apic 4646 arch/x86/kvm/svm.c u32 id = kvm_xapic_id(vcpu->arch.apic); apic 4666 arch/x86/kvm/svm.c u32 id = kvm_xapic_id(vcpu->arch.apic); apic 4694 arch/x86/kvm/svm.c u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR); apic 4705 arch/x86/kvm/svm.c struct kvm_lapic *apic = svm->vcpu.arch.apic; apic 4725 arch/x86/kvm/svm.c kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); apic 5195 arch/x86/kvm/svm.c kvm_lapic_set_irr(vec, vcpu->arch.apic); apic 5691 arch/x86/kvm/svm.c vcpu->arch.apic->lapic_timer.timer_advance_ns) apic 468 arch/x86/kvm/trace.h TP_PROTO(struct kvm_lapic *apic, int vector), apic 469 arch/x86/kvm/trace.h TP_ARGS(apic, vector), apic 477 arch/x86/kvm/trace.h __entry->apicid = apic->vcpu->vcpu_id; apic 485 arch/x86/kvm/trace.h TP_PROTO(struct kvm_lapic *apic, int vector), apic 486 arch/x86/kvm/trace.h TP_ARGS(apic, vector), apic 494 arch/x86/kvm/trace.h __entry->apicid = apic->vcpu->vcpu_id; apic 3035 arch/x86/kvm/vmx/nested.c u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI); apic 3469 arch/x86/kvm/vmx/nested.c struct kvm_lapic *apic = vcpu->arch.apic; apic 3472 arch/x86/kvm/vmx/nested.c test_bit(KVM_APIC_INIT, &apic->pending_events)) { apic 3792 arch/x86/kvm/vmx/vmx.c apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); apic 4331 arch/x86/kvm/vmx/vmx.c __pa(vcpu->arch.apic->regs)); apic 6542 arch/x86/kvm/vmx/vmx.c vcpu->arch.apic->lapic_timer.timer_advance_ns) apic 7206 arch/x86/kvm/vmx/vmx.c struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; apic 3882 arch/x86/kvm/x86.c vcpu->arch.apic->sipi_vector = events->sipi_vector; apic 3902 arch/x86/kvm/x86.c set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); apic 3904 arch/x86/kvm/x86.c clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); apic 5296 arch/x86/kvm/x86.c !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) apic 5316 arch/x86/kvm/x86.c !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, apic 7559 arch/x86/kvm/x86.c if (!vcpu->arch.apic->vapic_addr) apic 7973 arch/x86/kvm/x86.c if (!kvm_apic_hw_enabled(vcpu->arch.apic)) apic 8302 arch/x86/kvm/x86.c s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; apic 8305 arch/x86/kvm/x86.c vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; apic 8806 arch/x86/kvm/x86.c set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); apic 43 arch/x86/mm/srat.c if (!apic->apic_id_valid(apic_id)) { apic 38 arch/x86/platform/uv/uv_irq.c entry->delivery_mode = apic->irq_delivery_mode; apic 39 arch/x86/platform/uv/uv_irq.c entry->dest_mode = apic->irq_dest_mode; apic 558 arch/x86/platform/uv/uv_nmi.c apic->send_IPI_mask(uv_nmi_cpu_mask, APIC_DM_NMI); apic 14 arch/x86/xen/apic.c static unsigned int xen_io_apic_read(unsigned apic, unsigned reg) apic 19 arch/x86/xen/apic.c apic_op.apic_physbase = mpc_ioapic_addr(apic); apic 29 arch/x86/xen/apic.c return apic << 24; apic 154 arch/x86/xen/apic.c static struct apic xen_pv_apic = { apic 209 arch/x86/xen/apic.c if (apic == &xen_pv_apic) apic 212 arch/x86/xen/apic.c pr_info("Switched APIC routing from %s to %s.\n", apic->name, apic 214 arch/x86/xen/apic.c apic = &xen_pv_apic; apic 222 arch/x86/xen/apic.c apic = &xen_pv_apic; apic 54 drivers/acpi/processor_core.c struct acpi_madt_local_x2apic *apic = apic 57 drivers/acpi/processor_core.c if (!(apic->lapic_flags & ACPI_MADT_ENABLED)) apic 60 drivers/acpi/processor_core.c if (device_declaration && (apic->uid == acpi_id)) { apic 61 drivers/acpi/processor_core.c *apic_id = apic->local_apic_id; apic 4179 drivers/iommu/amd_iommu.c iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode, apic 4180 drivers/iommu/amd_iommu.c apic->irq_dest_mode, irq_cfg->vector, apic 4442 drivers/iommu/amd_iommu.c entry->lo.fields_remap.dm = apic->irq_dest_mode; apic 4443 drivers/iommu/amd_iommu.c entry->lo.fields_remap.int_type = apic->irq_delivery_mode; apic 216 drivers/iommu/intel_irq_remapping.c static struct intel_iommu *map_ioapic_to_ir(int apic) apic 221 drivers/iommu/intel_irq_remapping.c if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu) apic 309 drivers/iommu/intel_irq_remapping.c static int set_ioapic_sid(struct irte *irte, int apic) apic 319 drivers/iommu/intel_irq_remapping.c if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) { apic 327 drivers/iommu/intel_irq_remapping.c pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic); apic 1080 drivers/iommu/intel_irq_remapping.c irte->dst_mode = apic->irq_dest_mode; apic 1089 drivers/iommu/intel_irq_remapping.c irte->dlvry_mode = apic->irq_delivery_mode;