BXT_PORT_CL1CM_DW0  320 drivers/gpu/drm/i915/display/intel_dpio_phy.c 	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
BXT_PORT_CL1CM_DW0  389 drivers/gpu/drm/i915/display/intel_dpio_phy.c 				       BXT_PORT_CL1CM_DW0(phy),
BXT_PORT_CL1CM_DW0 1609 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
BXT_PORT_CL1CM_DW0 1611 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
BXT_PORT_CL1CM_DW0 1616 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
BXT_PORT_CL1CM_DW0 1618 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
BXT_PORT_CL1CM_DW0 3158 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
BXT_PORT_CL1CM_DW0 3168 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
BXT_PORT_CL1CM_DW0  251 drivers/gpu/drm/i915/gvt/mmio.c 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
BXT_PORT_CL1CM_DW0  253 drivers/gpu/drm/i915/gvt/mmio.c 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=