and 179 arch/alpha/include/asm/atomic.h ATOMIC_OPS(and, and) and 195 arch/arc/include/asm/atomic.h ATOMIC_OPS(and, &=, and) and 296 arch/arc/include/asm/atomic.h ATOMIC_OPS(and, &=, CTOP_INST_AAND_DI_R2_R2_R3) and 434 arch/arc/include/asm/atomic.h ATOMIC64_OPS(and, and, and) and 54 arch/arc/include/asm/entry-arcv2.h ; 3. Auto save: (mandatory) Push PC and STAT32 on stack and 153 arch/arc/include/asm/entry-arcv2.h ; ISA requires ADD.nz to have same dest and src reg operands and 138 arch/arc/include/asm/entry.h ; Retrieve orig r25 and save it with rest of callee_regs and 22 arch/arc/include/asm/tlb-mmu1.h ; and its unpleasant LFSR pseudo-random sequence and 34 arch/arc/include/asm/tlb-mmu1.h and r0,r0,1 ; clean and 39 arch/arc/include/asm/tlb-mmu1.h and r0,r0,0xff ; clean and 52 arch/arc/include/asm/tlb-mmu1.h and.f r0,r0,0x000fe000 /* 2-way MMU mask */ and 56 arch/arc/include/asm/tlb-mmu1.h and r0,r0,PAGE_MASK /* VPN of instruction address */ and 58 arch/arc/include/asm/tlb-mmu1.h and r1,r1,0xff /* Data ASID */ and 81 arch/arc/include/asm/tlb-mmu1.h and r0,r0,PAGE_MASK /* VPN of instruction address */ and 235 arch/arm/include/asm/atomic.h ATOMIC_OPS(and, &=, and) and 391 arch/arm/include/asm/atomic.h ATOMIC64_OPS(and, and, and) and 16 arch/arm/include/asm/tls.h mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register and 35 arch/arm/include/asm/vfpmacros.h VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 and 36 arch/arm/include/asm/vfpmacros.h and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field and 59 arch/arm/include/asm/vfpmacros.h VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 and 60 arch/arm/include/asm/vfpmacros.h and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field and 12 arch/arm/lib/bitops.h and r3, r0, #31 @ Get bit offset and 37 arch/arm/lib/bitops.h and r3, r0, #31 @ Get bit offset and 66 arch/arm/lib/bitops.h and r2, r0, #31 and 93 arch/arm/lib/bitops.h and r3, r0, #31 and 71 arch/arm/mach-tegra/sleep.h and \rd, \rd, #0xF and 112 arch/arm/mach-tegra/sleep.h and \tmp1, \tmp1, #0xff00 and 66 arch/arm64/include/asm/asm-uaccess.h and \dst, \dst, \addr and 45 arch/arm64/include/asm/assembler.h and \tmp, \pstate, #(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) and 319 arch/arm64/include/asm/assembler.h and \tmp, \tmp, #0xf // cache line size encoding and 329 arch/arm64/include/asm/assembler.h and \tmp, \tmp, #0xf // cache line size encoding and 540 arch/arm64/include/asm/assembler.h and \tmp, \tmp, #(0xf << ID_AA64MMFR2_LVA_SHIFT) and 568 arch/arm64/include/asm/assembler.h and \ttbr, \ttbr, #TTBR_BADDR_MASK_52 and 581 arch/arm64/include/asm/assembler.h and \pte, \pte, #PTE_ADDR_MASK and 593 arch/arm64/include/asm/assembler.h and \phys, \pte, #PTE_ADDR_MASK and 605 arch/arm64/include/asm/assembler.h and \tmp1, \tmp1, \tmp2 and 122 arch/arm64/include/asm/atomic_ll_sc.h ATOMIC_OPS(and, and, K) and 221 arch/arm64/include/asm/atomic_ll_sc.h ATOMIC64_OPS(and, and, L) and 311 arch/arm64/include/asm/insn.h __AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000) and 76 arch/arm64/include/asm/kvm_mmu.h and \reg, \reg, #1 /* mask with va_mask */ and 78 arch/arm64/include/asm/kvm_ptrauth.h and \reg1, \reg1, #(HCR_API | HCR_APK) and 94 arch/arm64/include/asm/kvm_ptrauth.h and \reg1, \reg1, #(HCR_API | HCR_APK) and 193 arch/csky/include/asm/atomic.h ATOMIC_FETCH_OP(and, &) and 200 arch/csky/include/asm/atomic.h ATOMIC_OP(and, &) and 62 arch/h8300/include/asm/atomic.h ATOMIC_OPS(and, &=) and 143 arch/hexagon/include/asm/atomic.h ATOMIC_OPS(and) and 110 arch/ia64/include/asm/atomic.h ATOMIC_FETCH_OP(and, &) and 195 arch/ia64/include/asm/atomic.h ATOMIC64_FETCH_OP(and, &) and 14 arch/m68k/fpsp040/fpsp.h | frame and any local variables needed by the FPSP package. and 45 arch/m68k/fpsp040/fpsp.h | offsets refer to the Local Variable area and the fsave area. and 56 arch/m68k/fpsp040/fpsp.h | and then either "bra fpsp_done" if the exception was completely and 66 arch/m68k/fpsp040/fpsp.h | a second fsave frame can be pushed onto the stack and the and 67 arch/m68k/fpsp040/fpsp.h | handler exit code will reload the new frame and discard the old. and 69 arch/m68k/fpsp040/fpsp.h | The registers d0, d1, a0, a1 and fp0-fp3 are always saved and and 70 arch/m68k/fpsp040/fpsp.h | restored from the "local variable" area and can be used as and 72 arch/m68k/fpsp040/fpsp.h | of these registers, it should modify the saved copy and let and 122 arch/m68k/fpsp040/fpsp.h | fsave offsets and bit definitions and 131 arch/m68k/fpsp040/fpsp.h .set WBTEMP_EX,WBTEMP | wbtemp sign and exponent (2 bytes) and 189 arch/m68k/fpsp040/fpsp.h .set E_BYTE,LV-28 | holds E1 and E3 bits (1 byte) and 194 arch/m68k/fpsp040/fpsp.h .set T_BYTE,LV-27 | holds T and U bits (1 byte) and 200 arch/m68k/fpsp040/fpsp.h .set FPTEMP_EX,FPTEMP | fptemp sign and exponent (2 bytes) and 207 arch/m68k/fpsp040/fpsp.h .set ETEMP_EX,ETEMP | etemp sign and exponent (2 bytes) and 270 arch/m68k/fpsp040/fpsp.h .set nzi_mask,0x01ffffff | clears N, Z, and I and 307 arch/m68k/fpsp040/fpsp.h .set sx_mask,0x01800000 | set s and x bits in word $48 and 322 arch/m68k/fpsp040/fpsp.h | fsave sizes and formats and 1621 arch/m68k/ifpsp060/src/fpsp.S # if a disabled overflow occurred and inexact was enabled but the result and 4143 arch/m68k/ifpsp060/src/fpsp.S # if the instruction was executed from supervisor mode and the addressing and 16332 arch/m68k/ifpsp060/src/fpsp.S # if the NAN bit is set, in which case BSUN and AIOP will be set. # and 16960 arch/m68k/ifpsp060/src/fpsp.S # if the NAN bit is set, in which case BSUN and AIOP will be set. # and 17530 arch/m68k/ifpsp060/src/fpsp.S # if the NAN bit is set, in which case BSUN and AIOP will be set. # and 23193 arch/m68k/ifpsp060/src/fpsp.S # if the exp was positive, and added if it was negative. The purpose and 1620 arch/m68k/ifpsp060/src/pfpsp.S # if a disabled overflow occurred and inexact was enabled but the result and 13153 arch/m68k/ifpsp060/src/pfpsp.S # if the exp was positive, and added if it was negative. The purpose and 116 arch/m68k/include/asm/atomic.h ATOMIC_OPS(and, &=, and) and 159 arch/m68k/math-emu/fp_decode.h and.w #3,%d1 and 188 arch/m68k/math-emu/fp_decode.h | get the extension word and test for brief or full extension type and 306 arch/m68k/math-emu/fp_decode.h | perform preindex (if I/IS == 0xx and xx != 00) and 309 arch/m68k/math-emu/fp_decode.h and.w %d2,%d0 and 346 arch/m68k/math-emu/fp_decode.h | with index and 8bit displacement and 356 arch/m68k/math-emu/fp_decode.h | with base and/or outer displacement and 166 arch/mips/include/asm/atomic.h ATOMIC_OPS(and, &=, and) and 368 arch/mips/include/asm/atomic.h ATOMIC64_OPS(and, &=, and) and 19 arch/mips/include/asm/mach-ath79/kernel-entry-init.h and t0, t1 and 21 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h # addresses, and need to have the appropriate memory region set and 40 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h # First clear off CvmCtl[IPPCI] bit and move the performance and 43 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h and v0, v0, v1 and 47 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h and t1, v1, 0xfff8 and 50 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h and t1, v1, 0xfff8 and 53 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h and t1, v1, 0xfff8 and 56 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h and t1, v1, 0xff00 and 59 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h and t1, v1, 0x00ff and 60 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h slti t1, t1, 2 # 66-P1.2 and later good. and 83 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h and t1, v0, 0xff00 and 22 arch/mips/include/asm/mach-ip27/kernel-entry-init.h and \res, NSRI_NODEID_MASK and 79 arch/mips/include/asm/mach-ip27/kernel-entry-init.h move t2, t1 # text and data are here and 363 arch/mips/include/asm/stackframe.h and a0, v1 and 366 arch/mips/include/asm/stackframe.h and v0, v1 and 401 arch/mips/include/asm/stackframe.h and a0, v1 and 404 arch/mips/include/asm/stackframe.h and v0, v1 and 536 arch/mips/net/ebpf_jit.c emit_instr(ctx, and, dst, dst, MIPS_R_AT); and 866 arch/mips/net/ebpf_jit.c emit_instr(ctx, and, dst, dst, src); and 958 arch/mips/net/ebpf_jit.c emit_instr(ctx, and, dst, dst, src); and 1039 arch/mips/net/ebpf_jit.c emit_instr(ctx, and, MIPS_R_AT, dst, src); and 1276 arch/mips/net/ebpf_jit.c emit_instr(ctx, and, MIPS_R_AT, dst, MIPS_R_AT); and 24 arch/nios2/include/asm/asm-macros.h and \reg1, \reg1, \reg2 and 74 arch/openrisc/include/asm/atomic.h ATOMIC_FETCH_OP(and) and 78 arch/openrisc/include/asm/atomic.h ATOMIC_OP(and) and 130 arch/parisc/include/asm/atomic.h ATOMIC_OPS(and, &=) and 195 arch/parisc/include/asm/atomic.h ATOMIC64_OPS(and, &=) and 113 arch/powerpc/include/asm/atomic.h ATOMIC_OPS(and, and) and 384 arch/powerpc/include/asm/atomic.h ATOMIC64_OPS(and, and) and 78 arch/riscv/include/asm/atomic.h ATOMIC_OPS(and, and, i) and 176 arch/riscv/include/asm/atomic.h ATOMIC_OPS(and, and, i) and 86 arch/riscv/include/asm/bitops.h return __test_and_op_bit(and, __NOT, nr, addr); and 130 arch/riscv/include/asm/bitops.h __op_bit(and, __NOT, nr, addr); and 171 arch/riscv/include/asm/bitops.h __op_bit_ord(and, __NOT, nr, addr, .rl); and 72 arch/s390/include/asm/atomic.h ATOMIC_OPS(and) and 142 arch/s390/include/asm/atomic.h ATOMIC64_OPS(and) and 77 arch/sh/include/asm/atomic-grb.h ATOMIC_OPS(and) and 63 arch/sh/include/asm/atomic-irq.h ATOMIC_OPS(and, &=) and 79 arch/sh/include/asm/atomic-llsc.h ATOMIC_OPS(and) and 44 arch/sparc/include/asm/atomic_64.h ATOMIC_OPS(and) and 122 arch/sparc/include/asm/trap_block.h and REG, 0x1f, REG; \ and 130 arch/sparc/include/asm/trap_block.h and REG, 0x3ff, REG; \ and 135 arch/sparc/include/asm/trap_block.h and REG, 0x1f, REG; \ and 188 arch/sparc/include/asm/tsb.h and VADDR, REG2, REG2; \ and 224 arch/sparc/include/asm/tsb.h and VADDR, REG2, REG2; \ and 252 arch/sparc/include/asm/tsb.h and VADDR, REG2, REG2; \ and 349 arch/sparc/include/asm/tsb.h and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \ and 371 arch/sparc/include/asm/tsb.h and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \ and 392 arch/sparc/include/asm/ttable.h and %sp, 1, %g3; \ and 427 arch/sparc/include/asm/ttable.h and %sp, 1, %g3; \ and 616 arch/sparc/include/asm/ttable.h and %sp, 1, %g3; \ and 649 arch/sparc/include/asm/ttable.h and %sp, 1, %g3; \ and 110 arch/sparc/include/asm/winmacro.h and %idreg, 0xc, %idreg; \ and 63 arch/sparc/lib/atomic32.c ATOMIC_FETCH_OP(and, &=) and 994 arch/x86/kvm/emulate.c FASTOP2(and); and 249 arch/xtensa/include/asm/atomic.h ATOMIC_OPS(and) and 223 arch/xtensa/include/asm/initialize_mmu.h and a3, a3, a6 and 228 arch/xtensa/include/asm/initialize_mmu.h and a3, a3, a6 and 141 crypto/poly1305_generic.c d1 += sr(d0, 26); h0 = and(d0, 0x3ffffff); and 142 crypto/poly1305_generic.c d2 += sr(d1, 26); h1 = and(d1, 0x3ffffff); and 143 crypto/poly1305_generic.c d3 += sr(d2, 26); h2 = and(d2, 0x3ffffff); and 144 crypto/poly1305_generic.c d4 += sr(d3, 26); h3 = and(d3, 0x3ffffff); and 145 crypto/poly1305_generic.c h0 += sr(d4, 26) * 5; h4 = and(d4, 0x3ffffff); and 312 drivers/dma/ti/edma.c static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, and 317 drivers/dma/ti/edma.c val &= and; and 322 drivers/dma/ti/edma.c static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) and 326 drivers/dma/ti/edma.c val &= and; and 351 drivers/dma/ti/edma.c unsigned and, unsigned or) and 353 drivers/dma/ti/edma.c edma_modify(ecc, offset + (i << 2), and, or); and 410 drivers/dma/ti/edma.c int param_no, unsigned and, unsigned or) and 412 drivers/dma/ti/edma.c edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); and 416 drivers/dma/ti/edma.c unsigned and) and 418 drivers/dma/ti/edma.c edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and); and 1096 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) and 2549 drivers/gpu/drm/radeon/radeon.h #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) and 1046 drivers/misc/habanalabs/habanalabs.h #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) and 147 drivers/mtd/nftlmount.c The new DiskOnChip driver scans the MediaHeader itself, and presents a virtual and 4443 drivers/net/wireless/atmel/atmel.c and r0, r0, #255 and 4457 drivers/net/wireless/atmel/atmel.c and r0, r0, #8 and 130 include/asm-generic/atomic.h ATOMIC_FETCH_OP(and, &) and 142 include/asm-generic/atomic.h ATOMIC_OP(and, &) and 40 include/asm-generic/atomic64.h ATOMIC64_OPS(and) and 77 include/linux/cb710.h int reg, uint32_t and, uint32_t xor); and 21 include/sound/wavefront.h All other wavefront_* types end up aligned to 32 bit values and and 124 lib/atomic64.c ATOMIC64_OPS(and, &=) and 119 lib/atomic64_test.c TEST(, and, &=, v1); and 171 lib/atomic64_test.c TEST(64, and, &=, v1); and 88 net/can/gw.c struct canfd_frame and; and 94 net/can/gw.c u8 and; and 157 net/can/gw.c MODFUNC(mod_and_id, cf->can_id &= mod->modframe.and.can_id) and 158 net/can/gw.c MODFUNC(mod_and_len, cf->len &= mod->modframe.and.len) and 159 net/can/gw.c MODFUNC(mod_and_flags, cf->flags &= mod->modframe.and.flags) and 160 net/can/gw.c MODFUNC(mod_and_data, *(u64 *)cf->data &= *(u64 *)mod->modframe.and.data) and 179 net/can/gw.c *(u64 *)(cf->data + i) &= *(u64 *)(mod->modframe.and.data + i); and 588 net/can/gw.c if (gwj->mod.modtype.and) { and 589 net/can/gw.c memcpy(&mb.cf, &gwj->mod.modframe.and, sizeof(mb.cf)); and 590 net/can/gw.c mb.modtype = gwj->mod.modtype.and; and 618 net/can/gw.c if (gwj->mod.modtype.and) { and 619 net/can/gw.c memcpy(&mb.cf, &gwj->mod.modframe.and, sizeof(mb.cf)); and 620 net/can/gw.c mb.modtype = gwj->mod.modtype.and; and 762 net/can/gw.c canfdframecpy(&mod->modframe.and, &mb.cf); and 763 net/can/gw.c mod->modtype.and = mb.modtype; and 840 net/can/gw.c canframecpy(&mod->modframe.and, &mb.cf); and 841 net/can/gw.c mod->modtype.and = mb.modtype; and 43 sound/usb/usx2y/usbusx2yaudio.c this #define out, and thereby produce smaller, faster code. and 108 tools/bpf/bpf_exp.y | and and 397 tools/bpf/bpf_exp.y and