_mask 502 arch/mips/include/asm/kvm_host.h unsigned long _mask = mask; \ _mask 503 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] &= ~_mask; \ _mask 504 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] |= val & _mask; \ _mask 12 arch/mips/include/asm/mach-ralink/pinmux.h #define GRP(_name, _func, _mask, _shift) \ _mask 13 arch/mips/include/asm/mach-ralink/pinmux.h { .name = _name, .mask = _mask, .shift = _shift, \ _mask 14 arch/mips/include/asm/mach-ralink/pinmux.h .func = _func, .gpio = _mask, \ _mask 17 arch/mips/include/asm/mach-ralink/pinmux.h #define GRP_G(_name, _func, _mask, _gpio, _shift) \ _mask 18 arch/mips/include/asm/mach-ralink/pinmux.h { .name = _name, .mask = _mask, .shift = _shift, \ _mask 77 arch/sh/kernel/cpu/sh2a/clock-sh7264.c #define DIV4(_reg, _bit, _mask, _flags) \ _mask 78 arch/sh/kernel/cpu/sh2a/clock-sh7264.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _mask 105 arch/sh/kernel/cpu/sh2a/clock-sh7269.c #define DIV4(_reg, _bit, _mask, _flags) \ _mask 106 arch/sh/kernel/cpu/sh2a/clock-sh7269.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _mask 105 arch/sh/kernel/cpu/sh4a/clock-sh7343.c #define DIV4(_reg, _bit, _mask, _flags) \ _mask 106 arch/sh/kernel/cpu/sh4a/clock-sh7343.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _mask 108 arch/sh/kernel/cpu/sh4a/clock-sh7366.c #define DIV4(_reg, _bit, _mask, _flags) \ _mask 109 arch/sh/kernel/cpu/sh4a/clock-sh7366.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _mask 108 arch/sh/kernel/cpu/sh4a/clock-sh7722.c #define DIV4(_reg, _bit, _mask, _flags) \ _mask 109 arch/sh/kernel/cpu/sh4a/clock-sh7722.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _mask 111 arch/sh/kernel/cpu/sh4a/clock-sh7723.c #define DIV4(_reg, _bit, _mask, _flags) \ _mask 112 arch/sh/kernel/cpu/sh4a/clock-sh7723.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _mask 150 arch/sh/kernel/cpu/sh4a/clock-sh7724.c #define DIV4(_reg, _bit, _mask, _flags) \ _mask 151 arch/sh/kernel/cpu/sh4a/clock-sh7724.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _mask 69 arch/sh/kernel/cpu/sh4a/clock-sh7734.c #define DIV4(_reg, _bit, _mask, _flags) \ _mask 70 arch/sh/kernel/cpu/sh4a/clock-sh7734.c SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) _mask 62 arch/sh/kernel/cpu/sh4a/clock-sh7757.c #define DIV4(_bit, _mask, _flags) \ _mask 63 arch/sh/kernel/cpu/sh4a/clock-sh7757.c SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags) _mask 66 arch/sh/kernel/cpu/sh4a/clock-sh7785.c #define DIV4(_bit, _mask, _flags) \ _mask 67 arch/sh/kernel/cpu/sh4a/clock-sh7785.c SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) _mask 67 arch/sh/kernel/cpu/sh4a/clock-sh7786.c #define DIV4(_bit, _mask, _flags) \ _mask 68 arch/sh/kernel/cpu/sh4a/clock-sh7786.c SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) _mask 61 arch/sh/kernel/cpu/sh4a/clock-shx3.c #define DIV4(_bit, _mask, _flags) \ _mask 62 arch/sh/kernel/cpu/sh4a/clock-shx3.c SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) _mask 185 drivers/bcma/sprom.c #define SPEX(_field, _offset, _mask, _shift) \ _mask 186 drivers/bcma/sprom.c bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift)) _mask 188 drivers/bcma/sprom.c #define SPEX32(_field, _offset, _mask, _shift) \ _mask 190 drivers/bcma/sprom.c sprom[SPOFF(_offset)]) & (_mask)) >> (_shift)) _mask 192 drivers/bcma/sprom.c #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ _mask 194 drivers/bcma/sprom.c SPEX(_field[0], _offset + 0, _mask, _shift); \ _mask 195 drivers/bcma/sprom.c SPEX(_field[1], _offset + 2, _mask, _shift); \ _mask 196 drivers/bcma/sprom.c SPEX(_field[2], _offset + 4, _mask, _shift); \ _mask 197 drivers/bcma/sprom.c SPEX(_field[3], _offset + 6, _mask, _shift); \ _mask 198 drivers/bcma/sprom.c SPEX(_field[4], _offset + 8, _mask, _shift); \ _mask 199 drivers/bcma/sprom.c SPEX(_field[5], _offset + 10, _mask, _shift); \ _mask 200 drivers/bcma/sprom.c SPEX(_field[6], _offset + 12, _mask, _shift); \ _mask 201 drivers/bcma/sprom.c SPEX(_field[7], _offset + 14, _mask, _shift); \ _mask 91 drivers/clk/at91/pmc.h #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) _mask 92 drivers/clk/at91/pmc.h #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) _mask 42 drivers/clk/meson/axg-audio.c #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) \ _mask 46 drivers/clk/meson/axg-audio.c .mask = (_mask), \ _mask 1109 drivers/clk/nxp/clk-lpc32xx.c #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \ _mask 1120 drivers/clk/nxp/clk-lpc32xx.c .mask = (_mask), \ _mask 38 drivers/clk/st/clkgen.h #define CLKGEN_FIELD(_offset, _mask, _shift) { \ _mask 40 drivers/clk/st/clkgen.h .mask = _mask, \ _mask 69 drivers/clk/uniphier/clk-uniphier.h #define UNIPHIER_CLK_CPUGEAR(_name, _idx, _regbase, _mask, \ _mask 79 drivers/clk/uniphier/clk-uniphier.h .mask = (_mask) \ _mask 21 drivers/crypto/ccp/ccp-dmaengine.c #define CCP_DMA_WIDTH(_mask) \ _mask 23 drivers/crypto/ccp/ccp-dmaengine.c u64 mask = _mask + 1; \ _mask 36 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\ _mask 61 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\ _mask 78 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\ _mask 33 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h .type ## _mask = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## _MASK,\ _mask 41 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h .type ## _mask = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\ _mask 35 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask _mask 230 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 _mask, u32 _data, u32 _copy) _mask 236 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 mask = _mask | _copy; _mask 237 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 data = (_data & _mask) | (reg->data & _copy); _mask 189 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t _offset, uint32_t _mask, uint32_t v, _mask 200 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mask = reg->mask & _mask; _mask 20 drivers/gpu/drm/rockchip/rockchip_vop_reg.c #define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \ _mask 23 drivers/gpu/drm/rockchip/rockchip_vop_reg.c .mask = _mask, \ _mask 29 drivers/gpu/drm/rockchip/rockchip_vop_reg.c #define VOP_REG(off, _mask, _shift) \ _mask 30 drivers/gpu/drm/rockchip/rockchip_vop_reg.c _VOP_REG(off, _mask, _shift, false, true) _mask 32 drivers/gpu/drm/rockchip/rockchip_vop_reg.c #define VOP_REG_SYNC(off, _mask, _shift) \ _mask 33 drivers/gpu/drm/rockchip/rockchip_vop_reg.c _VOP_REG(off, _mask, _shift, false, false) _mask 35 drivers/gpu/drm/rockchip/rockchip_vop_reg.c #define VOP_REG_MASK_SYNC(off, _mask, _shift) \ _mask 36 drivers/gpu/drm/rockchip/rockchip_vop_reg.c _VOP_REG(off, _mask, _shift, true, false) _mask 225 drivers/hwtracing/intel_th/gth.c #define OUTPUT_PARM(_name, _mask, _r, _w, _what) \ _mask 229 drivers/hwtracing/intel_th/gth.c .mask = (_mask), \ _mask 924 drivers/iio/accel/mma9553.c #define MMA9553_PEDOMETER_CHANNEL(_type, _mask) { \ _mask 928 drivers/iio/accel/mma9553.c _mask, \ _mask 190 drivers/iio/adc/max1363.c #define MAX1363_MODE_SINGLE(_num, _mask) { \ _mask 194 drivers/iio/adc/max1363.c .modemask[0] = _mask, \ _mask 197 drivers/iio/adc/max1363.c #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \ _mask 201 drivers/iio/adc/max1363.c .modemask[0] = _mask, \ _mask 205 drivers/iio/adc/max1363.c #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \ _mask 209 drivers/iio/adc/max1363.c .modemask[0] = _mask \ _mask 212 drivers/iio/adc/max1363.c #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \ _mask 216 drivers/iio/adc/max1363.c .modemask[0] = _mask \ _mask 220 drivers/iio/adc/max1363.c #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \ _mask 224 drivers/iio/adc/max1363.c .modemask[0] = _mask \ _mask 228 drivers/iio/adc/max1363.c #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \ _mask 232 drivers/iio/adc/max1363.c .modemask[0] = _mask \ _mask 427 drivers/iio/adc/qcom-spmi-adc5.c #define ADC5_CHAN(_dname, _type, _mask, _pre, _scale) \ _mask 432 drivers/iio/adc/qcom-spmi-adc5.c .info_mask = _mask, \ _mask 511 drivers/iio/adc/qcom-spmi-vadc.c #define VADC_CHAN(_dname, _type, _mask, _pre, _scale) \ _mask 516 drivers/iio/adc/qcom-spmi-vadc.c .info_mask = _mask, \ _mask 520 drivers/iio/adc/qcom-spmi-vadc.c #define VADC_NO_CHAN(_dname, _type, _mask, _pre) \ _mask 525 drivers/iio/adc/qcom-spmi-vadc.c .info_mask = _mask \ _mask 83 drivers/iio/health/afe440x.h #define AFE440X_INTENSITY_CHAN(_index, _mask) \ _mask 96 drivers/iio/health/afe440x.h _mask, \ _mask 170 drivers/input/mouse/trackpoint.c #define TRACKPOINT_BIT_ATTR(_name, _command, _mask, _inv, _default) \ _mask 175 drivers/input/mouse/trackpoint.c .mask = _mask, \ _mask 119 drivers/irqchip/irq-pic32-evic.c #define IRQ_REG_MASK(_hwirq, _reg, _mask) \ _mask 122 drivers/irqchip/irq-pic32-evic.c _mask = 1 << (_hwirq % 32); \ _mask 1047 drivers/media/rc/rc-main.c #define RC_FILTER_ATTR(_name, _mode, _show, _store, _type, _mask) \ _mask 1051 drivers/media/rc/rc-main.c .mask = (_mask), \ _mask 283 drivers/mfd/axp20x.c #define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \ _mask 284 drivers/mfd/axp20x.c [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) } _mask 54 drivers/mfd/max8997-irq.c #define DECLARE_IRQ(idx, _group, _mask) \ _mask 55 drivers/mfd/max8997-irq.c [(idx)] = { .group = (_group), .mask = (_mask) } _mask 59 drivers/mfd/tps6586x.c #define TPS6586X_IRQ(_reg, _mask) \ _mask 62 drivers/mfd/tps6586x.c .mask_mask = (_mask), \ _mask 82 drivers/mfd/tps80031.c #define TPS80031_IRQ(_reg, _mask) \ _mask 86 drivers/mfd/tps80031.c .mask = BIT(_mask), \ _mask 163 drivers/net/dsa/bcm_sf2.h priv->irq##which##_mask &= ~(mask); \ _mask 170 drivers/net/dsa/bcm_sf2.h priv->irq##which##_mask |= (mask); \ _mask 1686 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ _mask 1687 drivers/net/ethernet/amd/xgbe/xgbe-common.h (XMDIO_READ((_pdata), _mmd, _reg) & _mask) _mask 1693 drivers/net/ethernet/amd/xgbe/xgbe-common.h #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ _mask 1696 drivers/net/ethernet/amd/xgbe/xgbe-common.h mmd_val &= ~_mask; \ _mask 88 drivers/net/ethernet/broadcom/bcmsysport.c priv->irq##which##_mask &= ~(mask); \ _mask 95 drivers/net/ethernet/broadcom/bcmsysport.c priv->irq##which##_mask |= (mask); \ _mask 118 drivers/net/ethernet/sfc/enum.h #define LOOPBACK_CHANGED(_from, _to, _mask) \ _mask 119 drivers/net/ethernet/sfc/enum.h (!!((LOOPBACK_MASK(_from) ^ LOOPBACK_MASK(_to)) & (_mask))) _mask 121 drivers/net/ethernet/sfc/enum.h #define LOOPBACK_OUT_OF(_from, _to, _mask) \ _mask 122 drivers/net/ethernet/sfc/enum.h ((LOOPBACK_MASK(_from) & (_mask)) && !(LOOPBACK_MASK(_to) & (_mask))) _mask 117 drivers/net/ethernet/sfc/falcon/enum.h #define LOOPBACK_CHANGED(_from, _to, _mask) \ _mask 118 drivers/net/ethernet/sfc/falcon/enum.h (!!((LOOPBACK_MASK(_from) ^ LOOPBACK_MASK(_to)) & (_mask))) _mask 120 drivers/net/ethernet/sfc/falcon/enum.h #define LOOPBACK_OUT_OF(_from, _to, _mask) \ _mask 121 drivers/net/ethernet/sfc/falcon/enum.h ((LOOPBACK_MASK(_from) & (_mask)) && !(LOOPBACK_MASK(_to) & (_mask))) _mask 128 drivers/net/wireless/ath/ath5k/ath5k.h #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ _mask 130 drivers/net/wireless/ath/ath5k/ath5k.h (_mask)) | (_flags), _reg) _mask 286 drivers/perf/arm-ccn.c #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \ _mask 289 drivers/perf/arm-ccn.c .def = _def, .mask = _mask, } _mask 291 drivers/perf/arm-ccn.c #define CCN_EVENT_HNI(_name, _def, _mask) { \ _mask 294 drivers/perf/arm-ccn.c .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } _mask 296 drivers/perf/arm-ccn.c #define CCN_EVENT_SBSX(_name, _def, _mask) { \ _mask 299 drivers/perf/arm-ccn.c .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } _mask 345 drivers/phy/mscc/phy-ocelot-serdes.c #define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \ _mask 350 drivers/phy/mscc/phy-ocelot-serdes.c .mask = _mask, \ _mask 404 drivers/phy/tegra/xusb-tegra124.c #define TEGRA124_LANE(_name, _offset, _shift, _mask, _type) \ _mask 409 drivers/phy/tegra/xusb-tegra124.c .mask = _mask, \ _mask 112 drivers/phy/tegra/xusb-tegra186.c #define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \ _mask 117 drivers/phy/tegra/xusb-tegra186.c .mask = _mask, \ _mask 839 drivers/phy/tegra/xusb-tegra210.c #define TEGRA210_LANE(_name, _offset, _shift, _mask, _type) \ _mask 844 drivers/phy/tegra/xusb-tegra210.c .mask = _mask, \ _mask 112 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \ _mask 117 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .reg_mask = _mask, \ _mask 118 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .val = {0, _mask}, \ _mask 122 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \ _mask 127 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .reg_mask = _mask, \ _mask 128 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .val = {0, _mask}, \ _mask 132 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \ _mask 137 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .reg_mask = _mask, \ _mask 142 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \ _mask 147 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .reg_mask = _mask, \ _mask 152 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \ _mask 158 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c .reg_mask = _mask, \ _mask 157 drivers/pinctrl/mvebu/pinctrl-mvebu.h #define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ _mask 162 drivers/pinctrl/mvebu/pinctrl-mvebu.h .variant = _mask, \ _mask 167 drivers/pinctrl/mvebu/pinctrl-mvebu.h #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ _mask 168 drivers/pinctrl/mvebu/pinctrl-mvebu.h _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) _mask 170 drivers/pinctrl/mvebu/pinctrl-mvebu.h #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ _mask 171 drivers/pinctrl/mvebu/pinctrl-mvebu.h _MPP_VAR_FUNCTION(_val, _name, NULL, _mask) _mask 392 drivers/pinctrl/pinctrl-palmas.c #define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv) \ _mask 396 drivers/pinctrl/pinctrl-palmas.c .pullup_dn_mask = _mask, \ _mask 428 drivers/pinctrl/pinctrl-palmas.c #define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv) \ _mask 432 drivers/pinctrl/pinctrl-palmas.c .od_mask = _mask, \ _mask 506 drivers/pinctrl/pinctrl-palmas.c #define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \ _mask 513 drivers/pinctrl/pinctrl-palmas.c .mux_reg_mask = _mask, \ _mask 499 drivers/pinctrl/pinctrl-pistachio.c #define FUNCTION_SCENARIO(_name, _reg, _shift, _mask) \ _mask 508 drivers/pinctrl/pinctrl-pistachio.c .scenario_mask = _mask, \ _mask 662 drivers/pinctrl/pinctrl-pistachio.c #define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask) \ _mask 673 drivers/pinctrl/pinctrl-pistachio.c .mux_mask = _mask, \ _mask 645 drivers/pinctrl/spear/pinctrl-plgpio.c #define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \ _mask 648 drivers/pinctrl/spear/pinctrl-plgpio.c _tmp &= ~_mask; \ _mask 650 drivers/pinctrl/spear/pinctrl-plgpio.c _tmp | (plgpio->csave_regs[i].__reg & _mask); \ _mask 827 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ _mask 832 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c .mask = _mask, \ _mask 1071 drivers/regulator/ab8500.c #define REG_INIT(_id, _bank, _addr, _mask) \ _mask 1075 drivers/regulator/ab8500.c .mask = _mask, \ _mask 26 drivers/regulator/da9063-regulator.c #define BFIELD(_reg, _mask) \ _mask 27 drivers/regulator/da9063-regulator.c REG_FIELD(_reg, __builtin_ffs((int)_mask) - 1, \ _mask 28 drivers/regulator/da9063-regulator.c sizeof(unsigned int) * 8 - __builtin_clz((_mask)) - 1) _mask 287 drivers/regulator/max8997-regulator.c int *_reg, int *_shift, int *_mask) _mask 347 drivers/regulator/max8997-regulator.c *_mask = mask; _mask 118 drivers/regulator/max8998.c int *_reg, int *_shift, int *_mask) _mask 175 drivers/regulator/max8998.c *_mask = mask; _mask 371 drivers/regulator/tps6524x-regulator.c #define __MK_FIELD(_reg, _mask, _shift) \ _mask 372 drivers/regulator/tps6524x-regulator.c { .reg = (_reg), .mask = (_mask), .shift = (_shift), } _mask 171 drivers/ssb/pci.c #define SPEX16(_outvar, _offset, _mask, _shift) \ _mask 172 drivers/ssb/pci.c out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift)) _mask 173 drivers/ssb/pci.c #define SPEX32(_outvar, _offset, _mask, _shift) \ _mask 175 drivers/ssb/pci.c in[SPOFF(_offset)]) & (_mask)) >> (_shift)) _mask 176 drivers/ssb/pci.c #define SPEX(_outvar, _offset, _mask, _shift) \ _mask 177 drivers/ssb/pci.c SPEX16(_outvar, _offset, _mask, _shift) _mask 179 drivers/ssb/pci.c #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ _mask 181 drivers/ssb/pci.c SPEX(_field[0], _offset + 0, _mask, _shift); \ _mask 182 drivers/ssb/pci.c SPEX(_field[1], _offset + 2, _mask, _shift); \ _mask 183 drivers/ssb/pci.c SPEX(_field[2], _offset + 4, _mask, _shift); \ _mask 184 drivers/ssb/pci.c SPEX(_field[3], _offset + 6, _mask, _shift); \ _mask 185 drivers/ssb/pci.c SPEX(_field[4], _offset + 8, _mask, _shift); \ _mask 186 drivers/ssb/pci.c SPEX(_field[5], _offset + 10, _mask, _shift); \ _mask 187 drivers/ssb/pci.c SPEX(_field[6], _offset + 12, _mask, _shift); \ _mask 188 drivers/ssb/pci.c SPEX(_field[7], _offset + 14, _mask, _shift); \ _mask 352 drivers/staging/iio/meter/meter.h #define IIO_EVENT_ATTR_AENERGY_HALF_FULL(_evlist, _show, _store, _mask) \ _mask 353 drivers/staging/iio/meter/meter.h IIO_EVENT_ATTR_SH(aenergy_half_full, _evlist, _show, _store, _mask) _mask 356 drivers/staging/iio/meter/meter.h #define IIO_EVENT_ATTR_LINE_VOLT_SAG(_evlist, _show, _store, _mask) \ _mask 357 drivers/staging/iio/meter/meter.h IIO_EVENT_ATTR_SH(line_volt_sag, _evlist, _show, _store, _mask) _mask 363 drivers/staging/iio/meter/meter.h #define IIO_EVENT_ATTR_CYCEND(_evlist, _show, _store, _mask) \ _mask 364 drivers/staging/iio/meter/meter.h IIO_EVENT_ATTR_SH(cycend, _evlist, _show, _store, _mask) _mask 367 drivers/staging/iio/meter/meter.h #define IIO_EVENT_ATTR_ZERO_CROSS(_evlist, _show, _store, _mask) \ _mask 368 drivers/staging/iio/meter/meter.h IIO_EVENT_ATTR_SH(zero_cross, _evlist, _show, _store, _mask) _mask 371 drivers/staging/iio/meter/meter.h #define IIO_EVENT_ATTR_AENERGY_OVERFLOW(_evlist, _show, _store, _mask) \ _mask 372 drivers/staging/iio/meter/meter.h IIO_EVENT_ATTR_SH(aenergy_overflow, _evlist, _show, _store, _mask) _mask 375 drivers/staging/iio/meter/meter.h #define IIO_EVENT_ATTR_VAENERGY_OVERFLOW(_evlist, _show, _store, _mask) \ _mask 376 drivers/staging/iio/meter/meter.h IIO_EVENT_ATTR_SH(vaenergy_overflow, _evlist, _show, _store, _mask) _mask 379 drivers/staging/iio/meter/meter.h #define IIO_EVENT_ATTR_VAENERGY_HALF_FULL(_evlist, _show, _store, _mask) \ _mask 380 drivers/staging/iio/meter/meter.h IIO_EVENT_ATTR_SH(vaenergy_half_full, _evlist, _show, _store, _mask) _mask 383 drivers/staging/iio/meter/meter.h #define IIO_EVENT_ATTR_PPOS(_evlist, _show, _store, _mask) \ _mask 384 drivers/staging/iio/meter/meter.h IIO_EVENT_ATTR_SH(ppos, _evlist, _show, _store, _mask) _mask 387 drivers/staging/iio/meter/meter.h #define IIO_EVENT_ATTR_PNEG(_evlist, _show, _store, _mask) \ _mask 388 drivers/staging/iio/meter/meter.h IIO_EVENT_ATTR_SH(pneg, _evlist, _show, _store, _mask) _mask 391 drivers/staging/iio/meter/meter.h #define IIO_EVENT_ATTR_IPKLVL_EXC(_evlist, _show, _store, _mask) \ _mask 392 drivers/staging/iio/meter/meter.h IIO_EVENT_ATTR_SH(ipklvl_exc, _evlist, _show, _store, _mask) _mask 395 drivers/staging/iio/meter/meter.h #define IIO_EVENT_ATTR_VPKLVL_EXC(_evlist, _show, _store, _mask) \ _mask 396 drivers/staging/iio/meter/meter.h IIO_EVENT_ATTR_SH(vpklvl_exc, _evlist, _show, _store, _mask) _mask 44 include/linux/bitfield.h #define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ _mask 46 include/linux/bitfield.h BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ _mask 48 include/linux/bitfield.h BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \ _mask 50 include/linux/bitfield.h ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \ _mask 52 include/linux/bitfield.h BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \ _mask 54 include/linux/bitfield.h __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \ _mask 55 include/linux/bitfield.h (1ULL << __bf_shf(_mask))); \ _mask 65 include/linux/bitfield.h #define FIELD_FIT(_mask, _val) \ _mask 67 include/linux/bitfield.h __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_FIT: "); \ _mask 68 include/linux/bitfield.h !((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \ _mask 79 include/linux/bitfield.h #define FIELD_PREP(_mask, _val) \ _mask 81 include/linux/bitfield.h __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ _mask 82 include/linux/bitfield.h ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ _mask 93 include/linux/bitfield.h #define FIELD_GET(_mask, _reg) \ _mask 95 include/linux/bitfield.h __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \ _mask 96 include/linux/bitfield.h (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ _mask 404 include/linux/netfilter/x_tables.h const char *_mask) _mask 408 include/linux/netfilter/x_tables.h const unsigned long *mask = (const unsigned long *)_mask; _mask 53 include/linux/nospec.h unsigned long _mask = array_index_mask_nospec(_i, _s); \ _mask 58 include/linux/nospec.h (typeof(_i)) (_i & _mask); \ _mask 137 include/linux/perf/arm_pmu.h #define PMU_PROBE(_cpuid, _mask, _fn) \ _mask 140 include/linux/perf/arm_pmu.h .mask = (_mask), \ _mask 1142 include/linux/regmap.h #define REGMAP_IRQ_REG(_irq, _off, _mask) \ _mask 1143 include/linux/regmap.h [_irq] = { .reg_offset = (_off), .mask = (_mask) } _mask 55 include/linux/regulator/ab8500.h #define INIT_REGULATOR_REGISTER(_id, _mask, _value) \ _mask 58 include/linux/regulator/ab8500.h .mask = _mask, \ _mask 875 include/soc/fsl/qman.h ((np)->field & (qm_mcr_##field##_mask)) _mask 342 include/xen/interface/io/ring.h static inline RING_IDX name##_mask(RING_IDX idx, RING_IDX ring_size) \ _mask 351 include/xen/interface/io/ring.h return buf + name##_mask(idx, ring_size); \ _mask 369 include/xen/interface/io/ring.h *masked_cons = name##_mask(*masked_cons + size, ring_size); \ _mask 387 include/xen/interface/io/ring.h *masked_prod = name##_mask(*masked_prod + size, ring_size); \ _mask 399 include/xen/interface/io/ring.h prod = name##_mask(prod, ring_size); \ _mask 400 include/xen/interface/io/ring.h cons = name##_mask(cons, ring_size); \ _mask 6057 kernel/events/core.c DECLARE_BITMAP(_mask, 64); _mask 6059 kernel/events/core.c bitmap_from_u64(_mask, mask); _mask 6060 kernel/events/core.c for_each_set_bit(bit, _mask, sizeof(mask) * BITS_PER_BYTE) { _mask 350 kernel/sched/core.c typeof(mask) _mask = (mask); \ _mask 354 kernel/sched/core.c _old = cmpxchg(_ptr, _val, _val | _mask); \ _mask 28 net/6lowpan/nhc.h static u8 __nhc##_mask[_idlen]; \ _mask 34 net/6lowpan/nhc.h .idmask = __nhc##_mask, \ _mask 43 net/bridge/br_sysfs_if.c #define BRPORT_ATTR_FLAG(_name, _mask) \ _mask 46 net/bridge/br_sysfs_if.c return sprintf(buf, "%d\n", !!(p->flags & _mask)); \ _mask 50 net/bridge/br_sysfs_if.c return store_flag(p, v, _mask); \ _mask 64 net/ipv4/netfilter/arp_tables.c static unsigned long ifname_compare(const char *_a, const char *_b, const char *_mask) _mask 67 net/ipv4/netfilter/arp_tables.c unsigned long ret = ifname_compare_aligned(_a, _b, _mask); _mask 72 net/ipv4/netfilter/arp_tables.c const u16 *mask = (const u16 *)_mask; _mask 2095 net/sched/cls_flower.c __be32 _key, _mask; _mask 2111 net/sched/cls_flower.c _mask = cpu_to_be32(mask); _mask 2117 net/sched/cls_flower.c return nla_put(skb, TCA_FLOWER_KEY_FLAGS_MASK, 4, &_mask); _mask 187 sound/pci/hda/patch_realtek.c #define UPDATE_COEFEX(_nid, _idx, _mask, _val) \ _mask 188 sound/pci/hda/patch_realtek.c { .nid = (_nid), .idx = (_idx), .mask = (_mask), .val = (_val) } _mask 191 sound/pci/hda/patch_realtek.c #define UPDATE_COEF(_idx, _mask, _val) UPDATE_COEFEX(0x20, _idx, _mask, _val)