__raw_readl 258 arch/alpha/include/asm/io.h extern u32 __raw_readl(const volatile void __iomem *addr); __raw_readl 466 arch/alpha/include/asm/io.h u32 ret = __raw_readl(addr); __raw_readl 504 arch/alpha/include/asm/io.h #define readl_relaxed(addr) __raw_readl(addr) __raw_readl 142 arch/alpha/kernel/io.c EXPORT_SYMBOL(__raw_readl); __raw_readl 165 arch/alpha/kernel/io.c u32 ret = __raw_readl(addr); __raw_readl 440 arch/alpha/kernel/io.c *(u32 *)to = __raw_readl(from); __raw_readl 45 arch/arc/include/asm/io.h #define ioread32be(p) ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) __raw_readl 81 arch/arc/include/asm/io.h #define __raw_readl __raw_readl __raw_readl 231 arch/arc/include/asm/io.h __raw_readl(c)); __r; }) __raw_readl 37 arch/arm/common/it8152.c __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) | __raw_readl 41 arch/arm/common/it8152.c __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) | __raw_readl 45 arch/arm/common/it8152.c __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) | __raw_readl 56 arch/arm/common/it8152.c __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) & __raw_readl 60 arch/arm/common/it8152.c __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) & __raw_readl 64 arch/arm/common/it8152.c __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) & __raw_readl 102 arch/arm/common/it8152.c bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); __raw_readl 103 arch/arm/common/it8152.c bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); __raw_readl 104 arch/arm/common/it8152.c bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); __raw_readl 114 arch/arm/common/it8152.c bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); __raw_readl 115 arch/arm/common/it8152.c bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); __raw_readl 116 arch/arm/common/it8152.c bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); __raw_readl 185 arch/arm/common/it8152.c v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift))); __raw_readl 208 arch/arm/common/it8152.c vtemp = __raw_readl(IT8152_PCI_CFG_DATA); __raw_readl 90 arch/arm/include/asm/cti.h val = __raw_readl(base + CTIINEN + trig_in * 4); __raw_readl 94 arch/arm/include/asm/cti.h val = __raw_readl(base + CTIOUTEN + trig_out * 4); __raw_readl 132 arch/arm/include/asm/cti.h val = __raw_readl(base + CTIINTACK); __raw_readl 21 arch/arm/include/asm/hardware/iomd.h #define iomd_readl(off) __raw_readl(IOMD_BASE + (off)) __raw_readl 109 arch/arm/include/asm/io.h #define __raw_readl __raw_readl __raw_readl 262 arch/arm/include/asm/io.h __raw_readl(__io(p))); __iormb(); __v; }) __raw_readl 295 arch/arm/include/asm/io.h __raw_readl(c)); __r; }) __raw_readl 423 arch/arm/include/asm/io.h #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) __raw_readl 62 arch/arm/mach-at91/pm.c __raw_readl(soc_pm.data.ramc[id] + field) __raw_readl 140 arch/arm/mach-cns3xxx/cns3420vb.c __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), __raw_readl 316 arch/arm/mach-cns3xxx/core.c __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), __raw_readl 364 arch/arm/mach-cns3xxx/core.c tmp = __raw_readl(MISC_SATA_POWER_MODE); __raw_readl 383 arch/arm/mach-cns3xxx/core.c u32 gpioa_pins = __raw_readl(gpioa); __raw_readl 54 arch/arm/mach-cns3xxx/devices.c tmp = __raw_readl(MISC_SATA_POWER_MODE); __raw_readl 98 arch/arm/mach-cns3xxx/devices.c u32 gpioa_pins = __raw_readl(gpioa); __raw_readl 187 arch/arm/mach-cns3xxx/pcie.c reg = __raw_readl(MISC_PCIE_CTRL(port)); __raw_readl 200 arch/arm/mach-cns3xxx/pcie.c reg = __raw_readl(MISC_PCIE_PM_DEBUG(port)); __raw_readl 17 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_CLK_GATE_REG); __raw_readl 26 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_CLK_GATE_REG); __raw_readl 35 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); __raw_readl 47 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); __raw_readl 57 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_SOFT_RST_REG); __raw_readl 105 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_CLK_CTRL_REG); __raw_readl 1111 arch/arm/mach-davinci/board-da850-evm.c val = __raw_readl(cfg_chip3_base); __raw_readl 494 arch/arm/mach-davinci/board-dm646x-evm.c value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); __raw_readl 512 arch/arm/mach-davinci/board-dm646x-evm.c value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL)); __raw_readl 524 arch/arm/mach-davinci/board-dm646x-evm.c value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); __raw_readl 652 arch/arm/mach-davinci/board-dm646x-evm.c value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL)); __raw_readl 530 arch/arm/mach-davinci/board-mityomapl138.c val = __raw_readl(cfg_chip3_base); __raw_readl 55 arch/arm/mach-davinci/board-omapl138-hawk.c val = __raw_readl(cfgchip3); __raw_readl 40 arch/arm/mach-davinci/common.c soc_info->jtag_id = __raw_readl(base); __raw_readl 31 arch/arm/mach-davinci/cpuidle.c val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET); __raw_readl 210 arch/arm/mach-davinci/devices.c v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1)); __raw_readl 614 arch/arm/mach-davinci/dm646x.c value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS)); __raw_readl 618 arch/arm/mach-davinci/dm646x.c value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN)); __raw_readl 70 arch/arm/mach-davinci/mux.c reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); __raw_readl 51 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); __raw_readl 58 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); __raw_readl 64 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.deepsleep_reg); __raw_readl 75 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); __raw_readl 80 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); __raw_readl 88 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); __raw_readl 96 arch/arm/mach-davinci/pm.c val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); __raw_readl 128 arch/arm/mach-davinci/time.c __raw_writel(__raw_readl(t->base + t->tim_off) + t->period, __raw_readl 131 arch/arm/mach-davinci/time.c tcr = __raw_readl(t->base + TCR); __raw_readl 154 arch/arm/mach-davinci/time.c return __raw_readl(t->base + t->tim_off); __raw_readl 73 arch/arm/mach-ebsa110/io.c ret = __raw_readl(a); __raw_readl 226 arch/arm/mach-ebsa110/io.c ret = __raw_readl(a); __raw_readl 253 arch/arm/mach-ep93xx/clock.c v = __raw_readl(clk->enable_reg); __raw_readl 284 arch/arm/mach-ep93xx/clock.c v = __raw_readl(clk->enable_reg); __raw_readl 315 arch/arm/mach-ep93xx/clock.c value = __raw_readl(EP93XX_SYSCON_PWRCNT); __raw_readl 336 arch/arm/mach-ep93xx/clock.c val = __raw_readl(clk->enable_reg); __raw_readl 425 arch/arm/mach-ep93xx/clock.c val = __raw_readl(clk->enable_reg); __raw_readl 438 arch/arm/mach-ep93xx/clock.c unsigned val = __raw_readl(clk->enable_reg); __raw_readl 455 arch/arm/mach-ep93xx/clock.c unsigned val = __raw_readl(clk->enable_reg) & __raw_readl 547 arch/arm/mach-ep93xx/clock.c value = __raw_readl(EP93XX_SYSCON_CLKSET1); __raw_readl 560 arch/arm/mach-ep93xx/clock.c value = __raw_readl(EP93XX_SYSCON_CLKSET2); __raw_readl 112 arch/arm/mach-ep93xx/core.c val = __raw_readl(EP93XX_SYSCON_DEVCFG); __raw_readl 130 arch/arm/mach-ep93xx/core.c v = __raw_readl(EP93XX_SYSCON_SYSCFG); __raw_readl 685 arch/arm/mach-ep93xx/core.c val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV); __raw_readl 891 arch/arm/mach-ep93xx/core.c if (__raw_readl(EP93XX_SECURITY_UNIQVAL) != 1) __raw_readl 894 arch/arm/mach-ep93xx/core.c id = __raw_readl(EP93XX_SECURITY_UNIQID); __raw_readl 895 arch/arm/mach-ep93xx/core.c id2 = __raw_readl(EP93XX_SECURITY_UNIQID2); __raw_readl 896 arch/arm/mach-ep93xx/core.c id3 = __raw_readl(EP93XX_SECURITY_UNIQID3); __raw_readl 897 arch/arm/mach-ep93xx/core.c id4 = __raw_readl(EP93XX_SECURITY_UNIQID4); __raw_readl 898 arch/arm/mach-ep93xx/core.c id5 = __raw_readl(EP93XX_SECURITY_UNIQID5); __raw_readl 59 arch/arm/mach-ep93xx/crunch.c devcfg = __raw_readl(EP93XX_SYSCON_DEVCFG); __raw_readl 67 arch/arm/mach-ep93xx/include/mach/uncompress.h v = __raw_readl(PHYS_ETH_SELF_CTL); __raw_readl 71 arch/arm/mach-ep93xx/include/mach/uncompress.h while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET) __raw_readl 36 arch/arm/mach-ep93xx/micro9.c v = __raw_readl(EP93XX_SYSCON_SYSCFG); __raw_readl 361 arch/arm/mach-ixp4xx/goramo_mlr.c system_rev = __raw_readl(flash + CFG_REV); __raw_readl 362 arch/arm/mach-ixp4xx/goramo_mlr.c hw_bits = __raw_readl(flash + CFG_HW_BITS); __raw_readl 37 arch/arm/mach-ixp4xx/include/mach/cpu.h u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); __raw_readl 204 arch/arm/mach-ixp4xx/include/mach/io.h return __raw_readl(p); __raw_readl 425 arch/arm/mach-ixp4xx/include/mach/io.h return le32_to_cpu((__force __le32)__raw_readl(addr)); __raw_readl 27 arch/arm/mach-lpc32xx/common.c devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2)); __raw_readl 43 arch/arm/mach-lpc32xx/common.c savedval1 = __raw_readl(iramptr1); __raw_readl 44 arch/arm/mach-lpc32xx/common.c savedval2 = __raw_readl(iramptr2); __raw_readl 48 arch/arm/mach-lpc32xx/common.c if (__raw_readl(iramptr1) == savedval2 + 1) __raw_readl 67 arch/arm/mach-lpc32xx/common.c u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); __raw_readl 131 arch/arm/mach-lpc32xx/pm.c __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG); __raw_readl 120 arch/arm/mach-lpc32xx/serial.c tmp = __raw_readl( __raw_readl 134 arch/arm/mach-lpc32xx/serial.c tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart)); __raw_readl 139 arch/arm/mach-lpc32xx/serial.c tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); __raw_readl 144 arch/arm/mach-lpc32xx/serial.c tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); __raw_readl 53 arch/arm/mach-mmp/clock-mmp2.c clk_rst = __raw_readl(clk->clk_rst); __raw_readl 62 arch/arm/mach-mmp/clock-mmp2.c clk_rst = __raw_readl(clk->clk_rst); __raw_readl 44 arch/arm/mach-mmp/common.c mmp_chip_id = __raw_readl(MMP_CHIPID); __raw_readl 89 arch/arm/mach-mmp/mmp2.c data = __raw_readl(mfpr_pmic); __raw_readl 47 arch/arm/mach-mmp/pm-mmp2.c data |= __raw_readl(MPMU_WUCRM_PJ); __raw_readl 52 arch/arm/mach-mmp/pm-mmp2.c data = ~data & __raw_readl(MPMU_WUCRM_PJ); __raw_readl 68 arch/arm/mach-mmp/pm-mmp2.c val = __raw_readl(CIU_REG(0x1c)); __raw_readl 84 arch/arm/mach-mmp/pm-mmp2.c val = __raw_readl(CIU_REG(0x1c)); __raw_readl 105 arch/arm/mach-mmp/pm-mmp2.c val = __raw_readl(MPMU_PLL2_CTRL1); __raw_readl 116 arch/arm/mach-mmp/pm-mmp2.c idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG); __raw_readl 117 arch/arm/mach-mmp/pm-mmp2.c apcr = __raw_readl(MPMU_PCR_PJ); __raw_readl 162 arch/arm/mach-mmp/pm-mmp2.c temp = __raw_readl(MMP2_ICU_INT4_MASK); __raw_readl 168 arch/arm/mach-mmp/pm-mmp2.c temp = __raw_readl(APMU_SRAM_PWR_DWN); __raw_readl 237 arch/arm/mach-mmp/pm-mmp2.c __raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8)); __raw_readl 240 arch/arm/mach-mmp/pm-mmp2.c apcr = __raw_readl(MPMU_PCR_PJ); __raw_readl 112 arch/arm/mach-mmp/pm-pxa910.c awucrm |= __raw_readl(MPMU_AWUCRM); __raw_readl 116 arch/arm/mach-mmp/pm-pxa910.c apcr = ~apcr & __raw_readl(MPMU_APCR); __raw_readl 121 arch/arm/mach-mmp/pm-pxa910.c awucrm = ~awucrm & __raw_readl(MPMU_AWUCRM); __raw_readl 125 arch/arm/mach-mmp/pm-pxa910.c apcr |= __raw_readl(MPMU_APCR); __raw_readl 136 arch/arm/mach-mmp/pm-pxa910.c idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); __raw_readl 137 arch/arm/mach-mmp/pm-pxa910.c apcr = __raw_readl(MPMU_APCR); __raw_readl 192 arch/arm/mach-mmp/pm-pxa910.c reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT)); __raw_readl 196 arch/arm/mach-mmp/pm-pxa910.c idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); __raw_readl 215 arch/arm/mach-mmp/pm-pxa910.c idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); __raw_readl 262 arch/arm/mach-mmp/pm-pxa910.c __raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30), __raw_readl 264 arch/arm/mach-mmp/pm-pxa910.c __raw_writel(__raw_readl(MPMU_FCCR) | (1 << 28), MPMU_FCCR); __raw_readl 88 arch/arm/mach-mmp/pxa168.c val = __raw_readl(APMU_WAKE_CLR); __raw_readl 58 arch/arm/mach-mmp/time.c return __raw_readl(mmp_timer_base + TMR_CVWR(1)); __raw_readl 154 arch/arm/mach-mmp/time.c uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR); __raw_readl 110 arch/arm/mach-mxs/mach-mxs.c while ((__raw_readl(ocotp_base) & __raw_readl 125 arch/arm/mach-mxs/mach-mxs.c while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout) __raw_readl 132 arch/arm/mach-mxs/mach-mxs.c ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET + __raw_readl 43 arch/arm/mach-omap1/clock.c unsigned int val = __raw_readl(clk->enable_reg); __raw_readl 331 arch/arm/mach-omap1/clock.c val = __raw_readl(clk->enable_reg); __raw_readl 461 arch/arm/mach-omap1/clock.c regval32 = __raw_readl(clk->enable_reg); __raw_readl 482 arch/arm/mach-omap1/clock.c regval32 = __raw_readl(clk->enable_reg); __raw_readl 595 arch/arm/mach-omap1/clock.c regval32 = __raw_readl(clk->enable_reg); __raw_readl 159 arch/arm/mach-omap1/io.c return __raw_readl(OMAP1_IO_ADDRESS(pa)); __raw_readl 622 arch/arm/mach-omap2/omap-wakeupgen.c val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE); __raw_readl 495 arch/arm/mach-pxa/balloon3.c unsigned long pending = __raw_readl(BALLOON3_INT_CONTROL_REG) & __raw_readl 511 arch/arm/mach-pxa/balloon3.c pending = __raw_readl(BALLOON3_INT_CONTROL_REG) & __raw_readl 614 arch/arm/mach-pxa/balloon3.c return __raw_readl(BALLOON3_NAND_STAT_REG) & BALLOON3_NAND_STAT_RNB; __raw_readl 55 arch/arm/mach-pxa/cm-x2xx-pci.c sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR); __raw_readl 56 arch/arm/mach-pxa/cm-x2xx-pci.c sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR); __raw_readl 57 arch/arm/mach-pxa/cm-x2xx-pci.c sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR); __raw_readl 129 arch/arm/mach-pxa/cm-x2xx-pci.c if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) { __raw_readl 405 arch/arm/mach-pxa/cm-x2xx.c sleep_save_msc[0] = __raw_readl(MSC0); __raw_readl 406 arch/arm/mach-pxa/cm-x2xx.c sleep_save_msc[1] = __raw_readl(MSC1); __raw_readl 407 arch/arm/mach-pxa/cm-x2xx.c sleep_save_msc[2] = __raw_readl(MSC2); __raw_readl 266 arch/arm/mach-pxa/csb726.c __raw_writel((__raw_readl(MSC2) & ~0xffff) | 0x7ff4, MSC2); /* SM501 */ __raw_readl 177 arch/arm/mach-pxa/h5000.c __raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR); __raw_readl 68 arch/arm/mach-pxa/irq.c uint32_t icmr = __raw_readl(base + ICMR); __raw_readl 78 arch/arm/mach-pxa/irq.c uint32_t icmr = __raw_readl(base + ICMR); __raw_readl 96 arch/arm/mach-pxa/irq.c icip = __raw_readl(pxa_irq_base + ICIP); __raw_readl 97 arch/arm/mach-pxa/irq.c icmr = __raw_readl(pxa_irq_base + ICMR); __raw_readl 188 arch/arm/mach-pxa/irq.c saved_icmr[i] = __raw_readl(base + ICMR); __raw_readl 194 arch/arm/mach-pxa/irq.c saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i)); __raw_readl 468 arch/arm/mach-pxa/lpd270.c lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4; __raw_readl 506 arch/arm/mach-pxa/lubbock.c (__raw_readl(BOOT_DEF) & 1) ? 2 : 4; __raw_readl 567 arch/arm/mach-pxa/mainstone.c mst_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4; __raw_readl 114 arch/arm/mach-pxa/pxa27x.c sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR); __raw_readl 41 arch/arm/mach-pxa/pxa3xx-ulpi.c return __raw_readl(u2d->mmio_base + reg); __raw_readl 22 arch/arm/mach-pxa/smemc.c msc[0] = __raw_readl(MSC0); __raw_readl 23 arch/arm/mach-pxa/smemc.c msc[1] = __raw_readl(MSC1); __raw_readl 24 arch/arm/mach-pxa/smemc.c sxcnfg = __raw_readl(SXCNFG); __raw_readl 25 arch/arm/mach-pxa/smemc.c memclkcfg = __raw_readl(MEMCLKCFG); __raw_readl 26 arch/arm/mach-pxa/smemc.c csadrcfg[0] = __raw_readl(CSADRCFG0); __raw_readl 27 arch/arm/mach-pxa/smemc.c csadrcfg[1] = __raw_readl(CSADRCFG1); __raw_readl 28 arch/arm/mach-pxa/smemc.c csadrcfg[2] = __raw_readl(CSADRCFG2); __raw_readl 29 arch/arm/mach-pxa/smemc.c csadrcfg[3] = __raw_readl(CSADRCFG3); __raw_readl 969 arch/arm/mach-pxa/spitz.c uint32_t msc0 = __raw_readl(MSC0); __raw_readl 981 arch/arm/mach-pxa/stargate2.c __raw_writel(__raw_readl(MECR) & ~MECR_NOS, MECR); __raw_readl 889 arch/arm/mach-pxa/tosa.c uint32_t msc0 = __raw_readl(MSC0); __raw_readl 542 arch/arm/mach-pxa/trizeps4.c if ((__raw_readl(MSC0) & 0x8) && (__raw_readl(BOOT_DEF) & 0x1)) { __raw_readl 172 arch/arm/mach-pxa/xcep.c __raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1); __raw_readl 174 arch/arm/mach-pxa/xcep.c __raw_writel((__raw_readl(MSC2) & 0xffff) | 0x72A00000, MSC2); __raw_readl 869 arch/arm/mach-pxa/zeus.c msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16); __raw_readl 870 arch/arm/mach-pxa/zeus.c msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc; __raw_readl 154 arch/arm/mach-s3c24xx/common.c u32 gs = __raw_readl(S3C24XX_GSTATUS1); __raw_readl 162 arch/arm/mach-s3c24xx/common.c return __raw_readl(S3C2412_GSTATUS1); __raw_readl 170 arch/arm/mach-s3c24xx/common.c return __raw_readl(S3C2410_GSTATUS1); __raw_readl 184 arch/arm/mach-s3c24xx/common.c __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE, __raw_readl 189 arch/arm/mach-s3c24xx/common.c tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */ __raw_readl 193 arch/arm/mach-s3c24xx/common.c __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE, __raw_readl 48 arch/arm/mach-s3c24xx/cpufreq-utils.c refval = __raw_readl(S3C2410_REFRESH); __raw_readl 18 arch/arm/mach-s3c24xx/include/mach/pm-core.h unsigned long tmp = __raw_readl(S3C2410_CLKCON); __raw_readl 36 arch/arm/mach-s3c24xx/include/mach/pm-core.h __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); __raw_readl 37 arch/arm/mach-s3c24xx/include/mach/pm-core.h __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); __raw_readl 38 arch/arm/mach-s3c24xx/include/mach/pm-core.h __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); __raw_readl 68 arch/arm/mach-s3c24xx/include/mach/pm-core.h __raw_readl(S3C2410_SRCPND), __raw_readl 69 arch/arm/mach-s3c24xx/include/mach/pm-core.h __raw_readl(S3C2410_EINTPEND)); __raw_readl 71 arch/arm/mach-s3c24xx/include/mach/pm-core.h s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), __raw_readl 74 arch/arm/mach-s3c24xx/include/mach/pm-core.h s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), __raw_readl 366 arch/arm/mach-s3c24xx/iotiming-s3c2410.c bankcon = __raw_readl(bank_reg(bank)); __raw_readl 439 arch/arm/mach-s3c24xx/iotiming-s3c2410.c bwscon = __raw_readl(S3C2410_BWSCON); __raw_readl 444 arch/arm/mach-s3c24xx/iotiming-s3c2410.c bankcon = __raw_readl(bank_reg(bank)); __raw_readl 208 arch/arm/mach-s3c24xx/iotiming-s3c2412.c bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR)); __raw_readl 209 arch/arm/mach-s3c24xx/iotiming-s3c2412.c bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR)); __raw_readl 210 arch/arm/mach-s3c24xx/iotiming-s3c2412.c bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR)); __raw_readl 211 arch/arm/mach-s3c24xx/iotiming-s3c2412.c bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR)); __raw_readl 212 arch/arm/mach-s3c24xx/iotiming-s3c2412.c bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR)); __raw_readl 232 arch/arm/mach-s3c24xx/iotiming-s3c2412.c u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG); __raw_readl 64 arch/arm/mach-s3c24xx/irq-pm.c save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); __raw_readl 67 arch/arm/mach-s3c24xx/irq-pm.c save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); __raw_readl 70 arch/arm/mach-s3c24xx/irq-pm.c save_eintmask = __raw_readl(S3C24XX_EINTMASK); __raw_readl 380 arch/arm/mach-s3c24xx/mach-osiris.c __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON); __raw_readl 35 arch/arm/mach-s3c24xx/pm-s3c2410.c S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); __raw_readl 36 arch/arm/mach-s3c24xx/pm-s3c2410.c S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); __raw_readl 46 arch/arm/mach-s3c24xx/pm-s3c2410.c calc += __raw_readl(base+ptr); __raw_readl 62 arch/arm/mach-s3c24xx/pm-s3c2410.c calc += __raw_readl(base+ptr); __raw_readl 91 arch/arm/mach-s3c24xx/pm-s3c2410.c tmp = __raw_readl(S3C2410_GSTATUS2); __raw_readl 40 arch/arm/mach-s3c24xx/pm-s3c2412.c tmp = __raw_readl(S3C2412_PWRCFG); __raw_readl 115 arch/arm/mach-s3c24xx/pm-s3c2412.c tmp = __raw_readl(S3C2412_PWRCFG); __raw_readl 116 arch/arm/mach-s3c24xx/s3c2412.c tmp = __raw_readl(S3C2412_PWRCFG); __raw_readl 53 arch/arm/mach-s3c24xx/simtec-pm.c gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30; __raw_readl 54 arch/arm/mach-s3c24xx/simtec-pm.c gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28; __raw_readl 55 arch/arm/mach-s3c24xx/simtec-pm.c gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK); __raw_readl 253 arch/arm/mach-s3c64xx/common.c mask = __raw_readl(S3C64XX_EINT0MASK); __raw_readl 262 arch/arm/mach-s3c64xx/common.c mask = __raw_readl(S3C64XX_EINT0MASK); __raw_readl 332 arch/arm/mach-s3c64xx/common.c ctrl = __raw_readl(reg); __raw_readl 373 arch/arm/mach-s3c64xx/common.c u32 status = __raw_readl(S3C64XX_EINT0PEND); __raw_readl 374 arch/arm/mach-s3c64xx/common.c u32 mask = __raw_readl(S3C64XX_EINT0MASK); __raw_readl 29 arch/arm/mach-s3c64xx/cpuidle.c tmp = __raw_readl(S3C64XX_PWR_CFG); __raw_readl 23 arch/arm/mach-s3c64xx/include/mach/pm-core.h u32 tmp = __raw_readl(S3C_PCLK_GATE); __raw_readl 45 arch/arm/mach-s3c64xx/include/mach/pm-core.h __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); __raw_readl 69 arch/arm/mach-s3c64xx/include/mach/pm-core.h u32 ucon = __raw_readl(regs + S3C2410_UCON); __raw_readl 71 arch/arm/mach-s3c64xx/irq-pm.c irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM); __raw_readl 74 arch/arm/mach-s3c64xx/irq-pm.c grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4)); __raw_readl 75 arch/arm/mach-s3c64xx/irq-pm.c grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4)); __raw_readl 76 arch/arm/mach-s3c64xx/irq-pm.c grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4)); __raw_readl 89 arch/arm/mach-s3c64xx/mach-anw6410.c tmp = __raw_readl(S3C64XX_SPCON); __raw_readl 95 arch/arm/mach-s3c64xx/mach-anw6410.c tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); __raw_readl 244 arch/arm/mach-s3c64xx/mach-mini6410.c tmp = __raw_readl(S3C64XX_SPCON); __raw_readl 250 arch/arm/mach-s3c64xx/mach-mini6410.c tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); __raw_readl 334 arch/arm/mach-s3c64xx/mach-mini6410.c cs1 = __raw_readl(S3C64XX_SROM_BW) & __raw_readl 214 arch/arm/mach-s3c64xx/mach-real6410.c tmp = __raw_readl(S3C64XX_SPCON); __raw_readl 220 arch/arm/mach-s3c64xx/mach-real6410.c tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); __raw_readl 303 arch/arm/mach-s3c64xx/mach-real6410.c cs1 = __raw_readl(S3C64XX_SROM_BW) & __raw_readl 276 arch/arm/mach-s3c64xx/mach-smartq.c tmp = __raw_readl(S3C64XX_SPCON); __raw_readl 282 arch/arm/mach-s3c64xx/mach-smartq.c tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); __raw_readl 642 arch/arm/mach-s3c64xx/mach-smdk6410.c tmp = __raw_readl(S3C64XX_SPCON); __raw_readl 648 arch/arm/mach-s3c64xx/mach-smdk6410.c tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); __raw_readl 668 arch/arm/mach-s3c64xx/mach-smdk6410.c cs1 = __raw_readl(S3C64XX_SROM_BW) & __raw_readl 48 arch/arm/mach-s3c64xx/pm.c val = __raw_readl(S3C64XX_NORMAL_CFG); __raw_readl 63 arch/arm/mach-s3c64xx/pm.c val = __raw_readl(S3C64XX_NORMAL_CFG); __raw_readl 71 arch/arm/mach-s3c64xx/pm.c if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat) __raw_readl 251 arch/arm/mach-s3c64xx/pm.c tmp = __raw_readl(S3C64XX_PWR_CFG); __raw_readl 258 arch/arm/mach-s3c64xx/pm.c __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), __raw_readl 305 arch/arm/mach-s3c64xx/pm.c __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); __raw_readl 37 arch/arm/mach-s5pv210/pm.c return __raw_readl(S5P_EINT_WAKEUP_MASK); __raw_readl 76 arch/arm/mach-s5pv210/pm.c tmp = __raw_readl(S5P_SLEEP_CFG); __raw_readl 81 arch/arm/mach-s5pv210/pm.c tmp = __raw_readl(S5P_PWR_CFG); __raw_readl 87 arch/arm/mach-s5pv210/pm.c tmp = __raw_readl(S5P_OTHERS); __raw_readl 128 arch/arm/mach-s5pv210/pm.c __raw_readl(S5P_WAKEUP_STAT)); __raw_readl 67 arch/arm/mach-shmobile/platsmp-scu.c if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) __raw_readl 31 arch/arm/mach-shmobile/smp-sh73a0.c if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3) __raw_readl 64 arch/arm/mm/cache-b15-rac.c u32 val = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); __raw_readl 81 arch/arm/mm/cache-b15-rac.c reg = __raw_readl(b15_rac_base + rac_flush_offset); __raw_readl 352 arch/arm/mm/cache-b15-rac.c reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); __raw_readl 130 arch/arm/plat-pxa/mfp.c __raw_readl(mfpr_mmio_base + (off)) __raw_readl 142 arch/arm/plat-pxa/mfp.c #define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + mfpr_off_readback) __raw_readl 47 arch/arm/plat-samsung/gpio-samsung.c pup = __raw_readl(reg); __raw_readl 60 arch/arm/plat-samsung/gpio-samsung.c u32 pup = __raw_readl(reg); __raw_readl 113 arch/arm/plat-samsung/gpio-samsung.c u32 pup = __raw_readl(reg); __raw_readl 131 arch/arm/plat-samsung/gpio-samsung.c u32 pup = __raw_readl(reg); __raw_readl 190 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(reg); __raw_readl 213 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(chip->base); __raw_readl 253 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(reg); __raw_readl 283 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(reg); __raw_readl 321 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(reg); __raw_readl 346 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(chip->base); __raw_readl 437 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(base + 0x00); __raw_readl 457 arch/arm/plat-samsung/gpio-samsung.c dat = __raw_readl(base + 0x04); __raw_readl 463 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(base + 0x00); __raw_readl 497 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(base + GPIOCON_OFF); __raw_readl 517 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(base + GPIOCON_OFF); __raw_readl 521 arch/arm/plat-samsung/gpio-samsung.c dat = __raw_readl(base + GPIODAT_OFF); __raw_readl 572 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(regcon); __raw_readl 596 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(regcon); __raw_readl 600 arch/arm/plat-samsung/gpio-samsung.c dat = __raw_readl(base + GPIODAT_OFF); __raw_readl 635 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(base + 0x00); __raw_readl 636 arch/arm/plat-samsung/gpio-samsung.c dat = __raw_readl(base + 0x04); __raw_readl 664 arch/arm/plat-samsung/gpio-samsung.c dat = __raw_readl(base + 0x04); __raw_readl 678 arch/arm/plat-samsung/gpio-samsung.c val = __raw_readl(ourchip->base + 0x04); __raw_readl 1315 arch/arm/plat-samsung/gpio-samsung.c misccr = __raw_readl(S3C24XX_MISCCR); __raw_readl 67 arch/arm/plat-samsung/pm-debug.c save->ulcon = __raw_readl(regs + S3C2410_ULCON); __raw_readl 68 arch/arm/plat-samsung/pm-debug.c save->ucon = __raw_readl(regs + S3C2410_UCON); __raw_readl 69 arch/arm/plat-samsung/pm-debug.c save->ufcon = __raw_readl(regs + S3C2410_UFCON); __raw_readl 70 arch/arm/plat-samsung/pm-debug.c save->umcon = __raw_readl(regs + S3C2410_UMCON); __raw_readl 71 arch/arm/plat-samsung/pm-debug.c save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); __raw_readl 74 arch/arm/plat-samsung/pm-debug.c save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); __raw_readl 29 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); __raw_readl 30 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); __raw_readl 36 arch/arm/plat-samsung/pm-gpio.c u32 old_gpcon = __raw_readl(base + OFFS_CON); __raw_readl 37 arch/arm/plat-samsung/pm-gpio.c u32 old_gpdat = __raw_readl(base + OFFS_DAT); __raw_readl 66 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); __raw_readl 67 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); __raw_readl 68 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); __raw_readl 123 arch/arm/plat-samsung/pm-gpio.c u32 old_gpcon = __raw_readl(base + OFFS_CON); __raw_readl 124 arch/arm/plat-samsung/pm-gpio.c u32 old_gpdat = __raw_readl(base + OFFS_DAT); __raw_readl 194 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); __raw_readl 195 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); __raw_readl 196 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP); __raw_readl 199 arch/arm/plat-samsung/pm-gpio.c chip->pm_save[0] = __raw_readl(chip->base - 4); __raw_readl 244 arch/arm/plat-samsung/pm-gpio.c u32 old_gpcon = __raw_readl(con); __raw_readl 260 arch/arm/plat-samsung/pm-gpio.c u32 old_gpdat = __raw_readl(base + OFFS_DAT); __raw_readl 266 arch/arm/plat-samsung/pm-gpio.c old_gpcon[1] = __raw_readl(base + OFFS_CON); __raw_readl 270 arch/arm/plat-samsung/pm-gpio.c old_gpcon[0] = __raw_readl(base - 4); __raw_readl 287 arch/arm/plat-samsung/pm-gpio.c __raw_readl(base - 4), __raw_readl 288 arch/arm/plat-samsung/pm-gpio.c __raw_readl(base + OFFS_CON), __raw_readl 293 arch/arm/plat-samsung/pm-gpio.c __raw_readl(base + OFFS_CON), __raw_readl 23 arch/arm/plat-samsung/wakeup-mask.c val = __raw_readl(reg); __raw_readl 40 arch/arm/plat-samsung/wakeup-mask.c printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val); __raw_readl 71 arch/arm64/include/asm/io.h #define __raw_readl __raw_readl __raw_readl 121 arch/arm64/include/asm/io.h #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) __raw_readl 188 arch/arm64/include/asm/io.h #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; }) __raw_readl 32 arch/c6x/include/asm/soc.h #define soc_readl(addr) __raw_readl(addr) __raw_readl 23 arch/h8300/include/asm/io.h #define __raw_readl __raw_readl __raw_readl 168 arch/hexagon/include/asm/io.h #define readl_relaxed __raw_readl __raw_readl 40 arch/m68k/coldfire/dma_timer.c return __raw_readl(DTCN0); __raw_readl 79 arch/m68k/coldfire/dma_timer.c unsigned long cycl = __raw_readl(DTCN0); __raw_readl 64 arch/m68k/coldfire/intc-2.c val = __raw_readl(imraddr); __raw_readl 86 arch/m68k/coldfire/intc-2.c val = __raw_readl(imraddr); __raw_readl 72 arch/m68k/coldfire/intc.c imr = __raw_readl(MCFSIM_IMR); __raw_readl 79 arch/m68k/coldfire/intc.c imr = __raw_readl(MCFSIM_IMR); __raw_readl 86 arch/m68k/coldfire/intc.c imr = __raw_readl(MCFSIM_IMR); __raw_readl 72 arch/m68k/coldfire/pci.c __raw_readl(PCICAR); __raw_readl 83 arch/m68k/coldfire/pci.c *value = le32_to_cpu(__raw_readl(addr)); __raw_readl 88 arch/m68k/coldfire/pci.c __raw_readl(PCICAR); __raw_readl 104 arch/m68k/coldfire/pci.c __raw_readl(PCICAR); __raw_readl 120 arch/m68k/coldfire/pci.c __raw_readl(PCICAR); __raw_readl 107 arch/m68k/coldfire/sltimers.c scnt = __raw_readl(TA(MCFSLT_SCNT)); __raw_readl 109 arch/m68k/coldfire/sltimers.c if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) { __raw_readl 111 arch/m68k/coldfire/sltimers.c scnt = __raw_readl(TA(MCFSLT_SCNT)); __raw_readl 41 arch/m68k/coldfire/timers.c #define __raw_readtrr __raw_readl __raw_readl 77 arch/m68k/include/asm/io_no.h return __raw_readl(addr); __raw_readl 78 arch/m68k/include/asm/io_no.h return __le32_to_cpu(__raw_readl(addr)); __raw_readl 103 arch/m68k/include/asm/io_no.h #define readl __raw_readl __raw_readl 124 arch/m68k/include/asm/mcfgpio.h #define mcfgpio_read(port) __raw_readl(port) __raw_readl 52 arch/microblaze/include/asm/io.h #define in_be32(a) __raw_readl((const void __iomem __force *)(a)) __raw_readl 62 arch/microblaze/include/asm/io.h #define in_le32(a) __le32_to_cpu(__raw_readl(a)) __raw_readl 304 arch/mips/alchemy/common/clock.c v = __raw_readl(addr + AU1550_MEM_SDCONFIGB); __raw_readl 308 arch/mips/alchemy/common/clock.c v = __raw_readl(addr + AU1550_MEM_SDCONFIGB); __raw_readl 988 arch/mips/alchemy/common/dbdma.c alchemy_dbdma_pm_data[0][0] = __raw_readl(addr + 0x00); __raw_readl 989 arch/mips/alchemy/common/dbdma.c alchemy_dbdma_pm_data[0][1] = __raw_readl(addr + 0x04); __raw_readl 990 arch/mips/alchemy/common/dbdma.c alchemy_dbdma_pm_data[0][2] = __raw_readl(addr + 0x08); __raw_readl 991 arch/mips/alchemy/common/dbdma.c alchemy_dbdma_pm_data[0][3] = __raw_readl(addr + 0x0c); __raw_readl 996 arch/mips/alchemy/common/dbdma.c alchemy_dbdma_pm_data[i][0] = __raw_readl(addr + 0x00); __raw_readl 997 arch/mips/alchemy/common/dbdma.c alchemy_dbdma_pm_data[i][1] = __raw_readl(addr + 0x04); __raw_readl 998 arch/mips/alchemy/common/dbdma.c alchemy_dbdma_pm_data[i][2] = __raw_readl(addr + 0x08); __raw_readl 999 arch/mips/alchemy/common/dbdma.c alchemy_dbdma_pm_data[i][3] = __raw_readl(addr + 0x0c); __raw_readl 1000 arch/mips/alchemy/common/dbdma.c alchemy_dbdma_pm_data[i][4] = __raw_readl(addr + 0x10); __raw_readl 1001 arch/mips/alchemy/common/dbdma.c alchemy_dbdma_pm_data[i][5] = __raw_readl(addr + 0x14); __raw_readl 1006 arch/mips/alchemy/common/dbdma.c while (!(__raw_readl(addr + 0x14) & 1)) __raw_readl 144 arch/mips/alchemy/common/dma.c __raw_readl(chan->io + DMA_MODE_SET)); __raw_readl 146 arch/mips/alchemy/common/dma.c __raw_readl(chan->io + DMA_PERIPHERAL_ADDR)); __raw_readl 148 arch/mips/alchemy/common/dma.c __raw_readl(chan->io + DMA_BUFFER0_START)); __raw_readl 150 arch/mips/alchemy/common/dma.c __raw_readl(chan->io + DMA_BUFFER1_START)); __raw_readl 152 arch/mips/alchemy/common/dma.c __raw_readl(chan->io + DMA_BUFFER0_COUNT)); __raw_readl 154 arch/mips/alchemy/common/dma.c __raw_readl(chan->io + DMA_BUFFER1_COUNT)); __raw_readl 520 arch/mips/alchemy/common/irq.c l = __raw_readl(r + AU1300_GPIC_PINCFG); __raw_readl 586 arch/mips/alchemy/common/irq.c r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); __raw_readl 735 arch/mips/alchemy/common/irq.c d[0] = __raw_readl(base + IC_CFG0RD); __raw_readl 736 arch/mips/alchemy/common/irq.c d[1] = __raw_readl(base + IC_CFG1RD); __raw_readl 737 arch/mips/alchemy/common/irq.c d[2] = __raw_readl(base + IC_CFG2RD); __raw_readl 738 arch/mips/alchemy/common/irq.c d[3] = __raw_readl(base + IC_SRCRD); __raw_readl 739 arch/mips/alchemy/common/irq.c d[4] = __raw_readl(base + IC_ASSIGNRD); __raw_readl 740 arch/mips/alchemy/common/irq.c d[5] = __raw_readl(base + IC_WAKERD); __raw_readl 741 arch/mips/alchemy/common/irq.c d[6] = __raw_readl(base + IC_MASKRD); __raw_readl 784 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0); __raw_readl 785 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4); __raw_readl 786 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8); __raw_readl 787 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc); __raw_readl 790 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL); __raw_readl 802 arch/mips/alchemy/common/irq.c alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2)); __raw_readl 856 arch/mips/alchemy/common/irq.c unsigned long r = __raw_readl((void __iomem *)KSEG1ADDR(addr)); \ __raw_readl 870 arch/mips/alchemy/common/irq.c int i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC); __raw_readl 102 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL2); __raw_readl 103 arch/mips/alchemy/common/usb.c s = __raw_readl(base + USB_DWC_CTRL3); __raw_readl 131 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ __raw_readl 139 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); __raw_readl 148 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); __raw_readl 153 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); __raw_readl 168 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); __raw_readl 173 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); __raw_readl 180 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); __raw_readl 185 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); __raw_readl 190 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); __raw_readl 195 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); __raw_readl 209 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); __raw_readl 216 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); __raw_readl 221 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_INT_ENABLE); __raw_readl 226 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); __raw_readl 239 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); __raw_readl 244 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); __raw_readl 251 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL1); __raw_readl 256 arch/mips/alchemy/common/usb.c r = __raw_readl(base + USB_DWC_CTRL3); __raw_readl 318 arch/mips/alchemy/common/usb.c unsigned long r = __raw_readl(base + AU1200_USBCFG); __raw_readl 332 arch/mips/alchemy/common/usb.c unsigned long r = __raw_readl(base + AU1200_USBCFG); __raw_readl 348 arch/mips/alchemy/common/usb.c unsigned long r = __raw_readl(base + AU1200_USBCFG); __raw_readl 395 arch/mips/alchemy/common/usb.c unsigned long r = __raw_readl(base); __raw_readl 428 arch/mips/alchemy/common/usb.c unsigned long r = __raw_readl(base + creg); __raw_readl 446 arch/mips/alchemy/common/usb.c while (__raw_readl(base + creg), __raw_readl 447 arch/mips/alchemy/common/usb.c !(__raw_readl(base + creg) & USBHEN_RD)) __raw_readl 517 arch/mips/alchemy/common/usb.c alchemy_usb_pmdata[0] = __raw_readl(base + creg); __raw_readl 536 arch/mips/alchemy/common/usb.c alchemy_usb_pmdata[0] = __raw_readl(base + 0x00); __raw_readl 537 arch/mips/alchemy/common/usb.c alchemy_usb_pmdata[1] = __raw_readl(base + 0x04); __raw_readl 555 arch/mips/alchemy/common/usb.c alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4); __raw_readl 39 arch/mips/ath25/ar2315.c return __raw_readl(ar2315_rst_base + reg); __raw_readl 267 arch/mips/ath25/ar2315.c memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG); __raw_readl 40 arch/mips/ath25/ar5312.c return __raw_readl(ar5312_rst_base + reg); __raw_readl 191 arch/mips/ath25/ar5312.c ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0); __raw_readl 216 arch/mips/ath25/ar5312.c ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1); __raw_readl 219 arch/mips/ath25/ar5312.c ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2); __raw_readl 363 arch/mips/ath25/ar5312.c memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1); __raw_readl 34 arch/mips/ath25/board.c return __raw_readl(addr) != 0xffffffff; __raw_readl 40 arch/mips/ath25/board.c if (__raw_readl(addr) == ATH25_BD_MAGIC) __raw_readl 26 arch/mips/ath25/early_printk.c return __raw_readl(base + 4 * reg); __raw_readl 105 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); __raw_readl 131 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); __raw_readl 165 arch/mips/ath79/clock.c clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); __raw_readl 178 arch/mips/ath79/clock.c cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG); __raw_readl 253 arch/mips/ath79/clock.c pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); __raw_readl 257 arch/mips/ath79/clock.c pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); __raw_readl 265 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); __raw_readl 280 arch/mips/ath79/clock.c pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); __raw_readl 284 arch/mips/ath79/clock.c pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); __raw_readl 292 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); __raw_readl 307 arch/mips/ath79/clock.c clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); __raw_readl 343 arch/mips/ath79/clock.c clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); __raw_readl 368 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG); __raw_readl 382 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG); __raw_readl 396 arch/mips/ath79/clock.c clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG); __raw_readl 451 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG); __raw_readl 465 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG); __raw_readl 479 arch/mips/ath79/clock.c clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG); __raw_readl 544 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG); __raw_readl 550 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG); __raw_readl 563 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG); __raw_readl 568 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG); __raw_readl 581 arch/mips/ath79/clock.c clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG); __raw_readl 62 arch/mips/ath79/common.c while (__raw_readl(flush_reg) & 0x1) __raw_readl 67 arch/mips/ath79/common.c while (__raw_readl(flush_reg) & 0x1) __raw_readl 26 arch/mips/ath79/early_printk.c t = __raw_readl(reg); __raw_readl 95 arch/mips/ath79/early_printk.c t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC); __raw_readl 106 arch/mips/ath79/early_printk.c id = __raw_readl(base + AR71XX_RESET_REG_REV_ID); __raw_readl 78 arch/mips/bmips/dma.c cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); __raw_readl 80 arch/mips/bmips/dma.c __raw_readl(cbr + BMIPS_RAC_CONFIG); __raw_readl 93 arch/mips/bmips/setup.c if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED) __raw_readl 32 arch/mips/generic/board-ocelot.c rev = __raw_readl((void __iomem *)DEVCPU_GCB_CHIP_REGS_CHIP_ID); __raw_readl 39 arch/mips/generic/board-sead3.c rev = __raw_readl((void *)MIPS_REVISION); __raw_readl 57 arch/mips/generic/board-sead3.c cfg = __raw_readl((uint32_t *)SEAD_CONFIG); __raw_readl 499 arch/mips/include/asm/io.h be32_to_cpu(__raw_readl((__force unsigned *)(addr))) __raw_readl 161 arch/mips/include/asm/mach-ath79/ath79.h return __raw_readl(ath79_pll_base + reg); __raw_readl 167 arch/mips/include/asm/mach-ath79/ath79.h (void) __raw_readl(ath79_reset_base + reg); /* flush */ __raw_readl 172 arch/mips/include/asm/mach-ath79/ath79.h return __raw_readl(ath79_reset_base + reg); __raw_readl 605 arch/mips/include/asm/mach-au1x00/au1000.h return __raw_readl(b + regofs); __raw_readl 621 arch/mips/include/asm/mach-au1x00/au1000.h return __raw_readl(b + regofs); __raw_readl 729 arch/mips/include/asm/mach-au1x00/au1000.h if ((__raw_readl(addr + 0x100) & 3) != 3) { __raw_readl 755 arch/mips/include/asm/mach-au1x00/au1000.h if (__raw_readl(base + 0x1c) & 0x20) __raw_readl 202 arch/mips/include/asm/mach-au1x00/au1000_dma.h if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) __raw_readl 227 arch/mips/include/asm/mach-au1x00/au1000_dma.h return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0; __raw_readl 286 arch/mips/include/asm/mach-au1x00/au1000_dma.h return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0; __raw_readl 413 arch/mips/include/asm/mach-au1x00/au1000_dma.h return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1); __raw_readl 440 arch/mips/include/asm/mach-au1x00/au1000_dma.h curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? __raw_readl 443 arch/mips/include/asm/mach-au1x00/au1000_dma.h count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK; __raw_readl 288 arch/mips/include/asm/mach-au1x00/gpio-au1000.h unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR); __raw_readl 310 arch/mips/include/asm/mach-au1x00/gpio-au1000.h return __raw_readl(base + AU1000_GPIO2_PINSTATE) & __raw_readl 362 arch/mips/include/asm/mach-au1x00/gpio-au1000.h unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE); __raw_readl 37 arch/mips/include/asm/mach-au1x00/gpio-au1300.h return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit; __raw_readl 119 arch/mips/include/asm/mach-au1x00/gpio-au1300.h v = __raw_readl(roff + AU1300_GPIC_RSTVAL); __raw_readl 14 arch/mips/include/asm/mach-lantiq/lantiq.h #define ltq_r32(reg) __raw_readl(reg) __raw_readl 42 arch/mips/include/asm/mach-ralink/ralink_regs.h return __raw_readl(rt_sysc_membase + reg); __raw_readl 59 arch/mips/include/asm/mach-ralink/ralink_regs.h return __raw_readl(rt_memc_membase + reg); __raw_readl 29 arch/mips/include/asm/mach-rc32434/dma_v.h if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { __raw_readl 32 arch/mips/include/asm/mach-rc32434/dma_v.h if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) { __raw_readl 29 arch/mips/include/asm/mips-cps.h return __raw_readl(addr_##unit##_##name()); \ __raw_readl 35 arch/mips/include/asm/mips-cps.h val64 = __raw_readl(addr_##unit##_##name() + 4); \ __raw_readl 37 arch/mips/include/asm/mips-cps.h val64 |= __raw_readl(addr_##unit##_##name()); \ __raw_readl 57 arch/mips/include/asm/mips-gic.h return __raw_readl(addr_gic_##name(intr)); \ __raw_readl 102 arch/mips/include/asm/mips-gic.h val = __raw_readl(addr) >> intr % 32; \ __raw_readl 142 arch/mips/include/asm/mips-gic.h _val = __raw_readl(addr); \ __raw_readl 816 arch/mips/include/asm/pci/bridge.h #define bridge_read(bc, reg) __raw_readl(&bc->base->reg) __raw_readl 819 arch/mips/include/asm/pci/bridge.h __raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg) __raw_readl 821 arch/mips/include/asm/pci/bridge.h __raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg) __raw_readl 168 arch/mips/include/asm/vdso/gettimeofday.h hi = __raw_readl(gic + sizeof(lo)); __raw_readl 169 arch/mips/include/asm/vdso/gettimeofday.h lo = __raw_readl(gic); __raw_readl 170 arch/mips/include/asm/vdso/gettimeofday.h hi2 = __raw_readl(gic + sizeof(lo)); __raw_readl 34 arch/mips/kernel/cevt-txx9.c return __raw_readl(&txx9_cs->tmrptr->trr); __raw_readl 52 arch/mips/kernel/cevt-txx9.c return __raw_readl(&txx9_clocksource.tmrptr->trr); __raw_readl 21 arch/mips/kernel/gpio_txx9.c return !!(__raw_readl(&txx9_pioptr->din) & (1 << offset)); __raw_readl 27 arch/mips/kernel/gpio_txx9.c val = __raw_readl(&txx9_pioptr->dout); __raw_readl 49 arch/mips/kernel/gpio_txx9.c __raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset), __raw_readl 62 arch/mips/kernel/gpio_txx9.c __raw_writel(__raw_readl(&txx9_pioptr->dir) | (1 << offset), __raw_readl 72 arch/mips/kernel/irq_txx9.c __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) __raw_readl 88 arch/mips/kernel/irq_txx9.c __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) __raw_readl 96 arch/mips/kernel/irq_txx9.c __raw_readl(&txx9_ircptr->ssr); __raw_readl 131 arch/mips/kernel/irq_txx9.c cr = __raw_readl(crp); __raw_readl 186 arch/mips/kernel/irq_txx9.c u32 csr = __raw_readl(&txx9_ircptr->csr); __raw_readl 600 arch/mips/kernel/smp-bmips.c cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); __raw_readl 602 arch/mips/kernel/smp-bmips.c __raw_readl(cbr + BMIPS_RAC_CONFIG); __raw_readl 604 arch/mips/kernel/smp-bmips.c cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); __raw_readl 606 arch/mips/kernel/smp-bmips.c __raw_readl(cbr + BMIPS_RAC_CONFIG); __raw_readl 608 arch/mips/kernel/smp-bmips.c cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); __raw_readl 610 arch/mips/kernel/smp-bmips.c __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); __raw_readl 620 arch/mips/kernel/smp-bmips.c cfg = __raw_readl(cbr + BMIPS_L2_CONFIG); __raw_readl 622 arch/mips/kernel/smp-bmips.c __raw_readl(cbr + BMIPS_L2_CONFIG); __raw_readl 28 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) __raw_readl 37 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) __raw_readl 46 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) __raw_readl 48 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) __raw_readl 57 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) __raw_readl 68 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) __raw_readl 70 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) __raw_readl 74 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) __raw_readl 76 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) __raw_readl 80 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) __raw_readl 82 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) __raw_readl 86 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) __raw_readl 88 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) __raw_readl 92 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) __raw_readl 94 arch/mips/loongson32/common/irq.c __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) __raw_readl 120 arch/mips/loongson32/common/irq.c int_status = __raw_readl(LS1X_INTC_INTISR(n)) & __raw_readl 121 arch/mips/loongson32/common/irq.c __raw_readl(LS1X_INTC_INTIEN(n)); __raw_readl 94 arch/mips/loongson32/common/platform.c val = __raw_readl(LS1X_MUX_CTRL1); __raw_readl 99 arch/mips/loongson32/common/platform.c __raw_writel(__raw_readl(LS1X_MUX_CTRL0) | GMAC1_USE_UART1 | __raw_readl 138 arch/mips/loongson32/common/platform.c val = __raw_readl(LS1X_MUX_CTRL0); __raw_readl 286 arch/mips/loongson32/common/platform.c u32 val = __raw_readl(LS1X_RTC_CTRL); __raw_readl 86 arch/mips/loongson32/common/time.c count = __raw_readl(timer_reg_base + PWM_CNT); __raw_readl 149 arch/mips/loongson32/common/time.c __raw_writel(__raw_readl(timer_reg_base + PWM_CTRL) & ~CNT_EN, __raw_readl 245 arch/mips/mti-malta/malta-dtshim.c sc_cfg = __raw_readl(biu_base + MSC01_SC_CFG_OFS); __raw_readl 73 arch/mips/mti-malta/malta-int.c irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); __raw_readl 121 arch/mips/mti-malta/malta-setup.c cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); __raw_readl 151 arch/mips/mti-malta/malta-setup.c int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; __raw_readl 301 arch/mips/paravirt/paravirt-irq.c num_bits = __raw_readl(mips_irq_chip + MIPS_IRQ_CHIP_NUM_BITS); __raw_readl 330 arch/mips/paravirt/paravirt-irq.c en = __raw_readl(mips_irq_chip + mips_irq_chip_reg_src + __raw_readl 334 arch/mips/paravirt/paravirt-irq.c en = __raw_readl(mips_irq_chip + mips_irq_chip_reg_src + (cpuid * mips_irq_cpu_stride) + sizeof(u32)); __raw_readl 112 arch/mips/pci/ops-bcm63xx.c data = le32_to_cpu(__raw_readl(pci_iospace_start)); __raw_readl 134 arch/mips/pci/ops-bcm63xx.c data = le32_to_cpu(__raw_readl(pci_iospace_start)); __raw_readl 69 arch/mips/pci/ops-tx4927.c __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) __raw_readl 80 arch/mips/pci/ops-tx4927.c while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) __raw_readl 82 arch/mips/pci/ops-tx4927.c if (__raw_readl(&pcicptr->pcistatus) __raw_readl 84 arch/mips/pci/ops-tx4927.c __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) __raw_readl 110 arch/mips/pci/ops-tx4927.c return __raw_readl(&pcicptr->g2pcfgdata); __raw_readl 230 arch/mips/pci/ops-tx4927.c __raw_readl(&pcicptr->pciid) >> 16, __raw_readl 231 arch/mips/pci/ops-tx4927.c __raw_readl(&pcicptr->pciid) & 0xffff, __raw_readl 232 arch/mips/pci/ops-tx4927.c __raw_readl(&pcicptr->pciccrev) & 0xff, __raw_readl 239 arch/mips/pci/ops-tx4927.c __raw_writel(__raw_readl(&pcicptr->pciccfg) __raw_readl 307 arch/mips/pci/ops-tx4927.c __raw_writel(__raw_readl(&pcicptr->pciccfg) __raw_readl 312 arch/mips/pci/ops-tx4927.c __raw_writel(__raw_readl(&pcicptr->pciccfg) __raw_readl 316 arch/mips/pci/ops-tx4927.c __raw_writel(__raw_readl(&pcicptr->pciccfg) __raw_readl 323 arch/mips/pci/ops-tx4927.c __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff) __raw_readl 337 arch/mips/pci/ops-tx4927.c __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) __raw_readl 359 arch/mips/pci/ops-tx4927.c __raw_readl(&pcicptr->pcistatus) & 0xffff, __raw_readl 360 arch/mips/pci/ops-tx4927.c __raw_readl(&pcicptr->pcimask) & 0xffff, __raw_readl 361 arch/mips/pci/ops-tx4927.c __raw_readl(&pcicptr->g2ptocnt) & 0xff, __raw_readl 362 arch/mips/pci/ops-tx4927.c (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8, __raw_readl 363 arch/mips/pci/ops-tx4927.c (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff); __raw_readl 368 arch/mips/pci/ops-tx4927.c __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16); __raw_readl 369 arch/mips/pci/ops-tx4927.c __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus); __raw_readl 370 arch/mips/pci/ops-tx4927.c __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus); __raw_readl 453 arch/mips/pci/ops-tx4927.c printk(KERN_CONT " %08x", __raw_readl(preg)); __raw_readl 481 arch/mips/pci/ops-tx4927.c __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) __raw_readl 501 arch/mips/pci/ops-tx4927.c if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) { __raw_readl 518 arch/mips/pci/ops-tx4927.c __raw_readl(&pcicptr->pbareqport)); __raw_readl 114 arch/mips/pci/pci-alchemy.c r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; __raw_readl 157 arch/mips/pci/pci-alchemy.c *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); __raw_readl 164 arch/mips/pci/pci-alchemy.c status = __raw_readl(ctx->regs + PCI_REG_STATCMD); __raw_readl 313 arch/mips/pci/pci-alchemy.c ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); __raw_readl 314 arch/mips/pci/pci-alchemy.c ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; __raw_readl 315 arch/mips/pci/pci-alchemy.c ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); __raw_readl 316 arch/mips/pci/pci-alchemy.c ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); __raw_readl 317 arch/mips/pci/pci-alchemy.c ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); __raw_readl 318 arch/mips/pci/pci-alchemy.c ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); __raw_readl 319 arch/mips/pci/pci-alchemy.c ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); __raw_readl 320 arch/mips/pci/pci-alchemy.c ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); __raw_readl 321 arch/mips/pci/pci-alchemy.c ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); __raw_readl 322 arch/mips/pci/pci-alchemy.c ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); __raw_readl 323 arch/mips/pci/pci-alchemy.c ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); __raw_readl 324 arch/mips/pci/pci-alchemy.c ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); __raw_readl 435 arch/mips/pci/pci-alchemy.c val = __raw_readl(ctx->regs + PCI_REG_CONFIG); __raw_readl 473 arch/mips/pci/pci-alchemy.c val = __raw_readl(ctx->regs + PCI_REG_CONFIG); __raw_readl 192 arch/mips/pci/pci-ar2315.c return __raw_readl(apc->mmr_mem + reg); __raw_readl 233 arch/mips/pci/pci-ar2315.c value = __raw_readl(apc->cfg_mem + addr); __raw_readl 113 arch/mips/pci/pci-ar71xx.c pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; __raw_readl 118 arch/mips/pci/pci-ar71xx.c addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); __raw_readl 127 arch/mips/pci/pci-ar71xx.c ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; __raw_readl 132 arch/mips/pci/pci-ar71xx.c addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); __raw_readl 193 arch/mips/pci/pci-ar71xx.c data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); __raw_readl 234 arch/mips/pci/pci-ar71xx.c pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & __raw_readl 235 arch/mips/pci/pci-ar71xx.c __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); __raw_readl 263 arch/mips/pci/pci-ar71xx.c t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); __raw_readl 267 arch/mips/pci/pci-ar71xx.c __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); __raw_readl 280 arch/mips/pci/pci-ar71xx.c t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); __raw_readl 284 arch/mips/pci/pci-ar71xx.c __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); __raw_readl 60 arch/mips/pci/pci-ar724x.c reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); __raw_readl 86 arch/mips/pci/pci-ar724x.c data = __raw_readl(base + (where & ~3)); __raw_readl 108 arch/mips/pci/pci-ar724x.c __raw_readl(base + (where & ~3)); __raw_readl 128 arch/mips/pci/pci-ar724x.c data = __raw_readl(base + (where & ~3)); __raw_readl 197 arch/mips/pci/pci-ar724x.c data = __raw_readl(base + (where & ~3)); __raw_readl 219 arch/mips/pci/pci-ar724x.c __raw_readl(base + (where & ~3)); __raw_readl 238 arch/mips/pci/pci-ar724x.c pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & __raw_readl 239 arch/mips/pci/pci-ar724x.c __raw_readl(base + AR724X_PCI_REG_INT_MASK); __raw_readl 261 arch/mips/pci/pci-ar724x.c t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); __raw_readl 265 arch/mips/pci/pci-ar724x.c __raw_readl(base + AR724X_PCI_REG_INT_MASK); __raw_readl 282 arch/mips/pci/pci-ar724x.c t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); __raw_readl 287 arch/mips/pci/pci-ar724x.c __raw_readl(base + AR724X_PCI_REG_INT_MASK); __raw_readl 289 arch/mips/pci/pci-ar724x.c t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); __raw_readl 294 arch/mips/pci/pci-ar724x.c __raw_readl(base + AR724X_PCI_REG_INT_STATUS); __raw_readl 349 arch/mips/pci/pci-ar724x.c app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP); __raw_readl 33 arch/mips/pic32/common/reset.c (void)__raw_readl(reg); __raw_readl 45 arch/mips/pic32/pic32mzda/early_clk.c osccon = __raw_readl(osc_base + OSCCON); __raw_readl 46 arch/mips/pic32/pic32mzda/early_clk.c spllcon = __raw_readl(osc_base + SPLLCON); __raw_readl 91 arch/mips/pic32/pic32mzda/early_clk.c u32 pbdiv = (__raw_readl(osc_base + pbxdiv) & PB_MASK) + 1; __raw_readl 156 arch/mips/pic32/pic32mzda/early_console.c while (__raw_readl( __raw_readl 39 arch/mips/pistachio/init.c core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG); __raw_readl 71 arch/mips/pmcs-msp71xx/msp_irq_cic.c dummy_read = __raw_readl(cic_mem); __raw_readl 42 arch/mips/pmcs-msp71xx/msp_irq_per.c dummy_read = __raw_readl(per_mem); __raw_readl 42 arch/mips/ralink/early_printk.c return __raw_readl(uart_membase + reg); __raw_readl 48 arch/mips/ralink/early_printk.c (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1); __raw_readl 66 arch/mips/ralink/irq.c return __raw_readl(rt_intc_membase + rt_intc_regs[reg]); __raw_readl 654 arch/mips/ralink/mt7620.c n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); __raw_readl 655 arch/mips/ralink/mt7620.c n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); __raw_readl 656 arch/mips/ralink/mt7620.c rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); __raw_readl 670 arch/mips/ralink/mt7620.c u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); __raw_readl 690 arch/mips/ralink/mt7620.c cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); __raw_readl 706 arch/mips/ralink/mt7620.c pmu0 = __raw_readl(sysc + PMU0_CFG); __raw_readl 707 arch/mips/ralink/mt7620.c pmu1 = __raw_readl(sysc + PMU1_CFG); __raw_readl 193 arch/mips/ralink/mt7621.c n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); __raw_readl 194 arch/mips/ralink/mt7621.c n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); __raw_readl 203 arch/mips/ralink/mt7621.c rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); __raw_readl 88 arch/mips/ralink/rt288x.c n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); __raw_readl 89 arch/mips/ralink/rt288x.c n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); __raw_readl 90 arch/mips/ralink/rt288x.c id = __raw_readl(sysc + SYSC_REG_CHIP_ID); __raw_readl 102 arch/mips/ralink/rt305x.c t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG); __raw_readl 225 arch/mips/ralink/rt305x.c n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); __raw_readl 226 arch/mips/ralink/rt305x.c n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); __raw_readl 257 arch/mips/ralink/rt305x.c id = __raw_readl(sysc + SYSC_REG_CHIP_ID); __raw_readl 124 arch/mips/ralink/rt3883.c n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3); __raw_readl 125 arch/mips/ralink/rt3883.c n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7); __raw_readl 126 arch/mips/ralink/rt3883.c id = __raw_readl(sysc + RT3883_SYSC_REG_REVID); __raw_readl 44 arch/mips/ralink/timer.c return __raw_readl(rt->membase + reg); __raw_readl 59 arch/mips/rb532/setup.c val = __raw_readl(&pci_reg->pcic); __raw_readl 36 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \ __raw_readl 37 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ __raw_readl 38 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \ __raw_readl 40 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \ __raw_readl 41 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) __raw_readl 45 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ __raw_readl 46 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \ __raw_readl 47 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \ __raw_readl 48 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) __raw_readl 64 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); __raw_readl 66 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); __raw_readl 67 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); __raw_readl 69 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); __raw_readl 74 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); __raw_readl 82 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ctrl) & ~EEPROM_EPROT, ctrl); __raw_readl 88 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); __raw_readl 90 arch/mips/sgi-ip22/ip22-nvram.c __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); __raw_readl 93 arch/mips/sgi-ip22/ip22-nvram.c if (__raw_readl(ctrl) & EEPROM_DATI) __raw_readl 66 arch/mips/txx9/generic/irq_tx4939.c __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) __raw_readl 84 arch/mips/txx9/generic/irq_tx4939.c __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) __raw_readl 138 arch/mips/txx9/generic/irq_tx4939.c cr = __raw_readl(crp); __raw_readl 211 arch/mips/txx9/generic/irq_tx4939.c u32 csr = __raw_readl(&tx4939_ircptr->cs.r); __raw_readl 481 arch/mips/txx9/generic/setup.c while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) & __raw_readl 46 arch/nds32/include/asm/io.h #define __raw_readl __raw_readl __raw_readl 66 arch/nds32/include/asm/io.h #define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; }) __raw_readl 35 arch/parisc/include/asm/ide.h *(u32 *)addr = __raw_readl(port); __raw_readl 190 arch/parisc/include/asm/io.h return le32_to_cpu((__le32 __force) __raw_readl(addr)); __raw_readl 80 arch/parisc/lib/io.c *(u32 *)dst = __raw_readl(src); __raw_readl 175 arch/parisc/lib/iomap.c return __raw_readl(addr); __raw_readl 242 arch/parisc/lib/iomap.c *(u32 *)dst = __raw_readl(addr); __raw_readl 334 arch/powerpc/platforms/maple/setup.c rev = __raw_readl(mem); __raw_readl 2492 arch/powerpc/platforms/powermac/feature.c if (__raw_readl(mach_id_ptr) & 0x20000000UL) __raw_readl 76 arch/riscv/include/asm/io.h #define __raw_readl __raw_readl __raw_readl 103 arch/riscv/include/asm/io.h #define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) __raw_readl 32 arch/sh/boards/board-magicpanelr2.c #define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL) __raw_readl 65 arch/sh/boards/mach-cayman/irq.c mask = __raw_readl(reg); __raw_readl 83 arch/sh/boards/mach-cayman/irq.c mask = __raw_readl(reg); __raw_readl 103 arch/sh/boards/mach-cayman/irq.c status = __raw_readl(EPLD_STATUS_BASE) & __raw_readl 104 arch/sh/boards/mach-cayman/irq.c __raw_readl(EPLD_MASK_BASE) & 0xff; __raw_readl 120 arch/sh/boards/mach-cayman/irq.c status = __raw_readl(EPLD_STATUS_BASE + 3 * sizeof(u32)) & __raw_readl 121 arch/sh/boards/mach-cayman/irq.c __raw_readl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff; __raw_readl 39 arch/sh/boards/mach-dreamcast/rtc.c val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | __raw_readl 40 arch/sh/boards/mach-dreamcast/rtc.c (__raw_readl(AICA_RTC_SECS_L) & 0xffff); __raw_readl 42 arch/sh/boards/mach-dreamcast/rtc.c val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | __raw_readl 43 arch/sh/boards/mach-dreamcast/rtc.c (__raw_readl(AICA_RTC_SECS_L) & 0xffff); __raw_readl 71 arch/sh/boards/mach-dreamcast/rtc.c val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | __raw_readl 72 arch/sh/boards/mach-dreamcast/rtc.c (__raw_readl(AICA_RTC_SECS_L) & 0xffff); __raw_readl 74 arch/sh/boards/mach-dreamcast/rtc.c val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | __raw_readl 75 arch/sh/boards/mach-dreamcast/rtc.c (__raw_readl(AICA_RTC_SECS_L) & 0xffff); __raw_readl 107 arch/sh/boards/mach-landisk/gio.c data = __raw_readl(addr); __raw_readl 98 arch/sh/boards/mach-microdev/irq.c priorities = __raw_readl(priorityReg); __raw_readl 484 arch/sh/boards/mach-migor/setup.c __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR); __raw_readl 31 arch/sh/boards/mach-sh7763rdp/irq.c __raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000, __raw_readl 204 arch/sh/boards/mach-sh7763rdp/setup.c __raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1); __raw_readl 222 arch/sh/boards/mach-x3proto/setup.c __raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000); __raw_readl 42 arch/sh/boot/romimage/mmcif-sh7724.c __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); __raw_readl 75 arch/sh/boot/romimage/mmcif-sh7724.c __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); __raw_readl 40 arch/sh/drivers/dma/dma-pvr2.c if (__raw_readl(PVR2_DMA_MODE) != 0) __raw_readl 93 arch/sh/drivers/dma/dma-sh.c u32 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); __raw_readl 111 arch/sh/drivers/dma/dma-sh.c chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); __raw_readl 162 arch/sh/drivers/dma/dma-sh.c chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); __raw_readl 186 arch/sh/drivers/dma/dma-sh.c chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); __raw_readl 234 arch/sh/drivers/dma/dma-sh.c if (!(__raw_readl(dma_base_addr(chan->chan) + CHCR) & CHCR_DE)) __raw_readl 237 arch/sh/drivers/dma/dma-sh.c return __raw_readl(dma_base_addr(chan->chan) + TCR) __raw_readl 89 arch/sh/drivers/dma/dmabrg.c dcr = __raw_readl(DMABRGCR); __raw_readl 112 arch/sh/drivers/dma/dmabrg.c dcr = __raw_readl(DMABRGCR); __raw_readl 120 arch/sh/drivers/dma/dmabrg.c dcr = __raw_readl(DMABRGCR); __raw_readl 173 arch/sh/drivers/dma/dmabrg.c or = __raw_readl(DMAOR); __raw_readl 43 arch/sh/drivers/pci/fixups-landisk.c bcr1 = __raw_readl(SH7751_BCR1); __raw_readl 47 arch/sh/drivers/pci/fixups-landisk.c mcr = __raw_readl(SH7751_MCR); __raw_readl 43 arch/sh/drivers/pci/fixups-rts7751r2d.c bcr1 = __raw_readl(SH7751_BCR1); __raw_readl 54 arch/sh/drivers/pci/fixups-rts7751r2d.c mcr = __raw_readl(SH7751_MCR); __raw_readl 179 arch/sh/drivers/pci/pci-sh4.h return __raw_readl(chan->reg_base + reg); __raw_readl 92 arch/sh/drivers/pci/pci-sh5.h #define SH5PCI_READ(reg) __raw_readl(PCISH5_ICR_REG(reg)) __raw_readl 24 arch/sh/drivers/pci/pci-sh7751.c word = __raw_readl(SH7751_BCR1); __raw_readl 94 arch/sh/drivers/pci/pci-sh7751.c reg = __raw_readl(SH7751_BCR1); __raw_readl 156 arch/sh/drivers/pci/pci-sh7751.c word = __raw_readl(SH7751_WCR1); __raw_readl 158 arch/sh/drivers/pci/pci-sh7751.c word = __raw_readl(SH7751_WCR2); __raw_readl 160 arch/sh/drivers/pci/pci-sh7751.c word = __raw_readl(SH7751_WCR3); __raw_readl 162 arch/sh/drivers/pci/pci-sh7751.c word = __raw_readl(SH7751_MCR); __raw_readl 100 arch/sh/drivers/pci/pci-sh7780.c addr = __raw_readl(hose->reg_base + SH4_PCIALR); __raw_readl 119 arch/sh/drivers/pci/pci-sh7780.c status = __raw_readl(hose->reg_base + SH4_PCIAINT); __raw_readl 132 arch/sh/drivers/pci/pci-sh7780.c status = __raw_readl(hose->reg_base + SH4_PCIINT); __raw_readl 229 arch/sh/drivers/pci/pci-sh7780.c tmp = __raw_readl(hose->reg_base + SH4_PCICR); __raw_readl 239 arch/sh/drivers/pci/pci-sh7780.c tmp = __raw_readl(hose->reg_base + SH4_PCICR); __raw_readl 574 arch/sh/drivers/pci/pcie-sh7786.h return __raw_readl(chan->reg_base + reg); __raw_readl 134 arch/sh/drivers/superhyway/ops-sh4-202.c vcrh = __raw_readl(base); __raw_readl 135 arch/sh/drivers/superhyway/ops-sh4-202.c vcrl = __raw_readl(base + sizeof(u32)); __raw_readl 42 arch/sh/include/asm/io.h #define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; }) __raw_readl 177 arch/sh/include/asm/mmu_context.h cr = __raw_readl(MMUCR); __raw_readl 22 arch/sh/include/asm/mmu_context_32.h return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK; __raw_readl 58 arch/sh/include/asm/mmu_context_32.h return (pgd_t *)__raw_readl(MMU_TTB); __raw_readl 69 arch/sh/include/asm/watchdog.h return __raw_readl(WTCNT_R); __raw_readl 102 arch/sh/include/asm/watchdog.h return __raw_readl(WTCSR_R); __raw_readl 135 arch/sh/include/cpu-sh4/cpu/sh7786.h return __raw_readl((const volatile void __iomem *)0xFC400020) & 0x7; __raw_readl 21 arch/sh/include/mach-common/mach/magicpanelr2.h #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) __raw_readl 24 arch/sh/include/mach-common/mach/magicpanelr2.h #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg) __raw_readl 62 arch/sh/kernel/cpu/init.c __raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); __raw_readl 65 arch/sh/kernel/cpu/init.c (void)__raw_readl(CPUOPM); __raw_readl 80 arch/sh/kernel/cpu/init.c unsigned long expmask = __raw_readl(EXPMASK); __raw_readl 112 arch/sh/kernel/cpu/init.c ccr = __raw_readl(SH_CCR); __raw_readl 105 arch/sh/kernel/cpu/sh2/smp-j2.c return __raw_readl(sh2_cpuid_addr); __raw_readl 121 arch/sh/kernel/cpu/sh2/smp-j2.c val = __raw_readl(j2_ipi_trigger + cpu); __raw_readl 30 arch/sh/kernel/cpu/sh3/probe.c data0 = __raw_readl(addr0); __raw_readl 32 arch/sh/kernel/cpu/sh3/probe.c data1 = __raw_readl(addr1); __raw_readl 36 arch/sh/kernel/cpu/sh3/probe.c data0 = __raw_readl(addr0); __raw_readl 39 arch/sh/kernel/cpu/sh3/probe.c data1 = __raw_readl(addr1); __raw_readl 42 arch/sh/kernel/cpu/sh3/probe.c data3 = __raw_readl(addr0); __raw_readl 24 arch/sh/kernel/cpu/sh4/clock-sh4-202.c int idx = __raw_readl(CPG2_FRQCR3) & 0x0007; __raw_readl 52 arch/sh/kernel/cpu/sh4/clock-sh4-202.c int idx = (__raw_readl(CPG2_FRQCR3) >> 3) & 0x0007; __raw_readl 90 arch/sh/kernel/cpu/sh4/clock-sh4-202.c int idx = (__raw_readl(CPG2_FRQCR3) >> 6) & 0x0007; __raw_readl 120 arch/sh/kernel/cpu/sh4/clock-sh4-202.c frqcr3 = __raw_readl(CPG2_FRQCR3); __raw_readl 204 arch/sh/kernel/cpu/sh4/perf_event.c return (u64)((u64)(__raw_readl(PMCTRH(idx)) & 0xffff) << 32) | __raw_readl 205 arch/sh/kernel/cpu/sh4/perf_event.c __raw_readl(PMCTRL(idx)); __raw_readl 28 arch/sh/kernel/cpu/sh4/probe.c pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff; __raw_readl 29 arch/sh/kernel/cpu/sh4/probe.c prr = (__raw_readl(CCN_PRR) >> 4) & 0xff; __raw_readl 30 arch/sh/kernel/cpu/sh4/probe.c cvr = (__raw_readl(CCN_CVR)); __raw_readl 44 arch/sh/kernel/cpu/sh4/sq.c (void)__raw_readl(P4SEG_STORE_QUE); \ __raw_readl 44 arch/sh/kernel/cpu/sh4a/clock-sh7343.c if (__raw_readl(PLLCR) & 0x1000) __raw_readl 45 arch/sh/kernel/cpu/sh4a/clock-sh7343.c mult = __raw_readl(DLLFRQ); __raw_readl 66 arch/sh/kernel/cpu/sh4a/clock-sh7343.c if (__raw_readl(PLLCR) & 0x4000) __raw_readl 67 arch/sh/kernel/cpu/sh4a/clock-sh7343.c mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); __raw_readl 257 arch/sh/kernel/cpu/sh4a/clock-sh7343.c if (__raw_readl(PLLCR) & 0x1000) __raw_readl 44 arch/sh/kernel/cpu/sh4a/clock-sh7366.c if (__raw_readl(PLLCR) & 0x1000) __raw_readl 45 arch/sh/kernel/cpu/sh4a/clock-sh7366.c mult = __raw_readl(DLLFRQ); __raw_readl 67 arch/sh/kernel/cpu/sh4a/clock-sh7366.c if (__raw_readl(PLLCR) & 0x4000) __raw_readl 68 arch/sh/kernel/cpu/sh4a/clock-sh7366.c mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); __raw_readl 250 arch/sh/kernel/cpu/sh4a/clock-sh7366.c if (__raw_readl(PLLCR) & 0x1000) __raw_readl 47 arch/sh/kernel/cpu/sh4a/clock-sh7722.c if (__raw_readl(PLLCR) & 0x1000) __raw_readl 48 arch/sh/kernel/cpu/sh4a/clock-sh7722.c mult = __raw_readl(DLLFRQ); __raw_readl 70 arch/sh/kernel/cpu/sh4a/clock-sh7722.c if (__raw_readl(PLLCR) & 0x4000) __raw_readl 71 arch/sh/kernel/cpu/sh4a/clock-sh7722.c mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); __raw_readl 225 arch/sh/kernel/cpu/sh4a/clock-sh7722.c if (__raw_readl(PLLCR) & 0x1000) __raw_readl 48 arch/sh/kernel/cpu/sh4a/clock-sh7723.c if (__raw_readl(PLLCR) & 0x1000) __raw_readl 49 arch/sh/kernel/cpu/sh4a/clock-sh7723.c mult = __raw_readl(DLLFRQ); __raw_readl 71 arch/sh/kernel/cpu/sh4a/clock-sh7723.c if (__raw_readl(PLLCR) & 0x4000) __raw_readl 72 arch/sh/kernel/cpu/sh4a/clock-sh7723.c mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); __raw_readl 273 arch/sh/kernel/cpu/sh4a/clock-sh7723.c if (__raw_readl(PLLCR) & 0x1000) __raw_readl 52 arch/sh/kernel/cpu/sh4a/clock-sh7724.c if (__raw_readl(PLLCR) & 0x1000) __raw_readl 53 arch/sh/kernel/cpu/sh4a/clock-sh7724.c mult = __raw_readl(FLLFRQ) & 0x3ff; __raw_readl 55 arch/sh/kernel/cpu/sh4a/clock-sh7724.c if (__raw_readl(FLLFRQ) & 0x4000) __raw_readl 75 arch/sh/kernel/cpu/sh4a/clock-sh7724.c if (__raw_readl(PLLCR) & 0x4000) __raw_readl 76 arch/sh/kernel/cpu/sh4a/clock-sh7724.c mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; __raw_readl 131 arch/sh/kernel/cpu/sh4a/clock-sh7724.c value = __raw_readl(FRQCRA); __raw_readl 347 arch/sh/kernel/cpu/sh4a/clock-sh7724.c if (__raw_readl(PLLCR) & 0x1000) __raw_readl 30 arch/sh/kernel/cpu/sh4a/clock-sh7734.c u32 r = __raw_readl(MODEMR); __raw_readl 24 arch/sh/kernel/cpu/sh4a/clock-sh7763.c clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; __raw_readl 33 arch/sh/kernel/cpu/sh4a/clock-sh7763.c int idx = ((__raw_readl(FRQCR) >> 4) & 0x07); __raw_readl 43 arch/sh/kernel/cpu/sh4a/clock-sh7763.c int idx = ((__raw_readl(FRQCR) >> 16) & 0x07); __raw_readl 70 arch/sh/kernel/cpu/sh4a/clock-sh7763.c int idx = ((__raw_readl(FRQCR) >> 20) & 0x07); __raw_readl 21 arch/sh/kernel/cpu/sh4a/clock-sh7770.c clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; __raw_readl 30 arch/sh/kernel/cpu/sh4a/clock-sh7770.c int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); __raw_readl 40 arch/sh/kernel/cpu/sh4a/clock-sh7770.c int idx = (__raw_readl(FRQCR) & 0x000f); __raw_readl 50 arch/sh/kernel/cpu/sh4a/clock-sh7770.c int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f); __raw_readl 24 arch/sh/kernel/cpu/sh4a/clock-sh7780.c clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; __raw_readl 33 arch/sh/kernel/cpu/sh4a/clock-sh7780.c int idx = (__raw_readl(FRQCR) & 0x0003); __raw_readl 43 arch/sh/kernel/cpu/sh4a/clock-sh7780.c int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); __raw_readl 53 arch/sh/kernel/cpu/sh4a/clock-sh7780.c int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); __raw_readl 76 arch/sh/kernel/cpu/sh4a/clock-sh7780.c int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007); __raw_readl 18 arch/sh/kernel/cpu/sh4a/intc-shx3.c return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE; __raw_readl 229 arch/sh/kernel/cpu/sh4a/perf_event.c return __raw_readl(PPC_PMCTR(idx)); __raw_readl 236 arch/sh/kernel/cpu/sh4a/perf_event.c tmp = __raw_readl(PPC_CCBR(idx)); __raw_readl 245 arch/sh/kernel/cpu/sh4a/perf_event.c tmp = __raw_readl(PPC_PMCAT); __raw_readl 250 arch/sh/kernel/cpu/sh4a/perf_event.c tmp = __raw_readl(PPC_CCBR(idx)); __raw_readl 254 arch/sh/kernel/cpu/sh4a/perf_event.c __raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx)); __raw_readl 262 arch/sh/kernel/cpu/sh4a/perf_event.c __raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i)); __raw_readl 270 arch/sh/kernel/cpu/sh4a/perf_event.c __raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i)); __raw_readl 1154 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */ __raw_readl 1156 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */ __raw_readl 1157 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */ __raw_readl 1158 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */ __raw_readl 1159 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */ __raw_readl 1160 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */ __raw_readl 1161 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */ __raw_readl 1162 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */ __raw_readl 1163 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */ __raw_readl 1164 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */ __raw_readl 1165 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */ __raw_readl 1166 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */ __raw_readl 1203 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */ __raw_readl 1204 arch/sh/kernel/cpu/sh4a/setup-sh7724.c sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */ __raw_readl 591 arch/sh/kernel/cpu/sh4a/setup-sh7734.c __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0); __raw_readl 594 arch/sh/kernel/cpu/sh4a/setup-sh7734.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); __raw_readl 604 arch/sh/kernel/cpu/sh4a/setup-sh7734.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); __raw_readl 1193 arch/sh/kernel/cpu/sh4a/setup-sh7757.c __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); __raw_readl 1196 arch/sh/kernel/cpu/sh4a/setup-sh7757.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); __raw_readl 1206 arch/sh/kernel/cpu/sh4a/setup-sh7757.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); __raw_readl 1211 arch/sh/kernel/cpu/sh4a/setup-sh7757.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); __raw_readl 428 arch/sh/kernel/cpu/sh4a/setup-sh7763.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); __raw_readl 531 arch/sh/kernel/cpu/sh4a/setup-sh7770.c __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); __raw_readl 534 arch/sh/kernel/cpu/sh4a/setup-sh7770.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); __raw_readl 544 arch/sh/kernel/cpu/sh4a/setup-sh7770.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); __raw_readl 465 arch/sh/kernel/cpu/sh4a/setup-sh7780.c __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); __raw_readl 468 arch/sh/kernel/cpu/sh4a/setup-sh7780.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); __raw_readl 478 arch/sh/kernel/cpu/sh4a/setup-sh7780.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); __raw_readl 557 arch/sh/kernel/cpu/sh4a/setup-sh7785.c __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); __raw_readl 560 arch/sh/kernel/cpu/sh4a/setup-sh7785.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); __raw_readl 570 arch/sh/kernel/cpu/sh4a/setup-sh7785.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); __raw_readl 575 arch/sh/kernel/cpu/sh4a/setup-sh7785.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); __raw_readl 411 arch/sh/kernel/cpu/sh4a/setup-sh7786.c u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK; __raw_readl 447 arch/sh/kernel/cpu/sh4a/setup-sh7786.c if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) { __raw_readl 755 arch/sh/kernel/cpu/sh4a/setup-sh7786.c __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); __raw_readl 765 arch/sh/kernel/cpu/sh4a/setup-sh7786.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); __raw_readl 770 arch/sh/kernel/cpu/sh4a/setup-sh7786.c __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); __raw_readl 34 arch/sh/kernel/cpu/sh4a/smp-shx3.c x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ __raw_readl 51 arch/sh/kernel/cpu/sh4a/smp-shx3.c __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); __raw_readl 90 arch/sh/kernel/cpu/sh4a/smp-shx3.c if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) __raw_readl 93 arch/sh/kernel/cpu/sh4a/smp-shx3.c while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) __raw_readl 102 arch/sh/kernel/cpu/sh4a/smp-shx3.c return __raw_readl(0xff000048); /* CPIDR */ __raw_readl 117 arch/sh/kernel/cpu/sh4a/smp-shx3.c while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) __raw_readl 50 arch/sh/kernel/cpu/sh4a/ubc.c __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, __raw_readl 59 arch/sh/kernel/cpu/sh4a/ubc.c __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, __raw_readl 69 arch/sh/kernel/cpu/sh4a/ubc.c if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE) __raw_readl 77 arch/sh/kernel/cpu/sh4a/ubc.c return __raw_readl(UBC_CCMFR); __raw_readl 82 arch/sh/kernel/cpu/sh4a/ubc.c __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); __raw_readl 121 arch/sh/kernel/cpu/sh4a/ubc.c (void)__raw_readl(UBC_CRR(i)); __raw_readl 24 arch/sh/kernel/cpu/sh5/clock-sh5.c int idx = (__raw_readl(cprc_base + 0x00) >> 6) & 0x0007; __raw_readl 676 arch/sh/kernel/dwarf.c frame->cfa = __raw_readl(addr); __raw_readl 708 arch/sh/kernel/dwarf.c frame->return_addr = __raw_readl(addr); __raw_readl 274 arch/sh/kernel/ftrace.c if (old_addr != __raw_readl((unsigned long *)code)) __raw_readl 193 arch/sh/kernel/io_trapped.c tmp = __raw_readl(src_addr); __raw_readl 37 arch/sh/kernel/iomap.c return be32_to_cpu(__raw_readl(addr)); __raw_readl 98 arch/sh/kernel/iomap.c u32 data = __raw_readl(addr); __raw_readl 42 arch/sh/kernel/process_32.c printk("TEA : %08x\n", __raw_readl(MMU_TEA)); __raw_readl 19 arch/sh/lib/io.c *data++ = __raw_readl(addr); __raw_readl 59 arch/sh/lib/io.c *data++ = __raw_readl(addr); __raw_readl 39 arch/sh/mm/cache-debugfs.c ccr = __raw_readl(SH_CCR); __raw_readl 77 arch/sh/mm/cache-debugfs.c unsigned long data = __raw_readl(addr); __raw_readl 63 arch/sh/mm/cache-j2.c pr_info("Initial J2 CCR is %.8x\n", __raw_readl(j2_ccr_base)); __raw_readl 30 arch/sh/mm/cache-sh2.c unsigned long data = __raw_readl(addr | (way << 12)); __raw_readl 65 arch/sh/mm/cache-sh2.c ccr = __raw_readl(SH_CCR); __raw_readl 31 arch/sh/mm/cache-sh2a.c data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr); __raw_readl 71 arch/sh/mm/cache-sh2a.c unsigned long data = __raw_readl(v); __raw_readl 136 arch/sh/mm/cache-sh2a.c __raw_writel(__raw_readl(SH_CCR) | CCR_OCACHE_INVALIDATE, __raw_readl 170 arch/sh/mm/cache-sh2a.c __raw_writel(__raw_readl(SH_CCR) | CCR_ICACHE_INVALIDATE, __raw_readl 52 arch/sh/mm/cache-sh3.c data = __raw_readl(addr); __raw_readl 136 arch/sh/mm/cache-sh4.c ccr = __raw_readl(SH_CCR); __raw_readl 381 arch/sh/mm/cache-sh4.c __raw_readl(CCN_PVR), __raw_readl 382 arch/sh/mm/cache-sh4.c __raw_readl(CCN_CVR), __raw_readl 383 arch/sh/mm/cache-sh4.c __raw_readl(CCN_PRR)); __raw_readl 51 arch/sh/mm/cache-sh7705.c data = __raw_readl(addr); __raw_readl 118 arch/sh/mm/cache-sh7705.c data = __raw_readl(addr) & (0x1ffffC00 | SH_CACHE_VALID); __raw_readl 22 arch/sh/mm/cache-shx3.c ccr = __raw_readl(SH_CCR); __raw_readl 296 arch/sh/mm/cache.c cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE); __raw_readl 316 arch/sh/mm/pmb.c addr_val = __raw_readl(addr); __raw_readl 317 arch/sh/mm/pmb.c data_val = __raw_readl(data); __raw_readl 587 arch/sh/mm/pmb.c addr_val = __raw_readl(addr); __raw_readl 588 arch/sh/mm/pmb.c data_val = __raw_readl(data); __raw_readl 812 arch/sh/mm/pmb.c return (__raw_readl(PMB_PASCR) & PASCR_SE) == 0; __raw_readl 828 arch/sh/mm/pmb.c addr = __raw_readl(mk_pmb_addr(i)); __raw_readl 829 arch/sh/mm/pmb.c data = __raw_readl(mk_pmb_data(i)); __raw_readl 48 arch/sh/mm/tlb-debugfs.c mmucr = __raw_readl(MMUCR); __raw_readl 100 arch/sh/mm/tlb-debugfs.c val = __raw_readl(addr1 | (entry << MMU_TLB_ENTRY_SHIFT)); __raw_readl 105 arch/sh/mm/tlb-debugfs.c val = __raw_readl(addr2 | (entry << MMU_TLB_ENTRY_SHIFT)); __raw_readl 109 arch/sh/mm/tlb-debugfs.c val = __raw_readl(data1 | (entry << MMU_TLB_ENTRY_SHIFT)); __raw_readl 113 arch/sh/mm/tlb-debugfs.c val = __raw_readl(data2 | (entry << MMU_TLB_ENTRY_SHIFT)); __raw_readl 91 arch/sh/mm/tlb-pteaex.c status = __raw_readl(MMUCR); __raw_readl 91 arch/sh/mm/tlb-sh3.c status = __raw_readl(MMUCR); __raw_readl 93 arch/sh/mm/tlb-sh4.c status = __raw_readl(MMUCR); __raw_readl 27 arch/sh/mm/tlb-urb.c status = __raw_readl(MMUCR); __raw_readl 50 arch/sh/mm/tlb-urb.c status = __raw_readl(MMUCR); __raw_readl 76 arch/sh/mm/tlb-urb.c status = __raw_readl(MMUCR); __raw_readl 134 arch/sh/mm/tlbflush_32.c __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR); __raw_readl 17 arch/sparc/include/asm/io.h #define readl_be(__addr) __raw_readl(__addr) __raw_readl 44 arch/sparc/include/asm/io_64.h #define __raw_readl __raw_readl __raw_readl 302 arch/sparc/include/asm/io_64.h return __raw_readl(addr); __raw_readl 422 arch/sparc/include/asm/io_64.h #define ioread32be __raw_readl __raw_readl 48 arch/sparc/kernel/leon_pci_grpci1.c #define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a)))) __raw_readl 92 arch/sparc/kernel/leon_pci_grpci2.c #define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a)))) __raw_readl 152 arch/sparc/lib/PeeCeeI.c *pi++ = __raw_readl(addr); __raw_readl 162 arch/sparc/lib/PeeCeeI.c l = __raw_readl(addr); __raw_readl 166 arch/sparc/lib/PeeCeeI.c l2 = __raw_readl(addr); __raw_readl 177 arch/sparc/lib/PeeCeeI.c l = __raw_readl(addr); __raw_readl 183 arch/sparc/lib/PeeCeeI.c l2 = __raw_readl(addr); __raw_readl 194 arch/sparc/lib/PeeCeeI.c l = __raw_readl(addr); __raw_readl 198 arch/sparc/lib/PeeCeeI.c l2 = __raw_readl(addr); __raw_readl 97 arch/xtensa/platforms/xtfpga/setup.c freq = __raw_readl(base); __raw_readl 102 drivers/ata/ahci_brcm.c return __raw_readl(addr); __raw_readl 92 drivers/ata/pata_imx.c val = __raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL); __raw_readl 232 drivers/ata/pata_imx.c __raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL); __raw_readl 82 drivers/bcma/host_soc.c *buf = (__force __le32)__raw_readl(addr); __raw_readl 468 drivers/bus/mips_cdmm.c acsr = __raw_readl(cdmm + drb * CDMM_DRB_SIZE); __raw_readl 515 drivers/bus/mips_cdmm.c acsr = __raw_readl(cdmm + drb * CDMM_DRB_SIZE); __raw_readl 393 drivers/cdrom/gdrom.c __raw_readl(count); __raw_readl 48 drivers/char/hw_random/bcm2835-rng.c return __raw_readl(priv->base + offset); __raw_readl 33 drivers/char/hw_random/ixp4xx-rng.c *buffer = __raw_readl(rng_base); __raw_readl 68 drivers/char/hw_random/mxc-rnga.c int level = (__raw_readl(mxc_rng->mem + RNGA_STATUS) & __raw_readl 84 drivers/char/hw_random/mxc-rnga.c *data = __raw_readl(mxc_rng->mem + RNGA_OUTPUT_FIFO); __raw_readl 87 drivers/char/hw_random/mxc-rnga.c err = __raw_readl(mxc_rng->mem + RNGA_STATUS) & RNGA_STATUS_ERROR_INT; __raw_readl 92 drivers/char/hw_random/mxc-rnga.c ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); __raw_readl 106 drivers/char/hw_random/mxc-rnga.c ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); __raw_readl 110 drivers/char/hw_random/mxc-rnga.c osc = __raw_readl(mxc_rng->mem + RNGA_STATUS); __raw_readl 117 drivers/char/hw_random/mxc-rnga.c ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); __raw_readl 128 drivers/char/hw_random/mxc-rnga.c ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); __raw_readl 27 drivers/char/hw_random/nomadik-rng.c *(u16 *)data = __raw_readl(base + 8) & 0xffff; __raw_readl 165 drivers/char/hw_random/omap-rng.c return __raw_readl(priv->base + priv->pdata->regs[reg]); __raw_readl 103 drivers/clk/imx/clk-imx35.c pdr0 = __raw_readl(base + MXC_CCM_PDR0); __raw_readl 148 drivers/clk/imx/clk-imx6sl.c while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) __raw_readl 173 drivers/clk/imx/clk-imx6sl.c while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) __raw_readl 118 drivers/clk/imx/clk-pllv2.c dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); __raw_readl 119 drivers/clk/imx/clk-pllv2.c dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); __raw_readl 120 drivers/clk/imx/clk-pllv2.c dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); __raw_readl 121 drivers/clk/imx/clk-pllv2.c dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); __raw_readl 170 drivers/clk/imx/clk-pllv2.c dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); __raw_readl 203 drivers/clk/imx/clk-pllv2.c reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; __raw_readl 208 drivers/clk/imx/clk-pllv2.c reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); __raw_readl 230 drivers/clk/imx/clk-pllv2.c reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; __raw_readl 24 drivers/clk/loongson1/clk-loongson1b.c pll = __raw_readl(LS1X_CLK_PLL_FREQ); __raw_readl 23 drivers/clk/loongson1/clk-loongson1c.c pll = __raw_readl(LS1X_CLK_PLL_FREQ); __raw_readl 104 drivers/clk/pxa/clk-pxa3xx.c unsigned long memclkcfg = __raw_readl(MEMCLKCFG); __raw_readl 124 drivers/clk/renesas/clk-sh73a0.c mult = __raw_readl(dsi_reg); __raw_readl 332 drivers/clk/tegra/clk-dfll.c return __raw_readl(td->base + offs); __raw_readl 350 drivers/clk/tegra/clk-dfll.c return __raw_readl(td->i2c_base + offs); __raw_readl 1349 drivers/clk/tegra/clk-dfll.c __raw_readl(td->i2c_controller_base + offs)); __raw_readl 1354 drivers/clk/tegra/clk-dfll.c __raw_readl(td->lut_base + offs)); __raw_readl 77 drivers/clk/ti/clk-dra7-atl.c return __raw_readl(cinfo->iobase + reg); __raw_readl 88 drivers/clocksource/mxs_timer.c return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1)) __raw_readl 237 drivers/clocksource/mxs_timer.c timrot_major_version = __raw_readl(mxs_timrot_base + __raw_readl 80 drivers/clocksource/timer-ixp4xx.c return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET); __raw_readl 113 drivers/clocksource/timer-ixp4xx.c val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); __raw_readl 127 drivers/clocksource/timer-ixp4xx.c val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); __raw_readl 161 drivers/clocksource/timer-ixp4xx.c val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); __raw_readl 53 drivers/clocksource/timer-vf-pit.c return ~__raw_readl(clksrc_base + PITCVAL); __raw_readl 68 drivers/cpufreq/loongson1-cpufreq.c __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) | RST_CPU_EN | RST_CPU, __raw_readl 70 drivers/cpufreq/loongson1-cpufreq.c __raw_writel(__raw_readl(LS1X_CLK_PLL_DIV) & ~(RST_CPU_EN | RST_CPU), __raw_readl 120 drivers/cpufreq/s3c2412-cpufreq.c olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN); __raw_readl 146 drivers/cpufreq/s3c2440-cpufreq.c clkdiv = __raw_readl(S3C2410_CLKDIVN); __raw_readl 147 drivers/cpufreq/s3c2440-cpufreq.c camdiv = __raw_readl(S3C2440_CAMDIVN); __raw_readl 71 drivers/cpufreq/s3c24xx-cpufreq.c cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON); __raw_readl 389 drivers/cpufreq/s3c24xx-cpufreq.c suspend_pll.driver_data = __raw_readl(S3C2410_MPLLCON); __raw_readl 52 drivers/crypto/omap-aes.c _read_ret = __raw_readl(dd->io_base + offset); \ __raw_readl 60 drivers/crypto/omap-aes.c return __raw_readl(dd->io_base + offset); __raw_readl 177 drivers/crypto/omap-des.c _read_ret = __raw_readl(dd->io_base + offset); \ __raw_readl 185 drivers/crypto/omap-des.c return __raw_readl(dd->io_base + offset); __raw_readl 249 drivers/crypto/omap-sham.c return __raw_readl(dd->io_base + offset); __raw_readl 202 drivers/crypto/qat/qat_common/adf_accel_devices.h #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) __raw_readl 145 drivers/crypto/s5p-sss.c #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) __raw_readl 614 drivers/crypto/s5p-sss.c return __raw_readl(dd->io_hash_base + offset); __raw_readl 271 drivers/dma/at_hdmac_regs.h __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET) __raw_readl 340 drivers/dma/at_hdmac_regs.h __raw_readl((atdma)->regs + AT_DMA_##name) __raw_readl 265 drivers/dma/imx-dma.c return __raw_readl(imxdma->base + offset); __raw_readl 247 drivers/dma/iop-adma.h return __raw_readl(DMA_DAR(chan)); __raw_readl 249 drivers/dma/iop-adma.h return __raw_readl(AAU_ADAR(chan)); __raw_readl 280 drivers/dma/iop-adma.h u32 status = __raw_readl(DMA_CSR(chan)); __raw_readl 797 drivers/dma/iop-adma.h dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); __raw_readl 804 drivers/dma/iop-adma.h return __raw_readl(DMA_CSR(chan)); __raw_readl 809 drivers/dma/iop-adma.h u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); __raw_readl 816 drivers/dma/iop-adma.h u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); __raw_readl 824 drivers/dma/iop-adma.h u32 status = __raw_readl(DMA_CSR(chan)); __raw_readl 831 drivers/dma/iop-adma.h u32 status = __raw_readl(DMA_CSR(chan)); __raw_readl 838 drivers/dma/iop-adma.h u32 status = __raw_readl(DMA_CSR(chan)); __raw_readl 45 drivers/dma/ipu/ipu_idmac.c return __raw_readl(ipu->reg_ic + reg); __raw_readl 59 drivers/dma/ipu/ipu_idmac.c return __raw_readl(ipu->reg_ipu + reg); __raw_readl 24 drivers/dma/ipu/ipu_irq.c return __raw_readl(ipu->reg_ipu + reg); __raw_readl 307 drivers/dma/mmp_tdma.c reg = __raw_readl(tdmac->reg_base + TDSAR); __raw_readl 310 drivers/dma/mmp_tdma.c reg = __raw_readl(tdmac->reg_base + TDDAR); __raw_readl 85 drivers/dma/sh/shdmac.c return __raw_readl(sh_dc->base + reg); __raw_readl 93 drivers/dma/sh/shdmac.c return __raw_readl(addr); __raw_readl 119 drivers/dma/sh/shdmac.c return __raw_readl(sh_dc->base + shdev->chcr_offset); __raw_readl 285 drivers/dma/ti/cppi41.c return __raw_readl(mem); __raw_readl 304 drivers/dma/ti/edma.c return (unsigned int)__raw_readl(ecc->base + offset); __raw_readl 40 drivers/dma/txx9dmac.c __raw_readl(&(__dma_regs(dc)->name)) __raw_readl 45 drivers/dma/txx9dmac.c __raw_readl(&(__dma_regs32(dc)->name)) __raw_readl 113 drivers/dma/txx9dmac.c __raw_readl(&(__txx9dmac_regs(ddev)->name)) __raw_readl 118 drivers/dma/txx9dmac.c __raw_readl(&(__txx9dmac_regs32(ddev)->name)) __raw_readl 327 drivers/edac/cpc925_edac.c mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET + __raw_readl 329 drivers/edac/cpc925_edac.c mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET + __raw_readl 387 drivers/edac/cpc925_edac.c apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET); __raw_readl 394 drivers/edac/cpc925_edac.c mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET); __raw_readl 529 drivers/edac/cpc925_edac.c apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET); __raw_readl 533 drivers/edac/cpc925_edac.c mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET); __raw_readl 536 drivers/edac/cpc925_edac.c mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET); __raw_readl 560 drivers/edac/cpc925_edac.c __raw_readl(pdata->vbase + REG_APIMASK_OFFSET)); __raw_readl 564 drivers/edac/cpc925_edac.c __raw_readl(pdata->vbase + REG_MSCR_OFFSET)); __raw_readl 566 drivers/edac/cpc925_edac.c __raw_readl(pdata->vbase + REG_MSRSR_OFFSET)); __raw_readl 568 drivers/edac/cpc925_edac.c __raw_readl(pdata->vbase + REG_MSRER_OFFSET)); __raw_readl 570 drivers/edac/cpc925_edac.c __raw_readl(pdata->vbase + REG_MSPR_OFFSET)); __raw_readl 572 drivers/edac/cpc925_edac.c __raw_readl(pdata->vbase + REG_MCCR_OFFSET)); __raw_readl 574 drivers/edac/cpc925_edac.c __raw_readl(pdata->vbase + REG_MCRER_OFFSET)); __raw_readl 620 drivers/edac/cpc925_edac.c apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET); __raw_readl 660 drivers/edac/cpc925_edac.c apiexcp = __raw_readl(dev_info->vbase + REG_APIEXCP_OFFSET); __raw_readl 667 drivers/edac/cpc925_edac.c apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET); __raw_readl 682 drivers/edac/cpc925_edac.c ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET); __raw_readl 694 drivers/edac/cpc925_edac.c ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET); __raw_readl 703 drivers/edac/cpc925_edac.c u32 brgctrl = __raw_readl(dev_info->vbase + REG_BRGCTRL_OFFSET); __raw_readl 704 drivers/edac/cpc925_edac.c u32 linkctrl = __raw_readl(dev_info->vbase + REG_LINKCTRL_OFFSET); __raw_readl 705 drivers/edac/cpc925_edac.c u32 errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET); __raw_readl 706 drivers/edac/cpc925_edac.c u32 linkerr = __raw_readl(dev_info->vbase + REG_LINKERR_OFFSET); __raw_readl 870 drivers/edac/cpc925_edac.c mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET); __raw_readl 891 drivers/edac/cpc925_edac.c mbcr = __raw_readl(vbase + REG_MBCR_OFFSET); __raw_readl 41 drivers/firmware/tegra/bpmp-tegra210.c return __raw_readl(priv->arb_sema + STA_OFFSET) & CH_MASK(index); __raw_readl 148 drivers/fpga/socfpga.c return __raw_readl(priv->fpga_base_addr + reg_offset); __raw_readl 134 drivers/gpio/gpio-ixp4xx.c val = __raw_readl(g->base + int_reg); __raw_readl 141 drivers/gpio/gpio-ixp4xx.c val = __raw_readl(g->base + int_reg); __raw_readl 146 drivers/gpio/gpio-ixp4xx.c val = __raw_readl(g->base + IXP4XX_REG_GPOE); __raw_readl 29 drivers/gpio/gpio-loongson1.c __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) | BIT(offset), __raw_readl 41 drivers/gpio/gpio-loongson1.c __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) & ~BIT(offset), __raw_readl 170 drivers/gpio/gpio-lpc32xx.c return __raw_readl(group->reg_base + offset); __raw_readl 69 drivers/gpio/gpio-stp-xway.c #define xway_stp_r32(m, reg) __raw_readl(m + reg) __raw_readl 104 drivers/gpio/gpio-tegra.c return __raw_readl(tgi->regs + reg); __raw_readl 29 drivers/gpio/gpio-xilinx.c # define xgpio_readreg(offset) __raw_readl(offset) __raw_readl 365 drivers/gpu/drm/omapdrm/dss/dispc.c return __raw_readl(dispc->base + idx); __raw_readl 461 drivers/gpu/drm/omapdrm/dss/dsi.c return __raw_readl(base + idx.idx); __raw_readl 102 drivers/gpu/drm/omapdrm/dss/dss.c return __raw_readl(dss->base + idx.idx); __raw_readl 273 drivers/gpu/drm/omapdrm/dss/hdmi.h return __raw_readl(base_addr + idx); __raw_readl 317 drivers/gpu/drm/omapdrm/dss/venc.c u32 l = __raw_readl(venc->base + idx); __raw_readl 1122 drivers/hwtracing/coresight/coresight.c val = __raw_readl(addr + offset); __raw_readl 1656 drivers/hwtracing/intel_th/msu.c reg = __raw_readl(msc->reg_base + REG_MSU_MSC0STS); __raw_readl 52 drivers/i2c/busses/i2c-au1550.c return __raw_readl(a->psc_base + r); __raw_readl 95 drivers/i2c/busses/i2c-iop3xx.c unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); __raw_readl 111 drivers/i2c/busses/i2c-iop3xx.c u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET); __raw_readl 231 drivers/i2c/busses/i2c-iop3xx.c unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); __raw_readl 257 drivers/i2c/busses/i2c-iop3xx.c unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); __raw_readl 279 drivers/i2c/busses/i2c-iop3xx.c unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); __raw_readl 295 drivers/i2c/busses/i2c-iop3xx.c *byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET); __raw_readl 396 drivers/i2c/busses/i2c-iop3xx.c unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET); __raw_readl 59 drivers/i2c/busses/i2c-pmcmsp.c #define pmcmsptwi_readl __raw_readl __raw_readl 109 drivers/i2c/busses/i2c-sh7760.c return __raw_readl((unsigned long)cam->iobase + reg); __raw_readl 71 drivers/i2c/busses/i2c-xlr.c return __raw_readl(base + reg); __raw_readl 1305 drivers/i3c/master/i3c-master-cdns.c u32 tmp = __raw_readl(master->regs + IBI_DATA_FIFO); __raw_readl 134 drivers/iio/adc/lpc32xx_adc.c st->value = __raw_readl(LPC32XXAD_VALUE(st->adc_base)) & __raw_readl 118 drivers/iio/adc/spear_adc.c return __raw_readl(&st->adc_base_spear6xx->average.msb) & __raw_readl 121 drivers/iio/adc/spear_adc.c return __raw_readl(&st->adc_base_spear3xx->average) & __raw_readl 1730 drivers/infiniband/hw/hns/hns_roce_hw_v1.c __raw_readl(hcr + HCR_STATUS_OFFSET)); __raw_readl 367 drivers/infiniband/hw/mthca/mthca_cmd.c __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 | __raw_readl 369 drivers/infiniband/hw/mthca/mthca_cmd.c __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4)); __raw_readl 375 drivers/infiniband/hw/mthca/mthca_cmd.c status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24; __raw_readl 120 drivers/input/keyboard/davinci_keyscan.c prev_status = __raw_readl(davinci_ks->base + DAVINCI_KEYSCAN_PREVSTATE); __raw_readl 121 drivers/input/keyboard/davinci_keyscan.c new_status = __raw_readl(davinci_ks->base + DAVINCI_KEYSCAN_CURRENTST); __raw_readl 87 drivers/input/keyboard/ep93xx_keypad.c status = __raw_readl(keypad->mmio_base + KEY_REG); __raw_readl 41 drivers/input/keyboard/goldfish_events.c type = __raw_readl(edev->addr + REG_READ); __raw_readl 42 drivers/input/keyboard/goldfish_events.c code = __raw_readl(edev->addr + REG_READ); __raw_readl 43 drivers/input/keyboard/goldfish_events.c value = __raw_readl(edev->addr + REG_READ); __raw_readl 60 drivers/input/keyboard/goldfish_events.c size = __raw_readl(addr + REG_LEN) * 8; __raw_readl 83 drivers/input/keyboard/goldfish_events.c count = __raw_readl(addr + REG_LEN) / sizeof(val); __raw_readl 94 drivers/input/keyboard/goldfish_events.c val[j] = __raw_readl(edev->addr + REG_DATA + offset); __raw_readl 126 drivers/input/keyboard/goldfish_events.c keymapnamelen = __raw_readl(addr + REG_LEN); __raw_readl 87 drivers/input/keyboard/omap4-keypad.c return __raw_readl(keypad_data->base + __raw_readl 99 drivers/input/keyboard/omap4-keypad.c return __raw_readl(keypad_data->base + __raw_readl 285 drivers/input/keyboard/omap4-keypad.c rev = __raw_readl(keypad_data->base + OMAP4_KBD_REVISION); __raw_readl 90 drivers/input/keyboard/pxa27x_keypad.c #define keypad_readl(off) __raw_readl(keypad->mmio_base + (off)) __raw_readl 31 drivers/input/keyboard/pxa930_rotary.c uint32_t sbcr = __raw_readl(r->mmio_base + SBCR); __raw_readl 43 drivers/input/keyboard/pxa930_rotary.c ercr = __raw_readl(r->mmio_base + ERCR) & 0xf; __raw_readl 58 drivers/input/mouse/pxa930_trkball.c tbcntr = __raw_readl(trkball->mmio_base + TBCNTR); __raw_readl 60 drivers/input/mouse/pxa930_trkball.c if (tbcntr == __raw_readl(trkball->mmio_base + TBCNTR)) { __raw_readl 83 drivers/input/mouse/pxa930_trkball.c if (__raw_readl(trkball->mmio_base + TBCR) == v) __raw_readl 101 drivers/input/mouse/pxa930_trkball.c tbcr = __raw_readl(trkball->mmio_base + TBCR); __raw_readl 107 drivers/input/mouse/pxa930_trkball.c tbcr = __raw_readl(trkball->mmio_base + TBCR); __raw_readl 115 drivers/input/mouse/pxa930_trkball.c __raw_readl(trkball->mmio_base + TBCR)); __raw_readl 129 drivers/input/mouse/pxa930_trkball.c uint32_t tbcr = __raw_readl(trkball->mmio_base + TBCR); __raw_readl 42 drivers/input/mouse/rpcmouse.c b = (short) (__raw_readl(IOMEM(0xe0310000)) ^ 0x70); __raw_readl 60 drivers/input/touchscreen/lpc32xx_ts.c __raw_readl((dev)->tsc_base + (reg)) __raw_readl 258 drivers/iommu/omap-iommu.h return __raw_readl(obj->regbase + offs); __raw_readl 41 drivers/irqchip/irq-ath79-misc.c pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & __raw_readl 42 drivers/irqchip/irq-ath79-misc.c __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); __raw_readl 66 drivers/irqchip/irq-ath79-misc.c t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); __raw_readl 70 drivers/irqchip/irq-ath79-misc.c __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); __raw_readl 79 drivers/irqchip/irq-ath79-misc.c t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); __raw_readl 83 drivers/irqchip/irq-ath79-misc.c __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); __raw_readl 92 drivers/irqchip/irq-ath79-misc.c t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); __raw_readl 96 drivers/irqchip/irq-ath79-misc.c __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); __raw_readl 137 drivers/irqchip/irq-bcm6345-l1.c pending = __raw_readl(cpu->map_base + reg_status(intc, idx)); __raw_readl 138 drivers/irqchip/irq-bcm6345-l1.c pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx)); __raw_readl 79 drivers/irqchip/irq-ixp4xx.c val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2); __raw_readl 83 drivers/irqchip/irq-ixp4xx.c val = __raw_readl(ixi->irqbase + IXP4XX_ICMR); __raw_readl 99 drivers/irqchip/irq-ixp4xx.c val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2); __raw_readl 103 drivers/irqchip/irq-ixp4xx.c val = __raw_readl(ixi->irqbase + IXP4XX_ICMR); __raw_readl 115 drivers/irqchip/irq-ixp4xx.c status = __raw_readl(ixi->irqbase + IXP4XX_ICIP); __raw_readl 123 drivers/irqchip/irq-ixp4xx.c status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2); __raw_readl 137 drivers/irqchip/irq-mxs.c irqnr = __raw_readl(icoll_priv.stat); __raw_readl 134 drivers/mailbox/omap-mailbox.c return __raw_readl(mdev->mbox_base + ofs); __raw_readl 26 drivers/media/pci/cx18/cx18-io.h return __raw_readl(addr); __raw_readl 111 drivers/media/platform/davinci/dm355_ccdc.c return __raw_readl(ccdc_cfg.base_addr + offset); __raw_readl 89 drivers/media/platform/davinci/dm644x_ccdc.c return __raw_readl(ccdc_cfg.base_addr + offset); __raw_readl 138 drivers/media/platform/davinci/isif.c return __raw_readl(isif_cfg.base_addr + offset); __raw_readl 121 drivers/media/platform/davinci/vpss.c return __raw_readl(oper_cfg.vpss_regs_base0 + offset); __raw_readl 131 drivers/media/platform/davinci/vpss.c return __raw_readl(oper_cfg.vpss_regs_base1 + offset); __raw_readl 142 drivers/media/platform/davinci/vpss.c return __raw_readl(oper_cfg.vpss_regs_base0 + offset); __raw_readl 280 drivers/media/platform/omap3isp/isp.h return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset); __raw_readl 960 drivers/media/platform/pxa_camera.c __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR); __raw_readl 962 drivers/media/platform/pxa_camera.c cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; __raw_readl 973 drivers/media/platform/pxa_camera.c cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; __raw_readl 1049 drivers/media/platform/pxa_camera.c camera_status = __raw_readl(pcdev->base + CISR); __raw_readl 1197 drivers/media/platform/pxa_camera.c __raw_readl(pcdev->base + CISR)); __raw_readl 1200 drivers/media/platform/pxa_camera.c cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; __raw_readl 1216 drivers/media/platform/pxa_camera.c status = __raw_readl(pcdev->base + CISR); __raw_readl 1226 drivers/media/platform/pxa_camera.c cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; __raw_readl 1303 drivers/media/platform/pxa_camera.c cicr0 = __raw_readl(pcdev->base + CICR0); __raw_readl 1823 drivers/media/platform/pxa_camera.c reg->val = __raw_readl(pcdev->base + reg->reg); __raw_readl 2254 drivers/media/platform/pxa_camera.c pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); __raw_readl 2255 drivers/media/platform/pxa_camera.c pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); __raw_readl 2256 drivers/media/platform/pxa_camera.c pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); __raw_readl 2257 drivers/media/platform/pxa_camera.c pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); __raw_readl 2258 drivers/media/platform/pxa_camera.c pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); __raw_readl 114 drivers/media/platform/sh_vou.c return __raw_readl(vou_dev->base + reg); __raw_readl 120 drivers/media/platform/sh_vou.c u32 old = __raw_readl(vou_dev->base + reg); __raw_readl 175 drivers/media/rc/mtk-cir.c tmp = __raw_readl(ir->base + reg); __raw_readl 187 drivers/media/rc/mtk-cir.c return __raw_readl(ir->base + reg); __raw_readl 251 drivers/memory/ti-emif-pm.c __raw_readl((void *)emif_instance->ti_emif_sram_virt); __raw_readl 172 drivers/memstick/host/jmb38x_ms.c *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA); __raw_readl 73 drivers/memstick/host/r592.c u32 value = __raw_readl(dev->mmio + address); __raw_readl 101 drivers/memstick/host/tifm_ms.c *(unsigned int *)(buf + off) = __raw_readl(sock->addr __raw_readl 127 drivers/misc/genwqe/card_utils.c return be32_to_cpu((__force __be32)__raw_readl(cd->mmio + byte_offs)); __raw_readl 168 drivers/mmc/host/atmel-mci.c __raw_readl((port)->regs + reg) __raw_readl 166 drivers/mmc/host/au1xmmc.c u32 val = __raw_readl(HOST_CONFIG(host)); __raw_readl 174 drivers/mmc/host/au1xmmc.c u32 val = __raw_readl(HOST_CONFIG2(host)); __raw_readl 189 drivers/mmc/host/au1xmmc.c u32 val = __raw_readl(HOST_CONFIG(host)); __raw_readl 202 drivers/mmc/host/au1xmmc.c config2 = __raw_readl(HOST_CONFIG2(host)); __raw_readl 312 drivers/mmc/host/au1xmmc.c while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO) __raw_readl 317 drivers/mmc/host/au1xmmc.c u32 status = __raw_readl(HOST_STATUS(host)); __raw_readl 320 drivers/mmc/host/au1xmmc.c status = __raw_readl(HOST_STATUS(host)); __raw_readl 345 drivers/mmc/host/au1xmmc.c status = __raw_readl(HOST_STATUS(host)); __raw_readl 349 drivers/mmc/host/au1xmmc.c status = __raw_readl(HOST_STATUS(host)); __raw_readl 386 drivers/mmc/host/au1xmmc.c u32 status = __raw_readl(HOST_STATUS(host)); __raw_readl 418 drivers/mmc/host/au1xmmc.c status = __raw_readl(HOST_STATUS(host)); __raw_readl 479 drivers/mmc/host/au1xmmc.c status = __raw_readl(HOST_STATUS(host)); __raw_readl 501 drivers/mmc/host/au1xmmc.c val = __raw_readl(HOST_RXPORT(host)); __raw_readl 546 drivers/mmc/host/au1xmmc.c r[0] = __raw_readl(host->iobase + SD_RESP3); __raw_readl 547 drivers/mmc/host/au1xmmc.c r[1] = __raw_readl(host->iobase + SD_RESP2); __raw_readl 548 drivers/mmc/host/au1xmmc.c r[2] = __raw_readl(host->iobase + SD_RESP1); __raw_readl 549 drivers/mmc/host/au1xmmc.c r[3] = __raw_readl(host->iobase + SD_RESP0); __raw_readl 568 drivers/mmc/host/au1xmmc.c cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0); __raw_readl 595 drivers/mmc/host/au1xmmc.c status = __raw_readl(HOST_STATUS(host)); __raw_readl 608 drivers/mmc/host/au1xmmc.c config = __raw_readl(HOST_CONFIG(host)); __raw_readl 772 drivers/mmc/host/au1xmmc.c config2 = __raw_readl(HOST_CONFIG2(host)); __raw_readl 798 drivers/mmc/host/au1xmmc.c status = __raw_readl(HOST_STATUS(host)); __raw_readl 453 drivers/mmc/host/dw_mmc.h #define mci_fifo_readl(__reg) __raw_readl(__reg) __raw_readl 159 drivers/mmc/host/omap_hsmmc.c __raw_readl((base) + OMAP_HSMMC_##reg) __raw_readl 364 drivers/mtd/nand/raw/au1550nd.c staddr = __raw_readl(base + addr + 0x08); /* STADDRx */ __raw_readl 637 drivers/mtd/nand/raw/brcmnand/brcmnand.c return __raw_readl(ctrl->nand_fc + word * 4); __raw_readl 47 drivers/mtd/nand/raw/brcmnand/brcmnand.h return __raw_readl(addr); __raw_readl 72 drivers/mtd/nand/raw/davinci_nand.c return __raw_readl(info->base + offset); __raw_readl 200 drivers/mtd/nand/raw/mxc_nand.c *t++ = __raw_readl(s++); __raw_readl 93 drivers/mtd/nand/raw/txx9ndfmc.c return __raw_readl(ndregaddr(dev, reg)); __raw_readl 128 drivers/mtd/nand/raw/txx9ndfmc.c *buf++ = __raw_readl(ndfdtr); __raw_readl 235 drivers/mtd/nand/raw/vf610_nfc.c u32 val = swab32(__raw_readl(src + i)); __raw_readl 224 drivers/net/can/ti_hecc.c return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4); __raw_readl 235 drivers/net/can/ti_hecc.c return __raw_readl(priv->mbx + mbxno * 0x10 + reg); __raw_readl 245 drivers/net/can/ti_hecc.c return __raw_readl(priv->base + reg); __raw_readl 324 drivers/net/dsa/lantiq_gswip.c return __raw_readl(priv->gswip + (offset * 4)); __raw_readl 347 drivers/net/dsa/lantiq_gswip.c return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, __raw_readl 353 drivers/net/dsa/lantiq_gswip.c return __raw_readl(priv->mdio + (offset * 4)); __raw_readl 373 drivers/net/dsa/lantiq_gswip.c return __raw_readl(priv->mii + (offset * 4)); __raw_readl 81 drivers/net/ethernet/aeroflex/greth.c #define GRETH_REGLOAD(a) (be32_to_cpu(__raw_readl(&(a)))) __raw_readl 162 drivers/net/ethernet/aeroflex/greth.c return be32_to_cpu(__raw_readl(bd)); __raw_readl 86 drivers/net/ethernet/broadcom/genet/bcmgenet.c return __raw_readl(offset); __raw_readl 691 drivers/net/ethernet/broadcom/genet/bcmgenet.h return __raw_readl(priv->base + offset + off); \ __raw_readl 228 drivers/net/ethernet/cadence/macb_main.c return __raw_readl(bp->regs + offset); __raw_readl 255 drivers/net/ethernet/cadence/macb_main.c value = __raw_readl(addr + MACB_NCR); __raw_readl 268 drivers/net/ethernet/cadence/macb_main.c id = __raw_readl(addr + MACB_MID); __raw_readl 1370 drivers/net/ethernet/calxeda/xgmac.c intr_status = __raw_readl(ioaddr + XGMAC_INT_STAT); __raw_readl 1387 drivers/net/ethernet/calxeda/xgmac.c intr_status = __raw_readl(priv->base + XGMAC_DMA_STATUS); __raw_readl 1388 drivers/net/ethernet/calxeda/xgmac.c intr_status &= __raw_readl(priv->base + XGMAC_DMA_INTR_ENA); __raw_readl 180 drivers/net/ethernet/cirrus/ep93xx_eth.c #define rdl(ep, off) __raw_readl((ep)->base_addr + (off)) __raw_readl 493 drivers/net/ethernet/freescale/enetc/enetc_hw.h *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0); __raw_readl 20 drivers/net/ethernet/freescale/enetc/enetc_pf.c u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si)); __raw_readl 209 drivers/net/ethernet/freescale/fs_enet/fs_enet.h #define __cbd_in32(addr) __raw_readl(addr) __raw_readl 51 drivers/net/ethernet/freescale/fs_enet/mac-fec.c #define __fs_in32(addr) __raw_readl(addr) __raw_readl 48 drivers/net/ethernet/freescale/fs_enet/mac-scc.c #define __fs_in32(addr) __raw_readl(addr) __raw_readl 79 drivers/net/ethernet/lantiq_xrx200.c return __raw_readl(priv->pmac_reg + offset); __raw_readl 65 drivers/net/ethernet/mediatek/mtk_eth_soc.c return __raw_readl(eth->base + reg); __raw_readl 638 drivers/net/ethernet/mellanox/mlx4/cmd.c __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 | __raw_readl 640 drivers/net/ethernet/mellanox/mlx4/cmd.c __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4)); __raw_readl 642 drivers/net/ethernet/mellanox/mlx4/cmd.c __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24; __raw_readl 968 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c *wrptr32++ = __raw_readl(rdptr32++); __raw_readl 85 drivers/net/ethernet/sfc/falcon/io.h return (__force __le32)__raw_readl(efx->membase + reg); __raw_readl 173 drivers/net/ethernet/sfc/falcon/io.h value->u32[0] = (__force __le32)__raw_readl(membase + addr); __raw_readl 174 drivers/net/ethernet/sfc/falcon/io.h value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4); __raw_readl 97 drivers/net/ethernet/sfc/io.h return (__force __le32)__raw_readl(efx->membase + reg); __raw_readl 185 drivers/net/ethernet/sfc/io.h value->u32[0] = (__force __le32)__raw_readl(membase + addr); __raw_readl 186 drivers/net/ethernet/sfc/io.h value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4); __raw_readl 295 drivers/net/ethernet/xscale/ixp4xx_eth.c val = __raw_readl(®s->channel[ch].ch_event); __raw_readl 300 drivers/net/ethernet/xscale/ixp4xx_eth.c lo = __raw_readl(®s->channel[ch].src_uuid_lo); __raw_readl 301 drivers/net/ethernet/xscale/ixp4xx_eth.c hi = __raw_readl(®s->channel[ch].src_uuid_hi); __raw_readl 309 drivers/net/ethernet/xscale/ixp4xx_eth.c lo = __raw_readl(®s->channel[ch].rx_snap_lo); __raw_readl 310 drivers/net/ethernet/xscale/ixp4xx_eth.c hi = __raw_readl(®s->channel[ch].rx_snap_hi); __raw_readl 345 drivers/net/ethernet/xscale/ixp4xx_eth.c val = __raw_readl(®s->channel[ch].ch_event); __raw_readl 355 drivers/net/ethernet/xscale/ixp4xx_eth.c lo = __raw_readl(®s->channel[ch].tx_snap_lo); __raw_readl 356 drivers/net/ethernet/xscale/ixp4xx_eth.c hi = __raw_readl(®s->channel[ch].tx_snap_hi); __raw_readl 443 drivers/net/ethernet/xscale/ixp4xx_eth.c if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { __raw_readl 458 drivers/net/ethernet/xscale/ixp4xx_eth.c (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { __raw_readl 477 drivers/net/ethernet/xscale/ixp4xx_eth.c if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { __raw_readl 485 drivers/net/ethernet/xscale/ixp4xx_eth.c return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | __raw_readl 486 drivers/net/ethernet/xscale/ixp4xx_eth.c ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8); __raw_readl 55 drivers/net/phy/mdio-bcm-unimac.c return __raw_readl(priv->base + offset); __raw_readl 159 drivers/net/wireless/ath/wil6210/main.c *d++ = __raw_readl(s++); __raw_readl 163 drivers/net/wireless/ath/wil6210/main.c u32 tmp = __raw_readl(s); __raw_readl 86 drivers/net/wireless/intersil/p54/p54pci.h #define P54P_READ(r) (__force __le32)__raw_readl(&priv->map->r) __raw_readl 101 drivers/parisc/ccio-dma.c #define READ_U32(addr) __raw_readl(addr) __raw_readl 231 drivers/parisc/dino.c __raw_readl(base_addr + DINO_CONFIG_DATA); __raw_readl 332 drivers/parisc/dino.c __raw_readl(dino_dev->hba.base_addr+DINO_IPR); __raw_readl 347 drivers/parisc/dino.c tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR); __raw_readl 378 drivers/parisc/dino.c mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK; __raw_readl 400 drivers/parisc/dino.c mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr; __raw_readl 682 drivers/parisc/dino.c status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS); __raw_readl 749 drivers/parisc/dino.c io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN); __raw_readl 862 drivers/parisc/dino.c __raw_readl(dino_dev->hba.base_addr+DINO_IRR0); __raw_readl 130 drivers/parisc/lba_pci.c #define READ_U32(addr) __raw_readl(addr) __raw_readl 290 drivers/phy/ti/phy-ti-pipe3.c return __raw_readl(addr + offset); __raw_readl 48 drivers/pinctrl/samsung/pinctrl-exynos-arm.c tmp = __raw_readl(clk_base + S5P_OTHERS); __raw_readl 146 drivers/platform/x86/intel_scu_ipc.c return __raw_readl(scu->ipc_base + 0x04); __raw_readl 63 drivers/power/avs/smartreflex.c reg_val = __raw_readl(sr->base + offset); __raw_readl 75 drivers/power/avs/smartreflex.c return __raw_readl(sr->base + offset); __raw_readl 46 drivers/ptp/ptp_ixp46x.c lo = __raw_readl(®s->systime_lo); __raw_readl 47 drivers/ptp/ptp_ixp46x.c hi = __raw_readl(®s->systime_hi); __raw_readl 79 drivers/ptp/ptp_ixp46x.c val = __raw_readl(®s->event); __raw_readl 84 drivers/ptp/ptp_ixp46x.c hi = __raw_readl(®s->asms_hi); __raw_readl 85 drivers/ptp/ptp_ixp46x.c lo = __raw_readl(®s->asms_lo); __raw_readl 98 drivers/ptp/ptp_ixp46x.c hi = __raw_readl(®s->amms_hi); __raw_readl 99 drivers/ptp/ptp_ixp46x.c lo = __raw_readl(®s->amms_lo); __raw_readl 101 drivers/pwm/pwm-atmel-tcb.c cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); __raw_readl 109 drivers/pwm/pwm-atmel-tcb.c __raw_readl(regs + ATMEL_TC_REG(group, RA)); __raw_readl 112 drivers/pwm/pwm-atmel-tcb.c __raw_readl(regs + ATMEL_TC_REG(group, RB)); __raw_readl 115 drivers/pwm/pwm-atmel-tcb.c tcbpwm->period = __raw_readl(regs + ATMEL_TC_REG(group, RC)); __raw_readl 164 drivers/pwm/pwm-atmel-tcb.c cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); __raw_readl 223 drivers/pwm/pwm-atmel-tcb.c cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR)); __raw_readl 65 drivers/pwm/pwm-brcmstb.c return __raw_readl(p->base + offset); __raw_readl 27 drivers/rtc/rtc-ds1286.c return __raw_readl(&priv->rtcregs[reg]) & 0xff; __raw_readl 333 drivers/rtc/rtc-imxdi.c return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR)); __raw_readl 347 drivers/rtc/rtc-imxdi.c dcr = __raw_readl(imxdi->ioaddr + DCR); __raw_readl 43 drivers/rtc/rtc-lpc32xx.c __raw_readl((dev)->rtc_base + (reg)) __raw_readl 82 drivers/rtc/rtc-msm6242.c return __raw_readl(&priv->regs[reg]) & 0xf; __raw_readl 72 drivers/rtc/rtc-pxa.c __raw_readl((pxa_rtc)->base + (reg)) __raw_readl 73 drivers/rtc/rtc-rp5c01.c return __raw_readl(&priv->regs[reg]) & 0xf; __raw_readl 51 drivers/rtc/rtc-tx4939.c while (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_BUSY) { __raw_readl 80 drivers/rtc/rtc-tx4939.c (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); __raw_readl 96 drivers/rtc/rtc-tx4939.c (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); __raw_readl 103 drivers/rtc/rtc-tx4939.c buf[i] = __raw_readl(&rtcreg->dat); __raw_readl 148 drivers/rtc/rtc-tx4939.c (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALME)); __raw_readl 155 drivers/rtc/rtc-tx4939.c buf[i] = __raw_readl(&rtcreg->dat); __raw_readl 156 drivers/rtc/rtc-tx4939.c ctl = __raw_readl(&rtcreg->ctl); __raw_readl 185 drivers/rtc/rtc-tx4939.c if (__raw_readl(&rtcreg->ctl) & TX4939_RTCCTL_ALMD) { __raw_readl 213 drivers/rtc/rtc-tx4939.c *buf++ = __raw_readl(&rtcreg->dat); __raw_readl 274 drivers/scsi/ncr53c8xx.h #define readl_l2b __raw_readl __raw_readl 278 drivers/scsi/ncr53c8xx.h #define readl_raw __raw_readl __raw_readl 99 drivers/scsi/zalon.c while (!(__raw_readl(zalon + IO_MODULE_IO_STATUS) & IOSTATUS_RY)) __raw_readl 105 drivers/scsi/zalon.c zalon_vers = (__raw_readl(zalon + IO_MODULE_II_CDATA) >> 24) & 0x07; __raw_readl 414 drivers/sh/clk/cpg.c value = __raw_readl(clk->mapping->base); __raw_readl 437 drivers/sh/clk/cpg.c value = __raw_readl(clk->mapping->base) >> 16; __raw_readl 93 drivers/sh/intc/access.c return intc_get_field_from_handle(__raw_readl(ptr), h); __raw_readl 119 drivers/sh/intc/access.c (void)__raw_readl(ptr); /* Defeat write posting */ __raw_readl 158 drivers/sh/intc/access.c value = intc_set_field_from_handle(__raw_readl(ptr), data, h); __raw_readl 160 drivers/sh/intc/access.c (void)__raw_readl(ptr); /* Defeat write posting */ __raw_readl 107 drivers/sh/intc/chip.c __raw_readl(addr); __raw_readl 26 drivers/sh/intc/userimask.c return sprintf(buf, "%d\n", (__raw_readl(uimask) >> 4) & 0xf); __raw_readl 134 drivers/sh/maple/maple.c return (__raw_readl(MAPLE_STATE) & 1) == 0; __raw_readl 138 drivers/soc/bcm/brcmstb/pm/pm-mips.c tmp = __raw_readl(base + AON_CTRL_HOST_MISC_CMDS); __raw_readl 141 drivers/soc/bcm/brcmstb/pm/pm-mips.c (void)__raw_readl(base + AON_CTRL_HOST_MISC_CMDS); __raw_readl 144 drivers/soc/bcm/brcmstb/pm/pm-mips.c (void)__raw_readl(base + AON_CTRL_PM_INITIATE); __raw_readl 165 drivers/soc/bcm/brcmstb/pm/pm-mips.c (void)__raw_readl(base + AON_CTRL_PM_CPU_WAIT_COUNT); __raw_readl 169 drivers/soc/bcm/brcmstb/pm/pm-mips.c (void)__raw_readl(base + AON_CTRL_PM_CTRL); __raw_readl 173 drivers/soc/bcm/brcmstb/pm/pm-mips.c (void)__raw_readl(base + AON_CTRL_PM_CTRL); __raw_readl 194 drivers/soc/bcm/brcmstb/pm/pm-mips.c tmp = __raw_readl(ctrl.aon_ctrl_base + AON_CTRL_RESET_CTRL); __raw_readl 202 drivers/soc/bcm/brcmstb/pm/pm-mips.c tmp = __raw_readl(ctrl.memcs[i].ddr_phy_base + __raw_readl 219 drivers/soc/bcm/brcmstb/pm/pm-mips.c s3_context.memc0_rts[i] = __raw_readl(memc_arb_base); __raw_readl 164 drivers/soc/ixp4xx/ixp4xx-npe.c return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0; __raw_readl 181 drivers/soc/ixp4xx/ixp4xx-npe.c __raw_readl(&npe->regs->exec_data); __raw_readl 182 drivers/soc/ixp4xx/ixp4xx-npe.c __raw_readl(&npe->regs->exec_data); __raw_readl 183 drivers/soc/ixp4xx/ixp4xx-npe.c return __raw_readl(&npe->regs->exec_data); __raw_readl 236 drivers/soc/ixp4xx/ixp4xx-npe.c wc = __raw_readl(&npe->regs->watch_count); __raw_readl 243 drivers/soc/ixp4xx/ixp4xx-npe.c if (wc != __raw_readl(&npe->regs->watch_count)) __raw_readl 288 drivers/soc/ixp4xx/ixp4xx-npe.c ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) & __raw_readl 296 drivers/soc/ixp4xx/ixp4xx-npe.c exec_count = __raw_readl(&npe->regs->exec_count); __raw_readl 305 drivers/soc/ixp4xx/ixp4xx-npe.c while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID) __raw_readl 307 drivers/soc/ixp4xx/ixp4xx-npe.c while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) __raw_readl 310 drivers/soc/ixp4xx/ixp4xx-npe.c __raw_readl(&npe->regs->in_out_fifo)); __raw_readl 312 drivers/soc/ixp4xx/ixp4xx-npe.c while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) __raw_readl 413 drivers/soc/ixp4xx/ixp4xx-npe.c if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) { __raw_readl 420 drivers/soc/ixp4xx/ixp4xx-npe.c if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) { __raw_readl 428 drivers/soc/ixp4xx/ixp4xx-npe.c (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) { __raw_readl 452 drivers/soc/ixp4xx/ixp4xx-npe.c if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) { __raw_readl 453 drivers/soc/ixp4xx/ixp4xx-npe.c recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo); __raw_readl 42 drivers/soc/ixp4xx/ixp4xx-qmgr.c val = __raw_readl(&qmgr_regs->acc[queue][0]); __raw_readl 54 drivers/soc/ixp4xx/ixp4xx-qmgr.c return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) __raw_readl 61 drivers/soc/ixp4xx/ixp4xx-qmgr.c return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) __raw_readl 86 drivers/soc/ixp4xx/ixp4xx-qmgr.c return (__raw_readl(&qmgr_regs->statne_h) >> __raw_readl 100 drivers/soc/ixp4xx/ixp4xx-qmgr.c return (__raw_readl(&qmgr_regs->statf_h) >> __raw_readl 128 drivers/soc/ixp4xx/ixp4xx-qmgr.c __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), __raw_readl 187 drivers/soc/ixp4xx/ixp4xx-qmgr.c u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]); __raw_readl 210 drivers/soc/ixp4xx/ixp4xx-qmgr.c __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask, __raw_readl 222 drivers/soc/ixp4xx/ixp4xx-qmgr.c __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask, __raw_readl 285 drivers/soc/ixp4xx/ixp4xx-qmgr.c if (__raw_readl(&qmgr_regs->sram[queue])) { __raw_readl 334 drivers/soc/ixp4xx/ixp4xx-qmgr.c cfg = __raw_readl(&qmgr_regs->sram[queue]); __raw_readl 60 drivers/soc/renesas/rmobile-sysc.c if (__raw_readl(rmobile_pd->base + PSTR) & mask) { __raw_readl 65 drivers/soc/renesas/rmobile-sysc.c if (!(__raw_readl(rmobile_pd->base + SPDCR) & mask)) __raw_readl 72 drivers/soc/renesas/rmobile-sysc.c __raw_readl(rmobile_pd->base + PSTR)); __raw_readl 83 drivers/soc/renesas/rmobile-sysc.c if (__raw_readl(rmobile_pd->base + PSTR) & mask) __raw_readl 89 drivers/soc/renesas/rmobile-sysc.c if (!(__raw_readl(rmobile_pd->base + SWUCR) & mask)) __raw_readl 101 drivers/soc/renesas/rmobile-sysc.c __raw_readl(rmobile_pd->base + PSTR)); __raw_readl 148 drivers/soc/ti/pm33xx.c i = __raw_readl(pm_ops->get_rtc_base_addr() + 0x44) & 0x40; __raw_readl 227 drivers/spi/spi-atmel.c __raw_readl((port)->regs + SPI_##reg) __raw_readl 118 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); __raw_readl 138 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); __raw_readl 147 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); __raw_readl 228 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + __raw_readl 239 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); __raw_readl 302 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); __raw_readl 318 drivers/spi/spi-bcm63xx-hsspi.c if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0) __raw_readl 420 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); __raw_readl 151 drivers/spi/spi-dw.h return __raw_readl(dws->regs + offset); __raw_readl 191 drivers/spi/spi-lantiq-ssc.c return __raw_readl(spi->regbase + reg); __raw_readl 203 drivers/spi/spi-lantiq-ssc.c u32 val = __raw_readl(spi->regbase + reg); __raw_readl 93 drivers/spi/spi-pxa2xx.h return __raw_readl(drv_data->ioaddr + reg); __raw_readl 27 drivers/spi/spi-rb4xx.c return __raw_readl(rbspi->base + reg); __raw_readl 88 drivers/spi/spi-txx9.c return __raw_readl(c->membase + reg); __raw_readl 40 drivers/spi/spi-xtensa-xtfpga.c return __raw_readl(spi->regs + addr); __raw_readl 222 drivers/spmi/spmi-pmic-arb.c u32 data = __raw_readl(pmic_arb->rd_base + reg); __raw_readl 77 drivers/ssb/host_soc.c *buf = (__force __le32)__raw_readl(addr); __raw_readl 65 drivers/staging/emxx_udc/emxx_udc.c return __raw_readl(address); __raw_readl 79 drivers/staging/emxx_udc/emxx_udc.c u32 reg_dt = __raw_readl(address) | (udata); __raw_readl 88 drivers/staging/emxx_udc/emxx_udc.c u32 reg_dt = __raw_readl(address) & ~(udata); __raw_readl 42 drivers/staging/netlogic/xlr_net.c return __raw_readl(base + reg); __raw_readl 148 drivers/thermal/broadcom/brcmstb_thermal.c val = __raw_readl(priv->tmon_base + AVS_TMON_STATUS); __raw_readl 170 drivers/thermal/broadcom/brcmstb_thermal.c u32 val = __raw_readl(priv->tmon_base + trip->enable_offs); __raw_readl 186 drivers/thermal/broadcom/brcmstb_thermal.c u32 val = __raw_readl(priv->tmon_base + trip->reg_offs); __raw_readl 210 drivers/thermal/broadcom/brcmstb_thermal.c orig = __raw_readl(priv->tmon_base + trip->reg_offs); __raw_readl 220 drivers/thermal/broadcom/brcmstb_thermal.c val = __raw_readl(priv->tmon_base + AVS_TMON_TEMP_INT_CODE); __raw_readl 180 drivers/tty/mips_ejtag_fdc.c return __raw_readl(priv->reg + offs); __raw_readl 347 drivers/tty/mips_ejtag_fdc.c while (__raw_readl(regs + REG_FDSTAT) & REG_FDSTAT_TXF) __raw_readl 1197 drivers/tty/mips_ejtag_fdc.c stat = __raw_readl(regs + REG_FDSTAT); __raw_readl 1206 drivers/tty/mips_ejtag_fdc.c data = __raw_readl(regs + REG_FDRX); __raw_readl 1236 drivers/tty/mips_ejtag_fdc.c while (__raw_readl(regs + REG_FDSTAT) & REG_FDSTAT_TXF) __raw_readl 359 drivers/tty/serial/8250/8250_port.c return __raw_readl(p->membase + (offset << p->regshift)); __raw_readl 375 drivers/tty/serial/8250/8250_port.c return __raw_readl(up->port.membase + 0x28); __raw_readl 53 drivers/tty/serial/apbuart.h #define UART_GET_CHAR(port) (__raw_readl(APBBASE_DATA_P(port))) __raw_readl 55 drivers/tty/serial/apbuart.h #define UART_GET_STATUS(port) (__raw_readl(APBBASE_STATUS_P(port))) __raw_readl 57 drivers/tty/serial/apbuart.h #define UART_GET_CTRL(port) (__raw_readl(APBBASE_CTRL_P(port))) __raw_readl 59 drivers/tty/serial/apbuart.h #define UART_GET_SCAL(port) (__raw_readl(APBBASE_SCALAR_P(port))) __raw_readl 218 drivers/tty/serial/atmel_serial.c return __raw_readl(port->membase + reg); __raw_readl 80 drivers/tty/serial/bcm63xx_uart.c return __raw_readl(port->membase + offset); __raw_readl 127 drivers/tty/serial/lantiq.c u32 tmp = __raw_readl(reg); __raw_readl 168 drivers/tty/serial/lantiq.c fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & __raw_readl 173 drivers/tty/serial/lantiq.c rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) __raw_readl 233 drivers/tty/serial/lantiq.c while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) & __raw_readl 327 drivers/tty/serial/lantiq.c status = __raw_readl(port->membase + LTQ_ASC_FSTAT) & __raw_readl 610 drivers/tty/serial/lantiq.c fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT) __raw_readl 68 drivers/tty/serial/mux.c #define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET) __raw_readl 236 drivers/tty/serial/mux.c data = __raw_readl(port->membase + IO_DATA_REG_OFFSET); __raw_readl 86 drivers/tty/serial/pic32_uart.h return __raw_readl(port->membase + reg); __raw_readl 67 drivers/tty/serial/pnx8xxx_uart.c return (__raw_readl(sport->port.membase + offset)); __raw_readl 49 drivers/tty/serial/sa1100.c #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0) __raw_readl 50 drivers/tty/serial/sa1100.c #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1) __raw_readl 51 drivers/tty/serial/sa1100.c #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2) __raw_readl 52 drivers/tty/serial/sa1100.c #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3) __raw_readl 53 drivers/tty/serial/sa1100.c #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0) __raw_readl 54 drivers/tty/serial/sa1100.c #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1) __raw_readl 55 drivers/tty/serial/sa1100.c #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR) __raw_readl 174 drivers/tty/serial/serial_txx9.c return __raw_readl(up->port.membase + offset); __raw_readl 440 drivers/tty/serial/sirfsoc_uart.h #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg))) __raw_readl 495 drivers/usb/gadget/udc/aspeed-vhub/vhub.h (void)__raw_readl((void __iomem *)addr); __raw_readl 90 drivers/usb/gadget/udc/at91_udc.c __raw_readl((udc)->udp_baseaddr + (reg)) __raw_readl 118 drivers/usb/gadget/udc/at91_udc.c csr = __raw_readl(ep->creg); __raw_readl 326 drivers/usb/gadget/udc/at91_udc.c csr = __raw_readl(creg); __raw_readl 374 drivers/usb/gadget/udc/at91_udc.c csr = __raw_readl(creg); __raw_readl 388 drivers/usb/gadget/udc/at91_udc.c u32 csr = __raw_readl(creg); __raw_readl 410 drivers/usb/gadget/udc/at91_udc.c csr = __raw_readl(creg); __raw_readl 674 drivers/usb/gadget/udc/at91_udc.c tmp = __raw_readl(ep->creg); __raw_readl 749 drivers/usb/gadget/udc/at91_udc.c csr = __raw_readl(creg); __raw_readl 1007 drivers/usb/gadget/udc/at91_udc.c u32 csr = __raw_readl(creg); __raw_readl 1032 drivers/usb/gadget/udc/at91_udc.c csr = __raw_readl(creg); __raw_readl 1093 drivers/usb/gadget/udc/at91_udc.c csr = __raw_readl(creg); __raw_readl 1186 drivers/usb/gadget/udc/at91_udc.c if (__raw_readl(ep->creg) & AT91_UDP_FORCESTALL) __raw_readl 1208 drivers/usb/gadget/udc/at91_udc.c tmp = __raw_readl(ep->creg); __raw_readl 1231 drivers/usb/gadget/udc/at91_udc.c tmp = __raw_readl(ep->creg); __raw_readl 1275 drivers/usb/gadget/udc/at91_udc.c u32 csr = __raw_readl(creg); __raw_readl 1285 drivers/usb/gadget/udc/at91_udc.c csr = __raw_readl(creg); __raw_readl 1353 drivers/usb/gadget/udc/at91_udc.c csr = __raw_readl(creg); __raw_readl 244 drivers/usb/gadget/udc/fsl_udc_core.c ctrl = __raw_readl(&usb_sys_regs->control); __raw_readl 260 drivers/usb/gadget/udc/fsl_udc_core.c ctrl = __raw_readl(&usb_sys_regs->control); __raw_readl 329 drivers/usb/gadget/udc/fsl_udc_core.c ctrl = __raw_readl(&usb_sys_regs->control); __raw_readl 181 drivers/usb/gadget/udc/pxa27x_udc.h __raw_readl((ep)->dev->regs + ofs_##reg(ep)) __raw_readl 189 drivers/usb/gadget/udc/pxa27x_udc.h __raw_readl((dev)->regs + (reg)) __raw_readl 67 drivers/usb/host/ehci-omap.c return __raw_readl(base + reg); __raw_readl 734 drivers/usb/host/ehci.h #define readl_be(addr) __raw_readl((__force unsigned *)addr) __raw_readl 128 drivers/usb/host/ohci-nxp.c tmp = __raw_readl(usb_otg_stat_control) | HOST_EN; __raw_readl 145 drivers/usb/host/ohci-nxp.c tmp = __raw_readl(usb_otg_stat_control) & ~HOST_EN; __raw_readl 143 drivers/usb/host/ohci-pxa27x.c uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); __raw_readl 144 drivers/usb/host/ohci-pxa27x.c uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB); __raw_readl 224 drivers/usb/host/ohci-pxa27x.c uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); __raw_readl 225 drivers/usb/host/ohci-pxa27x.c uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); __raw_readl 263 drivers/usb/host/ohci-pxa27x.c uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); __raw_readl 291 drivers/usb/host/ohci-pxa27x.c uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR; __raw_readl 294 drivers/usb/host/ohci-pxa27x.c while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR) __raw_readl 310 drivers/usb/host/ohci-pxa27x.c uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE; __raw_readl 336 drivers/usb/host/ohci-pxa27x.c uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01; __raw_readl 198 drivers/usb/isp1760/isp1760-hcd.c *dst = le32_to_cpu(__raw_readl(src)); __raw_readl 205 drivers/usb/isp1760/isp1760-hcd.c *dst = __raw_readl(src); __raw_readl 219 drivers/usb/isp1760/isp1760-hcd.c val = le32_to_cpu(__raw_readl(src)); __raw_readl 221 drivers/usb/isp1760/isp1760-hcd.c val = __raw_readl(src); __raw_readl 53 drivers/usb/musb/davinci.c u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); __raw_readl 61 drivers/usb/musb/davinci.c while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0) __raw_readl 67 drivers/usb/musb/davinci.c u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); __raw_readl 384 drivers/usb/musb/davinci.c u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); __raw_readl 395 drivers/usb/musb/davinci.c u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); __raw_readl 411 drivers/usb/musb/davinci.c revision, __raw_readl(USB_PHY_CTRL), __raw_readl 433 drivers/usb/musb/davinci.c u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); __raw_readl 381 drivers/usb/musb/musb_core.c u32 data = __raw_readl(addr + offset); __raw_readl 925 drivers/usb/phy/phy-fsl-usb.c temp = __raw_readl(&p_otg->dr_mem_map->control); __raw_readl 70 drivers/video/fbdev/atmel_lcdfb.c #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg)) __raw_readl 133 drivers/video/fbdev/da8xx-fb.c return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr)); __raw_readl 125 drivers/video/fbdev/ep93xx-fb.c return __raw_readl(fbi->mmio_base + off); __raw_readl 486 drivers/video/fbdev/grvga.c __raw_writel(__raw_readl(&par->regs->status) | 1, /* Enable framebuffer */ __raw_readl 105 drivers/video/fbdev/mb862xx/mb862xxfb.h #define gdc_read __raw_readl __raw_readl 345 drivers/video/fbdev/mx3fb.c return __raw_readl(mx3fb->reg_base + reg); __raw_readl 67 drivers/video/fbdev/nvidia/nv_local.h #define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) __raw_readl 258 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return __raw_readl(dispc.base + idx); __raw_readl 460 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return __raw_readl(base + idx.idx); __raw_readl 120 drivers/video/fbdev/omap2/omapfb/dss/dss.c return __raw_readl(dss.base + idx.idx); __raw_readl 255 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h return __raw_readl(base_addr + idx); __raw_readl 308 drivers/video/fbdev/omap2/omapfb/dss/venc.c u32 l = __raw_readl(venc.base + idx); __raw_readl 107 drivers/video/fbdev/pxa3xx-gcu.c return __raw_readl(priv->mmio_base + off); __raw_readl 98 drivers/video/fbdev/pxafb.c return __raw_readl(fbi->mmio_base + off); __raw_readl 83 drivers/video/fbdev/riva/riva_hw.h #define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i))) __raw_readl 84 drivers/w1/masters/omap_hdq.c return __raw_readl(hdq_data->hdq_base + offset); __raw_readl 95 drivers/w1/masters/omap_hdq.c u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask) __raw_readl 69 drivers/watchdog/lantiq_wdt.c return __raw_readl(priv->membase + offset); __raw_readl 49 drivers/watchdog/m54xx_wdt.c gms0 = __raw_readl(MCF_GPT_GMS0); __raw_readl 67 drivers/watchdog/m54xx_wdt.c gms0 = __raw_readl(MCF_GPT_GMS0); __raw_readl 76 drivers/watchdog/m54xx_wdt.c gms0 = __raw_readl(MCF_GPT_GMS0); __raw_readl 68 drivers/watchdog/txx9wdt.c __raw_writel(__raw_readl(&txx9wdt_reg->tcr) & ~TXx9_TMTCR_TCE, __raw_readl 89 include/asm-generic/io.h #ifndef __raw_readl __raw_readl 90 include/asm-generic/io.h #define __raw_readl __raw_readl __raw_readl 179 include/asm-generic/io.h val = __le32_to_cpu(__raw_readl(addr)); __raw_readl 267 include/asm-generic/io.h return __le32_to_cpu(__raw_readl(addr)); __raw_readl 356 include/asm-generic/io.h u32 x = __raw_readl(addr); __raw_readl 492 include/asm-generic/io.h val = __le32_to_cpu(__raw_readl(PCI_IOBASE + addr)); __raw_readl 332 include/linux/atmel-ssc.h #define ssc_readl(base, reg) __raw_readl(base + SSC_##reg) __raw_readl 553 include/linux/fb.h #define fb_readl __raw_readl __raw_readl 83 include/linux/mmc/sh_mmcif.h return __raw_readl(addr + reg); __raw_readl 83 include/linux/mtd/doc2000.h return __raw_readl(addr + reg); __raw_readl 398 include/linux/mtd/map.h r.x[0] = __raw_readl(map->virt + ofs); __raw_readl 81 include/linux/phy/omap_usb.h return __raw_readl(addr + offset); __raw_readl 245 include/linux/pxa2xx_ssp.h return __raw_readl(dev->mmio_base + reg); __raw_readl 297 lib/iomap.c u32 data = __raw_readl(addr); __raw_readl 49 lib/iomap_copy.c *dst++ = __raw_readl(src++); __raw_readl 62 sound/atmel/ac97c.c __raw_readl((chip)->regs + AC97C_##reg) __raw_readl 94 sound/mips/hal2.c return __raw_readl(reg); __raw_readl 97 sound/parisc/harmony.c return __raw_readl(h->iobase + r); __raw_readl 16 sound/pci/mixart/mixart_hwdep.h #define readl_be(x) be32_to_cpu((__force __be32)__raw_readl(x)) __raw_readl 24 sound/pci/mixart/mixart_hwdep.h #define readl_le(x) le32_to_cpu((__force __le32)__raw_readl(x)) __raw_readl 70 sound/soc/atmel/atmel-pcm.h #define ssc_readx(base, reg) (__raw_readl((base) + (reg))) __raw_readl 74 sound/soc/au1x/ac97c.c return __raw_readl(ctx->mmio + reg); __raw_readl 72 sound/soc/au1x/i2sc.c return __raw_readl(ctx->mmio + reg); __raw_readl 92 sound/soc/au1x/psc-ac97.c if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) __raw_readl 96 sound/soc/au1x/psc-ac97.c data = __raw_readl(AC97_CDC(pscdata)); __raw_readl 132 sound/soc/au1x/psc-ac97.c if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) __raw_readl 179 sound/soc/au1x/psc-ac97.c while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i)) __raw_readl 193 sound/soc/au1x/psc-ac97.c while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i)) __raw_readl 217 sound/soc/au1x/psc-ac97.c r = ro = __raw_readl(AC97_CFG(pscdata)); __raw_readl 218 sound/soc/au1x/psc-ac97.c stat = __raw_readl(AC97_STAT(pscdata)); __raw_readl 256 sound/soc/au1x/psc-ac97.c while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t) __raw_readl 272 sound/soc/au1x/psc-ac97.c while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t) __raw_readl 309 sound/soc/au1x/psc-ac97.c while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype)) __raw_readl 396 sound/soc/au1x/psc-ac97.c sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK; __raw_readl 447 sound/soc/au1x/psc-ac97.c wd->pm[0] = __raw_readl(PSC_SEL(wd)); __raw_readl 120 sound/soc/au1x/psc-i2s.c stat = __raw_readl(I2S_STAT(pscdata)); __raw_readl 123 sound/soc/au1x/psc-i2s.c cfgbits = __raw_readl(I2S_CFG(pscdata)); __raw_readl 153 sound/soc/au1x/psc-i2s.c while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo) __raw_readl 166 sound/soc/au1x/psc-i2s.c while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo) __raw_readl 187 sound/soc/au1x/psc-i2s.c stat = __raw_readl(I2S_STAT(pscdata)); __raw_readl 201 sound/soc/au1x/psc-i2s.c while (!(__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) __raw_readl 222 sound/soc/au1x/psc-i2s.c while ((__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) __raw_readl 226 sound/soc/au1x/psc-i2s.c stat = __raw_readl(I2S_STAT(pscdata)); __raw_readl 320 sound/soc/au1x/psc-i2s.c sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK; __raw_readl 364 sound/soc/au1x/psc-i2s.c wd->pm[0] = __raw_readl(PSC_SEL(wd)); __raw_readl 121 sound/soc/cirrus/ep93xx-ac97.c return __raw_readl(info->regs + reg); __raw_readl 104 sound/soc/cirrus/ep93xx-i2s.c return __raw_readl(info->regs + reg); __raw_readl 102 sound/soc/mxs/mxs-saif.c scr = __raw_readl(master_saif->base + SAIF_CTRL); __raw_readl 213 sound/soc/mxs/mxs-saif.c stat = __raw_readl(saif->base + SAIF_STAT); __raw_readl 263 sound/soc/mxs/mxs-saif.c stat = __raw_readl(saif->base + SAIF_STAT); __raw_readl 296 sound/soc/mxs/mxs-saif.c stat = __raw_readl(saif->base + SAIF_STAT); __raw_readl 312 sound/soc/mxs/mxs-saif.c scr0 = __raw_readl(saif->base + SAIF_CTRL); __raw_readl 433 sound/soc/mxs/mxs-saif.c stat = __raw_readl(saif->base + SAIF_STAT); __raw_readl 469 sound/soc/mxs/mxs-saif.c scr = __raw_readl(saif->base + SAIF_CTRL); __raw_readl 579 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_DATA); __raw_readl 580 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_DATA); __raw_readl 587 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_CTRL), __raw_readl 588 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_STAT)); __raw_readl 591 sound/soc/mxs/mxs-saif.c __raw_readl(master_saif->base + SAIF_CTRL), __raw_readl 592 sound/soc/mxs/mxs-saif.c __raw_readl(master_saif->base + SAIF_STAT)); __raw_readl 681 sound/soc/mxs/mxs-saif.c stat = __raw_readl(saif->base + SAIF_STAT); __raw_readl 699 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_CTRL), __raw_readl 700 sound/soc/mxs/mxs-saif.c __raw_readl(saif->base + SAIF_STAT)); __raw_readl 46 sound/soc/pxa/mmp-sspa.c return __raw_readl(sspa->mmio_base + reg); __raw_readl 68 sound/soc/pxa/pxa-ssp.c sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE; __raw_readl 76 sound/soc/pxa/pxa-ssp.c sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE; __raw_readl 144 sound/soc/pxa/pxa-ssp.c priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0); __raw_readl 145 sound/soc/pxa/pxa-ssp.c priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1); __raw_readl 146 sound/soc/pxa/pxa-ssp.c priv->to = __raw_readl(ssp->mmio_base + SSTO); __raw_readl 147 sound/soc/pxa/pxa-ssp.c priv->psp = __raw_readl(ssp->mmio_base + SSPSP); __raw_readl 321 sound/soc/sh/fsi.c return __raw_readl(reg); __raw_readl 141 sound/soc/sh/siu.h return __raw_readl(addr); __raw_readl 174 sound/soc/ti/davinci-i2s.c return __raw_readl(dev->base + reg); __raw_readl 131 sound/soc/ti/davinci-mcasp.c __raw_writel(__raw_readl(reg) | val, reg); __raw_readl 138 sound/soc/ti/davinci-mcasp.c __raw_writel((__raw_readl(reg) & ~(val)), reg); __raw_readl 145 sound/soc/ti/davinci-mcasp.c __raw_writel((__raw_readl(reg) & ~mask) | val, reg); __raw_readl 156 sound/soc/ti/davinci-mcasp.c return (u32)__raw_readl(mcasp->base + offset); __raw_readl 41 sound/soc/txx9/txx9aclc-ac97.c return __raw_readl(drvdata->base + ACINTSTS) & ACINT_REGACCRDY; __raw_readl 52 sound/soc/txx9/txx9aclc-ac97.c if (!(__raw_readl(base + ACINTSTS) & ACINT_CODECRDY(ac97->num))) __raw_readl 64 sound/soc/txx9/txx9aclc-ac97.c dat = __raw_readl(base + ACREGACC); __raw_readl 107 sound/soc/txx9/txx9aclc-ac97.c (__raw_readl(base + ACINTSTS) & ready) == ready, __raw_readl 111 sound/soc/txx9/txx9aclc-ac97.c __raw_readl(base + ACINTSTS)); __raw_readl 129 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(__raw_readl(base + ACINTMSTS), base + ACINTDIS); __raw_readl 393 sound/soc/txx9/txx9aclc.c __raw_writel(__raw_readl(base + ACAUDIDAT), base + ACAUDODAT);