__offset_INTF    1754 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
__offset_INTF    1756 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
__offset_INTF    1758 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
__offset_INTF    1760 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
__offset_INTF    1774 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
__offset_INTF    1776 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
__offset_INTF    1778 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
__offset_INTF    1780 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
__offset_INTF    1782 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
__offset_INTF    1784 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
__offset_INTF    1786 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
__offset_INTF    1788 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
__offset_INTF    1790 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
__offset_INTF    1799 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
__offset_INTF    1807 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
__offset_INTF    1809 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
__offset_INTF    1811 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
__offset_INTF    1825 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
__offset_INTF    1840 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
__offset_INTF    1842 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
__offset_INTF    1844 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
__offset_INTF    1846 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
__offset_INTF    1851 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
__offset_INTF    1853 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
__offset_INTF    1855 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
__offset_INTF    1857 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
__offset_INTF    1859 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
__offset_INTF    1861 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
__offset_INTF    1863 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
__offset_INTF    1865 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
__offset_INTF    1867 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
__offset_INTF    1869 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
__offset_INTF    1871 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
__offset_INTF    1873 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
__offset_INTF    1875 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
__offset_INTF    1877 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
__offset_INTF    1879 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
__offset_INTF    1881 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
__offset_INTF    1883 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
__offset_INTF    1885 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
__offset_INTF    1887 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }