__offset_DSPP    1268 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
__offset_DSPP    1270 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
__offset_DSPP    1287 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
__offset_DSPP    1289 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
__offset_DSPP    1291 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
__offset_DSPP    1293 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
__offset_DSPP    1295 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
__offset_DSPP    1297 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
__offset_DSPP    1299 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
__offset_DSPP    1301 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }