__offset_AD      1897 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
__offset_AD      1899 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
__offset_AD      1901 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
__offset_AD      1903 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
__offset_AD      1905 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
__offset_AD      1907 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
__offset_AD      1909 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
__offset_AD      1911 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
__offset_AD      1913 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
__offset_AD      1915 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
__offset_AD      1917 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
__offset_AD      1919 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
__offset_AD      1921 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
__offset_AD      1923 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
__offset_AD      1925 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
__offset_AD      1927 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
__offset_AD      1929 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
__offset_AD      1931 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
__offset_AD      1933 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
__offset_AD      1935 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
__offset_AD      1937 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
__offset_AD      1939 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
__offset_AD      1941 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
__offset_AD      1943 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
__offset_AD      1945 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
__offset_AD      1947 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
__offset_AD      1949 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
__offset_AD      1951 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
__offset_AD      1953 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
__offset_AD      1955 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
__offset_AD      1957 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
__offset_AD      1959 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
__offset_AD      1961 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
__offset_AD      1963 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
__offset_AD      1965 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }