__REG 45 arch/arm/mach-pxa/include/mach/hardware.h (*(volatile u32 __iomem*)((u32)&__REG(x) + (y))) __REG 20 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ __REG 21 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ __REG 22 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ __REG 23 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ __REG 24 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ __REG 25 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ __REG 26 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ __REG 27 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ __REG 28 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ __REG 29 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ __REG 30 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ __REG 31 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ __REG 32 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ __REG 34 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ __REG 35 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ __REG 36 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ __REG 37 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ __REG 38 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ __REG 39 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ __REG 41 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD0 __REG(0x40F00080 + 0 * 4) __REG 42 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD1 __REG(0x40F00080 + 1 * 4) __REG 43 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD2 __REG(0x40F00080 + 2 * 4) __REG 44 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD3 __REG(0x40F00080 + 3 * 4) __REG 45 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD4 __REG(0x40F00080 + 4 * 4) __REG 46 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD5 __REG(0x40F00080 + 5 * 4) __REG 47 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD6 __REG(0x40F00080 + 6 * 4) __REG 48 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD7 __REG(0x40F00080 + 7 * 4) __REG 49 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD8 __REG(0x40F00080 + 8 * 4) __REG 50 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD9 __REG(0x40F00080 + 9 * 4) __REG 51 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD10 __REG(0x40F00080 + 10 * 4) __REG 52 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD11 __REG(0x40F00080 + 11 * 4) __REG 53 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD12 __REG(0x40F00080 + 12 * 4) __REG 54 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD13 __REG(0x40F00080 + 13 * 4) __REG 55 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD14 __REG(0x40F00080 + 14 * 4) __REG 56 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD15 __REG(0x40F00080 + 15 * 4) __REG 57 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD16 __REG(0x40F00080 + 16 * 4) __REG 58 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD17 __REG(0x40F00080 + 17 * 4) __REG 59 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD18 __REG(0x40F00080 + 18 * 4) __REG 60 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD19 __REG(0x40F00080 + 19 * 4) __REG 61 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD20 __REG(0x40F00080 + 20 * 4) __REG 62 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD21 __REG(0x40F00080 + 21 * 4) __REG 63 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD22 __REG(0x40F00080 + 22 * 4) __REG 64 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD23 __REG(0x40F00080 + 23 * 4) __REG 65 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD24 __REG(0x40F00080 + 24 * 4) __REG 66 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD25 __REG(0x40F00080 + 25 * 4) __REG 67 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD26 __REG(0x40F00080 + 26 * 4) __REG 68 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD27 __REG(0x40F00080 + 27 * 4) __REG 69 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD28 __REG(0x40F00080 + 28 * 4) __REG 70 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD29 __REG(0x40F00080 + 29 * 4) __REG 71 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD30 __REG(0x40F00080 + 30 * 4) __REG 72 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define PCMD31 __REG(0x40F00080 + 31 * 4) __REG 26 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define PMCR __REG(0x40F50000) /* Power Manager Control Register */ __REG 27 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ __REG 28 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ __REG 29 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ __REG 30 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ __REG 31 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ __REG 32 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ __REG 33 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ __REG 34 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ __REG 35 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define PCMD(x) __REG(0x40F50110 + ((x) << 2)) __REG 40 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ __REG 41 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ __REG 42 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */ __REG 43 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */ __REG 44 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */ __REG 45 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */ __REG 46 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */ __REG 47 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */ __REG 48 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */ __REG 49 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */ __REG 50 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */ __REG 51 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */ __REG 52 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */ __REG 53 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */ __REG 126 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ __REG 127 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ __REG 128 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ __REG 129 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ __REG 130 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define CKENB __REG(0x41340010) /* B Clock Enable Register */ __REG 131 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define CKENC __REG(0x41340024) /* C Clock Enable Register */ __REG 132 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ __REG 11 arch/arm/mach-pxa/include/mach/regs-ac97.h #define POCR __REG(0x40500000) /* PCM Out Control Register */ __REG 15 arch/arm/mach-pxa/include/mach/regs-ac97.h #define PICR __REG(0x40500004) /* PCM In Control Register */ __REG 19 arch/arm/mach-pxa/include/mach/regs-ac97.h #define MCCR __REG(0x40500008) /* Mic In Control Register */ __REG 23 arch/arm/mach-pxa/include/mach/regs-ac97.h #define GCR __REG(0x4050000C) /* Global Control Register */ __REG 39 arch/arm/mach-pxa/include/mach/regs-ac97.h #define POSR __REG(0x40500010) /* PCM Out Status Register */ __REG 43 arch/arm/mach-pxa/include/mach/regs-ac97.h #define PISR __REG(0x40500014) /* PCM In Status Register */ __REG 48 arch/arm/mach-pxa/include/mach/regs-ac97.h #define MCSR __REG(0x40500018) /* Mic In Status Register */ __REG 53 arch/arm/mach-pxa/include/mach/regs-ac97.h #define GSR __REG(0x4050001C) /* Global Status Register */ __REG 72 arch/arm/mach-pxa/include/mach/regs-ac97.h #define CAR __REG(0x40500020) /* CODEC Access Register */ __REG 75 arch/arm/mach-pxa/include/mach/regs-ac97.h #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ __REG 76 arch/arm/mach-pxa/include/mach/regs-ac97.h #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ __REG 78 arch/arm/mach-pxa/include/mach/regs-ac97.h #define MOCR __REG(0x40500100) /* Modem Out Control Register */ __REG 82 arch/arm/mach-pxa/include/mach/regs-ac97.h #define MICR __REG(0x40500108) /* Modem In Control Register */ __REG 86 arch/arm/mach-pxa/include/mach/regs-ac97.h #define MOSR __REG(0x40500110) /* Modem Out Status Register */ __REG 90 arch/arm/mach-pxa/include/mach/regs-ac97.h #define MISR __REG(0x40500118) /* Modem In Status Register */ __REG 95 arch/arm/mach-pxa/include/mach/regs-ac97.h #define MODR __REG(0x40500140) /* Modem FIFO Data Register */ __REG 97 arch/arm/mach-pxa/include/mach/regs-ac97.h #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ __REG 98 arch/arm/mach-pxa/include/mach/regs-ac97.h #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ __REG 99 arch/arm/mach-pxa/include/mach/regs-ac97.h #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ __REG 100 arch/arm/mach-pxa/include/mach/regs-ac97.h #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ __REG 11 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ __REG 12 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ __REG 13 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ __REG 14 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ __REG 15 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ __REG 16 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ __REG 17 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ __REG 18 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ __REG 19 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ __REG 20 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ __REG 21 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ __REG 22 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ __REG 23 arch/arm/mach-pxa/include/mach/regs-uart.h #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ __REG 27 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ __REG 28 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ __REG 29 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ __REG 30 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ __REG 31 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ __REG 32 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ __REG 33 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ __REG 34 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ __REG 35 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ __REG 36 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ __REG 37 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ __REG 38 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ __REG 39 arch/arm/mach-pxa/include/mach/regs-uart.h #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ __REG 43 arch/arm/mach-pxa/include/mach/regs-uart.h #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ __REG 44 arch/arm/mach-pxa/include/mach/regs-uart.h #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ __REG 45 arch/arm/mach-pxa/include/mach/regs-uart.h #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ __REG 46 arch/arm/mach-pxa/include/mach/regs-uart.h #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ __REG 47 arch/arm/mach-pxa/include/mach/regs-uart.h #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ __REG 48 arch/arm/mach-pxa/include/mach/regs-uart.h #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ __REG 49 arch/arm/mach-pxa/include/mach/regs-uart.h #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ __REG 50 arch/arm/mach-pxa/include/mach/regs-uart.h #define STLSR __REG(0x40700014) /* Line Status Register (read only) */ __REG 51 arch/arm/mach-pxa/include/mach/regs-uart.h #define STMSR __REG(0x40700018) /* Reserved */ __REG 52 arch/arm/mach-pxa/include/mach/regs-uart.h #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ __REG 53 arch/arm/mach-pxa/include/mach/regs-uart.h #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ __REG 54 arch/arm/mach-pxa/include/mach/regs-uart.h #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ __REG 55 arch/arm/mach-pxa/include/mach/regs-uart.h #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ __REG 59 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ __REG 60 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ __REG 61 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ __REG 62 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ __REG 63 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ __REG 64 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ __REG 65 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ __REG 66 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ __REG 67 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ __REG 68 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ __REG 69 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ __REG 70 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ __REG 71 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ __REG 72 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ __REG 73 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ __REG 74 arch/arm/mach-pxa/include/mach/regs-uart.h #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ __REG 9 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCR __REG(0x40600000) /* UDC Control Register */ __REG 33 arch/arm/mach-pxa/pxa27x-udc.h #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ __REG 34 arch/arm/mach-pxa/pxa27x-udc.h #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ __REG 48 arch/arm/mach-pxa/pxa27x-udc.h #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ __REG 49 arch/arm/mach-pxa/pxa27x-udc.h #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ __REG 57 arch/arm/mach-pxa/pxa27x-udc.h #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ __REG 58 arch/arm/mach-pxa/pxa27x-udc.h #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ __REG 85 arch/arm/mach-pxa/pxa27x-udc.h #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ __REG 86 arch/arm/mach-pxa/pxa27x-udc.h #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */ __REG 104 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ __REG 114 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ __REG 115 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ __REG 116 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ __REG 117 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ __REG 118 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ __REG 119 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ __REG 120 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ __REG 121 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ __REG 122 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ __REG 123 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ __REG 124 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ __REG 125 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ __REG 126 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ __REG 127 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ __REG 128 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ __REG 129 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ __REG 130 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ __REG 131 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ __REG 132 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ __REG 133 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ __REG 134 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ __REG 135 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ __REG 136 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ __REG 151 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ __REG 152 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ __REG 153 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ __REG 154 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ __REG 155 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ __REG 156 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ __REG 157 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ __REG 158 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ __REG 159 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ __REG 160 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ __REG 161 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ __REG 162 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ __REG 163 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ __REG 164 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ __REG 165 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ __REG 166 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ __REG 167 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ __REG 168 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ __REG 169 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ __REG 170 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ __REG 171 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ __REG 172 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ __REG 173 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ __REG 174 arch/arm/mach-pxa/pxa27x-udc.h #define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ __REG 179 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ __REG 180 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRA __REG(0x40600304) /* Data Register - EPA */ __REG 181 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRB __REG(0x40600308) /* Data Register - EPB */ __REG 182 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ __REG 183 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRD __REG(0x40600310) /* Data Register - EPD */ __REG 184 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRE __REG(0x40600314) /* Data Register - EPE */ __REG 185 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRF __REG(0x40600318) /* Data Register - EPF */ __REG 186 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ __REG 187 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRH __REG(0x40600320) /* Data Register - EPH */ __REG 188 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRI __REG(0x40600324) /* Data Register - EPI */ __REG 189 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ __REG 190 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ __REG 191 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRL __REG(0x40600330) /* Data Register - EPL */ __REG 192 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRM __REG(0x40600334) /* Data Register - EPM */ __REG 193 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRN __REG(0x40600338) /* Data Register - EPN */ __REG 194 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ __REG 195 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ __REG 196 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRR __REG(0x40600344) /* Data Register - EPR */ __REG 197 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRS __REG(0x40600348) /* Data Register - EPS */ __REG 198 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ __REG 199 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRU __REG(0x40600350) /* Data Register - EPU */ __REG 200 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRV __REG(0x40600354) /* Data Register - EPV */ __REG 201 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRW __REG(0x40600358) /* Data Register - EPW */ __REG 202 arch/arm/mach-pxa/pxa27x-udc.h #define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ __REG 205 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRA __REG(0x40600404) /* Configuration register EPA */ __REG 206 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRB __REG(0x40600408) /* Configuration register EPB */ __REG 207 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ __REG 208 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRD __REG(0x40600410) /* Configuration register EPD */ __REG 209 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRE __REG(0x40600414) /* Configuration register EPE */ __REG 210 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRF __REG(0x40600418) /* Configuration register EPF */ __REG 211 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ __REG 212 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRH __REG(0x40600420) /* Configuration register EPH */ __REG 213 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRI __REG(0x40600424) /* Configuration register EPI */ __REG 214 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ __REG 215 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ __REG 216 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRL __REG(0x40600430) /* Configuration register EPL */ __REG 217 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRM __REG(0x40600434) /* Configuration register EPM */ __REG 218 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRN __REG(0x40600438) /* Configuration register EPN */ __REG 219 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ __REG 220 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ __REG 221 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRR __REG(0x40600444) /* Configuration register EPR */ __REG 222 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRS __REG(0x40600448) /* Configuration register EPS */ __REG 223 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ __REG 224 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRU __REG(0x40600450) /* Configuration register EPU */ __REG 225 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRV __REG(0x40600454) /* Configuration register EPV */ __REG 226 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRW __REG(0x40600458) /* Configuration register EPW */ __REG 227 arch/arm/mach-pxa/pxa27x-udc.h #define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ __REG 11 arch/arm/mach-pxa/pxa27x.h #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ __REG 11 arch/arm/mach-pxa/regs-rtc.h #define RCNR __REG(0x40900000) /* RTC Count Register */ __REG 12 arch/arm/mach-pxa/regs-rtc.h #define RTAR __REG(0x40900004) /* RTC Alarm Register */ __REG 13 arch/arm/mach-pxa/regs-rtc.h #define RTSR __REG(0x40900008) /* RTC Status Register */ __REG 14 arch/arm/mach-pxa/regs-rtc.h #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ __REG 15 arch/arm/mach-pxa/regs-rtc.h #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ __REG 111 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */ __REG 112 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */ __REG 113 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */ __REG 114 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */ __REG 115 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */ __REG 116 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */ __REG 117 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */ __REG 118 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */ __REG 119 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */ __REG 120 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */ __REG 121 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */ __REG 267 arch/arm/mach-sa1100/include/mach/SA-1100.h #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */ __REG 268 arch/arm/mach-sa1100/include/mach/SA-1100.h #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */ __REG 269 arch/arm/mach-sa1100/include/mach/SA-1100.h #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */ __REG 270 arch/arm/mach-sa1100/include/mach/SA-1100.h #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */ __REG 271 arch/arm/mach-sa1100/include/mach/SA-1100.h #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */ __REG 272 arch/arm/mach-sa1100/include/mach/SA-1100.h #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */ __REG 273 arch/arm/mach-sa1100/include/mach/SA-1100.h #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */ __REG 274 arch/arm/mach-sa1100/include/mach/SA-1100.h #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */ __REG 429 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */ __REG 430 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */ __REG 431 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */ __REG 432 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */ __REG 433 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */ __REG 434 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */ __REG 435 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */ __REG 436 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */ __REG 543 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */ __REG 544 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */ __REG 545 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */ __REG 546 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */ __REG 547 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */ __REG 548 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */ __REG 630 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */ __REG 631 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */ __REG 632 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */ __REG 633 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */ __REG 634 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */ __REG 635 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */ __REG 753 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */ __REG 754 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */ __REG 755 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */ __REG 756 arch/arm/mach-sa1100/include/mach/SA-1100.h #define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */ __REG 884 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PMCR __REG(0x90020000) /* PM Control Reg. */ __REG 885 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */ __REG 886 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */ __REG 887 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */ __REG 888 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */ __REG 889 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */ __REG 890 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */ __REG 891 arch/arm/mach-sa1100/include/mach/SA-1100.h #define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */ __REG 1025 arch/arm/mach-sa1100/include/mach/SA-1100.h #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */ __REG 1026 arch/arm/mach-sa1100/include/mach/SA-1100.h #define RCSR __REG(0x90030004) /* RC Status Reg. */ __REG 1043 arch/arm/mach-sa1100/include/mach/SA-1100.h #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */ __REG 1105 arch/arm/mach-sa1100/include/mach/SA-1100.h #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */ __REG 1106 arch/arm/mach-sa1100/include/mach/SA-1100.h #define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */ __REG 1107 arch/arm/mach-sa1100/include/mach/SA-1100.h #define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */ __REG 1108 arch/arm/mach-sa1100/include/mach/SA-1100.h #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */ __REG 1109 arch/arm/mach-sa1100/include/mach/SA-1100.h #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */ __REG 1110 arch/arm/mach-sa1100/include/mach/SA-1100.h #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */ __REG 1111 arch/arm/mach-sa1100/include/mach/SA-1100.h #define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */ __REG 1112 arch/arm/mach-sa1100/include/mach/SA-1100.h #define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */ __REG 1210 arch/arm/mach-sa1100/include/mach/SA-1100.h #define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */ __REG 1211 arch/arm/mach-sa1100/include/mach/SA-1100.h #define ICMR __REG(0x90050004) /* IC Mask Reg. */ __REG 1212 arch/arm/mach-sa1100/include/mach/SA-1100.h #define ICLR __REG(0x90050008) /* IC Level Reg. */ __REG 1213 arch/arm/mach-sa1100/include/mach/SA-1100.h #define ICCR __REG(0x9005000C) /* IC Control Reg. */ __REG 1214 arch/arm/mach-sa1100/include/mach/SA-1100.h #define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */ __REG 1215 arch/arm/mach-sa1100/include/mach/SA-1100.h #define ICPR __REG(0x90050020) /* IC Pending Reg. */ __REG 1283 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */ __REG 1284 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PPSR __REG(0x90060004) /* PPC Pin State Reg. */ __REG 1285 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */ __REG 1286 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */ __REG 1287 arch/arm/mach-sa1100/include/mach/SA-1100.h #define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */ __REG 1368 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */ __REG 1369 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */ __REG 1370 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */ __REG 1371 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */ __REG 1443 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */ __REG 1444 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */ __REG 1445 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */ __REG 1513 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */ __REG 1541 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDREFR __REG(0xA000001C) __REG 102 arch/xtensa/include/asm/coprocessor.h __REG ## list (cc, abi, type, name, size, align) __REG 32 sound/soc/pxa/pxa2xx-i2s.c #define SACR0 __REG(0x40400000) /* Global Control Register */ __REG 33 sound/soc/pxa/pxa2xx-i2s.c #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ __REG 34 sound/soc/pxa/pxa2xx-i2s.c #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ __REG 35 sound/soc/pxa/pxa2xx-i2s.c #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ __REG 36 sound/soc/pxa/pxa2xx-i2s.c #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ __REG 37 sound/soc/pxa/pxa2xx-i2s.c #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ __REG 38 sound/soc/pxa/pxa2xx-i2s.c #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */