__MASK 72 arch/powerpc/include/asm/reg.h #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ __MASK 73 arch/powerpc/include/asm/reg.h #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ __MASK 74 arch/powerpc/include/asm/reg.h #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ __MASK 75 arch/powerpc/include/asm/reg.h #define MSR_S __MASK(MSR_S_LG) /* Secure state */ __MASK 92 arch/powerpc/include/asm/reg.h #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ __MASK 93 arch/powerpc/include/asm/reg.h #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */ __MASK 94 arch/powerpc/include/asm/reg.h #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ __MASK 95 arch/powerpc/include/asm/reg.h #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ __MASK 96 arch/powerpc/include/asm/reg.h #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ __MASK 97 arch/powerpc/include/asm/reg.h #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */ __MASK 98 arch/powerpc/include/asm/reg.h #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */ __MASK 99 arch/powerpc/include/asm/reg.h #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */ __MASK 100 arch/powerpc/include/asm/reg.h #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */ __MASK 101 arch/powerpc/include/asm/reg.h #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */ __MASK 102 arch/powerpc/include/asm/reg.h #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */ __MASK 103 arch/powerpc/include/asm/reg.h #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */ __MASK 104 arch/powerpc/include/asm/reg.h #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */ __MASK 105 arch/powerpc/include/asm/reg.h #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */ __MASK 106 arch/powerpc/include/asm/reg.h #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */ __MASK 107 arch/powerpc/include/asm/reg.h #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */ __MASK 108 arch/powerpc/include/asm/reg.h #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */ __MASK 109 arch/powerpc/include/asm/reg.h #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */ __MASK 110 arch/powerpc/include/asm/reg.h #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */ __MASK 111 arch/powerpc/include/asm/reg.h #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */ __MASK 112 arch/powerpc/include/asm/reg.h #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */ __MASK 114 arch/powerpc/include/asm/reg.h #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */ __MASK 116 arch/powerpc/include/asm/reg.h #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ __MASK 117 arch/powerpc/include/asm/reg.h #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ __MASK 119 arch/powerpc/include/asm/reg.h #define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */ __MASK 121 arch/powerpc/include/asm/reg.h #define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */ __MASK 122 arch/powerpc/include/asm/reg.h #define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */ __MASK 269 arch/powerpc/include/asm/reg.h #define TEXASR_ABORT __MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */ __MASK 270 arch/powerpc/include/asm/reg.h #define TEXASR_SUSP __MASK(TEXASR_SU_LG) /* tx failed in suspended state */ __MASK 271 arch/powerpc/include/asm/reg.h #define TEXASR_HV __MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */ __MASK 272 arch/powerpc/include/asm/reg.h #define TEXASR_PR __MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */ __MASK 273 arch/powerpc/include/asm/reg.h #define TEXASR_FS __MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */ __MASK 274 arch/powerpc/include/asm/reg.h #define TEXASR_EXACT __MASK(TEXASR_EX_LG) /* TFIAR value is exact */ __MASK 275 arch/powerpc/include/asm/reg.h #define TEXASR_ROT __MASK(TEXASR_ROT_LG) __MASK 296 arch/powerpc/include/asm/reg.h #define DAWRX_USER __MASK(0) __MASK 297 arch/powerpc/include/asm/reg.h #define DAWRX_KERNEL __MASK(1) __MASK 298 arch/powerpc/include/asm/reg.h #define DAWRX_HYP __MASK(2) __MASK 299 arch/powerpc/include/asm/reg.h #define DAWRX_WTI __MASK(3) __MASK 300 arch/powerpc/include/asm/reg.h #define DAWRX_WT __MASK(4) __MASK 301 arch/powerpc/include/asm/reg.h #define DAWRX_DR __MASK(5) __MASK 302 arch/powerpc/include/asm/reg.h #define DAWRX_DW __MASK(6) __MASK 306 arch/powerpc/include/asm/reg.h #define DABRX_USER __MASK(0) __MASK 307 arch/powerpc/include/asm/reg.h #define DABRX_KERNEL __MASK(1) __MASK 308 arch/powerpc/include/asm/reg.h #define DABRX_HYP __MASK(2) __MASK 309 arch/powerpc/include/asm/reg.h #define DABRX_BTI __MASK(3) __MASK 413 arch/powerpc/include/asm/reg.h #define FSCR_SCV __MASK(FSCR_SCV_LG) __MASK 414 arch/powerpc/include/asm/reg.h #define FSCR_TAR __MASK(FSCR_TAR_LG) __MASK 415 arch/powerpc/include/asm/reg.h #define FSCR_EBB __MASK(FSCR_EBB_LG) __MASK 416 arch/powerpc/include/asm/reg.h #define FSCR_DSCR __MASK(FSCR_DSCR_LG) __MASK 418 arch/powerpc/include/asm/reg.h #define HFSCR_MSGP __MASK(FSCR_MSGP_LG) __MASK 419 arch/powerpc/include/asm/reg.h #define HFSCR_TAR __MASK(FSCR_TAR_LG) __MASK 420 arch/powerpc/include/asm/reg.h #define HFSCR_EBB __MASK(FSCR_EBB_LG) __MASK 421 arch/powerpc/include/asm/reg.h #define HFSCR_TM __MASK(FSCR_TM_LG) __MASK 422 arch/powerpc/include/asm/reg.h #define HFSCR_PM __MASK(FSCR_PM_LG) __MASK 423 arch/powerpc/include/asm/reg.h #define HFSCR_BHRB __MASK(FSCR_BHRB_LG) __MASK 424 arch/powerpc/include/asm/reg.h #define HFSCR_DSCR __MASK(FSCR_DSCR_LG) __MASK 425 arch/powerpc/include/asm/reg.h #define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG) __MASK 426 arch/powerpc/include/asm/reg.h #define HFSCR_FP __MASK(FSCR_FP_LG) __MASK 478 arch/powerpc/include/asm/reg.h #define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */ __MASK 479 arch/powerpc/include/asm/reg.h #define PCR_VSX_DIS (__MASK(63-1)) /* VSX disable (bit NA since POWER8) */ __MASK 480 arch/powerpc/include/asm/reg.h #define PCR_TM_DIS (__MASK(63-2)) /* Trans. memory disable (POWER8) */ __MASK 582 arch/powerpc/include/asm/reg.h #define HID0_POWER8_4LPARMODE __MASK(61) __MASK 583 arch/powerpc/include/asm/reg.h #define HID0_POWER8_2LPARMODE __MASK(57) __MASK 584 arch/powerpc/include/asm/reg.h #define HID0_POWER8_1TO2LPAR __MASK(52) __MASK 585 arch/powerpc/include/asm/reg.h #define HID0_POWER8_1TO4LPAR __MASK(51) __MASK 586 arch/powerpc/include/asm/reg.h #define HID0_POWER8_DYNLPARDIS __MASK(48) __MASK 589 arch/powerpc/include/asm/reg.h #define HID0_POWER9_RADIX __MASK(63 - 8) __MASK 28 arch/powerpc/include/asm/reg_booke.h #define MSR_GS __MASK(MSR_GS_LG) __MASK 29 arch/powerpc/include/asm/reg_booke.h #define MSR_UCLE __MASK(MSR_UCLE_LG) __MASK 30 arch/powerpc/include/asm/reg_booke.h #define MSR_SPE __MASK(MSR_SPE_LG) __MASK 31 arch/powerpc/include/asm/reg_booke.h #define MSR_DWE __MASK(MSR_DWE_LG) __MASK 32 arch/powerpc/include/asm/reg_booke.h #define MSR_UBLE __MASK(MSR_UBLE_LG) __MASK 33 arch/powerpc/include/asm/reg_booke.h #define MSR_IS __MASK(MSR_IS_LG) __MASK 34 arch/powerpc/include/asm/reg_booke.h #define MSR_DS __MASK(MSR_DS_LG) __MASK 35 arch/powerpc/include/asm/reg_booke.h #define MSR_PMM __MASK(MSR_PMM_LG) __MASK 36 arch/powerpc/include/asm/reg_booke.h #define MSR_CM __MASK(MSR_CM_LG) __MASK 13 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c #define EXTRACT(val, field) (((val) & field##__MASK) >> field##__SHIFT) __MASK 172 drivers/gpu/drm/etnaviv/etnaviv_gpu.c (((val) & field##__MASK) >> field##__SHIFT) __MASK 443 drivers/gpu/drm/msm/msm_drv.h #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) __MASK 87 tools/testing/selftests/powerpc/include/reg.h #define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */ __MASK 88 tools/testing/selftests/powerpc/include/reg.h #define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */