BR 125 arch/powerpc/xmon/spu-insns.h APUOP(M_BR, RI16, 0x190, "br", _A1(A_R18), 00000, BR) /* BRel IP<-IP+I16 */ BR 126 arch/powerpc/xmon/spu-insns.h APUOP(M_BRSL, RI16, 0x198, "brsl", _A2(A_T,A_R18), 00002, BR) /* BRelSetLink RT,IP<-IP,IP+I16 */ BR 127 arch/powerpc/xmon/spu-insns.h APUOP(M_BRA, RI16, 0x180, "bra", _A1(A_S18), 00000, BR) /* BRAbs IP<-I16 */ BR 128 arch/powerpc/xmon/spu-insns.h APUOP(M_BRASL, RI16, 0x188, "brasl", _A2(A_T,A_S18), 00002, BR) /* BRAbsSetLink RT,IP<-IP,I16 */ BR 132 arch/powerpc/xmon/spu-insns.h APUOP(M_STOP, RR, 0x000, "stop", _A0(), 00000, BR) /* STOP stop */ BR 133 arch/powerpc/xmon/spu-insns.h APUOP(M_STOP2, RR, 0x000, "stop", _A1(A_U14), 00000, BR) /* STOP stop */ BR 134 arch/powerpc/xmon/spu-insns.h APUOP(M_STOPD, RR, 0x140, "stopd", _A3(A_T,A_A,A_B), 00111, BR) /* STOPD stop (with register dependencies) */ BR 136 arch/powerpc/xmon/spu-insns.h APUOP(M_SYNC, RR, 0x002, "sync", _A0(), 00000, BR) /* SYNC flush_pipe */ BR 137 arch/powerpc/xmon/spu-insns.h APUOP(M_DSYNC, RR, 0x003, "dsync", _A0(), 00000, BR) /* DSYNC flush_store_queue */ BR 143 arch/powerpc/xmon/spu-insns.h APUOP(M_BRZ, RI16, 0x100, "brz", _A2(A_T,A_R18), 00001, BR) /* BRZ IP<-IP+I16_if(RT) */ BR 144 arch/powerpc/xmon/spu-insns.h APUOP(M_BRNZ, RI16, 0x108, "brnz", _A2(A_T,A_R18), 00001, BR) /* BRNZ IP<-IP+I16_if(RT) */ BR 145 arch/powerpc/xmon/spu-insns.h APUOP(M_BRHZ, RI16, 0x110, "brhz", _A2(A_T,A_R18), 00001, BR) /* BRHZ IP<-IP+I16_if(RT) */ BR 146 arch/powerpc/xmon/spu-insns.h APUOP(M_BRHNZ, RI16, 0x118, "brhnz", _A2(A_T,A_R18), 00001, BR) /* BRHNZ IP<-IP+I16_if(RT) */ BR 152 arch/powerpc/xmon/spu-insns.h APUOP(M_BI, RR, 0x1a8, "bi", _A1(A_A), 00010, BR) /* BI IP<-RA */ BR 153 arch/powerpc/xmon/spu-insns.h APUOP(M_BISL, RR, 0x1a9, "bisl", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ BR 154 arch/powerpc/xmon/spu-insns.h APUOP(M_IRET, RR, 0x1aa, "iret", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ BR 155 arch/powerpc/xmon/spu-insns.h APUOP(M_IRET2, RR, 0x1aa, "iret", _A0(), 00010, BR) /* IRET IP<-SRR0 */ BR 156 arch/powerpc/xmon/spu-insns.h APUOP(M_BISLED, RR, 0x1ab, "bisled", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ BR 177 arch/powerpc/xmon/spu-insns.h APUOP(M_BIHNZ, RR, 0x12b, "bihnz", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ BR 178 arch/powerpc/xmon/spu-insns.h APUOP(M_BIHZ, RR, 0x12a, "bihz", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ BR 179 arch/powerpc/xmon/spu-insns.h APUOP(M_BINZ, RR, 0x129, "binz", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ BR 180 arch/powerpc/xmon/spu-insns.h APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ BR 210 arch/powerpc/xmon/spu-insns.h APUOP(M_ORX, RR, 0x1f0, "orx", _A2(A_T,A_A), 00012, BR) /* ORX RT<-RA.w0|RA.w1|RA.w2|RA.w3 */ BR 359 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BID, RR, 0x1a8, 0x20, "bid", _A1(A_A), 00010, BR) /* BI IP<-RA */ BR 360 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIE, RR, 0x1a8, 0x10, "bie", _A1(A_A), 00010, BR) /* BI IP<-RA */ BR 361 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BISLD, RR, 0x1a9, 0x20, "bisld", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ BR 362 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BISLE, RR, 0x1a9, 0x10, "bisle", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ BR 363 arch/powerpc/xmon/spu-insns.h APUOPFB(M_IRETD, RR, 0x1aa, 0x20, "iretd", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ BR 364 arch/powerpc/xmon/spu-insns.h APUOPFB(M_IRETD2, RR, 0x1aa, 0x20, "iretd", _A0(), 00010, BR) /* IRET IP<-SRR0 */ BR 365 arch/powerpc/xmon/spu-insns.h APUOPFB(M_IRETE, RR, 0x1aa, 0x10, "irete", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ BR 366 arch/powerpc/xmon/spu-insns.h APUOPFB(M_IRETE2, RR, 0x1aa, 0x10, "irete", _A0(), 00010, BR) /* IRET IP<-SRR0 */ BR 367 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BISLEDD, RR, 0x1ab, 0x20, "bisledd", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ BR 368 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BISLEDE, RR, 0x1ab, 0x10, "bislede", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ BR 369 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHNZD, RR, 0x12b, 0x20, "bihnzd", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ BR 370 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHNZE, RR, 0x12b, 0x10, "bihnze", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ BR 371 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHZD, RR, 0x12a, 0x20, "bihzd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ BR 372 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHZE, RR, 0x12a, 0x10, "bihze", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ BR 373 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BINZD, RR, 0x129, 0x20, "binzd", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ BR 374 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BINZE, RR, 0x129, 0x10, "binze", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ BR 375 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ BR 376 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ BR 377 arch/powerpc/xmon/spu-insns.h APUOPFB(M_SYNCC, RR, 0x002, 0x40, "syncc", _A0(), 00000, BR) /* SYNCC flush_pipe */ BR 382 arch/powerpc/xmon/spu-insns.h APUOP(M_BIHT, RR, 0x12b, "biht", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ BR 383 arch/powerpc/xmon/spu-insns.h APUOP(M_BIHF, RR, 0x12a, "bihf", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ BR 384 arch/powerpc/xmon/spu-insns.h APUOP(M_BIT, RR, 0x129, "bit", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ BR 385 arch/powerpc/xmon/spu-insns.h APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ BR 386 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHTD, RR, 0x12b, 0x20, "bihtd", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ BR 387 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHTE, RR, 0x12b, 0x10, "bihte", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ BR 388 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHFD, RR, 0x12a, 0x20, "bihfd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ BR 389 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIHFE, RR, 0x12a, 0x10, "bihfe", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ BR 390 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BITD, RR, 0x129, 0x20, "bitd", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ BR 391 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BITE, RR, 0x129, 0x10, "bite", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ BR 392 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ BR 393 arch/powerpc/xmon/spu-insns.h APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ BR 276 arch/x86/kvm/trace.h EXS(DE), EXS(DB), EXS(BP), EXS(OF), EXS(BR), EXS(UD), EXS(NM), \ BR 103 arch/xtensa/variants/csp/include/variant/tie-asm.h rsr.BR \at1 // boolean option BR 170 arch/xtensa/variants/csp/include/variant/tie-asm.h wsr.BR \at1 // boolean option BR 103 arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h rsr.BR \at1 // boolean option BR 170 arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h wsr.BR \at1 // boolean option BR 112 arch/xtensa/variants/test_kc705_hifi/include/variant/tie-asm.h rsr.BR \at1 // boolean option BR 179 arch/xtensa/variants/test_kc705_hifi/include/variant/tie-asm.h wsr.BR \at1 // boolean option BR 40 arch/xtensa/variants/test_mmuhifi_c3/include/variant/tie-asm.h rsr \at1, BR // boolean option BR 68 arch/xtensa/variants/test_mmuhifi_c3/include/variant/tie-asm.h wsr \at1, BR // boolean option BR 143 drivers/video/fbdev/sis/sis_accel.h while((MMIO_IN16(ivideo->mmio_vbase, BR(16)+2) & 0xE000) != 0xE000){}; \ BR 144 drivers/video/fbdev/sis/sis_accel.h while((MMIO_IN16(ivideo->mmio_vbase, BR(16)+2) & 0xE000) != 0xE000){}; \ BR 145 drivers/video/fbdev/sis/sis_accel.h while((MMIO_IN16(ivideo->mmio_vbase, BR(16)+2) & 0xE000) != 0xE000){}; \ BR 152 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(0), base);\ BR 157 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT16(ivideo->mmio_vbase, BR(1), pitch);\ BR 162 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(2), (x)<<16 | (y) );\ BR 167 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(4), base);\ BR 172 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(3), (x)<<16 | (y) );\ BR 177 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(5), (y)<<16 | (x) );\ BR 182 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT16(ivideo->mmio_vbase, BR(1)+2, bpp);\ BR 187 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(6), (h)<<16 | (w) );\ BR 192 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(7), color);\ BR 197 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(8), color);\ BR 202 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(9), color);\ BR 207 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(10), color);\ BR 228 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(11), p0);\ BR 229 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(12), p1);\ BR 234 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(13), ((left) & 0xFFFF) | (top)<<16 );\ BR 239 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(14), ((right) & 0xFFFF) | (bottom)<<16 );\ BR 251 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(15), ivideo->CommandReg); \ BR 252 drivers/video/fbdev/sis/sis_accel.h MMIO_OUT32(ivideo->mmio_vbase, BR(16), 0);\