_SB_MAKE64 833 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) _SB_MAKE64 834 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) _SB_MAKE64 835 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) _SB_MAKE64 836 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) _SB_MAKE64 837 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000) _SB_MAKE64 838 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000) _SB_MAKE64 839 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000) _SB_MAKE64 840 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000) _SB_MAKE64 841 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000) _SB_MAKE64 842 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000) _SB_MAKE64 843 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000) _SB_MAKE64 844 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000) _SB_MAKE64 845 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000) _SB_MAKE64 846 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000) _SB_MAKE64 847 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) _SB_MAKE64 848 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) _SB_MAKE64 849 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000) _SB_MAKE64 850 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000) _SB_MAKE64 851 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000) _SB_MAKE64 852 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000) _SB_MAKE64 853 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000) _SB_MAKE64 854 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000) _SB_MAKE64 855 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) _SB_MAKE64 856 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) _SB_MAKE64 857 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) _SB_MAKE64 858 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) _SB_MAKE64 859 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) _SB_MAKE64 860 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000) _SB_MAKE64 861 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) _SB_MAKE64 862 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) _SB_MAKE64 863 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) _SB_MAKE64 864 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) _SB_MAKE64 865 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) _SB_MAKE64 866 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000) _SB_MAKE64 867 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000) _SB_MAKE64 868 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000) _SB_MAKE64 869 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000) _SB_MAKE64 870 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000) _SB_MAKE64 877 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) _SB_MAKE64 879 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000) _SB_MAKE64 880 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000) _SB_MAKE64 881 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000) _SB_MAKE64 882 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000) _SB_MAKE64 883 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000) _SB_MAKE64 884 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000) _SB_MAKE64 885 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000) _SB_MAKE64 886 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000) _SB_MAKE64 887 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000) _SB_MAKE64 88 arch/mips/include/asm/sibyte/bcm1480_scd.h #define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) _SB_MAKE64 93 arch/mips/include/asm/sibyte/bcm1480_scd.h #define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) _SB_MAKE64 101 arch/mips/include/asm/sibyte/bcm1480_scd.h #define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) _SB_MAKE64 215 arch/mips/include/asm/sibyte/sb1250_defs.h #define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n)) _SB_MAKE64 222 arch/mips/include/asm/sibyte/sb1250_defs.h #define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) _SB_MAKE64 229 arch/mips/include/asm/sibyte/sb1250_defs.h #define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n)) _SB_MAKE64 232 arch/mips/include/asm/sibyte/sb1250_defs.h #define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) _SB_MAKE64 46 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DESC_TYPE _SB_MAKE64(1) _SB_MAKE64 65 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_INT_PKTCNT _SB_MAKE64(8) _SB_MAKE64 70 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_RINGSZ _SB_MAKE64(16) _SB_MAKE64 75 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) _SB_MAKE64 80 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_LOW_WATERMARK _SB_MAKE64(48) _SB_MAKE64 108 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_HDR_SIZE _SB_MAKE64(21) _SB_MAKE64 115 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) _SB_MAKE64 120 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_INT_TIMEOUT _SB_MAKE64(48) _SB_MAKE64 149 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) _SB_MAKE64 151 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) _SB_MAKE64 162 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_OODLOST_RX _SB_MAKE64(0) _SB_MAKE64 166 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) _SB_MAKE64 179 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) _SB_MAKE64 185 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) _SB_MAKE64 191 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) _SB_MAKE64 195 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) _SB_MAKE64 201 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) _SB_MAKE64 209 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRA_STATUS _SB_MAKE64(51) _SB_MAKE64 219 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) _SB_MAKE64 225 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) _SB_MAKE64 231 arch/mips/include/asm/sibyte/sb1250_dma.h #define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) _SB_MAKE64 234 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) _SB_MAKE64 237 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) _SB_MAKE64 245 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) _SB_MAKE64 251 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) _SB_MAKE64 259 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DMA_DSCRB_STATUS _SB_MAKE64(0) _SB_MAKE64 318 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00) _SB_MAKE64 319 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01) _SB_MAKE64 320 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02) _SB_MAKE64 321 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03) _SB_MAKE64 322 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04) _SB_MAKE64 323 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05) _SB_MAKE64 324 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6) _SB_MAKE64 325 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07) _SB_MAKE64 326 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08) _SB_MAKE64 327 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09) _SB_MAKE64 328 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A) _SB_MAKE64 329 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B) _SB_MAKE64 330 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C) _SB_MAKE64 331 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D) _SB_MAKE64 332 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E) _SB_MAKE64 333 arch/mips/include/asm/sibyte/sb1250_dma.h #define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F) _SB_MAKE64 378 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) _SB_MAKE64 381 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) _SB_MAKE64 386 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) _SB_MAKE64 418 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) _SB_MAKE64 421 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) _SB_MAKE64 436 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0) _SB_MAKE64 442 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) _SB_MAKE64 458 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) _SB_MAKE64 464 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) _SB_MAKE64 478 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) _SB_MAKE64 484 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) _SB_MAKE64 490 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) _SB_MAKE64 508 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) _SB_MAKE64 518 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) _SB_MAKE64 531 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) _SB_MAKE64 572 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) _SB_MAKE64 575 arch/mips/include/asm/sibyte/sb1250_dma.h #define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) _SB_MAKE64 111 arch/mips/include/asm/sibyte/sb1250_genbus.h #define S_IO_BURST_WIDTH _SB_MAKE64(6) _SB_MAKE64 44 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TX_PAUSE _SB_MAKE64(6) _SB_MAKE64 86 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_SPEED_SEL _SB_MAKE64(34) _SB_MAKE64 106 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_BYPASS_CFG _SB_MAKE64(40) _SB_MAKE64 127 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_BYPASS_IFG _SB_MAKE64(46) _SB_MAKE64 142 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_FC_CMD _SB_MAKE64(55) _SB_MAKE64 147 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_CH_SEL _SB_MAKE64(57) _SB_MAKE64 191 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) _SB_MAKE64 196 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) _SB_MAKE64 208 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TX_WR_THRSH _SB_MAKE64(0) _SB_MAKE64 219 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TX_RD_THRSH _SB_MAKE64(8) _SB_MAKE64 230 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TX_RL_THRSH _SB_MAKE64(16) _SB_MAKE64 235 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_PL_THRSH _SB_MAKE64(24) _SB_MAKE64 240 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_RD_THRSH _SB_MAKE64(32) _SB_MAKE64 245 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_RL_THRSH _SB_MAKE64(40) _SB_MAKE64 251 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) _SB_MAKE64 265 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_IFG_RX _SB_MAKE64(0) _SB_MAKE64 271 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_PRE_LEN _SB_MAKE64(0) _SB_MAKE64 277 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_IFG_TX _SB_MAKE64(6) _SB_MAKE64 282 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_IFG_THRSH _SB_MAKE64(12) _SB_MAKE64 287 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_BACKOFF_SEL _SB_MAKE64(18) _SB_MAKE64 292 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_LFSR_SEED _SB_MAKE64(22) _SB_MAKE64 297 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_SLOT_SIZE _SB_MAKE64(30) _SB_MAKE64 302 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) _SB_MAKE64 307 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) _SB_MAKE64 317 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ _SB_MAKE64 318 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_IFG_RX_100 _SB_MAKE64(0) _SB_MAKE64 319 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_IFG_RX_1000 _SB_MAKE64(0) _SB_MAKE64 321 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_IFG_TX_10 _SB_MAKE64(20) _SB_MAKE64 322 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_IFG_TX_100 _SB_MAKE64(20) _SB_MAKE64 323 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_IFG_TX_1000 _SB_MAKE64(8) _SB_MAKE64 325 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) _SB_MAKE64 326 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) _SB_MAKE64 327 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) _SB_MAKE64 329 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) _SB_MAKE64 330 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) _SB_MAKE64 331 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) _SB_MAKE64 349 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) _SB_MAKE64 350 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) _SB_MAKE64 351 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) _SB_MAKE64 352 arch/mips/include/asm/sibyte/sb1250_mac.h #define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) _SB_MAKE64 366 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_VLAN_TAG _SB_MAKE64(0) _SB_MAKE64 372 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) _SB_MAKE64 377 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) _SB_MAKE64 402 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_CH0 _SB_MAKE64(0) _SB_MAKE64 403 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_CH1 _SB_MAKE64(8) _SB_MAKE64 404 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TX_CH0 _SB_MAKE64(16) _SB_MAKE64 405 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TX_CH1 _SB_MAKE64(24) _SB_MAKE64 407 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ _SB_MAKE64 408 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ _SB_MAKE64 430 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) _SB_MAKE64 456 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_COUNTER_ADDR _SB_MAKE64(47) _SB_MAKE64 472 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TX_WRPTR _SB_MAKE64(0) _SB_MAKE64 477 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TX_RDPTR _SB_MAKE64(8) _SB_MAKE64 482 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_WRPTR _SB_MAKE64(16) _SB_MAKE64 487 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_RDPTR _SB_MAKE64(24) _SB_MAKE64 499 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) _SB_MAKE64 504 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) _SB_MAKE64 552 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_TYPECFG_TYPESIZE _SB_MAKE64(16) _SB_MAKE64 554 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_TYPECFG_TYPE0 _SB_MAKE64(0) _SB_MAKE64 559 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_TYPECFG_TYPE1 _SB_MAKE64(0) _SB_MAKE64 564 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_TYPECFG_TYPE2 _SB_MAKE64(0) _SB_MAKE64 569 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_TYPECFG_TYPE3 _SB_MAKE64(0) _SB_MAKE64 592 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) _SB_MAKE64 598 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) _SB_MAKE64 603 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) _SB_MAKE64 611 arch/mips/include/asm/sibyte/sb1250_mac.h #define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) _SB_MAKE64 844 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) _SB_MAKE64 845 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) _SB_MAKE64 846 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) _SB_MAKE64 847 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) _SB_MAKE64 848 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) _SB_MAKE64 849 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) _SB_MAKE64 850 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) _SB_MAKE64 851 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) _SB_MAKE64 852 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) _SB_MAKE64 853 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) _SB_MAKE64 854 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) _SB_MAKE64 855 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) _SB_MAKE64 856 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) _SB_MAKE64 857 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) _SB_MAKE64 858 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) _SB_MAKE64 859 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) _SB_MAKE64 860 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) _SB_MAKE64 861 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) _SB_MAKE64 862 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) _SB_MAKE64 863 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) _SB_MAKE64 864 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) _SB_MAKE64 865 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) _SB_MAKE64 866 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) _SB_MAKE64 867 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) _SB_MAKE64 868 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) _SB_MAKE64 870 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) _SB_MAKE64 872 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) _SB_MAKE64 873 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) _SB_MAKE64 874 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) _SB_MAKE64 875 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) _SB_MAKE64 876 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) _SB_MAKE64 34 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_REVISION _SB_MAKE64(8) _SB_MAKE64 83 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_L2C_SIZE _SB_MAKE64(20) _SB_MAKE64 99 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_NUM_CPUS _SB_MAKE64(24) _SB_MAKE64 106 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_PART _SB_MAKE64(16) _SB_MAKE64 120 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_SOC_TYPE _SB_MAKE64(16) _SB_MAKE64 159 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_WID _SB_MAKE64(32) _SB_MAKE64 171 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_WAFERID1_200 _SB_MAKE64(0) _SB_MAKE64 176 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_BIN _SB_MAKE64(32) _SB_MAKE64 182 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_WAFERID2_200 _SB_MAKE64(36) _SB_MAKE64 188 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_WAFERID_300 _SB_MAKE64(0) _SB_MAKE64 193 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_XPOS _SB_MAKE64(40) _SB_MAKE64 198 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_YPOS _SB_MAKE64(46) _SB_MAKE64 216 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_PLL_DIV _SB_MAKE64(7) _SB_MAKE64 227 arch/mips/include/asm/sibyte/sb1250_scd.h #define S_SYS_BOOT_MODE _SB_MAKE64(17) _SB_MAKE64 334 arch/mips/include/asm/sibyte/sb1250_uart.h #define S_DUART_SIG_FULL _SB_MAKE64(0) _SB_MAKE64 339 arch/mips/include/asm/sibyte/sb1250_uart.h #define S_DUART_INT_TIME _SB_MAKE64(4)