_MMIO_TRANS2     4130 drivers/gpu/drm/i915/i915_reg.h #define PIPE_CRC_CTL(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
_MMIO_TRANS2     4131 drivers/gpu/drm/i915/i915_reg.h #define PIPE_CRC_RES_1_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
_MMIO_TRANS2     4132 drivers/gpu/drm/i915/i915_reg.h #define PIPE_CRC_RES_2_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
_MMIO_TRANS2     4133 drivers/gpu/drm/i915/i915_reg.h #define PIPE_CRC_RES_3_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
_MMIO_TRANS2     4134 drivers/gpu/drm/i915/i915_reg.h #define PIPE_CRC_RES_4_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
_MMIO_TRANS2     4135 drivers/gpu/drm/i915/i915_reg.h #define PIPE_CRC_RES_5_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
_MMIO_TRANS2     4137 drivers/gpu/drm/i915/i915_reg.h #define PIPE_CRC_RES_RED(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
_MMIO_TRANS2     4138 drivers/gpu/drm/i915/i915_reg.h #define PIPE_CRC_RES_GREEN(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
_MMIO_TRANS2     4139 drivers/gpu/drm/i915/i915_reg.h #define PIPE_CRC_RES_BLUE(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
_MMIO_TRANS2     4140 drivers/gpu/drm/i915/i915_reg.h #define PIPE_CRC_RES_RES1_I915(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
_MMIO_TRANS2     4141 drivers/gpu/drm/i915/i915_reg.h #define PIPE_CRC_RES_RES2_G4X(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
_MMIO_TRANS2     4190 drivers/gpu/drm/i915/i915_reg.h #define HTOTAL(trans)		_MMIO_TRANS2(trans, _HTOTAL_A)
_MMIO_TRANS2     4191 drivers/gpu/drm/i915/i915_reg.h #define HBLANK(trans)		_MMIO_TRANS2(trans, _HBLANK_A)
_MMIO_TRANS2     4192 drivers/gpu/drm/i915/i915_reg.h #define HSYNC(trans)		_MMIO_TRANS2(trans, _HSYNC_A)
_MMIO_TRANS2     4193 drivers/gpu/drm/i915/i915_reg.h #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
_MMIO_TRANS2     4194 drivers/gpu/drm/i915/i915_reg.h #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
_MMIO_TRANS2     4195 drivers/gpu/drm/i915/i915_reg.h #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
_MMIO_TRANS2     4196 drivers/gpu/drm/i915/i915_reg.h #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
_MMIO_TRANS2     4197 drivers/gpu/drm/i915/i915_reg.h #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
_MMIO_TRANS2     4198 drivers/gpu/drm/i915/i915_reg.h #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
_MMIO_TRANS2     4199 drivers/gpu/drm/i915/i915_reg.h #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
_MMIO_TRANS2     4309 drivers/gpu/drm/i915/i915_reg.h #define PSR_EVENT(trans)			_MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
_MMIO_TRANS2     6288 drivers/gpu/drm/i915/i915_reg.h #define CHV_BLEND(pipe)		_MMIO_TRANS2(pipe, _CHV_BLEND_A)
_MMIO_TRANS2     6289 drivers/gpu/drm/i915/i915_reg.h #define CHV_CANVAS(pipe)	_MMIO_TRANS2(pipe, _CHV_CANVAS_A)
_MMIO_TRANS2     6290 drivers/gpu/drm/i915/i915_reg.h #define PRIMPOS(plane)		_MMIO_TRANS2(plane, _PRIMPOS_A)
_MMIO_TRANS2     6291 drivers/gpu/drm/i915/i915_reg.h #define PRIMSIZE(plane)		_MMIO_TRANS2(plane, _PRIMSIZE_A)
_MMIO_TRANS2     6292 drivers/gpu/drm/i915/i915_reg.h #define PRIMCNSTALPHA(plane)	_MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
_MMIO_TRANS2     7011 drivers/gpu/drm/i915/i915_reg.h #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
_MMIO_TRANS2     7012 drivers/gpu/drm/i915/i915_reg.h #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
_MMIO_TRANS2     7013 drivers/gpu/drm/i915/i915_reg.h #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
_MMIO_TRANS2     7014 drivers/gpu/drm/i915/i915_reg.h #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
_MMIO_TRANS2     7015 drivers/gpu/drm/i915/i915_reg.h #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
_MMIO_TRANS2     7016 drivers/gpu/drm/i915/i915_reg.h #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
_MMIO_TRANS2     7017 drivers/gpu/drm/i915/i915_reg.h #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
_MMIO_TRANS2     7018 drivers/gpu/drm/i915/i915_reg.h #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
_MMIO_TRANS2     8238 drivers/gpu/drm/i915/i915_reg.h #define HSW_TVIDEO_DIP_CTL(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
_MMIO_TRANS2     8239 drivers/gpu/drm/i915/i915_reg.h #define HSW_TVIDEO_DIP_GCP(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
_MMIO_TRANS2     8240 drivers/gpu/drm/i915/i915_reg.h #define HSW_TVIDEO_DIP_AVI_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
_MMIO_TRANS2     8241 drivers/gpu/drm/i915/i915_reg.h #define HSW_TVIDEO_DIP_VS_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
_MMIO_TRANS2     8242 drivers/gpu/drm/i915/i915_reg.h #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
_MMIO_TRANS2     8243 drivers/gpu/drm/i915/i915_reg.h #define HSW_TVIDEO_DIP_GMP_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
_MMIO_TRANS2     8244 drivers/gpu/drm/i915/i915_reg.h #define HSW_TVIDEO_DIP_VSC_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
_MMIO_TRANS2     8245 drivers/gpu/drm/i915/i915_reg.h #define GLK_TVIDEO_DIP_DRM_DATA(trans, i)	_MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
_MMIO_TRANS2     8246 drivers/gpu/drm/i915/i915_reg.h #define ICL_VIDEO_DIP_PPS_DATA(trans, i)	_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
_MMIO_TRANS2     8247 drivers/gpu/drm/i915/i915_reg.h #define ICL_VIDEO_DIP_PPS_ECC(trans, i)		_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
_MMIO_TRANS2     9381 drivers/gpu/drm/i915/i915_reg.h #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
_MMIO_TRANS2     9428 drivers/gpu/drm/i915/i915_reg.h #define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(tran, \
_MMIO_TRANS2     9612 drivers/gpu/drm/i915/i915_reg.h #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)