_MMIO 38 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_ELSP(base) _MMIO((base) + 0x230) _MMIO 39 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) _MMIO 40 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) _MMIO 41 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) _MMIO 46 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) _MMIO 47 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) _MMIO 48 drivers/gpu/drm/i915/gt/intel_lrc.h #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) _MMIO 1183 drivers/gpu/drm/i915/gt/intel_workarounds.c whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), _MMIO 1186 drivers/gpu/drm/i915/gt/intel_workarounds.c whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), _MMIO 1189 drivers/gpu/drm/i915/gt/intel_workarounds.c whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), _MMIO 32 drivers/gpu/drm/i915/gt/uc/intel_guc.c return _MMIO(guc->send_regs.base + 4 * i); _MMIO 16 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_STATUS _MMIO(0xc000) _MMIO 39 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4) _MMIO 42 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4) _MMIO 45 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4) _MMIO 48 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define DMA_ADDR_0_LOW _MMIO(0xc300) _MMIO 49 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define DMA_ADDR_0_HIGH _MMIO(0xc304) _MMIO 50 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define DMA_ADDR_1_LOW _MMIO(0xc308) _MMIO 51 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define DMA_ADDR_1_HIGH _MMIO(0xc30c) _MMIO 54 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define DMA_COPY_SIZE _MMIO(0xc310) _MMIO 55 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define DMA_CTRL _MMIO(0xc314) _MMIO 59 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340) _MMIO 65 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4) _MMIO 67 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define HUC_STATUS2 _MMIO(0xD3B0) _MMIO 70 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC) _MMIO 73 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_WOPCM_SIZE _MMIO(0xc050) _MMIO 78 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GEN8_GT_PM_CONFIG _MMIO(0x138140) _MMIO 79 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GEN9LP_GT_PM_CONFIG _MMIO(0x138140) _MMIO 80 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GEN9_GT_PM_CONFIG _MMIO(0x13816c) _MMIO 83 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GEN8_GTCR _MMIO(0x4274) _MMIO 86 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_ARAT_C6DIS _MMIO(0xA178) _MMIO 88 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_SHIM_CONTROL _MMIO(0xc064) _MMIO 98 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_SEND_INTERRUPT _MMIO(0xc4c8) _MMIO 100 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0) _MMIO 114 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8) _MMIO 116 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4) _MMIO 118 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define DE_GUCRMR _MMIO(0x44054) _MMIO 120 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_BCS_RCS_IER _MMIO(0xC550) _MMIO 121 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_VCS2_VCS1_IER _MMIO(0xC554) _MMIO 122 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_WD_VECS_IER _MMIO(0xC558) _MMIO 123 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h #define GUC_PM_P24C_IER _MMIO(0xC55C) _MMIO 66 drivers/gpu/drm/i915/gvt/debugfs.c preg = intel_uncore_read_notrace(&i915->uncore, _MMIO(offset)); _MMIO 74 drivers/gpu/drm/i915/gvt/firmware.c _MMIO(offset)); _MMIO 44 drivers/gpu/drm/i915/gvt/handlers.c #define PCH_PP_STATUS _MMIO(0xc7200) _MMIO 45 drivers/gpu/drm/i915/gvt/handlers.c #define PCH_PP_CONTROL _MMIO(0xc7204) _MMIO 46 drivers/gpu/drm/i915/gvt/handlers.c #define PCH_PP_ON_DELAYS _MMIO(0xc7208) _MMIO 47 drivers/gpu/drm/i915/gvt/handlers.c #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) _MMIO 48 drivers/gpu/drm/i915/gvt/handlers.c #define PCH_PP_DIVISOR _MMIO(0xc7210) _MMIO 464 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x2690), _MMIO 465 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x2694), _MMIO 466 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x2698), _MMIO 467 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x2754), _MMIO 468 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x28a0), _MMIO 469 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x4de0), _MMIO 470 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x4de4), _MMIO 471 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x4dfc), _MMIO 473 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x7014), _MMIO 476 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x7700), _MMIO 477 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x7704), _MMIO 478 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x7708), _MMIO 479 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x770c), _MMIO 480 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0x83a8), _MMIO 481 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0xb110), _MMIO 483 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0xe100), _MMIO 484 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0xe18c), _MMIO 485 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0xe48c), _MMIO 486 drivers/gpu/drm/i915/gvt/handlers.c _MMIO(0xe5f4), _MMIO 1657 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); _MMIO 1881 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x28) _MMIO 1885 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x134) _MMIO 1889 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x6c) _MMIO 1894 drivers/gpu/drm/i915/gvt/handlers.c MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); _MMIO 1896 drivers/gpu/drm/i915/gvt/handlers.c MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); _MMIO 1906 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x29c) _MMIO 1925 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); _MMIO 1927 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); _MMIO 1929 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); _MMIO 1932 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); _MMIO 1938 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 1939 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 1940 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 1941 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 1942 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 1943 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 1944 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 1945 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); _MMIO 1950 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 1951 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x602a0), D_ALL); _MMIO 1953 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x65050), D_ALL); _MMIO 1954 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x650b4), D_ALL); _MMIO 1956 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xc4040), D_ALL); _MMIO 2000 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x700ac), D_ALL); _MMIO 2001 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x710ac), D_ALL); _MMIO 2002 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x720ac), D_ALL); _MMIO 2004 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x70090), D_ALL); _MMIO 2005 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x70094), D_ALL); _MMIO 2006 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x70098), D_ALL); _MMIO 2007 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x7009c), D_ALL); _MMIO 2195 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x48268), D_ALL); _MMIO 2200 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2202 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, _MMIO 2204 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, _MMIO 2206 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, _MMIO 2211 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); _MMIO 2212 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); _MMIO 2224 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL); _MMIO 2225 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL); _MMIO 2226 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL); _MMIO 2227 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL); _MMIO 2228 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL); _MMIO 2229 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL); _MMIO 2230 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL); _MMIO 2232 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL); _MMIO 2233 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL); _MMIO 2234 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL); _MMIO 2235 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL); _MMIO 2236 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL); _MMIO 2237 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL); _MMIO 2238 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL); _MMIO 2240 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL); _MMIO 2241 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL); _MMIO 2242 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL); _MMIO 2243 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL); _MMIO 2244 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL); _MMIO 2245 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL); _MMIO 2246 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL); _MMIO 2247 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL); _MMIO 2265 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL); _MMIO 2266 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL); _MMIO 2267 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL); _MMIO 2268 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL); _MMIO 2269 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL); _MMIO 2270 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL); _MMIO 2276 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL); _MMIO 2277 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL); _MMIO 2278 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_FPA0), D_ALL); _MMIO 2279 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_FPA1), D_ALL); _MMIO 2280 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_FPB0), D_ALL); _MMIO 2281 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PCH_FPB1), D_ALL); _MMIO 2286 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x61208), D_ALL); _MMIO 2287 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6120c), D_ALL); _MMIO 2291 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); _MMIO 2292 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); _MMIO 2293 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); _MMIO 2294 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); _MMIO 2295 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); _MMIO 2296 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); _MMIO 2318 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL); _MMIO 2319 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL); _MMIO 2321 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL); _MMIO 2322 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL); _MMIO 2388 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x60110), D_ALL); _MMIO 2389 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x61110), D_ALL); _MMIO 2390 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2391 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2392 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2393 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); _MMIO 2394 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); _MMIO 2395 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); _MMIO 2396 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); _MMIO 2397 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); _MMIO 2398 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); _MMIO 2404 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); _MMIO 2405 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); _MMIO 2416 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x46508), D_ALL); _MMIO 2418 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x49080), D_ALL); _MMIO 2419 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x49180), D_ALL); _MMIO 2420 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x49280), D_ALL); _MMIO 2422 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2423 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2424 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2444 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, _MMIO 2465 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2466 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2467 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2468 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2469 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2475 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); _MMIO 2476 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); _MMIO 2477 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); _MMIO 2478 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); _MMIO 2480 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL); _MMIO 2481 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL); _MMIO 2482 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL); _MMIO 2483 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL); _MMIO 2542 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); _MMIO 2545 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x13812c), D_ALL); _MMIO 2551 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x3c), D_ALL); _MMIO 2552 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x860), D_ALL); _MMIO 2554 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x121d0), D_ALL); _MMIO 2556 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x41d0), D_ALL); _MMIO 2558 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6200), D_ALL); _MMIO 2559 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6204), D_ALL); _MMIO 2560 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6208), D_ALL); _MMIO 2561 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x7118), D_ALL); _MMIO 2562 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x7180), D_ALL); _MMIO 2563 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x7408), D_ALL); _MMIO 2564 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x7c00), D_ALL); _MMIO 2566 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x911c), D_ALL); _MMIO 2567 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x9120), D_ALL); _MMIO 2571 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x48800), D_ALL); _MMIO 2572 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xce044), D_ALL); _MMIO 2573 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6500), D_ALL); _MMIO 2574 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6504), D_ALL); _MMIO 2575 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6600), D_ALL); _MMIO 2576 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6604), D_ALL); _MMIO 2577 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6700), D_ALL); _MMIO 2578 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6704), D_ALL); _MMIO 2579 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6800), D_ALL); _MMIO 2580 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xe6804), D_ALL); _MMIO 2584 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x902c), D_ALL); _MMIO 2585 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec008), D_ALL); _MMIO 2586 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec00c), D_ALL); _MMIO 2587 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); _MMIO 2588 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); _MMIO 2589 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); _MMIO 2590 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); _MMIO 2591 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); _MMIO 2592 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); _MMIO 2593 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec408), D_ALL); _MMIO 2594 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec40c), D_ALL); _MMIO 2595 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); _MMIO 2596 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); _MMIO 2597 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); _MMIO 2598 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); _MMIO 2599 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); _MMIO 2600 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); _MMIO 2601 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfc810), D_ALL); _MMIO 2602 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfc81c), D_ALL); _MMIO 2603 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfc828), D_ALL); _MMIO 2604 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfc834), D_ALL); _MMIO 2605 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfcc00), D_ALL); _MMIO 2606 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfcc0c), D_ALL); _MMIO 2607 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfcc18), D_ALL); _MMIO 2608 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfcc24), D_ALL); _MMIO 2609 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfd000), D_ALL); _MMIO 2610 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfd00c), D_ALL); _MMIO 2611 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfd018), D_ALL); _MMIO 2612 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfd024), D_ALL); _MMIO 2613 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfd034), D_ALL); _MMIO 2616 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x2054), D_ALL); _MMIO 2617 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x12054), D_ALL); _MMIO 2618 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x22054), D_ALL); _MMIO 2619 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x1a054), D_ALL); _MMIO 2621 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x44070), D_ALL); _MMIO 2622 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2623 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 2624 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 2625 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 2626 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 2628 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); _MMIO 2629 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x2b00), D_BDW_PLUS); _MMIO 2630 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x2360), D_BDW_PLUS); _MMIO 2631 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); _MMIO 2632 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); _MMIO 2633 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); _MMIO 2635 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2636 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2650 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); _MMIO 2651 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); _MMIO 2652 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); _MMIO 2653 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); _MMIO 2654 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); _MMIO 2655 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2659 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 2660 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 2661 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); _MMIO 2664 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2665 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2666 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2667 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2744 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0xd0) _MMIO 2750 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x230) _MMIO 2754 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x234) _MMIO 2759 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x244) _MMIO 2763 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x370) _MMIO 2767 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x3a0) _MMIO 2774 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS); _MMIO 2777 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x1c054), D_BDW_PLUS); _MMIO 2786 drivers/gpu/drm/i915/gvt/handlers.c #define RING_REG(base) _MMIO((base) + 0x270) _MMIO 2799 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW); _MMIO 2801 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); _MMIO 2802 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); _MMIO 2803 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x66c04), D_BDW_PLUS); _MMIO 2811 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xfdc), D_BDW_PLUS); _MMIO 2818 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); _MMIO 2819 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); _MMIO 2821 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); _MMIO 2822 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); _MMIO 2823 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xb110), D_BDW); _MMIO 2825 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, _MMIO 2828 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x44484), D_BDW_PLUS); _MMIO 2829 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x4448c), D_BDW_PLUS); _MMIO 2831 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); _MMIO 2834 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); _MMIO 2836 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x110000), D_BDW_PLUS); _MMIO 2838 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x48400), D_BDW_PLUS); _MMIO 2840 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6e570), D_BDW_PLUS); _MMIO 2841 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x65f10), D_BDW_PLUS); _MMIO 2843 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); _MMIO 2844 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); _MMIO 2846 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); _MMIO 2848 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); _MMIO 2850 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2851 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2852 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2853 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2854 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2855 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2856 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2857 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2858 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2859 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); _MMIO 2875 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, _MMIO 2877 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, _MMIO 2879 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, _MMIO 2898 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS); _MMIO 2899 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS); _MMIO 2900 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS); _MMIO 2901 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS); _MMIO 2902 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS); _MMIO 2903 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS); _MMIO 2995 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); _MMIO 2996 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); _MMIO 2997 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); _MMIO 2998 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); _MMIO 3000 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); _MMIO 3001 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); _MMIO 3002 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); _MMIO 3003 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); _MMIO 3005 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); _MMIO 3006 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); _MMIO 3007 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); _MMIO 3008 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); _MMIO 3010 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); _MMIO 3011 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); _MMIO 3012 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); _MMIO 3013 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); _MMIO 3015 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); _MMIO 3016 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); _MMIO 3017 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); _MMIO 3018 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); _MMIO 3020 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); _MMIO 3021 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); _MMIO 3022 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); _MMIO 3023 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); _MMIO 3025 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS); _MMIO 3026 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS); _MMIO 3027 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x72380), D_SKL_PLUS); _MMIO 3028 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x7239c), D_SKL_PLUS); _MMIO 3029 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS); _MMIO 3046 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xd08), D_SKL_PLUS); _MMIO 3061 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write); _MMIO 3063 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x46430), D_SKL_PLUS); _MMIO 3065 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x46520), D_SKL_PLUS); _MMIO 3067 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0xc403c), D_SKL_PLUS); _MMIO 3071 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x65900), D_SKL_PLUS); _MMIO 3073 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x4068), D_SKL_PLUS); _MMIO 3074 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x67054), D_SKL_PLUS); _MMIO 3075 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6e560), D_SKL_PLUS); _MMIO 3076 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x6e554), D_SKL_PLUS); _MMIO 3077 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x2b20), D_SKL_PLUS); _MMIO 3078 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x65f00), D_SKL_PLUS); _MMIO 3079 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x65f08), D_SKL_PLUS); _MMIO 3080 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x320f0), D_SKL_PLUS); _MMIO 3082 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x70034), D_SKL_PLUS); _MMIO 3083 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x71034), D_SKL_PLUS); _MMIO 3084 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x72034), D_SKL_PLUS); _MMIO 3086 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS); _MMIO 3087 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS); _MMIO 3088 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS); _MMIO 3089 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS); _MMIO 3090 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS); _MMIO 3091 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS); _MMIO 3092 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS); _MMIO 3093 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS); _MMIO 3094 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS); _MMIO 3096 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x44500), D_SKL_PLUS); _MMIO 3097 drivers/gpu/drm/i915/gvt/handlers.c #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) _MMIO 3117 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL); _MMIO 3127 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x4194), D_BXT); _MMIO 3128 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x4294), D_BXT); _MMIO 3129 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(0x4494), D_BXT); _MMIO 3328 drivers/gpu/drm/i915/gvt/handlers.c {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL}, _MMIO 3329 drivers/gpu/drm/i915/gvt/handlers.c {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, _MMIO 3330 drivers/gpu/drm/i915/gvt/handlers.c {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, _MMIO 118 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, _MMIO(0x4dfc), 0, true}, _MMIO 137 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */ _MMIO 365 drivers/gpu/drm/i915/gvt/mmio_context.c reg = _MMIO(regs[ring_id]); _MMIO 72 drivers/gpu/drm/i915/gvt/reg.h (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \ _MMIO 73 drivers/gpu/drm/i915/gvt/reg.h (_MMIO(0x50090))) : \ _MMIO 74 drivers/gpu/drm/i915/gvt/reg.h (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \ _MMIO 75 drivers/gpu/drm/i915/gvt/reg.h (_MMIO(0x50098))) : \ _MMIO 76 drivers/gpu/drm/i915/gvt/reg.h (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \ _MMIO 77 drivers/gpu/drm/i915/gvt/reg.h (_MMIO(0x5009C))) : \ _MMIO 78 drivers/gpu/drm/i915/gvt/reg.h (_MMIO(0x50080))))); }) _MMIO 113 drivers/gpu/drm/i915/gvt/reg.h #define PCH_GPIO_BASE _MMIO(0xc5010) _MMIO 115 drivers/gpu/drm/i915/gvt/reg.h #define PCH_GMBUS0 _MMIO(0xc5100) _MMIO 116 drivers/gpu/drm/i915/gvt/reg.h #define PCH_GMBUS1 _MMIO(0xc5104) _MMIO 117 drivers/gpu/drm/i915/gvt/reg.h #define PCH_GMBUS2 _MMIO(0xc5108) _MMIO 118 drivers/gpu/drm/i915/gvt/reg.h #define PCH_GMBUS3 _MMIO(0xc510c) _MMIO 119 drivers/gpu/drm/i915/gvt/reg.h #define PCH_GMBUS4 _MMIO(0xc5110) _MMIO 120 drivers/gpu/drm/i915/gvt/reg.h #define PCH_GMBUS5 _MMIO(0xc5120) _MMIO 122 drivers/gpu/drm/i915/gvt/reg.h #define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i) * 4) _MMIO 123 drivers/gpu/drm/i915/gvt/reg.h #define TRNULLDETCT _MMIO(0x4de8) _MMIO 124 drivers/gpu/drm/i915/gvt/reg.h #define TRINVTILEDETCT _MMIO(0x4dec) _MMIO 125 drivers/gpu/drm/i915/gvt/reg.h #define TRVADR _MMIO(0x4df0) _MMIO 126 drivers/gpu/drm/i915/gvt/reg.h #define TRTTE _MMIO(0x4df4) _MMIO 127 drivers/gpu/drm/i915/gvt/reg.h #define RING_EXCC(base) _MMIO((base) + 0x28) _MMIO 128 drivers/gpu/drm/i915/gvt/reg.h #define RING_GFX_MODE(base) _MMIO((base) + 0x29c) _MMIO 129 drivers/gpu/drm/i915/gvt/reg.h #define VF_GUARDBAND _MMIO(0x83a4) _MMIO 3258 drivers/gpu/drm/i915/i915_perf.c oa_regs[i].addr = _MMIO(addr); _MMIO 117 drivers/gpu/drm/i915/i915_pvinfo.h #define vgtif_reg(x) _MMIO(VGT_PVINFO_PAGE + vgtif_offset(x)) _MMIO 187 drivers/gpu/drm/i915/i915_reg.h #define INVALID_MMIO_REG _MMIO(0) _MMIO 234 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) _MMIO 235 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) _MMIO 236 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) _MMIO 237 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) _MMIO 238 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) _MMIO 242 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) _MMIO 243 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) _MMIO 244 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) _MMIO 245 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c)) _MMIO 251 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ _MMIO 257 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg)) _MMIO 258 drivers/gpu/drm/i915/i915_reg.h #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ _MMIO 353 drivers/gpu/drm/i915/i915_reg.h #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) _MMIO 360 drivers/gpu/drm/i915/i915_reg.h #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ _MMIO 368 drivers/gpu/drm/i915/i915_reg.h #define VLV_G3DCTL _MMIO(0x9024) _MMIO 369 drivers/gpu/drm/i915/i915_reg.h #define VLV_GSCKGCTL _MMIO(0x9028) _MMIO 371 drivers/gpu/drm/i915/i915_reg.h #define GEN6_MBCTL _MMIO(0x0907c) _MMIO 378 drivers/gpu/drm/i915/i915_reg.h #define GEN6_GDRST _MMIO(0x941c) _MMIO 403 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C) _MMIO 405 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890) _MMIO 409 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C) _MMIO 411 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018) _MMIO 413 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014) _MMIO 416 drivers/gpu/drm/i915/i915_reg.h #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228) _MMIO 417 drivers/gpu/drm/i915/i915_reg.h #define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518) _MMIO 418 drivers/gpu/drm/i915/i915_reg.h #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220) _MMIO 421 drivers/gpu/drm/i915/i915_reg.h #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4) _MMIO 422 drivers/gpu/drm/i915/i915_reg.h #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8) _MMIO 424 drivers/gpu/drm/i915/i915_reg.h #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) _MMIO 439 drivers/gpu/drm/i915/i915_reg.h #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC) _MMIO 461 drivers/gpu/drm/i915/i915_reg.h #define GAM_ECOCHK _MMIO(0x4090) _MMIO 474 drivers/gpu/drm/i915/i915_reg.h #define GEN8_RC6_CTX_INFO _MMIO(0x8504) _MMIO 476 drivers/gpu/drm/i915/i915_reg.h #define GAC_ECO_BITS _MMIO(0x14090) _MMIO 481 drivers/gpu/drm/i915/i915_reg.h #define GAB_CTL _MMIO(0x24000) _MMIO 484 drivers/gpu/drm/i915/i915_reg.h #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) _MMIO 508 drivers/gpu/drm/i915/i915_reg.h #define _VGA_MSR_WRITE _MMIO(0x3c2) _MMIO 546 drivers/gpu/drm/i915/i915_reg.h #define MI_PREDICATE_SRC0 _MMIO(0x2400) _MMIO 547 drivers/gpu/drm/i915/i915_reg.h #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) _MMIO 548 drivers/gpu/drm/i915/i915_reg.h #define MI_PREDICATE_SRC1 _MMIO(0x2408) _MMIO 549 drivers/gpu/drm/i915/i915_reg.h #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) _MMIO 551 drivers/gpu/drm/i915/i915_reg.h #define MI_PREDICATE_RESULT_2 _MMIO(0x2214) _MMIO 558 drivers/gpu/drm/i915/i915_reg.h #define BCS_SWCTRL _MMIO(0x22200) _MMIO 561 drivers/gpu/drm/i915/i915_reg.h #define BCS_GPR(n) _MMIO(0x22600 + (n) * 8) _MMIO 562 drivers/gpu/drm/i915/i915_reg.h #define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4) _MMIO 564 drivers/gpu/drm/i915/i915_reg.h #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) _MMIO 565 drivers/gpu/drm/i915/i915_reg.h #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) _MMIO 566 drivers/gpu/drm/i915/i915_reg.h #define HS_INVOCATION_COUNT _MMIO(0x2300) _MMIO 567 drivers/gpu/drm/i915/i915_reg.h #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) _MMIO 568 drivers/gpu/drm/i915/i915_reg.h #define DS_INVOCATION_COUNT _MMIO(0x2308) _MMIO 569 drivers/gpu/drm/i915/i915_reg.h #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) _MMIO 570 drivers/gpu/drm/i915/i915_reg.h #define IA_VERTICES_COUNT _MMIO(0x2310) _MMIO 571 drivers/gpu/drm/i915/i915_reg.h #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) _MMIO 572 drivers/gpu/drm/i915/i915_reg.h #define IA_PRIMITIVES_COUNT _MMIO(0x2318) _MMIO 573 drivers/gpu/drm/i915/i915_reg.h #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) _MMIO 574 drivers/gpu/drm/i915/i915_reg.h #define VS_INVOCATION_COUNT _MMIO(0x2320) _MMIO 575 drivers/gpu/drm/i915/i915_reg.h #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) _MMIO 576 drivers/gpu/drm/i915/i915_reg.h #define GS_INVOCATION_COUNT _MMIO(0x2328) _MMIO 577 drivers/gpu/drm/i915/i915_reg.h #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) _MMIO 578 drivers/gpu/drm/i915/i915_reg.h #define GS_PRIMITIVES_COUNT _MMIO(0x2330) _MMIO 579 drivers/gpu/drm/i915/i915_reg.h #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) _MMIO 580 drivers/gpu/drm/i915/i915_reg.h #define CL_INVOCATION_COUNT _MMIO(0x2338) _MMIO 581 drivers/gpu/drm/i915/i915_reg.h #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) _MMIO 582 drivers/gpu/drm/i915/i915_reg.h #define CL_PRIMITIVES_COUNT _MMIO(0x2340) _MMIO 583 drivers/gpu/drm/i915/i915_reg.h #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) _MMIO 584 drivers/gpu/drm/i915/i915_reg.h #define PS_INVOCATION_COUNT _MMIO(0x2348) _MMIO 585 drivers/gpu/drm/i915/i915_reg.h #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) _MMIO 586 drivers/gpu/drm/i915/i915_reg.h #define PS_DEPTH_COUNT _MMIO(0x2350) _MMIO 587 drivers/gpu/drm/i915/i915_reg.h #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) _MMIO 590 drivers/gpu/drm/i915/i915_reg.h #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) _MMIO 591 drivers/gpu/drm/i915/i915_reg.h #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) _MMIO 593 drivers/gpu/drm/i915/i915_reg.h #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) _MMIO 594 drivers/gpu/drm/i915/i915_reg.h #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) _MMIO 596 drivers/gpu/drm/i915/i915_reg.h #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) _MMIO 597 drivers/gpu/drm/i915/i915_reg.h #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) _MMIO 598 drivers/gpu/drm/i915/i915_reg.h #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) _MMIO 599 drivers/gpu/drm/i915/i915_reg.h #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) _MMIO 600 drivers/gpu/drm/i915/i915_reg.h #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) _MMIO 601 drivers/gpu/drm/i915/i915_reg.h #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) _MMIO 603 drivers/gpu/drm/i915/i915_reg.h #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) _MMIO 604 drivers/gpu/drm/i915/i915_reg.h #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) _MMIO 605 drivers/gpu/drm/i915/i915_reg.h #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) _MMIO 608 drivers/gpu/drm/i915/i915_reg.h #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) _MMIO 609 drivers/gpu/drm/i915/i915_reg.h #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) _MMIO 611 drivers/gpu/drm/i915/i915_reg.h #define GEN7_OACONTROL _MMIO(0x2360) _MMIO 628 drivers/gpu/drm/i915/i915_reg.h #define GEN8_OACTXID _MMIO(0x2364) _MMIO 630 drivers/gpu/drm/i915/i915_reg.h #define GEN8_OA_DEBUG _MMIO(0x2B04) _MMIO 636 drivers/gpu/drm/i915/i915_reg.h #define GEN8_OACONTROL _MMIO(0x2B00) _MMIO 645 drivers/gpu/drm/i915/i915_reg.h #define GEN8_OACTXCONTROL _MMIO(0x2360) _MMIO 651 drivers/gpu/drm/i915/i915_reg.h #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ _MMIO 657 drivers/gpu/drm/i915/i915_reg.h #define GEN8_OABUFFER_UDW _MMIO(0x23b4) _MMIO 658 drivers/gpu/drm/i915/i915_reg.h #define GEN8_OABUFFER _MMIO(0x2b14) _MMIO 661 drivers/gpu/drm/i915/i915_reg.h #define GEN7_OASTATUS1 _MMIO(0x2364) _MMIO 667 drivers/gpu/drm/i915/i915_reg.h #define GEN7_OASTATUS2 _MMIO(0x2368) _MMIO 671 drivers/gpu/drm/i915/i915_reg.h #define GEN8_OASTATUS _MMIO(0x2b08) _MMIO 677 drivers/gpu/drm/i915/i915_reg.h #define GEN8_OAHEADPTR _MMIO(0x2B0C) _MMIO 679 drivers/gpu/drm/i915/i915_reg.h #define GEN8_OATAILPTR _MMIO(0x2B10) _MMIO 695 drivers/gpu/drm/i915/i915_reg.h #define EU_PERF_CNTL0 _MMIO(0xe458) _MMIO 696 drivers/gpu/drm/i915/i915_reg.h #define EU_PERF_CNTL1 _MMIO(0xe558) _MMIO 697 drivers/gpu/drm/i915/i915_reg.h #define EU_PERF_CNTL2 _MMIO(0xe658) _MMIO 698 drivers/gpu/drm/i915/i915_reg.h #define EU_PERF_CNTL3 _MMIO(0xe758) _MMIO 699 drivers/gpu/drm/i915/i915_reg.h #define EU_PERF_CNTL4 _MMIO(0xe45c) _MMIO 700 drivers/gpu/drm/i915/i915_reg.h #define EU_PERF_CNTL5 _MMIO(0xe55c) _MMIO 701 drivers/gpu/drm/i915/i915_reg.h #define EU_PERF_CNTL6 _MMIO(0xe65c) _MMIO 707 drivers/gpu/drm/i915/i915_reg.h #define OASTARTTRIG1 _MMIO(0x2710) _MMIO 711 drivers/gpu/drm/i915/i915_reg.h #define OASTARTTRIG2 _MMIO(0x2714) _MMIO 742 drivers/gpu/drm/i915/i915_reg.h #define OASTARTTRIG3 _MMIO(0x2718) _MMIO 753 drivers/gpu/drm/i915/i915_reg.h #define OASTARTTRIG4 _MMIO(0x271c) _MMIO 764 drivers/gpu/drm/i915/i915_reg.h #define OASTARTTRIG5 _MMIO(0x2720) _MMIO 768 drivers/gpu/drm/i915/i915_reg.h #define OASTARTTRIG6 _MMIO(0x2724) _MMIO 799 drivers/gpu/drm/i915/i915_reg.h #define OASTARTTRIG7 _MMIO(0x2728) _MMIO 810 drivers/gpu/drm/i915/i915_reg.h #define OASTARTTRIG8 _MMIO(0x272c) _MMIO 821 drivers/gpu/drm/i915/i915_reg.h #define OAREPORTTRIG1 _MMIO(0x2740) _MMIO 825 drivers/gpu/drm/i915/i915_reg.h #define OAREPORTTRIG2 _MMIO(0x2744) _MMIO 852 drivers/gpu/drm/i915/i915_reg.h #define OAREPORTTRIG3 _MMIO(0x2748) _MMIO 863 drivers/gpu/drm/i915/i915_reg.h #define OAREPORTTRIG4 _MMIO(0x274c) _MMIO 874 drivers/gpu/drm/i915/i915_reg.h #define OAREPORTTRIG5 _MMIO(0x2750) _MMIO 878 drivers/gpu/drm/i915/i915_reg.h #define OAREPORTTRIG6 _MMIO(0x2754) _MMIO 905 drivers/gpu/drm/i915/i915_reg.h #define OAREPORTTRIG7 _MMIO(0x2758) _MMIO 916 drivers/gpu/drm/i915/i915_reg.h #define OAREPORTTRIG8 _MMIO(0x275c) _MMIO 948 drivers/gpu/drm/i915/i915_reg.h #define OACEC0_0 _MMIO(0x2770) _MMIO 949 drivers/gpu/drm/i915/i915_reg.h #define OACEC0_1 _MMIO(0x2774) _MMIO 950 drivers/gpu/drm/i915/i915_reg.h #define OACEC1_0 _MMIO(0x2778) _MMIO 951 drivers/gpu/drm/i915/i915_reg.h #define OACEC1_1 _MMIO(0x277c) _MMIO 952 drivers/gpu/drm/i915/i915_reg.h #define OACEC2_0 _MMIO(0x2780) _MMIO 953 drivers/gpu/drm/i915/i915_reg.h #define OACEC2_1 _MMIO(0x2784) _MMIO 954 drivers/gpu/drm/i915/i915_reg.h #define OACEC3_0 _MMIO(0x2788) _MMIO 955 drivers/gpu/drm/i915/i915_reg.h #define OACEC3_1 _MMIO(0x278c) _MMIO 956 drivers/gpu/drm/i915/i915_reg.h #define OACEC4_0 _MMIO(0x2790) _MMIO 957 drivers/gpu/drm/i915/i915_reg.h #define OACEC4_1 _MMIO(0x2794) _MMIO 958 drivers/gpu/drm/i915/i915_reg.h #define OACEC5_0 _MMIO(0x2798) _MMIO 959 drivers/gpu/drm/i915/i915_reg.h #define OACEC5_1 _MMIO(0x279c) _MMIO 960 drivers/gpu/drm/i915/i915_reg.h #define OACEC6_0 _MMIO(0x27a0) _MMIO 961 drivers/gpu/drm/i915/i915_reg.h #define OACEC6_1 _MMIO(0x27a4) _MMIO 962 drivers/gpu/drm/i915/i915_reg.h #define OACEC7_0 _MMIO(0x27a8) _MMIO 963 drivers/gpu/drm/i915/i915_reg.h #define OACEC7_1 _MMIO(0x27ac) _MMIO 966 drivers/gpu/drm/i915/i915_reg.h #define OA_PERFCNT1_LO _MMIO(0x91B8) _MMIO 967 drivers/gpu/drm/i915/i915_reg.h #define OA_PERFCNT1_HI _MMIO(0x91BC) _MMIO 968 drivers/gpu/drm/i915/i915_reg.h #define OA_PERFCNT2_LO _MMIO(0x91C0) _MMIO 969 drivers/gpu/drm/i915/i915_reg.h #define OA_PERFCNT2_HI _MMIO(0x91C4) _MMIO 970 drivers/gpu/drm/i915/i915_reg.h #define OA_PERFCNT3_LO _MMIO(0x91C8) _MMIO 971 drivers/gpu/drm/i915/i915_reg.h #define OA_PERFCNT3_HI _MMIO(0x91CC) _MMIO 972 drivers/gpu/drm/i915/i915_reg.h #define OA_PERFCNT4_LO _MMIO(0x91D8) _MMIO 973 drivers/gpu/drm/i915/i915_reg.h #define OA_PERFCNT4_HI _MMIO(0x91DC) _MMIO 975 drivers/gpu/drm/i915/i915_reg.h #define OA_PERFMATRIX_LO _MMIO(0x91C8) _MMIO 976 drivers/gpu/drm/i915/i915_reg.h #define OA_PERFMATRIX_HI _MMIO(0x91CC) _MMIO 979 drivers/gpu/drm/i915/i915_reg.h #define RPM_CONFIG0 _MMIO(0x0D00) _MMIO 993 drivers/gpu/drm/i915/i915_reg.h #define RPM_CONFIG1 _MMIO(0x0D04) _MMIO 997 drivers/gpu/drm/i915/i915_reg.h #define CTC_MODE _MMIO(0xA26C) _MMIO 1005 drivers/gpu/drm/i915/i915_reg.h #define RCP_CONFIG _MMIO(0x0D08) _MMIO 1008 drivers/gpu/drm/i915/i915_reg.h #define HSW_MBVID2_NOA0 _MMIO(0x9E80) _MMIO 1009 drivers/gpu/drm/i915/i915_reg.h #define HSW_MBVID2_NOA1 _MMIO(0x9E84) _MMIO 1010 drivers/gpu/drm/i915/i915_reg.h #define HSW_MBVID2_NOA2 _MMIO(0x9E88) _MMIO 1011 drivers/gpu/drm/i915/i915_reg.h #define HSW_MBVID2_NOA3 _MMIO(0x9E8C) _MMIO 1012 drivers/gpu/drm/i915/i915_reg.h #define HSW_MBVID2_NOA4 _MMIO(0x9E90) _MMIO 1013 drivers/gpu/drm/i915/i915_reg.h #define HSW_MBVID2_NOA5 _MMIO(0x9E94) _MMIO 1014 drivers/gpu/drm/i915/i915_reg.h #define HSW_MBVID2_NOA6 _MMIO(0x9E98) _MMIO 1015 drivers/gpu/drm/i915/i915_reg.h #define HSW_MBVID2_NOA7 _MMIO(0x9E9C) _MMIO 1016 drivers/gpu/drm/i915/i915_reg.h #define HSW_MBVID2_NOA8 _MMIO(0x9EA0) _MMIO 1017 drivers/gpu/drm/i915/i915_reg.h #define HSW_MBVID2_NOA9 _MMIO(0x9EA4) _MMIO 1019 drivers/gpu/drm/i915/i915_reg.h #define HSW_MBVID2_MISR0 _MMIO(0x9EC0) _MMIO 1022 drivers/gpu/drm/i915/i915_reg.h #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) _MMIO 1024 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP0_0 _MMIO(0x9800) _MMIO 1025 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP0_2 _MMIO(0x9804) _MMIO 1026 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP0_1 _MMIO(0x9808) _MMIO 1028 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP1_0 _MMIO(0x980C) _MMIO 1029 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP1_2 _MMIO(0x9810) _MMIO 1030 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP1_1 _MMIO(0x9814) _MMIO 1032 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP2_0 _MMIO(0x9818) _MMIO 1033 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP2_2 _MMIO(0x981C) _MMIO 1034 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP2_1 _MMIO(0x9820) _MMIO 1036 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP3_0 _MMIO(0x9824) _MMIO 1037 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP3_2 _MMIO(0x9828) _MMIO 1038 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP3_1 _MMIO(0x982C) _MMIO 1040 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP_TRIGGER _MMIO(0x9830) _MMIO 1041 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) _MMIO 1042 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) _MMIO 1043 drivers/gpu/drm/i915/i915_reg.h #define MICRO_BP_FIRED_ARMED _MMIO(0x983C) _MMIO 1045 drivers/gpu/drm/i915/i915_reg.h #define GDT_CHICKEN_BITS _MMIO(0x9840) _MMIO 1048 drivers/gpu/drm/i915/i915_reg.h #define NOA_DATA _MMIO(0x986C) _MMIO 1049 drivers/gpu/drm/i915/i915_reg.h #define NOA_WRITE _MMIO(0x9888) _MMIO 1050 drivers/gpu/drm/i915/i915_reg.h #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884) _MMIO 1059 drivers/gpu/drm/i915/i915_reg.h #define DEBUG_RESET_I830 _MMIO(0x6070) _MMIO 1067 drivers/gpu/drm/i915/i915_reg.h #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) _MMIO 1089 drivers/gpu/drm/i915/i915_reg.h #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) _MMIO 1090 drivers/gpu/drm/i915/i915_reg.h #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) _MMIO 1266 drivers/gpu/drm/i915/i915_reg.h #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) _MMIO 1627 drivers/gpu/drm/i915/i915_reg.h _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) _MMIO 1633 drivers/gpu/drm/i915/i915_reg.h _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) _MMIO 1635 drivers/gpu/drm/i915/i915_reg.h #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) _MMIO 1720 drivers/gpu/drm/i915/i915_reg.h #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ _MMIO 1768 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) _MMIO 1769 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) _MMIO 1773 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy)) _MMIO 1788 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) _MMIO 1796 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_COMP_DW0 _MMIO(0x162100) _MMIO 1797 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) _MMIO 1800 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_COMP_DW1 _MMIO(0x162104) _MMIO 1801 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) _MMIO 1803 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) _MMIO 1804 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) _MMIO 1816 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) _MMIO 1819 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_COMP_DW9 _MMIO(0x162124) _MMIO 1820 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy)) _MMIO 1822 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_COMP_DW10 _MMIO(0x162128) _MMIO 1823 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy)) _MMIO 1836 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \ _MMIO 1843 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \ _MMIO 1860 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) _MMIO 1861 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) _MMIO 1862 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy)) _MMIO 1906 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port)) _MMIO 1907 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port)) _MMIO 1908 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy)) _MMIO 1909 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy)) _MMIO 1910 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy)) _MMIO 1922 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port))) _MMIO 1923 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port))) _MMIO 1924 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ _MMIO 1927 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy)) _MMIO 1928 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy)) _MMIO 1929 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy)) _MMIO 1930 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy)) _MMIO 1939 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port)) _MMIO 1940 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port)) _MMIO 1941 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy)) _MMIO 1942 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy)) _MMIO 1943 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy)) _MMIO 1952 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port))) _MMIO 1953 drivers/gpu/drm/i915/i915_reg.h #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port))) _MMIO 1954 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy)) _MMIO 1955 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy)) _MMIO 1956 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy)) _MMIO 1957 drivers/gpu/drm/i915/i915_reg.h #define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy)) _MMIO 1962 drivers/gpu/drm/i915/i915_reg.h #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG) _MMIO 1966 drivers/gpu/drm/i915/i915_reg.h _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) _MMIO 2150 drivers/gpu/drm/i915/i915_reg.h _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2)) _MMIO 2172 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off)) _MMIO 2316 drivers/gpu/drm/i915/i915_reg.h _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ _MMIO 2321 drivers/gpu/drm/i915/i915_reg.h #define UAIMI_SPR1 _MMIO(0x4F074) _MMIO 2325 drivers/gpu/drm/i915/i915_reg.h #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) _MMIO 2343 drivers/gpu/drm/i915/i915_reg.h #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) _MMIO 2356 drivers/gpu/drm/i915/i915_reg.h #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) _MMIO 2357 drivers/gpu/drm/i915/i915_reg.h #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) _MMIO 2363 drivers/gpu/drm/i915/i915_reg.h #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) _MMIO 2364 drivers/gpu/drm/i915/i915_reg.h #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) _MMIO 2370 drivers/gpu/drm/i915/i915_reg.h #define TILECTL _MMIO(0x101000) _MMIO 2379 drivers/gpu/drm/i915/i915_reg.h #define PGTBL_CTL _MMIO(0x02020) _MMIO 2382 drivers/gpu/drm/i915/i915_reg.h #define PGTBL_ER _MMIO(0x02024) _MMIO 2402 drivers/gpu/drm/i915/i915_reg.h #define RING_TAIL(base) _MMIO((base) + 0x30) _MMIO 2403 drivers/gpu/drm/i915/i915_reg.h #define RING_HEAD(base) _MMIO((base) + 0x34) _MMIO 2404 drivers/gpu/drm/i915/i915_reg.h #define RING_START(base) _MMIO((base) + 0x38) _MMIO 2405 drivers/gpu/drm/i915/i915_reg.h #define RING_CTL(base) _MMIO((base) + 0x3c) _MMIO 2407 drivers/gpu/drm/i915/i915_reg.h #define RING_SYNC_0(base) _MMIO((base) + 0x40) _MMIO 2408 drivers/gpu/drm/i915/i915_reg.h #define RING_SYNC_1(base) _MMIO((base) + 0x44) _MMIO 2409 drivers/gpu/drm/i915/i915_reg.h #define RING_SYNC_2(base) _MMIO((base) + 0x48) _MMIO 2423 drivers/gpu/drm/i915/i915_reg.h #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) _MMIO 2424 drivers/gpu/drm/i915/i915_reg.h #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) _MMIO 2425 drivers/gpu/drm/i915/i915_reg.h #define RING_HWS_PGA(base) _MMIO((base) + 0x80) _MMIO 2426 drivers/gpu/drm/i915/i915_reg.h #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) _MMIO 2427 drivers/gpu/drm/i915/i915_reg.h #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) _MMIO 2432 drivers/gpu/drm/i915/i915_reg.h #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) _MMIO 2434 drivers/gpu/drm/i915/i915_reg.h #define HSW_GTT_CACHE_EN _MMIO(0x4024) _MMIO 2436 drivers/gpu/drm/i915/i915_reg.h #define GEN7_WR_WATERMARK _MMIO(0x4028) _MMIO 2437 drivers/gpu/drm/i915/i915_reg.h #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) _MMIO 2438 drivers/gpu/drm/i915/i915_reg.h #define ARB_MODE _MMIO(0x4030) _MMIO 2441 drivers/gpu/drm/i915/i915_reg.h #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) _MMIO 2442 drivers/gpu/drm/i915/i915_reg.h #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) _MMIO 2444 drivers/gpu/drm/i915/i915_reg.h #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) _MMIO 2446 drivers/gpu/drm/i915/i915_reg.h #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) _MMIO 2447 drivers/gpu/drm/i915/i915_reg.h #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) _MMIO 2449 drivers/gpu/drm/i915/i915_reg.h #define GAMTARBMODE _MMIO(0x04a08) _MMIO 2452 drivers/gpu/drm/i915/i915_reg.h #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) _MMIO 2453 drivers/gpu/drm/i915/i915_reg.h #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id) _MMIO 2454 drivers/gpu/drm/i915/i915_reg.h #define GEN8_RING_FAULT_REG _MMIO(0x4094) _MMIO 2455 drivers/gpu/drm/i915/i915_reg.h #define GEN12_RING_FAULT_REG _MMIO(0xcec4) _MMIO 2461 drivers/gpu/drm/i915/i915_reg.h #define DONE_REG _MMIO(0x40b0) _MMIO 2462 drivers/gpu/drm/i915/i915_reg.h #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) _MMIO 2463 drivers/gpu/drm/i915/i915_reg.h #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) _MMIO 2464 drivers/gpu/drm/i915/i915_reg.h #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4) _MMIO 2465 drivers/gpu/drm/i915/i915_reg.h #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) _MMIO 2466 drivers/gpu/drm/i915/i915_reg.h #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) _MMIO 2467 drivers/gpu/drm/i915/i915_reg.h #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) _MMIO 2468 drivers/gpu/drm/i915/i915_reg.h #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) _MMIO 2469 drivers/gpu/drm/i915/i915_reg.h #define RING_ACTHD(base) _MMIO((base) + 0x74) _MMIO 2470 drivers/gpu/drm/i915/i915_reg.h #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) _MMIO 2471 drivers/gpu/drm/i915/i915_reg.h #define RING_NOPID(base) _MMIO((base) + 0x94) _MMIO 2472 drivers/gpu/drm/i915/i915_reg.h #define RING_IMR(base) _MMIO((base) + 0xa8) _MMIO 2473 drivers/gpu/drm/i915/i915_reg.h #define RING_HWSTAM(base) _MMIO((base) + 0x98) _MMIO 2474 drivers/gpu/drm/i915/i915_reg.h #define RING_TIMESTAMP(base) _MMIO((base) + 0x358) _MMIO 2475 drivers/gpu/drm/i915/i915_reg.h #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) _MMIO 2492 drivers/gpu/drm/i915/i915_reg.h #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) _MMIO 2508 drivers/gpu/drm/i915/i915_reg.h #define GEN7_TLB_RD_ADDR _MMIO(0x4700) _MMIO 2510 drivers/gpu/drm/i915/i915_reg.h #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) _MMIO 2513 drivers/gpu/drm/i915/i915_reg.h #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) _MMIO 2517 drivers/gpu/drm/i915/i915_reg.h #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) _MMIO 2523 drivers/gpu/drm/i915/i915_reg.h #define PRB0_TAIL _MMIO(0x2030) _MMIO 2524 drivers/gpu/drm/i915/i915_reg.h #define PRB0_HEAD _MMIO(0x2034) _MMIO 2525 drivers/gpu/drm/i915/i915_reg.h #define PRB0_START _MMIO(0x2038) _MMIO 2526 drivers/gpu/drm/i915/i915_reg.h #define PRB0_CTL _MMIO(0x203c) _MMIO 2527 drivers/gpu/drm/i915/i915_reg.h #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ _MMIO 2528 drivers/gpu/drm/i915/i915_reg.h #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ _MMIO 2529 drivers/gpu/drm/i915/i915_reg.h #define PRB1_START _MMIO(0x2048) /* 915+ only */ _MMIO 2530 drivers/gpu/drm/i915/i915_reg.h #define PRB1_CTL _MMIO(0x204c) /* 915+ only */ _MMIO 2532 drivers/gpu/drm/i915/i915_reg.h #define IPEIR_I965 _MMIO(0x2064) _MMIO 2533 drivers/gpu/drm/i915/i915_reg.h #define IPEHR_I965 _MMIO(0x2068) _MMIO 2534 drivers/gpu/drm/i915/i915_reg.h #define GEN7_SC_INSTDONE _MMIO(0x7100) _MMIO 2535 drivers/gpu/drm/i915/i915_reg.h #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) _MMIO 2536 drivers/gpu/drm/i915/i915_reg.h #define GEN7_ROW_INSTDONE _MMIO(0xe164) _MMIO 2537 drivers/gpu/drm/i915/i915_reg.h #define GEN8_MCR_SELECTOR _MMIO(0xfdc) _MMIO 2546 drivers/gpu/drm/i915/i915_reg.h #define RING_IPEIR(base) _MMIO((base) + 0x64) _MMIO 2547 drivers/gpu/drm/i915/i915_reg.h #define RING_IPEHR(base) _MMIO((base) + 0x68) _MMIO 2553 drivers/gpu/drm/i915/i915_reg.h #define RING_INSTDONE(base) _MMIO((base) + 0x6c) _MMIO 2554 drivers/gpu/drm/i915/i915_reg.h #define RING_INSTPS(base) _MMIO((base) + 0x70) _MMIO 2555 drivers/gpu/drm/i915/i915_reg.h #define RING_DMA_FADD(base) _MMIO((base) + 0x78) _MMIO 2556 drivers/gpu/drm/i915/i915_reg.h #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ _MMIO 2557 drivers/gpu/drm/i915/i915_reg.h #define RING_INSTPM(base) _MMIO((base) + 0xc0) _MMIO 2558 drivers/gpu/drm/i915/i915_reg.h #define RING_MI_MODE(base) _MMIO((base) + 0x9c) _MMIO 2559 drivers/gpu/drm/i915/i915_reg.h #define INSTPS _MMIO(0x2070) /* 965+ only */ _MMIO 2560 drivers/gpu/drm/i915/i915_reg.h #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ _MMIO 2561 drivers/gpu/drm/i915/i915_reg.h #define ACTHD_I965 _MMIO(0x2074) _MMIO 2562 drivers/gpu/drm/i915/i915_reg.h #define HWS_PGA _MMIO(0x2080) _MMIO 2565 drivers/gpu/drm/i915/i915_reg.h #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ _MMIO 2567 drivers/gpu/drm/i915/i915_reg.h #define IPEIR(base) _MMIO((base) + 0x88) _MMIO 2568 drivers/gpu/drm/i915/i915_reg.h #define IPEHR(base) _MMIO((base) + 0x8c) _MMIO 2569 drivers/gpu/drm/i915/i915_reg.h #define GEN2_INSTDONE _MMIO(0x2090) _MMIO 2570 drivers/gpu/drm/i915/i915_reg.h #define NOPID _MMIO(0x2094) _MMIO 2571 drivers/gpu/drm/i915/i915_reg.h #define HWSTAM _MMIO(0x2098) _MMIO 2572 drivers/gpu/drm/i915/i915_reg.h #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0) _MMIO 2573 drivers/gpu/drm/i915/i915_reg.h #define RING_BBSTATE(base) _MMIO((base) + 0x110) _MMIO 2575 drivers/gpu/drm/i915/i915_reg.h #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ _MMIO 2576 drivers/gpu/drm/i915/i915_reg.h #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */ _MMIO 2577 drivers/gpu/drm/i915/i915_reg.h #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */ _MMIO 2578 drivers/gpu/drm/i915/i915_reg.h #define RING_BBADDR(base) _MMIO((base) + 0x140) _MMIO 2579 drivers/gpu/drm/i915/i915_reg.h #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */ _MMIO 2580 drivers/gpu/drm/i915/i915_reg.h #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ _MMIO 2581 drivers/gpu/drm/i915/i915_reg.h #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ _MMIO 2582 drivers/gpu/drm/i915/i915_reg.h #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ _MMIO 2583 drivers/gpu/drm/i915/i915_reg.h #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ _MMIO 2585 drivers/gpu/drm/i915/i915_reg.h #define ERROR_GEN6 _MMIO(0x40a0) _MMIO 2586 drivers/gpu/drm/i915/i915_reg.h #define GEN7_ERR_INT _MMIO(0x44040) _MMIO 2598 drivers/gpu/drm/i915/i915_reg.h #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) _MMIO 2599 drivers/gpu/drm/i915/i915_reg.h #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) _MMIO 2600 drivers/gpu/drm/i915/i915_reg.h #define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8) _MMIO 2601 drivers/gpu/drm/i915/i915_reg.h #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc) _MMIO 2605 drivers/gpu/drm/i915/i915_reg.h #define FPGA_DBG _MMIO(0x42300) _MMIO 2608 drivers/gpu/drm/i915/i915_reg.h #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) _MMIO 2613 drivers/gpu/drm/i915/i915_reg.h #define DERRMR _MMIO(0x44050) _MMIO 2637 drivers/gpu/drm/i915/i915_reg.h #define _3D_CHICKEN _MMIO(0x2084) _MMIO 2639 drivers/gpu/drm/i915/i915_reg.h #define _3D_CHICKEN2 _MMIO(0x208c) _MMIO 2641 drivers/gpu/drm/i915/i915_reg.h #define FF_SLICE_CHICKEN _MMIO(0x2088) _MMIO 2649 drivers/gpu/drm/i915/i915_reg.h #define _3D_CHICKEN3 _MMIO(0x2090) _MMIO 2657 drivers/gpu/drm/i915/i915_reg.h #define MI_MODE _MMIO(0x209c) _MMIO 2664 drivers/gpu/drm/i915/i915_reg.h #define GEN6_GT_MODE _MMIO(0x20d0) _MMIO 2665 drivers/gpu/drm/i915/i915_reg.h #define GEN7_GT_MODE _MMIO(0x7008) _MMIO 2676 drivers/gpu/drm/i915/i915_reg.h #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) _MMIO 2681 drivers/gpu/drm/i915/i915_reg.h #define GEN8_STATE_ACK _MMIO(0x20F0) _MMIO 2682 drivers/gpu/drm/i915/i915_reg.h #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) _MMIO 2683 drivers/gpu/drm/i915/i915_reg.h #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) _MMIO 2692 drivers/gpu/drm/i915/i915_reg.h #define GFX_MODE _MMIO(0x2520) _MMIO 2693 drivers/gpu/drm/i915/i915_reg.h #define GFX_MODE_GEN7 _MMIO(0x229c) _MMIO 2694 drivers/gpu/drm/i915/i915_reg.h #define RING_MODE_GEN7(base) _MMIO((base) + 0x29c) _MMIO 2711 drivers/gpu/drm/i915/i915_reg.h #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) _MMIO 2712 drivers/gpu/drm/i915/i915_reg.h #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) _MMIO 2713 drivers/gpu/drm/i915/i915_reg.h #define SCPD0 _MMIO(0x209c) /* 915+ only */ _MMIO 2714 drivers/gpu/drm/i915/i915_reg.h #define GEN2_IER _MMIO(0x20a0) _MMIO 2715 drivers/gpu/drm/i915/i915_reg.h #define GEN2_IIR _MMIO(0x20a4) _MMIO 2716 drivers/gpu/drm/i915/i915_reg.h #define GEN2_IMR _MMIO(0x20a8) _MMIO 2717 drivers/gpu/drm/i915/i915_reg.h #define GEN2_ISR _MMIO(0x20ac) _MMIO 2718 drivers/gpu/drm/i915/i915_reg.h #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) _MMIO 2721 drivers/gpu/drm/i915/i915_reg.h #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) _MMIO 2722 drivers/gpu/drm/i915/i915_reg.h #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) _MMIO 2723 drivers/gpu/drm/i915/i915_reg.h #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) _MMIO 2724 drivers/gpu/drm/i915/i915_reg.h #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) _MMIO 2725 drivers/gpu/drm/i915/i915_reg.h #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) _MMIO 2726 drivers/gpu/drm/i915/i915_reg.h #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) _MMIO 2727 drivers/gpu/drm/i915/i915_reg.h #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) _MMIO 2731 drivers/gpu/drm/i915/i915_reg.h #define EIR _MMIO(0x20b0) _MMIO 2732 drivers/gpu/drm/i915/i915_reg.h #define EMR _MMIO(0x20b4) _MMIO 2733 drivers/gpu/drm/i915/i915_reg.h #define ESR _MMIO(0x20b8) _MMIO 2740 drivers/gpu/drm/i915/i915_reg.h #define INSTPM _MMIO(0x20c0) _MMIO 2748 drivers/gpu/drm/i915/i915_reg.h #define ACTHD(base) _MMIO((base) + 0xc8) _MMIO 2749 drivers/gpu/drm/i915/i915_reg.h #define MEM_MODE _MMIO(0x20cc) _MMIO 2753 drivers/gpu/drm/i915/i915_reg.h #define FW_BLC _MMIO(0x20d8) _MMIO 2754 drivers/gpu/drm/i915/i915_reg.h #define FW_BLC2 _MMIO(0x20dc) _MMIO 2755 drivers/gpu/drm/i915/i915_reg.h #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ _MMIO 2763 drivers/gpu/drm/i915/i915_reg.h #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ _MMIO 2765 drivers/gpu/drm/i915/i915_reg.h #define MBUS_ABOX_CTL _MMIO(0x45038) _MMIO 2786 drivers/gpu/drm/i915/i915_reg.h #define MBUS_UBOX_CTL _MMIO(0x4503C) _MMIO 2787 drivers/gpu/drm/i915/i915_reg.h #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) _MMIO 2788 drivers/gpu/drm/i915/i915_reg.h #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) _MMIO 2852 drivers/gpu/drm/i915/i915_reg.h #define MI_STATE _MMIO(0x20e4) /* gen2 only */ _MMIO 2856 drivers/gpu/drm/i915/i915_reg.h #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ _MMIO 2865 drivers/gpu/drm/i915/i915_reg.h #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ _MMIO 2866 drivers/gpu/drm/i915/i915_reg.h #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) _MMIO 2868 drivers/gpu/drm/i915/i915_reg.h #define ECOSKPD _MMIO(0x21d0) _MMIO 2873 drivers/gpu/drm/i915/i915_reg.h #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ _MMIO 2876 drivers/gpu/drm/i915/i915_reg.h #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ _MMIO 2881 drivers/gpu/drm/i915/i915_reg.h #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0) _MMIO 2885 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050) _MMIO 2890 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RCS_PWR_FSM _MMIO(0x22ac) _MMIO 2891 drivers/gpu/drm/i915/i915_reg.h #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4) _MMIO 2893 drivers/gpu/drm/i915/i915_reg.h #define GEN10_CACHE_MODE_SS _MMIO(0xe420) _MMIO 2897 drivers/gpu/drm/i915/i915_reg.h #define HSW_PAVP_FUSE1 _MMIO(0x911C) _MMIO 2904 drivers/gpu/drm/i915/i915_reg.h #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) _MMIO 2916 drivers/gpu/drm/i915/i915_reg.h #define GEN8_FUSE2 _MMIO(0x9120) _MMIO 2930 drivers/gpu/drm/i915/i915_reg.h #define GEN10_MIRROR_FUSE3 _MMIO(0x9118) _MMIO 2934 drivers/gpu/drm/i915/i915_reg.h #define GEN8_EU_DISABLE0 _MMIO(0x9134) _MMIO 2939 drivers/gpu/drm/i915/i915_reg.h #define GEN8_EU_DISABLE1 _MMIO(0x9138) _MMIO 2944 drivers/gpu/drm/i915/i915_reg.h #define GEN8_EU_DISABLE2 _MMIO(0x913c) _MMIO 2947 drivers/gpu/drm/i915/i915_reg.h #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4) _MMIO 2949 drivers/gpu/drm/i915/i915_reg.h #define GEN10_EU_DISABLE3 _MMIO(0x9140) _MMIO 2952 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) _MMIO 2957 drivers/gpu/drm/i915/i915_reg.h #define GEN11_EU_DISABLE _MMIO(0x9134) _MMIO 2960 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138) _MMIO 2963 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C) _MMIO 2965 drivers/gpu/drm/i915/i915_reg.h #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) _MMIO 3046 drivers/gpu/drm/i915/i915_reg.h #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) _MMIO 3058 drivers/gpu/drm/i915/i915_reg.h #define GEN6_BSD_RNCID _MMIO(0x12198) _MMIO 3060 drivers/gpu/drm/i915/i915_reg.h #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) _MMIO 3081 drivers/gpu/drm/i915/i915_reg.h #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ _MMIO 3082 drivers/gpu/drm/i915/i915_reg.h #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ _MMIO 3083 drivers/gpu/drm/i915/i915_reg.h #define FBC_CONTROL _MMIO(0x3208) _MMIO 3091 drivers/gpu/drm/i915/i915_reg.h #define FBC_COMMAND _MMIO(0x320c) _MMIO 3093 drivers/gpu/drm/i915/i915_reg.h #define FBC_STATUS _MMIO(0x3210) _MMIO 3098 drivers/gpu/drm/i915/i915_reg.h #define FBC_CONTROL2 _MMIO(0x3214) _MMIO 3106 drivers/gpu/drm/i915/i915_reg.h #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ _MMIO 3107 drivers/gpu/drm/i915/i915_reg.h #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) _MMIO 3111 drivers/gpu/drm/i915/i915_reg.h #define FBC_LLC_READ_CTRL _MMIO(0x9044) _MMIO 3115 drivers/gpu/drm/i915/i915_reg.h #define DPFC_CB_BASE _MMIO(0x3200) _MMIO 3116 drivers/gpu/drm/i915/i915_reg.h #define DPFC_CONTROL _MMIO(0x3208) _MMIO 3127 drivers/gpu/drm/i915/i915_reg.h #define DPFC_RECOMP_CTL _MMIO(0x320c) _MMIO 3133 drivers/gpu/drm/i915/i915_reg.h #define DPFC_STATUS _MMIO(0x3210) _MMIO 3138 drivers/gpu/drm/i915/i915_reg.h #define DPFC_STATUS2 _MMIO(0x3214) _MMIO 3139 drivers/gpu/drm/i915/i915_reg.h #define DPFC_FENCE_YOFF _MMIO(0x3218) _MMIO 3140 drivers/gpu/drm/i915/i915_reg.h #define DPFC_CHICKEN _MMIO(0x3224) _MMIO 3144 drivers/gpu/drm/i915/i915_reg.h #define ILK_DPFC_CB_BASE _MMIO(0x43200) _MMIO 3145 drivers/gpu/drm/i915/i915_reg.h #define ILK_DPFC_CONTROL _MMIO(0x43208) _MMIO 3149 drivers/gpu/drm/i915/i915_reg.h #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) _MMIO 3150 drivers/gpu/drm/i915/i915_reg.h #define ILK_DPFC_STATUS _MMIO(0x43210) _MMIO 3152 drivers/gpu/drm/i915/i915_reg.h #define IVB_FBC_STATUS2 _MMIO(0x43214) _MMIO 3155 drivers/gpu/drm/i915/i915_reg.h #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) _MMIO 3156 drivers/gpu/drm/i915/i915_reg.h #define ILK_DPFC_CHICKEN _MMIO(0x43224) _MMIO 3160 drivers/gpu/drm/i915/i915_reg.h #define ILK_FBC_RT_BASE _MMIO(0x2128) _MMIO 3164 drivers/gpu/drm/i915/i915_reg.h #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) _MMIO 3174 drivers/gpu/drm/i915/i915_reg.h #define SNB_DPFC_CTL_SA _MMIO(0x100100) _MMIO 3176 drivers/gpu/drm/i915/i915_reg.h #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) _MMIO 3179 drivers/gpu/drm/i915/i915_reg.h #define IVB_FBC_RT_BASE _MMIO(0x7020) _MMIO 3181 drivers/gpu/drm/i915/i915_reg.h #define IPS_CTL _MMIO(0x43408) _MMIO 3184 drivers/gpu/drm/i915/i915_reg.h #define MSG_FBC_REND_STATE _MMIO(0x50380) _MMIO 3191 drivers/gpu/drm/i915/i915_reg.h #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \ _MMIO 3209 drivers/gpu/drm/i915/i915_reg.h #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ _MMIO 3218 drivers/gpu/drm/i915/i915_reg.h #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ _MMIO 3233 drivers/gpu/drm/i915/i915_reg.h #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ _MMIO 3241 drivers/gpu/drm/i915/i915_reg.h #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ _MMIO 3242 drivers/gpu/drm/i915/i915_reg.h #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ _MMIO 3248 drivers/gpu/drm/i915/i915_reg.h #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ _MMIO 3259 drivers/gpu/drm/i915/i915_reg.h #define VGA0 _MMIO(0x6000) _MMIO 3260 drivers/gpu/drm/i915/i915_reg.h #define VGA1 _MMIO(0x6004) _MMIO 3261 drivers/gpu/drm/i915/i915_reg.h #define VGA_PD _MMIO(0x6010) _MMIO 3297 drivers/gpu/drm/i915/i915_reg.h #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) _MMIO 3299 drivers/gpu/drm/i915/i915_reg.h #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) _MMIO 3310 drivers/gpu/drm/i915/i915_reg.h #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) _MMIO 3395 drivers/gpu/drm/i915/i915_reg.h #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) _MMIO 3411 drivers/gpu/drm/i915/i915_reg.h #define DPLL_TEST _MMIO(0x606c) _MMIO 3422 drivers/gpu/drm/i915/i915_reg.h #define D_STATE _MMIO(0x6104) _MMIO 3427 drivers/gpu/drm/i915/i915_reg.h #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) _MMIO 3467 drivers/gpu/drm/i915/i915_reg.h #define RENCLK_GATE_D1 _MMIO(0x6204) _MMIO 3531 drivers/gpu/drm/i915/i915_reg.h #define RENCLK_GATE_D2 _MMIO(0x6208) _MMIO 3536 drivers/gpu/drm/i915/i915_reg.h #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ _MMIO 3539 drivers/gpu/drm/i915/i915_reg.h #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ _MMIO 3540 drivers/gpu/drm/i915/i915_reg.h #define DEUC _MMIO(0x6214) /* CRL only */ _MMIO 3542 drivers/gpu/drm/i915/i915_reg.h #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) _MMIO 3545 drivers/gpu/drm/i915/i915_reg.h #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) _MMIO 3547 drivers/gpu/drm/i915/i915_reg.h #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) _MMIO 3552 drivers/gpu/drm/i915/i915_reg.h #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) _MMIO 3559 drivers/gpu/drm/i915/i915_reg.h #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) _MMIO 3567 drivers/gpu/drm/i915/i915_reg.h #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ _MMIO 3588 drivers/gpu/drm/i915/i915_reg.h #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) _MMIO 3589 drivers/gpu/drm/i915/i915_reg.h #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) _MMIO 3595 drivers/gpu/drm/i915/i915_reg.h #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) _MMIO 3598 drivers/gpu/drm/i915/i915_reg.h #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) _MMIO 3605 drivers/gpu/drm/i915/i915_reg.h #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) _MMIO 3609 drivers/gpu/drm/i915/i915_reg.h #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) _MMIO 3613 drivers/gpu/drm/i915/i915_reg.h #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) _MMIO 3614 drivers/gpu/drm/i915/i915_reg.h #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) _MMIO 3617 drivers/gpu/drm/i915/i915_reg.h #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) _MMIO 3618 drivers/gpu/drm/i915/i915_reg.h #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) _MMIO 3619 drivers/gpu/drm/i915/i915_reg.h #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) _MMIO 3639 drivers/gpu/drm/i915/i915_reg.h #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) _MMIO 3643 drivers/gpu/drm/i915/i915_reg.h #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c) _MMIO 3646 drivers/gpu/drm/i915/i915_reg.h #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) _MMIO 3666 drivers/gpu/drm/i915/i915_reg.h #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) _MMIO 3667 drivers/gpu/drm/i915/i915_reg.h #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) _MMIO 3669 drivers/gpu/drm/i915/i915_reg.h #define TSC1 _MMIO(0x11001) _MMIO 3671 drivers/gpu/drm/i915/i915_reg.h #define TR1 _MMIO(0x11006) _MMIO 3672 drivers/gpu/drm/i915/i915_reg.h #define TSFS _MMIO(0x11020) _MMIO 3677 drivers/gpu/drm/i915/i915_reg.h #define CRSTANDVID _MMIO(0x11100) _MMIO 3678 drivers/gpu/drm/i915/i915_reg.h #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ _MMIO 3681 drivers/gpu/drm/i915/i915_reg.h #define VIDFREQ_BASE _MMIO(0x11110) _MMIO 3682 drivers/gpu/drm/i915/i915_reg.h #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ _MMIO 3683 drivers/gpu/drm/i915/i915_reg.h #define VIDFREQ2 _MMIO(0x11114) _MMIO 3684 drivers/gpu/drm/i915/i915_reg.h #define VIDFREQ3 _MMIO(0x11118) _MMIO 3685 drivers/gpu/drm/i915/i915_reg.h #define VIDFREQ4 _MMIO(0x1111c) _MMIO 3697 drivers/gpu/drm/i915/i915_reg.h #define INTTOEXT_BASE_ILK _MMIO(0x11300) _MMIO 3698 drivers/gpu/drm/i915/i915_reg.h #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ _MMIO 3707 drivers/gpu/drm/i915/i915_reg.h #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ _MMIO 3722 drivers/gpu/drm/i915/i915_reg.h #define MEMIHYST _MMIO(0x1117c) _MMIO 3723 drivers/gpu/drm/i915/i915_reg.h #define MEMINTREN _MMIO(0x11180) /* 16 bits */ _MMIO 3733 drivers/gpu/drm/i915/i915_reg.h #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ _MMIO 3753 drivers/gpu/drm/i915/i915_reg.h #define MEMINTRSTS _MMIO(0x11184) _MMIO 3762 drivers/gpu/drm/i915/i915_reg.h #define MEMMODECTL _MMIO(0x11190) _MMIO 3779 drivers/gpu/drm/i915/i915_reg.h #define RCBMAXAVG _MMIO(0x1119c) _MMIO 3780 drivers/gpu/drm/i915/i915_reg.h #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ _MMIO 3792 drivers/gpu/drm/i915/i915_reg.h #define MEMSTAT_CTG _MMIO(0x111a0) _MMIO 3793 drivers/gpu/drm/i915/i915_reg.h #define RCBMINAVG _MMIO(0x111a0) _MMIO 3794 drivers/gpu/drm/i915/i915_reg.h #define RCUPEI _MMIO(0x111b0) _MMIO 3795 drivers/gpu/drm/i915/i915_reg.h #define RCDNEI _MMIO(0x111b4) _MMIO 3796 drivers/gpu/drm/i915/i915_reg.h #define RSTDBYCTL _MMIO(0x111b8) _MMIO 3840 drivers/gpu/drm/i915/i915_reg.h #define VIDCTL _MMIO(0x111c0) _MMIO 3841 drivers/gpu/drm/i915/i915_reg.h #define VIDSTS _MMIO(0x111c8) _MMIO 3842 drivers/gpu/drm/i915/i915_reg.h #define VIDSTART _MMIO(0x111cc) /* 8 bits */ _MMIO 3843 drivers/gpu/drm/i915/i915_reg.h #define MEMSTAT_ILK _MMIO(0x111f8) _MMIO 3854 drivers/gpu/drm/i915/i915_reg.h #define RCPREVBSYTUPAVG _MMIO(0x113b8) _MMIO 3855 drivers/gpu/drm/i915/i915_reg.h #define RCPREVBSYTDNAVG _MMIO(0x113bc) _MMIO 3856 drivers/gpu/drm/i915/i915_reg.h #define PMMISC _MMIO(0x11214) _MMIO 3858 drivers/gpu/drm/i915/i915_reg.h #define SDEW _MMIO(0x1124c) _MMIO 3859 drivers/gpu/drm/i915/i915_reg.h #define CSIEW0 _MMIO(0x11250) _MMIO 3860 drivers/gpu/drm/i915/i915_reg.h #define CSIEW1 _MMIO(0x11254) _MMIO 3861 drivers/gpu/drm/i915/i915_reg.h #define CSIEW2 _MMIO(0x11258) _MMIO 3862 drivers/gpu/drm/i915/i915_reg.h #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ _MMIO 3863 drivers/gpu/drm/i915/i915_reg.h #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ _MMIO 3864 drivers/gpu/drm/i915/i915_reg.h #define MCHAFE _MMIO(0x112c0) _MMIO 3865 drivers/gpu/drm/i915/i915_reg.h #define CSIEC _MMIO(0x112e0) _MMIO 3866 drivers/gpu/drm/i915/i915_reg.h #define DMIEC _MMIO(0x112e4) _MMIO 3867 drivers/gpu/drm/i915/i915_reg.h #define DDREC _MMIO(0x112e8) _MMIO 3868 drivers/gpu/drm/i915/i915_reg.h #define PEG0EC _MMIO(0x112ec) _MMIO 3869 drivers/gpu/drm/i915/i915_reg.h #define PEG1EC _MMIO(0x112f0) _MMIO 3870 drivers/gpu/drm/i915/i915_reg.h #define GFXEC _MMIO(0x112f4) _MMIO 3871 drivers/gpu/drm/i915/i915_reg.h #define RPPREVBSYTUPAVG _MMIO(0x113b8) _MMIO 3872 drivers/gpu/drm/i915/i915_reg.h #define RPPREVBSYTDNAVG _MMIO(0x113bc) _MMIO 3873 drivers/gpu/drm/i915/i915_reg.h #define ECR _MMIO(0x11600) _MMIO 3877 drivers/gpu/drm/i915/i915_reg.h #define OGW0 _MMIO(0x11608) _MMIO 3878 drivers/gpu/drm/i915/i915_reg.h #define OGW1 _MMIO(0x1160c) _MMIO 3879 drivers/gpu/drm/i915/i915_reg.h #define EG0 _MMIO(0x11610) _MMIO 3880 drivers/gpu/drm/i915/i915_reg.h #define EG1 _MMIO(0x11614) _MMIO 3881 drivers/gpu/drm/i915/i915_reg.h #define EG2 _MMIO(0x11618) _MMIO 3882 drivers/gpu/drm/i915/i915_reg.h #define EG3 _MMIO(0x1161c) _MMIO 3883 drivers/gpu/drm/i915/i915_reg.h #define EG4 _MMIO(0x11620) _MMIO 3884 drivers/gpu/drm/i915/i915_reg.h #define EG5 _MMIO(0x11624) _MMIO 3885 drivers/gpu/drm/i915/i915_reg.h #define EG6 _MMIO(0x11628) _MMIO 3886 drivers/gpu/drm/i915/i915_reg.h #define EG7 _MMIO(0x1162c) _MMIO 3887 drivers/gpu/drm/i915/i915_reg.h #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ _MMIO 3888 drivers/gpu/drm/i915/i915_reg.h #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ _MMIO 3889 drivers/gpu/drm/i915/i915_reg.h #define LCFUSE02 _MMIO(0x116c0) _MMIO 3891 drivers/gpu/drm/i915/i915_reg.h #define CSIPLL0 _MMIO(0x12c10) _MMIO 3892 drivers/gpu/drm/i915/i915_reg.h #define DDRMPLL1 _MMIO(0X12c20) _MMIO 3893 drivers/gpu/drm/i915/i915_reg.h #define PEG_BAND_GAP_DATA _MMIO(0x14d68) _MMIO 3895 drivers/gpu/drm/i915/i915_reg.h #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) _MMIO 3898 drivers/gpu/drm/i915/i915_reg.h #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) _MMIO 3899 drivers/gpu/drm/i915/i915_reg.h #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) _MMIO 3900 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) _MMIO 3901 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) _MMIO 3902 drivers/gpu/drm/i915/i915_reg.h #define BXT_RP_STATE_CAP _MMIO(0x138170) _MMIO 3932 drivers/gpu/drm/i915/i915_reg.h #define CCID(base) _MMIO((base) + 0x180) _MMIO 3949 drivers/gpu/drm/i915/i915_reg.h #define CXT_SIZE _MMIO(0x21a0) _MMIO 3958 drivers/gpu/drm/i915/i915_reg.h #define GEN7_CXT_SIZE _MMIO(0x21a8) _MMIO 3998 drivers/gpu/drm/i915/i915_reg.h #define CHV_CLK_CTL1 _MMIO(0x101100) _MMIO 3999 drivers/gpu/drm/i915/i915_reg.h #define VLV_CLK_CTL2 _MMIO(0x101104) _MMIO 4006 drivers/gpu/drm/i915/i915_reg.h #define OVADD _MMIO(0x30000) _MMIO 4007 drivers/gpu/drm/i915/i915_reg.h #define DOVSTA _MMIO(0x30008) _MMIO 4009 drivers/gpu/drm/i915/i915_reg.h #define OGAMC5 _MMIO(0x30010) _MMIO 4010 drivers/gpu/drm/i915/i915_reg.h #define OGAMC4 _MMIO(0x30014) _MMIO 4011 drivers/gpu/drm/i915/i915_reg.h #define OGAMC3 _MMIO(0x30018) _MMIO 4012 drivers/gpu/drm/i915/i915_reg.h #define OGAMC2 _MMIO(0x3001c) _MMIO 4013 drivers/gpu/drm/i915/i915_reg.h #define OGAMC1 _MMIO(0x30020) _MMIO 4014 drivers/gpu/drm/i915/i915_reg.h #define OGAMC0 _MMIO(0x30024) _MMIO 4019 drivers/gpu/drm/i915/i915_reg.h #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) _MMIO 4024 drivers/gpu/drm/i915/i915_reg.h #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) _MMIO 4043 drivers/gpu/drm/i915/i915_reg.h #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) _MMIO 4048 drivers/gpu/drm/i915/i915_reg.h #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524) _MMIO 4051 drivers/gpu/drm/i915/i915_reg.h #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) _MMIO 4056 drivers/gpu/drm/i915/i915_reg.h #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4) _MMIO 4060 drivers/gpu/drm/i915/i915_reg.h #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) _MMIO 4204 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) _MMIO 4231 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_IMR _MMIO(0x64834) _MMIO 4232 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_IIR _MMIO(0x64838) _MMIO 4241 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) _MMIO 4248 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */ _MMIO 4250 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40) _MMIO 4275 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44) _MMIO 4278 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */ _MMIO 4286 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR2_CTL _MMIO(0x6f900) _MMIO 4327 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR2_STATUS _MMIO(0x6f940) _MMIO 4334 drivers/gpu/drm/i915/i915_reg.h #define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1)) _MMIO 4341 drivers/gpu/drm/i915/i915_reg.h #define ADPA _MMIO(0x61100) _MMIO 4342 drivers/gpu/drm/i915/i915_reg.h #define PCH_ADPA _MMIO(0xe1100) _MMIO 4343 drivers/gpu/drm/i915/i915_reg.h #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) _MMIO 4390 drivers/gpu/drm/i915/i915_reg.h #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) _MMIO 4420 drivers/gpu/drm/i915/i915_reg.h #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) _MMIO 4488 drivers/gpu/drm/i915/i915_reg.h #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) _MMIO 4489 drivers/gpu/drm/i915/i915_reg.h #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) _MMIO 4492 drivers/gpu/drm/i915/i915_reg.h #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) _MMIO 4493 drivers/gpu/drm/i915/i915_reg.h #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) _MMIO 4494 drivers/gpu/drm/i915/i915_reg.h #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) _MMIO 4495 drivers/gpu/drm/i915/i915_reg.h #define PCH_SDVOB _MMIO(0xe1140) _MMIO 4497 drivers/gpu/drm/i915/i915_reg.h #define PCH_HDMIC _MMIO(0xe1150) _MMIO 4498 drivers/gpu/drm/i915/i915_reg.h #define PCH_HDMID _MMIO(0xe1160) _MMIO 4500 drivers/gpu/drm/i915/i915_reg.h #define PORT_DFT_I9XX _MMIO(0x61150) _MMIO 4502 drivers/gpu/drm/i915/i915_reg.h #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) _MMIO 4565 drivers/gpu/drm/i915/i915_reg.h #define DVOA _MMIO(_DVOA) _MMIO 4567 drivers/gpu/drm/i915/i915_reg.h #define DVOB _MMIO(_DVOB) _MMIO 4569 drivers/gpu/drm/i915/i915_reg.h #define DVOC _MMIO(_DVOC) _MMIO 4596 drivers/gpu/drm/i915/i915_reg.h #define DVOA_SRCDIM _MMIO(0x61124) _MMIO 4597 drivers/gpu/drm/i915/i915_reg.h #define DVOB_SRCDIM _MMIO(0x61144) _MMIO 4598 drivers/gpu/drm/i915/i915_reg.h #define DVOC_SRCDIM _MMIO(0x61164) _MMIO 4603 drivers/gpu/drm/i915/i915_reg.h #define LVDS _MMIO(0x61180) _MMIO 4656 drivers/gpu/drm/i915/i915_reg.h #define VIDEO_DIP_DATA _MMIO(0x61178) _MMIO 4663 drivers/gpu/drm/i915/i915_reg.h #define VIDEO_DIP_CTL _MMIO(0x61170) _MMIO 4704 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ _MMIO 4714 drivers/gpu/drm/i915/i915_reg.h #define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \ _MMIO 4777 drivers/gpu/drm/i915/i915_reg.h #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) _MMIO 4795 drivers/gpu/drm/i915/i915_reg.h #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) _MMIO 4807 drivers/gpu/drm/i915/i915_reg.h #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) _MMIO 4825 drivers/gpu/drm/i915/i915_reg.h #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ _MMIO 4848 drivers/gpu/drm/i915/i915_reg.h #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) _MMIO 4870 drivers/gpu/drm/i915/i915_reg.h #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) _MMIO 4875 drivers/gpu/drm/i915/i915_reg.h #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) _MMIO 4876 drivers/gpu/drm/i915/i915_reg.h #define BLC_PWM_CPU_CTL _MMIO(0x48254) _MMIO 4878 drivers/gpu/drm/i915/i915_reg.h #define HSW_BLC_PWM2_CTL _MMIO(0x48350) _MMIO 4882 drivers/gpu/drm/i915/i915_reg.h #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) _MMIO 4886 drivers/gpu/drm/i915/i915_reg.h #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) _MMIO 4888 drivers/gpu/drm/i915/i915_reg.h #define UTIL_PIN_CTL _MMIO(0x48400) _MMIO 4915 drivers/gpu/drm/i915/i915_reg.h #define PCH_GTC_CTL _MMIO(0xe7000) _MMIO 4919 drivers/gpu/drm/i915/i915_reg.h #define TV_CTL _MMIO(0x68000) _MMIO 4989 drivers/gpu/drm/i915/i915_reg.h #define TV_DAC _MMIO(0x68004) _MMIO 5040 drivers/gpu/drm/i915/i915_reg.h #define TV_CSC_Y _MMIO(0x68010) _MMIO 5046 drivers/gpu/drm/i915/i915_reg.h #define TV_CSC_Y2 _MMIO(0x68014) _MMIO 5057 drivers/gpu/drm/i915/i915_reg.h #define TV_CSC_U _MMIO(0x68018) _MMIO 5063 drivers/gpu/drm/i915/i915_reg.h #define TV_CSC_U2 _MMIO(0x6801c) _MMIO 5074 drivers/gpu/drm/i915/i915_reg.h #define TV_CSC_V _MMIO(0x68020) _MMIO 5080 drivers/gpu/drm/i915/i915_reg.h #define TV_CSC_V2 _MMIO(0x68024) _MMIO 5091 drivers/gpu/drm/i915/i915_reg.h #define TV_CLR_KNOBS _MMIO(0x68028) _MMIO 5105 drivers/gpu/drm/i915/i915_reg.h #define TV_CLR_LEVEL _MMIO(0x6802c) _MMIO 5113 drivers/gpu/drm/i915/i915_reg.h #define TV_H_CTL_1 _MMIO(0x68030) _MMIO 5121 drivers/gpu/drm/i915/i915_reg.h #define TV_H_CTL_2 _MMIO(0x68034) _MMIO 5131 drivers/gpu/drm/i915/i915_reg.h #define TV_H_CTL_3 _MMIO(0x68038) _MMIO 5139 drivers/gpu/drm/i915/i915_reg.h #define TV_V_CTL_1 _MMIO(0x6803c) _MMIO 5150 drivers/gpu/drm/i915/i915_reg.h #define TV_V_CTL_2 _MMIO(0x68040) _MMIO 5166 drivers/gpu/drm/i915/i915_reg.h #define TV_V_CTL_3 _MMIO(0x68044) _MMIO 5184 drivers/gpu/drm/i915/i915_reg.h #define TV_V_CTL_4 _MMIO(0x68048) _MMIO 5198 drivers/gpu/drm/i915/i915_reg.h #define TV_V_CTL_5 _MMIO(0x6804c) _MMIO 5212 drivers/gpu/drm/i915/i915_reg.h #define TV_V_CTL_6 _MMIO(0x68050) _MMIO 5226 drivers/gpu/drm/i915/i915_reg.h #define TV_V_CTL_7 _MMIO(0x68054) _MMIO 5240 drivers/gpu/drm/i915/i915_reg.h #define TV_SC_CTL_1 _MMIO(0x68060) _MMIO 5262 drivers/gpu/drm/i915/i915_reg.h #define TV_SC_CTL_2 _MMIO(0x68064) _MMIO 5270 drivers/gpu/drm/i915/i915_reg.h #define TV_SC_CTL_3 _MMIO(0x68068) _MMIO 5278 drivers/gpu/drm/i915/i915_reg.h #define TV_WIN_POS _MMIO(0x68070) _MMIO 5286 drivers/gpu/drm/i915/i915_reg.h #define TV_WIN_SIZE _MMIO(0x68074) _MMIO 5298 drivers/gpu/drm/i915/i915_reg.h #define TV_FILTER_CTL_1 _MMIO(0x68080) _MMIO 5331 drivers/gpu/drm/i915/i915_reg.h #define TV_FILTER_CTL_2 _MMIO(0x68084) _MMIO 5347 drivers/gpu/drm/i915/i915_reg.h #define TV_FILTER_CTL_3 _MMIO(0x68088) _MMIO 5367 drivers/gpu/drm/i915/i915_reg.h #define TV_CC_CONTROL _MMIO(0x68090) _MMIO 5383 drivers/gpu/drm/i915/i915_reg.h #define TV_CC_DATA _MMIO(0x68094) _MMIO 5392 drivers/gpu/drm/i915/i915_reg.h #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ _MMIO 5393 drivers/gpu/drm/i915/i915_reg.h #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ _MMIO 5394 drivers/gpu/drm/i915/i915_reg.h #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ _MMIO 5395 drivers/gpu/drm/i915/i915_reg.h #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ _MMIO 5398 drivers/gpu/drm/i915/i915_reg.h #define DP_A _MMIO(0x64000) /* eDP */ _MMIO 5399 drivers/gpu/drm/i915/i915_reg.h #define DP_B _MMIO(0x64100) _MMIO 5400 drivers/gpu/drm/i915/i915_reg.h #define DP_C _MMIO(0x64200) _MMIO 5401 drivers/gpu/drm/i915/i915_reg.h #define DP_D _MMIO(0x64300) _MMIO 5403 drivers/gpu/drm/i915/i915_reg.h #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) _MMIO 5404 drivers/gpu/drm/i915/i915_reg.h #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) _MMIO 5405 drivers/gpu/drm/i915/i915_reg.h #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) _MMIO 5538 drivers/gpu/drm/i915/i915_reg.h #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ _MMIO 5778 drivers/gpu/drm/i915/i915_reg.h #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) _MMIO 5799 drivers/gpu/drm/i915/i915_reg.h #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ _MMIO 5829 drivers/gpu/drm/i915/i915_reg.h #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) _MMIO 5844 drivers/gpu/drm/i915/i915_reg.h #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ _MMIO 5857 drivers/gpu/drm/i915/i915_reg.h #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ _MMIO 5864 drivers/gpu/drm/i915/i915_reg.h #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) _MMIO 5875 drivers/gpu/drm/i915/i915_reg.h #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) _MMIO 5891 drivers/gpu/drm/i915/i915_reg.h #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) _MMIO 5902 drivers/gpu/drm/i915/i915_reg.h #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) _MMIO 5909 drivers/gpu/drm/i915/i915_reg.h #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) _MMIO 5918 drivers/gpu/drm/i915/i915_reg.h #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) _MMIO 5921 drivers/gpu/drm/i915/i915_reg.h #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) _MMIO 5922 drivers/gpu/drm/i915/i915_reg.h #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ _MMIO 5931 drivers/gpu/drm/i915/i915_reg.h #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) _MMIO 5940 drivers/gpu/drm/i915/i915_reg.h #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ _MMIO 5951 drivers/gpu/drm/i915/i915_reg.h #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) _MMIO 5972 drivers/gpu/drm/i915/i915_reg.h #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) _MMIO 5995 drivers/gpu/drm/i915/i915_reg.h #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) _MMIO 6003 drivers/gpu/drm/i915/i915_reg.h #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) _MMIO 6007 drivers/gpu/drm/i915/i915_reg.h #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) _MMIO 6063 drivers/gpu/drm/i915/i915_reg.h #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) _MMIO 6071 drivers/gpu/drm/i915/i915_reg.h _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) _MMIO 6077 drivers/gpu/drm/i915/i915_reg.h _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) _MMIO 6080 drivers/gpu/drm/i915/i915_reg.h #define WM0_PIPEA_ILK _MMIO(0x45100) _MMIO 6087 drivers/gpu/drm/i915/i915_reg.h #define WM0_PIPEB_ILK _MMIO(0x45104) _MMIO 6088 drivers/gpu/drm/i915/i915_reg.h #define WM0_PIPEC_IVB _MMIO(0x45200) _MMIO 6089 drivers/gpu/drm/i915/i915_reg.h #define WM1_LP_ILK _MMIO(0x45108) _MMIO 6099 drivers/gpu/drm/i915/i915_reg.h #define WM2_LP_ILK _MMIO(0x4510c) _MMIO 6101 drivers/gpu/drm/i915/i915_reg.h #define WM3_LP_ILK _MMIO(0x45110) _MMIO 6103 drivers/gpu/drm/i915/i915_reg.h #define WM1S_LP_ILK _MMIO(0x45120) _MMIO 6104 drivers/gpu/drm/i915/i915_reg.h #define WM2S_LP_IVB _MMIO(0x45124) _MMIO 6105 drivers/gpu/drm/i915/i915_reg.h #define WM3S_LP_IVB _MMIO(0x45128) _MMIO 6113 drivers/gpu/drm/i915/i915_reg.h #define MLTR_ILK _MMIO(0x11222) _MMIO 6121 drivers/gpu/drm/i915/i915_reg.h #define SSKPD _MMIO(0x5d10) _MMIO 6193 drivers/gpu/drm/i915/i915_reg.h #define CURSIZE _MMIO(0x700a0) /* 845/865 */ _MMIO 6274 drivers/gpu/drm/i915/i915_reg.h #define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ _MMIO 6310 drivers/gpu/drm/i915/i915_reg.h #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) _MMIO 6311 drivers/gpu/drm/i915/i915_reg.h #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) _MMIO 6312 drivers/gpu/drm/i915/i915_reg.h #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) _MMIO 6313 drivers/gpu/drm/i915/i915_reg.h #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) _MMIO 6417 drivers/gpu/drm/i915/i915_reg.h #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ _MMIO 6418 drivers/gpu/drm/i915/i915_reg.h #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ _MMIO 6419 drivers/gpu/drm/i915/i915_reg.h #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ _MMIO 6499 drivers/gpu/drm/i915/i915_reg.h #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ _MMIO 6500 drivers/gpu/drm/i915/i915_reg.h #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ _MMIO 6501 drivers/gpu/drm/i915/i915_reg.h #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ _MMIO 6564 drivers/gpu/drm/i915/i915_reg.h _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) _MMIO 6579 drivers/gpu/drm/i915/i915_reg.h #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ _MMIO 6589 drivers/gpu/drm/i915/i915_reg.h _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) _MMIO 6931 drivers/gpu/drm/i915/i915_reg.h #define VGACNTRL _MMIO(0x71400) _MMIO 6936 drivers/gpu/drm/i915/i915_reg.h #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) _MMIO 6940 drivers/gpu/drm/i915/i915_reg.h #define CPU_VGACNTRL _MMIO(0x41000) _MMIO 6942 drivers/gpu/drm/i915/i915_reg.h #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) _MMIO 6955 drivers/gpu/drm/i915/i915_reg.h #define RR_HW_CTL _MMIO(0x45300) _MMIO 6959 drivers/gpu/drm/i915/i915_reg.h #define FDI_PLL_BIOS_0 _MMIO(0x46000) _MMIO 6961 drivers/gpu/drm/i915/i915_reg.h #define FDI_PLL_BIOS_1 _MMIO(0x46004) _MMIO 6962 drivers/gpu/drm/i915/i915_reg.h #define FDI_PLL_BIOS_2 _MMIO(0x46008) _MMIO 6963 drivers/gpu/drm/i915/i915_reg.h #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) _MMIO 6964 drivers/gpu/drm/i915/i915_reg.h #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) _MMIO 6965 drivers/gpu/drm/i915/i915_reg.h #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) _MMIO 6967 drivers/gpu/drm/i915/i915_reg.h #define PCH_3DCGDIS0 _MMIO(0x46020) _MMIO 6971 drivers/gpu/drm/i915/i915_reg.h #define PCH_3DCGDIS1 _MMIO(0x46024) _MMIO 6974 drivers/gpu/drm/i915/i915_reg.h #define FDI_PLL_FREQ_CTL _MMIO(0x46030) _MMIO 7186 drivers/gpu/drm/i915/i915_reg.h #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) _MMIO 7191 drivers/gpu/drm/i915/i915_reg.h #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) _MMIO 7195 drivers/gpu/drm/i915/i915_reg.h #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) _MMIO 7210 drivers/gpu/drm/i915/i915_reg.h #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) _MMIO 7213 drivers/gpu/drm/i915/i915_reg.h #define CSR_SSP_BASE _MMIO(0x8F074) _MMIO 7214 drivers/gpu/drm/i915/i915_reg.h #define CSR_HTP_SKL _MMIO(0x8F004) _MMIO 7215 drivers/gpu/drm/i915/i915_reg.h #define CSR_LAST_WRITE _MMIO(0x8F034) _MMIO 7220 drivers/gpu/drm/i915/i915_reg.h #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) _MMIO 7221 drivers/gpu/drm/i915/i915_reg.h #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) _MMIO 7222 drivers/gpu/drm/i915/i915_reg.h #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) _MMIO 7223 drivers/gpu/drm/i915/i915_reg.h #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) _MMIO 7224 drivers/gpu/drm/i915/i915_reg.h #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) _MMIO 7227 drivers/gpu/drm/i915/i915_reg.h #define RM_TIMEOUT _MMIO(0x42060) _MMIO 7282 drivers/gpu/drm/i915/i915_reg.h #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ _MMIO 7285 drivers/gpu/drm/i915/i915_reg.h #define DEISR _MMIO(0x44000) _MMIO 7286 drivers/gpu/drm/i915/i915_reg.h #define DEIMR _MMIO(0x44004) _MMIO 7287 drivers/gpu/drm/i915/i915_reg.h #define DEIIR _MMIO(0x44008) _MMIO 7288 drivers/gpu/drm/i915/i915_reg.h #define DEIER _MMIO(0x4400c) _MMIO 7290 drivers/gpu/drm/i915/i915_reg.h #define GTISR _MMIO(0x44010) _MMIO 7291 drivers/gpu/drm/i915/i915_reg.h #define GTIMR _MMIO(0x44014) _MMIO 7292 drivers/gpu/drm/i915/i915_reg.h #define GTIIR _MMIO(0x44018) _MMIO 7293 drivers/gpu/drm/i915/i915_reg.h #define GTIER _MMIO(0x4401c) _MMIO 7295 drivers/gpu/drm/i915/i915_reg.h #define GEN8_MASTER_IRQ _MMIO(0x44200) _MMIO 7313 drivers/gpu/drm/i915/i915_reg.h #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) _MMIO 7314 drivers/gpu/drm/i915/i915_reg.h #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) _MMIO 7315 drivers/gpu/drm/i915/i915_reg.h #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) _MMIO 7316 drivers/gpu/drm/i915/i915_reg.h #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) _MMIO 7325 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) _MMIO 7326 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) _MMIO 7327 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) _MMIO 7328 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) _MMIO 7361 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_PORT_ISR _MMIO(0x44440) _MMIO 7362 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_PORT_IMR _MMIO(0x44444) _MMIO 7363 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_PORT_IIR _MMIO(0x44448) _MMIO 7364 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_PORT_IER _MMIO(0x4444c) _MMIO 7383 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_MISC_ISR _MMIO(0x44460) _MMIO 7384 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_MISC_IMR _MMIO(0x44464) _MMIO 7385 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_MISC_IIR _MMIO(0x44468) _MMIO 7386 drivers/gpu/drm/i915/i915_reg.h #define GEN8_DE_MISC_IER _MMIO(0x4446c) _MMIO 7390 drivers/gpu/drm/i915/i915_reg.h #define GEN8_PCU_ISR _MMIO(0x444e0) _MMIO 7391 drivers/gpu/drm/i915/i915_reg.h #define GEN8_PCU_IMR _MMIO(0x444e4) _MMIO 7392 drivers/gpu/drm/i915/i915_reg.h #define GEN8_PCU_IIR _MMIO(0x444e8) _MMIO 7393 drivers/gpu/drm/i915/i915_reg.h #define GEN8_PCU_IER _MMIO(0x444ec) _MMIO 7395 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GU_MISC_ISR _MMIO(0x444f0) _MMIO 7396 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GU_MISC_IMR _MMIO(0x444f4) _MMIO 7397 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GU_MISC_IIR _MMIO(0x444f8) _MMIO 7398 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GU_MISC_IER _MMIO(0x444fc) _MMIO 7401 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) _MMIO 7410 drivers/gpu/drm/i915/i915_reg.h #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) _MMIO 7421 drivers/gpu/drm/i915/i915_reg.h #define GEN11_DE_HPD_ISR _MMIO(0x44470) _MMIO 7422 drivers/gpu/drm/i915/i915_reg.h #define GEN11_DE_HPD_IMR _MMIO(0x44474) _MMIO 7423 drivers/gpu/drm/i915/i915_reg.h #define GEN11_DE_HPD_IIR _MMIO(0x44478) _MMIO 7424 drivers/gpu/drm/i915/i915_reg.h #define GEN11_DE_HPD_IER _MMIO(0x4447c) _MMIO 7452 drivers/gpu/drm/i915/i915_reg.h #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) _MMIO 7453 drivers/gpu/drm/i915/i915_reg.h #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) _MMIO 7459 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GT_INTR_DW0 _MMIO(0x190018) _MMIO 7469 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GT_INTR_DW1 _MMIO(0x19001c) _MMIO 7473 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) _MMIO 7475 drivers/gpu/drm/i915/i915_reg.h #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060) _MMIO 7476 drivers/gpu/drm/i915/i915_reg.h #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064) _MMIO 7485 drivers/gpu/drm/i915/i915_reg.h #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) _MMIO 7487 drivers/gpu/drm/i915/i915_reg.h #define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070) _MMIO 7488 drivers/gpu/drm/i915/i915_reg.h #define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074) _MMIO 7490 drivers/gpu/drm/i915/i915_reg.h #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4)) _MMIO 7492 drivers/gpu/drm/i915/i915_reg.h #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030) _MMIO 7493 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034) _MMIO 7494 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038) _MMIO 7495 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c) _MMIO 7496 drivers/gpu/drm/i915/i915_reg.h #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040) _MMIO 7497 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044) _MMIO 7499 drivers/gpu/drm/i915/i915_reg.h #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090) _MMIO 7500 drivers/gpu/drm/i915/i915_reg.h #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0) _MMIO 7501 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8) _MMIO 7502 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac) _MMIO 7503 drivers/gpu/drm/i915/i915_reg.h #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0) _MMIO 7504 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8) _MMIO 7505 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) _MMIO 7506 drivers/gpu/drm/i915/i915_reg.h #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) _MMIO 7507 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) _MMIO 7512 drivers/gpu/drm/i915/i915_reg.h #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) _MMIO 7517 drivers/gpu/drm/i915/i915_reg.h #define FUSE_STRAP _MMIO(0x42014) _MMIO 7528 drivers/gpu/drm/i915/i915_reg.h #define FUSE_STRAP3 _MMIO(0x42020) _MMIO 7531 drivers/gpu/drm/i915/i915_reg.h #define ILK_DSPCLK_GATE_D _MMIO(0x42020) _MMIO 7538 drivers/gpu/drm/i915/i915_reg.h #define IVB_CHICKEN3 _MMIO(0x4200c) _MMIO 7542 drivers/gpu/drm/i915/i915_reg.h #define CHICKEN_PAR1_1 _MMIO(0x42080) _MMIO 7548 drivers/gpu/drm/i915/i915_reg.h #define CHICKEN_PAR2_1 _MMIO(0x42090) _MMIO 7551 drivers/gpu/drm/i915/i915_reg.h #define CHICKEN_MISC_2 _MMIO(0x42084) _MMIO 7557 drivers/gpu/drm/i915/i915_reg.h #define CHICKEN_MISC_4 _MMIO(0x4208c) _MMIO 7567 drivers/gpu/drm/i915/i915_reg.h #define CHICKEN_TRANS_A _MMIO(0x420c0) _MMIO 7568 drivers/gpu/drm/i915/i915_reg.h #define CHICKEN_TRANS_B _MMIO(0x420c4) _MMIO 7569 drivers/gpu/drm/i915/i915_reg.h #define CHICKEN_TRANS_C _MMIO(0x420c8) _MMIO 7570 drivers/gpu/drm/i915/i915_reg.h #define CHICKEN_TRANS_EDP _MMIO(0x420cc) _MMIO 7579 drivers/gpu/drm/i915/i915_reg.h #define DISP_ARB_CTL _MMIO(0x45000) _MMIO 7583 drivers/gpu/drm/i915/i915_reg.h #define DISP_ARB_CTL2 _MMIO(0x45004) _MMIO 7586 drivers/gpu/drm/i915/i915_reg.h #define DBUF_CTL _MMIO(0x45008) _MMIO 7587 drivers/gpu/drm/i915/i915_reg.h #define DBUF_CTL_S1 _MMIO(0x45008) _MMIO 7588 drivers/gpu/drm/i915/i915_reg.h #define DBUF_CTL_S2 _MMIO(0x44FE8) _MMIO 7591 drivers/gpu/drm/i915/i915_reg.h #define GEN7_MSG_CTL _MMIO(0x45010) _MMIO 7594 drivers/gpu/drm/i915/i915_reg.h #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) _MMIO 7597 drivers/gpu/drm/i915/i915_reg.h #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) _MMIO 7602 drivers/gpu/drm/i915/i915_reg.h #define SKL_DFSM _MMIO(0x51000) _MMIO 7613 drivers/gpu/drm/i915/i915_reg.h #define SKL_DSSM _MMIO(0x51004) _MMIO 7620 drivers/gpu/drm/i915/i915_reg.h #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) _MMIO 7623 drivers/gpu/drm/i915/i915_reg.h #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) _MMIO 7627 drivers/gpu/drm/i915/i915_reg.h #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) _MMIO 7628 drivers/gpu/drm/i915/i915_reg.h #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) _MMIO 7629 drivers/gpu/drm/i915/i915_reg.h #define GEN8_CS_CHICKEN1 _MMIO(0x2580) _MMIO 7638 drivers/gpu/drm/i915/i915_reg.h #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) _MMIO 7642 drivers/gpu/drm/i915/i915_reg.h #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) _MMIO 7648 drivers/gpu/drm/i915/i915_reg.h #define GEN8_L3CNTLREG _MMIO(0x7034) _MMIO 7651 drivers/gpu/drm/i915/i915_reg.h #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) _MMIO 7654 drivers/gpu/drm/i915/i915_reg.h #define HIZ_CHICKEN _MMIO(0x7018) _MMIO 7658 drivers/gpu/drm/i915/i915_reg.h #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) _MMIO 7661 drivers/gpu/drm/i915/i915_reg.h #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) _MMIO 7664 drivers/gpu/drm/i915/i915_reg.h #define GEN7_SARCHKMD _MMIO(0xB000) _MMIO 7668 drivers/gpu/drm/i915/i915_reg.h #define GEN7_L3SQCREG1 _MMIO(0xB010) _MMIO 7671 drivers/gpu/drm/i915/i915_reg.h #define GEN8_L3SQCREG1 _MMIO(0xB100) _MMIO 7682 drivers/gpu/drm/i915/i915_reg.h #define GEN7_L3CNTLREG1 _MMIO(0xB01C) _MMIO 7685 drivers/gpu/drm/i915/i915_reg.h #define GEN7_L3CNTLREG2 _MMIO(0xB020) _MMIO 7686 drivers/gpu/drm/i915/i915_reg.h #define GEN7_L3CNTLREG3 _MMIO(0xB024) _MMIO 7688 drivers/gpu/drm/i915/i915_reg.h #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030) _MMIO 7690 drivers/gpu/drm/i915/i915_reg.h #define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114) _MMIO 7693 drivers/gpu/drm/i915/i915_reg.h #define GEN7_L3SQCREG4 _MMIO(0xb034) _MMIO 7696 drivers/gpu/drm/i915/i915_reg.h #define GEN11_SCRATCH2 _MMIO(0xb140) _MMIO 7699 drivers/gpu/drm/i915/i915_reg.h #define GEN8_L3SQCREG4 _MMIO(0xb118) _MMIO 7705 drivers/gpu/drm/i915/i915_reg.h #define HDC_CHICKEN0 _MMIO(0x7300) _MMIO 7706 drivers/gpu/drm/i915/i915_reg.h #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) _MMIO 7707 drivers/gpu/drm/i915/i915_reg.h #define ICL_HDC_MODE _MMIO(0xE5F4) _MMIO 7715 drivers/gpu/drm/i915/i915_reg.h #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) _MMIO 7718 drivers/gpu/drm/i915/i915_reg.h #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) _MMIO 7721 drivers/gpu/drm/i915/i915_reg.h #define GEN9_WM_CHICKEN3 _MMIO(0x5588) _MMIO 7725 drivers/gpu/drm/i915/i915_reg.h #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) _MMIO 7728 drivers/gpu/drm/i915/i915_reg.h #define HSW_SCRATCH1 _MMIO(0xb038) _MMIO 7731 drivers/gpu/drm/i915/i915_reg.h #define BDW_SCRATCH1 _MMIO(0xb11c) _MMIO 7861 drivers/gpu/drm/i915/i915_reg.h #define SDEISR _MMIO(0xc4000) _MMIO 7862 drivers/gpu/drm/i915/i915_reg.h #define SDEIMR _MMIO(0xc4004) _MMIO 7863 drivers/gpu/drm/i915/i915_reg.h #define SDEIIR _MMIO(0xc4008) _MMIO 7864 drivers/gpu/drm/i915/i915_reg.h #define SDEIER _MMIO(0xc400c) _MMIO 7866 drivers/gpu/drm/i915/i915_reg.h #define SERR_INT _MMIO(0xc4040) _MMIO 7871 drivers/gpu/drm/i915/i915_reg.h #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ _MMIO 7914 drivers/gpu/drm/i915/i915_reg.h #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ _MMIO 7926 drivers/gpu/drm/i915/i915_reg.h #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) _MMIO 7947 drivers/gpu/drm/i915/i915_reg.h #define SHOTPLUG_CTL_TC _MMIO(0xc4034) _MMIO 7950 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) _MMIO 7951 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) _MMIO 7952 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) _MMIO 7953 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) _MMIO 7978 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) _MMIO 7979 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) _MMIO 7980 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) _MMIO 7981 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) _MMIO 8003 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) _MMIO 8004 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) _MMIO 8005 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) _MMIO 8006 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) _MMIO 8028 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) _MMIO 8029 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) _MMIO 8030 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) _MMIO 8031 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) _MMIO 8070 drivers/gpu/drm/i915/i915_reg.h #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) _MMIO 8077 drivers/gpu/drm/i915/i915_reg.h #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) _MMIO 8078 drivers/gpu/drm/i915/i915_reg.h #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) _MMIO 8080 drivers/gpu/drm/i915/i915_reg.h #define PCH_DPLL_TEST _MMIO(0xc606c) _MMIO 8082 drivers/gpu/drm/i915/i915_reg.h #define PCH_DREF_CONTROL _MMIO(0xC6200) _MMIO 8105 drivers/gpu/drm/i915/i915_reg.h #define PCH_RAWCLK_FREQ _MMIO(0xc6204) _MMIO 8117 drivers/gpu/drm/i915/i915_reg.h #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) _MMIO 8119 drivers/gpu/drm/i915/i915_reg.h #define PCH_SSC4_PARMS _MMIO(0xc6210) _MMIO 8120 drivers/gpu/drm/i915/i915_reg.h #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) _MMIO 8122 drivers/gpu/drm/i915/i915_reg.h #define PCH_DPLL_SEL _MMIO(0xc7000) _MMIO 8325 drivers/gpu/drm/i915/i915_reg.h #define SOUTH_CHICKEN1 _MMIO(0xc2000) _MMIO 8334 drivers/gpu/drm/i915/i915_reg.h #define SOUTH_CHICKEN2 _MMIO(0xc2004) _MMIO 8346 drivers/gpu/drm/i915/i915_reg.h #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) _MMIO 8472 drivers/gpu/drm/i915/i915_reg.h #define FDI_PLL_CTL_1 _MMIO(0xfe000) _MMIO 8473 drivers/gpu/drm/i915/i915_reg.h #define FDI_PLL_CTL_2 _MMIO(0xfe004) _MMIO 8475 drivers/gpu/drm/i915/i915_reg.h #define PCH_LVDS _MMIO(0xe1180) _MMIO 8479 drivers/gpu/drm/i915/i915_reg.h #define PCH_DP_B _MMIO(_PCH_DP_B) _MMIO 8488 drivers/gpu/drm/i915/i915_reg.h #define PCH_DP_C _MMIO(_PCH_DP_C) _MMIO 8497 drivers/gpu/drm/i915/i915_reg.h #define PCH_DP_D _MMIO(_PCH_DP_D) _MMIO 8506 drivers/gpu/drm/i915/i915_reg.h #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ _MMIO 8562 drivers/gpu/drm/i915/i915_reg.h #define VLV_PMWGICZ _MMIO(0x1300a4) _MMIO 8564 drivers/gpu/drm/i915/i915_reg.h #define RC6_LOCATION _MMIO(0xD40) _MMIO 8566 drivers/gpu/drm/i915/i915_reg.h #define RC6_CTX_BASE _MMIO(0xD48) _MMIO 8568 drivers/gpu/drm/i915/i915_reg.h #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) _MMIO 8569 drivers/gpu/drm/i915/i915_reg.h #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) _MMIO 8570 drivers/gpu/drm/i915/i915_reg.h #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) _MMIO 8571 drivers/gpu/drm/i915/i915_reg.h #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) _MMIO 8572 drivers/gpu/drm/i915/i915_reg.h #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) _MMIO 8574 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE _MMIO(0xA18C) _MMIO 8575 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_VLV _MMIO(0x1300b0) _MMIO 8576 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) _MMIO 8577 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) _MMIO 8578 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) _MMIO 8579 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_ACK_HSW _MMIO(0x130044) _MMIO 8580 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_ACK _MMIO(0x130090) _MMIO 8581 drivers/gpu/drm/i915/i915_reg.h #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) _MMIO 8586 drivers/gpu/drm/i915/i915_reg.h #define VLV_GTLC_PW_STATUS _MMIO(0x130094) _MMIO 8591 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ _MMIO 8592 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) _MMIO 8593 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) _MMIO 8594 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) _MMIO 8595 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) _MMIO 8596 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) _MMIO 8597 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) _MMIO 8598 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4) _MMIO 8599 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4) _MMIO 8600 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) _MMIO 8601 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) _MMIO 8605 drivers/gpu/drm/i915/i915_reg.h #define FORCEWAKE_MT_ACK _MMIO(0x130040) _MMIO 8606 drivers/gpu/drm/i915/i915_reg.h #define ECOBUS _MMIO(0xa180) _MMIO 8608 drivers/gpu/drm/i915/i915_reg.h #define VLV_SPAREG2H _MMIO(0xA194) _MMIO 8609 drivers/gpu/drm/i915/i915_reg.h #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0) _MMIO 8613 drivers/gpu/drm/i915/i915_reg.h #define GTFIFODBG _MMIO(0x120000) _MMIO 8624 drivers/gpu/drm/i915/i915_reg.h #define GTFIFOCTL _MMIO(0x120008) _MMIO 8630 drivers/gpu/drm/i915/i915_reg.h #define HSW_IDICR _MMIO(0x9008) _MMIO 8632 drivers/gpu/drm/i915/i915_reg.h #define HSW_EDRAM_CAP _MMIO(0x120010) _MMIO 8638 drivers/gpu/drm/i915/i915_reg.h #define GEN6_UCGCTL1 _MMIO(0x9400) _MMIO 8644 drivers/gpu/drm/i915/i915_reg.h #define GEN6_UCGCTL2 _MMIO(0x9404) _MMIO 8652 drivers/gpu/drm/i915/i915_reg.h #define GEN6_UCGCTL3 _MMIO(0x9408) _MMIO 8655 drivers/gpu/drm/i915/i915_reg.h #define GEN7_UCGCTL4 _MMIO(0x940c) _MMIO 8659 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RCGCTL1 _MMIO(0x9410) _MMIO 8660 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RCGCTL2 _MMIO(0x9414) _MMIO 8661 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RSTCTL _MMIO(0x9420) _MMIO 8663 drivers/gpu/drm/i915/i915_reg.h #define GEN8_UCGCTL6 _MMIO(0x9430) _MMIO 8668 drivers/gpu/drm/i915/i915_reg.h #define GEN6_GFXPAUSE _MMIO(0xA000) _MMIO 8669 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RPNSWREQ _MMIO(0xA008) _MMIO 8676 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) _MMIO 8677 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC_CONTROL _MMIO(0xA090) _MMIO 8687 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010) _MMIO 8688 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014) _MMIO 8689 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RPSTAT1 _MMIO(0xA01C) _MMIO 8696 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_CONTROL _MMIO(0xA024) _MMIO 8710 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) _MMIO 8711 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) _MMIO 8712 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_CUR_UP_EI _MMIO(0xA050) _MMIO 8715 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_CUR_UP _MMIO(0xA054) _MMIO 8717 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_PREV_UP _MMIO(0xA058) _MMIO 8718 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C) _MMIO 8720 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_CUR_DOWN _MMIO(0xA060) _MMIO 8721 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_PREV_DOWN _MMIO(0xA064) _MMIO 8722 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_UP_EI _MMIO(0xA068) _MMIO 8723 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_DOWN_EI _MMIO(0xA06C) _MMIO 8724 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) _MMIO 8725 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RPDEUHWTC _MMIO(0xA080) _MMIO 8726 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RPDEUC _MMIO(0xA084) _MMIO 8727 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RPDEUCSW _MMIO(0xA088) _MMIO 8728 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC_STATE _MMIO(0xA094) _MMIO 8731 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) _MMIO 8732 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) _MMIO 8733 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) _MMIO 8734 drivers/gpu/drm/i915/i915_reg.h #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0) _MMIO 8735 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) _MMIO 8736 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) _MMIO 8737 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC_SLEEP _MMIO(0xA0B0) _MMIO 8738 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RCUBMABDTMR _MMIO(0xA0B0) _MMIO 8739 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4) _MMIO 8740 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8) _MMIO 8741 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC) _MMIO 8742 drivers/gpu/drm/i915/i915_reg.h #define VLV_RCEDATA _MMIO(0xA0BC) _MMIO 8743 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) _MMIO 8744 drivers/gpu/drm/i915/i915_reg.h #define GEN6_PMINTRMSK _MMIO(0xA168) _MMIO 8747 drivers/gpu/drm/i915/i915_reg.h #define GEN8_MISC_CTRL0 _MMIO(0xA180) _MMIO 8748 drivers/gpu/drm/i915/i915_reg.h #define VLV_PWRDWNUPCTL _MMIO(0xA294) _MMIO 8749 drivers/gpu/drm/i915/i915_reg.h #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) _MMIO 8750 drivers/gpu/drm/i915/i915_reg.h #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) _MMIO 8751 drivers/gpu/drm/i915/i915_reg.h #define GEN9_PG_ENABLE _MMIO(0xA210) _MMIO 8755 drivers/gpu/drm/i915/i915_reg.h #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248) _MMIO 8756 drivers/gpu/drm/i915/i915_reg.h #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250) _MMIO 8757 drivers/gpu/drm/i915/i915_reg.h #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C) _MMIO 8759 drivers/gpu/drm/i915/i915_reg.h #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) _MMIO 8763 drivers/gpu/drm/i915/i915_reg.h #define GEN6_PMISR _MMIO(0x44020) _MMIO 8764 drivers/gpu/drm/i915/i915_reg.h #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ _MMIO 8765 drivers/gpu/drm/i915/i915_reg.h #define GEN6_PMIIR _MMIO(0x44028) _MMIO 8766 drivers/gpu/drm/i915/i915_reg.h #define GEN6_PMIER _MMIO(0x4402C) _MMIO 8785 drivers/gpu/drm/i915/i915_reg.h #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4) _MMIO 8788 drivers/gpu/drm/i915/i915_reg.h #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) _MMIO 8792 drivers/gpu/drm/i915/i915_reg.h #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) _MMIO 8793 drivers/gpu/drm/i915/i915_reg.h #define VLV_COUNTER_CONTROL _MMIO(0x138104) _MMIO 8799 drivers/gpu/drm/i915/i915_reg.h #define GEN6_GT_GFX_RC6 _MMIO(0x138108) _MMIO 8800 drivers/gpu/drm/i915/i915_reg.h #define VLV_GT_RENDER_RC6 _MMIO(0x138108) _MMIO 8801 drivers/gpu/drm/i915/i915_reg.h #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C) _MMIO 8803 drivers/gpu/drm/i915/i915_reg.h #define GEN6_GT_GFX_RC6p _MMIO(0x13810C) _MMIO 8804 drivers/gpu/drm/i915/i915_reg.h #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) _MMIO 8805 drivers/gpu/drm/i915/i915_reg.h #define VLV_RENDER_C0_COUNT _MMIO(0x138118) _MMIO 8806 drivers/gpu/drm/i915/i915_reg.h #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) _MMIO 8808 drivers/gpu/drm/i915/i915_reg.h #define GEN6_PCODE_MAILBOX _MMIO(0x138124) _MMIO 8850 drivers/gpu/drm/i915/i915_reg.h #define GEN6_PCODE_DATA _MMIO(0x138128) _MMIO 8853 drivers/gpu/drm/i915/i915_reg.h #define GEN6_PCODE_DATA1 _MMIO(0x13812C) _MMIO 8855 drivers/gpu/drm/i915/i915_reg.h #define GEN6_GT_CORE_STATUS _MMIO(0x138060) _MMIO 8863 drivers/gpu/drm/i915/i915_reg.h #define GEN8_GT_SLICE_INFO _MMIO(0x138064) _MMIO 8866 drivers/gpu/drm/i915/i915_reg.h #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) _MMIO 8867 drivers/gpu/drm/i915/i915_reg.h #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) _MMIO 8873 drivers/gpu/drm/i915/i915_reg.h #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) _MMIO 8874 drivers/gpu/drm/i915/i915_reg.h #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) _MMIO 8877 drivers/gpu/drm/i915/i915_reg.h #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) _MMIO 8878 drivers/gpu/drm/i915/i915_reg.h #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ _MMIO 8884 drivers/gpu/drm/i915/i915_reg.h #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) _MMIO 8885 drivers/gpu/drm/i915/i915_reg.h #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ _MMIO 8887 drivers/gpu/drm/i915/i915_reg.h #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) _MMIO 8888 drivers/gpu/drm/i915/i915_reg.h #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ _MMIO 8899 drivers/gpu/drm/i915/i915_reg.h #define GEN7_MISCCPCTL _MMIO(0x9424) _MMIO 8905 drivers/gpu/drm/i915/i915_reg.h #define GEN8_GARBCNTL _MMIO(0xB004) _MMIO 8911 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GLBLINVL _MMIO(0xB404) _MMIO 8915 drivers/gpu/drm/i915/i915_reg.h #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550) _MMIO 8918 drivers/gpu/drm/i915/i915_reg.h #define GEN11_GACB_PERF_CTRL _MMIO(0x4B80) _MMIO 8923 drivers/gpu/drm/i915/i915_reg.h #define GEN11_LSN_UNSLCVC _MMIO(0xB43C) _MMIO 8927 drivers/gpu/drm/i915/i915_reg.h #define GEN10_SAMPLER_MODE _MMIO(0xE18C) _MMIO 8931 drivers/gpu/drm/i915/i915_reg.h #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ _MMIO 8944 drivers/gpu/drm/i915/i915_reg.h #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4) _MMIO 8947 drivers/gpu/drm/i915/i915_reg.h #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ _MMIO 8948 drivers/gpu/drm/i915/i915_reg.h #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) _MMIO 8954 drivers/gpu/drm/i915/i915_reg.h #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188) _MMIO 8958 drivers/gpu/drm/i915/i915_reg.h #define GEN8_ROW_CHICKEN _MMIO(0xe4f0) _MMIO 8965 drivers/gpu/drm/i915/i915_reg.h #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) _MMIO 8966 drivers/gpu/drm/i915/i915_reg.h #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) _MMIO 8971 drivers/gpu/drm/i915/i915_reg.h #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) _MMIO 8974 drivers/gpu/drm/i915/i915_reg.h #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) _MMIO 8977 drivers/gpu/drm/i915/i915_reg.h #define HALF_SLICE_CHICKEN3 _MMIO(0xe184) _MMIO 8984 drivers/gpu/drm/i915/i915_reg.h #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) _MMIO 8990 drivers/gpu/drm/i915/i915_reg.h #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) _MMIO 8995 drivers/gpu/drm/i915/i915_reg.h #define G4X_AUD_CNTL_ST _MMIO(0x620B4) _MMIO 9000 drivers/gpu/drm/i915/i915_reg.h #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) _MMIO 9013 drivers/gpu/drm/i915/i915_reg.h #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) _MMIO 9023 drivers/gpu/drm/i915/i915_reg.h #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) _MMIO 9031 drivers/gpu/drm/i915/i915_reg.h #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) _MMIO 9037 drivers/gpu/drm/i915/i915_reg.h #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) _MMIO 9103 drivers/gpu/drm/i915/i915_reg.h #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) _MMIO 9104 drivers/gpu/drm/i915/i915_reg.h #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) _MMIO 9110 drivers/gpu/drm/i915/i915_reg.h #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) _MMIO 9128 drivers/gpu/drm/i915/i915_reg.h #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) _MMIO 9129 drivers/gpu/drm/i915/i915_reg.h #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) _MMIO 9130 drivers/gpu/drm/i915/i915_reg.h #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) _MMIO 9131 drivers/gpu/drm/i915/i915_reg.h #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) _MMIO 9161 drivers/gpu/drm/i915/i915_reg.h #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) _MMIO 9162 drivers/gpu/drm/i915/i915_reg.h #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) _MMIO 9163 drivers/gpu/drm/i915/i915_reg.h #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) _MMIO 9187 drivers/gpu/drm/i915/i915_reg.h #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) _MMIO 9188 drivers/gpu/drm/i915/i915_reg.h #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) _MMIO 9189 drivers/gpu/drm/i915/i915_reg.h #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) _MMIO 9204 drivers/gpu/drm/i915/i915_reg.h #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) _MMIO 9208 drivers/gpu/drm/i915/i915_reg.h #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) _MMIO 9219 drivers/gpu/drm/i915/i915_reg.h #define SKL_FUSE_STATUS _MMIO(0x42000) _MMIO 9240 drivers/gpu/drm/i915/i915_reg.h #define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \ _MMIO 9252 drivers/gpu/drm/i915/i915_reg.h #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ _MMIO 9260 drivers/gpu/drm/i915/i915_reg.h #define HDCP_KEY_CONF _MMIO(0x66c00) _MMIO 9264 drivers/gpu/drm/i915/i915_reg.h #define HDCP_KEY_STATUS _MMIO(0x66c04) _MMIO 9270 drivers/gpu/drm/i915/i915_reg.h #define HDCP_AKSV_LO _MMIO(0x66c10) _MMIO 9271 drivers/gpu/drm/i915/i915_reg.h #define HDCP_AKSV_HI _MMIO(0x66c14) _MMIO 9274 drivers/gpu/drm/i915/i915_reg.h #define HDCP_REP_CTL _MMIO(0x66d00) _MMIO 9297 drivers/gpu/drm/i915/i915_reg.h #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04) _MMIO 9298 drivers/gpu/drm/i915/i915_reg.h #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08) _MMIO 9299 drivers/gpu/drm/i915/i915_reg.h #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C) _MMIO 9300 drivers/gpu/drm/i915/i915_reg.h #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10) _MMIO 9301 drivers/gpu/drm/i915/i915_reg.h #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14) _MMIO 9302 drivers/gpu/drm/i915/i915_reg.h #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4)) _MMIO 9303 drivers/gpu/drm/i915/i915_reg.h #define HDCP_SHA_TEXT _MMIO(0x66d18) _MMIO 9312 drivers/gpu/drm/i915/i915_reg.h #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \ _MMIO 9348 drivers/gpu/drm/i915/i915_reg.h #define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \ _MMIO 9486 drivers/gpu/drm/i915/i915_reg.h #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) _MMIO 9488 drivers/gpu/drm/i915/i915_reg.h #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) _MMIO 9493 drivers/gpu/drm/i915/i915_reg.h #define SBI_ADDR _MMIO(0xC6000) _MMIO 9494 drivers/gpu/drm/i915/i915_reg.h #define SBI_DATA _MMIO(0xC6004) _MMIO 9495 drivers/gpu/drm/i915/i915_reg.h #define SBI_CTL_STAT _MMIO(0xC6008) _MMIO 9532 drivers/gpu/drm/i915/i915_reg.h #define PIXCLK_GATE _MMIO(0xC6020) _MMIO 9537 drivers/gpu/drm/i915/i915_reg.h #define SPLL_CTL _MMIO(0x46020) _MMIO 9606 drivers/gpu/drm/i915/i915_reg.h #define CDCLK_FREQ _MMIO(0x46200) _MMIO 9626 drivers/gpu/drm/i915/i915_reg.h #define LCPLL_CTL _MMIO(0x130040) _MMIO 9650 drivers/gpu/drm/i915/i915_reg.h #define CDCLK_CTL _MMIO(0x46000) _MMIO 9669 drivers/gpu/drm/i915/i915_reg.h #define LCPLL1_CTL _MMIO(0x46010) _MMIO 9670 drivers/gpu/drm/i915/i915_reg.h #define LCPLL2_CTL _MMIO(0x46014) _MMIO 9674 drivers/gpu/drm/i915/i915_reg.h #define DPLL_CTRL1 _MMIO(0x6C058) _MMIO 9689 drivers/gpu/drm/i915/i915_reg.h #define DPLL_CTRL2 _MMIO(0x6C05C) _MMIO 9697 drivers/gpu/drm/i915/i915_reg.h #define DPLL_STATUS _MMIO(0x6C060) _MMIO 9735 drivers/gpu/drm/i915/i915_reg.h #define DPCLKA_CFGCR0 _MMIO(0x6C200) _MMIO 9743 drivers/gpu/drm/i915/i915_reg.h #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) _MMIO 9761 drivers/gpu/drm/i915/i915_reg.h #define TBT_PLL_ENABLE _MMIO(0x46020) _MMIO 9986 drivers/gpu/drm/i915/i915_reg.h #define BXT_DE_PLL_CTL _MMIO(0x6d000) _MMIO 9990 drivers/gpu/drm/i915/i915_reg.h #define BXT_DE_PLL_ENABLE _MMIO(0x46070) _MMIO 9997 drivers/gpu/drm/i915/i915_reg.h #define DC_STATE_EN _MMIO(0x45504) _MMIO 10004 drivers/gpu/drm/i915/i915_reg.h #define DC_STATE_DEBUG _MMIO(0x45520) _MMIO 10008 drivers/gpu/drm/i915/i915_reg.h #define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114) _MMIO 10018 drivers/gpu/drm/i915/i915_reg.h #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \ _MMIO 10045 drivers/gpu/drm/i915/i915_reg.h #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04) _MMIO 10048 drivers/gpu/drm/i915/i915_reg.h #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000) _MMIO 10055 drivers/gpu/drm/i915/i915_reg.h #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) _MMIO 10056 drivers/gpu/drm/i915/i915_reg.h #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) _MMIO 10084 drivers/gpu/drm/i915/i915_reg.h #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) _MMIO 10085 drivers/gpu/drm/i915/i915_reg.h #define D_COMP_BDW _MMIO(0x138144) _MMIO 10100 drivers/gpu/drm/i915/i915_reg.h #define SFUSE_STRAP _MMIO(0xc2014) _MMIO 10110 drivers/gpu/drm/i915/i915_reg.h #define WM_MISC _MMIO(0x45260) _MMIO 10113 drivers/gpu/drm/i915/i915_reg.h #define WM_DBG _MMIO(0x45280) _MMIO 10256 drivers/gpu/drm/i915/i915_reg.h #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) _MMIO 10257 drivers/gpu/drm/i915/i915_reg.h #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) _MMIO 10258 drivers/gpu/drm/i915/i915_reg.h #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) _MMIO 10314 drivers/gpu/drm/i915/i915_reg.h #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) _MMIO 10315 drivers/gpu/drm/i915/i915_reg.h #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) _MMIO 10321 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) _MMIO 10327 drivers/gpu/drm/i915/i915_reg.h #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) _MMIO 10329 drivers/gpu/drm/i915/i915_reg.h #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) _MMIO 10349 drivers/gpu/drm/i915/i915_reg.h #define GEN4_TIMESTAMP _MMIO(0x2358) _MMIO 10350 drivers/gpu/drm/i915/i915_reg.h #define ILK_TIMESTAMP_HI _MMIO(0x70070) _MMIO 10351 drivers/gpu/drm/i915/i915_reg.h #define IVB_TIMESTAMP_CTR _MMIO(0x44070) _MMIO 10353 drivers/gpu/drm/i915/i915_reg.h #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) _MMIO 10366 drivers/gpu/drm/i915/i915_reg.h #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) _MMIO 10445 drivers/gpu/drm/i915/i915_reg.h #define BXT_DSI_PLL_CTL _MMIO(0x161000) _MMIO 10469 drivers/gpu/drm/i915/i915_reg.h #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) _MMIO 10491 drivers/gpu/drm/i915/i915_reg.h #define DSS_CTL1 _MMIO(0x67400) _MMIO 10502 drivers/gpu/drm/i915/i915_reg.h #define DSS_CTL2 _MMIO(0x67404) _MMIO 10523 drivers/gpu/drm/i915/i915_reg.h #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) _MMIO 10526 drivers/gpu/drm/i915/i915_reg.h #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) _MMIO 11194 drivers/gpu/drm/i915/i915_reg.h #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ _MMIO 11202 drivers/gpu/drm/i915/i915_reg.h #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ _MMIO 11204 drivers/gpu/drm/i915/i915_reg.h #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */ _MMIO 11205 drivers/gpu/drm/i915/i915_reg.h #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */ _MMIO 11206 drivers/gpu/drm/i915/i915_reg.h #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */ _MMIO 11207 drivers/gpu/drm/i915/i915_reg.h #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */ _MMIO 11208 drivers/gpu/drm/i915/i915_reg.h #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */ _MMIO 11210 drivers/gpu/drm/i915/i915_reg.h #define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4) _MMIO 11212 drivers/gpu/drm/i915/i915_reg.h #define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0) _MMIO 11217 drivers/gpu/drm/i915/i915_reg.h #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ _MMIO 11220 drivers/gpu/drm/i915/i915_reg.h #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) _MMIO 11226 drivers/gpu/drm/i915/i915_reg.h #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */ _MMIO 11238 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) _MMIO 11239 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) _MMIO 11259 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) _MMIO 11260 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) _MMIO 11273 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) _MMIO 11274 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) _MMIO 11288 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) _MMIO 11289 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) _MMIO 11303 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) _MMIO 11304 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) _MMIO 11318 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) _MMIO 11319 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) _MMIO 11333 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) _MMIO 11334 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) _MMIO 11350 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) _MMIO 11351 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) _MMIO 11365 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) _MMIO 11366 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) _MMIO 11380 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) _MMIO 11381 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) _MMIO 11395 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) _MMIO 11396 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) _MMIO 11412 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) _MMIO 11413 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) _MMIO 11425 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) _MMIO 11426 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) _MMIO 11438 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) _MMIO 11439 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) _MMIO 11451 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) _MMIO 11452 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) _MMIO 11464 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) _MMIO 11465 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) _MMIO 11477 drivers/gpu/drm/i915/i915_reg.h #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) _MMIO 11478 drivers/gpu/drm/i915/i915_reg.h #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) _MMIO 11494 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) _MMIO 11495 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) _MMIO 11496 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) _MMIO 11497 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) _MMIO 11519 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) _MMIO 11520 drivers/gpu/drm/i915/i915_reg.h #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) _MMIO 11521 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) _MMIO 11522 drivers/gpu/drm/i915/i915_reg.h #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) _MMIO 446 drivers/gpu/drm/i915/intel_csr.c csr->mmioaddr[i] = _MMIO(mmioaddr[i]); _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2744), 0x00800000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2710), 0x00000000 }, _MMIO 19 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2724), 0xf0800000 }, _MMIO 20 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2720), 0x00000000 }, _MMIO 21 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2770), 0x00000004 }, _MMIO 22 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2774), 0x00000000 }, _MMIO 23 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2778), 0x00000003 }, _MMIO 24 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x277c), 0x00000000 }, _MMIO 25 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2780), 0x00000007 }, _MMIO 26 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2784), 0x00000000 }, _MMIO 27 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2788), 0x00100002 }, _MMIO 28 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x278c), 0x0000fff7 }, _MMIO 29 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2790), 0x00100002 }, _MMIO 30 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2794), 0x0000ffcf }, _MMIO 31 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x2798), 0x00100082 }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x279c), 0x0000ffef }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x27a0), 0x001000c2 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x27a4), 0x0000ffe7 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 36 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9840), 0x000000a0 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x198b0000 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x078b0066 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x118b0000 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x258b0000 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x21850008 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x0d834000 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x07844000 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x17804000 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x21800000 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x4f800000 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x41800000 }, _MMIO 55 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9888), 0x31800000 }, _MMIO 56 drivers/gpu/drm/i915/oa/i915_oa_bdw.c { _MMIO(0x9840), 0x00000080 }, _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2744), 0x00800000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2710), 0x00000000 }, _MMIO 19 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2724), 0xf0800000 }, _MMIO 20 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2720), 0x00000000 }, _MMIO 21 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2770), 0x00000004 }, _MMIO 22 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2774), 0x00000000 }, _MMIO 23 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2778), 0x00000003 }, _MMIO 24 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x277c), 0x00000000 }, _MMIO 25 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2780), 0x00000007 }, _MMIO 26 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2784), 0x00000000 }, _MMIO 27 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2788), 0x00100002 }, _MMIO 28 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x278c), 0x0000fff7 }, _MMIO 29 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2790), 0x00100002 }, _MMIO 30 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2794), 0x0000ffcf }, _MMIO 31 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x2798), 0x00100082 }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x279c), 0x0000ffef }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x27a0), 0x001000c2 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x27a4), 0x0000ffe7 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 36 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9840), 0x00000080 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9888), 0x19800000 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9888), 0x07800063 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9888), 0x11800000 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9888), 0x23810008 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9888), 0x1d950400 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9888), 0x0f922000 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9888), 0x1f908000 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9888), 0x37900000 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9888), 0x55900000 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9888), 0x47900000 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_bxt.c { _MMIO(0x9888), 0x33900000 }, _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c { _MMIO(0x2744), 0x00800000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c { _MMIO(0x2710), 0x00000000 }, _MMIO 19 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c { _MMIO(0x2724), 0xf0800000 }, _MMIO 20 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c { _MMIO(0x2720), 0x00000000 }, _MMIO 21 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c { _MMIO(0x2770), 0x00000004 }, _MMIO 22 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drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 36 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9840), 0x00000080 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x11810000 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x07810013 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x1f810000 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x1d810000 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x1b930040 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x07e54000 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x1f908000 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x11900000 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x37900000 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x53900000 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x45900000 }, _MMIO 55 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c { _MMIO(0x9888), 0x33900000 }, _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2744), 0x00800000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2710), 0x00000000 }, _MMIO 19 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2724), 0xf0800000 }, _MMIO 20 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2720), 0x00000000 }, _MMIO 21 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2770), 0x00000004 }, _MMIO 22 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2774), 0x00000000 }, _MMIO 23 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2778), 0x00000003 }, _MMIO 24 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x277c), 0x00000000 }, _MMIO 25 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2780), 0x00000007 }, _MMIO 26 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2784), 0x00000000 }, _MMIO 27 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2788), 0x00100002 }, _MMIO 28 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x278c), 0x0000fff7 }, _MMIO 29 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2790), 0x00100002 }, _MMIO 30 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2794), 0x0000ffcf }, _MMIO 31 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x2798), 0x00100082 }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x279c), 0x0000ffef }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x27a0), 0x001000c2 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x27a4), 0x0000ffe7 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 36 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9840), 0x000000a0 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9888), 0x59800000 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9888), 0x59800001 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9888), 0x338b0000 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9888), 0x258b0066 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9888), 0x058b0000 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9888), 0x038b0000 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9888), 0x03844000 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9888), 0x47800080 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9888), 0x57800000 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x1823a4), 0x00000000 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9888), 0x59800000 }, _MMIO 55 drivers/gpu/drm/i915/oa/i915_oa_chv.c { _MMIO(0x9840), 0x00000080 }, _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2710), 0x00000000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2720), 0x00000000 }, _MMIO 19 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2724), 0xf0800000 }, _MMIO 20 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2770), 0x00000004 }, _MMIO 21 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2774), 0x0000ffff }, _MMIO 22 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2778), 0x00000003 }, _MMIO 23 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x277c), 0x0000ffff }, _MMIO 24 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2780), 0x00000007 }, _MMIO 25 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2784), 0x0000ffff }, _MMIO 26 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2788), 0x00100002 }, _MMIO 27 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x278c), 0x0000fff7 }, _MMIO 28 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2790), 0x00100002 }, _MMIO 29 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2794), 0x0000ffcf }, _MMIO 30 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x2798), 0x00100082 }, _MMIO 31 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x279c), 0x0000ffef }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x27a0), 0x001000c2 }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x27a4), 0x0000ffe7 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 42 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0xd04), 0x00000200 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x17060000 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9840), 0x00000000 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x13034000 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x07060066 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x05060000 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x0f080040 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 55 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x07091000 }, _MMIO 56 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 57 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x0f041000 }, _MMIO 58 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 59 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x1d004000 }, _MMIO 60 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 61 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x35000000 }, _MMIO 62 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 63 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x49000000 }, _MMIO 64 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 65 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x3d000000 }, _MMIO 66 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9884), 0x00000007 }, _MMIO 67 drivers/gpu/drm/i915/oa/i915_oa_cnl.c { _MMIO(0x9888), 0x31000000 }, _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x2744), 0x00800000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x2710), 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_MMIO(0x2798), 0x00100082 }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x279c), 0x0000ffef }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x27a0), 0x001000c2 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x27a4), 0x0000ffe7 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 36 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x9840), 0x00000080 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x9888), 0x19800000 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x9888), 0x07800063 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x9888), 0x11800000 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x9888), 0x23810008 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x9888), 0x1d950400 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_glk.c { _MMIO(0x9888), 0x0f922000 }, _MMIO 50 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0x00000000 }, _MMIO 29 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x2691c), 0x00000800 }, _MMIO 30 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26aa0), 0x01500000 }, _MMIO 31 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26b9c), 0x00006000 }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x2791c), 0x00000800 }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27aa0), 0x01500000 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27b9c), 0x00006000 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x2641c), 0x00000400 }, _MMIO 36 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x25380), 0x00000010 }, _MMIO 37 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x2538c), 0x00000000 }, _MMIO 38 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x25384), 0x0800aaaa }, _MMIO 39 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x25400), 0x00000004 }, _MMIO 40 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x2540c), 0x06029000 }, _MMIO 41 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x25410), 0x00000002 }, _MMIO 42 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x25404), 0x5c30ffff }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x25100), 0x00000016 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x25110), 0x00000400 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x25104), 0x00000000 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26804), 0x00001211 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26884), 0x00000100 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26900), 0x00000002 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26908), 0x00700000 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26904), 0x00000000 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26984), 0x00001022 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26a04), 0x00000011 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26a80), 0x00000006 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26a88), 0x00000c02 }, _MMIO 55 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26a84), 0x00000000 }, _MMIO 56 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26b04), 0x00001000 }, _MMIO 57 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26b80), 0x00000002 }, _MMIO 58 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26b8c), 0x00000007 }, _MMIO 59 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26b84), 0x00000000 }, _MMIO 60 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27804), 0x00004844 }, _MMIO 61 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27884), 0x00000400 }, _MMIO 62 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27900), 0x00000002 }, _MMIO 63 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27908), 0x0e000000 }, _MMIO 64 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27904), 0x00000000 }, _MMIO 65 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27984), 0x00004088 }, _MMIO 66 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27a04), 0x00000044 }, _MMIO 67 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27a80), 0x00000006 }, _MMIO 68 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27a88), 0x00018040 }, _MMIO 69 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27a84), 0x00000000 }, _MMIO 70 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27b04), 0x00004000 }, _MMIO 71 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27b80), 0x00000002 }, _MMIO 72 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27b8c), 0x000000e0 }, _MMIO 73 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x27b84), 0x00000000 }, _MMIO 74 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26104), 0x00002222 }, _MMIO 75 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26184), 0x0c006666 }, _MMIO 76 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26284), 0x04000000 }, _MMIO 77 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26304), 0x04000000 }, _MMIO 78 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26400), 0x00000002 }, _MMIO 79 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26410), 0x000000a0 }, _MMIO 80 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x26404), 0x00000000 }, _MMIO 81 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x25420), 0x04108020 }, _MMIO 82 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x25424), 0x1284a420 }, _MMIO 83 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x2541c), 0x00000000 }, _MMIO 84 drivers/gpu/drm/i915/oa/i915_oa_hsw.c { _MMIO(0x25428), 0x00042049 }, _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2710), 0x00000000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2720), 0x00000000 }, _MMIO 19 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2724), 0xf0800000 }, _MMIO 20 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2770), 0x00000004 }, _MMIO 21 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2774), 0x0000ffff }, _MMIO 22 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2778), 0x00000003 }, _MMIO 23 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x277c), 0x0000ffff }, _MMIO 24 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2780), 0x00000007 }, _MMIO 25 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2784), 0x0000ffff }, _MMIO 26 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2788), 0x00100002 }, _MMIO 27 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x278c), 0x0000fff7 }, _MMIO 28 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2790), 0x00100002 }, _MMIO 29 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2794), 0x0000ffcf }, _MMIO 30 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x2798), 0x00100082 }, _MMIO 31 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x279c), 0x0000ffef }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x27a0), 0x001000c2 }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x27a4), 0x0000ffe7 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 42 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0xd04), 0x00000200 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9840), 0x00000000 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9884), 0x00000000 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x10060000 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x22060000 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x16060000 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x24060000 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x18060000 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x1a060000 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x12060000 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x14060000 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x10060000 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x22060000 }, _MMIO 55 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9884), 0x00000003 }, _MMIO 56 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x16130000 }, _MMIO 57 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x24000001 }, _MMIO 58 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x0e130056 }, _MMIO 59 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x10130000 }, _MMIO 60 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x1a130000 }, _MMIO 61 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x541f0001 }, _MMIO 62 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x181f0000 }, _MMIO 63 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x4c1f0000 }, _MMIO 64 drivers/gpu/drm/i915/oa/i915_oa_icl.c { _MMIO(0x9888), 0x301f0000 }, _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2744), 0x00800000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2710), 0x00000000 }, _MMIO 19 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2724), 0xf0800000 }, _MMIO 20 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2720), 0x00000000 }, _MMIO 21 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2770), 0x00000004 }, _MMIO 22 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2774), 0x00000000 }, _MMIO 23 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2778), 0x00000003 }, _MMIO 24 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x277c), 0x00000000 }, _MMIO 25 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2780), 0x00000007 }, _MMIO 26 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2784), 0x00000000 }, _MMIO 27 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2788), 0x00100002 }, _MMIO 28 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x278c), 0x0000fff7 }, _MMIO 29 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2790), 0x00100002 }, _MMIO 30 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2794), 0x0000ffcf }, _MMIO 31 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x2798), 0x00100082 }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x279c), 0x0000ffef }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x27a0), 0x001000c2 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x27a4), 0x0000ffe7 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 36 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9840), 0x00000080 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x11810000 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x07810013 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x1f810000 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x1d810000 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x1b930040 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x07e54000 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x1f908000 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x11900000 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x37900000 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x53900000 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x45900000 }, _MMIO 55 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c { _MMIO(0x9888), 0x33900000 }, _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2744), 0x00800000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2710), 0x00000000 }, _MMIO 19 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2724), 0xf0800000 }, _MMIO 20 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2720), 0x00000000 }, _MMIO 21 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2770), 0x00000004 }, _MMIO 22 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2774), 0x00000000 }, _MMIO 23 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2778), 0x00000003 }, _MMIO 24 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x277c), 0x00000000 }, _MMIO 25 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2780), 0x00000007 }, _MMIO 26 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2784), 0x00000000 }, _MMIO 27 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2788), 0x00100002 }, _MMIO 28 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x278c), 0x0000fff7 }, _MMIO 29 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2790), 0x00100002 }, _MMIO 30 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2794), 0x0000ffcf }, _MMIO 31 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x2798), 0x00100082 }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x279c), 0x0000ffef }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x27a0), 0x001000c2 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x27a4), 0x0000ffe7 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 36 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9840), 0x00000080 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x11810000 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x07810013 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x1f810000 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x1d810000 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x1b930040 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x07e54000 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x1f908000 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x11900000 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x37900000 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x53900000 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x45900000 }, _MMIO 55 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c { _MMIO(0x9888), 0x33900000 }, _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2710), 0x00000000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2724), 0xf0800000 }, _MMIO 19 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2720), 0x00000000 }, _MMIO 20 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2770), 0x00000004 }, _MMIO 21 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2774), 0x00000000 }, _MMIO 22 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2778), 0x00000003 }, _MMIO 23 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x277c), 0x00000000 }, _MMIO 24 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2780), 0x00000007 }, _MMIO 25 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2784), 0x00000000 }, _MMIO 26 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2788), 0x00100002 }, _MMIO 27 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x278c), 0x0000fff7 }, _MMIO 28 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2790), 0x00100002 }, _MMIO 29 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2794), 0x0000ffcf }, _MMIO 30 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x2798), 0x00100082 }, _MMIO 31 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x279c), 0x0000ffef }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x27a0), 0x001000c2 }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x27a4), 0x0000ffe7 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 42 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9840), 0x00000080 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x11810000 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x07810016 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x1f810000 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x1d810000 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x1b930040 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x07e54000 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x1f908000 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x11900000 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x37900000 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x53900000 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x45900000 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c { _MMIO(0x9888), 0x33900000 }, _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2744), 0x00800000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2710), 0x00000000 }, _MMIO 19 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2724), 0xf0800000 }, _MMIO 20 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2720), 0x00000000 }, _MMIO 21 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2770), 0x00000004 }, _MMIO 22 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2774), 0x00000000 }, _MMIO 23 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2778), 0x00000003 }, _MMIO 24 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x277c), 0x00000000 }, _MMIO 25 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2780), 0x00000007 }, _MMIO 26 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2784), 0x00000000 }, _MMIO 27 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2788), 0x00100002 }, _MMIO 28 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x278c), 0x0000fff7 }, _MMIO 29 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2790), 0x00100002 }, _MMIO 30 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2794), 0x0000ffcf }, _MMIO 31 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x2798), 0x00100082 }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x279c), 0x0000ffef }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x27a0), 0x001000c2 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x27a4), 0x0000ffe7 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 36 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9840), 0x00000080 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x11810000 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x07810013 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x1f810000 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x1d810000 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x1b930040 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x07e54000 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x1f908000 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x11900000 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x37900000 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x53900000 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x45900000 }, _MMIO 55 drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c { _MMIO(0x9888), 0x33900000 }, _MMIO 15 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2740), 0x00000000 }, _MMIO 16 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2744), 0x00800000 }, _MMIO 17 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2714), 0xf0800000 }, _MMIO 18 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2710), 0x00000000 }, _MMIO 19 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2724), 0xf0800000 }, _MMIO 20 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2720), 0x00000000 }, _MMIO 21 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2770), 0x00000004 }, _MMIO 22 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2774), 0x00000000 }, _MMIO 23 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2778), 0x00000003 }, _MMIO 24 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x277c), 0x00000000 }, _MMIO 25 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2780), 0x00000007 }, _MMIO 26 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2784), 0x00000000 }, _MMIO 27 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2788), 0x00100002 }, _MMIO 28 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x278c), 0x0000fff7 }, _MMIO 29 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2790), 0x00100002 }, _MMIO 30 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2794), 0x0000ffcf }, _MMIO 31 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x2798), 0x00100082 }, _MMIO 32 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x279c), 0x0000ffef }, _MMIO 33 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x27a0), 0x001000c2 }, _MMIO 34 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x27a4), 0x0000ffe7 }, _MMIO 35 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x27a8), 0x00100001 }, _MMIO 36 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x27ac), 0x0000ffe7 }, _MMIO 43 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9840), 0x00000080 }, _MMIO 44 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x11810000 }, _MMIO 45 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x07810013 }, _MMIO 46 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x1f810000 }, _MMIO 47 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x1d810000 }, _MMIO 48 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x1b930040 }, _MMIO 49 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x07e54000 }, _MMIO 50 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x1f908000 }, _MMIO 51 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x11900000 }, _MMIO 52 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x37900000 }, _MMIO 53 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x53900000 }, _MMIO 54 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x45900000 }, _MMIO 55 drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c { _MMIO(0x9888), 0x33900000 }, _MMIO 190 drivers/gpu/drm/i915/selftests/intel_uncore.c i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);