_MASKED_BIT_ENABLE  866 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
_MASKED_BIT_ENABLE 2328 drivers/gpu/drm/i915/gt/intel_lrc.c 		mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
_MASKED_BIT_ENABLE 2330 drivers/gpu/drm/i915/gt/intel_lrc.c 		mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
_MASKED_BIT_ENABLE 3212 drivers/gpu/drm/i915/gt/intel_lrc.c 		_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
_MASKED_BIT_ENABLE 3336 drivers/gpu/drm/i915/gt/intel_lrc.c 			_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
_MASKED_BIT_ENABLE  470 drivers/gpu/drm/i915/gt/intel_reset.c 	intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
_MASKED_BIT_ENABLE  583 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		     _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
_MASKED_BIT_ENABLE  607 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			     RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING));
_MASKED_BIT_ENABLE  867 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			   _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE));
_MASKED_BIT_ENABLE  871 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
_MASKED_BIT_ENABLE  880 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
_MASKED_BIT_ENABLE  886 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
_MASKED_BIT_ENABLE  891 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
_MASKED_BIT_ENABLE  892 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
_MASKED_BIT_ENABLE  905 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
_MASKED_BIT_ENABLE 1620 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 				*cs++ = _MASKED_BIT_ENABLE(
_MASKED_BIT_ENABLE 2020 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			      _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
_MASKED_BIT_ENABLE  165 drivers/gpu/drm/i915/gt/intel_workarounds.c 	wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val));
_MASKED_BIT_ENABLE  181 drivers/gpu/drm/i915/gt/intel_workarounds.c 	wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
_MASKED_BIT_ENABLE  555 drivers/gpu/drm/i915/gt/intel_workarounds.c 			   _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
_MASKED_BIT_ENABLE  885 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | \
_MASKED_BIT_ENABLE 1016 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
_MASKED_BIT_ENABLE  473 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 			      _MASKED_BIT_ENABLE(dma_flags | START_DMA));
_MASKED_BIT_ENABLE 1698 drivers/gpu/drm/i915/gvt/handlers.c 	(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
_MASKED_BIT_ENABLE 1700 drivers/gpu/drm/i915/gvt/handlers.c 		(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
_MASKED_BIT_ENABLE 1703 drivers/gpu/drm/i915/gvt/handlers.c 	if (data & _MASKED_BIT_ENABLE(1)) {
_MASKED_BIT_ENABLE 1709 drivers/gpu/drm/i915/gvt/handlers.c 	    data & _MASKED_BIT_ENABLE(2)) {
_MASKED_BIT_ENABLE 1718 drivers/gpu/drm/i915/gvt/handlers.c 	if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
_MASKED_BIT_ENABLE 1719 drivers/gpu/drm/i915/gvt/handlers.c 			(data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
_MASKED_BIT_ENABLE 1724 drivers/gpu/drm/i915/gvt/handlers.c 	if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
_MASKED_BIT_ENABLE 1786 drivers/gpu/drm/i915/gvt/handlers.c 	if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
_MASKED_BIT_ENABLE 1801 drivers/gpu/drm/i915/gvt/handlers.c 	(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
_MASKED_BIT_ENABLE 1804 drivers/gpu/drm/i915/gvt/handlers.c 	if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8))
_MASKED_BIT_ENABLE 2746 drivers/gpu/drm/i915/gvt/handlers.c 		~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
_MASKED_BIT_ENABLE  460 drivers/gpu/drm/i915/gvt/mmio_context.c 		_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
_MASKED_BIT_ENABLE   57 drivers/gpu/drm/i915/gvt/mmio_context.h 	(_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) == \
_MASKED_BIT_ENABLE   58 drivers/gpu/drm/i915/gvt/mmio_context.h 	((a) & _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)))
_MASKED_BIT_ENABLE  877 drivers/gpu/drm/i915/i915_gem_fence_reg.c 				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
_MASKED_BIT_ENABLE  881 drivers/gpu/drm/i915/i915_gem_fence_reg.c 				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
_MASKED_BIT_ENABLE  885 drivers/gpu/drm/i915/i915_gem_fence_reg.c 				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
_MASKED_BIT_ENABLE 1574 drivers/gpu/drm/i915/i915_gem_gtt.c 			     _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
_MASKED_BIT_ENABLE 1600 drivers/gpu/drm/i915/i915_gem_gtt.c 				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
_MASKED_BIT_ENABLE 1976 drivers/gpu/drm/i915/i915_perf.c 			   _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
_MASKED_BIT_ENABLE 3205 drivers/gpu/drm/i915/i915_perf.c 		val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
_MASKED_BIT_ENABLE 3212 drivers/gpu/drm/i915/i915_perf.c 		val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
_MASKED_BIT_ENABLE  394 drivers/gpu/drm/i915/intel_pm.c 		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
_MASKED_BIT_ENABLE  405 drivers/gpu/drm/i915/intel_pm.c 		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
_MASKED_BIT_ENABLE 7930 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
_MASKED_BIT_ENABLE 8021 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
_MASKED_BIT_ENABLE 8967 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
_MASKED_BIT_ENABLE 9035 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
_MASKED_BIT_ENABLE 9078 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
_MASKED_BIT_ENABLE 9086 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
_MASKED_BIT_ENABLE 9196 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
_MASKED_BIT_ENABLE 9227 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
_MASKED_BIT_ENABLE 9324 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
_MASKED_BIT_ENABLE 9353 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
_MASKED_BIT_ENABLE 9373 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
_MASKED_BIT_ENABLE 9388 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
_MASKED_BIT_ENABLE 9404 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
_MASKED_BIT_ENABLE 9414 drivers/gpu/drm/i915/intel_pm.c 			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
_MASKED_BIT_ENABLE 9430 drivers/gpu/drm/i915/intel_pm.c 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
_MASKED_BIT_ENABLE 9434 drivers/gpu/drm/i915/intel_pm.c 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
_MASKED_BIT_ENABLE 9436 drivers/gpu/drm/i915/intel_pm.c 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
_MASKED_BIT_ENABLE 9467 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
_MASKED_BIT_ENABLE 9495 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
_MASKED_BIT_ENABLE 9505 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
_MASKED_BIT_ENABLE 9517 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
_MASKED_BIT_ENABLE 9544 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
_MASKED_BIT_ENABLE 9581 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
_MASKED_BIT_ENABLE 9617 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
_MASKED_BIT_ENABLE 9636 drivers/gpu/drm/i915/intel_pm.c 			   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
_MASKED_BIT_ENABLE 9653 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
_MASKED_BIT_ENABLE 9668 drivers/gpu/drm/i915/intel_pm.c 		I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
_MASKED_BIT_ENABLE 9674 drivers/gpu/drm/i915/intel_pm.c 	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
_MASKED_BIT_ENABLE 9677 drivers/gpu/drm/i915/intel_pm.c 	I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
_MASKED_BIT_ENABLE 9680 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
_MASKED_BIT_ENABLE 9688 drivers/gpu/drm/i915/intel_pm.c 	I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
_MASKED_BIT_ENABLE 9692 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
_MASKED_BIT_ENABLE 9698 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
_MASKED_BIT_ENABLE 9699 drivers/gpu/drm/i915/intel_pm.c 		   _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
_MASKED_BIT_ENABLE 9953 drivers/gpu/drm/i915/intel_pm.c 		      _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
_MASKED_BIT_ENABLE 9963 drivers/gpu/drm/i915/intel_pm.c 			      _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
_MASKED_BIT_ENABLE   89 drivers/gpu/drm/i915/intel_uncore.c #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)